diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51.atsln b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51.atsln
new file mode 100644
index 0000000..b6441c5
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51.atsln
@@ -0,0 +1,22 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "Two_Motor_D51", "Two_Motor_D51\Two_Motor_D51.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
+EndProject
+Global
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution
+ Debug|ARM = Debug|ARM
+ Release|ARM = Release|ARM
+ EndGlobalSection
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution
+ {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
+ {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
+ {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
+ {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
+ EndGlobalSection
+ GlobalSection(SolutionProperties) = preSolution
+ HideSolutionNode = FALSE
+ EndGlobalSection
+EndGlobal
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.env_conf b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.env_conf
new file mode 100644
index 0000000..d052f3a
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.env_conf
@@ -0,0 +1,6 @@
+
+
+
+
+
+
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.gpdsc b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.gpdsc
new file mode 100644
index 0000000..4f2fef4
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.gpdsc
@@ -0,0 +1,251 @@
+
+ Atmel
+ Two_Motor_D51
+ Project generated by Atmel Start
+ http://start.atmel.com/
+
+ Initial version
+
+
+ Configuration Files generated by Atmel Start
+
+
+
+ Atmel Start
+
+ http://start.atmel.com/
+
+
+
+
+
+
+
+
+ Dependency on CMSIS core and Device Startup components
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Atmel Start Framework
+ #define ATMEL_START
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/atmel_start_config.atstart b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/atmel_start_config.atstart
new file mode 100644
index 0000000..89c10b1
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/atmel_start_config.atstart
@@ -0,0 +1,2712 @@
+format_version: '2'
+name: Two_Motor_D51
+versions:
+ api: '1.0'
+ backend: 1.8.580
+ commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c
+ content: unknown
+ content_pack_name: unknown
+ format: '2'
+ frontend: 1.8.580
+ packs_version_avr8: 1.0.1463
+ packs_version_qtouch: unknown
+ packs_version_sam: 1.0.1726
+ version_backend: 1.8.580
+ version_frontend: ''
+board:
+ identifier: CustomBoard
+ device: SAMD51J18A-MF
+details: null
+application: null
+middlewares: {}
+drivers:
+ ADC_0:
+ user_label: ADC_0
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync
+ functionality: ADC
+ api: HAL:Driver:ADC_Sync
+ configuration:
+ adc_advanced_settings: false
+ adc_arch_adjres: 0
+ adc_arch_corren: false
+ adc_arch_dbgrun: false
+ adc_arch_event_settings: false
+ adc_arch_flushei: false
+ adc_arch_flushinv: false
+ adc_arch_gaincorr: 0
+ adc_arch_leftadj: false
+ adc_arch_offcomp: false
+ adc_arch_offsetcorr: 0
+ adc_arch_ondemand: false
+ adc_arch_refcomp: false
+ adc_arch_resrdyeo: false
+ adc_arch_runstdby: false
+ adc_arch_samplen: 0
+ adc_arch_samplenum: 1 sample
+ adc_arch_seqen: 0
+ adc_arch_startei: false
+ adc_arch_startinv: false
+ adc_arch_winlt: 0
+ adc_arch_winmode: No window mode
+ adc_arch_winmoneo: false
+ adc_arch_winut: 0
+ adc_differential_mode: false
+ adc_freerunning_mode: false
+ adc_pinmux_negative: ADC AIN0 pin
+ adc_pinmux_positive: ADC AIN0 pin
+ adc_prescaler: Peripheral clock divided by 2
+ adc_reference: Internal bandgap reference
+ adc_resolution: 12-bit
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: ADC
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ adc_gclk_selection: Generic clock generator 0
+ ADC_1:
+ user_label: ADC_1
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::ADC1::driver_config_definition::ADC::HAL:Driver:ADC.Sync
+ functionality: ADC
+ api: HAL:Driver:ADC_Sync
+ configuration:
+ adc_advanced_settings: true
+ adc_arch_adjres: 0
+ adc_arch_corren: false
+ adc_arch_dbgrun: false
+ adc_arch_event_settings: true
+ adc_arch_flushei: false
+ adc_arch_flushinv: false
+ adc_arch_gaincorr: 0
+ adc_arch_leftadj: false
+ adc_arch_offcomp: false
+ adc_arch_offsetcorr: 0
+ adc_arch_ondemand: false
+ adc_arch_refcomp: false
+ adc_arch_resrdyeo: true
+ adc_arch_runstdby: false
+ adc_arch_samplen: 2
+ adc_arch_samplenum: 1 sample
+ adc_arch_seqen: 0
+ adc_arch_startei: false
+ adc_arch_startinv: false
+ adc_arch_winlt: 0
+ adc_arch_winmode: No window mode
+ adc_arch_winmoneo: false
+ adc_arch_winut: 0
+ adc_differential_mode: true
+ adc_freerunning_mode: false
+ adc_pinmux_negative: ADC AIN0 pin
+ adc_pinmux_positive: ADC AIN6 pin
+ adc_prescaler: Peripheral clock divided by 8
+ adc_reference: External reference A
+ adc_resolution: 12-bit
+ optional_signals:
+ - identifier: ADC_1:AIN/0
+ pad: PB08
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.0
+ name: ADC1/AIN/0
+ label: AIN/0
+ - identifier: ADC_1:AIN/6
+ pad: PB04
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.6
+ name: ADC1/AIN/6
+ label: AIN/6
+ - identifier: ADC_1:AIN/7
+ pad: PB05
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.7
+ name: ADC1/AIN/7
+ label: AIN/7
+ - identifier: ADC_1:AIN/8
+ pad: PB06
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.8
+ name: ADC1/AIN/8
+ label: AIN/8
+ - identifier: ADC_1:AIN/9
+ pad: PB07
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.9
+ name: ADC1/AIN/9
+ label: AIN/9
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: ADC
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ adc_gclk_selection: Generic clock generator 0
+ DIGITAL_GLUE_LOGIC_0:
+ user_label: DIGITAL_GLUE_LOGIC_0
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::CCL::driver_config_definition::CCL::HAL:Driver:CCL
+ functionality: Digital_Glue_Logic
+ api: HAL:Driver:CCL
+ configuration:
+ ccl_arch_advanced_settings: false
+ ccl_arch_edgesel_0: false
+ ccl_arch_edgesel_1: false
+ ccl_arch_edgesel_2: false
+ ccl_arch_edgesel_3: false
+ ccl_arch_filtsel_0: Disabled
+ ccl_arch_filtsel_1: Disabled
+ ccl_arch_filtsel_2: Disabled
+ ccl_arch_filtsel_3: Disabled
+ ccl_arch_insel0_0: IO pin input source
+ ccl_arch_insel0_1: IO pin input source
+ ccl_arch_insel0_2: IO pin input source
+ ccl_arch_insel0_3: IO pin input source
+ ccl_arch_insel1_0: IO pin input source
+ ccl_arch_insel1_1: IO pin input source
+ ccl_arch_insel1_2: IO pin input source
+ ccl_arch_insel1_3: IO pin input source
+ ccl_arch_insel2_0: IO pin input source
+ ccl_arch_insel2_1: IO pin input source
+ ccl_arch_insel2_2: IO pin input source
+ ccl_arch_insel2_3: IO pin input source
+ ccl_arch_invei_0: false
+ ccl_arch_invei_1: false
+ ccl_arch_invei_2: false
+ ccl_arch_invei_3: false
+ ccl_arch_lutctrl0: true
+ ccl_arch_lutctrl1: false
+ ccl_arch_lutctrl2: true
+ ccl_arch_lutctrl3: false
+ ccl_arch_lutei_0: false
+ ccl_arch_lutei_1: false
+ ccl_arch_lutei_2: false
+ ccl_arch_lutei_3: false
+ ccl_arch_luteo_0: true
+ ccl_arch_luteo_1: false
+ ccl_arch_luteo_2: true
+ ccl_arch_luteo_3: false
+ ccl_arch_runstdby: false
+ ccl_arch_seqsel_0: Sequential logic is disabled
+ ccl_arch_seqsel_1: Sequential logic is disabled
+ ccl_arch_truth_0: 150
+ ccl_arch_truth_1: 0
+ ccl_arch_truth_2: 150
+ ccl_arch_truth_3: 0
+ ccl_e_persistance_0: ''
+ ccl_e_persistance_1: ''
+ ccl_e_persistance_2: ''
+ ccl_e_persistance_3: ''
+ ccl_l_persistance_0: ''
+ ccl_l_persistance_1: ''
+ ccl_l_persistance_2: ''
+ ccl_l_persistance_3: ''
+ optional_signals:
+ - identifier: DIGITAL_GLUE_LOGIC_0:IN/0
+ pad: PA04
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.0
+ name: CCL/IN/0
+ label: IN/0
+ - identifier: DIGITAL_GLUE_LOGIC_0:IN/1
+ pad: PA05
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.1
+ name: CCL/IN/1
+ label: IN/1
+ - identifier: DIGITAL_GLUE_LOGIC_0:IN/2
+ pad: PA06
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.2
+ name: CCL/IN/2
+ label: IN/2
+ - identifier: DIGITAL_GLUE_LOGIC_0:IN/6
+ pad: PA22
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.6
+ name: CCL/IN/6
+ label: IN/6
+ - identifier: DIGITAL_GLUE_LOGIC_0:IN/7
+ pad: PA23
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.7
+ name: CCL/IN/7
+ label: IN/7
+ - identifier: DIGITAL_GLUE_LOGIC_0:IN/8
+ pad: PA24
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.8
+ name: CCL/IN/8
+ label: IN/8
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: CCL
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ ccl_gclk_selection: Generic clock generator 0
+ CMCC:
+ user_label: CMCC
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC
+ functionality: System
+ api: HAL:HPL:CMCC
+ configuration:
+ cache_size: 4 KB
+ cmcc_advanced_configuration: false
+ cmcc_clock_gating_disable: false
+ cmcc_data_cache_disable: false
+ cmcc_enable: false
+ cmcc_inst_cache_disable: false
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ DMAC:
+ user_label: DMAC
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
+ functionality: System
+ api: HAL:HPL:DMAC
+ configuration:
+ dmac_beatsize_0: 32-bit bus transfer
+ dmac_beatsize_1: 32-bit bus transfer
+ dmac_beatsize_10: 8-bit bus transfer
+ dmac_beatsize_11: 8-bit bus transfer
+ dmac_beatsize_12: 8-bit bus transfer
+ dmac_beatsize_13: 8-bit bus transfer
+ dmac_beatsize_14: 8-bit bus transfer
+ dmac_beatsize_15: 8-bit bus transfer
+ dmac_beatsize_16: 8-bit bus transfer
+ dmac_beatsize_17: 8-bit bus transfer
+ dmac_beatsize_18: 8-bit bus transfer
+ dmac_beatsize_19: 8-bit bus transfer
+ dmac_beatsize_2: 32-bit bus transfer
+ dmac_beatsize_20: 8-bit bus transfer
+ dmac_beatsize_21: 8-bit bus transfer
+ dmac_beatsize_22: 8-bit bus transfer
+ dmac_beatsize_23: 8-bit bus transfer
+ dmac_beatsize_24: 8-bit bus transfer
+ dmac_beatsize_25: 8-bit bus transfer
+ dmac_beatsize_26: 8-bit bus transfer
+ dmac_beatsize_27: 8-bit bus transfer
+ dmac_beatsize_28: 8-bit bus transfer
+ dmac_beatsize_29: 8-bit bus transfer
+ dmac_beatsize_3: 16-bit bus transfer
+ dmac_beatsize_30: 8-bit bus transfer
+ dmac_beatsize_31: 8-bit bus transfer
+ dmac_beatsize_4: 32-bit bus transfer
+ dmac_beatsize_5: 32-bit bus transfer
+ dmac_beatsize_6: 32-bit bus transfer
+ dmac_beatsize_7: 32-bit bus transfer
+ dmac_beatsize_8: 8-bit bus transfer
+ dmac_beatsize_9: 8-bit bus transfer
+ dmac_blockact_0: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_1: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_10: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_11: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_12: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_13: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_14: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_15: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_16: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_17: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_18: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_19: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_2: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_20: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_21: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_22: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_23: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_24: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_25: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_26: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_27: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_28: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_29: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_3: Channel will be disabled if it is the last block transfer in
+ the transaction and block interrupt
+ dmac_blockact_30: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_31: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_4: Channel suspend operation is complete
+ dmac_blockact_5: Channel suspend operation is complete
+ dmac_blockact_6: Channel suspend operation is complete
+ dmac_blockact_7: Channel suspend operation is complete
+ dmac_blockact_8: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_9: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_channel_0_settings: true
+ dmac_channel_10_settings: false
+ dmac_channel_11_settings: false
+ dmac_channel_12_settings: false
+ dmac_channel_13_settings: false
+ dmac_channel_14_settings: false
+ dmac_channel_15_settings: false
+ dmac_channel_16_settings: false
+ dmac_channel_17_settings: false
+ dmac_channel_18_settings: false
+ dmac_channel_19_settings: false
+ dmac_channel_1_settings: true
+ dmac_channel_20_settings: false
+ dmac_channel_21_settings: false
+ dmac_channel_22_settings: false
+ dmac_channel_23_settings: false
+ dmac_channel_24_settings: false
+ dmac_channel_25_settings: false
+ dmac_channel_26_settings: false
+ dmac_channel_27_settings: false
+ dmac_channel_28_settings: false
+ dmac_channel_29_settings: false
+ dmac_channel_2_settings: true
+ dmac_channel_30_settings: false
+ dmac_channel_31_settings: false
+ dmac_channel_3_settings: true
+ dmac_channel_4_settings: true
+ dmac_channel_5_settings: true
+ dmac_channel_6_settings: true
+ dmac_channel_7_settings: true
+ dmac_channel_8_settings: false
+ dmac_channel_9_settings: false
+ dmac_dbgrun: false
+ dmac_dstinc_0: true
+ dmac_dstinc_1: true
+ dmac_dstinc_10: false
+ dmac_dstinc_11: false
+ dmac_dstinc_12: false
+ dmac_dstinc_13: false
+ dmac_dstinc_14: false
+ dmac_dstinc_15: false
+ dmac_dstinc_16: false
+ dmac_dstinc_17: false
+ dmac_dstinc_18: false
+ dmac_dstinc_19: false
+ dmac_dstinc_2: true
+ dmac_dstinc_20: false
+ dmac_dstinc_21: false
+ dmac_dstinc_22: false
+ dmac_dstinc_23: false
+ dmac_dstinc_24: false
+ dmac_dstinc_25: false
+ dmac_dstinc_26: false
+ dmac_dstinc_27: false
+ dmac_dstinc_28: false
+ dmac_dstinc_29: false
+ dmac_dstinc_3: true
+ dmac_dstinc_30: false
+ dmac_dstinc_31: false
+ dmac_dstinc_4: false
+ dmac_dstinc_5: false
+ dmac_dstinc_6: false
+ dmac_dstinc_7: false
+ dmac_dstinc_8: false
+ dmac_dstinc_9: false
+ dmac_enable: true
+ dmac_evact_0: No action
+ dmac_evact_1: No action
+ dmac_evact_10: No action
+ dmac_evact_11: No action
+ dmac_evact_12: No action
+ dmac_evact_13: No action
+ dmac_evact_14: No action
+ dmac_evact_15: No action
+ dmac_evact_16: No action
+ dmac_evact_17: No action
+ dmac_evact_18: No action
+ dmac_evact_19: No action
+ dmac_evact_2: No action
+ dmac_evact_20: No action
+ dmac_evact_21: No action
+ dmac_evact_22: No action
+ dmac_evact_23: No action
+ dmac_evact_24: No action
+ dmac_evact_25: No action
+ dmac_evact_26: No action
+ dmac_evact_27: No action
+ dmac_evact_28: No action
+ dmac_evact_29: No action
+ dmac_evact_3: No action
+ dmac_evact_30: No action
+ dmac_evact_31: No action
+ dmac_evact_4: Channel resume operation
+ dmac_evact_5: Channel resume operation
+ dmac_evact_6: Channel resume operation
+ dmac_evact_7: No action
+ dmac_evact_8: No action
+ dmac_evact_9: No action
+ dmac_evie_0: false
+ dmac_evie_1: false
+ dmac_evie_10: false
+ dmac_evie_11: false
+ dmac_evie_12: false
+ dmac_evie_13: false
+ dmac_evie_14: false
+ dmac_evie_15: false
+ dmac_evie_16: false
+ dmac_evie_17: false
+ dmac_evie_18: false
+ dmac_evie_19: false
+ dmac_evie_2: false
+ dmac_evie_20: false
+ dmac_evie_21: false
+ dmac_evie_22: false
+ dmac_evie_23: false
+ dmac_evie_24: false
+ dmac_evie_25: false
+ dmac_evie_26: false
+ dmac_evie_27: false
+ dmac_evie_28: false
+ dmac_evie_29: false
+ dmac_evie_3: false
+ dmac_evie_30: false
+ dmac_evie_31: false
+ dmac_evie_4: true
+ dmac_evie_5: true
+ dmac_evie_6: true
+ dmac_evie_7: true
+ dmac_evie_8: false
+ dmac_evie_9: false
+ dmac_evoe_0: true
+ dmac_evoe_1: true
+ dmac_evoe_10: false
+ dmac_evoe_11: false
+ dmac_evoe_12: false
+ dmac_evoe_13: false
+ dmac_evoe_14: false
+ dmac_evoe_15: false
+ dmac_evoe_16: false
+ dmac_evoe_17: false
+ dmac_evoe_18: false
+ dmac_evoe_19: false
+ dmac_evoe_2: true
+ dmac_evoe_20: false
+ dmac_evoe_21: false
+ dmac_evoe_22: false
+ dmac_evoe_23: false
+ dmac_evoe_24: false
+ dmac_evoe_25: false
+ dmac_evoe_26: false
+ dmac_evoe_27: false
+ dmac_evoe_28: false
+ dmac_evoe_29: false
+ dmac_evoe_3: false
+ dmac_evoe_30: false
+ dmac_evoe_31: false
+ dmac_evoe_4: false
+ dmac_evoe_5: false
+ dmac_evoe_6: false
+ dmac_evoe_7: false
+ dmac_evoe_8: false
+ dmac_evoe_9: false
+ dmac_evosel_0: Event strobe when block transfer complete
+ dmac_evosel_1: Event strobe when block transfer complete
+ dmac_evosel_10: Event generation disabled
+ dmac_evosel_11: Event generation disabled
+ dmac_evosel_12: Event generation disabled
+ dmac_evosel_13: Event generation disabled
+ dmac_evosel_14: Event generation disabled
+ dmac_evosel_15: Event generation disabled
+ dmac_evosel_16: Event generation disabled
+ dmac_evosel_17: Event generation disabled
+ dmac_evosel_18: Event generation disabled
+ dmac_evosel_19: Event generation disabled
+ dmac_evosel_2: Event strobe when block transfer complete
+ dmac_evosel_20: Event generation disabled
+ dmac_evosel_21: Event generation disabled
+ dmac_evosel_22: Event generation disabled
+ dmac_evosel_23: Event generation disabled
+ dmac_evosel_24: Event generation disabled
+ dmac_evosel_25: Event generation disabled
+ dmac_evosel_26: Event generation disabled
+ dmac_evosel_27: Event generation disabled
+ dmac_evosel_28: Event generation disabled
+ dmac_evosel_29: Event generation disabled
+ dmac_evosel_3: Event generation disabled
+ dmac_evosel_30: Event generation disabled
+ dmac_evosel_31: Event generation disabled
+ dmac_evosel_4: Event generation disabled
+ dmac_evosel_5: Event generation disabled
+ dmac_evosel_6: Event generation disabled
+ dmac_evosel_7: Event generation disabled
+ dmac_evosel_8: Event generation disabled
+ dmac_evosel_9: Event generation disabled
+ dmac_lvl_0: Channel priority 0
+ dmac_lvl_1: Channel priority 0
+ dmac_lvl_10: Channel priority 0
+ dmac_lvl_11: Channel priority 0
+ dmac_lvl_12: Channel priority 0
+ dmac_lvl_13: Channel priority 0
+ dmac_lvl_14: Channel priority 0
+ dmac_lvl_15: Channel priority 0
+ dmac_lvl_16: Channel priority 0
+ dmac_lvl_17: Channel priority 0
+ dmac_lvl_18: Channel priority 0
+ dmac_lvl_19: Channel priority 0
+ dmac_lvl_2: Channel priority 0
+ dmac_lvl_20: Channel priority 0
+ dmac_lvl_21: Channel priority 0
+ dmac_lvl_22: Channel priority 0
+ dmac_lvl_23: Channel priority 0
+ dmac_lvl_24: Channel priority 0
+ dmac_lvl_25: Channel priority 0
+ dmac_lvl_26: Channel priority 0
+ dmac_lvl_27: Channel priority 0
+ dmac_lvl_28: Channel priority 0
+ dmac_lvl_29: Channel priority 0
+ dmac_lvl_3: Channel priority 0
+ dmac_lvl_30: Channel priority 0
+ dmac_lvl_31: Channel priority 0
+ dmac_lvl_4: Channel priority 0
+ dmac_lvl_5: Channel priority 0
+ dmac_lvl_6: Channel priority 0
+ dmac_lvl_7: Channel priority 0
+ dmac_lvl_8: Channel priority 0
+ dmac_lvl_9: Channel priority 0
+ dmac_lvlen0: true
+ dmac_lvlen1: false
+ dmac_lvlen2: false
+ dmac_lvlen3: false
+ dmac_lvlpri0: 0
+ dmac_lvlpri1: 0
+ dmac_lvlpri2: 0
+ dmac_lvlpri3: 0
+ dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
+ dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
+ dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
+ dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
+ dmac_runstdby_0: true
+ dmac_runstdby_1: true
+ dmac_runstdby_10: false
+ dmac_runstdby_11: false
+ dmac_runstdby_12: false
+ dmac_runstdby_13: false
+ dmac_runstdby_14: false
+ dmac_runstdby_15: false
+ dmac_runstdby_16: false
+ dmac_runstdby_17: false
+ dmac_runstdby_18: false
+ dmac_runstdby_19: false
+ dmac_runstdby_2: true
+ dmac_runstdby_20: false
+ dmac_runstdby_21: false
+ dmac_runstdby_22: false
+ dmac_runstdby_23: false
+ dmac_runstdby_24: false
+ dmac_runstdby_25: false
+ dmac_runstdby_26: false
+ dmac_runstdby_27: false
+ dmac_runstdby_28: false
+ dmac_runstdby_29: false
+ dmac_runstdby_3: true
+ dmac_runstdby_30: false
+ dmac_runstdby_31: false
+ dmac_runstdby_4: true
+ dmac_runstdby_5: true
+ dmac_runstdby_6: true
+ dmac_runstdby_7: true
+ dmac_runstdby_8: false
+ dmac_runstdby_9: false
+ dmac_srcinc_0: false
+ dmac_srcinc_1: false
+ dmac_srcinc_10: false
+ dmac_srcinc_11: false
+ dmac_srcinc_12: false
+ dmac_srcinc_13: false
+ dmac_srcinc_14: false
+ dmac_srcinc_15: false
+ dmac_srcinc_16: false
+ dmac_srcinc_17: false
+ dmac_srcinc_18: false
+ dmac_srcinc_19: false
+ dmac_srcinc_2: false
+ dmac_srcinc_20: false
+ dmac_srcinc_21: false
+ dmac_srcinc_22: false
+ dmac_srcinc_23: false
+ dmac_srcinc_24: false
+ dmac_srcinc_25: false
+ dmac_srcinc_26: false
+ dmac_srcinc_27: false
+ dmac_srcinc_28: false
+ dmac_srcinc_29: false
+ dmac_srcinc_3: false
+ dmac_srcinc_30: false
+ dmac_srcinc_31: false
+ dmac_srcinc_4: true
+ dmac_srcinc_5: true
+ dmac_srcinc_6: true
+ dmac_srcinc_7: true
+ dmac_srcinc_8: false
+ dmac_srcinc_9: false
+ dmac_stepsel_0: Step size settings apply to the destination address
+ dmac_stepsel_1: Step size settings apply to the destination address
+ dmac_stepsel_10: Step size settings apply to the destination address
+ dmac_stepsel_11: Step size settings apply to the destination address
+ dmac_stepsel_12: Step size settings apply to the destination address
+ dmac_stepsel_13: Step size settings apply to the destination address
+ dmac_stepsel_14: Step size settings apply to the destination address
+ dmac_stepsel_15: Step size settings apply to the destination address
+ dmac_stepsel_16: Step size settings apply to the destination address
+ dmac_stepsel_17: Step size settings apply to the destination address
+ dmac_stepsel_18: Step size settings apply to the destination address
+ dmac_stepsel_19: Step size settings apply to the destination address
+ dmac_stepsel_2: Step size settings apply to the destination address
+ dmac_stepsel_20: Step size settings apply to the destination address
+ dmac_stepsel_21: Step size settings apply to the destination address
+ dmac_stepsel_22: Step size settings apply to the destination address
+ dmac_stepsel_23: Step size settings apply to the destination address
+ dmac_stepsel_24: Step size settings apply to the destination address
+ dmac_stepsel_25: Step size settings apply to the destination address
+ dmac_stepsel_26: Step size settings apply to the destination address
+ dmac_stepsel_27: Step size settings apply to the destination address
+ dmac_stepsel_28: Step size settings apply to the destination address
+ dmac_stepsel_29: Step size settings apply to the destination address
+ dmac_stepsel_3: Step size settings apply to the destination address
+ dmac_stepsel_30: Step size settings apply to the destination address
+ dmac_stepsel_31: Step size settings apply to the destination address
+ dmac_stepsel_4: Step size settings apply to the source address
+ dmac_stepsel_5: Step size settings apply to the source address
+ dmac_stepsel_6: Step size settings apply to the source address
+ dmac_stepsel_7: Step size settings apply to the source address
+ dmac_stepsel_8: Step size settings apply to the destination address
+ dmac_stepsel_9: Step size settings apply to the destination address
+ dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_trifsrc_0: SERCOM1 RX Trigger
+ dmac_trifsrc_1: SERCOM5 RX Trigger
+ dmac_trifsrc_10: Only software/event triggers
+ dmac_trifsrc_11: Only software/event triggers
+ dmac_trifsrc_12: Only software/event triggers
+ dmac_trifsrc_13: Only software/event triggers
+ dmac_trifsrc_14: Only software/event triggers
+ dmac_trifsrc_15: Only software/event triggers
+ dmac_trifsrc_16: Only software/event triggers
+ dmac_trifsrc_17: Only software/event triggers
+ dmac_trifsrc_18: Only software/event triggers
+ dmac_trifsrc_19: Only software/event triggers
+ dmac_trifsrc_2: SERCOM2 RX Trigger
+ dmac_trifsrc_20: Only software/event triggers
+ dmac_trifsrc_21: Only software/event triggers
+ dmac_trifsrc_22: Only software/event triggers
+ dmac_trifsrc_23: Only software/event triggers
+ dmac_trifsrc_24: Only software/event triggers
+ dmac_trifsrc_25: Only software/event triggers
+ dmac_trifsrc_26: Only software/event triggers
+ dmac_trifsrc_27: Only software/event triggers
+ dmac_trifsrc_28: Only software/event triggers
+ dmac_trifsrc_29: Only software/event triggers
+ dmac_trifsrc_3: ADC1 Result Ready Trigger
+ dmac_trifsrc_30: Only software/event triggers
+ dmac_trifsrc_31: Only software/event triggers
+ dmac_trifsrc_4: ADC1 Sequencing Trigger
+ dmac_trifsrc_5: SERCOM2 TX Trigger
+ dmac_trifsrc_6: SERCOM5 TX Trigger
+ dmac_trifsrc_7: SERCOM1 TX Trigger
+ dmac_trifsrc_8: Only software/event triggers
+ dmac_trifsrc_9: Only software/event triggers
+ dmac_trigact_0: One trigger required for each beat transfer
+ dmac_trigact_1: One trigger required for each beat transfer
+ dmac_trigact_10: One trigger required for each block transfer
+ dmac_trigact_11: One trigger required for each block transfer
+ dmac_trigact_12: One trigger required for each block transfer
+ dmac_trigact_13: One trigger required for each block transfer
+ dmac_trigact_14: One trigger required for each block transfer
+ dmac_trigact_15: One trigger required for each block transfer
+ dmac_trigact_16: One trigger required for each block transfer
+ dmac_trigact_17: One trigger required for each block transfer
+ dmac_trigact_18: One trigger required for each block transfer
+ dmac_trigact_19: One trigger required for each block transfer
+ dmac_trigact_2: One trigger required for each beat transfer
+ dmac_trigact_20: One trigger required for each block transfer
+ dmac_trigact_21: One trigger required for each block transfer
+ dmac_trigact_22: One trigger required for each block transfer
+ dmac_trigact_23: One trigger required for each block transfer
+ dmac_trigact_24: One trigger required for each block transfer
+ dmac_trigact_25: One trigger required for each block transfer
+ dmac_trigact_26: One trigger required for each block transfer
+ dmac_trigact_27: One trigger required for each block transfer
+ dmac_trigact_28: One trigger required for each block transfer
+ dmac_trigact_29: One trigger required for each block transfer
+ dmac_trigact_3: One trigger required for each beat transfer
+ dmac_trigact_30: One trigger required for each block transfer
+ dmac_trigact_31: One trigger required for each block transfer
+ dmac_trigact_4: One trigger required for each beat transfer
+ dmac_trigact_5: One trigger required for each beat transfer
+ dmac_trigact_6: One trigger required for each beat transfer
+ dmac_trigact_7: One trigger required for each beat transfer
+ dmac_trigact_8: One trigger required for each block transfer
+ dmac_trigact_9: One trigger required for each block transfer
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ EXTERNAL_IRQ_0:
+ user_label: EXTERNAL_IRQ_0
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ
+ functionality: External_IRQ
+ api: HAL:Driver:Ext_IRQ
+ configuration:
+ eic_arch_asynch0: false
+ eic_arch_asynch1: false
+ eic_arch_asynch10: false
+ eic_arch_asynch11: false
+ eic_arch_asynch12: false
+ eic_arch_asynch13: false
+ eic_arch_asynch14: false
+ eic_arch_asynch15: false
+ eic_arch_asynch2: true
+ eic_arch_asynch3: false
+ eic_arch_asynch4: false
+ eic_arch_asynch5: false
+ eic_arch_asynch6: false
+ eic_arch_asynch7: false
+ eic_arch_asynch8: false
+ eic_arch_asynch9: false
+ eic_arch_cksel: Clocked by GCLK
+ eic_arch_debounce_enable0: false
+ eic_arch_debounce_enable1: false
+ eic_arch_debounce_enable10: false
+ eic_arch_debounce_enable11: false
+ eic_arch_debounce_enable12: false
+ eic_arch_debounce_enable13: false
+ eic_arch_debounce_enable14: false
+ eic_arch_debounce_enable15: false
+ eic_arch_debounce_enable2: false
+ eic_arch_debounce_enable3: false
+ eic_arch_debounce_enable4: false
+ eic_arch_debounce_enable5: false
+ eic_arch_debounce_enable6: false
+ eic_arch_debounce_enable7: false
+ eic_arch_debounce_enable8: false
+ eic_arch_debounce_enable9: false
+ eic_arch_enable_irq_setting0: false
+ eic_arch_enable_irq_setting1: false
+ eic_arch_enable_irq_setting10: false
+ eic_arch_enable_irq_setting11: false
+ eic_arch_enable_irq_setting12: false
+ eic_arch_enable_irq_setting13: false
+ eic_arch_enable_irq_setting14: true
+ eic_arch_enable_irq_setting15: true
+ eic_arch_enable_irq_setting2: true
+ eic_arch_enable_irq_setting3: false
+ eic_arch_enable_irq_setting4: false
+ eic_arch_enable_irq_setting5: false
+ eic_arch_enable_irq_setting6: false
+ eic_arch_enable_irq_setting7: false
+ eic_arch_enable_irq_setting8: false
+ eic_arch_enable_irq_setting9: false
+ eic_arch_extinteo0: false
+ eic_arch_extinteo1: false
+ eic_arch_extinteo10: false
+ eic_arch_extinteo11: false
+ eic_arch_extinteo12: false
+ eic_arch_extinteo13: false
+ eic_arch_extinteo14: false
+ eic_arch_extinteo15: false
+ eic_arch_extinteo2: true
+ eic_arch_extinteo3: false
+ eic_arch_extinteo4: false
+ eic_arch_extinteo5: false
+ eic_arch_extinteo6: false
+ eic_arch_extinteo7: false
+ eic_arch_extinteo8: false
+ eic_arch_extinteo9: false
+ eic_arch_filten0: false
+ eic_arch_filten1: false
+ eic_arch_filten10: false
+ eic_arch_filten11: false
+ eic_arch_filten12: false
+ eic_arch_filten13: false
+ eic_arch_filten14: true
+ eic_arch_filten15: true
+ eic_arch_filten2: false
+ eic_arch_filten3: false
+ eic_arch_filten4: false
+ eic_arch_filten5: false
+ eic_arch_filten6: false
+ eic_arch_filten7: false
+ eic_arch_filten8: false
+ eic_arch_filten9: false
+ eic_arch_nmi_ctrl: false
+ eic_arch_nmiasynch: false
+ eic_arch_nmifilten: false
+ eic_arch_nmisense: No detection
+ eic_arch_prescaler0: Divided by 2
+ eic_arch_prescaler1: Divided by 2
+ eic_arch_sense0: No detection
+ eic_arch_sense1: No detection
+ eic_arch_sense10: No detection
+ eic_arch_sense11: No detection
+ eic_arch_sense12: No detection
+ eic_arch_sense13: No detection
+ eic_arch_sense14: Falling-edge detection
+ eic_arch_sense15: Falling-edge detection
+ eic_arch_sense2: Falling-edge detection
+ eic_arch_sense3: No detection
+ eic_arch_sense4: No detection
+ eic_arch_sense5: No detection
+ eic_arch_sense6: No detection
+ eic_arch_sense7: No detection
+ eic_arch_sense8: No detection
+ eic_arch_sense9: No detection
+ eic_arch_states0: '3'
+ eic_arch_states1: '3'
+ eic_arch_tickon: The sampling rate is EIC clock
+ optional_signals:
+ - identifier: EXTERNAL_IRQ_0:EXTINT/2
+ pad: PA02
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::EIC.EXTINT.2
+ name: EIC/EXTINT/2
+ label: EXTINT/2
+ - identifier: EXTERNAL_IRQ_0:EXTINT/7
+ pad: PA07
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::EIC.EXTINT.7
+ name: EIC/EXTINT/7
+ label: EXTINT/7
+ - identifier: EXTERNAL_IRQ_0:EXTINT/14
+ pad: PB30
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::EIC.EXTINT.14
+ name: EIC/EXTINT/14
+ label: EXTINT/14
+ - identifier: EXTERNAL_IRQ_0:EXTINT/15
+ pad: PB31
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::EIC.EXTINT.15
+ name: EIC/EXTINT/15
+ label: EXTINT/15
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: EIC
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ eic_gclk_selection: Generic clock generator 0
+ EVENT_SYSTEM_0:
+ user_label: EVENT_SYSTEM_0
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::EVSYS::driver_config_definition::Event.System::HAL:Driver:Event.system
+ functionality: Event_System
+ api: HAL:Driver:Event_system
+ configuration:
+ evsys_channel_0: No channel output selected
+ evsys_channel_1: Channel 1
+ evsys_channel_10: Channel 5
+ evsys_channel_11: No channel output selected
+ evsys_channel_12: Channel 2
+ evsys_channel_17: No channel output selected
+ evsys_channel_18: No channel output selected
+ evsys_channel_19: No channel output selected
+ evsys_channel_2: Channel 6
+ evsys_channel_20: No channel output selected
+ evsys_channel_21: No channel output selected
+ evsys_channel_22: No channel output selected
+ evsys_channel_23: No channel output selected
+ evsys_channel_24: No channel output selected
+ evsys_channel_25: No channel output selected
+ evsys_channel_26: No channel output selected
+ evsys_channel_27: No channel output selected
+ evsys_channel_28: No channel output selected
+ evsys_channel_29: No channel output selected
+ evsys_channel_3: Channel 5
+ evsys_channel_30: No channel output selected
+ evsys_channel_31: No channel output selected
+ evsys_channel_32: No channel output selected
+ evsys_channel_33: No channel output selected
+ evsys_channel_34: No channel output selected
+ evsys_channel_35: No channel output selected
+ evsys_channel_36: No channel output selected
+ evsys_channel_37: No channel output selected
+ evsys_channel_38: No channel output selected
+ evsys_channel_39: No channel output selected
+ evsys_channel_4: Channel 8
+ evsys_channel_40: No channel output selected
+ evsys_channel_41: No channel output selected
+ evsys_channel_42: No channel output selected
+ evsys_channel_43: No channel output selected
+ evsys_channel_44: No channel output selected
+ evsys_channel_45: No channel output selected
+ evsys_channel_46: Channel 11
+ evsys_channel_47: No channel output selected
+ evsys_channel_48: Channel 12
+ evsys_channel_49: No channel output selected
+ evsys_channel_5: No channel output selected
+ evsys_channel_50: No channel output selected
+ evsys_channel_51: No channel output selected
+ evsys_channel_52: No channel output selected
+ evsys_channel_53: No channel output selected
+ evsys_channel_54: No channel output selected
+ evsys_channel_55: No channel output selected
+ evsys_channel_56: No channel output selected
+ evsys_channel_57: No channel output selected
+ evsys_channel_58: No channel output selected
+ evsys_channel_59: No channel output selected
+ evsys_channel_6: No channel output selected
+ evsys_channel_60: No channel output selected
+ evsys_channel_61: No channel output selected
+ evsys_channel_62: No channel output selected
+ evsys_channel_63: No channel output selected
+ evsys_channel_64: No channel output selected
+ evsys_channel_65: No channel output selected
+ evsys_channel_66: No channel output selected
+ evsys_channel_7: No channel output selected
+ evsys_channel_8: No channel output selected
+ evsys_channel_9: Channel 0
+ evsys_channel_setting_0: true
+ evsys_channel_setting_1: true
+ evsys_channel_setting_10: false
+ evsys_channel_setting_11: true
+ evsys_channel_setting_12: true
+ evsys_channel_setting_13: false
+ evsys_channel_setting_14: false
+ evsys_channel_setting_15: false
+ evsys_channel_setting_16: false
+ evsys_channel_setting_17: false
+ evsys_channel_setting_18: false
+ evsys_channel_setting_19: false
+ evsys_channel_setting_2: true
+ evsys_channel_setting_20: false
+ evsys_channel_setting_21: false
+ evsys_channel_setting_22: false
+ evsys_channel_setting_23: false
+ evsys_channel_setting_24: false
+ evsys_channel_setting_25: false
+ evsys_channel_setting_26: false
+ evsys_channel_setting_27: false
+ evsys_channel_setting_28: false
+ evsys_channel_setting_29: false
+ evsys_channel_setting_3: true
+ evsys_channel_setting_30: false
+ evsys_channel_setting_31: false
+ evsys_channel_setting_4: true
+ evsys_channel_setting_5: true
+ evsys_channel_setting_6: true
+ evsys_channel_setting_7: true
+ evsys_channel_setting_8: true
+ evsys_channel_setting_9: false
+ evsys_edgsel_0: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_1: Event is detected on the rising edge of the signal from event
+ generator
+ evsys_edgsel_10: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_11: Event is detected on the rising edge of the signal from event
+ generator
+ evsys_edgsel_12: Event is detected on the rising edge of the signal from event
+ generator
+ evsys_edgsel_13: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_14: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_15: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_16: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_17: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_18: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_19: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_2: Event is detected on the rising edge of the signal from event
+ generator
+ evsys_edgsel_20: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_21: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_22: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_23: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_24: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_25: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_26: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_27: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_28: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_29: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_3: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_30: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_31: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_4: No event output when using the resynchronized or synchronous
+ path
+ evsys_edgsel_5: Event is detected on the rising edge of the signal from event
+ generator
+ evsys_edgsel_6: Event is detected on the rising edge of the signal from event
+ generator
+ evsys_edgsel_7: Event is detected on the rising edge of the signal from event
+ generator
+ evsys_edgsel_8: Event is detected on the rising edge of the signal from event
+ generator
+ evsys_edgsel_9: No event output when using the resynchronized or synchronous
+ path
+ evsys_evd_0: false
+ evsys_evd_1: false
+ evsys_evd_10: false
+ evsys_evd_11: false
+ evsys_evd_12: false
+ evsys_evd_13: false
+ evsys_evd_14: false
+ evsys_evd_15: false
+ evsys_evd_16: false
+ evsys_evd_17: false
+ evsys_evd_18: false
+ evsys_evd_19: false
+ evsys_evd_2: false
+ evsys_evd_20: false
+ evsys_evd_21: false
+ evsys_evd_22: false
+ evsys_evd_23: false
+ evsys_evd_24: false
+ evsys_evd_25: false
+ evsys_evd_26: false
+ evsys_evd_27: false
+ evsys_evd_28: false
+ evsys_evd_29: false
+ evsys_evd_3: false
+ evsys_evd_30: false
+ evsys_evd_31: false
+ evsys_evd_4: false
+ evsys_evd_5: false
+ evsys_evd_6: true
+ evsys_evd_7: true
+ evsys_evd_8: false
+ evsys_evd_9: false
+ evsys_evgen_0: TCC0 overflow
+ evsys_evgen_1: TC0 match/capture 0
+ evsys_evgen_10: No event generator
+ evsys_evgen_11: CCL LUT output 0
+ evsys_evgen_12: CCL LUT output 2
+ evsys_evgen_13: No event generator
+ evsys_evgen_14: No event generator
+ evsys_evgen_15: No event generator
+ evsys_evgen_16: No event generator
+ evsys_evgen_17: No event generator
+ evsys_evgen_18: No event generator
+ evsys_evgen_19: No event generator
+ evsys_evgen_2: TC0 match/capture 1
+ evsys_evgen_20: No event generator
+ evsys_evgen_21: No event generator
+ evsys_evgen_22: No event generator
+ evsys_evgen_23: No event generator
+ evsys_evgen_24: No event generator
+ evsys_evgen_25: No event generator
+ evsys_evgen_26: No event generator
+ evsys_evgen_27: No event generator
+ evsys_evgen_28: No event generator
+ evsys_evgen_29: No event generator
+ evsys_evgen_3: TC1 match/capture 1
+ evsys_evgen_30: No event generator
+ evsys_evgen_31: No event generator
+ evsys_evgen_4: No event generator
+ evsys_evgen_5: EIC external interrupt 2
+ evsys_evgen_6: DMAC channel 0
+ evsys_evgen_7: DMAC channel 1
+ evsys_evgen_8: DMAC channel 2
+ evsys_evgen_9: No event generator
+ evsys_ondemand_0: false
+ evsys_ondemand_1: false
+ evsys_ondemand_10: false
+ evsys_ondemand_11: false
+ evsys_ondemand_12: false
+ evsys_ondemand_13: false
+ evsys_ondemand_14: false
+ evsys_ondemand_15: false
+ evsys_ondemand_16: false
+ evsys_ondemand_17: false
+ evsys_ondemand_18: false
+ evsys_ondemand_19: false
+ evsys_ondemand_2: false
+ evsys_ondemand_20: false
+ evsys_ondemand_21: false
+ evsys_ondemand_22: false
+ evsys_ondemand_23: false
+ evsys_ondemand_24: false
+ evsys_ondemand_25: false
+ evsys_ondemand_26: false
+ evsys_ondemand_27: false
+ evsys_ondemand_28: false
+ evsys_ondemand_29: false
+ evsys_ondemand_3: false
+ evsys_ondemand_30: false
+ evsys_ondemand_31: false
+ evsys_ondemand_4: false
+ evsys_ondemand_5: false
+ evsys_ondemand_6: false
+ evsys_ondemand_7: false
+ evsys_ondemand_8: false
+ evsys_ondemand_9: false
+ evsys_ovr_0: false
+ evsys_ovr_1: false
+ evsys_ovr_10: false
+ evsys_ovr_11: false
+ evsys_ovr_12: false
+ evsys_ovr_13: false
+ evsys_ovr_14: false
+ evsys_ovr_15: false
+ evsys_ovr_16: false
+ evsys_ovr_17: false
+ evsys_ovr_18: false
+ evsys_ovr_19: false
+ evsys_ovr_2: false
+ evsys_ovr_20: false
+ evsys_ovr_21: false
+ evsys_ovr_22: false
+ evsys_ovr_23: false
+ evsys_ovr_24: false
+ evsys_ovr_25: false
+ evsys_ovr_26: false
+ evsys_ovr_27: false
+ evsys_ovr_28: false
+ evsys_ovr_29: false
+ evsys_ovr_3: false
+ evsys_ovr_30: false
+ evsys_ovr_31: false
+ evsys_ovr_4: false
+ evsys_ovr_5: false
+ evsys_ovr_6: false
+ evsys_ovr_7: false
+ evsys_ovr_8: false
+ evsys_ovr_9: false
+ evsys_path_0: Asynchronous path
+ evsys_path_1: Asynchronous path
+ evsys_path_10: Synchronous path
+ evsys_path_11: Asynchronous path
+ evsys_path_12: Asynchronous path
+ evsys_path_13: Synchronous path
+ evsys_path_14: Synchronous path
+ evsys_path_15: Synchronous path
+ evsys_path_16: Synchronous path
+ evsys_path_17: Synchronous path
+ evsys_path_18: Synchronous path
+ evsys_path_19: Synchronous path
+ evsys_path_2: Synchronous path
+ evsys_path_20: Synchronous path
+ evsys_path_21: Synchronous path
+ evsys_path_22: Synchronous path
+ evsys_path_23: Synchronous path
+ evsys_path_24: Synchronous path
+ evsys_path_25: Synchronous path
+ evsys_path_26: Synchronous path
+ evsys_path_27: Synchronous path
+ evsys_path_28: Synchronous path
+ evsys_path_29: Synchronous path
+ evsys_path_3: Synchronous path
+ evsys_path_30: Synchronous path
+ evsys_path_31: Synchronous path
+ evsys_path_4: Synchronous path
+ evsys_path_5: Asynchronous path
+ evsys_path_6: Synchronous path
+ evsys_path_7: Synchronous path
+ evsys_path_8: Synchronous path
+ evsys_path_9: Synchronous path
+ evsys_runstdby_0: false
+ evsys_runstdby_1: false
+ evsys_runstdby_10: false
+ evsys_runstdby_11: false
+ evsys_runstdby_12: false
+ evsys_runstdby_13: false
+ evsys_runstdby_14: false
+ evsys_runstdby_15: false
+ evsys_runstdby_16: false
+ evsys_runstdby_17: false
+ evsys_runstdby_18: false
+ evsys_runstdby_19: false
+ evsys_runstdby_2: false
+ evsys_runstdby_20: false
+ evsys_runstdby_21: false
+ evsys_runstdby_22: false
+ evsys_runstdby_23: false
+ evsys_runstdby_24: false
+ evsys_runstdby_25: false
+ evsys_runstdby_26: false
+ evsys_runstdby_27: false
+ evsys_runstdby_28: false
+ evsys_runstdby_29: false
+ evsys_runstdby_3: false
+ evsys_runstdby_30: false
+ evsys_runstdby_31: false
+ evsys_runstdby_4: false
+ evsys_runstdby_5: false
+ evsys_runstdby_6: false
+ evsys_runstdby_7: false
+ evsys_runstdby_8: false
+ evsys_runstdby_9: false
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: Channel 0
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 1
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 2
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 3
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 4
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 5
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 6
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 7
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 8
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 9
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 10
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Channel 11
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ evsys_clk_selection_0: Generic clock generator 0
+ evsys_clk_selection_1: Generic clock generator 0
+ evsys_clk_selection_10: Generic clock generator 0
+ evsys_clk_selection_11: Generic clock generator 0
+ evsys_clk_selection_2: Generic clock generator 0
+ evsys_clk_selection_3: Generic clock generator 0
+ evsys_clk_selection_4: Generic clock generator 0
+ evsys_clk_selection_5: Generic clock generator 0
+ evsys_clk_selection_6: Generic clock generator 0
+ evsys_clk_selection_7: Generic clock generator 0
+ evsys_clk_selection_8: Generic clock generator 0
+ evsys_clk_selection_9: Generic clock generator 0
+ GCLK:
+ user_label: GCLK
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
+ functionality: System
+ api: HAL:HPL:GCLK
+ configuration:
+ $input: 12000000
+ $input_id: External Crystal Oscillator 8-48MHz (XOSC1)
+ RESERVED_InputFreq: 12000000
+ RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1)
+ _$freq_output_Generic clock generator 0: 100000000
+ _$freq_output_Generic clock generator 1: 2000000
+ _$freq_output_Generic clock generator 10: 12000000
+ _$freq_output_Generic clock generator 11: 12000000
+ _$freq_output_Generic clock generator 2: 32768
+ _$freq_output_Generic clock generator 3: 32768
+ _$freq_output_Generic clock generator 4: 12000000
+ _$freq_output_Generic clock generator 5: 12000000
+ _$freq_output_Generic clock generator 6: 12000000
+ _$freq_output_Generic clock generator 7: 12000000
+ _$freq_output_Generic clock generator 8: 12000000
+ _$freq_output_Generic clock generator 9: 12000000
+ enable_gclk_gen_0: true
+ enable_gclk_gen_0__externalclock: 1000000
+ enable_gclk_gen_1: true
+ enable_gclk_gen_10: false
+ enable_gclk_gen_10__externalclock: 1000000
+ enable_gclk_gen_11: false
+ enable_gclk_gen_11__externalclock: 1000000
+ enable_gclk_gen_1__externalclock: 1000000
+ enable_gclk_gen_2: true
+ enable_gclk_gen_2__externalclock: 1000000
+ enable_gclk_gen_3: false
+ enable_gclk_gen_3__externalclock: 1000000
+ enable_gclk_gen_4: false
+ enable_gclk_gen_4__externalclock: 1000000
+ enable_gclk_gen_5: false
+ enable_gclk_gen_5__externalclock: 1000000
+ enable_gclk_gen_6: false
+ enable_gclk_gen_6__externalclock: 1000000
+ enable_gclk_gen_7: false
+ enable_gclk_gen_7__externalclock: 1000000
+ enable_gclk_gen_8: false
+ enable_gclk_gen_8__externalclock: 1000000
+ enable_gclk_gen_9: false
+ enable_gclk_gen_9__externalclock: 1000000
+ gclk_arch_gen_0_enable: true
+ gclk_arch_gen_0_idc: false
+ gclk_arch_gen_0_oe: true
+ gclk_arch_gen_0_oov: false
+ gclk_arch_gen_0_runstdby: false
+ gclk_arch_gen_10_enable: false
+ gclk_arch_gen_10_idc: false
+ gclk_arch_gen_10_oe: false
+ gclk_arch_gen_10_oov: false
+ gclk_arch_gen_10_runstdby: false
+ gclk_arch_gen_11_enable: false
+ gclk_arch_gen_11_idc: false
+ gclk_arch_gen_11_oe: false
+ gclk_arch_gen_11_oov: false
+ gclk_arch_gen_11_runstdby: false
+ gclk_arch_gen_1_enable: true
+ gclk_arch_gen_1_idc: false
+ gclk_arch_gen_1_oe: true
+ gclk_arch_gen_1_oov: false
+ gclk_arch_gen_1_runstdby: false
+ gclk_arch_gen_2_enable: true
+ gclk_arch_gen_2_idc: false
+ gclk_arch_gen_2_oe: true
+ gclk_arch_gen_2_oov: false
+ gclk_arch_gen_2_runstdby: false
+ gclk_arch_gen_3_enable: false
+ gclk_arch_gen_3_idc: false
+ gclk_arch_gen_3_oe: false
+ gclk_arch_gen_3_oov: false
+ gclk_arch_gen_3_runstdby: false
+ gclk_arch_gen_4_enable: false
+ gclk_arch_gen_4_idc: false
+ gclk_arch_gen_4_oe: false
+ gclk_arch_gen_4_oov: false
+ gclk_arch_gen_4_runstdby: false
+ gclk_arch_gen_5_enable: false
+ gclk_arch_gen_5_idc: false
+ gclk_arch_gen_5_oe: false
+ gclk_arch_gen_5_oov: false
+ gclk_arch_gen_5_runstdby: false
+ gclk_arch_gen_6_enable: false
+ gclk_arch_gen_6_idc: false
+ gclk_arch_gen_6_oe: false
+ gclk_arch_gen_6_oov: false
+ gclk_arch_gen_6_runstdby: false
+ gclk_arch_gen_7_enable: false
+ gclk_arch_gen_7_idc: false
+ gclk_arch_gen_7_oe: false
+ gclk_arch_gen_7_oov: false
+ gclk_arch_gen_7_runstdby: false
+ gclk_arch_gen_8_enable: false
+ gclk_arch_gen_8_idc: false
+ gclk_arch_gen_8_oe: false
+ gclk_arch_gen_8_oov: false
+ gclk_arch_gen_8_runstdby: false
+ gclk_arch_gen_9_enable: false
+ gclk_arch_gen_9_idc: false
+ gclk_arch_gen_9_oe: false
+ gclk_arch_gen_9_oov: false
+ gclk_arch_gen_9_runstdby: false
+ gclk_gen_0_div: 1
+ gclk_gen_0_div_sel: false
+ gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL1)
+ gclk_gen_10_div: 1
+ gclk_gen_10_div_sel: false
+ gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_11_div: 1
+ gclk_gen_11_div_sel: false
+ gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_1_div: 24
+ gclk_gen_1_div_sel: false
+ gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M)
+ gclk_gen_2_div: 1
+ gclk_gen_2_div_sel: false
+ gclk_gen_2_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+ gclk_gen_3_div: 1
+ gclk_gen_3_div_sel: false
+ gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
+ gclk_gen_4_div: 1
+ gclk_gen_4_div_sel: false
+ gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_5_div: 1
+ gclk_gen_5_div_sel: false
+ gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_6_div: 1
+ gclk_gen_6_div_sel: false
+ gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_7_div: 1
+ gclk_gen_7_div_sel: false
+ gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_8_div: 1
+ gclk_gen_8_div_sel: false
+ gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ gclk_gen_9_div: 1
+ gclk_gen_9_div_sel: false
+ gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ MCLK:
+ user_label: MCLK
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK
+ functionality: System
+ api: HAL:HPL:MCLK
+ configuration:
+ $input: 100000000
+ $input_id: Generic clock generator 0
+ RESERVED_InputFreq: 100000000
+ RESERVED_InputFreq_id: Generic clock generator 0
+ _$freq_output_CPU: 100000000
+ cpu_clock_source: Generic clock generator 0
+ cpu_div: '1'
+ enable_cpu_clock: true
+ mclk_arch_bupdiv: Divide by 8
+ mclk_arch_hsdiv: Divide by 1
+ mclk_arch_lpdiv: Divide by 4
+ nvm_wait_states: '0'
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: CPU
+ input: CPU
+ external: false
+ external_frequency: 0
+ configuration: {}
+ OSC32KCTRL:
+ user_label: OSC32KCTRL
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL
+ functionality: System
+ api: HAL:HPL:OSC32KCTRL
+ configuration:
+ $input: 32768
+ $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+ RESERVED_InputFreq: 32768
+ RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+ _$freq_output_RTC source: 32768
+ enable_osculp32k: true
+ enable_rtc_source: false
+ enable_xosc32k: false
+ osculp32k_calib: 0
+ osculp32k_calib_enable: false
+ rtc_1khz_selection: false
+ rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+ xosc32k_arch_cfden: false
+ xosc32k_arch_cfdeo: false
+ xosc32k_arch_cgm: Standard mode
+ xosc32k_arch_en1k: false
+ xosc32k_arch_en32k: false
+ xosc32k_arch_enable: false
+ xosc32k_arch_ondemand: true
+ xosc32k_arch_runstdby: false
+ xosc32k_arch_startup: 62592us
+ xosc32k_arch_swben: false
+ xosc32k_arch_xtalen: true
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ OSCCTRL:
+ user_label: OSCCTRL
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL
+ functionality: System
+ api: HAL:HPL:OSCCTRL
+ configuration:
+ $input: 2000000
+ $input_id: Generic clock generator 1
+ RESERVED_InputFreq: 2000000
+ RESERVED_InputFreq_id: Generic clock generator 1
+ _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
+ _$freq_output_Digital Phase Locked Loop (DPLL0): 47985664
+ _$freq_output_Digital Phase Locked Loop (DPLL1): 100000000
+ _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000
+ _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000
+ dfll_arch_bplckc: false
+ dfll_arch_calibration: false
+ dfll_arch_ccdis: false
+ dfll_arch_coarse: 31
+ dfll_arch_cstep: 1
+ dfll_arch_enable: true
+ dfll_arch_fine: 128
+ dfll_arch_fstep: 1
+ dfll_arch_llaw: false
+ dfll_arch_ondemand: false
+ dfll_arch_qldis: false
+ dfll_arch_runstdby: false
+ dfll_arch_stable: false
+ dfll_arch_usbcrm: false
+ dfll_arch_waitlock: true
+ dfll_mode: Open Loop Mode
+ dfll_mul: 0
+ dfll_ref_clock: Generic clock generator 2
+ enable_dfll: true
+ enable_fdpll0: false
+ enable_fdpll1: true
+ enable_xosc0: false
+ enable_xosc1: false
+ fdpll0_arch_dcoen: false
+ fdpll0_arch_enable: false
+ fdpll0_arch_filter: 0
+ fdpll0_arch_lbypass: false
+ fdpll0_arch_ltime: No time-out, automatic lock
+ fdpll0_arch_ondemand: false
+ fdpll0_arch_refclk: XOSC32K clock reference
+ fdpll0_arch_runstdby: false
+ fdpll0_arch_wuf: false
+ fdpll0_clock_dcofilter: 0
+ fdpll0_clock_div: 0
+ fdpll0_ldr: 1463
+ fdpll0_ldrfrac: 13
+ fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
+ fdpll1_arch_dcoen: false
+ fdpll1_arch_enable: true
+ fdpll1_arch_filter: 0
+ fdpll1_arch_lbypass: false
+ fdpll1_arch_ltime: No time-out, automatic lock
+ fdpll1_arch_ondemand: false
+ fdpll1_arch_refclk: GCLK clock reference
+ fdpll1_arch_runstdby: false
+ fdpll1_arch_wuf: false
+ fdpll1_clock_dcofilter: 0
+ fdpll1_clock_div: 0
+ fdpll1_ldr: 49
+ fdpll1_ldrfrac: 0
+ fdpll1_ref_clock: Generic clock generator 1
+ xosc0_arch_cfden: false
+ xosc0_arch_enable: false
+ xosc0_arch_enalc: false
+ xosc0_arch_lowbufgain: false
+ xosc0_arch_ondemand: false
+ xosc0_arch_runstdby: false
+ xosc0_arch_startup: 31us
+ xosc0_arch_swben: false
+ xosc0_arch_xtalen: false
+ xosc0_frequency: 12000000
+ xosc1_arch_cfden: false
+ xosc1_arch_enable: false
+ xosc1_arch_enalc: false
+ xosc1_arch_lowbufgain: false
+ xosc1_arch_ondemand: false
+ xosc1_arch_runstdby: false
+ xosc1_arch_startup: 31us
+ xosc1_arch_swben: false
+ xosc1_arch_xtalen: true
+ xosc1_frequency: 12000000
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ PORT:
+ user_label: PORT
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::PORT::driver_config_definition::PORT::HAL:HPL:PORT
+ functionality: System
+ api: HAL:HPL:PORT
+ configuration:
+ enable_port_input_event_0: true
+ enable_port_input_event_1: true
+ enable_port_input_event_2: true
+ enable_port_input_event_3: true
+ porta_event_action_0: Output register of pin will be set to level of event
+ porta_event_action_1: Output register of pin will be set to level of event
+ porta_event_action_2: Clear output register of pin on event
+ porta_event_action_3: Set output register of pin on event
+ porta_event_pin_identifier_0: 0
+ porta_event_pin_identifier_1: 0
+ porta_event_pin_identifier_2: 14
+ porta_event_pin_identifier_3: 14
+ porta_input_event_enable_0: false
+ porta_input_event_enable_1: false
+ porta_input_event_enable_2: true
+ porta_input_event_enable_3: true
+ portb_event_action_0: Clear output register of pin on event
+ portb_event_action_1: Set output register of pin on event
+ portb_event_action_2: Output register of pin will be set to level of event
+ portb_event_action_3: Output register of pin will be set to level of event
+ portb_event_pin_identifier_0: 22
+ portb_event_pin_identifier_1: 22
+ portb_event_pin_identifier_2: 0
+ portb_event_pin_identifier_3: 0
+ portb_input_event_enable_0: true
+ portb_input_event_enable_1: true
+ portb_input_event_enable_2: false
+ portb_input_event_enable_3: false
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ ECAT_QSPI:
+ user_label: ECAT_QSPI
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::QSPI::driver_config_definition::QSPI.Master::HAL:Driver:QSPI.DMA
+ functionality: Quad_SPI
+ api: HAL:Driver:QSPI_DMA
+ configuration:
+ qspi_advanced: false
+ qspi_baud_rate: 6000000
+ qspi_cpha: Data is changed on the leading edge of SPCK and captured on the following
+ edge of SPCK.
+ qspi_cpol: The inactive state value of SPCK is logic level zero.
+ qspi_dlybs: 0
+ qspi_dlycs: 0
+ qspi_dma_rx_channel: 0
+ qspi_dma_tx_channel: 1
+ optional_signals:
+ - identifier: ECAT_QSPI:CS
+ pad: PB11
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.CS
+ name: QSPI/CS
+ label: CS
+ - identifier: ECAT_QSPI:DATA/0
+ pad: PA08
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.DATA.0
+ name: QSPI/DATA/0
+ label: DATA/0
+ - identifier: ECAT_QSPI:DATA/1
+ pad: PA09
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.DATA.1
+ name: QSPI/DATA/1
+ label: DATA/1
+ - identifier: ECAT_QSPI:DATA/2
+ pad: PA10
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.DATA.2
+ name: QSPI/DATA/2
+ label: DATA/2
+ - identifier: ECAT_QSPI:DATA/3
+ pad: PA11
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.DATA.3
+ name: QSPI/DATA/3
+ label: DATA/3
+ - identifier: ECAT_QSPI:SCK
+ pad: PB10
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.SCK
+ name: QSPI/SCK
+ label: SCK
+ variant: null
+ clocks:
+ domain_group: null
+ RAMECC:
+ user_label: RAMECC
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC
+ functionality: System
+ api: HAL:HPL:RAMECC
+ configuration: {}
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ I2C_0:
+ user_label: I2C_0
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Async
+ functionality: I2C
+ api: HAL:Driver:I2C_Master_Async
+ configuration:
+ i2c_master_advanced: false
+ i2c_master_arch_dbgstop: Keep running
+ i2c_master_arch_inactout: Disabled
+ i2c_master_arch_lowtout: false
+ i2c_master_arch_mexttoen: false
+ i2c_master_arch_runstdby: false
+ i2c_master_arch_sdahold: 300-600ns hold time
+ i2c_master_arch_sexttoen: false
+ i2c_master_arch_trise: 215
+ i2c_master_baud_rate: 100000
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: Core
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Slow
+ input: Generic clock generator 3
+ external: false
+ external_frequency: 0
+ configuration:
+ core_gclk_selection: Generic clock generator 0
+ slow_gclk_selection: Generic clock generator 3
+ SPI_1_MSIF:
+ user_label: SPI_1_MSIF
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::SERCOM1::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.DMA
+ functionality: SPI
+ api: HAL:Driver:SPI_Master_DMA
+ configuration:
+ spi_master_advanced: true
+ spi_master_arch_cpha: Sample input on leading edge
+ spi_master_arch_cpol: SCK is low when idle
+ spi_master_arch_dbgstop: Keep running
+ spi_master_arch_dord: MSB first
+ spi_master_arch_ibon: In data stream
+ spi_master_arch_runstdby: false
+ spi_master_baud_rate: 1000000
+ spi_master_character_size: 8 bits
+ spi_master_dma_rx_channel: 0
+ spi_master_dma_tx_channel: 7
+ spi_master_dummybyte: 511
+ spi_master_rx_channel: true
+ spi_master_rx_enable: true
+ optional_signals: []
+ variant:
+ specification: TXPO=0, RXPO=3
+ required_signals:
+ - name: SERCOM1/PAD/0
+ pad: PA00
+ label: MOSI
+ - name: SERCOM1/PAD/1
+ pad: PA01
+ label: SCK
+ - name: SERCOM1/PAD/3
+ pad: PB23
+ label: MISO
+ clocks:
+ domain_group:
+ nodes:
+ - name: Core
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Slow
+ input: Generic clock generator 3
+ external: false
+ external_frequency: 0
+ configuration:
+ core_gclk_selection: Generic clock generator 0
+ slow_gclk_selection: Generic clock generator 3
+ SPI_2:
+ user_label: SPI_2
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::SERCOM2::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync
+ functionality: SPI
+ api: HAL:Driver:SPI_Master_Sync
+ configuration:
+ spi_master_advanced: true
+ spi_master_arch_cpha: Sample input on trailing edge
+ spi_master_arch_cpol: SCK is low when idle
+ spi_master_arch_dbgstop: Keep running
+ spi_master_arch_dord: MSB first
+ spi_master_arch_ibon: On buffer overflow
+ spi_master_arch_runstdby: false
+ spi_master_baud_rate: 1000000
+ spi_master_character_size: 8 bits
+ spi_master_dummybyte: 511
+ spi_master_rx_enable: true
+ optional_signals: []
+ variant:
+ specification: TXPO=0, RXPO=3
+ required_signals:
+ - name: SERCOM2/PAD/0
+ pad: PA12
+ label: MOSI
+ - name: SERCOM2/PAD/1
+ pad: PA13
+ label: SCK
+ - name: SERCOM2/PAD/3
+ pad: PA15
+ label: MISO
+ clocks:
+ domain_group:
+ nodes:
+ - name: Core
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Slow
+ input: Generic clock generator 3
+ external: false
+ external_frequency: 0
+ configuration:
+ core_gclk_selection: Generic clock generator 0
+ slow_gclk_selection: Generic clock generator 3
+ SPI_3:
+ user_label: SPI_3
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::SERCOM5::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync
+ functionality: SPI
+ api: HAL:Driver:SPI_Master_Sync
+ configuration:
+ spi_master_advanced: false
+ spi_master_arch_cpha: Sample input on leading edge
+ spi_master_arch_cpol: SCK is low when idle
+ spi_master_arch_dbgstop: Keep running
+ spi_master_arch_dord: MSB first
+ spi_master_arch_ibon: In data stream
+ spi_master_arch_runstdby: false
+ spi_master_baud_rate: 1000000
+ spi_master_character_size: 8 bits
+ spi_master_dummybyte: 511
+ spi_master_rx_enable: true
+ optional_signals: []
+ variant:
+ specification: TXPO=0, RXPO=3
+ required_signals:
+ - name: SERCOM5/PAD/0
+ pad: PB02
+ label: MOSI
+ - name: SERCOM5/PAD/1
+ pad: PB03
+ label: SCK
+ - name: SERCOM5/PAD/3
+ pad: PB01
+ label: MISO
+ clocks:
+ domain_group:
+ nodes:
+ - name: Core
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Slow
+ input: Generic clock generator 3
+ external: false
+ external_frequency: 0
+ configuration:
+ core_gclk_selection: Generic clock generator 0
+ slow_gclk_selection: Generic clock generator 3
+ TIMER_0:
+ user_label: TIMER_0
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TC0::driver_config_definition::8-bit.Counter.Mode::Lite:TC:Timer
+ functionality: Timer
+ api: Lite:TC:Timer
+ configuration:
+ cc_cc0: 10
+ cc_cc1: 60
+ cc_control: true
+ count_control: false
+ count_count: 0
+ ctrla_alock: false
+ ctrla_capten0: false
+ ctrla_capten1: false
+ ctrla_captmode0: DEFAULT
+ ctrla_captmode1: DEFAULT
+ ctrla_control: true
+ ctrla_copen0: false
+ ctrla_copen1: false
+ ctrla_enable: true
+ ctrla_mode: 1
+ ctrla_ondemand: false
+ ctrla_prescaler: DIV8
+ ctrla_prescsync: GCLK
+ ctrla_runstdby: false
+ ctrlbset_cmd: NONE
+ ctrlbset_control: false
+ ctrlbset_dir: false
+ ctrlbset_lupd: false
+ ctrlbset_oneshot: false
+ ctrlc_inven0: false
+ ctrlc_inven1: false
+ dbgctrl_control: false
+ dbgctrl_dbgrun: false
+ drvctrl_control: false
+ evctrl_control: true
+ evctrl_evact: 'OFF'
+ evctrl_mceo0: true
+ evctrl_mceo1: true
+ evctrl_ovfeo: false
+ evctrl_tcei: false
+ evctrl_tcinv: false
+ intenset_control: true
+ intenset_err: false
+ intenset_mc0: false
+ intenset_mc1: false
+ intenset_ovf: true
+ per_control: true
+ per_per: 250
+ wave_control: true
+ wave_wavegen: NFRQ
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: TC
+ input: Generic clock generator 1
+ external: false
+ external_frequency: 0
+ configuration:
+ tc_gclk_selection: Generic clock generator 1
+ TIMER_SPARE:
+ user_label: TIMER_SPARE
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TC1::driver_config_definition::8-bit.Counter.Mode::Lite:TC:Timer
+ functionality: Timer
+ api: Lite:TC:Timer
+ configuration:
+ cc_cc0: 10
+ cc_cc1: 60
+ cc_control: true
+ count_control: false
+ count_count: 0
+ ctrla_alock: false
+ ctrla_capten0: false
+ ctrla_capten1: false
+ ctrla_captmode0: DEFAULT
+ ctrla_captmode1: DEFAULT
+ ctrla_control: true
+ ctrla_copen0: false
+ ctrla_copen1: false
+ ctrla_enable: false
+ ctrla_mode: 1
+ ctrla_ondemand: false
+ ctrla_prescaler: DIV4
+ ctrla_prescsync: GCLK
+ ctrla_runstdby: false
+ ctrlbset_cmd: NONE
+ ctrlbset_control: false
+ ctrlbset_dir: false
+ ctrlbset_lupd: false
+ ctrlbset_oneshot: false
+ ctrlc_inven0: false
+ ctrlc_inven1: false
+ dbgctrl_control: false
+ dbgctrl_dbgrun: false
+ drvctrl_control: false
+ evctrl_control: true
+ evctrl_evact: 'OFF'
+ evctrl_mceo0: true
+ evctrl_mceo1: true
+ evctrl_ovfeo: true
+ evctrl_tcei: false
+ evctrl_tcinv: false
+ intenset_control: true
+ intenset_err: false
+ intenset_mc0: false
+ intenset_mc1: true
+ intenset_ovf: true
+ per_control: true
+ per_per: 250
+ wave_control: true
+ wave_wavegen: NFRQ
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: TC
+ input: Generic clock generator 1
+ external: false
+ external_frequency: 0
+ configuration:
+ tc_gclk_selection: Generic clock generator 1
+ TC_SPEED_M1:
+ user_label: TC_SPEED_M1
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TC2::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer
+ functionality: Timer
+ api: Lite:TC:Timer
+ configuration:
+ cc_cc0: 0
+ cc_cc1: 0
+ cc_control: false
+ count_control: false
+ count_count: 0
+ ctrla_alock: false
+ ctrla_capten0: true
+ ctrla_capten1: true
+ ctrla_captmode0: DEFAULT
+ ctrla_captmode1: DEFAULT
+ ctrla_control: true
+ ctrla_copen0: false
+ ctrla_copen1: false
+ ctrla_enable: true
+ ctrla_mode: 2
+ ctrla_ondemand: false
+ ctrla_prescaler: DIV4
+ ctrla_prescsync: GCLK
+ ctrla_runstdby: false
+ ctrlbset_cmd: NONE
+ ctrlbset_control: false
+ ctrlbset_dir: false
+ ctrlbset_lupd: false
+ ctrlbset_oneshot: false
+ ctrlc_inven0: false
+ ctrlc_inven1: false
+ dbgctrl_control: false
+ dbgctrl_dbgrun: false
+ drvctrl_control: false
+ evctrl_control: true
+ evctrl_evact: PPW
+ evctrl_mceo0: false
+ evctrl_mceo1: false
+ evctrl_ovfeo: true
+ evctrl_tcei: true
+ evctrl_tcinv: false
+ intenset_control: true
+ intenset_err: false
+ intenset_mc0: false
+ intenset_mc1: false
+ intenset_ovf: true
+ wave_control: true
+ wave_wavegen: NFRQ
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: TC
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ tc_gclk_selection: Generic clock generator 0
+ TC_SPEED_M2:
+ user_label: TC_SPEED_M2
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TC4::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer
+ functionality: Timer
+ api: Lite:TC:Timer
+ configuration:
+ cc_cc0: 0
+ cc_cc1: 0
+ cc_control: false
+ count_control: false
+ count_count: 0
+ ctrla_alock: false
+ ctrla_capten0: true
+ ctrla_capten1: true
+ ctrla_captmode0: DEFAULT
+ ctrla_captmode1: DEFAULT
+ ctrla_control: true
+ ctrla_copen0: false
+ ctrla_copen1: false
+ ctrla_enable: true
+ ctrla_mode: 2
+ ctrla_ondemand: false
+ ctrla_prescaler: DIV4
+ ctrla_prescsync: GCLK
+ ctrla_runstdby: false
+ ctrlbset_cmd: NONE
+ ctrlbset_control: false
+ ctrlbset_dir: false
+ ctrlbset_lupd: false
+ ctrlbset_oneshot: false
+ ctrlc_inven0: false
+ ctrlc_inven1: false
+ dbgctrl_control: false
+ dbgctrl_dbgrun: false
+ drvctrl_control: false
+ evctrl_control: true
+ evctrl_evact: PPW
+ evctrl_mceo0: false
+ evctrl_mceo1: false
+ evctrl_ovfeo: true
+ evctrl_tcei: true
+ evctrl_tcinv: false
+ intenset_control: true
+ intenset_err: false
+ intenset_mc0: false
+ intenset_mc1: false
+ intenset_ovf: true
+ wave_control: true
+ wave_wavegen: NFRQ
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: TC
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ tc_gclk_selection: Generic clock generator 0
+ PWM_0:
+ user_label: PWM_0
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TCC0::driver_config_definition::PWM::HAL:Driver:PWM
+ functionality: PWM
+ api: HAL:Driver:PWM
+ configuration:
+ tcc_arch_alock: false
+ tcc_arch_cc0: 0
+ tcc_arch_cc1: 0
+ tcc_arch_cc2: 0
+ tcc_arch_cc3: 0
+ tcc_arch_cc4: 0
+ tcc_arch_cc5: 0
+ tcc_arch_cnteo: false
+ tcc_arch_cntsel: An interrupt/event is generated when a new counter cycle starts
+ tcc_arch_cpten0: false
+ tcc_arch_cpten1: false
+ tcc_arch_cpten2: false
+ tcc_arch_cpten3: false
+ tcc_arch_cpten4: false
+ tcc_arch_cpten5: false
+ tcc_arch_cpten6: false
+ tcc_arch_cpten7: false
+ tcc_arch_dbgrun: false
+ tcc_arch_evact0: Event action disabled
+ tcc_arch_evact1: Event action disabled
+ tcc_arch_lupd: false
+ tcc_arch_mcei0: false
+ tcc_arch_mcei1: false
+ tcc_arch_mcei2: false
+ tcc_arch_mcei3: false
+ tcc_arch_mcei4: false
+ tcc_arch_mcei5: false
+ tcc_arch_mceo0: false
+ tcc_arch_mceo1: false
+ tcc_arch_mceo2: false
+ tcc_arch_mceo3: false
+ tcc_arch_mceo4: false
+ tcc_arch_mceo5: false
+ tcc_arch_ovfeo: true
+ tcc_arch_prescsync: Reload or reset counter on next GCLK
+ tcc_arch_runstdby: false
+ tcc_arch_sel_ch: 2
+ tcc_arch_tcei0: false
+ tcc_arch_tcei1: false
+ tcc_arch_tceinv0: false
+ tcc_arch_tceinv1: false
+ tcc_arch_trgeo: false
+ tcc_arch_wave_duty_val: 500
+ tcc_arch_wave_per_val: 48
+ tcc_arch_wavegen: Dual-slope, interrupt/event at ZERO (DSBOTTOM)
+ tcc_per: 10000
+ tcc_prescaler: Divide by 2
+ timer_event_control: true
+ optional_signals:
+ - identifier: PWM_0:WO/0
+ pad: PB12
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.0
+ name: TCC0/WO/0
+ label: WO/0
+ - identifier: PWM_0:WO/1
+ pad: PB13
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.1
+ name: TCC0/WO/1
+ label: WO/1
+ - identifier: PWM_0:WO/2
+ pad: PB14
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.2
+ name: TCC0/WO/2
+ label: WO/2
+ - identifier: PWM_0:WO/3
+ pad: PB15
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.3
+ name: TCC0/WO/3
+ label: WO/3
+ - identifier: PWM_0:WO/4
+ pad: PB16
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.4
+ name: TCC0/WO/4
+ label: WO/4
+ - identifier: PWM_0:WO/5
+ pad: PB17
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.5
+ name: TCC0/WO/5
+ label: WO/5
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: TCC
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ tcc_gclk_selection: Generic clock generator 0
+ PWM_1:
+ user_label: PWM_1
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TCC1::driver_config_definition::PWM::HAL:Driver:PWM
+ functionality: PWM
+ api: HAL:Driver:PWM
+ configuration:
+ tcc_arch_alock: false
+ tcc_arch_cc0: 0
+ tcc_arch_cc1: 0
+ tcc_arch_cc2: 0
+ tcc_arch_cc3: 0
+ tcc_arch_cnteo: false
+ tcc_arch_cntsel: An interrupt/event is generated when a new counter cycle starts
+ tcc_arch_cpten0: false
+ tcc_arch_cpten1: false
+ tcc_arch_cpten2: false
+ tcc_arch_cpten3: false
+ tcc_arch_cpten4: false
+ tcc_arch_cpten5: false
+ tcc_arch_cpten6: false
+ tcc_arch_cpten7: false
+ tcc_arch_dbgrun: false
+ tcc_arch_evact0: Event action disabled
+ tcc_arch_evact1: Event action disabled
+ tcc_arch_lupd: false
+ tcc_arch_mcei0: false
+ tcc_arch_mcei1: false
+ tcc_arch_mcei2: false
+ tcc_arch_mcei3: false
+ tcc_arch_mceo0: false
+ tcc_arch_mceo1: false
+ tcc_arch_mceo2: false
+ tcc_arch_mceo3: false
+ tcc_arch_ovfeo: false
+ tcc_arch_prescsync: Reload or reset counter on next GCLK
+ tcc_arch_runstdby: false
+ tcc_arch_sel_ch: 2
+ tcc_arch_tcei0: false
+ tcc_arch_tcei1: false
+ tcc_arch_tceinv0: false
+ tcc_arch_tceinv1: false
+ tcc_arch_trgeo: false
+ tcc_arch_wave_duty_val: 500
+ tcc_arch_wave_per_val: 48
+ tcc_arch_wavegen: Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
+ tcc_per: 10000
+ tcc_prescaler: Divide by 2
+ timer_event_control: true
+ optional_signals:
+ - identifier: PWM_1:WO/0
+ pad: PA16
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.0
+ name: TCC1/WO/0
+ label: WO/0
+ - identifier: PWM_1:WO/1
+ pad: PA17
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.1
+ name: TCC1/WO/1
+ label: WO/1
+ - identifier: PWM_1:WO/2
+ pad: PA18
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.2
+ name: TCC1/WO/2
+ label: WO/2
+ - identifier: PWM_1:WO/3
+ pad: PA19
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.3
+ name: TCC1/WO/3
+ label: WO/3
+ - identifier: PWM_1:WO/4
+ pad: PA20
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.4
+ name: TCC1/WO/4
+ label: WO/4
+ - identifier: PWM_1:WO/5
+ pad: PA21
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.5
+ name: TCC1/WO/5
+ label: WO/5
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: TCC
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ tcc_gclk_selection: Generic clock generator 0
+pads:
+ SPI1_MOSI:
+ name: PA00
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA00
+ mode: Digital output
+ user_label: SPI1_MOSI
+ configuration: null
+ SPI1_SCK:
+ name: PA01
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA01
+ mode: Digital output
+ user_label: SPI1_SCK
+ configuration: null
+ ADS_DATA_RDY:
+ name: PA02
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA02
+ mode: Digital input
+ user_label: ADS_DATA_RDY
+ configuration: null
+ ANAREF_3V:
+ name: PA03
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA03
+ mode: Analog
+ user_label: ANAREF_3V
+ configuration: null
+ M1_IA:
+ name: PB04
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB04
+ mode: Analog
+ user_label: M1_IA
+ configuration: null
+ M1_IB:
+ name: PB05
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB05
+ mode: Analog
+ user_label: M1_IB
+ configuration: null
+ M2_IA:
+ name: PB06
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB06
+ mode: Analog
+ user_label: M2_IA
+ configuration: null
+ M2_IB:
+ name: PB07
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB07
+ mode: Analog
+ user_label: M2_IB
+ configuration: null
+ half_VREF:
+ name: PB08
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB08
+ mode: Analog
+ user_label: half_VREF
+ configuration: null
+ ADS_RESET:
+ name: PB09
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB09
+ mode: Digital output
+ user_label: ADS_RESET
+ configuration:
+ pad_initial_level: High
+ M1_HALLA:
+ name: PA04
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA04
+ mode: Peripheral IO
+ user_label: M1_HALLA
+ configuration: null
+ M1_HALLB:
+ name: PA05
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA05
+ mode: Peripheral IO
+ user_label: M1_HALLB
+ configuration: null
+ M1_HALLC:
+ name: PA06
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA06
+ mode: Peripheral IO
+ user_label: M1_HALLC
+ configuration: null
+ ECAT_SYNC:
+ name: PA07
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA07
+ mode: Digital input
+ user_label: ECAT_SYNC
+ configuration: null
+ ECAT_QSPI_MOSI:
+ name: PA08
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA08
+ mode: Advanced
+ user_label: ECAT_QSPI_MOSI
+ configuration: null
+ ECAT_QSPI_MISO:
+ name: PA09
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA09
+ mode: Advanced
+ user_label: ECAT_QSPI_MISO
+ configuration: null
+ ECAT_QSPI_DATA2:
+ name: PA10
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA10
+ mode: Advanced
+ user_label: ECAT_QSPI_DATA2
+ configuration: null
+ ECAT_QSPI_DATA3:
+ name: PA11
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA11
+ mode: Advanced
+ user_label: ECAT_QSPI_DATA3
+ configuration: null
+ ECAT_QSPI_SCK:
+ name: PB10
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB10
+ mode: Digital input
+ user_label: ECAT_QSPI_SCK
+ configuration: null
+ ECAT_QSPI_CS:
+ name: PB11
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB11
+ mode: Digital input
+ user_label: ECAT_QSPI_CS
+ configuration: null
+ M1_PWMA:
+ name: PB12
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB12
+ mode: Peripheral IO
+ user_label: M1_PWMA
+ configuration: null
+ M1_PWMB:
+ name: PB13
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB13
+ mode: Peripheral IO
+ user_label: M1_PWMB
+ configuration: null
+ M1_PWMC:
+ name: PB14
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB14
+ mode: Peripheral IO
+ user_label: M1_PWMC
+ configuration: null
+ M1_ENA:
+ name: PB15
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB15
+ mode: Peripheral IO
+ user_label: M1_ENA
+ configuration: null
+ SPI2_MOSI:
+ name: PA12
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA12
+ mode: Digital output
+ user_label: SPI2_MOSI
+ configuration: null
+ SPI2_SCK:
+ name: PA13
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA13
+ mode: Digital output
+ user_label: SPI2_SCK
+ configuration: null
+ SPI2_SS:
+ name: PA14
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA14
+ mode: Digital output
+ user_label: SPI2_SS
+ configuration:
+ pad_initial_level: High
+ SPI2_MISO:
+ name: PA15
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA15
+ mode: Digital input
+ user_label: SPI2_MISO
+ configuration: null
+ M2_PWMA:
+ name: PA16
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA16
+ mode: Peripheral IO
+ user_label: M2_PWMA
+ configuration: null
+ M2_PWMB:
+ name: PA17
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA17
+ mode: Peripheral IO
+ user_label: M2_PWMB
+ configuration: null
+ M2_PWMC:
+ name: PA18
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA18
+ mode: Peripheral IO
+ user_label: M2_PWMC
+ configuration: null
+ M2_ENA:
+ name: PA19
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA19
+ mode: Peripheral IO
+ user_label: M2_ENA
+ configuration: null
+ M1_ENB:
+ name: PB16
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB16
+ mode: Peripheral IO
+ user_label: M1_ENB
+ configuration: null
+ M1_ENC:
+ name: PB17
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB17
+ mode: Peripheral IO
+ user_label: M1_ENC
+ configuration: null
+ M2_ENB:
+ name: PA20
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA20
+ mode: Peripheral IO
+ user_label: M2_ENB
+ configuration: null
+ M2_ENC:
+ name: PA21
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA21
+ mode: Peripheral IO
+ user_label: M2_ENC
+ configuration: null
+ M2_HALLA:
+ name: PA22
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA22
+ mode: Peripheral IO
+ user_label: M2_HALLA
+ configuration: null
+ M2_HALLB:
+ name: PA23
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA23
+ mode: Peripheral IO
+ user_label: M2_HALLB
+ configuration: null
+ M2_HALLC:
+ name: PA24
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA24
+ mode: Peripheral IO
+ user_label: M2_HALLC
+ configuration: null
+ M1_RST:
+ name: PA25
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA25
+ mode: Digital output
+ user_label: M1_RST
+ configuration: null
+ SPI1_CS:
+ name: PB22
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB22
+ mode: Digital output
+ user_label: SPI1_CS
+ configuration:
+ pad_initial_level: High
+ SPI1_MISO:
+ name: PB23
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB23
+ mode: Digital input
+ user_label: SPI1_MISO
+ configuration: null
+ M2_RST:
+ name: PA27
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA27
+ mode: Digital output
+ user_label: M2_RST
+ configuration: null
+ M1_RST_Bar:
+ name: PB30
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB30
+ mode: Digital input
+ user_label: M1_RST_Bar
+ configuration: null
+ M2_RST_Bar:
+ name: PB31
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB31
+ mode: Digital input
+ user_label: M2_RST_Bar
+ configuration: null
+ SPI3_SS:
+ name: PB00
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB00
+ mode: Digital output
+ user_label: SPI3_SS
+ configuration:
+ pad_initial_level: High
+ SPI3_MISO:
+ name: PB01
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB01
+ mode: Digital input
+ user_label: SPI3_MISO
+ configuration: null
+ SPI3_MOSI:
+ name: PB02
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB02
+ mode: Digital output
+ user_label: SPI3_MOSI
+ configuration: null
+ SPI3_SCK:
+ name: PB03
+ definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB03
+ mode: Digital output
+ user_label: SPI3_SCK
+ configuration: null
+toolchain_options: []
+static_files: []
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.c
new file mode 100644
index 0000000..545750c
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.c
@@ -0,0 +1,330 @@
+/*
+ * ADS1299.c
+ *
+ * Created: 8/22/2021 3:25:55 PM
+ * Author: ge37vez
+ */
+
+#include "ADS1299.h"
+
+/* Settings
+* No daisy:
+* 4 EMG channels channels at 1000.0 Hz.
+* Gain 24, SRB2 Open, Normal electrode input
+* Route all Channels_P to Bias derivation
+* Route all Channels_P to Bias derivation
+* Lead off functions off
+
+Expected ADS Board Registers
+* ADS_ID, 00, 3C, 0, 0, 1, 1, 1, 1, 1, 0
+* CONFIG1, 01, 94, 1, 0, 0, 1, 0, 1, 0, 0
+* CONFIG2, 02, C0, 1, 1, 0, 0, 0, 0, 0, 0
+* CONFIG3, 03, EC, 1, 1, 1, 0, 1, 1, 0, 0
+* LOFF, 04, 02, 0, 0, 0, 0, 0, 0, 1, 0
+* CH1SET, 05, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH2SET, 06, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH3SET, 07, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH4SET, 08, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH5SET, 09, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH6SET, 0A, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH7SET, 0B, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH8SET, 0C, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* BIAS_SENSP, 0D, FF, 1, 1, 1, 1, 1, 1, 1, 1
+* BIAS_SENSN, 0E, FF, 1, 1, 1, 1, 1, 1, 1, 1
+* LOFF_SENSP, 0F, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* LOFF_SENSN, 10, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* LOFF_FLIP, 11, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* LOFF_STATP, 12, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* LOFF_STATN, 13, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* GPIO, 14, 0F, 0, 0, 0, 0, 1, 1, 1, 1
+* MISC1, 15, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* MISC2, 16, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* CONFIG4, 17, 00, 0, 0, 0, 0, 0, 0, 0, 0
+*/
+
+void initialize_ads()
+{
+ spi_m_sync_disable(ADS1299.SPI_descr);
+ /* Set Mode 1 */
+ hri_sercomspi_write_CTRLA_CPOL_bit((SercomSpi *)(ADS1299.SPI_descr->dev.prvt), false);
+ hri_sercomspi_write_CTRLA_CPHA_bit((SercomSpi *)(ADS1299.SPI_descr->dev.prvt), true);
+ /* Init SPI*/
+ spi_m_sync_enable(ADS1299.SPI_descr);
+ gpio_set_pin_level(ADS1299.SS_pin, true);
+ delay_us(20);
+
+ /* Reset ADS1299 - Reset Active Low*/
+ gpio_set_pin_level(ADS1299.reset_pin, false);
+ delay_us(20);
+ gpio_set_pin_level(ADS1299.reset_pin, true);
+ delay_us(20);
+
+ ADS1299_RESET(); // all registers set to default
+ ADS1299_SDATAC(); // stop Read Data Continuous mode to communicate with ADS
+ ADS1299_RREGS(0x00, 0x17); // read ADS registers starting at 0x00 and ending at 0x17
+
+ /* Write Config Registers */
+ ADS1299_WREG(CONFIG1,0x94); // Set Config 1 Register
+ //ADS1299_WREG(CONFIG2,0xC0); // Set Config 2 Register - Standard
+ ADS1299_WREG(CONFIG2,0xD4); // Set Config 2 Register - internal test signal, pulsed
+ //ADS1299_WREG(CONFIG2,0xD7); // Set Config 2 Register - internal test signal, DC
+ ADS1299_WREG(CONFIG3,0xEC); // Set Config 3 Register
+ ADS1299_WREG(LOFF,0x02); // Set LOFF Register
+ for(uint8_t i=CH1SET; i<=CH4SET; i++) // set up to modify the 4 channel setting registers
+ {
+ //ADS1299.reg_data[i] = 0x68; // the regData array mirrors the ADS1299 register addresses
+ ADS1299.reg_data[i] = 0x6D; // Test signal
+ }
+ ADS1299_WREGS(CH1SET,3); // write new channel settings
+ ADS1299_WREG(BIAS_SENSP,0xFF); // Set BIAS_SENSP Register
+ ADS1299_WREG(BIAS_SENSN,0xFF); // Set BIAS_SENSN Register
+ ADS1299_WREG(BIAS_SENSP,0xFF); // Set BIAS_SENSP Register
+ ADS1299_WREG(GPIO_REG,0x0F); // Set BIAS_SENSP Register
+ /* Remaining Registers left at 0x00 */
+ ADS1299_RREGS(0x00, 0x17); // read ADS registers to verify settings
+ ADS1299_RDATAC(); // enter Read Data Continuous mode
+ volatile int x = 0;
+}
+
+uint8_t getDeviceID()
+{
+ uint8_t data = ADS1299_RREG(0x00);
+ return data;
+}
+
+// ----------------------------------------------------------------------
+// AS5048 Registers & Commands
+// ----------------------------------------------------------------------
+
+void ADS1299_WAKEUP() {
+ gpio_set_pin_level(ADS1299.SS_pin, false);
+ _transfer_byte(ADS1299.SPI_descr, _WAKEUP);
+ gpio_set_pin_level(ADS1299.SS_pin, true);
+ delay_us(3); //must wait 4 tCLK cycles before sending another command (Datasheet, pg. 35)
+}
+
+void ADS1299_STANDBY() { // only allowed to send WAKEUP after sending STANDBY
+ gpio_set_pin_level(ADS1299.SS_pin, false);
+ _transfer_byte(ADS1299.SPI_descr, _STANDBY);
+ gpio_set_pin_level(ADS1299.SS_pin, true);
+}
+
+void ADS1299_RESET() { // reset all the registers to default settings
+ gpio_set_pin_level(ADS1299.SS_pin, false);
+ _transfer_byte(ADS1299.SPI_descr, _RESET);
+ delay_us(12); //must wait 18 tCLK cycles to execute this command (Datasheet, pg. 35)
+ gpio_set_pin_level(ADS1299.SS_pin, true);
+}
+
+void ADS1299_START() { //start data conversion
+ gpio_set_pin_level(ADS1299.SS_pin, false);
+ _transfer_byte(ADS1299.SPI_descr, _START);
+ gpio_set_pin_level(ADS1299.SS_pin, true);
+ init_streaming_mode();
+
+}
+
+void init_streaming_mode()
+{
+ spi_m_sync_disable(ADS1299.SPI_descr);
+ /* Change to 32-Bit Mode */
+ SERCOM2->SPI.CTRLC.bit.ICSPACE = 4;
+ SERCOM2->SPI.CTRLC.bit.DATA32B= true;
+ SERCOM2->SPI.LENGTH.bit.LENEN = true;
+ SERCOM2->SPI.LENGTH.bit.LEN = 3;
+ /* Init SPI*/
+ spi_m_sync_enable(ADS1299.SPI_descr);
+}
+void ADS1299_STOP() { //stop data conversion
+ gpio_set_pin_level(ADS1299.SS_pin, false);
+ _transfer_byte(ADS1299.SPI_descr, _STOP);
+ gpio_set_pin_level(ADS1299.SS_pin, true);
+}
+
+void ADS1299_RDATAC() {
+ gpio_set_pin_level(ADS1299.SS_pin, false);
+ _transfer_byte(ADS1299.SPI_descr, _RDATAC);
+ gpio_set_pin_level(ADS1299.SS_pin, true);
+ delay_us(3);
+}
+void ADS1299_SDATAC() {
+ gpio_set_pin_level(ADS1299.SS_pin, false);
+ _transfer_byte(ADS1299.SPI_descr, _SDATAC);
+ gpio_set_pin_level(ADS1299.SS_pin, true);
+ delay_us(3); //must wait 4 tCLK cycles after executing this command (Datasheet, pg. 37)
+}
+
+// ----------------------------------------------------------------------
+// SPI register Related Commands
+// ----------------------------------------------------------------------
+// reads ONE register at _address
+uint8_t ADS1299_RREG(uint8_t _address)
+{
+ uint8_t opcode1 = _address + 0x20; // RREG expects 001rrrrr where rrrrr = _address
+ gpio_set_pin_level(ADS1299.SS_pin, false);
+ _transfer_byte(ADS1299.SPI_descr, opcode1);
+ _transfer_byte(ADS1299.SPI_descr, 0x00);
+ ADS1299.reg_data[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00);
+ gpio_set_pin_level(ADS1299.SS_pin, true);
+ return ADS1299.reg_data[_address];
+}
+
+// Read more than one register starting at _address
+void ADS1299_RREGS(uint8_t _address, uint8_t _numRegistersMinusOne)
+{
+ uint8_t opcode1 = _address + 0x20; // RREG expects 001rrrrr where rrrrr = _address
+ gpio_set_pin_level(ADS1299.SS_pin, false);
+ _transfer_byte(ADS1299.SPI_descr, opcode1);
+ _transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne);
+ for(int i = 0; i <= _numRegistersMinusOne; i++){ // add register uint8_t to mirror array
+ ADS1299.reg_data[_address + i] = _transfer_byte(ADS1299.SPI_descr, 0x00);
+ }
+ //ADS1299.regData[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00);
+ gpio_set_pin_level(ADS1299.SS_pin, true);
+}
+
+void ADS1299_WREG(uint8_t _address, uint8_t _value) { // Write ONE register at _address
+ uint8_t opcode1 = _address + 0x40; // WREG expects 010rrrrr where rrrrr = _address
+ gpio_set_pin_level(ADS1299.SS_pin, false); // open SPI
+ _transfer_byte(ADS1299.SPI_descr, opcode1); // Send WREG command & address
+ _transfer_byte(ADS1299.SPI_descr, 0x00); // Send number of registers to read -1
+ _transfer_byte(ADS1299.SPI_descr, _value); // Write the value to the register
+ gpio_set_pin_level(ADS1299.SS_pin, true); // close SPI
+ ADS1299.reg_data[_address] = _value; // update the mirror array
+}
+
+void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne) {
+ uint8_t opcode1 = _address + 0x40; // WREG expects 010rrrrr where rrrrr = _address
+ gpio_set_pin_level(ADS1299.SS_pin, false); // open SPI
+ _transfer_byte(ADS1299.SPI_descr, opcode1); // Send WREG command & address
+ _transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne); // Send number of registers to read -1
+ for (int i=_address; i <=(_address + _numRegistersMinusOne); i++){
+ _transfer_byte(ADS1299.SPI_descr, ADS1299.reg_data[i]); // Write to the registers
+ }
+ gpio_set_pin_level(ADS1299.SS_pin, true); // close SPI
+}
+
+//read data
+void ADS1299_RDATA() { // use in Stop Read Continuous mode when DRDY goes low
+ uint8_t inByte;
+ ADS1299.stat_1 = 0; // clear the status registers
+ int nchan = 4; //assume 4 channel.
+ gpio_set_pin_level(ADS1299.SS_pin, false); // open SPI
+ _transfer_byte(ADS1299.SPI_descr, _RDATA);
+
+ for(int i=0; i<3; i++){ // read 3 byte status register (1100+LOFF_STATP+LOFF_STATN+GPIO[7:4])
+ inByte = _transfer_byte(ADS1299.SPI_descr, 0x00);
+ ADS1299.stat_1 = (ADS1299.stat_1<<8) | inByte;
+ }
+
+ for(int i = 0; i> 8 ) & 0xFF;
+ struct spi_xfer xfer;
+ xfer.rxbuf = in_buf;
+ xfer.txbuf = (uint8_t *)out_buf;
+ xfer.size = 2;
+ spi_m_sync_transfer(ADS1299.SPI_descr, &xfer);
+ wordRead = (uint16_t)((in_buf[0] << 8) | in_buf[1]);
+ return (wordRead);
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.h
new file mode 100644
index 0000000..4fddcd2
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.h
@@ -0,0 +1,113 @@
+/*
+ * ADS1299.h
+ *
+ * Created: 8/22/2021 3:25:39 PM
+ * Author: ge37vez
+ */
+
+
+#ifndef ADS1299_H_
+#define ADS1299_H_
+
+#include "atmel_start.h"
+
+#define bitRead(value, bit) (((value) >> (bit)) & 0x01)
+#define bitSet(value, bit) ((value) |= (1UL << (bit)))
+#define bitClear(value, bit) ((value) &= ~(1UL << (bit)))
+#define bitWrite(value, bit, bitvalue) ((bitvalue) ? bitSet(value, bit) : bitClear(value, bit))
+
+//SPI Command Definition Byte Assignments (Datasheet, p35)
+#define _WAKEUP 0x02 // Wake-up from standby mode
+#define _STANDBY 0x04 // Enter Standby mode
+#define _RESET 0x06 // Reset the device registers to default
+#define _START 0x08 // Start and restart (synchronize) conversions
+#define _STOP 0x0A // Stop conversion
+#define _RDATAC 0x10 // Enable Read Data Continuous mode (default mode at power-up)
+#define _SDATAC 0x11 // Stop Read Data Continuous mode
+#define _RDATA 0x12 // Read data by command; supports multiple read back
+
+//Register Addresses
+#define ID 0x00
+#define CONFIG1 0x01
+#define CONFIG2 0x02
+#define CONFIG3 0x03
+#define LOFF 0x04
+#define CH1SET 0x05
+#define CH2SET 0x06
+#define CH3SET 0x07
+#define CH4SET 0x08
+#define CH5SET 0x09
+#define CH6SET 0x0A
+#define CH7SET 0x0B
+#define CH8SET 0x0C
+#define BIAS_SENSP 0x0D
+#define BIAS_SENSN 0x0E
+#define LOFF_SENSP 0x0F
+#define LOFF_SENSN 0x10
+#define LOFF_FLIP 0x11
+#define LOFF_STATP 0x12
+#define LOFF_STATN 0x13
+#define GPIO_REG 0x14
+#define MISC1 0x15
+#define MISC2 0x16
+#define CONFIG4 0x17
+
+#define ADS_BUFFER_SIZE 9
+
+volatile int32_t _ads1299_channel_data[9];
+volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
+volatile uint8_t _ads1299_reg_data[24];
+
+/* Struct Definitions */
+volatile struct SPI_ADS1299 {
+ volatile struct spi_m_sync_descriptor *SPI_descr;
+ volatile bool data_ReadyFlag;
+ volatile uint32_t SS_pin;
+ volatile uint32_t reset_pin;
+ volatile uint8_t* reg_data;
+ volatile int32_t* channel_data;
+ volatile int16_t stat_1;
+};
+
+static volatile struct SPI_ADS1299 ADS1299 = {
+ .SPI_descr = &SPI_2,
+ .data_ReadyFlag = false,
+ .SS_pin = SPI2_SS,
+ .reset_pin = ADS_RESET,
+ .reg_data = &_ads1299_reg_data[0],
+ .channel_data = &_ads1299_channel_data[0],
+};
+
+void initialize_ads();
+void init_streaming_mode();
+
+//ADS1299 SPI Command Definitions (Datasheet, p35)
+//System Commands
+void ADS1299_WAKEUP();
+void ADS1299_STANDBY();
+void ADS1299_RESET();
+void ADS1299_START();
+void ADS1299_STOP();
+
+//Data Read Commands
+void ADS1299_RDATAC();
+void ADS1299_SDATAC();
+void ADS1299_RDATA();
+
+//Register Read/Write Commands
+uint8_t getDeviceID();
+uint8_t ADS1299_RREG(uint8_t _address);
+void ADS1299_RREGS(uint8_t _address, uint8_t _numRegistersMinusOne);
+void printRegisterName(uint8_t _address);
+void ADS1299_WREG(uint8_t _address, uint8_t _value);
+void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne);
+void printHex(uint8_t _data);
+int32_t* ADS1299_UPDATECHANNELDATA();
+
+uint8_t _transfer_byte(struct spi_m_sync_descriptor *spi, uint8_t command);
+uint16_t _transfer_word(struct spi_m_sync_descriptor *spi, uint16_t command);
+//SPI Transfer function
+
+
+
+#endif /* ADS1299_H_ */
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/RTE_Components.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/RTE_Components.h
new file mode 100644
index 0000000..bc463d5
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/RTE_Components.h
@@ -0,0 +1,54 @@
+ /**
+ * \file
+ *
+ * \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
+ *
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.
+ *
+ * \acme_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \acme_license_stop
+ *
+ * Project: Two_Motor_D51
+ * Target: ATSAMD51J18A
+ *
+ **/
+
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+#define ATMEL_START
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_adc_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_adc_config.h
new file mode 100644
index 0000000..f3597b3
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_adc_config.h
@@ -0,0 +1,595 @@
+/* Auto-generated config file hpl_adc_config.h */
+#ifndef HPL_ADC_CONFIG_H
+#define HPL_ADC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#ifndef CONF_ADC_0_ENABLE
+#define CONF_ADC_0_ENABLE 1
+#endif
+
+// Basic Configuration
+
+// Conversion Result Resolution
+// <0x0=>12-bit
+// <0x1=>16-bit (averaging must be enabled)
+// <0x2=>10-bit
+// <0x3=>8-bit
+// Defines the bit resolution for the ADC sample values (RESSEL)
+// adc_resolution
+#ifndef CONF_ADC_0_RESSEL
+#define CONF_ADC_0_RESSEL 0x0
+#endif
+
+// Reference Selection
+// <0x0=>Internal bandgap reference
+// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
+// <0x3=>VDDANA
+// <0x4=>External reference A
+// <0x5=>External reference B
+// <0x6=>External reference C
+// Select the reference for the ADC (REFSEL)
+// adc_reference
+#ifndef CONF_ADC_0_REFSEL
+#define CONF_ADC_0_REFSEL 0x0
+#endif
+
+// Prescaler configuration
+// <0x0=>Peripheral clock divided by 2
+// <0x1=>Peripheral clock divided by 4
+// <0x2=>Peripheral clock divided by 8
+// <0x3=>Peripheral clock divided by 16
+// <0x4=>Peripheral clock divided by 32
+// <0x5=>Peripheral clock divided by 64
+// <0x6=>Peripheral clock divided by 128
+// <0x7=>Peripheral clock divided by 256
+// These bits define the ADC clock relative to the peripheral clock (PRESCALER)
+// adc_prescaler
+#ifndef CONF_ADC_0_PRESCALER
+#define CONF_ADC_0_PRESCALER 0x0
+#endif
+
+// Free Running Mode
+// When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
+// adc_freerunning_mode
+#ifndef CONF_ADC_0_FREERUN
+#define CONF_ADC_0_FREERUN 0
+#endif
+
+// Differential Mode
+// In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
+// adc_differential_mode
+#ifndef CONF_ADC_0_DIFFMODE
+#define CONF_ADC_0_DIFFMODE 0
+#endif
+
+// Positive Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x08=>ADC AIN8 pin
+// <0x09=>ADC AIN9 pin
+// <0x0A=>ADC AIN10 pin
+// <0x0B=>ADC AIN11 pin
+// <0x0C=>ADC AIN12 pin
+// <0x0D=>ADC AIN13 pin
+// <0x0E=>ADC AIN14 pin
+// <0x0F=>ADC AIN15 pin
+// <0x18=>1/4 scaled core supply
+// <0x19=>1/4 Scaled VBAT Supply
+// <0x1A=>1/4 scaled I/O supply
+// <0x1B=>Bandgap voltage
+// <0x1C=>Temperature reference (PTAT)
+// <0x1D=>Temperature reference (CTAT)
+// <0x1E=>DAC Output
+// These bits define the Mux selection for the positive ADC input. (MUXPOS)
+// adc_pinmux_positive
+#ifndef CONF_ADC_0_MUXPOS
+#define CONF_ADC_0_MUXPOS 0x0
+#endif
+
+// Negative Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x18=>Internal ground
+// These bits define the Mux selection for the negative ADC input. (MUXNEG)
+// adc_pinmux_negative
+#ifndef CONF_ADC_0_MUXNEG
+#define CONF_ADC_0_MUXNEG 0x0
+#endif
+
+//
+
+// Advanced Configuration
+// adc_advanced_settings
+#ifndef CONF_ADC_0_ADVANCED
+#define CONF_ADC_0_ADVANCED 0
+#endif
+
+// Run in standby
+// Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
+// adc_arch_runstdby
+#ifndef CONF_ADC_0_RUNSTDBY
+#define CONF_ADC_0_RUNSTDBY 0
+#endif
+
+// Debug Run
+// If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
+// adc_arch_dbgrun
+#ifndef CONF_ADC_0_DBGRUN
+#define CONF_ADC_0_DBGRUN 0
+#endif
+
+// On Demand Control
+// Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
+// adc_arch_ondemand
+#ifndef CONF_ADC_0_ONDEMAND
+#define CONF_ADC_0_ONDEMAND 0
+#endif
+
+// Left-Adjusted Result
+// When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
+// adc_arch_leftadj
+#ifndef CONF_ADC_0_LEFTADJ
+#define CONF_ADC_0_LEFTADJ 0
+#endif
+
+// Reference Buffer Offset Compensation Enable
+// The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
+// adc_arch_refcomp
+#ifndef CONF_ADC_0_REFCOMP
+#define CONF_ADC_0_REFCOMP 0
+#endif
+
+// Comparator Offset Compensation Enable
+// This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
+// adc_arch_offcomp
+#ifndef CONF_ADC_0_OFFCOMP
+#define CONF_ADC_0_OFFCOMP 0
+#endif
+
+// Digital Correction Logic Enabled
+// When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
+// adc_arch_corren
+#ifndef CONF_ADC_0_CORREN
+#define CONF_ADC_0_CORREN 0
+#endif
+
+// Offset Correction Value <0-4095>
+// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
+// adc_arch_offsetcorr
+#ifndef CONF_ADC_0_OFFSETCORR
+#define CONF_ADC_0_OFFSETCORR 0
+#endif
+
+// Gain Correction Value <0-4095>
+// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
+// adc_arch_gaincorr
+#ifndef CONF_ADC_0_GAINCORR
+#define CONF_ADC_0_GAINCORR 0
+#endif
+
+// Adjusting Result / Division Coefficient <0-7>
+// These bits define the division coefficient in 2n steps. (ADJRES)
+// adc_arch_adjres
+#ifndef CONF_ADC_0_ADJRES
+#define CONF_ADC_0_ADJRES 0x0
+#endif
+
+// Number of Samples to be Collected
+// <0x0=>1 sample
+// <0x1=>2 samples
+// <0x2=>4 samples
+// <0x3=>8 samples
+// <0x4=>16 samples
+// <0x5=>32 samples
+// <0x6=>64 samples
+// <0x7=>128 samples
+// <0x8=>256 samples
+// <0x9=>512 samples
+// <0xA=>1024 samples
+// Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
+// adc_arch_samplenum
+#ifndef CONF_ADC_0_SAMPLENUM
+#define CONF_ADC_0_SAMPLENUM 0x0
+#endif
+
+// Sampling Time Length <0-63>
+// These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
+// adc_arch_samplen
+#ifndef CONF_ADC_0_SAMPLEN
+#define CONF_ADC_0_SAMPLEN 0
+#endif
+
+// Window Monitor Mode
+// <0x0=>No window mode
+// <0x1=>Mode 1: RESULT above lower threshold
+// <0x2=>Mode 2: RESULT beneath upper threshold
+// <0x3=>Mode 3: RESULT inside lower and upper threshold
+// <0x4=>Mode 4: RESULT outside lower and upper threshold
+// These bits enable and define the window monitor mode. (WINMODE)
+// adc_arch_winmode
+#ifndef CONF_ADC_0_WINMODE
+#define CONF_ADC_0_WINMODE 0x0
+#endif
+
+// Window Monitor Lower Threshold <0-65535>
+// If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
+// adc_arch_winlt
+#ifndef CONF_ADC_0_WINLT
+#define CONF_ADC_0_WINLT 0
+#endif
+
+// Window Monitor Upper Threshold <0-65535>
+// If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
+// adc_arch_winut
+#ifndef CONF_ADC_0_WINUT
+#define CONF_ADC_0_WINUT 0
+#endif
+
+// Bitmask for positive input sequence <0-4294967295>
+// Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
+// adc_arch_seqen
+#ifndef CONF_ADC_0_SEQEN
+#define CONF_ADC_0_SEQEN 0x0
+#endif
+
+//
+
+// Event Control
+// adc_arch_event_settings
+#ifndef CONF_ADC_0_EVENT_CONTROL
+#define CONF_ADC_0_EVENT_CONTROL 0
+#endif
+
+// Window Monitor Event Out
+// Enables event output on window event (WINMONEO)
+// adc_arch_winmoneo
+#ifndef CONF_ADC_0_WINMONEO
+#define CONF_ADC_0_WINMONEO 0
+#endif
+
+// Result Ready Event Out
+// Enables event output on result ready event (RESRDEO)
+// adc_arch_resrdyeo
+#ifndef CONF_ADC_0_RESRDYEO
+#define CONF_ADC_0_RESRDYEO 0
+#endif
+
+// Invert flush Event Signal
+// Invert the flush event input signal (FLUSHINV)
+// adc_arch_flushinv
+#ifndef CONF_ADC_0_FLUSHINV
+#define CONF_ADC_0_FLUSHINV 0
+#endif
+
+// Trigger Flush On Event
+// Trigger an ADC pipeline flush on event (FLUSHEI)
+// adc_arch_flushei
+#ifndef CONF_ADC_0_FLUSHEI
+#define CONF_ADC_0_FLUSHEI 0
+#endif
+
+// Invert Start Conversion Event Signal
+// Invert the start conversion event input signal (STARTINV)
+// adc_arch_startinv
+#ifndef CONF_ADC_0_STARTINV
+#define CONF_ADC_0_STARTINV 0
+#endif
+
+// Trigger Conversion On Event
+// Trigger a conversion on event. (STARTEI)
+// adc_arch_startei
+#ifndef CONF_ADC_0_STARTEI
+#define CONF_ADC_0_STARTEI 0
+#endif
+
+//
+
+#ifndef CONF_ADC_1_ENABLE
+#define CONF_ADC_1_ENABLE 1
+#endif
+
+// Basic Configuration
+
+// Conversion Result Resolution
+// <0x0=>12-bit
+// <0x1=>16-bit (averaging must be enabled)
+// <0x2=>10-bit
+// <0x3=>8-bit
+// Defines the bit resolution for the ADC sample values (RESSEL)
+// adc_resolution
+#ifndef CONF_ADC_1_RESSEL
+#define CONF_ADC_1_RESSEL 0x0
+#endif
+
+// Reference Selection
+// <0x0=>Internal bandgap reference
+// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
+// <0x3=>VDDANA
+// <0x4=>External reference A
+// <0x5=>External reference B
+// <0x6=>External reference C
+// Select the reference for the ADC (REFSEL)
+// adc_reference
+#ifndef CONF_ADC_1_REFSEL
+#define CONF_ADC_1_REFSEL 0x4
+#endif
+
+// Prescaler configuration
+// <0x0=>Peripheral clock divided by 2
+// <0x1=>Peripheral clock divided by 4
+// <0x2=>Peripheral clock divided by 8
+// <0x3=>Peripheral clock divided by 16
+// <0x4=>Peripheral clock divided by 32
+// <0x5=>Peripheral clock divided by 64
+// <0x6=>Peripheral clock divided by 128
+// <0x7=>Peripheral clock divided by 256
+// These bits define the ADC clock relative to the peripheral clock (PRESCALER)
+// adc_prescaler
+#ifndef CONF_ADC_1_PRESCALER
+#define CONF_ADC_1_PRESCALER 0x2
+#endif
+
+// Free Running Mode
+// When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
+// adc_freerunning_mode
+#ifndef CONF_ADC_1_FREERUN
+#define CONF_ADC_1_FREERUN 0
+#endif
+
+// Differential Mode
+// In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
+// adc_differential_mode
+#ifndef CONF_ADC_1_DIFFMODE
+#define CONF_ADC_1_DIFFMODE 1
+#endif
+
+// Positive Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x08=>ADC AIN8 pin
+// <0x09=>ADC AIN9 pin
+// <0x0A=>ADC AIN10 pin
+// <0x0B=>ADC AIN11 pin
+// <0x0C=>ADC AIN12 pin
+// <0x0D=>ADC AIN13 pin
+// <0x0E=>ADC AIN14 pin
+// <0x0F=>ADC AIN15 pin
+// <0x18=>1/4 scaled core supply
+// <0x19=>1/4 Scaled VBAT Supply
+// <0x1A=>1/4 scaled I/O supply
+// <0x1B=>Bandgap voltage
+// <0x1C=>Temperature reference (PTAT)
+// <0x1D=>Temperature reference (CTAT)
+// <0x1E=>DAC Output
+// These bits define the Mux selection for the positive ADC input. (MUXPOS)
+// adc_pinmux_positive
+#ifndef CONF_ADC_1_MUXPOS
+#define CONF_ADC_1_MUXPOS 0x6
+#endif
+
+// Negative Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x18=>Internal ground
+// These bits define the Mux selection for the negative ADC input. (MUXNEG)
+// adc_pinmux_negative
+#ifndef CONF_ADC_1_MUXNEG
+#define CONF_ADC_1_MUXNEG 0x0
+#endif
+
+//
+
+// Advanced Configuration
+// adc_advanced_settings
+#ifndef CONF_ADC_1_ADVANCED
+#define CONF_ADC_1_ADVANCED 1
+#endif
+
+// Run in standby
+// Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
+// adc_arch_runstdby
+#ifndef CONF_ADC_1_RUNSTDBY
+#define CONF_ADC_1_RUNSTDBY 0
+#endif
+
+// Debug Run
+// If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
+// adc_arch_dbgrun
+#ifndef CONF_ADC_1_DBGRUN
+#define CONF_ADC_1_DBGRUN 0
+#endif
+
+// On Demand Control
+// Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
+// adc_arch_ondemand
+#ifndef CONF_ADC_1_ONDEMAND
+#define CONF_ADC_1_ONDEMAND 0
+#endif
+
+// Left-Adjusted Result
+// When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
+// adc_arch_leftadj
+#ifndef CONF_ADC_1_LEFTADJ
+#define CONF_ADC_1_LEFTADJ 0
+#endif
+
+// Reference Buffer Offset Compensation Enable
+// The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
+// adc_arch_refcomp
+#ifndef CONF_ADC_1_REFCOMP
+#define CONF_ADC_1_REFCOMP 0
+#endif
+
+// Comparator Offset Compensation Enable
+// This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
+// adc_arch_offcomp
+#ifndef CONF_ADC_1_OFFCOMP
+#define CONF_ADC_1_OFFCOMP 0
+#endif
+
+// Digital Correction Logic Enabled
+// When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
+// adc_arch_corren
+#ifndef CONF_ADC_1_CORREN
+#define CONF_ADC_1_CORREN 0
+#endif
+
+// Offset Correction Value <0-4095>
+// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
+// adc_arch_offsetcorr
+#ifndef CONF_ADC_1_OFFSETCORR
+#define CONF_ADC_1_OFFSETCORR 0
+#endif
+
+// Gain Correction Value <0-4095>
+// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
+// adc_arch_gaincorr
+#ifndef CONF_ADC_1_GAINCORR
+#define CONF_ADC_1_GAINCORR 0
+#endif
+
+// Adjusting Result / Division Coefficient <0-7>
+// These bits define the division coefficient in 2n steps. (ADJRES)
+// adc_arch_adjres
+#ifndef CONF_ADC_1_ADJRES
+#define CONF_ADC_1_ADJRES 0x0
+#endif
+
+// Number of Samples to be Collected
+// <0x0=>1 sample
+// <0x1=>2 samples
+// <0x2=>4 samples
+// <0x3=>8 samples
+// <0x4=>16 samples
+// <0x5=>32 samples
+// <0x6=>64 samples
+// <0x7=>128 samples
+// <0x8=>256 samples
+// <0x9=>512 samples
+// <0xA=>1024 samples
+// Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
+// adc_arch_samplenum
+#ifndef CONF_ADC_1_SAMPLENUM
+#define CONF_ADC_1_SAMPLENUM 0x0
+#endif
+
+// Sampling Time Length <0-63>
+// These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
+// adc_arch_samplen
+#ifndef CONF_ADC_1_SAMPLEN
+#define CONF_ADC_1_SAMPLEN 2
+#endif
+
+// Window Monitor Mode
+// <0x0=>No window mode
+// <0x1=>Mode 1: RESULT above lower threshold
+// <0x2=>Mode 2: RESULT beneath upper threshold
+// <0x3=>Mode 3: RESULT inside lower and upper threshold
+// <0x4=>Mode 4: RESULT outside lower and upper threshold
+// These bits enable and define the window monitor mode. (WINMODE)
+// adc_arch_winmode
+#ifndef CONF_ADC_1_WINMODE
+#define CONF_ADC_1_WINMODE 0x0
+#endif
+
+// Window Monitor Lower Threshold <0-65535>
+// If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
+// adc_arch_winlt
+#ifndef CONF_ADC_1_WINLT
+#define CONF_ADC_1_WINLT 0
+#endif
+
+// Window Monitor Upper Threshold <0-65535>
+// If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
+// adc_arch_winut
+#ifndef CONF_ADC_1_WINUT
+#define CONF_ADC_1_WINUT 0
+#endif
+
+// Bitmask for positive input sequence <0-4294967295>
+// Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
+// adc_arch_seqen
+#ifndef CONF_ADC_1_SEQEN
+#define CONF_ADC_1_SEQEN 0x0
+#endif
+
+//
+
+// Event Control
+// adc_arch_event_settings
+#ifndef CONF_ADC_1_EVENT_CONTROL
+#define CONF_ADC_1_EVENT_CONTROL 1
+#endif
+
+// Window Monitor Event Out
+// Enables event output on window event (WINMONEO)
+// adc_arch_winmoneo
+#ifndef CONF_ADC_1_WINMONEO
+#define CONF_ADC_1_WINMONEO 0
+#endif
+
+// Result Ready Event Out
+// Enables event output on result ready event (RESRDEO)
+// adc_arch_resrdyeo
+#ifndef CONF_ADC_1_RESRDYEO
+#define CONF_ADC_1_RESRDYEO 1
+#endif
+
+// Invert flush Event Signal
+// Invert the flush event input signal (FLUSHINV)
+// adc_arch_flushinv
+#ifndef CONF_ADC_1_FLUSHINV
+#define CONF_ADC_1_FLUSHINV 0
+#endif
+
+// Trigger Flush On Event
+// Trigger an ADC pipeline flush on event (FLUSHEI)
+// adc_arch_flushei
+#ifndef CONF_ADC_1_FLUSHEI
+#define CONF_ADC_1_FLUSHEI 0
+#endif
+
+// Invert Start Conversion Event Signal
+// Invert the start conversion event input signal (STARTINV)
+// adc_arch_startinv
+#ifndef CONF_ADC_1_STARTINV
+#define CONF_ADC_1_STARTINV 0
+#endif
+
+// Trigger Conversion On Event
+// Trigger a conversion on event. (STARTEI)
+// adc_arch_startei
+#ifndef CONF_ADC_1_STARTEI
+#define CONF_ADC_1_STARTEI 0
+#endif
+
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_ADC_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_ccl_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_ccl_config.h
new file mode 100644
index 0000000..694e623
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_ccl_config.h
@@ -0,0 +1,499 @@
+/* Auto-generated config file hpl_ccl_config.h */
+#ifndef HPL_CCL_CONFIG_H
+#define HPL_CCL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Sequential Control Logic 0
+// <0x0=> Sequential logic is disabled
+// <0x1=> D flip flop
+// <0x2=> JK flip flop
+// <0x3=> D latch
+// <0x4=> RS latch
+// Selects mode for sequential module 0
+// ccl_arch_seqsel_0
+#ifndef CONF_CCL_SEQSEL_0
+#define CONF_CCL_SEQSEL_0 0x0
+#endif
+
+// Sequential Control Logic 1
+// <0x0=> Sequential logic is disabled
+// <0x1=> D flip flop
+// <0x2=> JK flip flop
+// <0x3=> D latch
+// <0x4=> RS latch
+// Selects mode for sequential module 1
+// ccl_arch_seqsel_1
+#ifndef CONF_CCL_SEQSEL_1
+#define CONF_CCL_SEQSEL_1 0x0
+#endif
+
+// Lookup Table Control 0
+// Enable and setup the lookup table module 0
+// ccl_arch_lutctrl0
+#ifndef CONF_CCL_LUTCTRL_EN_0
+#define CONF_CCL_LUTCTRL_EN_0 1
+#endif
+
+// Truth Table <0x00-0xFF>
+// Define the value of truth logic according to inputs IN[2:0]
+// ccl_arch_truth_0
+#ifndef CONF_CCL_TRUTH_0
+#define CONF_CCL_TRUTH_0 0x96
+#endif
+
+// Input Source Selection 0
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// ccl_arch_insel0_0
+#ifndef CONF_CCL_INSEL0_0
+#define CONF_CCL_INSEL0_0 0x4
+#endif
+
+// Input Source Selection 1
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// ccl_arch_insel1_0
+#ifndef CONF_CCL_INSEL1_0
+#define CONF_CCL_INSEL1_0 0x4
+#endif
+
+// Input Source Selection 2
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// ccl_arch_insel2_0
+#ifndef CONF_CCL_INSEL2_0
+#define CONF_CCL_INSEL2_0 0x4
+#endif
+
+// Edge detector enable
+// ccl_arch_edgesel_0
+#ifndef CONF_CCL_EDGESEL_0
+#define CONF_CCL_EDGESEL_0 0
+#endif
+
+// Output Filter
+// <0x0=> Disabled
+// <0x1=> Synchronizer Enabled
+// <0x2=> Filter Enabled
+// ccl_arch_filtsel_0
+#ifndef CONF_CCL_FILTSEL_0
+#define CONF_CCL_FILTSEL_0 0x0
+#endif
+
+// Event settings 0
+
+// Event output enable
+// ccl_arch_luteo_0
+#ifndef CONF_CCL_LUTEO_0
+#define CONF_CCL_LUTEO_0 1
+#endif
+
+// Event input enable
+// ccl_arch_lutei_0
+#ifndef CONF_CCL_LUTEI_0
+#define CONF_CCL_LUTEI_0 0
+#endif
+
+// Event input invert
+// ccl_arch_invei_0
+#ifndef CONF_CCL_INVEI_0
+#define CONF_CCL_INVEI_0 0
+#endif
+
+//
+
+//
+
+// Persistance settings 0
+
+// Expression Persistance
+// ccl_e_persistance_0
+#define EXPRESSION_PERSISTANCE_0 ""
+
+// Logic Persistance
+// ccl_l_persistance_0
+#define LOGIC_PERSISTANCE_0 ""
+
+//
+
+// Lookup Table Control 1
+// Enable and setup the lookup table module 1
+// ccl_arch_lutctrl1
+#ifndef CONF_CCL_LUTCTRL_EN_1
+#define CONF_CCL_LUTCTRL_EN_1 0
+#endif
+
+// Truth Table <0x00-0xFF>
+// Define the value of truth logic according to inputs IN[2:0]
+// ccl_arch_truth_1
+#ifndef CONF_CCL_TRUTH_1
+#define CONF_CCL_TRUTH_1 0x0
+#endif
+
+// Input Source Selection 0
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// ccl_arch_insel0_1
+#ifndef CONF_CCL_INSEL0_1
+#define CONF_CCL_INSEL0_1 0x4
+#endif
+
+// Input Source Selection 1
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// ccl_arch_insel1_1
+#ifndef CONF_CCL_INSEL1_1
+#define CONF_CCL_INSEL1_1 0x4
+#endif
+
+// Input Source Selection 2
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// ccl_arch_insel2_1
+#ifndef CONF_CCL_INSEL2_1
+#define CONF_CCL_INSEL2_1 0x4
+#endif
+
+// Edge detector enable
+// ccl_arch_edgesel_1
+#ifndef CONF_CCL_EDGESEL_1
+#define CONF_CCL_EDGESEL_1 0
+#endif
+
+// Output Filter
+// <0x0=> Disabled
+// <0x1=> Synchronizer Enabled
+// <0x2=> Filter Enabled
+// ccl_arch_filtsel_1
+#ifndef CONF_CCL_FILTSEL_1
+#define CONF_CCL_FILTSEL_1 0x0
+#endif
+
+// Event settings 1
+
+// Event output enable
+// ccl_arch_luteo_1
+#ifndef CONF_CCL_LUTEO_1
+#define CONF_CCL_LUTEO_1 0
+#endif
+
+// Event input enable
+// ccl_arch_lutei_1
+#ifndef CONF_CCL_LUTEI_1
+#define CONF_CCL_LUTEI_1 0
+#endif
+
+// Event input invert
+// ccl_arch_invei_1
+#ifndef CONF_CCL_INVEI_1
+#define CONF_CCL_INVEI_1 0
+#endif
+
+//
+
+//
+
+// Persistance settings 1
+
+// Expression Persistance
+// ccl_e_persistance_1
+#define EXPRESSION_PERSISTANCE_1 ""
+
+// Logic Persistance
+// ccl_l_persistance_1
+#define LOGIC_PERSISTANCE_1 ""
+
+//
+
+// Lookup Table Control 2
+// Enable and setup the lookup table module 2
+// ccl_arch_lutctrl2
+#ifndef CONF_CCL_LUTCTRL_EN_2
+#define CONF_CCL_LUTCTRL_EN_2 1
+#endif
+
+// Truth Table <0x00-0xFF>
+// Define the value of truth logic according to inputs IN[2:0]
+// ccl_arch_truth_2
+#ifndef CONF_CCL_TRUTH_2
+#define CONF_CCL_TRUTH_2 0x96
+#endif
+
+// Input Source Selection 0
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// ccl_arch_insel0_2
+#ifndef CONF_CCL_INSEL0_2
+#define CONF_CCL_INSEL0_2 0x4
+#endif
+
+// Input Source Selection 1
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// ccl_arch_insel1_2
+#ifndef CONF_CCL_INSEL1_2
+#define CONF_CCL_INSEL1_2 0x4
+#endif
+
+// Input Source Selection 2
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// ccl_arch_insel2_2
+#ifndef CONF_CCL_INSEL2_2
+#define CONF_CCL_INSEL2_2 0x4
+#endif
+
+// Edge detector enable
+// ccl_arch_edgesel_2
+#ifndef CONF_CCL_EDGESEL_2
+#define CONF_CCL_EDGESEL_2 0
+#endif
+
+// Output Filter
+// <0x0=> Disabled
+// <0x1=> Synchronizer Enabled
+// <0x2=> Filter Enabled
+// ccl_arch_filtsel_2
+#ifndef CONF_CCL_FILTSEL_2
+#define CONF_CCL_FILTSEL_2 0x0
+#endif
+
+// Event settings 2
+
+// Event output enable
+// ccl_arch_luteo_2
+#ifndef CONF_CCL_LUTEO_2
+#define CONF_CCL_LUTEO_2 1
+#endif
+
+// Event input enable
+// ccl_arch_lutei_2
+#ifndef CONF_CCL_LUTEI_2
+#define CONF_CCL_LUTEI_2 0
+#endif
+
+// Event input invert
+// ccl_arch_invei_2
+#ifndef CONF_CCL_INVEI_2
+#define CONF_CCL_INVEI_2 0
+#endif
+
+//
+
+//
+
+// Persistance settings 2
+
+// Expression Persistance
+// ccl_e_persistance_2
+#define EXPRESSION_PERSISTANCE_2 ""
+
+// Logic Persistance
+// ccl_l_persistance_2
+#define LOGIC_PERSISTANCE_2 ""
+
+//
+
+// Lookup Table Control 3
+// Enable and setup the lookup table module 3
+// ccl_arch_lutctrl3
+#ifndef CONF_CCL_LUTCTRL_EN_3
+#define CONF_CCL_LUTCTRL_EN_3 0
+#endif
+
+// Truth Table <0x00-0xFF>
+// Define the value of truth logic according to inputs IN[2:0]
+// ccl_arch_truth_3
+#ifndef CONF_CCL_TRUTH_3
+#define CONF_CCL_TRUTH_3 0x0
+#endif
+
+// Input Source Selection 0
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// ccl_arch_insel0_3
+#ifndef CONF_CCL_INSEL0_3
+#define CONF_CCL_INSEL0_3 0x4
+#endif
+
+// Input Source Selection 1
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// ccl_arch_insel1_3
+#ifndef CONF_CCL_INSEL1_3
+#define CONF_CCL_INSEL1_3 0x4
+#endif
+
+// Input Source Selection 2
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// ccl_arch_insel2_3
+#ifndef CONF_CCL_INSEL2_3
+#define CONF_CCL_INSEL2_3 0x4
+#endif
+
+// Edge detector enable
+// ccl_arch_edgesel_3
+#ifndef CONF_CCL_EDGESEL_3
+#define CONF_CCL_EDGESEL_3 0
+#endif
+
+// Output Filter
+// <0x0=> Disabled
+// <0x1=> Synchronizer Enabled
+// <0x2=> Filter Enabled
+// ccl_arch_filtsel_3
+#ifndef CONF_CCL_FILTSEL_3
+#define CONF_CCL_FILTSEL_3 0x0
+#endif
+
+// Event settings 3
+
+// Event output enable
+// ccl_arch_luteo_3
+#ifndef CONF_CCL_LUTEO_3
+#define CONF_CCL_LUTEO_3 0
+#endif
+
+// Event input enable
+// ccl_arch_lutei_3
+#ifndef CONF_CCL_LUTEI_3
+#define CONF_CCL_LUTEI_3 0
+#endif
+
+// Event input invert
+// ccl_arch_invei_3
+#ifndef CONF_CCL_INVEI_3
+#define CONF_CCL_INVEI_3 0
+#endif
+
+//
+
+//
+
+// Persistance settings 3
+
+// Expression Persistance
+// ccl_e_persistance_3
+#define EXPRESSION_PERSISTANCE_3 ""
+
+// Logic Persistance
+// ccl_l_persistance_3
+#define LOGIC_PERSISTANCE_3 ""
+
+//
+
+// Advanced configurations
+// ccl_arch_advanced_settings
+#ifndef CONF_CCL_ADVANCED
+#define CONF_CCL_ADVANCED 0
+#endif
+
+// Run in Standby
+// ccl_arch_runstdby
+#ifndef CONF_CCL_RUNSTDBY
+#define CONF_CCL_RUNSTDBY 0
+#endif
+
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_CCL_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_cmcc_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_cmcc_config.h
new file mode 100644
index 0000000..8590736
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_cmcc_config.h
@@ -0,0 +1,54 @@
+/* Auto-generated config file hpl_cmcc_config.h */
+#ifndef HPL_CMCC_CONFIG_H
+#define HPL_CMCC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Basic Configuration
+
+// Cache enable
+// Defines the cache should be enabled or not.
+// cmcc_enable
+#ifndef CONF_CMCC_ENABLE
+#define CONF_CMCC_ENABLE 0x0
+#endif
+
+// Cache Size
+// Defines the cache memory size to be configured.
+// <0x0=>1 KB
+// <0x1=>2 KB
+// <0x2=>4 KB
+// cache_size
+#ifndef CONF_CMCC_CACHE_SIZE
+#define CONF_CMCC_CACHE_SIZE 0x2
+#endif
+
+// Advanced Configuration
+// cmcc_advanced_configuration
+// Data cache disable
+// Defines the data cache should be disabled or not.
+// cmcc_data_cache_disable
+#ifndef CONF_CMCC_DATA_CACHE_DISABLE
+#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
+#endif
+
+// Instruction cache disable
+// Defines the Instruction cache should be disabled or not.
+// cmcc_inst_cache_disable
+#ifndef CONF_CMCC_INST_CACHE_DISABLE
+#define CONF_CMCC_INST_CACHE_DISABLE 0x0
+#endif
+
+// Clock Gating disable
+// Defines the clock gating should be disabled or not.
+// cmcc_clock_gating_disable
+#ifndef CONF_CMCC_CLK_GATING_DISABLE
+#define CONF_CMCC_CLK_GATING_DISABLE 0x0
+#endif
+
+//
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_CMCC_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_dmac_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_dmac_config.h
new file mode 100644
index 0000000..dbbe6bf
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_dmac_config.h
@@ -0,0 +1,7277 @@
+/* Auto-generated config file hpl_dmac_config.h */
+#ifndef HPL_DMAC_CONFIG_H
+#define HPL_DMAC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// DMAC enable
+// Indicates whether dmac is enabled or not
+// dmac_enable
+#ifndef CONF_DMAC_ENABLE
+#define CONF_DMAC_ENABLE 1
+#endif
+
+// Priority Level 0
+// Indicates whether Priority Level 0 is enabled or not
+// dmac_lvlen0
+#ifndef CONF_DMAC_LVLEN0
+#define CONF_DMAC_LVLEN0 1
+#endif
+
+// Level 0 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 0
+// <1=> Round-robin arbitration scheme for channel with priority 0
+// Defines Level 0 Arbitration for DMA channels
+// dmac_rrlvlen0
+#ifndef CONF_DMAC_RRLVLEN0
+#define CONF_DMAC_RRLVLEN0 0
+#endif
+
+// Level 0 Channel Priority Number <0x00-0xFF>
+// dmac_lvlpri0
+#ifndef CONF_DMAC_LVLPRI0
+#define CONF_DMAC_LVLPRI0 0
+#endif
+// Priority Level 1
+// Indicates whether Priority Level 1 is enabled or not
+// dmac_lvlen1
+#ifndef CONF_DMAC_LVLEN1
+#define CONF_DMAC_LVLEN1 0
+#endif
+
+// Level 1 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 1
+// <1=> Round-robin arbitration scheme for channel with priority 1
+// Defines Level 1 Arbitration for DMA channels
+// dmac_rrlvlen1
+#ifndef CONF_DMAC_RRLVLEN1
+#define CONF_DMAC_RRLVLEN1 0
+#endif
+
+// Level 1 Channel Priority Number <0x00-0xFF>
+// dmac_lvlpri1
+#ifndef CONF_DMAC_LVLPRI1
+#define CONF_DMAC_LVLPRI1 0
+#endif
+// Priority Level 2
+// Indicates whether Priority Level 2 is enabled or not
+// dmac_lvlen2
+#ifndef CONF_DMAC_LVLEN2
+#define CONF_DMAC_LVLEN2 0
+#endif
+
+// Level 2 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 2
+// <1=> Round-robin arbitration scheme for channel with priority 2
+// Defines Level 2 Arbitration for DMA channels
+// dmac_rrlvlen2
+#ifndef CONF_DMAC_RRLVLEN2
+#define CONF_DMAC_RRLVLEN2 0
+#endif
+
+// Level 2 Channel Priority Number <0x00-0xFF>
+// dmac_lvlpri2
+#ifndef CONF_DMAC_LVLPRI2
+#define CONF_DMAC_LVLPRI2 0
+#endif
+// Priority Level 3
+// Indicates whether Priority Level 3 is enabled or not
+// dmac_lvlen3
+#ifndef CONF_DMAC_LVLEN3
+#define CONF_DMAC_LVLEN3 0
+#endif
+
+// Level 3 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 3
+// <1=> Round-robin arbitration scheme for channel with priority 3
+// Defines Level 3 Arbitration for DMA channels
+// dmac_rrlvlen3
+#ifndef CONF_DMAC_RRLVLEN3
+#define CONF_DMAC_RRLVLEN3 0
+#endif
+
+// Level 3 Channel Priority Number <0x00-0xFF>
+// dmac_lvlpri3
+#ifndef CONF_DMAC_LVLPRI3
+#define CONF_DMAC_LVLPRI3 0
+#endif
+// Debug Run
+// Indicates whether Debug Run is enabled or not
+// dmac_dbgrun
+#ifndef CONF_DMAC_DBGRUN
+#define CONF_DMAC_DBGRUN 0
+#endif
+
+// Channel 0 settings
+// dmac_channel_0_settings
+#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
+#define CONF_DMAC_CHANNEL_0_SETTINGS 1
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 0 is running in standby mode or not
+// dmac_runstdby_0
+#ifndef CONF_DMAC_RUNSTDBY_0
+#define CONF_DMAC_RUNSTDBY_0 1
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_0
+#ifndef CONF_DMAC_TRIGACT_0
+#define CONF_DMAC_TRIGACT_0 2
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_0
+#ifndef CONF_DMAC_TRIGSRC_0
+#define CONF_DMAC_TRIGSRC_0 6
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_0
+#ifndef CONF_DMAC_LVL_0
+#define CONF_DMAC_LVL_0 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_0
+#ifndef CONF_DMAC_EVOE_0
+#define CONF_DMAC_EVOE_0 1
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_0
+#ifndef CONF_DMAC_EVIE_0
+#define CONF_DMAC_EVIE_0 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_0
+#ifndef CONF_DMAC_EVACT_0
+#define CONF_DMAC_EVACT_0 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_0
+#ifndef CONF_DMAC_STEPSIZE_0
+#define CONF_DMAC_STEPSIZE_0 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_0
+#ifndef CONF_DMAC_STEPSEL_0
+#define CONF_DMAC_STEPSEL_0 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_0
+#ifndef CONF_DMAC_SRCINC_0
+#define CONF_DMAC_SRCINC_0 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_0
+#ifndef CONF_DMAC_DSTINC_0
+#define CONF_DMAC_DSTINC_0 1
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_0
+#ifndef CONF_DMAC_BEATSIZE_0
+#define CONF_DMAC_BEATSIZE_0 2
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_0
+#ifndef CONF_DMAC_BLOCKACT_0
+#define CONF_DMAC_BLOCKACT_0 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_0
+#ifndef CONF_DMAC_EVOSEL_0
+#define CONF_DMAC_EVOSEL_0 1
+#endif
+//
+
+// Channel 1 settings
+// dmac_channel_1_settings
+#ifndef CONF_DMAC_CHANNEL_1_SETTINGS
+#define CONF_DMAC_CHANNEL_1_SETTINGS 1
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 1 is running in standby mode or not
+// dmac_runstdby_1
+#ifndef CONF_DMAC_RUNSTDBY_1
+#define CONF_DMAC_RUNSTDBY_1 1
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_1
+#ifndef CONF_DMAC_TRIGACT_1
+#define CONF_DMAC_TRIGACT_1 2
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_1
+#ifndef CONF_DMAC_TRIGSRC_1
+#define CONF_DMAC_TRIGSRC_1 14
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_1
+#ifndef CONF_DMAC_LVL_1
+#define CONF_DMAC_LVL_1 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_1
+#ifndef CONF_DMAC_EVOE_1
+#define CONF_DMAC_EVOE_1 1
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_1
+#ifndef CONF_DMAC_EVIE_1
+#define CONF_DMAC_EVIE_1 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_1
+#ifndef CONF_DMAC_EVACT_1
+#define CONF_DMAC_EVACT_1 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_1
+#ifndef CONF_DMAC_STEPSIZE_1
+#define CONF_DMAC_STEPSIZE_1 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_1
+#ifndef CONF_DMAC_STEPSEL_1
+#define CONF_DMAC_STEPSEL_1 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_1
+#ifndef CONF_DMAC_SRCINC_1
+#define CONF_DMAC_SRCINC_1 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_1
+#ifndef CONF_DMAC_DSTINC_1
+#define CONF_DMAC_DSTINC_1 1
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_1
+#ifndef CONF_DMAC_BEATSIZE_1
+#define CONF_DMAC_BEATSIZE_1 2
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_1
+#ifndef CONF_DMAC_BLOCKACT_1
+#define CONF_DMAC_BLOCKACT_1 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_1
+#ifndef CONF_DMAC_EVOSEL_1
+#define CONF_DMAC_EVOSEL_1 1
+#endif
+//
+
+// Channel 2 settings
+// dmac_channel_2_settings
+#ifndef CONF_DMAC_CHANNEL_2_SETTINGS
+#define CONF_DMAC_CHANNEL_2_SETTINGS 1
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 2 is running in standby mode or not
+// dmac_runstdby_2
+#ifndef CONF_DMAC_RUNSTDBY_2
+#define CONF_DMAC_RUNSTDBY_2 1
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_2
+#ifndef CONF_DMAC_TRIGACT_2
+#define CONF_DMAC_TRIGACT_2 2
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_2
+#ifndef CONF_DMAC_TRIGSRC_2
+#define CONF_DMAC_TRIGSRC_2 8
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_2
+#ifndef CONF_DMAC_LVL_2
+#define CONF_DMAC_LVL_2 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_2
+#ifndef CONF_DMAC_EVOE_2
+#define CONF_DMAC_EVOE_2 1
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_2
+#ifndef CONF_DMAC_EVIE_2
+#define CONF_DMAC_EVIE_2 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_2
+#ifndef CONF_DMAC_EVACT_2
+#define CONF_DMAC_EVACT_2 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_2
+#ifndef CONF_DMAC_STEPSIZE_2
+#define CONF_DMAC_STEPSIZE_2 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_2
+#ifndef CONF_DMAC_STEPSEL_2
+#define CONF_DMAC_STEPSEL_2 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_2
+#ifndef CONF_DMAC_SRCINC_2
+#define CONF_DMAC_SRCINC_2 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_2
+#ifndef CONF_DMAC_DSTINC_2
+#define CONF_DMAC_DSTINC_2 1
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_2
+#ifndef CONF_DMAC_BEATSIZE_2
+#define CONF_DMAC_BEATSIZE_2 2
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_2
+#ifndef CONF_DMAC_BLOCKACT_2
+#define CONF_DMAC_BLOCKACT_2 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_2
+#ifndef CONF_DMAC_EVOSEL_2
+#define CONF_DMAC_EVOSEL_2 1
+#endif
+//
+
+// Channel 3 settings
+// dmac_channel_3_settings
+#ifndef CONF_DMAC_CHANNEL_3_SETTINGS
+#define CONF_DMAC_CHANNEL_3_SETTINGS 1
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 3 is running in standby mode or not
+// dmac_runstdby_3
+#ifndef CONF_DMAC_RUNSTDBY_3
+#define CONF_DMAC_RUNSTDBY_3 1
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_3
+#ifndef CONF_DMAC_TRIGACT_3
+#define CONF_DMAC_TRIGACT_3 2
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_3
+#ifndef CONF_DMAC_TRIGSRC_3
+#define CONF_DMAC_TRIGSRC_3 70
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_3
+#ifndef CONF_DMAC_LVL_3
+#define CONF_DMAC_LVL_3 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_3
+#ifndef CONF_DMAC_EVOE_3
+#define CONF_DMAC_EVOE_3 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_3
+#ifndef CONF_DMAC_EVIE_3
+#define CONF_DMAC_EVIE_3 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_3
+#ifndef CONF_DMAC_EVACT_3
+#define CONF_DMAC_EVACT_3 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_3
+#ifndef CONF_DMAC_STEPSIZE_3
+#define CONF_DMAC_STEPSIZE_3 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_3
+#ifndef CONF_DMAC_STEPSEL_3
+#define CONF_DMAC_STEPSEL_3 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_3
+#ifndef CONF_DMAC_SRCINC_3
+#define CONF_DMAC_SRCINC_3 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_3
+#ifndef CONF_DMAC_DSTINC_3
+#define CONF_DMAC_DSTINC_3 1
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_3
+#ifndef CONF_DMAC_BEATSIZE_3
+#define CONF_DMAC_BEATSIZE_3 1
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_3
+#ifndef CONF_DMAC_BLOCKACT_3
+#define CONF_DMAC_BLOCKACT_3 1
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_3
+#ifndef CONF_DMAC_EVOSEL_3
+#define CONF_DMAC_EVOSEL_3 0
+#endif
+//
+
+// Channel 4 settings
+// dmac_channel_4_settings
+#ifndef CONF_DMAC_CHANNEL_4_SETTINGS
+#define CONF_DMAC_CHANNEL_4_SETTINGS 1
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 4 is running in standby mode or not
+// dmac_runstdby_4
+#ifndef CONF_DMAC_RUNSTDBY_4
+#define CONF_DMAC_RUNSTDBY_4 1
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_4
+#ifndef CONF_DMAC_TRIGACT_4
+#define CONF_DMAC_TRIGACT_4 2
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_4
+#ifndef CONF_DMAC_TRIGSRC_4
+#define CONF_DMAC_TRIGSRC_4 71
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_4
+#ifndef CONF_DMAC_LVL_4
+#define CONF_DMAC_LVL_4 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_4
+#ifndef CONF_DMAC_EVOE_4
+#define CONF_DMAC_EVOE_4 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_4
+#ifndef CONF_DMAC_EVIE_4
+#define CONF_DMAC_EVIE_4 1
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_4
+#ifndef CONF_DMAC_EVACT_4
+#define CONF_DMAC_EVACT_4 5
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_4
+#ifndef CONF_DMAC_STEPSIZE_4
+#define CONF_DMAC_STEPSIZE_4 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_4
+#ifndef CONF_DMAC_STEPSEL_4
+#define CONF_DMAC_STEPSEL_4 1
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_4
+#ifndef CONF_DMAC_SRCINC_4
+#define CONF_DMAC_SRCINC_4 1
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_4
+#ifndef CONF_DMAC_DSTINC_4
+#define CONF_DMAC_DSTINC_4 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_4
+#ifndef CONF_DMAC_BEATSIZE_4
+#define CONF_DMAC_BEATSIZE_4 2
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_4
+#ifndef CONF_DMAC_BLOCKACT_4
+#define CONF_DMAC_BLOCKACT_4 2
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_4
+#ifndef CONF_DMAC_EVOSEL_4
+#define CONF_DMAC_EVOSEL_4 0
+#endif
+//
+
+// Channel 5 settings
+// dmac_channel_5_settings
+#ifndef CONF_DMAC_CHANNEL_5_SETTINGS
+#define CONF_DMAC_CHANNEL_5_SETTINGS 1
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 5 is running in standby mode or not
+// dmac_runstdby_5
+#ifndef CONF_DMAC_RUNSTDBY_5
+#define CONF_DMAC_RUNSTDBY_5 1
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_5
+#ifndef CONF_DMAC_TRIGACT_5
+#define CONF_DMAC_TRIGACT_5 2
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_5
+#ifndef CONF_DMAC_TRIGSRC_5
+#define CONF_DMAC_TRIGSRC_5 9
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_5
+#ifndef CONF_DMAC_LVL_5
+#define CONF_DMAC_LVL_5 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_5
+#ifndef CONF_DMAC_EVOE_5
+#define CONF_DMAC_EVOE_5 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_5
+#ifndef CONF_DMAC_EVIE_5
+#define CONF_DMAC_EVIE_5 1
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_5
+#ifndef CONF_DMAC_EVACT_5
+#define CONF_DMAC_EVACT_5 5
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_5
+#ifndef CONF_DMAC_STEPSIZE_5
+#define CONF_DMAC_STEPSIZE_5 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_5
+#ifndef CONF_DMAC_STEPSEL_5
+#define CONF_DMAC_STEPSEL_5 1
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_5
+#ifndef CONF_DMAC_SRCINC_5
+#define CONF_DMAC_SRCINC_5 1
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_5
+#ifndef CONF_DMAC_DSTINC_5
+#define CONF_DMAC_DSTINC_5 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_5
+#ifndef CONF_DMAC_BEATSIZE_5
+#define CONF_DMAC_BEATSIZE_5 2
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_5
+#ifndef CONF_DMAC_BLOCKACT_5
+#define CONF_DMAC_BLOCKACT_5 2
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_5
+#ifndef CONF_DMAC_EVOSEL_5
+#define CONF_DMAC_EVOSEL_5 0
+#endif
+//
+
+// Channel 6 settings
+// dmac_channel_6_settings
+#ifndef CONF_DMAC_CHANNEL_6_SETTINGS
+#define CONF_DMAC_CHANNEL_6_SETTINGS 1
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 6 is running in standby mode or not
+// dmac_runstdby_6
+#ifndef CONF_DMAC_RUNSTDBY_6
+#define CONF_DMAC_RUNSTDBY_6 1
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_6
+#ifndef CONF_DMAC_TRIGACT_6
+#define CONF_DMAC_TRIGACT_6 2
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_6
+#ifndef CONF_DMAC_TRIGSRC_6
+#define CONF_DMAC_TRIGSRC_6 15
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_6
+#ifndef CONF_DMAC_LVL_6
+#define CONF_DMAC_LVL_6 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_6
+#ifndef CONF_DMAC_EVOE_6
+#define CONF_DMAC_EVOE_6 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_6
+#ifndef CONF_DMAC_EVIE_6
+#define CONF_DMAC_EVIE_6 1
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_6
+#ifndef CONF_DMAC_EVACT_6
+#define CONF_DMAC_EVACT_6 5
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_6
+#ifndef CONF_DMAC_STEPSIZE_6
+#define CONF_DMAC_STEPSIZE_6 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_6
+#ifndef CONF_DMAC_STEPSEL_6
+#define CONF_DMAC_STEPSEL_6 1
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_6
+#ifndef CONF_DMAC_SRCINC_6
+#define CONF_DMAC_SRCINC_6 1
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_6
+#ifndef CONF_DMAC_DSTINC_6
+#define CONF_DMAC_DSTINC_6 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_6
+#ifndef CONF_DMAC_BEATSIZE_6
+#define CONF_DMAC_BEATSIZE_6 2
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_6
+#ifndef CONF_DMAC_BLOCKACT_6
+#define CONF_DMAC_BLOCKACT_6 2
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_6
+#ifndef CONF_DMAC_EVOSEL_6
+#define CONF_DMAC_EVOSEL_6 0
+#endif
+//
+
+// Channel 7 settings
+// dmac_channel_7_settings
+#ifndef CONF_DMAC_CHANNEL_7_SETTINGS
+#define CONF_DMAC_CHANNEL_7_SETTINGS 1
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 7 is running in standby mode or not
+// dmac_runstdby_7
+#ifndef CONF_DMAC_RUNSTDBY_7
+#define CONF_DMAC_RUNSTDBY_7 1
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_7
+#ifndef CONF_DMAC_TRIGACT_7
+#define CONF_DMAC_TRIGACT_7 2
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_7
+#ifndef CONF_DMAC_TRIGSRC_7
+#define CONF_DMAC_TRIGSRC_7 7
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_7
+#ifndef CONF_DMAC_LVL_7
+#define CONF_DMAC_LVL_7 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_7
+#ifndef CONF_DMAC_EVOE_7
+#define CONF_DMAC_EVOE_7 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_7
+#ifndef CONF_DMAC_EVIE_7
+#define CONF_DMAC_EVIE_7 1
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_7
+#ifndef CONF_DMAC_EVACT_7
+#define CONF_DMAC_EVACT_7 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_7
+#ifndef CONF_DMAC_STEPSIZE_7
+#define CONF_DMAC_STEPSIZE_7 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_7
+#ifndef CONF_DMAC_STEPSEL_7
+#define CONF_DMAC_STEPSEL_7 1
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_7
+#ifndef CONF_DMAC_SRCINC_7
+#define CONF_DMAC_SRCINC_7 1
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_7
+#ifndef CONF_DMAC_DSTINC_7
+#define CONF_DMAC_DSTINC_7 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_7
+#ifndef CONF_DMAC_BEATSIZE_7
+#define CONF_DMAC_BEATSIZE_7 2
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_7
+#ifndef CONF_DMAC_BLOCKACT_7
+#define CONF_DMAC_BLOCKACT_7 2
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_7
+#ifndef CONF_DMAC_EVOSEL_7
+#define CONF_DMAC_EVOSEL_7 0
+#endif
+//
+
+// Channel 8 settings
+// dmac_channel_8_settings
+#ifndef CONF_DMAC_CHANNEL_8_SETTINGS
+#define CONF_DMAC_CHANNEL_8_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 8 is running in standby mode or not
+// dmac_runstdby_8
+#ifndef CONF_DMAC_RUNSTDBY_8
+#define CONF_DMAC_RUNSTDBY_8 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_8
+#ifndef CONF_DMAC_TRIGACT_8
+#define CONF_DMAC_TRIGACT_8 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_8
+#ifndef CONF_DMAC_TRIGSRC_8
+#define CONF_DMAC_TRIGSRC_8 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_8
+#ifndef CONF_DMAC_LVL_8
+#define CONF_DMAC_LVL_8 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_8
+#ifndef CONF_DMAC_EVOE_8
+#define CONF_DMAC_EVOE_8 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_8
+#ifndef CONF_DMAC_EVIE_8
+#define CONF_DMAC_EVIE_8 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_8
+#ifndef CONF_DMAC_EVACT_8
+#define CONF_DMAC_EVACT_8 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_8
+#ifndef CONF_DMAC_STEPSIZE_8
+#define CONF_DMAC_STEPSIZE_8 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_8
+#ifndef CONF_DMAC_STEPSEL_8
+#define CONF_DMAC_STEPSEL_8 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_8
+#ifndef CONF_DMAC_SRCINC_8
+#define CONF_DMAC_SRCINC_8 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_8
+#ifndef CONF_DMAC_DSTINC_8
+#define CONF_DMAC_DSTINC_8 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_8
+#ifndef CONF_DMAC_BEATSIZE_8
+#define CONF_DMAC_BEATSIZE_8 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_8
+#ifndef CONF_DMAC_BLOCKACT_8
+#define CONF_DMAC_BLOCKACT_8 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_8
+#ifndef CONF_DMAC_EVOSEL_8
+#define CONF_DMAC_EVOSEL_8 0
+#endif
+//
+
+// Channel 9 settings
+// dmac_channel_9_settings
+#ifndef CONF_DMAC_CHANNEL_9_SETTINGS
+#define CONF_DMAC_CHANNEL_9_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 9 is running in standby mode or not
+// dmac_runstdby_9
+#ifndef CONF_DMAC_RUNSTDBY_9
+#define CONF_DMAC_RUNSTDBY_9 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_9
+#ifndef CONF_DMAC_TRIGACT_9
+#define CONF_DMAC_TRIGACT_9 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_9
+#ifndef CONF_DMAC_TRIGSRC_9
+#define CONF_DMAC_TRIGSRC_9 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_9
+#ifndef CONF_DMAC_LVL_9
+#define CONF_DMAC_LVL_9 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_9
+#ifndef CONF_DMAC_EVOE_9
+#define CONF_DMAC_EVOE_9 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_9
+#ifndef CONF_DMAC_EVIE_9
+#define CONF_DMAC_EVIE_9 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_9
+#ifndef CONF_DMAC_EVACT_9
+#define CONF_DMAC_EVACT_9 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_9
+#ifndef CONF_DMAC_STEPSIZE_9
+#define CONF_DMAC_STEPSIZE_9 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_9
+#ifndef CONF_DMAC_STEPSEL_9
+#define CONF_DMAC_STEPSEL_9 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_9
+#ifndef CONF_DMAC_SRCINC_9
+#define CONF_DMAC_SRCINC_9 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_9
+#ifndef CONF_DMAC_DSTINC_9
+#define CONF_DMAC_DSTINC_9 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_9
+#ifndef CONF_DMAC_BEATSIZE_9
+#define CONF_DMAC_BEATSIZE_9 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_9
+#ifndef CONF_DMAC_BLOCKACT_9
+#define CONF_DMAC_BLOCKACT_9 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_9
+#ifndef CONF_DMAC_EVOSEL_9
+#define CONF_DMAC_EVOSEL_9 0
+#endif
+//
+
+// Channel 10 settings
+// dmac_channel_10_settings
+#ifndef CONF_DMAC_CHANNEL_10_SETTINGS
+#define CONF_DMAC_CHANNEL_10_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 10 is running in standby mode or not
+// dmac_runstdby_10
+#ifndef CONF_DMAC_RUNSTDBY_10
+#define CONF_DMAC_RUNSTDBY_10 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_10
+#ifndef CONF_DMAC_TRIGACT_10
+#define CONF_DMAC_TRIGACT_10 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_10
+#ifndef CONF_DMAC_TRIGSRC_10
+#define CONF_DMAC_TRIGSRC_10 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_10
+#ifndef CONF_DMAC_LVL_10
+#define CONF_DMAC_LVL_10 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_10
+#ifndef CONF_DMAC_EVOE_10
+#define CONF_DMAC_EVOE_10 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_10
+#ifndef CONF_DMAC_EVIE_10
+#define CONF_DMAC_EVIE_10 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_10
+#ifndef CONF_DMAC_EVACT_10
+#define CONF_DMAC_EVACT_10 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_10
+#ifndef CONF_DMAC_STEPSIZE_10
+#define CONF_DMAC_STEPSIZE_10 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_10
+#ifndef CONF_DMAC_STEPSEL_10
+#define CONF_DMAC_STEPSEL_10 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_10
+#ifndef CONF_DMAC_SRCINC_10
+#define CONF_DMAC_SRCINC_10 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_10
+#ifndef CONF_DMAC_DSTINC_10
+#define CONF_DMAC_DSTINC_10 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_10
+#ifndef CONF_DMAC_BEATSIZE_10
+#define CONF_DMAC_BEATSIZE_10 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_10
+#ifndef CONF_DMAC_BLOCKACT_10
+#define CONF_DMAC_BLOCKACT_10 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_10
+#ifndef CONF_DMAC_EVOSEL_10
+#define CONF_DMAC_EVOSEL_10 0
+#endif
+//
+
+// Channel 11 settings
+// dmac_channel_11_settings
+#ifndef CONF_DMAC_CHANNEL_11_SETTINGS
+#define CONF_DMAC_CHANNEL_11_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 11 is running in standby mode or not
+// dmac_runstdby_11
+#ifndef CONF_DMAC_RUNSTDBY_11
+#define CONF_DMAC_RUNSTDBY_11 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_11
+#ifndef CONF_DMAC_TRIGACT_11
+#define CONF_DMAC_TRIGACT_11 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_11
+#ifndef CONF_DMAC_TRIGSRC_11
+#define CONF_DMAC_TRIGSRC_11 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_11
+#ifndef CONF_DMAC_LVL_11
+#define CONF_DMAC_LVL_11 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_11
+#ifndef CONF_DMAC_EVOE_11
+#define CONF_DMAC_EVOE_11 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_11
+#ifndef CONF_DMAC_EVIE_11
+#define CONF_DMAC_EVIE_11 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_11
+#ifndef CONF_DMAC_EVACT_11
+#define CONF_DMAC_EVACT_11 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_11
+#ifndef CONF_DMAC_STEPSIZE_11
+#define CONF_DMAC_STEPSIZE_11 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_11
+#ifndef CONF_DMAC_STEPSEL_11
+#define CONF_DMAC_STEPSEL_11 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_11
+#ifndef CONF_DMAC_SRCINC_11
+#define CONF_DMAC_SRCINC_11 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_11
+#ifndef CONF_DMAC_DSTINC_11
+#define CONF_DMAC_DSTINC_11 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_11
+#ifndef CONF_DMAC_BEATSIZE_11
+#define CONF_DMAC_BEATSIZE_11 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_11
+#ifndef CONF_DMAC_BLOCKACT_11
+#define CONF_DMAC_BLOCKACT_11 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_11
+#ifndef CONF_DMAC_EVOSEL_11
+#define CONF_DMAC_EVOSEL_11 0
+#endif
+//
+
+// Channel 12 settings
+// dmac_channel_12_settings
+#ifndef CONF_DMAC_CHANNEL_12_SETTINGS
+#define CONF_DMAC_CHANNEL_12_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 12 is running in standby mode or not
+// dmac_runstdby_12
+#ifndef CONF_DMAC_RUNSTDBY_12
+#define CONF_DMAC_RUNSTDBY_12 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_12
+#ifndef CONF_DMAC_TRIGACT_12
+#define CONF_DMAC_TRIGACT_12 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_12
+#ifndef CONF_DMAC_TRIGSRC_12
+#define CONF_DMAC_TRIGSRC_12 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_12
+#ifndef CONF_DMAC_LVL_12
+#define CONF_DMAC_LVL_12 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_12
+#ifndef CONF_DMAC_EVOE_12
+#define CONF_DMAC_EVOE_12 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_12
+#ifndef CONF_DMAC_EVIE_12
+#define CONF_DMAC_EVIE_12 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_12
+#ifndef CONF_DMAC_EVACT_12
+#define CONF_DMAC_EVACT_12 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_12
+#ifndef CONF_DMAC_STEPSIZE_12
+#define CONF_DMAC_STEPSIZE_12 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_12
+#ifndef CONF_DMAC_STEPSEL_12
+#define CONF_DMAC_STEPSEL_12 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_12
+#ifndef CONF_DMAC_SRCINC_12
+#define CONF_DMAC_SRCINC_12 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_12
+#ifndef CONF_DMAC_DSTINC_12
+#define CONF_DMAC_DSTINC_12 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_12
+#ifndef CONF_DMAC_BEATSIZE_12
+#define CONF_DMAC_BEATSIZE_12 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_12
+#ifndef CONF_DMAC_BLOCKACT_12
+#define CONF_DMAC_BLOCKACT_12 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_12
+#ifndef CONF_DMAC_EVOSEL_12
+#define CONF_DMAC_EVOSEL_12 0
+#endif
+//
+
+// Channel 13 settings
+// dmac_channel_13_settings
+#ifndef CONF_DMAC_CHANNEL_13_SETTINGS
+#define CONF_DMAC_CHANNEL_13_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 13 is running in standby mode or not
+// dmac_runstdby_13
+#ifndef CONF_DMAC_RUNSTDBY_13
+#define CONF_DMAC_RUNSTDBY_13 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_13
+#ifndef CONF_DMAC_TRIGACT_13
+#define CONF_DMAC_TRIGACT_13 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_13
+#ifndef CONF_DMAC_TRIGSRC_13
+#define CONF_DMAC_TRIGSRC_13 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_13
+#ifndef CONF_DMAC_LVL_13
+#define CONF_DMAC_LVL_13 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_13
+#ifndef CONF_DMAC_EVOE_13
+#define CONF_DMAC_EVOE_13 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_13
+#ifndef CONF_DMAC_EVIE_13
+#define CONF_DMAC_EVIE_13 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_13
+#ifndef CONF_DMAC_EVACT_13
+#define CONF_DMAC_EVACT_13 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_13
+#ifndef CONF_DMAC_STEPSIZE_13
+#define CONF_DMAC_STEPSIZE_13 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_13
+#ifndef CONF_DMAC_STEPSEL_13
+#define CONF_DMAC_STEPSEL_13 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_13
+#ifndef CONF_DMAC_SRCINC_13
+#define CONF_DMAC_SRCINC_13 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_13
+#ifndef CONF_DMAC_DSTINC_13
+#define CONF_DMAC_DSTINC_13 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_13
+#ifndef CONF_DMAC_BEATSIZE_13
+#define CONF_DMAC_BEATSIZE_13 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_13
+#ifndef CONF_DMAC_BLOCKACT_13
+#define CONF_DMAC_BLOCKACT_13 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_13
+#ifndef CONF_DMAC_EVOSEL_13
+#define CONF_DMAC_EVOSEL_13 0
+#endif
+//
+
+// Channel 14 settings
+// dmac_channel_14_settings
+#ifndef CONF_DMAC_CHANNEL_14_SETTINGS
+#define CONF_DMAC_CHANNEL_14_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 14 is running in standby mode or not
+// dmac_runstdby_14
+#ifndef CONF_DMAC_RUNSTDBY_14
+#define CONF_DMAC_RUNSTDBY_14 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_14
+#ifndef CONF_DMAC_TRIGACT_14
+#define CONF_DMAC_TRIGACT_14 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_14
+#ifndef CONF_DMAC_TRIGSRC_14
+#define CONF_DMAC_TRIGSRC_14 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_14
+#ifndef CONF_DMAC_LVL_14
+#define CONF_DMAC_LVL_14 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_14
+#ifndef CONF_DMAC_EVOE_14
+#define CONF_DMAC_EVOE_14 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_14
+#ifndef CONF_DMAC_EVIE_14
+#define CONF_DMAC_EVIE_14 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_14
+#ifndef CONF_DMAC_EVACT_14
+#define CONF_DMAC_EVACT_14 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_14
+#ifndef CONF_DMAC_STEPSIZE_14
+#define CONF_DMAC_STEPSIZE_14 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_14
+#ifndef CONF_DMAC_STEPSEL_14
+#define CONF_DMAC_STEPSEL_14 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_14
+#ifndef CONF_DMAC_SRCINC_14
+#define CONF_DMAC_SRCINC_14 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_14
+#ifndef CONF_DMAC_DSTINC_14
+#define CONF_DMAC_DSTINC_14 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_14
+#ifndef CONF_DMAC_BEATSIZE_14
+#define CONF_DMAC_BEATSIZE_14 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_14
+#ifndef CONF_DMAC_BLOCKACT_14
+#define CONF_DMAC_BLOCKACT_14 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_14
+#ifndef CONF_DMAC_EVOSEL_14
+#define CONF_DMAC_EVOSEL_14 0
+#endif
+//
+
+// Channel 15 settings
+// dmac_channel_15_settings
+#ifndef CONF_DMAC_CHANNEL_15_SETTINGS
+#define CONF_DMAC_CHANNEL_15_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 15 is running in standby mode or not
+// dmac_runstdby_15
+#ifndef CONF_DMAC_RUNSTDBY_15
+#define CONF_DMAC_RUNSTDBY_15 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_15
+#ifndef CONF_DMAC_TRIGACT_15
+#define CONF_DMAC_TRIGACT_15 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_15
+#ifndef CONF_DMAC_TRIGSRC_15
+#define CONF_DMAC_TRIGSRC_15 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_15
+#ifndef CONF_DMAC_LVL_15
+#define CONF_DMAC_LVL_15 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_15
+#ifndef CONF_DMAC_EVOE_15
+#define CONF_DMAC_EVOE_15 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_15
+#ifndef CONF_DMAC_EVIE_15
+#define CONF_DMAC_EVIE_15 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_15
+#ifndef CONF_DMAC_EVACT_15
+#define CONF_DMAC_EVACT_15 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_15
+#ifndef CONF_DMAC_STEPSIZE_15
+#define CONF_DMAC_STEPSIZE_15 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_15
+#ifndef CONF_DMAC_STEPSEL_15
+#define CONF_DMAC_STEPSEL_15 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_15
+#ifndef CONF_DMAC_SRCINC_15
+#define CONF_DMAC_SRCINC_15 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_15
+#ifndef CONF_DMAC_DSTINC_15
+#define CONF_DMAC_DSTINC_15 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_15
+#ifndef CONF_DMAC_BEATSIZE_15
+#define CONF_DMAC_BEATSIZE_15 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_15
+#ifndef CONF_DMAC_BLOCKACT_15
+#define CONF_DMAC_BLOCKACT_15 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_15
+#ifndef CONF_DMAC_EVOSEL_15
+#define CONF_DMAC_EVOSEL_15 0
+#endif
+//
+
+// Channel 16 settings
+// dmac_channel_16_settings
+#ifndef CONF_DMAC_CHANNEL_16_SETTINGS
+#define CONF_DMAC_CHANNEL_16_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 16 is running in standby mode or not
+// dmac_runstdby_16
+#ifndef CONF_DMAC_RUNSTDBY_16
+#define CONF_DMAC_RUNSTDBY_16 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_16
+#ifndef CONF_DMAC_TRIGACT_16
+#define CONF_DMAC_TRIGACT_16 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_16
+#ifndef CONF_DMAC_TRIGSRC_16
+#define CONF_DMAC_TRIGSRC_16 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_16
+#ifndef CONF_DMAC_LVL_16
+#define CONF_DMAC_LVL_16 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_16
+#ifndef CONF_DMAC_EVOE_16
+#define CONF_DMAC_EVOE_16 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_16
+#ifndef CONF_DMAC_EVIE_16
+#define CONF_DMAC_EVIE_16 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_16
+#ifndef CONF_DMAC_EVACT_16
+#define CONF_DMAC_EVACT_16 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_16
+#ifndef CONF_DMAC_STEPSIZE_16
+#define CONF_DMAC_STEPSIZE_16 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_16
+#ifndef CONF_DMAC_STEPSEL_16
+#define CONF_DMAC_STEPSEL_16 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_16
+#ifndef CONF_DMAC_SRCINC_16
+#define CONF_DMAC_SRCINC_16 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_16
+#ifndef CONF_DMAC_DSTINC_16
+#define CONF_DMAC_DSTINC_16 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_16
+#ifndef CONF_DMAC_BEATSIZE_16
+#define CONF_DMAC_BEATSIZE_16 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_16
+#ifndef CONF_DMAC_BLOCKACT_16
+#define CONF_DMAC_BLOCKACT_16 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_16
+#ifndef CONF_DMAC_EVOSEL_16
+#define CONF_DMAC_EVOSEL_16 0
+#endif
+//
+
+// Channel 17 settings
+// dmac_channel_17_settings
+#ifndef CONF_DMAC_CHANNEL_17_SETTINGS
+#define CONF_DMAC_CHANNEL_17_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 17 is running in standby mode or not
+// dmac_runstdby_17
+#ifndef CONF_DMAC_RUNSTDBY_17
+#define CONF_DMAC_RUNSTDBY_17 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_17
+#ifndef CONF_DMAC_TRIGACT_17
+#define CONF_DMAC_TRIGACT_17 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_17
+#ifndef CONF_DMAC_TRIGSRC_17
+#define CONF_DMAC_TRIGSRC_17 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_17
+#ifndef CONF_DMAC_LVL_17
+#define CONF_DMAC_LVL_17 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_17
+#ifndef CONF_DMAC_EVOE_17
+#define CONF_DMAC_EVOE_17 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_17
+#ifndef CONF_DMAC_EVIE_17
+#define CONF_DMAC_EVIE_17 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_17
+#ifndef CONF_DMAC_EVACT_17
+#define CONF_DMAC_EVACT_17 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_17
+#ifndef CONF_DMAC_STEPSIZE_17
+#define CONF_DMAC_STEPSIZE_17 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_17
+#ifndef CONF_DMAC_STEPSEL_17
+#define CONF_DMAC_STEPSEL_17 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_17
+#ifndef CONF_DMAC_SRCINC_17
+#define CONF_DMAC_SRCINC_17 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_17
+#ifndef CONF_DMAC_DSTINC_17
+#define CONF_DMAC_DSTINC_17 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_17
+#ifndef CONF_DMAC_BEATSIZE_17
+#define CONF_DMAC_BEATSIZE_17 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_17
+#ifndef CONF_DMAC_BLOCKACT_17
+#define CONF_DMAC_BLOCKACT_17 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_17
+#ifndef CONF_DMAC_EVOSEL_17
+#define CONF_DMAC_EVOSEL_17 0
+#endif
+//
+
+// Channel 18 settings
+// dmac_channel_18_settings
+#ifndef CONF_DMAC_CHANNEL_18_SETTINGS
+#define CONF_DMAC_CHANNEL_18_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 18 is running in standby mode or not
+// dmac_runstdby_18
+#ifndef CONF_DMAC_RUNSTDBY_18
+#define CONF_DMAC_RUNSTDBY_18 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_18
+#ifndef CONF_DMAC_TRIGACT_18
+#define CONF_DMAC_TRIGACT_18 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_18
+#ifndef CONF_DMAC_TRIGSRC_18
+#define CONF_DMAC_TRIGSRC_18 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_18
+#ifndef CONF_DMAC_LVL_18
+#define CONF_DMAC_LVL_18 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_18
+#ifndef CONF_DMAC_EVOE_18
+#define CONF_DMAC_EVOE_18 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_18
+#ifndef CONF_DMAC_EVIE_18
+#define CONF_DMAC_EVIE_18 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_18
+#ifndef CONF_DMAC_EVACT_18
+#define CONF_DMAC_EVACT_18 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_18
+#ifndef CONF_DMAC_STEPSIZE_18
+#define CONF_DMAC_STEPSIZE_18 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_18
+#ifndef CONF_DMAC_STEPSEL_18
+#define CONF_DMAC_STEPSEL_18 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_18
+#ifndef CONF_DMAC_SRCINC_18
+#define CONF_DMAC_SRCINC_18 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_18
+#ifndef CONF_DMAC_DSTINC_18
+#define CONF_DMAC_DSTINC_18 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_18
+#ifndef CONF_DMAC_BEATSIZE_18
+#define CONF_DMAC_BEATSIZE_18 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_18
+#ifndef CONF_DMAC_BLOCKACT_18
+#define CONF_DMAC_BLOCKACT_18 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_18
+#ifndef CONF_DMAC_EVOSEL_18
+#define CONF_DMAC_EVOSEL_18 0
+#endif
+//
+
+// Channel 19 settings
+// dmac_channel_19_settings
+#ifndef CONF_DMAC_CHANNEL_19_SETTINGS
+#define CONF_DMAC_CHANNEL_19_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 19 is running in standby mode or not
+// dmac_runstdby_19
+#ifndef CONF_DMAC_RUNSTDBY_19
+#define CONF_DMAC_RUNSTDBY_19 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_19
+#ifndef CONF_DMAC_TRIGACT_19
+#define CONF_DMAC_TRIGACT_19 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_19
+#ifndef CONF_DMAC_TRIGSRC_19
+#define CONF_DMAC_TRIGSRC_19 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_19
+#ifndef CONF_DMAC_LVL_19
+#define CONF_DMAC_LVL_19 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_19
+#ifndef CONF_DMAC_EVOE_19
+#define CONF_DMAC_EVOE_19 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_19
+#ifndef CONF_DMAC_EVIE_19
+#define CONF_DMAC_EVIE_19 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_19
+#ifndef CONF_DMAC_EVACT_19
+#define CONF_DMAC_EVACT_19 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_19
+#ifndef CONF_DMAC_STEPSIZE_19
+#define CONF_DMAC_STEPSIZE_19 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_19
+#ifndef CONF_DMAC_STEPSEL_19
+#define CONF_DMAC_STEPSEL_19 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_19
+#ifndef CONF_DMAC_SRCINC_19
+#define CONF_DMAC_SRCINC_19 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_19
+#ifndef CONF_DMAC_DSTINC_19
+#define CONF_DMAC_DSTINC_19 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_19
+#ifndef CONF_DMAC_BEATSIZE_19
+#define CONF_DMAC_BEATSIZE_19 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_19
+#ifndef CONF_DMAC_BLOCKACT_19
+#define CONF_DMAC_BLOCKACT_19 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_19
+#ifndef CONF_DMAC_EVOSEL_19
+#define CONF_DMAC_EVOSEL_19 0
+#endif
+//
+
+// Channel 20 settings
+// dmac_channel_20_settings
+#ifndef CONF_DMAC_CHANNEL_20_SETTINGS
+#define CONF_DMAC_CHANNEL_20_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 20 is running in standby mode or not
+// dmac_runstdby_20
+#ifndef CONF_DMAC_RUNSTDBY_20
+#define CONF_DMAC_RUNSTDBY_20 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_20
+#ifndef CONF_DMAC_TRIGACT_20
+#define CONF_DMAC_TRIGACT_20 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_20
+#ifndef CONF_DMAC_TRIGSRC_20
+#define CONF_DMAC_TRIGSRC_20 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_20
+#ifndef CONF_DMAC_LVL_20
+#define CONF_DMAC_LVL_20 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_20
+#ifndef CONF_DMAC_EVOE_20
+#define CONF_DMAC_EVOE_20 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_20
+#ifndef CONF_DMAC_EVIE_20
+#define CONF_DMAC_EVIE_20 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_20
+#ifndef CONF_DMAC_EVACT_20
+#define CONF_DMAC_EVACT_20 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_20
+#ifndef CONF_DMAC_STEPSIZE_20
+#define CONF_DMAC_STEPSIZE_20 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_20
+#ifndef CONF_DMAC_STEPSEL_20
+#define CONF_DMAC_STEPSEL_20 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_20
+#ifndef CONF_DMAC_SRCINC_20
+#define CONF_DMAC_SRCINC_20 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_20
+#ifndef CONF_DMAC_DSTINC_20
+#define CONF_DMAC_DSTINC_20 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_20
+#ifndef CONF_DMAC_BEATSIZE_20
+#define CONF_DMAC_BEATSIZE_20 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_20
+#ifndef CONF_DMAC_BLOCKACT_20
+#define CONF_DMAC_BLOCKACT_20 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_20
+#ifndef CONF_DMAC_EVOSEL_20
+#define CONF_DMAC_EVOSEL_20 0
+#endif
+//
+
+// Channel 21 settings
+// dmac_channel_21_settings
+#ifndef CONF_DMAC_CHANNEL_21_SETTINGS
+#define CONF_DMAC_CHANNEL_21_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 21 is running in standby mode or not
+// dmac_runstdby_21
+#ifndef CONF_DMAC_RUNSTDBY_21
+#define CONF_DMAC_RUNSTDBY_21 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_21
+#ifndef CONF_DMAC_TRIGACT_21
+#define CONF_DMAC_TRIGACT_21 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_21
+#ifndef CONF_DMAC_TRIGSRC_21
+#define CONF_DMAC_TRIGSRC_21 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_21
+#ifndef CONF_DMAC_LVL_21
+#define CONF_DMAC_LVL_21 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_21
+#ifndef CONF_DMAC_EVOE_21
+#define CONF_DMAC_EVOE_21 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_21
+#ifndef CONF_DMAC_EVIE_21
+#define CONF_DMAC_EVIE_21 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_21
+#ifndef CONF_DMAC_EVACT_21
+#define CONF_DMAC_EVACT_21 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_21
+#ifndef CONF_DMAC_STEPSIZE_21
+#define CONF_DMAC_STEPSIZE_21 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_21
+#ifndef CONF_DMAC_STEPSEL_21
+#define CONF_DMAC_STEPSEL_21 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_21
+#ifndef CONF_DMAC_SRCINC_21
+#define CONF_DMAC_SRCINC_21 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_21
+#ifndef CONF_DMAC_DSTINC_21
+#define CONF_DMAC_DSTINC_21 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_21
+#ifndef CONF_DMAC_BEATSIZE_21
+#define CONF_DMAC_BEATSIZE_21 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_21
+#ifndef CONF_DMAC_BLOCKACT_21
+#define CONF_DMAC_BLOCKACT_21 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_21
+#ifndef CONF_DMAC_EVOSEL_21
+#define CONF_DMAC_EVOSEL_21 0
+#endif
+//
+
+// Channel 22 settings
+// dmac_channel_22_settings
+#ifndef CONF_DMAC_CHANNEL_22_SETTINGS
+#define CONF_DMAC_CHANNEL_22_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 22 is running in standby mode or not
+// dmac_runstdby_22
+#ifndef CONF_DMAC_RUNSTDBY_22
+#define CONF_DMAC_RUNSTDBY_22 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_22
+#ifndef CONF_DMAC_TRIGACT_22
+#define CONF_DMAC_TRIGACT_22 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_22
+#ifndef CONF_DMAC_TRIGSRC_22
+#define CONF_DMAC_TRIGSRC_22 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_22
+#ifndef CONF_DMAC_LVL_22
+#define CONF_DMAC_LVL_22 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_22
+#ifndef CONF_DMAC_EVOE_22
+#define CONF_DMAC_EVOE_22 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_22
+#ifndef CONF_DMAC_EVIE_22
+#define CONF_DMAC_EVIE_22 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_22
+#ifndef CONF_DMAC_EVACT_22
+#define CONF_DMAC_EVACT_22 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_22
+#ifndef CONF_DMAC_STEPSIZE_22
+#define CONF_DMAC_STEPSIZE_22 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_22
+#ifndef CONF_DMAC_STEPSEL_22
+#define CONF_DMAC_STEPSEL_22 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_22
+#ifndef CONF_DMAC_SRCINC_22
+#define CONF_DMAC_SRCINC_22 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_22
+#ifndef CONF_DMAC_DSTINC_22
+#define CONF_DMAC_DSTINC_22 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_22
+#ifndef CONF_DMAC_BEATSIZE_22
+#define CONF_DMAC_BEATSIZE_22 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_22
+#ifndef CONF_DMAC_BLOCKACT_22
+#define CONF_DMAC_BLOCKACT_22 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_22
+#ifndef CONF_DMAC_EVOSEL_22
+#define CONF_DMAC_EVOSEL_22 0
+#endif
+//
+
+// Channel 23 settings
+// dmac_channel_23_settings
+#ifndef CONF_DMAC_CHANNEL_23_SETTINGS
+#define CONF_DMAC_CHANNEL_23_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 23 is running in standby mode or not
+// dmac_runstdby_23
+#ifndef CONF_DMAC_RUNSTDBY_23
+#define CONF_DMAC_RUNSTDBY_23 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_23
+#ifndef CONF_DMAC_TRIGACT_23
+#define CONF_DMAC_TRIGACT_23 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_23
+#ifndef CONF_DMAC_TRIGSRC_23
+#define CONF_DMAC_TRIGSRC_23 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_23
+#ifndef CONF_DMAC_LVL_23
+#define CONF_DMAC_LVL_23 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_23
+#ifndef CONF_DMAC_EVOE_23
+#define CONF_DMAC_EVOE_23 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_23
+#ifndef CONF_DMAC_EVIE_23
+#define CONF_DMAC_EVIE_23 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_23
+#ifndef CONF_DMAC_EVACT_23
+#define CONF_DMAC_EVACT_23 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_23
+#ifndef CONF_DMAC_STEPSIZE_23
+#define CONF_DMAC_STEPSIZE_23 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_23
+#ifndef CONF_DMAC_STEPSEL_23
+#define CONF_DMAC_STEPSEL_23 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_23
+#ifndef CONF_DMAC_SRCINC_23
+#define CONF_DMAC_SRCINC_23 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_23
+#ifndef CONF_DMAC_DSTINC_23
+#define CONF_DMAC_DSTINC_23 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_23
+#ifndef CONF_DMAC_BEATSIZE_23
+#define CONF_DMAC_BEATSIZE_23 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_23
+#ifndef CONF_DMAC_BLOCKACT_23
+#define CONF_DMAC_BLOCKACT_23 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_23
+#ifndef CONF_DMAC_EVOSEL_23
+#define CONF_DMAC_EVOSEL_23 0
+#endif
+//
+
+// Channel 24 settings
+// dmac_channel_24_settings
+#ifndef CONF_DMAC_CHANNEL_24_SETTINGS
+#define CONF_DMAC_CHANNEL_24_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 24 is running in standby mode or not
+// dmac_runstdby_24
+#ifndef CONF_DMAC_RUNSTDBY_24
+#define CONF_DMAC_RUNSTDBY_24 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_24
+#ifndef CONF_DMAC_TRIGACT_24
+#define CONF_DMAC_TRIGACT_24 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_24
+#ifndef CONF_DMAC_TRIGSRC_24
+#define CONF_DMAC_TRIGSRC_24 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_24
+#ifndef CONF_DMAC_LVL_24
+#define CONF_DMAC_LVL_24 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_24
+#ifndef CONF_DMAC_EVOE_24
+#define CONF_DMAC_EVOE_24 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_24
+#ifndef CONF_DMAC_EVIE_24
+#define CONF_DMAC_EVIE_24 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_24
+#ifndef CONF_DMAC_EVACT_24
+#define CONF_DMAC_EVACT_24 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_24
+#ifndef CONF_DMAC_STEPSIZE_24
+#define CONF_DMAC_STEPSIZE_24 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_24
+#ifndef CONF_DMAC_STEPSEL_24
+#define CONF_DMAC_STEPSEL_24 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_24
+#ifndef CONF_DMAC_SRCINC_24
+#define CONF_DMAC_SRCINC_24 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_24
+#ifndef CONF_DMAC_DSTINC_24
+#define CONF_DMAC_DSTINC_24 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_24
+#ifndef CONF_DMAC_BEATSIZE_24
+#define CONF_DMAC_BEATSIZE_24 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_24
+#ifndef CONF_DMAC_BLOCKACT_24
+#define CONF_DMAC_BLOCKACT_24 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_24
+#ifndef CONF_DMAC_EVOSEL_24
+#define CONF_DMAC_EVOSEL_24 0
+#endif
+//
+
+// Channel 25 settings
+// dmac_channel_25_settings
+#ifndef CONF_DMAC_CHANNEL_25_SETTINGS
+#define CONF_DMAC_CHANNEL_25_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 25 is running in standby mode or not
+// dmac_runstdby_25
+#ifndef CONF_DMAC_RUNSTDBY_25
+#define CONF_DMAC_RUNSTDBY_25 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_25
+#ifndef CONF_DMAC_TRIGACT_25
+#define CONF_DMAC_TRIGACT_25 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_25
+#ifndef CONF_DMAC_TRIGSRC_25
+#define CONF_DMAC_TRIGSRC_25 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_25
+#ifndef CONF_DMAC_LVL_25
+#define CONF_DMAC_LVL_25 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_25
+#ifndef CONF_DMAC_EVOE_25
+#define CONF_DMAC_EVOE_25 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_25
+#ifndef CONF_DMAC_EVIE_25
+#define CONF_DMAC_EVIE_25 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_25
+#ifndef CONF_DMAC_EVACT_25
+#define CONF_DMAC_EVACT_25 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_25
+#ifndef CONF_DMAC_STEPSIZE_25
+#define CONF_DMAC_STEPSIZE_25 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_25
+#ifndef CONF_DMAC_STEPSEL_25
+#define CONF_DMAC_STEPSEL_25 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_25
+#ifndef CONF_DMAC_SRCINC_25
+#define CONF_DMAC_SRCINC_25 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_25
+#ifndef CONF_DMAC_DSTINC_25
+#define CONF_DMAC_DSTINC_25 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_25
+#ifndef CONF_DMAC_BEATSIZE_25
+#define CONF_DMAC_BEATSIZE_25 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_25
+#ifndef CONF_DMAC_BLOCKACT_25
+#define CONF_DMAC_BLOCKACT_25 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_25
+#ifndef CONF_DMAC_EVOSEL_25
+#define CONF_DMAC_EVOSEL_25 0
+#endif
+//
+
+// Channel 26 settings
+// dmac_channel_26_settings
+#ifndef CONF_DMAC_CHANNEL_26_SETTINGS
+#define CONF_DMAC_CHANNEL_26_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 26 is running in standby mode or not
+// dmac_runstdby_26
+#ifndef CONF_DMAC_RUNSTDBY_26
+#define CONF_DMAC_RUNSTDBY_26 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_26
+#ifndef CONF_DMAC_TRIGACT_26
+#define CONF_DMAC_TRIGACT_26 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_26
+#ifndef CONF_DMAC_TRIGSRC_26
+#define CONF_DMAC_TRIGSRC_26 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_26
+#ifndef CONF_DMAC_LVL_26
+#define CONF_DMAC_LVL_26 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_26
+#ifndef CONF_DMAC_EVOE_26
+#define CONF_DMAC_EVOE_26 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_26
+#ifndef CONF_DMAC_EVIE_26
+#define CONF_DMAC_EVIE_26 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_26
+#ifndef CONF_DMAC_EVACT_26
+#define CONF_DMAC_EVACT_26 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_26
+#ifndef CONF_DMAC_STEPSIZE_26
+#define CONF_DMAC_STEPSIZE_26 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_26
+#ifndef CONF_DMAC_STEPSEL_26
+#define CONF_DMAC_STEPSEL_26 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_26
+#ifndef CONF_DMAC_SRCINC_26
+#define CONF_DMAC_SRCINC_26 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_26
+#ifndef CONF_DMAC_DSTINC_26
+#define CONF_DMAC_DSTINC_26 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_26
+#ifndef CONF_DMAC_BEATSIZE_26
+#define CONF_DMAC_BEATSIZE_26 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_26
+#ifndef CONF_DMAC_BLOCKACT_26
+#define CONF_DMAC_BLOCKACT_26 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_26
+#ifndef CONF_DMAC_EVOSEL_26
+#define CONF_DMAC_EVOSEL_26 0
+#endif
+//
+
+// Channel 27 settings
+// dmac_channel_27_settings
+#ifndef CONF_DMAC_CHANNEL_27_SETTINGS
+#define CONF_DMAC_CHANNEL_27_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 27 is running in standby mode or not
+// dmac_runstdby_27
+#ifndef CONF_DMAC_RUNSTDBY_27
+#define CONF_DMAC_RUNSTDBY_27 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_27
+#ifndef CONF_DMAC_TRIGACT_27
+#define CONF_DMAC_TRIGACT_27 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_27
+#ifndef CONF_DMAC_TRIGSRC_27
+#define CONF_DMAC_TRIGSRC_27 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_27
+#ifndef CONF_DMAC_LVL_27
+#define CONF_DMAC_LVL_27 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_27
+#ifndef CONF_DMAC_EVOE_27
+#define CONF_DMAC_EVOE_27 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_27
+#ifndef CONF_DMAC_EVIE_27
+#define CONF_DMAC_EVIE_27 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_27
+#ifndef CONF_DMAC_EVACT_27
+#define CONF_DMAC_EVACT_27 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_27
+#ifndef CONF_DMAC_STEPSIZE_27
+#define CONF_DMAC_STEPSIZE_27 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_27
+#ifndef CONF_DMAC_STEPSEL_27
+#define CONF_DMAC_STEPSEL_27 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_27
+#ifndef CONF_DMAC_SRCINC_27
+#define CONF_DMAC_SRCINC_27 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_27
+#ifndef CONF_DMAC_DSTINC_27
+#define CONF_DMAC_DSTINC_27 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_27
+#ifndef CONF_DMAC_BEATSIZE_27
+#define CONF_DMAC_BEATSIZE_27 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_27
+#ifndef CONF_DMAC_BLOCKACT_27
+#define CONF_DMAC_BLOCKACT_27 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_27
+#ifndef CONF_DMAC_EVOSEL_27
+#define CONF_DMAC_EVOSEL_27 0
+#endif
+//
+
+// Channel 28 settings
+// dmac_channel_28_settings
+#ifndef CONF_DMAC_CHANNEL_28_SETTINGS
+#define CONF_DMAC_CHANNEL_28_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 28 is running in standby mode or not
+// dmac_runstdby_28
+#ifndef CONF_DMAC_RUNSTDBY_28
+#define CONF_DMAC_RUNSTDBY_28 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_28
+#ifndef CONF_DMAC_TRIGACT_28
+#define CONF_DMAC_TRIGACT_28 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_28
+#ifndef CONF_DMAC_TRIGSRC_28
+#define CONF_DMAC_TRIGSRC_28 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_28
+#ifndef CONF_DMAC_LVL_28
+#define CONF_DMAC_LVL_28 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_28
+#ifndef CONF_DMAC_EVOE_28
+#define CONF_DMAC_EVOE_28 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_28
+#ifndef CONF_DMAC_EVIE_28
+#define CONF_DMAC_EVIE_28 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_28
+#ifndef CONF_DMAC_EVACT_28
+#define CONF_DMAC_EVACT_28 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_28
+#ifndef CONF_DMAC_STEPSIZE_28
+#define CONF_DMAC_STEPSIZE_28 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_28
+#ifndef CONF_DMAC_STEPSEL_28
+#define CONF_DMAC_STEPSEL_28 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_28
+#ifndef CONF_DMAC_SRCINC_28
+#define CONF_DMAC_SRCINC_28 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_28
+#ifndef CONF_DMAC_DSTINC_28
+#define CONF_DMAC_DSTINC_28 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_28
+#ifndef CONF_DMAC_BEATSIZE_28
+#define CONF_DMAC_BEATSIZE_28 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_28
+#ifndef CONF_DMAC_BLOCKACT_28
+#define CONF_DMAC_BLOCKACT_28 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_28
+#ifndef CONF_DMAC_EVOSEL_28
+#define CONF_DMAC_EVOSEL_28 0
+#endif
+//
+
+// Channel 29 settings
+// dmac_channel_29_settings
+#ifndef CONF_DMAC_CHANNEL_29_SETTINGS
+#define CONF_DMAC_CHANNEL_29_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 29 is running in standby mode or not
+// dmac_runstdby_29
+#ifndef CONF_DMAC_RUNSTDBY_29
+#define CONF_DMAC_RUNSTDBY_29 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_29
+#ifndef CONF_DMAC_TRIGACT_29
+#define CONF_DMAC_TRIGACT_29 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_29
+#ifndef CONF_DMAC_TRIGSRC_29
+#define CONF_DMAC_TRIGSRC_29 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_29
+#ifndef CONF_DMAC_LVL_29
+#define CONF_DMAC_LVL_29 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_29
+#ifndef CONF_DMAC_EVOE_29
+#define CONF_DMAC_EVOE_29 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_29
+#ifndef CONF_DMAC_EVIE_29
+#define CONF_DMAC_EVIE_29 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_29
+#ifndef CONF_DMAC_EVACT_29
+#define CONF_DMAC_EVACT_29 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_29
+#ifndef CONF_DMAC_STEPSIZE_29
+#define CONF_DMAC_STEPSIZE_29 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_29
+#ifndef CONF_DMAC_STEPSEL_29
+#define CONF_DMAC_STEPSEL_29 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_29
+#ifndef CONF_DMAC_SRCINC_29
+#define CONF_DMAC_SRCINC_29 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_29
+#ifndef CONF_DMAC_DSTINC_29
+#define CONF_DMAC_DSTINC_29 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_29
+#ifndef CONF_DMAC_BEATSIZE_29
+#define CONF_DMAC_BEATSIZE_29 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_29
+#ifndef CONF_DMAC_BLOCKACT_29
+#define CONF_DMAC_BLOCKACT_29 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_29
+#ifndef CONF_DMAC_EVOSEL_29
+#define CONF_DMAC_EVOSEL_29 0
+#endif
+//
+
+// Channel 30 settings
+// dmac_channel_30_settings
+#ifndef CONF_DMAC_CHANNEL_30_SETTINGS
+#define CONF_DMAC_CHANNEL_30_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 30 is running in standby mode or not
+// dmac_runstdby_30
+#ifndef CONF_DMAC_RUNSTDBY_30
+#define CONF_DMAC_RUNSTDBY_30 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_30
+#ifndef CONF_DMAC_TRIGACT_30
+#define CONF_DMAC_TRIGACT_30 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_30
+#ifndef CONF_DMAC_TRIGSRC_30
+#define CONF_DMAC_TRIGSRC_30 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_30
+#ifndef CONF_DMAC_LVL_30
+#define CONF_DMAC_LVL_30 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_30
+#ifndef CONF_DMAC_EVOE_30
+#define CONF_DMAC_EVOE_30 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_30
+#ifndef CONF_DMAC_EVIE_30
+#define CONF_DMAC_EVIE_30 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_30
+#ifndef CONF_DMAC_EVACT_30
+#define CONF_DMAC_EVACT_30 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_30
+#ifndef CONF_DMAC_STEPSIZE_30
+#define CONF_DMAC_STEPSIZE_30 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_30
+#ifndef CONF_DMAC_STEPSEL_30
+#define CONF_DMAC_STEPSEL_30 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_30
+#ifndef CONF_DMAC_SRCINC_30
+#define CONF_DMAC_SRCINC_30 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_30
+#ifndef CONF_DMAC_DSTINC_30
+#define CONF_DMAC_DSTINC_30 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_30
+#ifndef CONF_DMAC_BEATSIZE_30
+#define CONF_DMAC_BEATSIZE_30 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_30
+#ifndef CONF_DMAC_BLOCKACT_30
+#define CONF_DMAC_BLOCKACT_30 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_30
+#ifndef CONF_DMAC_EVOSEL_30
+#define CONF_DMAC_EVOSEL_30 0
+#endif
+//
+
+// Channel 31 settings
+// dmac_channel_31_settings
+#ifndef CONF_DMAC_CHANNEL_31_SETTINGS
+#define CONF_DMAC_CHANNEL_31_SETTINGS 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 31 is running in standby mode or not
+// dmac_runstdby_31
+#ifndef CONF_DMAC_RUNSTDBY_31
+#define CONF_DMAC_RUNSTDBY_31 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_31
+#ifndef CONF_DMAC_TRIGACT_31
+#define CONF_DMAC_TRIGACT_31 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_31
+#ifndef CONF_DMAC_TRIGSRC_31
+#define CONF_DMAC_TRIGSRC_31 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_31
+#ifndef CONF_DMAC_LVL_31
+#define CONF_DMAC_LVL_31 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_31
+#ifndef CONF_DMAC_EVOE_31
+#define CONF_DMAC_EVOE_31 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_31
+#ifndef CONF_DMAC_EVIE_31
+#define CONF_DMAC_EVIE_31 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_31
+#ifndef CONF_DMAC_EVACT_31
+#define CONF_DMAC_EVACT_31 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_31
+#ifndef CONF_DMAC_STEPSIZE_31
+#define CONF_DMAC_STEPSIZE_31 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_31
+#ifndef CONF_DMAC_STEPSEL_31
+#define CONF_DMAC_STEPSEL_31 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_31
+#ifndef CONF_DMAC_SRCINC_31
+#define CONF_DMAC_SRCINC_31 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_31
+#ifndef CONF_DMAC_DSTINC_31
+#define CONF_DMAC_DSTINC_31 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_31
+#ifndef CONF_DMAC_BEATSIZE_31
+#define CONF_DMAC_BEATSIZE_31 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_31
+#ifndef CONF_DMAC_BLOCKACT_31
+#define CONF_DMAC_BLOCKACT_31 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_31
+#ifndef CONF_DMAC_EVOSEL_31
+#define CONF_DMAC_EVOSEL_31 0
+#endif
+//
+
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_DMAC_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_eic_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_eic_config.h
new file mode 100644
index 0000000..4b92f33
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_eic_config.h
@@ -0,0 +1,913 @@
+/* Auto-generated config file hpl_eic_config.h */
+#ifndef HPL_EIC_CONFIG_H
+#define HPL_EIC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Basic Settings
+// Clock Selection
+// Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or
+// either by CLK_ULP32K when power consumption is the priority.
+// <0x0=> Clocked by GCLK
+// <0x1=> Clocked by ULPOSC32K
+// eic_arch_cksel
+#ifndef CONF_EIC_CKSEL
+#define CONF_EIC_CKSEL 0
+#endif
+
+// Pin Sampler frequency selection
+// Indicates the sampling rate of the EXTINT pin.
+// <0x0=> The sampling rate is EIC clock
+// <0x1=> The sampling rate is the prescaled clock
+// eic_arch_tickon
+#ifndef CONF_EIC_TICKON
+#define CONF_EIC_TICKON 0
+#endif
+
+//
+
+// Non-Maskable Interrupt Control
+// eic_arch_nmi_ctrl
+#ifndef CONF_EIC_ENABLE_NMI_CTRL
+#define CONF_EIC_ENABLE_NMI_CTRL 0
+#endif
+
+// Non-Maskable Interrupt Filter Enable
+// Indicates whether the mon-maskable interrupt filter is enabled or not
+// eic_arch_nmifilten
+#ifndef CONF_EIC_NMIFILTEN
+#define CONF_EIC_NMIFILTEN 0
+#endif
+
+// Non-Maskable Interrupt Sense
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines non-maskable interrupt sense
+// eic_arch_nmisense
+#ifndef CONF_EIC_NMISENSE
+#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// Asynchronous Edge Detection Mode
+// Indicates the interrupt detection mode operated synchronously or asynchronousl
+// eic_arch_nmiasynch
+#ifndef CONF_EIC_NMIASYNCH
+#define CONF_EIC_NMIASYNCH 0
+#endif
+//
+
+// Interrupt 0 Settings
+// eic_arch_enable_irq_setting0
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING0
+#define CONF_EIC_ENABLE_IRQ_SETTING0 0
+#endif
+
+// External Interrupt 0 Filter Enable
+// Indicates whether the external interrupt 0 filter is enabled or not
+// eic_arch_filten0
+#ifndef CONF_EIC_FILTEN0
+#define CONF_EIC_FILTEN0 0
+#endif
+
+// External Interrupt 0 Debounce Enable
+// Indicates whether the external interrupt 0 debounce is enabled or not
+// eic_arch_debounce_enable0
+#ifndef CONF_EIC_DEBOUNCE_ENABLE0
+#define CONF_EIC_DEBOUNCE_ENABLE0 0
+#endif
+
+// External Interrupt 0 Event Output Enable
+// Indicates whether the external interrupt 0 event output is enabled or not
+// eic_arch_extinteo0
+#ifndef CONF_EIC_EXTINTEO0
+#define CONF_EIC_EXTINTEO0 0
+#endif
+
+// Input 0 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense0
+#ifndef CONF_EIC_SENSE0
+#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 0 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch0
+#ifndef CONF_EIC_ASYNCH0
+#define CONF_EIC_ASYNCH0 0
+#endif
+
+//
+
+// Interrupt 1 Settings
+// eic_arch_enable_irq_setting1
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING1
+#define CONF_EIC_ENABLE_IRQ_SETTING1 0
+#endif
+
+// External Interrupt 1 Filter Enable
+// Indicates whether the external interrupt 1 filter is enabled or not
+// eic_arch_filten1
+#ifndef CONF_EIC_FILTEN1
+#define CONF_EIC_FILTEN1 0
+#endif
+
+// External Interrupt 1 Debounce Enable
+// Indicates whether the external interrupt 1 debounce is enabled or not
+// eic_arch_debounce_enable1
+#ifndef CONF_EIC_DEBOUNCE_ENABLE1
+#define CONF_EIC_DEBOUNCE_ENABLE1 0
+#endif
+
+// External Interrupt 1 Event Output Enable
+// Indicates whether the external interrupt 1 event output is enabled or not
+// eic_arch_extinteo1
+#ifndef CONF_EIC_EXTINTEO1
+#define CONF_EIC_EXTINTEO1 0
+#endif
+
+// Input 1 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense1
+#ifndef CONF_EIC_SENSE1
+#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 1 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch1
+#ifndef CONF_EIC_ASYNCH1
+#define CONF_EIC_ASYNCH1 0
+#endif
+
+//
+
+// Interrupt 2 Settings
+// eic_arch_enable_irq_setting2
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING2
+#define CONF_EIC_ENABLE_IRQ_SETTING2 1
+#endif
+
+// External Interrupt 2 Filter Enable
+// Indicates whether the external interrupt 2 filter is enabled or not
+// eic_arch_filten2
+#ifndef CONF_EIC_FILTEN2
+#define CONF_EIC_FILTEN2 0
+#endif
+
+// External Interrupt 2 Debounce Enable
+// Indicates whether the external interrupt 2 debounce is enabled or not
+// eic_arch_debounce_enable2
+#ifndef CONF_EIC_DEBOUNCE_ENABLE2
+#define CONF_EIC_DEBOUNCE_ENABLE2 0
+#endif
+
+// External Interrupt 2 Event Output Enable
+// Indicates whether the external interrupt 2 event output is enabled or not
+// eic_arch_extinteo2
+#ifndef CONF_EIC_EXTINTEO2
+#define CONF_EIC_EXTINTEO2 1
+#endif
+
+// Input 2 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense2
+#ifndef CONF_EIC_SENSE2
+#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_FALL_Val
+#endif
+
+// External Interrupt 2 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch2
+#ifndef CONF_EIC_ASYNCH2
+#define CONF_EIC_ASYNCH2 1
+#endif
+
+//
+
+// Interrupt 3 Settings
+// eic_arch_enable_irq_setting3
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING3
+#define CONF_EIC_ENABLE_IRQ_SETTING3 0
+#endif
+
+// External Interrupt 3 Filter Enable
+// Indicates whether the external interrupt 3 filter is enabled or not
+// eic_arch_filten3
+#ifndef CONF_EIC_FILTEN3
+#define CONF_EIC_FILTEN3 0
+#endif
+
+// External Interrupt 3 Debounce Enable
+// Indicates whether the external interrupt 3 debounce is enabled or not
+// eic_arch_debounce_enable3
+#ifndef CONF_EIC_DEBOUNCE_ENABLE3
+#define CONF_EIC_DEBOUNCE_ENABLE3 0
+#endif
+
+// External Interrupt 3 Event Output Enable
+// Indicates whether the external interrupt 3 event output is enabled or not
+// eic_arch_extinteo3
+#ifndef CONF_EIC_EXTINTEO3
+#define CONF_EIC_EXTINTEO3 0
+#endif
+
+// Input 3 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense3
+#ifndef CONF_EIC_SENSE3
+#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 3 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch3
+#ifndef CONF_EIC_ASYNCH3
+#define CONF_EIC_ASYNCH3 0
+#endif
+
+//
+
+// Interrupt 4 Settings
+// eic_arch_enable_irq_setting4
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING4
+#define CONF_EIC_ENABLE_IRQ_SETTING4 0
+#endif
+
+// External Interrupt 4 Filter Enable
+// Indicates whether the external interrupt 4 filter is enabled or not
+// eic_arch_filten4
+#ifndef CONF_EIC_FILTEN4
+#define CONF_EIC_FILTEN4 0
+#endif
+
+// External Interrupt 4 Debounce Enable
+// Indicates whether the external interrupt 4 debounce is enabled or not
+// eic_arch_debounce_enable4
+#ifndef CONF_EIC_DEBOUNCE_ENABLE4
+#define CONF_EIC_DEBOUNCE_ENABLE4 0
+#endif
+
+// External Interrupt 4 Event Output Enable
+// Indicates whether the external interrupt 4 event output is enabled or not
+// eic_arch_extinteo4
+#ifndef CONF_EIC_EXTINTEO4
+#define CONF_EIC_EXTINTEO4 0
+#endif
+
+// Input 4 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense4
+#ifndef CONF_EIC_SENSE4
+#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 4 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch4
+#ifndef CONF_EIC_ASYNCH4
+#define CONF_EIC_ASYNCH4 0
+#endif
+
+//
+
+// Interrupt 5 Settings
+// eic_arch_enable_irq_setting5
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING5
+#define CONF_EIC_ENABLE_IRQ_SETTING5 0
+#endif
+
+// External Interrupt 5 Filter Enable
+// Indicates whether the external interrupt 5 filter is enabled or not
+// eic_arch_filten5
+#ifndef CONF_EIC_FILTEN5
+#define CONF_EIC_FILTEN5 0
+#endif
+
+// External Interrupt 5 Debounce Enable
+// Indicates whether the external interrupt 5 debounce is enabled or not
+// eic_arch_debounce_enable5
+#ifndef CONF_EIC_DEBOUNCE_ENABLE5
+#define CONF_EIC_DEBOUNCE_ENABLE5 0
+#endif
+
+// External Interrupt 5 Event Output Enable
+// Indicates whether the external interrupt 5 event output is enabled or not
+// eic_arch_extinteo5
+#ifndef CONF_EIC_EXTINTEO5
+#define CONF_EIC_EXTINTEO5 0
+#endif
+
+// Input 5 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense5
+#ifndef CONF_EIC_SENSE5
+#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 5 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch5
+#ifndef CONF_EIC_ASYNCH5
+#define CONF_EIC_ASYNCH5 0
+#endif
+
+//
+
+// Interrupt 6 Settings
+// eic_arch_enable_irq_setting6
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING6
+#define CONF_EIC_ENABLE_IRQ_SETTING6 0
+#endif
+
+// External Interrupt 6 Filter Enable
+// Indicates whether the external interrupt 6 filter is enabled or not
+// eic_arch_filten6
+#ifndef CONF_EIC_FILTEN6
+#define CONF_EIC_FILTEN6 0
+#endif
+
+// External Interrupt 6 Debounce Enable
+// Indicates whether the external interrupt 6 debounce is enabled or not
+// eic_arch_debounce_enable6
+#ifndef CONF_EIC_DEBOUNCE_ENABLE6
+#define CONF_EIC_DEBOUNCE_ENABLE6 0
+#endif
+
+// External Interrupt 6 Event Output Enable
+// Indicates whether the external interrupt 6 event output is enabled or not
+// eic_arch_extinteo6
+#ifndef CONF_EIC_EXTINTEO6
+#define CONF_EIC_EXTINTEO6 0
+#endif
+
+// Input 6 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense6
+#ifndef CONF_EIC_SENSE6
+#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 6 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch6
+#ifndef CONF_EIC_ASYNCH6
+#define CONF_EIC_ASYNCH6 0
+#endif
+
+//
+
+// Interrupt 7 Settings
+// eic_arch_enable_irq_setting7
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING7
+#define CONF_EIC_ENABLE_IRQ_SETTING7 0
+#endif
+
+// External Interrupt 7 Filter Enable
+// Indicates whether the external interrupt 7 filter is enabled or not
+// eic_arch_filten7
+#ifndef CONF_EIC_FILTEN7
+#define CONF_EIC_FILTEN7 0
+#endif
+
+// External Interrupt 7 Debounce Enable
+// Indicates whether the external interrupt 7 debounce is enabled or not
+// eic_arch_debounce_enable7
+#ifndef CONF_EIC_DEBOUNCE_ENABLE7
+#define CONF_EIC_DEBOUNCE_ENABLE7 0
+#endif
+
+// External Interrupt 7 Event Output Enable
+// Indicates whether the external interrupt 7 event output is enabled or not
+// eic_arch_extinteo7
+#ifndef CONF_EIC_EXTINTEO7
+#define CONF_EIC_EXTINTEO7 0
+#endif
+
+// Input 7 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense7
+#ifndef CONF_EIC_SENSE7
+#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 7 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch7
+#ifndef CONF_EIC_ASYNCH7
+#define CONF_EIC_ASYNCH7 0
+#endif
+
+//
+
+// Interrupt 8 Settings
+// eic_arch_enable_irq_setting8
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING8
+#define CONF_EIC_ENABLE_IRQ_SETTING8 0
+#endif
+
+// External Interrupt 8 Filter Enable
+// Indicates whether the external interrupt 8 filter is enabled or not
+// eic_arch_filten8
+#ifndef CONF_EIC_FILTEN8
+#define CONF_EIC_FILTEN8 0
+#endif
+
+// External Interrupt 8 Debounce Enable
+// Indicates whether the external interrupt 8 debounce is enabled or not
+// eic_arch_debounce_enable8
+#ifndef CONF_EIC_DEBOUNCE_ENABLE8
+#define CONF_EIC_DEBOUNCE_ENABLE8 0
+#endif
+
+// External Interrupt 8 Event Output Enable
+// Indicates whether the external interrupt 8 event output is enabled or not
+// eic_arch_extinteo8
+#ifndef CONF_EIC_EXTINTEO8
+#define CONF_EIC_EXTINTEO8 0
+#endif
+
+// Input 8 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense8
+#ifndef CONF_EIC_SENSE8
+#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 8 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch8
+#ifndef CONF_EIC_ASYNCH8
+#define CONF_EIC_ASYNCH8 0
+#endif
+
+//
+
+// Interrupt 9 Settings
+// eic_arch_enable_irq_setting9
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING9
+#define CONF_EIC_ENABLE_IRQ_SETTING9 0
+#endif
+
+// External Interrupt 9 Filter Enable
+// Indicates whether the external interrupt 9 filter is enabled or not
+// eic_arch_filten9
+#ifndef CONF_EIC_FILTEN9
+#define CONF_EIC_FILTEN9 0
+#endif
+
+// External Interrupt 9 Debounce Enable
+// Indicates whether the external interrupt 9 debounce is enabled or not
+// eic_arch_debounce_enable9
+#ifndef CONF_EIC_DEBOUNCE_ENABLE9
+#define CONF_EIC_DEBOUNCE_ENABLE9 0
+#endif
+
+// External Interrupt 9 Event Output Enable
+// Indicates whether the external interrupt 9 event output is enabled or not
+// eic_arch_extinteo9
+#ifndef CONF_EIC_EXTINTEO9
+#define CONF_EIC_EXTINTEO9 0
+#endif
+
+// Input 9 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense9
+#ifndef CONF_EIC_SENSE9
+#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 9 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch9
+#ifndef CONF_EIC_ASYNCH9
+#define CONF_EIC_ASYNCH9 0
+#endif
+
+//
+
+// Interrupt 10 Settings
+// eic_arch_enable_irq_setting10
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING10
+#define CONF_EIC_ENABLE_IRQ_SETTING10 0
+#endif
+
+// External Interrupt 10 Filter Enable
+// Indicates whether the external interrupt 10 filter is enabled or not
+// eic_arch_filten10
+#ifndef CONF_EIC_FILTEN10
+#define CONF_EIC_FILTEN10 0
+#endif
+
+// External Interrupt 10 Debounce Enable
+// Indicates whether the external interrupt 10 debounce is enabled or not
+// eic_arch_debounce_enable10
+#ifndef CONF_EIC_DEBOUNCE_ENABLE10
+#define CONF_EIC_DEBOUNCE_ENABLE10 0
+#endif
+
+// External Interrupt 10 Event Output Enable
+// Indicates whether the external interrupt 10 event output is enabled or not
+// eic_arch_extinteo10
+#ifndef CONF_EIC_EXTINTEO10
+#define CONF_EIC_EXTINTEO10 0
+#endif
+
+// Input 10 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense10
+#ifndef CONF_EIC_SENSE10
+#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 10 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch10
+#ifndef CONF_EIC_ASYNCH10
+#define CONF_EIC_ASYNCH10 0
+#endif
+
+//
+
+// Interrupt 11 Settings
+// eic_arch_enable_irq_setting11
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING11
+#define CONF_EIC_ENABLE_IRQ_SETTING11 0
+#endif
+
+// External Interrupt 11 Filter Enable
+// Indicates whether the external interrupt 11 filter is enabled or not
+// eic_arch_filten11
+#ifndef CONF_EIC_FILTEN11
+#define CONF_EIC_FILTEN11 0
+#endif
+
+// External Interrupt 11 Debounce Enable
+// Indicates whether the external interrupt 11 debounce is enabled or not
+// eic_arch_debounce_enable11
+#ifndef CONF_EIC_DEBOUNCE_ENABLE11
+#define CONF_EIC_DEBOUNCE_ENABLE11 0
+#endif
+
+// External Interrupt 11 Event Output Enable
+// Indicates whether the external interrupt 11 event output is enabled or not
+// eic_arch_extinteo11
+#ifndef CONF_EIC_EXTINTEO11
+#define CONF_EIC_EXTINTEO11 0
+#endif
+
+// Input 11 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense11
+#ifndef CONF_EIC_SENSE11
+#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 11 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch11
+#ifndef CONF_EIC_ASYNCH11
+#define CONF_EIC_ASYNCH11 0
+#endif
+
+//
+
+// Interrupt 12 Settings
+// eic_arch_enable_irq_setting12
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING12
+#define CONF_EIC_ENABLE_IRQ_SETTING12 0
+#endif
+
+// External Interrupt 12 Filter Enable
+// Indicates whether the external interrupt 12 filter is enabled or not
+// eic_arch_filten12
+#ifndef CONF_EIC_FILTEN12
+#define CONF_EIC_FILTEN12 0
+#endif
+
+// External Interrupt 12 Debounce Enable
+// Indicates whether the external interrupt 12 debounce is enabled or not
+// eic_arch_debounce_enable12
+#ifndef CONF_EIC_DEBOUNCE_ENABLE12
+#define CONF_EIC_DEBOUNCE_ENABLE12 0
+#endif
+
+// External Interrupt 12 Event Output Enable
+// Indicates whether the external interrupt 12 event output is enabled or not
+// eic_arch_extinteo12
+#ifndef CONF_EIC_EXTINTEO12
+#define CONF_EIC_EXTINTEO12 0
+#endif
+
+// Input 12 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense12
+#ifndef CONF_EIC_SENSE12
+#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 12 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch12
+#ifndef CONF_EIC_ASYNCH12
+#define CONF_EIC_ASYNCH12 0
+#endif
+
+//
+
+// Interrupt 13 Settings
+// eic_arch_enable_irq_setting13
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING13
+#define CONF_EIC_ENABLE_IRQ_SETTING13 0
+#endif
+
+// External Interrupt 13 Filter Enable
+// Indicates whether the external interrupt 13 filter is enabled or not
+// eic_arch_filten13
+#ifndef CONF_EIC_FILTEN13
+#define CONF_EIC_FILTEN13 0
+#endif
+
+// External Interrupt 13 Debounce Enable
+// Indicates whether the external interrupt 13 debounce is enabled or not
+// eic_arch_debounce_enable13
+#ifndef CONF_EIC_DEBOUNCE_ENABLE13
+#define CONF_EIC_DEBOUNCE_ENABLE13 0
+#endif
+
+// External Interrupt 13 Event Output Enable
+// Indicates whether the external interrupt 13 event output is enabled or not
+// eic_arch_extinteo13
+#ifndef CONF_EIC_EXTINTEO13
+#define CONF_EIC_EXTINTEO13 0
+#endif
+
+// Input 13 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense13
+#ifndef CONF_EIC_SENSE13
+#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 13 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch13
+#ifndef CONF_EIC_ASYNCH13
+#define CONF_EIC_ASYNCH13 0
+#endif
+
+//
+
+// Interrupt 14 Settings
+// eic_arch_enable_irq_setting14
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING14
+#define CONF_EIC_ENABLE_IRQ_SETTING14 1
+#endif
+
+// External Interrupt 14 Filter Enable
+// Indicates whether the external interrupt 14 filter is enabled or not
+// eic_arch_filten14
+#ifndef CONF_EIC_FILTEN14
+#define CONF_EIC_FILTEN14 1
+#endif
+
+// External Interrupt 14 Debounce Enable
+// Indicates whether the external interrupt 14 debounce is enabled or not
+// eic_arch_debounce_enable14
+#ifndef CONF_EIC_DEBOUNCE_ENABLE14
+#define CONF_EIC_DEBOUNCE_ENABLE14 0
+#endif
+
+// External Interrupt 14 Event Output Enable
+// Indicates whether the external interrupt 14 event output is enabled or not
+// eic_arch_extinteo14
+#ifndef CONF_EIC_EXTINTEO14
+#define CONF_EIC_EXTINTEO14 0
+#endif
+
+// Input 14 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense14
+#ifndef CONF_EIC_SENSE14
+#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_FALL_Val
+#endif
+
+// External Interrupt 14 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch14
+#ifndef CONF_EIC_ASYNCH14
+#define CONF_EIC_ASYNCH14 0
+#endif
+
+//
+
+// Interrupt 15 Settings
+// eic_arch_enable_irq_setting15
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING15
+#define CONF_EIC_ENABLE_IRQ_SETTING15 1
+#endif
+
+// External Interrupt 15 Filter Enable
+// Indicates whether the external interrupt 15 filter is enabled or not
+// eic_arch_filten15
+#ifndef CONF_EIC_FILTEN15
+#define CONF_EIC_FILTEN15 1
+#endif
+
+// External Interrupt 15 Debounce Enable
+// Indicates whether the external interrupt 15 debounce is enabled or not
+// eic_arch_debounce_enable15
+#ifndef CONF_EIC_DEBOUNCE_ENABLE15
+#define CONF_EIC_DEBOUNCE_ENABLE15 0
+#endif
+
+// External Interrupt 15 Event Output Enable
+// Indicates whether the external interrupt 15 event output is enabled or not
+// eic_arch_extinteo15
+#ifndef CONF_EIC_EXTINTEO15
+#define CONF_EIC_EXTINTEO15 0
+#endif
+
+// Input 15 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense15
+#ifndef CONF_EIC_SENSE15
+#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_FALL_Val
+#endif
+
+// External Interrupt 15 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch15
+#ifndef CONF_EIC_ASYNCH15
+#define CONF_EIC_ASYNCH15 0
+#endif
+
+//
+
+// Debouncer 0 Settings
+// Debouncer Frequency Selection
+// <0x0=>Divided by 2
+// <0x1=>Divided by 4
+// <0x2=>Divided by 8
+// <0x3=>Divided by 16
+// <0x4=>Divided by 32
+// <0x5=>Divided by 64
+// <0x6=>Divided by 128
+// <0x7=>Divided by 256
+// Select the debouncer low frequency clock for pins
+
+// EXTINT[7:0].
+
+// eic_arch_prescaler0
+#ifndef CONF_EIC_DPRESCALER0
+#define CONF_EIC_DPRESCALER0 EIC_DPRESCALER_PRESCALER0(0x0)
+#endif
+
+// Low frequency samples
+// <0x0=>3
+// <0x1=>7
+// Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from
+// current pin state to next pin state in synchronous debouncing mode.
+// eic_arch_states0
+#ifndef CONF_EIC_STATES0
+#define CONF_EIC_STATES0 0x0
+#endif
+
+//
+
+// Debouncer 1 Settings
+// Debouncer Frequency Selection
+// <0x0=>Divided by 2
+// <0x1=>Divided by 4
+// <0x2=>Divided by 8
+// <0x3=>Divided by 16
+// <0x4=>Divided by 32
+// <0x5=>Divided by 64
+// <0x6=>Divided by 128
+// <0x7=>Divided by 256
+// Select the debouncer low frequency clock for pins
+
+// EXTINT[15:8].
+
+// eic_arch_prescaler1
+#ifndef CONF_EIC_DPRESCALER1
+#define CONF_EIC_DPRESCALER1 EIC_DPRESCALER_PRESCALER1(0x0)
+#endif
+
+// Low frequency samples
+// <0x0=>3
+// <0x1=>7
+// Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from
+// current pin state to next pin state in synchronous debouncing mode.
+// eic_arch_states1
+#ifndef CONF_EIC_STATES1
+#define CONF_EIC_STATES1 0x0
+#endif
+
+//
+
+#define CONFIG_EIC_EXTINT_MAP {2, PIN_PA02}, {7, PIN_PA07}, {14, PIN_PB30}, {15, PIN_PB31},
+
+// <<< end of configuration section >>>
+
+#endif // HPL_EIC_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_evsys_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_evsys_config.h
new file mode 100644
index 0000000..b193999
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_evsys_config.h
@@ -0,0 +1,8363 @@
+/* Auto-generated config file hpl_evsys_config.h */
+#ifndef HPL_EVSYS_CONFIG_H
+#define HPL_EVSYS_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Channel 0 settings
+// evsys_channel_setting_0
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_0
+#define CONF_EVSYS_CHANNEL_SETTINGS_0 1
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_0
+#ifndef CONF_EDGSEL_0
+#define CONF_EDGSEL_0 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_0
+#ifndef CONF_PATH_0
+#define CONF_PATH_0 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_0
+#ifndef CONF_EVGEN_0
+#define CONF_EVGEN_0 41
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_0
+#ifndef CONF_OVR_0
+#define CONF_OVR_0 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_0
+#ifndef CONF_EVD_0
+#define CONF_EVD_0 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_0
+#ifndef CONF_ONDEMAND_0
+#define CONF_ONDEMAND_0 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_0
+#ifndef CONF_RUNSTDBY_0
+#define CONF_RUNSTDBY_0 0
+#endif
+
+//
+
+// Channel 1 settings
+// evsys_channel_setting_1
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_1
+#define CONF_EVSYS_CHANNEL_SETTINGS_1 1
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_1
+#ifndef CONF_EDGSEL_1
+#define CONF_EDGSEL_1 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_1
+#ifndef CONF_PATH_1
+#define CONF_PATH_1 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_1
+#ifndef CONF_EVGEN_1
+#define CONF_EVGEN_1 74
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_1
+#ifndef CONF_OVR_1
+#define CONF_OVR_1 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_1
+#ifndef CONF_EVD_1
+#define CONF_EVD_1 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_1
+#ifndef CONF_ONDEMAND_1
+#define CONF_ONDEMAND_1 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_1
+#ifndef CONF_RUNSTDBY_1
+#define CONF_RUNSTDBY_1 0
+#endif
+
+//
+
+// Channel 2 settings
+// evsys_channel_setting_2
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_2
+#define CONF_EVSYS_CHANNEL_SETTINGS_2 1
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_2
+#ifndef CONF_EDGSEL_2
+#define CONF_EDGSEL_2 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_2
+#ifndef CONF_PATH_2
+#define CONF_PATH_2 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_2
+#ifndef CONF_EVGEN_2
+#define CONF_EVGEN_2 75
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_2
+#ifndef CONF_OVR_2
+#define CONF_OVR_2 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_2
+#ifndef CONF_EVD_2
+#define CONF_EVD_2 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_2
+#ifndef CONF_ONDEMAND_2
+#define CONF_ONDEMAND_2 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_2
+#ifndef CONF_RUNSTDBY_2
+#define CONF_RUNSTDBY_2 0
+#endif
+
+//
+
+// Channel 3 settings
+// evsys_channel_setting_3
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_3
+#define CONF_EVSYS_CHANNEL_SETTINGS_3 1
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_3
+#ifndef CONF_EDGSEL_3
+#define CONF_EDGSEL_3 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_3
+#ifndef CONF_PATH_3
+#define CONF_PATH_3 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_3
+#ifndef CONF_EVGEN_3
+#define CONF_EVGEN_3 78
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_3
+#ifndef CONF_OVR_3
+#define CONF_OVR_3 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_3
+#ifndef CONF_EVD_3
+#define CONF_EVD_3 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_3
+#ifndef CONF_ONDEMAND_3
+#define CONF_ONDEMAND_3 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_3
+#ifndef CONF_RUNSTDBY_3
+#define CONF_RUNSTDBY_3 0
+#endif
+
+//
+
+// Channel 4 settings
+// evsys_channel_setting_4
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_4
+#define CONF_EVSYS_CHANNEL_SETTINGS_4 1
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_4
+#ifndef CONF_EDGSEL_4
+#define CONF_EDGSEL_4 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_4
+#ifndef CONF_PATH_4
+#define CONF_PATH_4 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_4
+#ifndef CONF_EVGEN_4
+#define CONF_EVGEN_4 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_4
+#ifndef CONF_OVR_4
+#define CONF_OVR_4 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_4
+#ifndef CONF_EVD_4
+#define CONF_EVD_4 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_4
+#ifndef CONF_ONDEMAND_4
+#define CONF_ONDEMAND_4 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_4
+#ifndef CONF_RUNSTDBY_4
+#define CONF_RUNSTDBY_4 0
+#endif
+
+//
+
+// Channel 5 settings
+// evsys_channel_setting_5
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_5
+#define CONF_EVSYS_CHANNEL_SETTINGS_5 1
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_5
+#ifndef CONF_EDGSEL_5
+#define CONF_EDGSEL_5 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_5
+#ifndef CONF_PATH_5
+#define CONF_PATH_5 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_5
+#ifndef CONF_EVGEN_5
+#define CONF_EVGEN_5 20
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_5
+#ifndef CONF_OVR_5
+#define CONF_OVR_5 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_5
+#ifndef CONF_EVD_5
+#define CONF_EVD_5 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_5
+#ifndef CONF_ONDEMAND_5
+#define CONF_ONDEMAND_5 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_5
+#ifndef CONF_RUNSTDBY_5
+#define CONF_RUNSTDBY_5 0
+#endif
+
+//
+
+// Channel 6 settings
+// evsys_channel_setting_6
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_6
+#define CONF_EVSYS_CHANNEL_SETTINGS_6 1
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_6
+#ifndef CONF_EDGSEL_6
+#define CONF_EDGSEL_6 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_6
+#ifndef CONF_PATH_6
+#define CONF_PATH_6 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_6
+#ifndef CONF_EVGEN_6
+#define CONF_EVGEN_6 34
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_6
+#ifndef CONF_OVR_6
+#define CONF_OVR_6 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_6
+#ifndef CONF_EVD_6
+#define CONF_EVD_6 1
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_6
+#ifndef CONF_ONDEMAND_6
+#define CONF_ONDEMAND_6 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_6
+#ifndef CONF_RUNSTDBY_6
+#define CONF_RUNSTDBY_6 0
+#endif
+
+//
+
+// Channel 7 settings
+// evsys_channel_setting_7
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_7
+#define CONF_EVSYS_CHANNEL_SETTINGS_7 1
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_7
+#ifndef CONF_EDGSEL_7
+#define CONF_EDGSEL_7 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_7
+#ifndef CONF_PATH_7
+#define CONF_PATH_7 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_7
+#ifndef CONF_EVGEN_7
+#define CONF_EVGEN_7 35
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_7
+#ifndef CONF_OVR_7
+#define CONF_OVR_7 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_7
+#ifndef CONF_EVD_7
+#define CONF_EVD_7 1
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_7
+#ifndef CONF_ONDEMAND_7
+#define CONF_ONDEMAND_7 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_7
+#ifndef CONF_RUNSTDBY_7
+#define CONF_RUNSTDBY_7 0
+#endif
+
+//
+
+// Channel 8 settings
+// evsys_channel_setting_8
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_8
+#define CONF_EVSYS_CHANNEL_SETTINGS_8 1
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_8
+#ifndef CONF_EDGSEL_8
+#define CONF_EDGSEL_8 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_8
+#ifndef CONF_PATH_8
+#define CONF_PATH_8 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_8
+#ifndef CONF_EVGEN_8
+#define CONF_EVGEN_8 36
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_8
+#ifndef CONF_OVR_8
+#define CONF_OVR_8 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_8
+#ifndef CONF_EVD_8
+#define CONF_EVD_8 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_8
+#ifndef CONF_ONDEMAND_8
+#define CONF_ONDEMAND_8 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_8
+#ifndef CONF_RUNSTDBY_8
+#define CONF_RUNSTDBY_8 0
+#endif
+
+//
+
+// Channel 9 settings
+// evsys_channel_setting_9
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_9
+#define CONF_EVSYS_CHANNEL_SETTINGS_9 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_9
+#ifndef CONF_EDGSEL_9
+#define CONF_EDGSEL_9 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_9
+#ifndef CONF_PATH_9
+#define CONF_PATH_9 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_9
+#ifndef CONF_EVGEN_9
+#define CONF_EVGEN_9 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_9
+#ifndef CONF_OVR_9
+#define CONF_OVR_9 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_9
+#ifndef CONF_EVD_9
+#define CONF_EVD_9 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_9
+#ifndef CONF_ONDEMAND_9
+#define CONF_ONDEMAND_9 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_9
+#ifndef CONF_RUNSTDBY_9
+#define CONF_RUNSTDBY_9 0
+#endif
+
+//
+
+// Channel 10 settings
+// evsys_channel_setting_10
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_10
+#define CONF_EVSYS_CHANNEL_SETTINGS_10 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_10
+#ifndef CONF_EDGSEL_10
+#define CONF_EDGSEL_10 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_10
+#ifndef CONF_PATH_10
+#define CONF_PATH_10 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_10
+#ifndef CONF_EVGEN_10
+#define CONF_EVGEN_10 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_10
+#ifndef CONF_OVR_10
+#define CONF_OVR_10 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_10
+#ifndef CONF_EVD_10
+#define CONF_EVD_10 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_10
+#ifndef CONF_ONDEMAND_10
+#define CONF_ONDEMAND_10 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_10
+#ifndef CONF_RUNSTDBY_10
+#define CONF_RUNSTDBY_10 0
+#endif
+
+//
+
+// Channel 11 settings
+// evsys_channel_setting_11
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_11
+#define CONF_EVSYS_CHANNEL_SETTINGS_11 1
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_11
+#ifndef CONF_EDGSEL_11
+#define CONF_EDGSEL_11 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_11
+#ifndef CONF_PATH_11
+#define CONF_PATH_11 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_11
+#ifndef CONF_EVGEN_11
+#define CONF_EVGEN_11 116
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_11
+#ifndef CONF_OVR_11
+#define CONF_OVR_11 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_11
+#ifndef CONF_EVD_11
+#define CONF_EVD_11 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_11
+#ifndef CONF_ONDEMAND_11
+#define CONF_ONDEMAND_11 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_11
+#ifndef CONF_RUNSTDBY_11
+#define CONF_RUNSTDBY_11 0
+#endif
+
+//
+
+// Channel 12 settings
+// evsys_channel_setting_12
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_12
+#define CONF_EVSYS_CHANNEL_SETTINGS_12 1
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_12
+#ifndef CONF_EDGSEL_12
+#define CONF_EDGSEL_12 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_12
+#ifndef CONF_PATH_12
+#define CONF_PATH_12 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_12
+#ifndef CONF_EVGEN_12
+#define CONF_EVGEN_12 118
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_12
+#ifndef CONF_OVR_12
+#define CONF_OVR_12 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_12
+#ifndef CONF_EVD_12
+#define CONF_EVD_12 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_12
+#ifndef CONF_ONDEMAND_12
+#define CONF_ONDEMAND_12 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_12
+#ifndef CONF_RUNSTDBY_12
+#define CONF_RUNSTDBY_12 0
+#endif
+
+//
+
+// Channel 13 settings
+// evsys_channel_setting_13
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_13
+#define CONF_EVSYS_CHANNEL_SETTINGS_13 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_13
+#ifndef CONF_EDGSEL_13
+#define CONF_EDGSEL_13 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_13
+#ifndef CONF_PATH_13
+#define CONF_PATH_13 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_13
+#ifndef CONF_EVGEN_13
+#define CONF_EVGEN_13 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_13
+#ifndef CONF_OVR_13
+#define CONF_OVR_13 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_13
+#ifndef CONF_EVD_13
+#define CONF_EVD_13 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_13
+#ifndef CONF_ONDEMAND_13
+#define CONF_ONDEMAND_13 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_13
+#ifndef CONF_RUNSTDBY_13
+#define CONF_RUNSTDBY_13 0
+#endif
+
+//
+
+// Channel 14 settings
+// evsys_channel_setting_14
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_14
+#define CONF_EVSYS_CHANNEL_SETTINGS_14 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_14
+#ifndef CONF_EDGSEL_14
+#define CONF_EDGSEL_14 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_14
+#ifndef CONF_PATH_14
+#define CONF_PATH_14 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_14
+#ifndef CONF_EVGEN_14
+#define CONF_EVGEN_14 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_14
+#ifndef CONF_OVR_14
+#define CONF_OVR_14 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_14
+#ifndef CONF_EVD_14
+#define CONF_EVD_14 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_14
+#ifndef CONF_ONDEMAND_14
+#define CONF_ONDEMAND_14 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_14
+#ifndef CONF_RUNSTDBY_14
+#define CONF_RUNSTDBY_14 0
+#endif
+
+//
+
+// Channel 15 settings
+// evsys_channel_setting_15
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_15
+#define CONF_EVSYS_CHANNEL_SETTINGS_15 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_15
+#ifndef CONF_EDGSEL_15
+#define CONF_EDGSEL_15 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_15
+#ifndef CONF_PATH_15
+#define CONF_PATH_15 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_15
+#ifndef CONF_EVGEN_15
+#define CONF_EVGEN_15 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_15
+#ifndef CONF_OVR_15
+#define CONF_OVR_15 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_15
+#ifndef CONF_EVD_15
+#define CONF_EVD_15 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_15
+#ifndef CONF_ONDEMAND_15
+#define CONF_ONDEMAND_15 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_15
+#ifndef CONF_RUNSTDBY_15
+#define CONF_RUNSTDBY_15 0
+#endif
+
+//
+
+// Channel 16 settings
+// evsys_channel_setting_16
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_16
+#define CONF_EVSYS_CHANNEL_SETTINGS_16 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_16
+#ifndef CONF_EDGSEL_16
+#define CONF_EDGSEL_16 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_16
+#ifndef CONF_PATH_16
+#define CONF_PATH_16 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_16
+#ifndef CONF_EVGEN_16
+#define CONF_EVGEN_16 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_16
+#ifndef CONF_OVR_16
+#define CONF_OVR_16 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_16
+#ifndef CONF_EVD_16
+#define CONF_EVD_16 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_16
+#ifndef CONF_ONDEMAND_16
+#define CONF_ONDEMAND_16 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_16
+#ifndef CONF_RUNSTDBY_16
+#define CONF_RUNSTDBY_16 0
+#endif
+
+//
+
+// Channel 17 settings
+// evsys_channel_setting_17
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_17
+#define CONF_EVSYS_CHANNEL_SETTINGS_17 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_17
+#ifndef CONF_EDGSEL_17
+#define CONF_EDGSEL_17 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_17
+#ifndef CONF_PATH_17
+#define CONF_PATH_17 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_17
+#ifndef CONF_EVGEN_17
+#define CONF_EVGEN_17 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_17
+#ifndef CONF_OVR_17
+#define CONF_OVR_17 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_17
+#ifndef CONF_EVD_17
+#define CONF_EVD_17 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_17
+#ifndef CONF_ONDEMAND_17
+#define CONF_ONDEMAND_17 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_17
+#ifndef CONF_RUNSTDBY_17
+#define CONF_RUNSTDBY_17 0
+#endif
+
+//
+
+// Channel 18 settings
+// evsys_channel_setting_18
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_18
+#define CONF_EVSYS_CHANNEL_SETTINGS_18 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_18
+#ifndef CONF_EDGSEL_18
+#define CONF_EDGSEL_18 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_18
+#ifndef CONF_PATH_18
+#define CONF_PATH_18 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_18
+#ifndef CONF_EVGEN_18
+#define CONF_EVGEN_18 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_18
+#ifndef CONF_OVR_18
+#define CONF_OVR_18 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_18
+#ifndef CONF_EVD_18
+#define CONF_EVD_18 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_18
+#ifndef CONF_ONDEMAND_18
+#define CONF_ONDEMAND_18 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_18
+#ifndef CONF_RUNSTDBY_18
+#define CONF_RUNSTDBY_18 0
+#endif
+
+//
+
+// Channel 19 settings
+// evsys_channel_setting_19
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_19
+#define CONF_EVSYS_CHANNEL_SETTINGS_19 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_19
+#ifndef CONF_EDGSEL_19
+#define CONF_EDGSEL_19 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_19
+#ifndef CONF_PATH_19
+#define CONF_PATH_19 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_19
+#ifndef CONF_EVGEN_19
+#define CONF_EVGEN_19 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_19
+#ifndef CONF_OVR_19
+#define CONF_OVR_19 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_19
+#ifndef CONF_EVD_19
+#define CONF_EVD_19 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_19
+#ifndef CONF_ONDEMAND_19
+#define CONF_ONDEMAND_19 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_19
+#ifndef CONF_RUNSTDBY_19
+#define CONF_RUNSTDBY_19 0
+#endif
+
+//
+
+// Channel 20 settings
+// evsys_channel_setting_20
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_20
+#define CONF_EVSYS_CHANNEL_SETTINGS_20 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_20
+#ifndef CONF_EDGSEL_20
+#define CONF_EDGSEL_20 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_20
+#ifndef CONF_PATH_20
+#define CONF_PATH_20 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_20
+#ifndef CONF_EVGEN_20
+#define CONF_EVGEN_20 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_20
+#ifndef CONF_OVR_20
+#define CONF_OVR_20 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_20
+#ifndef CONF_EVD_20
+#define CONF_EVD_20 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_20
+#ifndef CONF_ONDEMAND_20
+#define CONF_ONDEMAND_20 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_20
+#ifndef CONF_RUNSTDBY_20
+#define CONF_RUNSTDBY_20 0
+#endif
+
+//
+
+// Channel 21 settings
+// evsys_channel_setting_21
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_21
+#define CONF_EVSYS_CHANNEL_SETTINGS_21 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_21
+#ifndef CONF_EDGSEL_21
+#define CONF_EDGSEL_21 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_21
+#ifndef CONF_PATH_21
+#define CONF_PATH_21 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_21
+#ifndef CONF_EVGEN_21
+#define CONF_EVGEN_21 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_21
+#ifndef CONF_OVR_21
+#define CONF_OVR_21 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_21
+#ifndef CONF_EVD_21
+#define CONF_EVD_21 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_21
+#ifndef CONF_ONDEMAND_21
+#define CONF_ONDEMAND_21 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_21
+#ifndef CONF_RUNSTDBY_21
+#define CONF_RUNSTDBY_21 0
+#endif
+
+//
+
+// Channel 22 settings
+// evsys_channel_setting_22
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_22
+#define CONF_EVSYS_CHANNEL_SETTINGS_22 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_22
+#ifndef CONF_EDGSEL_22
+#define CONF_EDGSEL_22 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_22
+#ifndef CONF_PATH_22
+#define CONF_PATH_22 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_22
+#ifndef CONF_EVGEN_22
+#define CONF_EVGEN_22 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_22
+#ifndef CONF_OVR_22
+#define CONF_OVR_22 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_22
+#ifndef CONF_EVD_22
+#define CONF_EVD_22 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_22
+#ifndef CONF_ONDEMAND_22
+#define CONF_ONDEMAND_22 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_22
+#ifndef CONF_RUNSTDBY_22
+#define CONF_RUNSTDBY_22 0
+#endif
+
+//
+
+// Channel 23 settings
+// evsys_channel_setting_23
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_23
+#define CONF_EVSYS_CHANNEL_SETTINGS_23 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_23
+#ifndef CONF_EDGSEL_23
+#define CONF_EDGSEL_23 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_23
+#ifndef CONF_PATH_23
+#define CONF_PATH_23 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_23
+#ifndef CONF_EVGEN_23
+#define CONF_EVGEN_23 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_23
+#ifndef CONF_OVR_23
+#define CONF_OVR_23 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_23
+#ifndef CONF_EVD_23
+#define CONF_EVD_23 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_23
+#ifndef CONF_ONDEMAND_23
+#define CONF_ONDEMAND_23 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_23
+#ifndef CONF_RUNSTDBY_23
+#define CONF_RUNSTDBY_23 0
+#endif
+
+//
+
+// Channel 24 settings
+// evsys_channel_setting_24
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_24
+#define CONF_EVSYS_CHANNEL_SETTINGS_24 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_24
+#ifndef CONF_EDGSEL_24
+#define CONF_EDGSEL_24 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_24
+#ifndef CONF_PATH_24
+#define CONF_PATH_24 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_24
+#ifndef CONF_EVGEN_24
+#define CONF_EVGEN_24 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_24
+#ifndef CONF_OVR_24
+#define CONF_OVR_24 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_24
+#ifndef CONF_EVD_24
+#define CONF_EVD_24 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_24
+#ifndef CONF_ONDEMAND_24
+#define CONF_ONDEMAND_24 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_24
+#ifndef CONF_RUNSTDBY_24
+#define CONF_RUNSTDBY_24 0
+#endif
+
+//
+
+// Channel 25 settings
+// evsys_channel_setting_25
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_25
+#define CONF_EVSYS_CHANNEL_SETTINGS_25 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_25
+#ifndef CONF_EDGSEL_25
+#define CONF_EDGSEL_25 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_25
+#ifndef CONF_PATH_25
+#define CONF_PATH_25 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_25
+#ifndef CONF_EVGEN_25
+#define CONF_EVGEN_25 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_25
+#ifndef CONF_OVR_25
+#define CONF_OVR_25 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_25
+#ifndef CONF_EVD_25
+#define CONF_EVD_25 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_25
+#ifndef CONF_ONDEMAND_25
+#define CONF_ONDEMAND_25 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_25
+#ifndef CONF_RUNSTDBY_25
+#define CONF_RUNSTDBY_25 0
+#endif
+
+//
+
+// Channel 26 settings
+// evsys_channel_setting_26
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_26
+#define CONF_EVSYS_CHANNEL_SETTINGS_26 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_26
+#ifndef CONF_EDGSEL_26
+#define CONF_EDGSEL_26 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_26
+#ifndef CONF_PATH_26
+#define CONF_PATH_26 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_26
+#ifndef CONF_EVGEN_26
+#define CONF_EVGEN_26 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_26
+#ifndef CONF_OVR_26
+#define CONF_OVR_26 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_26
+#ifndef CONF_EVD_26
+#define CONF_EVD_26 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_26
+#ifndef CONF_ONDEMAND_26
+#define CONF_ONDEMAND_26 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_26
+#ifndef CONF_RUNSTDBY_26
+#define CONF_RUNSTDBY_26 0
+#endif
+
+//
+
+// Channel 27 settings
+// evsys_channel_setting_27
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_27
+#define CONF_EVSYS_CHANNEL_SETTINGS_27 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_27
+#ifndef CONF_EDGSEL_27
+#define CONF_EDGSEL_27 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_27
+#ifndef CONF_PATH_27
+#define CONF_PATH_27 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_27
+#ifndef CONF_EVGEN_27
+#define CONF_EVGEN_27 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_27
+#ifndef CONF_OVR_27
+#define CONF_OVR_27 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_27
+#ifndef CONF_EVD_27
+#define CONF_EVD_27 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_27
+#ifndef CONF_ONDEMAND_27
+#define CONF_ONDEMAND_27 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_27
+#ifndef CONF_RUNSTDBY_27
+#define CONF_RUNSTDBY_27 0
+#endif
+
+//
+
+// Channel 28 settings
+// evsys_channel_setting_28
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_28
+#define CONF_EVSYS_CHANNEL_SETTINGS_28 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_28
+#ifndef CONF_EDGSEL_28
+#define CONF_EDGSEL_28 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_28
+#ifndef CONF_PATH_28
+#define CONF_PATH_28 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_28
+#ifndef CONF_EVGEN_28
+#define CONF_EVGEN_28 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_28
+#ifndef CONF_OVR_28
+#define CONF_OVR_28 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_28
+#ifndef CONF_EVD_28
+#define CONF_EVD_28 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_28
+#ifndef CONF_ONDEMAND_28
+#define CONF_ONDEMAND_28 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_28
+#ifndef CONF_RUNSTDBY_28
+#define CONF_RUNSTDBY_28 0
+#endif
+
+//
+
+// Channel 29 settings
+// evsys_channel_setting_29
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_29
+#define CONF_EVSYS_CHANNEL_SETTINGS_29 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_29
+#ifndef CONF_EDGSEL_29
+#define CONF_EDGSEL_29 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_29
+#ifndef CONF_PATH_29
+#define CONF_PATH_29 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_29
+#ifndef CONF_EVGEN_29
+#define CONF_EVGEN_29 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_29
+#ifndef CONF_OVR_29
+#define CONF_OVR_29 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_29
+#ifndef CONF_EVD_29
+#define CONF_EVD_29 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_29
+#ifndef CONF_ONDEMAND_29
+#define CONF_ONDEMAND_29 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_29
+#ifndef CONF_RUNSTDBY_29
+#define CONF_RUNSTDBY_29 0
+#endif
+
+//
+
+// Channel 30 settings
+// evsys_channel_setting_30
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_30
+#define CONF_EVSYS_CHANNEL_SETTINGS_30 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_30
+#ifndef CONF_EDGSEL_30
+#define CONF_EDGSEL_30 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_30
+#ifndef CONF_PATH_30
+#define CONF_PATH_30 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_30
+#ifndef CONF_EVGEN_30
+#define CONF_EVGEN_30 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_30
+#ifndef CONF_OVR_30
+#define CONF_OVR_30 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_30
+#ifndef CONF_EVD_30
+#define CONF_EVD_30 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_30
+#ifndef CONF_ONDEMAND_30
+#define CONF_ONDEMAND_30 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_30
+#ifndef CONF_RUNSTDBY_30
+#define CONF_RUNSTDBY_30 0
+#endif
+
+//
+
+// Channel 31 settings
+// evsys_channel_setting_31
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_31
+#define CONF_EVSYS_CHANNEL_SETTINGS_31 0
+#endif
+
+// Edge detection
+// Indicates whether channel is enabled in standby sleep mode
+// No event output when using the resynchronized or synchronous path
+// Event is detected on the rising edge of the signal from event generator
+// Event is detected on the falling edge of the signal from event generator
+// Event is detected on the rising and falling edge of the signal from event generator
+// evsys_edgsel_31
+#ifndef CONF_EDGSEL_31
+#define CONF_EDGSEL_31 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// Path selection
+// Indicates which path for the event signal is chosen
+// Synchronous path
+// Resynchronized path
+// Asynchronous path
+// evsys_path_31
+#ifndef CONF_PATH_31
+#define CONF_PATH_31 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// Event generator
+// Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// evsys_evgen_31
+#ifndef CONF_EVGEN_31
+#define CONF_EVGEN_31 0
+#endif
+
+// Overrun channel interrupt
+// Indicates whether overrun channel interrupt is enabled or not
+// evsys_ovr_31
+#ifndef CONF_OVR_31
+#define CONF_OVR_31 0
+#endif
+
+// Event detected interrupt
+// Indicates whether event detected interrupt is enabled or not
+// evsys_evd_31
+#ifndef CONF_EVD_31
+#define CONF_EVD_31 0
+#endif
+
+// On demand clock
+// Indicates whether clock for channel is requested on demand or not
+// evsys_ondemand_31
+#ifndef CONF_ONDEMAND_31
+#define CONF_ONDEMAND_31 0
+#endif
+
+// Run is standby mode
+// Indicates whether channel is enabled in standby sleep mode
+// evsys_runstdby_31
+#ifndef CONF_RUNSTDBY_31
+#define CONF_RUNSTDBY_31 0
+#endif
+
+//
+
+// Event User Security Attribution Settings
+
+//
+
+// RTC events
+// Channel selection for RTC Tamper Event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_0
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_0
+#define CONF_CHANNEL_0 0
+#endif
+//
+
+// PORT events
+// Channel selection for PORT event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_1
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_1
+#define CONF_CHANNEL_1 2
+#endif
+
+// Channel selection for PORT event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_2
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_2
+#define CONF_CHANNEL_2 7
+#endif
+
+// Channel selection for PORT event 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_3
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_3
+#define CONF_CHANNEL_3 6
+#endif
+
+// Channel selection for PORT event 3
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_4
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_4
+#define CONF_CHANNEL_4 9
+#endif
+//
+
+// DMAC events
+// Channel selection for DMAC channel 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_5
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_5
+#define CONF_CHANNEL_5 0
+#endif
+
+// Channel selection for DMAC channel 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_6
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_6
+#define CONF_CHANNEL_6 0
+#endif
+
+// Channel selection for DMAC channel 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_7
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_7
+#define CONF_CHANNEL_7 0
+#endif
+
+// Channel selection for DMAC channel 3
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_8
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_8
+#define CONF_CHANNEL_8 0
+#endif
+
+// Channel selection for DMAC channel 4
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_9
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_9
+#define CONF_CHANNEL_9 1
+#endif
+
+// Channel selection for DMAC channel 5
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_10
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_10
+#define CONF_CHANNEL_10 6
+#endif
+
+// Channel selection for DMAC channel 6
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_11
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_11
+#define CONF_CHANNEL_11 0
+#endif
+
+// Channel selection for DMAC channel 7
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_12
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_12
+#define CONF_CHANNEL_12 3
+#endif
+//
+
+// Reserved
+#ifndef CONF_CHANNEL_13
+#define CONF_CHANNEL_13 0
+#endif
+
+#ifndef CONF_CHANNEL_14
+#define CONF_CHANNEL_14 0
+#endif
+
+#ifndef CONF_CHANNEL_15
+#define CONF_CHANNEL_15 0
+#endif
+
+#ifndef CONF_CHANNEL_16
+#define CONF_CHANNEL_16 0
+#endif
+//
+
+// TCC events
+// Channel selection for TCC0 Event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_17
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_17
+#define CONF_CHANNEL_17 0
+#endif
+
+// Channel selection for TCC0 Event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_18
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_18
+#define CONF_CHANNEL_18 0
+#endif
+
+// Channel selection for TCC0 match/capture 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_19
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_19
+#define CONF_CHANNEL_19 0
+#endif
+
+// Channel selection for TCC0 match/capture 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_20
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_20
+#define CONF_CHANNEL_20 0
+#endif
+
+// Channel selection for TCC0 match/capture 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_21
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_21
+#define CONF_CHANNEL_21 0
+#endif
+
+// Channel selection for TCC0 match/capture 3
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_22
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_22
+#define CONF_CHANNEL_22 0
+#endif
+
+// Channel selection for TCC0 match/capture 4
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_23
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_23
+#define CONF_CHANNEL_23 0
+#endif
+
+// Channel selection for TCC0 match/capture 5
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_24
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_24
+#define CONF_CHANNEL_24 0
+#endif
+
+// Channel selection for TCC1 Event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_25
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_25
+#define CONF_CHANNEL_25 0
+#endif
+
+// Channel selection for TCC1 Event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_26
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_26
+#define CONF_CHANNEL_26 0
+#endif
+
+// Channel selection for TCC1 match/capture 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_27
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_27
+#define CONF_CHANNEL_27 0
+#endif
+
+// Channel selection for TCC1 match/capture 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_28
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_28
+#define CONF_CHANNEL_28 0
+#endif
+
+// Channel selection for TCC1 match/capture 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_29
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_29
+#define CONF_CHANNEL_29 0
+#endif
+
+// Channel selection for TCC1 match/capture 3
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_30
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_30
+#define CONF_CHANNEL_30 0
+#endif
+
+// Channel selection for TCC2 Event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_31
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_31
+#define CONF_CHANNEL_31 0
+#endif
+
+// Channel selection for TCC2 Event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_32
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_32
+#define CONF_CHANNEL_32 0
+#endif
+
+// Channel selection for TCC2 match/capture 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_33
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_33
+#define CONF_CHANNEL_33 0
+#endif
+
+// Channel selection for TCC2 match/capture 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_34
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_34
+#define CONF_CHANNEL_34 0
+#endif
+
+// Channel selection for TCC2 match/capture 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_35
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_35
+#define CONF_CHANNEL_35 0
+#endif
+
+// Channel selection for TCC3 Event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_36
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_36
+#define CONF_CHANNEL_36 0
+#endif
+
+// Channel selection for TCC3 Event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_37
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_37
+#define CONF_CHANNEL_37 0
+#endif
+
+// Channel selection for TCC3 match/capture 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_38
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_38
+#define CONF_CHANNEL_38 0
+#endif
+
+// Channel selection for TCC3 match/capture 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_39
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_39
+#define CONF_CHANNEL_39 0
+#endif
+
+// Channel selection for TCC4 Event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_40
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_40
+#define CONF_CHANNEL_40 0
+#endif
+
+// Channel selection for TCC4 Event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_41
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_41
+#define CONF_CHANNEL_41 0
+#endif
+
+// Channel selection for TCC4 match/capture 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_42
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_42
+#define CONF_CHANNEL_42 0
+#endif
+
+// Channel selection for TCC4 match/capture 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_43
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_43
+#define CONF_CHANNEL_43 0
+#endif
+//
+
+// TC events
+// Channel selection for TC0 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_44
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_44
+#define CONF_CHANNEL_44 0
+#endif
+
+// Channel selection for TC1 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_45
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_45
+#define CONF_CHANNEL_45 0
+#endif
+
+// Channel selection for TC2 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_46
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_46
+#define CONF_CHANNEL_46 12
+#endif
+
+// Channel selection for TC3 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_47
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_47
+#define CONF_CHANNEL_47 0
+#endif
+
+// Channel selection for TC4 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_48
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_48
+#define CONF_CHANNEL_48 13
+#endif
+
+// Channel selection for TC5 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_49
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_49
+#define CONF_CHANNEL_49 0
+#endif
+
+// Channel selection for TC6 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_50
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_50
+#define CONF_CHANNEL_50 0
+#endif
+
+// Channel selection for TC7 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_51
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_51
+#define CONF_CHANNEL_51 0
+#endif
+//
+
+// PDEC events
+// Channel selection for PDEC event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_52
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_52
+#define CONF_CHANNEL_52 0
+#endif
+
+// Channel selection for PDEC event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_53
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_53
+#define CONF_CHANNEL_53 0
+#endif
+
+// Channel selection for PDEC event 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_54
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_54
+#define CONF_CHANNEL_54 0
+#endif
+//
+
+// ADC events
+// Channel selection for ADC0 start conversion event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_55
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_55
+#define CONF_CHANNEL_55 0
+#endif
+
+// Channel selection for ADC0 flush event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_56
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_56
+#define CONF_CHANNEL_56 0
+#endif
+
+// Channel selection for ADC1 start conversion event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_57
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_57
+#define CONF_CHANNEL_57 0
+#endif
+
+// Channel selection for ADC1 flush event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_58
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_58
+#define CONF_CHANNEL_58 0
+#endif
+//
+
+// AC events
+// Channel selection for Start comparator event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_59
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_59
+#define CONF_CHANNEL_59 0
+#endif
+
+// Channel selection for Start comparator event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_60
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_60
+#define CONF_CHANNEL_60 0
+#endif
+//
+
+// DAC events
+// Channel selection for DAC Start event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_61
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_61
+#define CONF_CHANNEL_61 0
+#endif
+
+// Channel selection for DAC Start event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_62
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_62
+#define CONF_CHANNEL_62 0
+#endif
+//
+
+// CCL events
+// Channel selection for CCL input event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_63
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_63
+#define CONF_CHANNEL_63 0
+#endif
+
+// Channel selection for CCL input event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_64
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_64
+#define CONF_CHANNEL_64 0
+#endif
+
+// Channel selection for CCL input event 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_65
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_65
+#define CONF_CHANNEL_65 0
+#endif
+
+// Channel selection for CCL input event 3
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// evsys_channel_66
+// Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_66
+#define CONF_CHANNEL_66 0
+#endif
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_EVSYS_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_gclk_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_gclk_config.h
new file mode 100644
index 0000000..1d59d98
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_gclk_config.h
@@ -0,0 +1,920 @@
+/* Auto-generated config file hpl_gclk_config.h */
+#ifndef HPL_GCLK_CONFIG_H
+#define HPL_GCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Generic clock generator 0 configuration
+// Indicates whether generic clock 0 configuration is enabled or not
+// enable_gclk_gen_0
+#ifndef CONF_GCLK_GENERATOR_0_CONFIG
+#define CONF_GCLK_GENERATOR_0_CONFIG 1
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 0 source
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// Digital Frequency Locked Loop (DFLL48M)
+// Digital Phase Locked Loop (DPLL0)
+// Digital Phase Locked Loop (DPLL1)
+// This defines the clock source for generic clock generator 0
+// gclk_gen_0_oscillator
+#ifndef CONF_GCLK_GEN_0_SOURCE
+#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_0_runstdby
+#ifndef CONF_GCLK_GEN_0_RUNSTDBY
+#define CONF_GCLK_GEN_0_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_0_div_sel
+#ifndef CONF_GCLK_GEN_0_DIVSEL
+#define CONF_GCLK_GEN_0_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_0_oe
+#ifndef CONF_GCLK_GEN_0_OE
+#define CONF_GCLK_GEN_0_OE 1
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_0_oov
+#ifndef CONF_GCLK_GEN_0_OOV
+#define CONF_GCLK_GEN_0_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_0_idc
+#ifndef CONF_GCLK_GEN_0_IDC
+#define CONF_GCLK_GEN_0_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_0_enable
+#ifndef CONF_GCLK_GEN_0_GENEN
+#define CONF_GCLK_GEN_0_GENEN 1
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 0 division <0x0000-0xFFFF>
+// gclk_gen_0_div
+#ifndef CONF_GCLK_GEN_0_DIV
+#define CONF_GCLK_GEN_0_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 1 configuration
+// Indicates whether generic clock 1 configuration is enabled or not
+// enable_gclk_gen_1
+#ifndef CONF_GCLK_GENERATOR_1_CONFIG
+#define CONF_GCLK_GENERATOR_1_CONFIG 1
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 1 source
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator input pad
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// Digital Frequency Locked Loop (DFLL48M)
+// Digital Phase Locked Loop (DPLL0)
+// Digital Phase Locked Loop (DPLL1)
+// This defines the clock source for generic clock generator 1
+// gclk_gen_1_oscillator
+#ifndef CONF_GCLK_GEN_1_SOURCE
+#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_1_runstdby
+#ifndef CONF_GCLK_GEN_1_RUNSTDBY
+#define CONF_GCLK_GEN_1_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_1_div_sel
+#ifndef CONF_GCLK_GEN_1_DIVSEL
+#define CONF_GCLK_GEN_1_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_1_oe
+#ifndef CONF_GCLK_GEN_1_OE
+#define CONF_GCLK_GEN_1_OE 1
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_1_oov
+#ifndef CONF_GCLK_GEN_1_OOV
+#define CONF_GCLK_GEN_1_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_1_idc
+#ifndef CONF_GCLK_GEN_1_IDC
+#define CONF_GCLK_GEN_1_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_1_enable
+#ifndef CONF_GCLK_GEN_1_GENEN
+#define CONF_GCLK_GEN_1_GENEN 1
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 1 division <0x0000-0xFFFF>
+// gclk_gen_1_div
+#ifndef CONF_GCLK_GEN_1_DIV
+#define CONF_GCLK_GEN_1_DIV 24
+#endif
+//
+//
+
+// Generic clock generator 2 configuration
+// Indicates whether generic clock 2 configuration is enabled or not
+// enable_gclk_gen_2
+#ifndef CONF_GCLK_GENERATOR_2_CONFIG
+#define CONF_GCLK_GENERATOR_2_CONFIG 1
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 2 source
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// Digital Frequency Locked Loop (DFLL48M)
+// Digital Phase Locked Loop (DPLL0)
+// Digital Phase Locked Loop (DPLL1)
+// This defines the clock source for generic clock generator 2
+// gclk_gen_2_oscillator
+#ifndef CONF_GCLK_GEN_2_SOURCE
+#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSCULP32K
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_2_runstdby
+#ifndef CONF_GCLK_GEN_2_RUNSTDBY
+#define CONF_GCLK_GEN_2_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_2_div_sel
+#ifndef CONF_GCLK_GEN_2_DIVSEL
+#define CONF_GCLK_GEN_2_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_2_oe
+#ifndef CONF_GCLK_GEN_2_OE
+#define CONF_GCLK_GEN_2_OE 1
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_2_oov
+#ifndef CONF_GCLK_GEN_2_OOV
+#define CONF_GCLK_GEN_2_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_2_idc
+#ifndef CONF_GCLK_GEN_2_IDC
+#define CONF_GCLK_GEN_2_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_2_enable
+#ifndef CONF_GCLK_GEN_2_GENEN
+#define CONF_GCLK_GEN_2_GENEN 1
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 2 division <0x0000-0xFFFF>
+// gclk_gen_2_div
+#ifndef CONF_GCLK_GEN_2_DIV
+#define CONF_GCLK_GEN_2_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 3 configuration
+// Indicates whether generic clock 3 configuration is enabled or not
+// enable_gclk_gen_3
+#ifndef CONF_GCLK_GENERATOR_3_CONFIG
+#define CONF_GCLK_GENERATOR_3_CONFIG 0
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 3 source
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// Digital Frequency Locked Loop (DFLL48M)
+// Digital Phase Locked Loop (DPLL0)
+// Digital Phase Locked Loop (DPLL1)
+// This defines the clock source for generic clock generator 3
+// gclk_gen_3_oscillator
+#ifndef CONF_GCLK_GEN_3_SOURCE
+#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_3_runstdby
+#ifndef CONF_GCLK_GEN_3_RUNSTDBY
+#define CONF_GCLK_GEN_3_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_3_div_sel
+#ifndef CONF_GCLK_GEN_3_DIVSEL
+#define CONF_GCLK_GEN_3_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_3_oe
+#ifndef CONF_GCLK_GEN_3_OE
+#define CONF_GCLK_GEN_3_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_3_oov
+#ifndef CONF_GCLK_GEN_3_OOV
+#define CONF_GCLK_GEN_3_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_3_idc
+#ifndef CONF_GCLK_GEN_3_IDC
+#define CONF_GCLK_GEN_3_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_3_enable
+#ifndef CONF_GCLK_GEN_3_GENEN
+#define CONF_GCLK_GEN_3_GENEN 0
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 3 division <0x0000-0xFFFF>
+// gclk_gen_3_div
+#ifndef CONF_GCLK_GEN_3_DIV
+#define CONF_GCLK_GEN_3_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 4 configuration
+// Indicates whether generic clock 4 configuration is enabled or not
+// enable_gclk_gen_4
+#ifndef CONF_GCLK_GENERATOR_4_CONFIG
+#define CONF_GCLK_GENERATOR_4_CONFIG 0
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 4 source
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// Digital Frequency Locked Loop (DFLL48M)
+// Digital Phase Locked Loop (DPLL0)
+// Digital Phase Locked Loop (DPLL1)
+// This defines the clock source for generic clock generator 4
+// gclk_gen_4_oscillator
+#ifndef CONF_GCLK_GEN_4_SOURCE
+#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_4_runstdby
+#ifndef CONF_GCLK_GEN_4_RUNSTDBY
+#define CONF_GCLK_GEN_4_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_4_div_sel
+#ifndef CONF_GCLK_GEN_4_DIVSEL
+#define CONF_GCLK_GEN_4_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_4_oe
+#ifndef CONF_GCLK_GEN_4_OE
+#define CONF_GCLK_GEN_4_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_4_oov
+#ifndef CONF_GCLK_GEN_4_OOV
+#define CONF_GCLK_GEN_4_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_4_idc
+#ifndef CONF_GCLK_GEN_4_IDC
+#define CONF_GCLK_GEN_4_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_4_enable
+#ifndef CONF_GCLK_GEN_4_GENEN
+#define CONF_GCLK_GEN_4_GENEN 0
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 4 division <0x0000-0xFFFF>
+// gclk_gen_4_div
+#ifndef CONF_GCLK_GEN_4_DIV
+#define CONF_GCLK_GEN_4_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 5 configuration
+// Indicates whether generic clock 5 configuration is enabled or not
+// enable_gclk_gen_5
+#ifndef CONF_GCLK_GENERATOR_5_CONFIG
+#define CONF_GCLK_GENERATOR_5_CONFIG 0
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 5 source
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// Digital Frequency Locked Loop (DFLL48M)
+// Digital Phase Locked Loop (DPLL0)
+// Digital Phase Locked Loop (DPLL1)
+// This defines the clock source for generic clock generator 5
+// gclk_gen_5_oscillator
+#ifndef CONF_GCLK_GEN_5_SOURCE
+#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_5_runstdby
+#ifndef CONF_GCLK_GEN_5_RUNSTDBY
+#define CONF_GCLK_GEN_5_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_5_div_sel
+#ifndef CONF_GCLK_GEN_5_DIVSEL
+#define CONF_GCLK_GEN_5_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_5_oe
+#ifndef CONF_GCLK_GEN_5_OE
+#define CONF_GCLK_GEN_5_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_5_oov
+#ifndef CONF_GCLK_GEN_5_OOV
+#define CONF_GCLK_GEN_5_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_5_idc
+#ifndef CONF_GCLK_GEN_5_IDC
+#define CONF_GCLK_GEN_5_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_5_enable
+#ifndef CONF_GCLK_GEN_5_GENEN
+#define CONF_GCLK_GEN_5_GENEN 0
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 5 division <0x0000-0xFFFF>
+// gclk_gen_5_div
+#ifndef CONF_GCLK_GEN_5_DIV
+#define CONF_GCLK_GEN_5_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 6 configuration
+// Indicates whether generic clock 6 configuration is enabled or not
+// enable_gclk_gen_6
+#ifndef CONF_GCLK_GENERATOR_6_CONFIG
+#define CONF_GCLK_GENERATOR_6_CONFIG 0
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 6 source
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// Digital Frequency Locked Loop (DFLL48M)
+// Digital Phase Locked Loop (DPLL0)
+// Digital Phase Locked Loop (DPLL1)
+// This defines the clock source for generic clock generator 6
+// gclk_gen_6_oscillator
+#ifndef CONF_GCLK_GEN_6_SOURCE
+#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_6_runstdby
+#ifndef CONF_GCLK_GEN_6_RUNSTDBY
+#define CONF_GCLK_GEN_6_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_6_div_sel
+#ifndef CONF_GCLK_GEN_6_DIVSEL
+#define CONF_GCLK_GEN_6_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_6_oe
+#ifndef CONF_GCLK_GEN_6_OE
+#define CONF_GCLK_GEN_6_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_6_oov
+#ifndef CONF_GCLK_GEN_6_OOV
+#define CONF_GCLK_GEN_6_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_6_idc
+#ifndef CONF_GCLK_GEN_6_IDC
+#define CONF_GCLK_GEN_6_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_6_enable
+#ifndef CONF_GCLK_GEN_6_GENEN
+#define CONF_GCLK_GEN_6_GENEN 0
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 6 division <0x0000-0xFFFF>
+// gclk_gen_6_div
+#ifndef CONF_GCLK_GEN_6_DIV
+#define CONF_GCLK_GEN_6_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 7 configuration
+// Indicates whether generic clock 7 configuration is enabled or not
+// enable_gclk_gen_7
+#ifndef CONF_GCLK_GENERATOR_7_CONFIG
+#define CONF_GCLK_GENERATOR_7_CONFIG 0
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 7 source
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// Digital Frequency Locked Loop (DFLL48M)
+// Digital Phase Locked Loop (DPLL0)
+// Digital Phase Locked Loop (DPLL1)
+// This defines the clock source for generic clock generator 7
+// gclk_gen_7_oscillator
+#ifndef CONF_GCLK_GEN_7_SOURCE
+#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_7_runstdby
+#ifndef CONF_GCLK_GEN_7_RUNSTDBY
+#define CONF_GCLK_GEN_7_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_7_div_sel
+#ifndef CONF_GCLK_GEN_7_DIVSEL
+#define CONF_GCLK_GEN_7_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_7_oe
+#ifndef CONF_GCLK_GEN_7_OE
+#define CONF_GCLK_GEN_7_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_7_oov
+#ifndef CONF_GCLK_GEN_7_OOV
+#define CONF_GCLK_GEN_7_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_7_idc
+#ifndef CONF_GCLK_GEN_7_IDC
+#define CONF_GCLK_GEN_7_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_7_enable
+#ifndef CONF_GCLK_GEN_7_GENEN
+#define CONF_GCLK_GEN_7_GENEN 0
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 7 division <0x0000-0xFFFF>
+// gclk_gen_7_div
+#ifndef CONF_GCLK_GEN_7_DIV
+#define CONF_GCLK_GEN_7_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 8 configuration
+// Indicates whether generic clock 8 configuration is enabled or not
+// enable_gclk_gen_8
+#ifndef CONF_GCLK_GENERATOR_8_CONFIG
+#define CONF_GCLK_GENERATOR_8_CONFIG 0
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 8 source
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// Digital Frequency Locked Loop (DFLL48M)
+// Digital Phase Locked Loop (DPLL0)
+// Digital Phase Locked Loop (DPLL1)
+// This defines the clock source for generic clock generator 8
+// gclk_gen_8_oscillator
+#ifndef CONF_GCLK_GEN_8_SOURCE
+#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_8_runstdby
+#ifndef CONF_GCLK_GEN_8_RUNSTDBY
+#define CONF_GCLK_GEN_8_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_8_div_sel
+#ifndef CONF_GCLK_GEN_8_DIVSEL
+#define CONF_GCLK_GEN_8_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_8_oe
+#ifndef CONF_GCLK_GEN_8_OE
+#define CONF_GCLK_GEN_8_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_8_oov
+#ifndef CONF_GCLK_GEN_8_OOV
+#define CONF_GCLK_GEN_8_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_8_idc
+#ifndef CONF_GCLK_GEN_8_IDC
+#define CONF_GCLK_GEN_8_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_8_enable
+#ifndef CONF_GCLK_GEN_8_GENEN
+#define CONF_GCLK_GEN_8_GENEN 0
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 8 division <0x0000-0xFFFF>
+// gclk_gen_8_div
+#ifndef CONF_GCLK_GEN_8_DIV
+#define CONF_GCLK_GEN_8_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 9 configuration
+// Indicates whether generic clock 9 configuration is enabled or not
+// enable_gclk_gen_9
+#ifndef CONF_GCLK_GENERATOR_9_CONFIG
+#define CONF_GCLK_GENERATOR_9_CONFIG 0
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 9 source
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// Digital Frequency Locked Loop (DFLL48M)
+// Digital Phase Locked Loop (DPLL0)
+// Digital Phase Locked Loop (DPLL1)
+// This defines the clock source for generic clock generator 9
+// gclk_gen_9_oscillator
+#ifndef CONF_GCLK_GEN_9_SOURCE
+#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_9_runstdby
+#ifndef CONF_GCLK_GEN_9_RUNSTDBY
+#define CONF_GCLK_GEN_9_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_9_div_sel
+#ifndef CONF_GCLK_GEN_9_DIVSEL
+#define CONF_GCLK_GEN_9_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_9_oe
+#ifndef CONF_GCLK_GEN_9_OE
+#define CONF_GCLK_GEN_9_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_9_oov
+#ifndef CONF_GCLK_GEN_9_OOV
+#define CONF_GCLK_GEN_9_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_9_idc
+#ifndef CONF_GCLK_GEN_9_IDC
+#define CONF_GCLK_GEN_9_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_9_enable
+#ifndef CONF_GCLK_GEN_9_GENEN
+#define CONF_GCLK_GEN_9_GENEN 0
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 9 division <0x0000-0xFFFF>
+// gclk_gen_9_div
+#ifndef CONF_GCLK_GEN_9_DIV
+#define CONF_GCLK_GEN_9_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 10 configuration
+// Indicates whether generic clock 10 configuration is enabled or not
+// enable_gclk_gen_10
+#ifndef CONF_GCLK_GENERATOR_10_CONFIG
+#define CONF_GCLK_GENERATOR_10_CONFIG 0
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 10 source
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// Digital Frequency Locked Loop (DFLL48M)
+// Digital Phase Locked Loop (DPLL0)
+// Digital Phase Locked Loop (DPLL1)
+// This defines the clock source for generic clock generator 10
+// gclk_gen_10_oscillator
+#ifndef CONF_GCLK_GEN_10_SOURCE
+#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_10_runstdby
+#ifndef CONF_GCLK_GEN_10_RUNSTDBY
+#define CONF_GCLK_GEN_10_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_10_div_sel
+#ifndef CONF_GCLK_GEN_10_DIVSEL
+#define CONF_GCLK_GEN_10_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_10_oe
+#ifndef CONF_GCLK_GEN_10_OE
+#define CONF_GCLK_GEN_10_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_10_oov
+#ifndef CONF_GCLK_GEN_10_OOV
+#define CONF_GCLK_GEN_10_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_10_idc
+#ifndef CONF_GCLK_GEN_10_IDC
+#define CONF_GCLK_GEN_10_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_10_enable
+#ifndef CONF_GCLK_GEN_10_GENEN
+#define CONF_GCLK_GEN_10_GENEN 0
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 10 division <0x0000-0xFFFF>
+// gclk_gen_10_div
+#ifndef CONF_GCLK_GEN_10_DIV
+#define CONF_GCLK_GEN_10_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 11 configuration
+// Indicates whether generic clock 11 configuration is enabled or not
+// enable_gclk_gen_11
+#ifndef CONF_GCLK_GENERATOR_11_CONFIG
+#define CONF_GCLK_GENERATOR_11_CONFIG 0
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 11 source
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// Digital Frequency Locked Loop (DFLL48M)
+// Digital Phase Locked Loop (DPLL0)
+// Digital Phase Locked Loop (DPLL1)
+// This defines the clock source for generic clock generator 11
+// gclk_gen_11_oscillator
+#ifndef CONF_GCLK_GEN_11_SOURCE
+#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_11_runstdby
+#ifndef CONF_GCLK_GEN_11_RUNSTDBY
+#define CONF_GCLK_GEN_11_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_11_div_sel
+#ifndef CONF_GCLK_GEN_11_DIVSEL
+#define CONF_GCLK_GEN_11_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_11_oe
+#ifndef CONF_GCLK_GEN_11_OE
+#define CONF_GCLK_GEN_11_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_11_oov
+#ifndef CONF_GCLK_GEN_11_OOV
+#define CONF_GCLK_GEN_11_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_11_idc
+#ifndef CONF_GCLK_GEN_11_IDC
+#define CONF_GCLK_GEN_11_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_11_enable
+#ifndef CONF_GCLK_GEN_11_GENEN
+#define CONF_GCLK_GEN_11_GENEN 0
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 11 division <0x0000-0xFFFF>
+// gclk_gen_11_div
+#ifndef CONF_GCLK_GEN_11_DIV
+#define CONF_GCLK_GEN_11_DIV 1
+#endif
+//
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_GCLK_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_mclk_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_mclk_config.h
new file mode 100644
index 0000000..a5a7de5
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_mclk_config.h
@@ -0,0 +1,104 @@
+/* Auto-generated config file hpl_mclk_config.h */
+#ifndef HPL_MCLK_CONFIG_H
+#define HPL_MCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include
+
+// System Configuration
+// Indicates whether configuration for system is enabled or not
+// enable_cpu_clock
+#ifndef CONF_SYSTEM_CONFIG
+#define CONF_SYSTEM_CONFIG 1
+#endif
+
+// Basic settings
+// CPU Clock source
+// Generic clock generator 0
+// This defines the clock source for the CPU
+// cpu_clock_source
+#ifndef CONF_CPU_SRC
+#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// CPU Clock Division Factor
+// 1
+// 2
+// 4
+// 8
+// 16
+// 32
+// 64
+// 128
+// Prescalar for CPU clock
+// cpu_div
+#ifndef CONF_MCLK_CPUDIV
+#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
+#endif
+// Low Power Clock Division
+// Divide by 1
+// Divide by 2
+// Divide by 4
+// Divide by 8
+// Divide by 16
+// Divide by 32
+// Divide by 64
+// Divide by 128
+// mclk_arch_lpdiv
+#ifndef CONF_MCLK_LPDIV
+#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
+#endif
+
+// Backup Clock Division
+// Divide by 1
+// Divide by 2
+// Divide by 4
+// Divide by 8
+// Divide by 16
+// Divide by 32
+// Divide by 64
+// Divide by 128
+// mclk_arch_bupdiv
+#ifndef CONF_MCLK_BUPDIV
+#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
+#endif
+// High-Speed Clock Division
+// Divide by 1
+// mclk_arch_hsdiv
+#ifndef CONF_MCLK_HSDIV
+#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
+#endif
+//
+
+// NVM Settings
+// NVM Wait States
+// These bits select the number of wait states for a read operation.
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// nvm_wait_states
+#ifndef CONF_NVM_WAIT_STATE
+#define CONF_NVM_WAIT_STATE 0
+#endif
+
+//
+
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_MCLK_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_osc32kctrl_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_osc32kctrl_config.h
new file mode 100644
index 0000000..e7fddd2
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_osc32kctrl_config.h
@@ -0,0 +1,165 @@
+/* Auto-generated config file hpl_osc32kctrl_config.h */
+#ifndef HPL_OSC32KCTRL_CONFIG_H
+#define HPL_OSC32KCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// RTC Source configuration
+// enable_rtc_source
+#ifndef CONF_RTCCTRL_CONFIG
+#define CONF_RTCCTRL_CONFIG 0
+#endif
+
+// RTC source control
+// RTC Clock Source Selection
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// This defines the clock source for RTC
+// rtc_source_oscillator
+#ifndef CONF_RTCCTRL_SRC
+#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
+#endif
+
+// Use 1 kHz output
+// rtc_1khz_selection
+#ifndef CONF_RTCCTRL_1KHZ
+
+#define CONF_RTCCTRL_1KHZ 0
+
+#endif
+
+#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
+#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
+#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
+#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
+#else
+#error unexpected CONF_RTCCTRL_SRC
+#endif
+
+//
+//
+
+// 32kHz External Crystal Oscillator Configuration
+// Indicates whether configuration for External 32K Osc is enabled or not
+// enable_xosc32k
+#ifndef CONF_XOSC32K_CONFIG
+#define CONF_XOSC32K_CONFIG 0
+#endif
+
+// 32kHz External Crystal Oscillator Control
+// Oscillator enable
+// Indicates whether 32kHz External Crystal Oscillator is enabled or not
+// xosc32k_arch_enable
+#ifndef CONF_XOSC32K_ENABLE
+#define CONF_XOSC32K_ENABLE 0
+#endif
+
+// Start-Up Time
+// <0x0=>62592us
+// <0x1=>125092us
+// <0x2=>500092us
+// <0x3=>1000092us
+// <0x4=>2000092us
+// <0x5=>4000092us
+// <0x6=>8000092us
+// xosc32k_arch_startup
+#ifndef CONF_XOSC32K_STARTUP
+#define CONF_XOSC32K_STARTUP 0x0
+#endif
+
+// On Demand Control
+// Indicates whether On Demand Control is enabled or not
+// xosc32k_arch_ondemand
+#ifndef CONF_XOSC32K_ONDEMAND
+#define CONF_XOSC32K_ONDEMAND 1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// xosc32k_arch_runstdby
+#ifndef CONF_XOSC32K_RUNSTDBY
+#define CONF_XOSC32K_RUNSTDBY 0
+#endif
+
+// 1kHz Output Enable
+// Indicates whether 1kHz Output is enabled or not
+// xosc32k_arch_en1k
+#ifndef CONF_XOSC32K_EN1K
+#define CONF_XOSC32K_EN1K 0
+#endif
+
+// 32kHz Output Enable
+// Indicates whether 32kHz Output is enabled or not
+// xosc32k_arch_en32k
+#ifndef CONF_XOSC32K_EN32K
+#define CONF_XOSC32K_EN32K 0
+#endif
+
+// Clock Switch Back
+// Indicates whether Clock Switch Back is enabled or not
+// xosc32k_arch_swben
+#ifndef CONF_XOSC32K_SWBEN
+#define CONF_XOSC32K_SWBEN 0
+#endif
+
+// Clock Failure Detector
+// Indicates whether Clock Failure Detector is enabled or not
+// xosc32k_arch_cfden
+#ifndef CONF_XOSC32K_CFDEN
+#define CONF_XOSC32K_CFDEN 0
+#endif
+
+// Clock Failure Detector Event Out
+// Indicates whether Clock Failure Detector Event Out is enabled or not
+// xosc32k_arch_cfdeo
+#ifndef CONF_XOSC32K_CFDEO
+#define CONF_XOSC32K_CFDEO 0
+#endif
+
+// Crystal connected to XIN32/XOUT32 Enable
+// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// xosc32k_arch_xtalen
+#ifndef CONF_XOSC32K_XTALEN
+#define CONF_XOSC32K_XTALEN 1
+#endif
+
+// Control Gain Mode
+// <0x0=>Low Power mode
+// <0x1=>Standard mode
+// <0x2=>High Speed mode
+// xosc32k_arch_cgm
+#ifndef CONF_XOSC32K_CGM
+#define CONF_XOSC32K_CGM 0x1
+#endif
+
+//
+//
+
+// 32kHz Ultra Low Power Internal Oscillator Configuration
+// Indicates whether configuration for OSCULP32K is enabled or not
+// enable_osculp32k
+#ifndef CONF_OSCULP32K_CONFIG
+#define CONF_OSCULP32K_CONFIG 1
+#endif
+
+// 32kHz Ultra Low Power Internal Oscillator Control
+
+// Oscillator Calibration Control
+// Indicates whether Oscillator Calibration is enabled or not
+// osculp32k_calib_enable
+#ifndef CONF_OSCULP32K_CALIB_ENABLE
+#define CONF_OSCULP32K_CALIB_ENABLE 0
+#endif
+
+// Oscillator Calibration <0x0-0x3F>
+// osculp32k_calib
+#ifndef CONF_OSCULP32K_CALIB
+#define CONF_OSCULP32K_CALIB 0x0
+#endif
+
+//
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_OSC32KCTRL_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_oscctrl_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_oscctrl_config.h
new file mode 100644
index 0000000..b62c2bc
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_oscctrl_config.h
@@ -0,0 +1,640 @@
+/* Auto-generated config file hpl_oscctrl_config.h */
+#ifndef HPL_OSCCTRL_CONFIG_H
+#define HPL_OSCCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// External Multipurpose Crystal Oscillator Configuration
+// Indicates whether configuration for XOSC0 is enabled or not
+// enable_xosc0
+#ifndef CONF_XOSC0_CONFIG
+#define CONF_XOSC0_CONFIG 0
+#endif
+
+// Frequency <8000000-48000000>
+// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
+// xosc0_frequency
+#ifndef CONF_XOSC_FREQUENCY
+#define CONF_XOSC0_FREQUENCY 12000000
+#endif
+
+// External Multipurpose Crystal Oscillator Control
+// Oscillator enable
+// Indicates whether External Multipurpose Crystal Oscillator is enabled or not
+// xosc0_arch_enable
+#ifndef CONF_XOSC0_ENABLE
+#define CONF_XOSC0_ENABLE 0
+#endif
+
+// Start-Up Time
+// <0x0=>31us
+// <0x1=>61us
+// <0x2=>122us
+// <0x3=>244us
+// <0x4=>488us
+// <0x5=>977us
+// <0x6=>1953us
+// <0x7=>3906us
+// <0x8=>7813us
+// <0x9=>15625us
+// <0xA=>31250us
+// <0xB=>62500us
+// <0xC=>125000us
+// <0xD=>250000us
+// <0xE=>500000us
+// <0xF=>1000000us
+// xosc0_arch_startup
+#ifndef CONF_XOSC0_STARTUP
+#define CONF_XOSC0_STARTUP 0
+#endif
+
+// Clock Switch Back
+// Indicates whether Clock Switch Back is enabled or not
+// xosc0_arch_swben
+#ifndef CONF_XOSC0_SWBEN
+#define CONF_XOSC0_SWBEN 0
+#endif
+
+// Clock Failure Detector
+// Indicates whether Clock Failure Detector is enabled or not
+// xosc0_arch_cfden
+#ifndef CONF_XOSC0_CFDEN
+#define CONF_XOSC0_CFDEN 0
+#endif
+
+// Automatic Loop Control Enable
+// Indicates whether Automatic Loop Control is enabled or not
+// xosc0_arch_enalc
+#ifndef CONF_XOSC0_ENALC
+#define CONF_XOSC0_ENALC 0
+#endif
+
+// Low Buffer Gain Enable
+// Indicates whether Low Buffer Gain is enabled or not
+// xosc0_arch_lowbufgain
+#ifndef CONF_XOSC0_LOWBUFGAIN
+#define CONF_XOSC0_LOWBUFGAIN 0
+#endif
+
+// On Demand Control
+// Indicates whether On Demand Control is enabled or not
+// xosc0_arch_ondemand
+#ifndef CONF_XOSC0_ONDEMAND
+#define CONF_XOSC0_ONDEMAND 0
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// xosc0_arch_runstdby
+#ifndef CONF_XOSC0_RUNSTDBY
+#define CONF_XOSC0_RUNSTDBY 0
+#endif
+
+// Crystal connected to XIN/XOUT Enable
+// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// xosc0_arch_xtalen
+#ifndef CONF_XOSC0_XTALEN
+#define CONF_XOSC0_XTALEN 0
+#endif
+//
+//
+
+#if CONF_XOSC0_FREQUENCY >= 32000000
+#define CONF_XOSC0_CFDPRESC 0x0
+#define CONF_XOSC0_IMULT 0x7
+#define CONF_XOSC0_IPTAT 0x3
+#elif CONF_XOSC0_FREQUENCY >= 24000000
+#define CONF_XOSC0_CFDPRESC 0x1
+#define CONF_XOSC0_IMULT 0x6
+#define CONF_XOSC0_IPTAT 0x3
+#elif CONF_XOSC0_FREQUENCY >= 16000000
+#define CONF_XOSC0_CFDPRESC 0x2
+#define CONF_XOSC0_IMULT 0x5
+#define CONF_XOSC0_IPTAT 0x3
+#elif CONF_XOSC0_FREQUENCY >= 8000000
+#define CONF_XOSC0_CFDPRESC 0x3
+#define CONF_XOSC0_IMULT 0x4
+#define CONF_XOSC0_IPTAT 0x3
+#endif
+
+// External Multipurpose Crystal Oscillator Configuration
+// Indicates whether configuration for XOSC1 is enabled or not
+// enable_xosc1
+#ifndef CONF_XOSC1_CONFIG
+#define CONF_XOSC1_CONFIG 0
+#endif
+
+// Frequency <8000000-48000000>
+// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
+// xosc1_frequency
+#ifndef CONF_XOSC_FREQUENCY
+#define CONF_XOSC1_FREQUENCY 12000000
+#endif
+
+// External Multipurpose Crystal Oscillator Control
+// Oscillator enable
+// Indicates whether External Multipurpose Crystal Oscillator is enabled or not
+// xosc1_arch_enable
+#ifndef CONF_XOSC1_ENABLE
+#define CONF_XOSC1_ENABLE 0
+#endif
+
+// Start-Up Time
+// <0x0=>31us
+// <0x1=>61us
+// <0x2=>122us
+// <0x3=>244us
+// <0x4=>488us
+// <0x5=>977us
+// <0x6=>1953us
+// <0x7=>3906us
+// <0x8=>7813us
+// <0x9=>15625us
+// <0xA=>31250us
+// <0xB=>62500us
+// <0xC=>125000us
+// <0xD=>250000us
+// <0xE=>500000us
+// <0xF=>1000000us
+// xosc1_arch_startup
+#ifndef CONF_XOSC1_STARTUP
+#define CONF_XOSC1_STARTUP 0
+#endif
+
+// Clock Switch Back
+// Indicates whether Clock Switch Back is enabled or not
+// xosc1_arch_swben
+#ifndef CONF_XOSC1_SWBEN
+#define CONF_XOSC1_SWBEN 0
+#endif
+
+// Clock Failure Detector
+// Indicates whether Clock Failure Detector is enabled or not
+// xosc1_arch_cfden
+#ifndef CONF_XOSC1_CFDEN
+#define CONF_XOSC1_CFDEN 0
+#endif
+
+// Automatic Loop Control Enable
+// Indicates whether Automatic Loop Control is enabled or not
+// xosc1_arch_enalc
+#ifndef CONF_XOSC1_ENALC
+#define CONF_XOSC1_ENALC 0
+#endif
+
+// Low Buffer Gain Enable
+// Indicates whether Low Buffer Gain is enabled or not
+// xosc1_arch_lowbufgain
+#ifndef CONF_XOSC1_LOWBUFGAIN
+#define CONF_XOSC1_LOWBUFGAIN 0
+#endif
+
+// On Demand Control
+// Indicates whether On Demand Control is enabled or not
+// xosc1_arch_ondemand
+#ifndef CONF_XOSC1_ONDEMAND
+#define CONF_XOSC1_ONDEMAND 0
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// xosc1_arch_runstdby
+#ifndef CONF_XOSC1_RUNSTDBY
+#define CONF_XOSC1_RUNSTDBY 0
+#endif
+
+// Crystal connected to XIN/XOUT Enable
+// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// xosc1_arch_xtalen
+#ifndef CONF_XOSC1_XTALEN
+#define CONF_XOSC1_XTALEN 1
+#endif
+//
+//
+
+#if CONF_XOSC1_FREQUENCY >= 32000000
+#define CONF_XOSC1_CFDPRESC 0x0
+#define CONF_XOSC1_IMULT 0x7
+#define CONF_XOSC1_IPTAT 0x3
+#elif CONF_XOSC1_FREQUENCY >= 24000000
+#define CONF_XOSC1_CFDPRESC 0x1
+#define CONF_XOSC1_IMULT 0x6
+#define CONF_XOSC1_IPTAT 0x3
+#elif CONF_XOSC1_FREQUENCY >= 16000000
+#define CONF_XOSC1_CFDPRESC 0x2
+#define CONF_XOSC1_IMULT 0x5
+#define CONF_XOSC1_IPTAT 0x3
+#elif CONF_XOSC1_FREQUENCY >= 8000000
+#define CONF_XOSC1_CFDPRESC 0x3
+#define CONF_XOSC1_IMULT 0x4
+#define CONF_XOSC1_IPTAT 0x3
+#endif
+
+// DFLL Configuration
+// Indicates whether configuration for DFLL is enabled or not
+// enable_dfll
+#ifndef CONF_DFLL_CONFIG
+#define CONF_DFLL_CONFIG 1
+#endif
+
+// Reference Clock Source
+// Generic clock generator 0
+// Generic clock generator 1
+// Generic clock generator 2
+// Generic clock generator 3
+// Generic clock generator 4
+// Generic clock generator 5
+// Generic clock generator 6
+// Generic clock generator 7
+// Generic clock generator 8
+// Generic clock generator 9
+// Generic clock generator 10
+// Generic clock generator 11
+// Select the clock source
+// dfll_ref_clock
+#ifndef CONF_DFLL_GCLK
+#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK2_Val
+#endif
+
+// Digital Frequency Locked Loop Control
+// DFLL Enable
+// Indicates whether DFLL is enabled or not
+// dfll_arch_enable
+#ifndef CONF_DFLL_ENABLE
+#define CONF_DFLL_ENABLE 1
+#endif
+
+// On Demand Control
+// Indicates whether On Demand Control is enabled or not
+// dfll_arch_ondemand
+#ifndef CONF_DFLL_ONDEMAND
+#define CONF_DFLL_ONDEMAND 0
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// dfll_arch_runstdby
+#ifndef CONF_DFLL_RUNSTDBY
+#define CONF_DFLL_RUNSTDBY 0
+#endif
+
+// USB Clock Recovery Mode
+// Indicates whether USB Clock Recovery Mode is enabled or not
+// dfll_arch_usbcrm
+#ifndef CONF_DFLL_USBCRM
+#define CONF_DFLL_USBCRM 0
+#endif
+
+// Wait Lock
+// Indicates whether Wait Lock is enabled or not
+// dfll_arch_waitlock
+#ifndef CONF_DFLL_WAITLOCK
+#define CONF_DFLL_WAITLOCK 1
+#endif
+
+// Bypass Coarse Lock
+// Indicates whether Bypass Coarse Lock is enabled or not
+// dfll_arch_bplckc
+#ifndef CONF_DFLL_BPLCKC
+#define CONF_DFLL_BPLCKC 0
+#endif
+
+// Quick Lock Disable
+// Indicates whether Quick Lock Disable is enabled or not
+// dfll_arch_qldis
+#ifndef CONF_DFLL_QLDIS
+#define CONF_DFLL_QLDIS 0
+#endif
+
+// Chill Cycle Disable
+// Indicates whether Chill Cycle Disable is enabled or not
+// dfll_arch_ccdis
+#ifndef CONF_DFLL_CCDIS
+#define CONF_DFLL_CCDIS 0
+#endif
+
+// Lose Lock After Wake
+// Indicates whether Lose Lock After Wake is enabled or not
+// dfll_arch_llaw
+#ifndef CONF_DFLL_LLAW
+#define CONF_DFLL_LLAW 0
+#endif
+
+// Stable DFLL Frequency
+// Indicates whether Stable DFLL Frequency is enabled or not
+// dfll_arch_stable
+#ifndef CONF_DFLL_STABLE
+#define CONF_DFLL_STABLE 0
+#endif
+
+// Operating Mode Selection
+// <0=>Open Loop Mode
+// <1=>Closed Loop Mode
+// dfll_mode
+#ifndef CONF_DFLL_MODE
+#define CONF_DFLL_MODE 0x0
+#endif
+
+// Coarse Maximum Step <0x0-0x1F>
+// dfll_arch_cstep
+#ifndef CONF_DFLL_CSTEP
+#define CONF_DFLL_CSTEP 0x1
+#endif
+
+// Fine Maximum Step <0x0-0xFF>
+// dfll_arch_fstep
+#ifndef CONF_DFLL_FSTEP
+#define CONF_DFLL_FSTEP 0x1
+#endif
+
+// DFLL Multiply Factor <0x0-0xFFFF>
+// dfll_mul
+#ifndef CONF_DFLL_MUL
+#define CONF_DFLL_MUL 0x0
+#endif
+
+// DFLL Calibration Overwrite
+// Indicates whether Overwrite Calibration value of DFLL
+// dfll_arch_calibration
+#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
+#define CONF_DFLL_OVERWRITE_CALIBRATION 0
+#endif
+
+// Coarse Value <0x0-0x3F>
+// dfll_arch_coarse
+#ifndef CONF_DFLL_COARSE
+#define CONF_DFLL_COARSE (0x1f / 4)
+#endif
+
+// Fine Value <0x0-0xFF>
+// dfll_arch_fine
+#ifndef CONF_DFLL_FINE
+#define CONF_DFLL_FINE (0x80)
+#endif
+
+//
+
+//
+
+//
+
+// FDPLL0 Configuration
+// Indicates whether configuration for FDPLL0 is enabled or not
+// enable_fdpll0
+#ifndef CONF_FDPLL0_CONFIG
+#define CONF_FDPLL0_CONFIG 0
+#endif
+
+// Reference Clock Source
+// 32kHz External Crystal Oscillator (XOSC32K)
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator 0
+// Generic clock generator 1
+// Generic clock generator 2
+// Generic clock generator 3
+// Generic clock generator 4
+// Generic clock generator 5
+// Generic clock generator 6
+// Generic clock generator 7
+// Generic clock generator 8
+// Generic clock generator 9
+// Generic clock generator 10
+// Generic clock generator 11
+// Select the clock source.
+// fdpll0_ref_clock
+#ifndef CONF_FDPLL0_GCLK
+#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// Digital Phase Locked Loop Control
+// Enable
+// Indicates whether Digital Phase Locked Loop is enabled or not
+// fdpll0_arch_enable
+#ifndef CONF_FDPLL0_ENABLE
+#define CONF_FDPLL0_ENABLE 0
+#endif
+
+// On Demand Control
+// Indicates whether On Demand Control is enabled or not
+// fdpll0_arch_ondemand
+#ifndef CONF_FDPLL0_ONDEMAND
+#define CONF_FDPLL0_ONDEMAND 0
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// fdpll0_arch_runstdby
+#ifndef CONF_FDPLL0_RUNSTDBY
+#define CONF_FDPLL0_RUNSTDBY 0
+#endif
+
+// Loop Divider Ratio Fractional Part <0x0-0x1F>
+// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
+// fdpll0_ldrfrac
+#ifndef CONF_FDPLL0_LDRFRAC
+#define CONF_FDPLL0_LDRFRAC 0xd
+#endif
+
+// Loop Divider Ratio Integer Part <0x0-0x1FFF>
+// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
+// fdpll0_ldr
+#ifndef CONF_FDPLL0_LDR
+#define CONF_FDPLL0_LDR 0x5b7
+#endif
+
+// Clock Divider <0x0-0x7FF>
+// This Clock divider is only for XOSC clock input to DPLL
+// fdpll0_clock_div
+#ifndef CONF_FDPLL0_DIV
+#define CONF_FDPLL0_DIV 0x0
+#endif
+
+// DCO Filter Enable
+// Indicates whether DCO Filter Enable is enabled or not
+// fdpll0_arch_dcoen
+#ifndef CONF_FDPLL0_DCOEN
+#define CONF_FDPLL0_DCOEN 0
+#endif
+
+// Sigma-Delta DCO Filter Selection <0x0-0x7>
+// fdpll0_clock_dcofilter
+#ifndef CONF_FDPLL0_DCOFILTER
+#define CONF_FDPLL0_DCOFILTER 0x0
+#endif
+
+// Lock Bypass
+// Indicates whether Lock Bypass is enabled or not
+// fdpll0_arch_lbypass
+#ifndef CONF_FDPLL0_LBYPASS
+#define CONF_FDPLL0_LBYPASS 0
+#endif
+
+// Lock Time
+// <0x0=>No time-out, automatic lock
+// <0x4=>The Time-out if no lock within 800 us
+// <0x5=>The Time-out if no lock within 900 us
+// <0x6=>The Time-out if no lock within 1 ms
+// <0x7=>The Time-out if no lock within 11 ms
+// fdpll0_arch_ltime
+#ifndef CONF_FDPLL0_LTIME
+#define CONF_FDPLL0_LTIME 0x0
+#endif
+
+// Reference Clock Selection
+// <0x0=>GCLK clock reference
+// <0x1=>XOSC32K clock reference
+// <0x2=>XOSC0 clock reference
+// <0x3=>XOSC1 clock reference
+// fdpll0_arch_refclk
+#ifndef CONF_FDPLL0_REFCLK
+#define CONF_FDPLL0_REFCLK 0x1
+#endif
+
+// Wake Up Fast
+// Indicates whether Wake Up Fast is enabled or not
+// fdpll0_arch_wuf
+#ifndef CONF_FDPLL0_WUF
+#define CONF_FDPLL0_WUF 0
+#endif
+
+// Proportional Integral Filter Selection <0x0-0xF>
+// fdpll0_arch_filter
+#ifndef CONF_FDPLL0_FILTER
+#define CONF_FDPLL0_FILTER 0x0
+#endif
+
+//
+//
+// FDPLL1 Configuration
+// Indicates whether configuration for FDPLL1 is enabled or not
+// enable_fdpll1
+#ifndef CONF_FDPLL1_CONFIG
+#define CONF_FDPLL1_CONFIG 1
+#endif
+
+// Reference Clock Source
+// 32kHz External Crystal Oscillator (XOSC32K)
+// External Crystal Oscillator 8-48MHz (XOSC0)
+// External Crystal Oscillator 8-48MHz (XOSC1)
+// Generic clock generator 0
+// Generic clock generator 1
+// Generic clock generator 2
+// Generic clock generator 3
+// Generic clock generator 4
+// Generic clock generator 5
+// Generic clock generator 6
+// Generic clock generator 7
+// Generic clock generator 8
+// Generic clock generator 9
+// Generic clock generator 10
+// Generic clock generator 11
+// Select the clock source.
+// fdpll1_ref_clock
+#ifndef CONF_FDPLL1_GCLK
+#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+// Digital Phase Locked Loop Control
+// Enable
+// Indicates whether Digital Phase Locked Loop is enabled or not
+// fdpll1_arch_enable
+#ifndef CONF_FDPLL1_ENABLE
+#define CONF_FDPLL1_ENABLE 1
+#endif
+
+// On Demand Control
+// Indicates whether On Demand Control is enabled or not
+// fdpll1_arch_ondemand
+#ifndef CONF_FDPLL1_ONDEMAND
+#define CONF_FDPLL1_ONDEMAND 0
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// fdpll1_arch_runstdby
+#ifndef CONF_FDPLL1_RUNSTDBY
+#define CONF_FDPLL1_RUNSTDBY 0
+#endif
+
+// Loop Divider Ratio Fractional Part <0x0-0x1F>
+// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
+// fdpll1_ldrfrac
+#ifndef CONF_FDPLL1_LDRFRAC
+#define CONF_FDPLL1_LDRFRAC 0x0
+#endif
+
+// Loop Divider Ratio Integer Part <0x0-0x1FFF>
+// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
+// fdpll1_ldr
+#ifndef CONF_FDPLL1_LDR
+#define CONF_FDPLL1_LDR 0x31
+#endif
+
+// Clock Divider <0x0-0x7FF>
+// This Clock divider is only for XOSC clock input to DPLL
+// fdpll1_clock_div
+#ifndef CONF_FDPLL1_DIV
+#define CONF_FDPLL1_DIV 0x0
+#endif
+
+// DCO Filter Enable
+// Indicates whether DCO Filter Enable is enabled or not
+// fdpll1_arch_dcoen
+#ifndef CONF_FDPLL1_DCOEN
+#define CONF_FDPLL1_DCOEN 0
+#endif
+
+// Sigma-Delta DCO Filter Selection <0x0-0x7>
+// fdpll1_clock_dcofilter
+#ifndef CONF_FDPLL1_DCOFILTER
+#define CONF_FDPLL1_DCOFILTER 0x0
+#endif
+
+// Lock Bypass
+// Indicates whether Lock Bypass is enabled or not
+// fdpll1_arch_lbypass
+#ifndef CONF_FDPLL1_LBYPASS
+#define CONF_FDPLL1_LBYPASS 0
+#endif
+
+// Lock Time
+// <0x0=>No time-out, automatic lock
+// <0x4=>The Time-out if no lock within 800 us
+// <0x5=>The Time-out if no lock within 900 us
+// <0x6=>The Time-out if no lock within 1 ms
+// <0x7=>The Time-out if no lock within 11 ms
+// fdpll1_arch_ltime
+#ifndef CONF_FDPLL1_LTIME
+#define CONF_FDPLL1_LTIME 0x0
+#endif
+
+// Reference Clock Selection
+// <0x0=>GCLK clock reference
+// <0x1=>XOSC32K clock reference
+// <0x2=>XOSC0 clock reference
+// <0x3=>XOSC1 clock reference
+// fdpll1_arch_refclk
+#ifndef CONF_FDPLL1_REFCLK
+#define CONF_FDPLL1_REFCLK 0x0
+#endif
+
+// Wake Up Fast
+// Indicates whether Wake Up Fast is enabled or not
+// fdpll1_arch_wuf
+#ifndef CONF_FDPLL1_WUF
+#define CONF_FDPLL1_WUF 0
+#endif
+
+// Proportional Integral Filter Selection <0x0-0xF>
+// fdpll1_arch_filter
+#ifndef CONF_FDPLL1_FILTER
+#define CONF_FDPLL1_FILTER 0x0
+#endif
+
+//
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_OSCCTRL_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_port_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_port_config.h
new file mode 100644
index 0000000..7e6e94f
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_port_config.h
@@ -0,0 +1,284 @@
+/* Auto-generated config file hpl_port_config.h */
+#ifndef HPL_PORT_CONFIG_H
+#define HPL_PORT_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// PORT Input Event 0 configuration
+// enable_port_input_event_0
+#ifndef CONF_PORT_EVCTRL_PORT_0
+#define CONF_PORT_EVCTRL_PORT_0 1
+#endif
+
+// PORT Input Event 0 configuration on PORT A
+
+// PORTA Input Event 0 Enable
+// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
+// porta_input_event_enable_0
+#ifndef CONF_PORTA_EVCTRL_PORTEI_0
+#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
+#endif
+
+// PORTA Event 0 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port A on which the event action will be performed
+// porta_event_pin_identifier_0
+#ifndef CONF_PORTA_EVCTRL_PID_0
+#define CONF_PORTA_EVCTRL_PID_0 0x0
+#endif
+
+// PORTA Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT A will perform on event input 0
+// porta_event_action_0
+#ifndef CONF_PORTA_EVCTRL_EVACT_0
+#define CONF_PORTA_EVCTRL_EVACT_0 0
+#endif
+
+//
+// PORT Input Event 0 configuration on PORT B
+
+// PORTB Input Event 0 Enable
+// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
+// portb_input_event_enable_0
+#ifndef CONF_PORTB_EVCTRL_PORTEI_0
+#define CONF_PORTB_EVCTRL_PORTEI_0 0x1
+#endif
+
+// PORTB Event 0 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port B on which the event action will be performed
+// portb_event_pin_identifier_0
+#ifndef CONF_PORTB_EVCTRL_PID_0
+#define CONF_PORTB_EVCTRL_PID_0 0x16
+#endif
+
+// PORTB Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT B will perform on event input 0
+// portb_event_action_0
+#ifndef CONF_PORTB_EVCTRL_EVACT_0
+#define CONF_PORTB_EVCTRL_EVACT_0 2
+#endif
+
+//
+
+//
+
+// PORT Input Event 1 configuration
+// enable_port_input_event_1
+#ifndef CONF_PORT_EVCTRL_PORT_1
+#define CONF_PORT_EVCTRL_PORT_1 1
+#endif
+
+// PORT Input Event 1 configuration on PORT A
+
+// PORTA Input Event 1 Enable
+// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
+// porta_input_event_enable_1
+#ifndef CONF_PORTA_EVCTRL_PORTEI_1
+#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
+#endif
+
+// PORTA Event 1 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port A on which the event action will be performed
+// porta_event_pin_identifier_1
+#ifndef CONF_PORTA_EVCTRL_PID_1
+#define CONF_PORTA_EVCTRL_PID_1 0x0
+#endif
+
+// PORTA Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT A will perform on event input 1
+// porta_event_action_1
+#ifndef CONF_PORTA_EVCTRL_EVACT_1
+#define CONF_PORTA_EVCTRL_EVACT_1 0
+#endif
+
+//
+// PORT Input Event 1 configuration on PORT B
+
+// PORTB Input Event 1 Enable
+// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
+// portb_input_event_enable_1
+#ifndef CONF_PORTB_EVCTRL_PORTEI_1
+#define CONF_PORTB_EVCTRL_PORTEI_1 0x1
+#endif
+
+// PORTB Event 1 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port B on which the event action will be performed
+// portb_event_pin_identifier_1
+#ifndef CONF_PORTB_EVCTRL_PID_1
+#define CONF_PORTB_EVCTRL_PID_1 0x16
+#endif
+
+// PORTB Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT B will perform on event input 1
+// portb_event_action_1
+#ifndef CONF_PORTB_EVCTRL_EVACT_1
+#define CONF_PORTB_EVCTRL_EVACT_1 1
+#endif
+
+//
+
+//
+
+// PORT Input Event 2 configuration
+// enable_port_input_event_2
+#ifndef CONF_PORT_EVCTRL_PORT_2
+#define CONF_PORT_EVCTRL_PORT_2 1
+#endif
+
+// PORT Input Event 2 configuration on PORT A
+
+// PORTA Input Event 2 Enable
+// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
+// porta_input_event_enable_2
+#ifndef CONF_PORTA_EVCTRL_PORTEI_2
+#define CONF_PORTA_EVCTRL_PORTEI_2 0x1
+#endif
+
+// PORTA Event 2 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port A on which the event action will be performed
+// porta_event_pin_identifier_2
+#ifndef CONF_PORTA_EVCTRL_PID_2
+#define CONF_PORTA_EVCTRL_PID_2 0xe
+#endif
+
+// PORTA Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT A will perform on event input 2
+// porta_event_action_2
+#ifndef CONF_PORTA_EVCTRL_EVACT_2
+#define CONF_PORTA_EVCTRL_EVACT_2 2
+#endif
+
+//
+// PORT Input Event 2 configuration on PORT B
+
+// PORTB Input Event 2 Enable
+// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
+// portb_input_event_enable_2
+#ifndef CONF_PORTB_EVCTRL_PORTEI_2
+#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
+#endif
+
+// PORTB Event 2 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port B on which the event action will be performed
+// portb_event_pin_identifier_2
+#ifndef CONF_PORTB_EVCTRL_PID_2
+#define CONF_PORTB_EVCTRL_PID_2 0x0
+#endif
+
+// PORTB Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT B will perform on event input 2
+// portb_event_action_2
+#ifndef CONF_PORTB_EVCTRL_EVACT_2
+#define CONF_PORTB_EVCTRL_EVACT_2 0
+#endif
+
+//
+
+//
+
+// PORT Input Event 3 configuration
+// enable_port_input_event_3
+#ifndef CONF_PORT_EVCTRL_PORT_3
+#define CONF_PORT_EVCTRL_PORT_3 1
+#endif
+
+// PORT Input Event 3 configuration on PORT A
+
+// PORTA Input Event 3 Enable
+// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
+// porta_input_event_enable_3
+#ifndef CONF_PORTA_EVCTRL_PORTEI_3
+#define CONF_PORTA_EVCTRL_PORTEI_3 0x1
+#endif
+
+// PORTA Event 3 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port A on which the event action will be performed
+// porta_event_pin_identifier_3
+#ifndef CONF_PORTA_EVCTRL_PID_3
+#define CONF_PORTA_EVCTRL_PID_3 0xe
+#endif
+
+// PORTA Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT A will perform on event input 3
+// porta_event_action_3
+#ifndef CONF_PORTA_EVCTRL_EVACT_3
+#define CONF_PORTA_EVCTRL_EVACT_3 1
+#endif
+
+//
+// PORT Input Event 3 configuration on PORT B
+
+// PORTB Input Event 3 Enable
+// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
+// portb_input_event_enable_3
+#ifndef CONF_PORTB_EVCTRL_PORTEI_3
+#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
+#endif
+
+// PORTB Event 3 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port B on which the event action will be performed
+// portb_event_pin_identifier_3
+#ifndef CONF_PORTB_EVCTRL_PID_3
+#define CONF_PORTB_EVCTRL_PID_3 0x0
+#endif
+
+// PORTB Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT B will perform on event input 3
+// portb_event_action_3
+#ifndef CONF_PORTB_EVCTRL_EVACT_3
+#define CONF_PORTB_EVCTRL_EVACT_3 0
+#endif
+
+//
+
+//
+
+#define CONF_PORTA_EVCTRL \
+ (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
+ | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \
+ | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \
+ | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
+ | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \
+ | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
+#define CONF_PORTB_EVCTRL \
+ (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
+ | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \
+ | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \
+ | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
+ | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \
+ | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
+
+// <<< end of configuration section >>>
+
+#endif // HPL_PORT_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_qspi_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_qspi_config.h
new file mode 100644
index 0000000..1dbf955
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_qspi_config.h
@@ -0,0 +1,98 @@
+/* Auto-generated config file hpl_qspi_config.h */
+#ifndef HPL_QSPI_CONFIG_H
+#define HPL_QSPI_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include
+
+// Basic settings
+
+#ifndef CONF_CONF_QSPI_ENABLE
+#define CONF_CONF_QSPI_ENABLE 1
+#endif
+
+// Baud rate <1-150000000>
+// The SPI data transfer rate. Note: (fqspi_clock / baudrate) < 255
+// qspi_baud_rate
+#ifndef CONF_QSPI_BAUD
+#define CONF_QSPI_BAUD 6000000
+#endif
+
+// Clock Polarity
+// <0x0=>The inactive state value of SPCK is logic level zero.
+// <0x1=>The inactive state value of SPCK is logic level one.
+// Determines the inactive state value of the serial clock (SPCK).
+// qspi_cpol
+#ifndef CONF_QSPI_CPOL
+#define CONF_QSPI_CPOL 0x0
+#endif
+
+// Clock Phase
+// <0x0=>Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
+// <0x1=>Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
+// Determines which edge of SPCK causes data to change and which edge causes data to be captured.
+// qspi_cpha
+#ifndef CONF_QSPI_CPHA
+#define CONF_QSPI_CPHA 0x0
+#endif
+
+// QSPI DMA TX Channel <0-32>
+// This defines DMA channel to be used
+// qspi_dma_tx_channel
+#ifndef CONF_QSPI_DMA_TX_CHANNEL
+#define CONF_QSPI_DMA_TX_CHANNEL 1
+#endif
+
+// QSPI DMA RX Channel <0-32>
+// This defines DMA channel to be used
+// qspi_dma_rx_channel
+#ifndef CONF_QSPI_DMA_RX_CHANNEL
+#define CONF_QSPI_DMA_RX_CHANNEL 0
+#endif
+
+//
+
+// Advanced Configuration
+// qspi_advanced
+#ifndef CONF_QSPI_ADVANCED
+#define CONF_QSPI_ADVANCED 0
+#endif
+
+// Delay Before QSCK (ns) <0-255000>
+// This field defines the delay from QCS falling edge (activation) to the first valid QSCK transition (in ns).
+// qspi_dlybs
+#ifndef CONF_QSPI_DLY_BS
+#define CONF_QSPI_DLY_BS 0
+#endif
+
+// Minimum Inactive QCS Delay (ns) <0-8160000>
+// This field defines the minimum delay between the deactivation and the activation of QCS (in ns).
+// qspi_dlycs
+#ifndef CONF_QSPI_DLY_CS
+#define CONF_QSPI_DLY_CS 0
+#endif
+
+//
+
+/* Calculate baud register value from requested baudrate value */
+#ifndef CONF_QSPI_BAUD_RATE
+#define CONF_QSPI_BAUD_RATE ((CONF_CPU_FREQUENCY / CONF_QSPI_BAUD) - 1)
+#if CONF_QSPI_BAUD > CONF_CPU_FREQUENCY || CONF_QSPI_BAUD_RATE > 255
+#warning Invalid baudrate, please check.
+#endif
+#endif
+
+/* Calculates the value of the CSR DLYCS field given the desired delay (in ns) */
+#ifndef CONF_QSPI_DLYCS
+#define CONF_QSPI_DLYCS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_CS) / 1000)
+#endif
+
+/* Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
+#ifndef CONF_QSPI_DLYBS
+#define CONF_QSPI_DLYBS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_BS) / 1000)
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_QSPI_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_sercom_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_sercom_config.h
new file mode 100644
index 0000000..1d01fe3
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_sercom_config.h
@@ -0,0 +1,643 @@
+/* Auto-generated config file hpl_sercom_config.h */
+#ifndef HPL_SERCOM_CONFIG_H
+#define HPL_SERCOM_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include
+
+#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+#endif
+
+#ifndef CONF_SERCOM_0_I2CM_ENABLE
+#define CONF_SERCOM_0_I2CM_ENABLE 1
+#endif
+
+// Basic
+
+// I2C Bus clock speed (Hz) <1-400000>
+// I2C Bus clock (SCL) speed measured in Hz
+// i2c_master_baud_rate
+#ifndef CONF_SERCOM_0_I2CM_BAUD
+#define CONF_SERCOM_0_I2CM_BAUD 100000
+#endif
+
+//
+
+// Advanced
+// i2c_master_advanced
+#ifndef CONF_SERCOM_0_I2CM_ADVANCED_CONFIG
+#define CONF_SERCOM_0_I2CM_ADVANCED_CONFIG 0
+#endif
+
+// TRise (ns) <0-300>
+// Determined by the bus impedance, check electric characteristics in the datasheet
+// Standard Fast Mode: typical 215ns, max 300ns
+// Fast Mode +: typical 60ns, max 100ns
+// High Speed Mode: typical 20ns, max 40ns
+// i2c_master_arch_trise
+
+#ifndef CONF_SERCOM_0_I2CM_TRISE
+#define CONF_SERCOM_0_I2CM_TRISE 215
+#endif
+
+// Master SCL Low Extended Time-Out (MEXTTOEN)
+// This enables the master SCL low extend time-out
+// i2c_master_arch_mexttoen
+#ifndef CONF_SERCOM_0_I2CM_MEXTTOEN
+#define CONF_SERCOM_0_I2CM_MEXTTOEN 0
+#endif
+
+// Slave SCL Low Extend Time-Out (SEXTTOEN)
+// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
+// i2c_master_arch_sexttoen
+#ifndef CONF_SERCOM_0_I2CM_SEXTTOEN
+#define CONF_SERCOM_0_I2CM_SEXTTOEN 0
+#endif
+
+// SCL Low Time-Out (LOWTOUT)
+// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
+// i2c_master_arch_lowtout
+#ifndef CONF_SERCOM_0_I2CM_LOWTOUT
+#define CONF_SERCOM_0_I2CM_LOWTOUT 0
+#endif
+
+// Inactive Time-Out (INACTOUT)
+// <0x0=>Disabled
+// <0x1=>5-6 SCL cycle time-out(50-60us)
+// <0x2=>10-11 SCL cycle time-out(100-110us)
+// <0x3=>20-21 SCL cycle time-out(200-210us)
+// Defines if inactivity time-out should be enabled, and how long the time-out should be
+// i2c_master_arch_inactout
+#ifndef CONF_SERCOM_0_I2CM_INACTOUT
+#define CONF_SERCOM_0_I2CM_INACTOUT 0x0
+#endif
+
+// SDA Hold Time (SDAHOLD)
+// <0=>Disabled
+// <1=>50-100ns hold time
+// <2=>300-600ns hold time
+// <3=>400-800ns hold time
+// Defines the SDA hold time with respect to the negative edge of SCL
+// i2c_master_arch_sdahold
+#ifndef CONF_SERCOM_0_I2CM_SDAHOLD
+#define CONF_SERCOM_0_I2CM_SDAHOLD 0x2
+#endif
+
+// Run in stand-by
+// Determine if the module shall run in standby sleep mode
+// i2c_master_arch_runstdby
+#ifndef CONF_SERCOM_0_I2CM_RUNSTDBY
+#define CONF_SERCOM_0_I2CM_RUNSTDBY 0
+#endif
+
+// Debug Stop Mode
+// Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// i2c_master_arch_dbgstop
+#ifndef CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE
+#define CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE 0
+#endif
+
+//
+
+#ifndef CONF_SERCOM_0_I2CM_SPEED
+#define CONF_SERCOM_0_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
+#endif
+#if CONF_SERCOM_0_I2CM_TRISE < 215 || CONF_SERCOM_0_I2CM_TRISE > 300
+#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
+#undef CONF_SERCOM_0_I2CM_TRISE
+#define CONF_SERCOM_0_I2CM_TRISE 215U
+#endif
+
+// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
+// BAUD + BAUDLOW = --------------------------------------------------------------------
+// i2c_scl_freq
+// BAUD: register value low [7:0]
+// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
+#define CONF_SERCOM_0_I2CM_BAUD_BAUDLOW \
+ (((CONF_GCLK_SERCOM0_CORE_FREQUENCY - (CONF_SERCOM_0_I2CM_BAUD * 10U) \
+ - (CONF_SERCOM_0_I2CM_TRISE * (CONF_SERCOM_0_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM0_CORE_FREQUENCY / 10000U) \
+ / 1000U)) \
+ * 10U \
+ + 5U) \
+ / (CONF_SERCOM_0_I2CM_BAUD * 10U))
+#ifndef CONF_SERCOM_0_I2CM_BAUD_RATE
+#if CONF_SERCOM_0_I2CM_BAUD_BAUDLOW > (0xFF * 2)
+#warning Requested I2C baudrate too low, please check
+#define CONF_SERCOM_0_I2CM_BAUD_RATE 0xFF
+#elif CONF_SERCOM_0_I2CM_BAUD_BAUDLOW <= 1
+#warning Requested I2C baudrate too high, please check
+#define CONF_SERCOM_0_I2CM_BAUD_RATE 1
+#else
+#define CONF_SERCOM_0_I2CM_BAUD_RATE \
+ ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW & 0x1) \
+ ? (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
+ : (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2))
+#endif
+#endif
+
+#include
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_1_SPI_ENABLE
+#define CONF_SERCOM_1_SPI_ENABLE 1
+#endif
+
+// SPI DMA TX Channel <0-32>
+// This defines DMA channel to be used
+// spi_master_dma_tx_channel
+#ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 7
+#endif
+
+// SPI RX Channel Enable
+// spi_master_rx_channel
+#ifndef CONF_SERCOM_1_SPI_RX_CHANNEL
+#define CONF_SERCOM_1_SPI_RX_CHANNEL 1
+#endif
+
+// DMA Channel <0-32>
+// This defines DMA channel to be used
+// spi_master_dma_rx_channel
+#ifndef CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 0
+#endif
+
+//
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_1_SPI_MODE
+#define CONF_SERCOM_1_SPI_MODE 0x03
+#endif
+
+// Basic Configuration
+
+// Receive buffer enable
+// Enable receive buffer to receive data from slave (RXEN)
+// spi_master_rx_enable
+#ifndef CONF_SERCOM_1_SPI_RXEN
+#define CONF_SERCOM_1_SPI_RXEN 0x1
+#endif
+
+// Character Size
+// Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// spi_master_character_size
+#ifndef CONF_SERCOM_1_SPI_CHSIZE
+#define CONF_SERCOM_1_SPI_CHSIZE 0x0
+#endif
+// Baud rate <1-18000000>
+// The SPI data transfer rate
+// spi_master_baud_rate
+#ifndef CONF_SERCOM_1_SPI_BAUD
+#define CONF_SERCOM_1_SPI_BAUD 1000000
+#endif
+
+//
+
+// Advanced Configuration
+// spi_master_advanced
+#ifndef CONF_SERCOM_1_SPI_ADVANCED
+#define CONF_SERCOM_1_SPI_ADVANCED 1
+#endif
+
+// Dummy byte <0x00-0x1ff>
+// spi_master_dummybyte
+// Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_1_SPI_DUMMYBYTE
+#define CONF_SERCOM_1_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// Data Order
+// <0=>MSB first
+// <1=>LSB first
+// I least significant or most significant bit is shifted out first (DORD)
+// spi_master_arch_dord
+#ifndef CONF_SERCOM_1_SPI_DORD
+#define CONF_SERCOM_1_SPI_DORD 0x0
+#endif
+
+// Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// spi_master_arch_cpol
+#ifndef CONF_SERCOM_1_SPI_CPOL
+#define CONF_SERCOM_1_SPI_CPOL 0x0
+#endif
+
+// Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// spi_master_arch_cpha
+#ifndef CONF_SERCOM_1_SPI_CPHA
+#define CONF_SERCOM_1_SPI_CPHA 0x0
+#endif
+
+// Immediate Buffer Overflow Notification
+// Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// spi_master_arch_ibon
+#ifndef CONF_SERCOM_1_SPI_IBON
+#define CONF_SERCOM_1_SPI_IBON 0x0
+#endif
+
+// Run in stand-by
+// Module stays active in stand-by sleep mode. (RUNSTDBY)
+// spi_master_arch_runstdby
+#ifndef CONF_SERCOM_1_SPI_RUNSTDBY
+#define CONF_SERCOM_1_SPI_RUNSTDBY 0x0
+#endif
+
+// Debug Stop Mode
+// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_1_SPI_DBGSTOP
+#define CONF_SERCOM_1_SPI_DBGSTOP 0
+#endif
+
+//
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_1_SPI_AMODE_EN
+#define CONF_SERCOM_1_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_AMODE
+#define CONF_SERCOM_1_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_ADDR
+#define CONF_SERCOM_1_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_ADDRMASK
+#define CONF_SERCOM_1_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_SSDE
+#define CONF_SERCOM_1_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_MSSEN
+#define CONF_SERCOM_1_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_PLOADEN
+#define CONF_SERCOM_1_SPI_PLOADEN 0
+#endif
+
+// Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// spi_master_rxpo
+#ifndef CONF_SERCOM_1_SPI_RXPO
+#define CONF_SERCOM_1_SPI_RXPO 3
+#endif
+
+// Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// spi_master_txpo
+#ifndef CONF_SERCOM_1_SPI_TXPO
+#define CONF_SERCOM_1_SPI_TXPO 0
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_1_SPI_BAUD_RATE
+#define CONF_SERCOM_1_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM1_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_1_SPI_BAUD)) - 1
+#endif
+
+#include
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_2_SPI_ENABLE
+#define CONF_SERCOM_2_SPI_ENABLE 1
+#endif
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_2_SPI_MODE
+#define CONF_SERCOM_2_SPI_MODE 0x03
+#endif
+
+// Basic Configuration
+
+// Receive buffer enable
+// Enable receive buffer to receive data from slave (RXEN)
+// spi_master_rx_enable
+#ifndef CONF_SERCOM_2_SPI_RXEN
+#define CONF_SERCOM_2_SPI_RXEN 0x1
+#endif
+
+// Character Size
+// Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// spi_master_character_size
+#ifndef CONF_SERCOM_2_SPI_CHSIZE
+#define CONF_SERCOM_2_SPI_CHSIZE 0x0
+#endif
+// Baud rate <1-18000000>
+// The SPI data transfer rate
+// spi_master_baud_rate
+#ifndef CONF_SERCOM_2_SPI_BAUD
+#define CONF_SERCOM_2_SPI_BAUD 1000000
+#endif
+
+//
+
+// Advanced Configuration
+// spi_master_advanced
+#ifndef CONF_SERCOM_2_SPI_ADVANCED
+#define CONF_SERCOM_2_SPI_ADVANCED 1
+#endif
+
+// Dummy byte <0x00-0x1ff>
+// spi_master_dummybyte
+// Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_2_SPI_DUMMYBYTE
+#define CONF_SERCOM_2_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// Data Order
+// <0=>MSB first
+// <1=>LSB first
+// I least significant or most significant bit is shifted out first (DORD)
+// spi_master_arch_dord
+#ifndef CONF_SERCOM_2_SPI_DORD
+#define CONF_SERCOM_2_SPI_DORD 0x0
+#endif
+
+// Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// spi_master_arch_cpol
+#ifndef CONF_SERCOM_2_SPI_CPOL
+#define CONF_SERCOM_2_SPI_CPOL 0x0
+#endif
+
+// Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// spi_master_arch_cpha
+#ifndef CONF_SERCOM_2_SPI_CPHA
+#define CONF_SERCOM_2_SPI_CPHA 0x1
+#endif
+
+// Immediate Buffer Overflow Notification
+// Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// spi_master_arch_ibon
+#ifndef CONF_SERCOM_2_SPI_IBON
+#define CONF_SERCOM_2_SPI_IBON 0x1
+#endif
+
+// Run in stand-by
+// Module stays active in stand-by sleep mode. (RUNSTDBY)
+// spi_master_arch_runstdby
+#ifndef CONF_SERCOM_2_SPI_RUNSTDBY
+#define CONF_SERCOM_2_SPI_RUNSTDBY 0x0
+#endif
+
+// Debug Stop Mode
+// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_2_SPI_DBGSTOP
+#define CONF_SERCOM_2_SPI_DBGSTOP 0
+#endif
+
+//
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_2_SPI_AMODE_EN
+#define CONF_SERCOM_2_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_AMODE
+#define CONF_SERCOM_2_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_ADDR
+#define CONF_SERCOM_2_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_ADDRMASK
+#define CONF_SERCOM_2_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_SSDE
+#define CONF_SERCOM_2_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_MSSEN
+#define CONF_SERCOM_2_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_PLOADEN
+#define CONF_SERCOM_2_SPI_PLOADEN 0
+#endif
+
+// Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// spi_master_rxpo
+#ifndef CONF_SERCOM_2_SPI_RXPO
+#define CONF_SERCOM_2_SPI_RXPO 3
+#endif
+
+// Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// spi_master_txpo
+#ifndef CONF_SERCOM_2_SPI_TXPO
+#define CONF_SERCOM_2_SPI_TXPO 0
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_2_SPI_BAUD_RATE
+#define CONF_SERCOM_2_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM2_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_2_SPI_BAUD)) - 1
+#endif
+
+#include
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_5_SPI_ENABLE
+#define CONF_SERCOM_5_SPI_ENABLE 1
+#endif
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_5_SPI_MODE
+#define CONF_SERCOM_5_SPI_MODE 0x03
+#endif
+
+// Basic Configuration
+
+// Receive buffer enable
+// Enable receive buffer to receive data from slave (RXEN)
+// spi_master_rx_enable
+#ifndef CONF_SERCOM_5_SPI_RXEN
+#define CONF_SERCOM_5_SPI_RXEN 0x1
+#endif
+
+// Character Size
+// Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// spi_master_character_size
+#ifndef CONF_SERCOM_5_SPI_CHSIZE
+#define CONF_SERCOM_5_SPI_CHSIZE 0x0
+#endif
+// Baud rate <1-18000000>
+// The SPI data transfer rate
+// spi_master_baud_rate
+#ifndef CONF_SERCOM_5_SPI_BAUD
+#define CONF_SERCOM_5_SPI_BAUD 1000000
+#endif
+
+//
+
+// Advanced Configuration
+// spi_master_advanced
+#ifndef CONF_SERCOM_5_SPI_ADVANCED
+#define CONF_SERCOM_5_SPI_ADVANCED 0
+#endif
+
+// Dummy byte <0x00-0x1ff>
+// spi_master_dummybyte
+// Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_5_SPI_DUMMYBYTE
+#define CONF_SERCOM_5_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// Data Order
+// <0=>MSB first
+// <1=>LSB first
+// I least significant or most significant bit is shifted out first (DORD)
+// spi_master_arch_dord
+#ifndef CONF_SERCOM_5_SPI_DORD
+#define CONF_SERCOM_5_SPI_DORD 0x0
+#endif
+
+// Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// spi_master_arch_cpol
+#ifndef CONF_SERCOM_5_SPI_CPOL
+#define CONF_SERCOM_5_SPI_CPOL 0x0
+#endif
+
+// Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// spi_master_arch_cpha
+#ifndef CONF_SERCOM_5_SPI_CPHA
+#define CONF_SERCOM_5_SPI_CPHA 0x0
+#endif
+
+// Immediate Buffer Overflow Notification
+// Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// spi_master_arch_ibon
+#ifndef CONF_SERCOM_5_SPI_IBON
+#define CONF_SERCOM_5_SPI_IBON 0x0
+#endif
+
+// Run in stand-by
+// Module stays active in stand-by sleep mode. (RUNSTDBY)
+// spi_master_arch_runstdby
+#ifndef CONF_SERCOM_5_SPI_RUNSTDBY
+#define CONF_SERCOM_5_SPI_RUNSTDBY 0x0
+#endif
+
+// Debug Stop Mode
+// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_5_SPI_DBGSTOP
+#define CONF_SERCOM_5_SPI_DBGSTOP 0
+#endif
+
+//
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_5_SPI_AMODE_EN
+#define CONF_SERCOM_5_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_AMODE
+#define CONF_SERCOM_5_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_ADDR
+#define CONF_SERCOM_5_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_ADDRMASK
+#define CONF_SERCOM_5_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_SSDE
+#define CONF_SERCOM_5_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_MSSEN
+#define CONF_SERCOM_5_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_PLOADEN
+#define CONF_SERCOM_5_SPI_PLOADEN 0
+#endif
+
+// Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// spi_master_rxpo
+#ifndef CONF_SERCOM_5_SPI_RXPO
+#define CONF_SERCOM_5_SPI_RXPO 3
+#endif
+
+// Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// spi_master_txpo
+#ifndef CONF_SERCOM_5_SPI_TXPO
+#define CONF_SERCOM_5_SPI_TXPO 0
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_5_SPI_BAUD_RATE
+#define CONF_SERCOM_5_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM5_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_5_SPI_BAUD)) - 1
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SERCOM_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_tcc_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_tcc_config.h
new file mode 100644
index 0000000..ccac794
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_tcc_config.h
@@ -0,0 +1,1124 @@
+/* Auto-generated config file hpl_tcc_config.h */
+#ifndef HPL_TCC_CONFIG_H
+#define HPL_TCC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include
+#ifndef CONF_TCC0_ENABLE
+#define CONF_TCC0_ENABLE 1
+#endif
+
+#ifndef CONF_TCC0_PWM_ENABLE
+#define CONF_TCC0_PWM_ENABLE 1
+#endif
+
+// Basic settings
+// TCC0 Prescaler
+// No division
+// Divide by 2
+// Divide by 4
+// Divide by 8
+// Divide by 16
+// Divide by 64
+// Divide by 256
+// Divide by 1024
+// This defines the TCC0 prescaler value
+// tcc_prescaler
+#ifndef CONF_TCC0_PRESCALER
+#define CONF_TCC0_PRESCALER TCC_CTRLA_PRESCALER_DIV2_Val
+#endif
+
+//
+// TCC0 Period Value <0x000000-0xFFFFFF>
+// tcc_per
+#ifndef CONF_TCC0_PER
+#define CONF_TCC0_PER 0x2710
+#endif
+//
+
+//
+
+// PWM Waveform Output settings
+// TCC0 Waveform Period Value (uS) <0x00-0xFFFFFFFF>
+// The unit of this value is us.
+// tcc_arch_wave_per_val
+#ifndef CONF_TCC0_WAVE_PER_VAL
+#define CONF_TCC0_WAVE_PER_VAL 0x30
+#endif
+
+// TCC0 Waveform Duty Value (0.1%) <0x00-0x03E8>
+// The unit of this value is 1/1000.
+// tcc_arch_wave_duty_val
+#ifndef CONF_TCC0_WAVE_DUTY_VAL
+#define CONF_TCC0_WAVE_DUTY_VAL 0x1f4
+#endif
+
+// TCC0 Waveform Channel Select <0x00-0x05>
+// Index of the Compare Channel register, into which the Waveform Duty Value is written.
+// Give index of the Compare Channel register here in 0x00-0x05 range.
+// tcc_arch_sel_ch
+#ifndef CONF_TCC0_SEL_CH
+#define CONF_TCC0_SEL_CH 0x2
+#endif
+
+/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
+#if CONF_TCC0_PRESCALER < TCC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TCC0_PER_REG \
+ ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1000000 / (1 << CONF_TCC0_PRESCALER) - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)(double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 64000000 - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV256_Val
+#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 256000000 - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV1024_Val
+#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1024000000 - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+#endif
+//
+
+// Advanced settings
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL A register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC0_RESOLUTION TCC_CTRLA_RESOLUTION_NONE_Val
+// Run in standby
+// Indicates whether the TCC0 will continue running in standby sleep mode or not
+// tcc_arch_runstdby
+#ifndef CONF_TCC0_RUNSTDBY
+#define CONF_TCC0_RUNSTDBY 0
+#endif
+
+// TCC0 Prescaler and Counter Synchronization Selection
+// Reload or reset counter on next GCLK
+// Reload or reset counter on next prescaler clock
+// Reload or reset counter on next GCLK and reset prescaler counter
+// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock.
+// tcc_arch_prescsync
+#ifndef CONF_TCC0_PRESCSYNC
+#define CONF_TCC0_PRESCSYNC TCC_CTRLA_PRESCSYNC_GCLK_Val
+#endif
+
+// TCC0 Waveform Generation Selection
+// Single-slope PWM
+// Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
+// Dual-slope, interrupt/event at ZERO (DSBOTTOM)
+// Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
+// Dual-slope, interrupt/event at Top (DSTOP)
+// tcc_arch_wavegen
+#ifndef CONF_TCC0_WAVEGEN
+#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_DSBOTTOM_Val
+#endif
+// TCC0 Auto Lock
+// Indicates whether the TCC0 Auto Lock is enabled or not
+// tcc_arch_alock
+#ifndef CONF_TCC0_ALOCK
+#define CONF_TCC0_ALOCK 0
+#endif
+
+// TCC0 Capture Channel 0 Enable
+// Indicates whether the TCC0 Capture Channel 0 is enabled or not
+// tcc_arch_cpten0
+#ifndef CONF_TCC0_CPTEN0
+#define CONF_TCC0_CPTEN0 0
+#endif
+
+// TCC0 Capture Channel 1 Enable
+// Indicates whether the TCC0 Capture Channel 1 is enabled or not
+// tcc_arch_cpten1
+#ifndef CONF_TCC0_CPTEN1
+#define CONF_TCC0_CPTEN1 0
+#endif
+
+// TCC0 Capture Channel 2 Enable
+// Indicates whether the TCC0 Capture Channel 2 is enabled or not
+// tcc_arch_cpten2
+#ifndef CONF_TCC0_CPTEN2
+#define CONF_TCC0_CPTEN2 0
+#endif
+
+// TCC0 Capture Channel 3 Enable
+// Indicates whether the TCC0 Capture Channel 3 is enabled or not
+// tcc_arch_cpten3
+#ifndef CONF_TCC0_CPTEN3
+#define CONF_TCC0_CPTEN3 0
+#endif
+
+// TCC0 Capture Channel 4 Enable
+// Indicates whether the TCC0 Capture Channel 4 is enabled or not
+// tcc_arch_cpten4
+#ifndef CONF_TCC0_CPTEN4
+#define CONF_TCC0_CPTEN4 0
+#endif
+
+// TCC0 Capture Channel 5 Enable
+// Indicates whether the TCC0 Capture Channel 5 is enabled or not
+// tcc_arch_cpten5
+#ifndef CONF_TCC0_CPTEN5
+#define CONF_TCC0_CPTEN5 0
+#endif
+
+//
+// TCC0 Capture Channel 6 Enable
+// Indicates whether the TCC0 Capture Channel 6 is enabled or not
+// tcc_arch_cpten6
+#ifndef CONF_TCC0_CPTEN6
+#define CONF_TCC0_CPTEN6 0
+#endif
+//
+//
+// TCC0 Capture Channel 7 Enable
+// Indicates whether the TCC0 Capture Channel 7 is enabled or not
+// tcc_arch_cpten7
+#ifndef CONF_TCC0_CPTEN7
+#define CONF_TCC0_CPTEN7 0
+#endif
+//
+
+// TCC0 Lock update
+// Indicates whether the TCC0 Lock update is enabled or not
+// tcc_arch_lupd
+#ifndef CONF_TCC0_LUPD
+#define CONF_TCC0_LUPD 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL B register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC0_DIR 0
+//#define CONF_TCC0_ONESHOT 0
+
+/* Commented intentionally. No fault control for timers. */
+/*#define CONF_TCC0_FAULT_A_SRC TCC_FCTRLA_SRC_DISABLE_Val
+#define CONF_TCC0_FAULT_A_KEEP 0
+#define CONF_TCC0_FAULT_A_QUAL 0
+#define CONF_TCC0_FAULT_A_BLANK TCC_FCTRLA_BLANK_DISABLE_Val
+#define CONF_TCC0_FAULT_A_RESTART 0
+#define CONF_TCC0_FAULT_A_HALT TCC_FCTRLA_HALT_DISABLE_Val
+#define CONF_TCC0_FAULT_A_CHSEL TCC_FCTRLA_CHSEL_CC0_Val
+#define CONF_TCC0_FAULT_A_CAPTURE TCC_FCTRLA_CAPTURE_DISABLE_Val
+#define CONF_TCC0_FAULT_A_BLACNKPRESC 0
+#define CONF_TCC0_FAULT_A_BLANKVAL 0
+#define CONF_TCC0_FAULT_A_FILTERVAL 0
+
+#define CONF_TCC0_FAULT_B_SRC TCC_FCTRLB_SRC_DISABLE_Val
+#define CONF_TCC0_FAULT_B_KEEP 0
+#define CONF_TCC0_FAULT_B_QUAL 0
+#define CONF_TCC0_FAULT_B_BLANK TCC_FCTRLB_BLANK_DISABLE_Val
+#define CONF_TCC0_FAULT_B_RESTART 0
+#define CONF_TCC0_FAULT_B_HALT TCC_FCTRLB_HALT_DISABLE_Val
+#define CONF_TCC0_FAULT_B_CHSEL TCC_FCTRLB_CHSEL_CC0_Val
+#define CONF_TCC0_FAULT_B_CAPTURE TCC_FCTRLB_CAPTURE_DISABLE_Val
+#define CONF_TCC0_FAULT_B_BLACNKPRESC 0
+#define CONF_TCC0_FAULT_B_BLANKVAL 0
+#define CONF_TCC0_FAULT_B_FILTERVAL 0*/
+
+/* Commented intentionally. No dead-time control for timers. */
+/*#define CONF_TCC0_OTMX 0
+#define CONF_TCC0_DTIEN0 0
+#define CONF_TCC0_DTIEN1 0
+#define CONF_TCC0_DTIEN2 0
+#define CONF_TCC0_DTIEN3 0
+#define CONF_TCC0_DTHS 0*/
+
+/* Commented intentionally. No driver control for timers. */
+/*#define CONF_TCC0_NRE0 0
+#define CONF_TCC0_NRE1 0
+#define CONF_TCC0_NRE2 0
+#define CONF_TCC0_NRE3 0
+#define CONF_TCC0_NRE4 0
+#define CONF_TCC0_NRE5 0
+#define CONF_TCC0_NRE6 0
+#define CONF_TCC0_NRE7 0
+#define CONF_TCC0_NVR0 0
+#define CONF_TCC0_NVR1 0
+#define CONF_TCC0_NVR2 0
+#define CONF_TCC0_NVR3 0
+#define CONF_TCC0_NVR4 0
+#define CONF_TCC0_NVR5 0
+#define CONF_TCC0_NVR6 0
+#define CONF_TCC0_NVR7 0
+#define CONF_TCC0_INVEN0 0
+#define CONF_TCC0_INVEN1 0
+#define CONF_TCC0_INVEN2 0
+#define CONF_TCC0_INVEN3 0
+#define CONF_TCC0_INVEN4 0
+#define CONF_TCC0_INVEN5 0
+#define CONF_TCC0_INVEN6 0
+#define CONF_TCC0_INVEN7 0
+#define CONF_TCC0_FILTERVAL0 0
+#define CONF_TCC0_FILTERVAL1 0*/
+
+// TCC0 Debug Running Mode
+// Indicates whether the TCC0 Debug Running Mode is enabled or not
+// tcc_arch_dbgrun
+#ifndef CONF_TCC0_DBGRUN
+#define CONF_TCC0_DBGRUN 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of Debug Control register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC0_FDDBD 0
+
+// Event control
+// timer_event_control
+#ifndef CONF_TCC0_EVENT_CONTROL_ENABLE
+#define CONF_TCC0_EVENT_CONTROL_ENABLE 1
+#endif
+
+// Match or Capture Channel 0 Event Output
+// This bit indicates whether match/capture event on channel 0 is enabled and will be generated
+// tcc_arch_mceo0
+#ifndef CONF_TCC0_MCEO0
+#define CONF_TCC0_MCEO0 0
+#endif
+
+// Match or Capture Channel 0 Event Input
+// This bit indicates whether match/capture 0 incoming event is enabled
+// tcc_arch_mcei0
+#ifndef CONF_TCC0_MCEI0
+#define CONF_TCC0_MCEI0 0
+#endif
+// Match or Capture Channel 1 Event Output
+// This bit indicates whether match/capture event on channel 1 is enabled and will be generated
+// tcc_arch_mceo1
+#ifndef CONF_TCC0_MCEO1
+#define CONF_TCC0_MCEO1 0
+#endif
+
+// Match or Capture Channel 1 Event Input
+// This bit indicates whether match/capture 1 incoming event is enabled
+// tcc_arch_mcei1
+#ifndef CONF_TCC0_MCEI1
+#define CONF_TCC0_MCEI1 0
+#endif
+// Match or Capture Channel 2 Event Output
+// This bit indicates whether match/capture event on channel 2 is enabled and will be generated
+// tcc_arch_mceo2
+#ifndef CONF_TCC0_MCEO2
+#define CONF_TCC0_MCEO2 0
+#endif
+
+// Match or Capture Channel 2 Event Input
+// This bit indicates whether match/capture 2 incoming event is enabled
+// tcc_arch_mcei2
+#ifndef CONF_TCC0_MCEI2
+#define CONF_TCC0_MCEI2 0
+#endif
+// Match or Capture Channel 3 Event Output
+// This bit indicates whether match/capture event on channel 3 is enabled and will be generated
+// tcc_arch_mceo3
+#ifndef CONF_TCC0_MCEO3
+#define CONF_TCC0_MCEO3 0
+#endif
+
+// Match or Capture Channel 3 Event Input
+// This bit indicates whether match/capture 3 incoming event is enabled
+// tcc_arch_mcei3
+#ifndef CONF_TCC0_MCEI3
+#define CONF_TCC0_MCEI3 0
+#endif
+// Match or Capture Channel 4 Event Output
+// This bit indicates whether match/capture event on channel 4 is enabled and will be generated
+// tcc_arch_mceo4
+#ifndef CONF_TCC0_MCEO4
+#define CONF_TCC0_MCEO4 0
+#endif
+
+// Match or Capture Channel 4 Event Input
+// This bit indicates whether match/capture 4 incoming event is enabled
+// tcc_arch_mcei4
+#ifndef CONF_TCC0_MCEI4
+#define CONF_TCC0_MCEI4 0
+#endif
+// Match or Capture Channel 5 Event Output
+// This bit indicates whether match/capture event on channel 5 is enabled and will be generated
+// tcc_arch_mceo5
+#ifndef CONF_TCC0_MCEO5
+#define CONF_TCC0_MCEO5 0
+#endif
+
+// Match or Capture Channel 5 Event Input
+// This bit indicates whether match/capture 5 incoming event is enabled
+// tcc_arch_mcei5
+#ifndef CONF_TCC0_MCEI5
+#define CONF_TCC0_MCEI5 0
+#endif
+
+// Timer/Counter Event Input 0
+// This bit is used to enable input event 0 to the TCC
+// tcc_arch_tcei0
+#ifndef CONF_TCC0_TCEI0
+#define CONF_TCC0_TCEI0 0
+#endif
+
+// Timer/Counter Event Input 0 Invert
+// This bit inverts the event 0 input
+// tcc_arch_tceinv0
+#ifndef CONF_TCC0_TCINV0
+#define CONF_TCC0_TCINV0 0
+#endif
+// Timer/Counter Event Input 1
+// This bit is used to enable input event 1 to the TCC
+// tcc_arch_tcei1
+#ifndef CONF_TCC0_TCEI1
+#define CONF_TCC0_TCEI1 0
+#endif
+
+// Timer/Counter Event Input 1 Invert
+// This bit inverts the event 1 input
+// tcc_arch_tceinv1
+#ifndef CONF_TCC0_TCINV1
+#define CONF_TCC0_TCINV1 0
+#endif
+
+// Timer/Counter Event Output
+// This bit is used to enable the counter cycle event.
+// tcc_arch_cnteo
+#ifndef CONF_TCC0_CNTEO
+#define CONF_TCC0_CNTEO 0
+#endif
+
+// Re-trigger Event Output
+// This bit is used to enable the counter re-trigger event.
+// tcc_arch_trgeo
+#ifndef CONF_TCC0_TRGEO
+#define CONF_TCC0_TRGEO 0
+#endif
+
+// Overflow/Underflow Event Output
+// This bit is used to enable enable event on overflow/underflow.
+// tcc_arch_ovfeo
+#ifndef CONF_TCC0_OVFEO
+#define CONF_TCC0_OVFEO 1
+#endif
+
+// Timer/Counter Interrupt and Event Output Selection
+// <0=> An interrupt/event is generated when a new counter cycle starts
+// <1=> An interrupt/event is generated when a counter cycle ends
+// <2=> An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
+// <3=> An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
+// These bits define on which part of the counter cycle the counter event output is generated
+// tcc_arch_cntsel
+#ifndef CONF_TCC0_CNTSEL
+#define CONF_TCC0_CNTSEL 0
+#endif
+
+// Timer/Counter Event Input 0 Action
+// <0=>Event action disabled
+// <1=>Start restart or re-trigger on event
+// <2=>Count on event
+// <3=>Start on event
+// <4=>Increment on event
+// <5=>Count on active state of asynchronous event
+// <6=>Capture overflow times (Max value)
+// <7=>Non-recoverable fault
+// These bits define the action the TCC performs on TCE0 event input 0
+// tcc_arch_evact0
+#ifndef CONF_TCC0_EVACT0
+#define CONF_TCC0_EVACT0 0
+#endif
+
+// Timer/Counter Event Input 1 Action
+// <0=>Event action disabled
+// <1=>Re-trigger counter on event
+// <2=>Direction control
+// <3=>Stop counter on event
+// <4=>Decrement counter on event
+// <5=>Period capture value in CC0 register, pulse width capture value in CC1 register
+// <6=>Period capture value in CC1 register, pulse width capture value in CC0 register
+// <7=>Non-recoverable fault
+// These bits define the action the TCC performs on TCE0 event input 0
+// tcc_arch_evact1
+#ifndef CONF_TCC0_EVACT1
+#define CONF_TCC0_EVACT1 0
+#endif
+//
+
+/* Commented intentionally. No pattern control for timers. */
+/*#define CONF_TCC0_PGE0 0
+#define CONF_TCC0_PGE1 0
+#define CONF_TCC0_PGE2 0
+#define CONF_TCC0_PGE3 0
+#define CONF_TCC0_PGE4 0
+#define CONF_TCC0_PGE5 0
+#define CONF_TCC0_PGE6 0
+#define CONF_TCC0_PGE7 0
+#define CONF_TCC0_PGV0 0
+#define CONF_TCC0_PGV1 0
+#define CONF_TCC0_PGV2 0
+#define CONF_TCC0_PGV3 0
+#define CONF_TCC0_PGV4 0
+#define CONF_TCC0_PGV5 0
+#define CONF_TCC0_PGV6 0
+#define CONF_TCC0_PGV7 0*/
+
+/* Commented intentionally. No pattern waveform control for timers. */
+/*#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_MFRQ_Val
+#define CONF_TCC0_RAMP TCC_WAVE_RAMP_RAMP1_Val
+#define CONF_TCC0_CIPEREN 0
+#define CONF_TCC0_CICCEN0 0
+#define CONF_TCC0_CICCEN1 0
+#define CONF_TCC0_CICCEN2 0
+#define CONF_TCC0_CICCEN3 0
+#define CONF_TCC0_POL0 0
+#define CONF_TCC0_POL1 0
+#define CONF_TCC0_POL2 0
+#define CONF_TCC0_POL3 0
+#define CONF_TCC0_POL4 0
+#define CONF_TCC0_POL5 0
+#define CONF_TCC0_POL6 0
+#define CONF_TCC0_POL7 0
+#define CONF_TCC0_SWAP0 0
+#define CONF_TCC0_SWAP1 0
+#define CONF_TCC0_SWAP2 0
+#define CONF_TCC0_SWAP3 0*/
+
+// TCC0 Compare and Capture value 0 <0x00-0xFFFFFF>
+// tcc_arch_cc0
+#ifndef CONF_TCC0_CC0
+#define CONF_TCC0_CC0 0x0
+#endif
+
+// TCC0 Compare and Capture value 1 <0x00-0xFFFFFF>
+// tcc_arch_cc1
+#ifndef CONF_TCC0_CC1
+#define CONF_TCC0_CC1 0x0
+#endif
+
+// TCC0 Compare and Capture value 2 <0x00-0xFFFFFF>
+// tcc_arch_cc2
+#ifndef CONF_TCC0_CC2
+#define CONF_TCC0_CC2 0x0
+#endif
+
+// TCC0 Compare and Capture value 3 <0x00-0xFFFFFF>
+// tcc_arch_cc3
+#ifndef CONF_TCC0_CC3
+#define CONF_TCC0_CC3 0x0
+#endif
+
+// TCC0 Compare and Capture value 4 <0x00-0xFFFFFF>
+// tcc_arch_cc4
+#ifndef CONF_TCC0_CC4
+#define CONF_TCC0_CC4 0x0
+#endif
+
+// TCC0 Compare and Capture value 5 <0x00-0xFFFFFF>
+// tcc_arch_cc5
+#ifndef CONF_TCC0_CC5
+#define CONF_TCC0_CC5 0x0
+#endif
+
+/* Commented intentionally. No pattern control for timers. */
+/*#define CONF_TCC0_PATTB_PGEB0 0
+#define CONF_TCC0_PATTB_PGEB1 0
+#define CONF_TCC0_PATTB_PGEB2 0
+#define CONF_TCC0_PATTB_PGEB3 0
+#define CONF_TCC0_PATTB_PGEB4 0
+#define CONF_TCC0_PATTB_PGEB5 0
+#define CONF_TCC0_PATTB_PGEB6 0
+#define CONF_TCC0_PATTB_PGEB7 0
+#define CONF_TCC0_PATTB_PGVB0 0
+#define CONF_TCC0_PATTB_PGVB1 0
+#define CONF_TCC0_PATTB_PGVB2 0
+#define CONF_TCC0_PATTB_PGVB3 0
+#define CONF_TCC0_PATTB_PGVB4 0
+#define CONF_TCC0_PATTB_PGVB5 0
+#define CONF_TCC0_PATTB_PGVB6 0
+#define CONF_TCC0_PATTB_PGVB7 0*/
+
+/* Commented intentionally. No waveform control for timers. */
+/*#define CONF_TCC0_WAVEGENB TCC_WAVEB_WAVEGENB_MFRQ_Val
+#define CONF_TCC0_RAMPB TCC_WAVE_RAMP_RAMP1_Val
+#define CONF_TCC0_CIPERENB 0
+#define CONF_TCC0_CICCEN0B 0
+#define CONF_TCC0_CICCEN1B 0
+#define CONF_TCC0_CICCEN2B 0
+#define CONF_TCC0_CICCEN3B 0
+#define CONF_TCC0_POL0B 0
+#define CONF_TCC0_POL1B 0
+#define CONF_TCC0_POL2B 0
+#define CONF_TCC0_POL3B 0
+#define CONF_TCC0_POL4B 0
+#define CONF_TCC0_POL5B 0
+#define CONF_TCC0_POL6B 0
+#define CONF_TCC0_POL7B 0
+#define CONF_TCC0_SWAP0B 0
+#define CONF_TCC0_SWAP1B 0
+#define CONF_TCC0_SWAP2B 0
+#define CONF_TCC0_SWAP3B 0*/
+
+/* Commented intentionally. No buffering for timers. */
+/*#define CONF_TCC0_PERB 0
+#define CONF_TCC0_CCB0 0
+#define CONF_TCC0_CCB1 0
+#define CONF_TCC0_CCB2 0
+#define CONF_TCC0_CCB3 0*/
+//
+
+#define CONF_TCC0_CTRLA \
+ TCC_CTRLA_PRESCALER(CONF_TCC0_PRESCALER) | (CONF_TCC0_RUNSTDBY << TCC_CTRLA_RUNSTDBY_Pos) \
+ | TCC_CTRLA_PRESCSYNC(CONF_TCC0_PRESCSYNC) | (CONF_TCC0_CPTEN0 << TCC_CTRLA_CPTEN0_Pos) \
+ | (CONF_TCC0_CPTEN1 << TCC_CTRLA_CPTEN1_Pos) | (CONF_TCC0_CPTEN2 << TCC_CTRLA_CPTEN2_Pos) \
+ | (CONF_TCC0_CPTEN3 << TCC_CTRLA_CPTEN3_Pos) | (CONF_TCC0_CPTEN4 << TCC_CTRLA_CPTEN4_Pos) \
+ | (CONF_TCC0_CPTEN5 << TCC_CTRLA_CPTEN5_Pos) | (CONF_TCC0_ALOCK << TCC_CTRLA_ALOCK_Pos)
+#define CONF_TCC0_CTRLB (CONF_TCC0_LUPD << TCC_CTRLBSET_LUPD_Pos)
+#define CONF_TCC0_DBGCTRL (CONF_TCC0_DBGRUN << TCC_DBGCTRL_DBGRUN_Pos)
+#define CONF_TCC0_EVCTRL \
+ TCC_EVCTRL_CNTSEL(CONF_TCC0_CNTSEL) | (CONF_TCC0_OVFEO << TCC_EVCTRL_OVFEO_Pos) \
+ | (CONF_TCC0_TRGEO << TCC_EVCTRL_TRGEO_Pos) | (CONF_TCC0_CNTEO << TCC_EVCTRL_CNTEO_Pos) \
+ | (CONF_TCC0_MCEO0 << TCC_EVCTRL_MCEO0_Pos) | (CONF_TCC0_MCEI0 << TCC_EVCTRL_MCEI0_Pos) \
+ | (CONF_TCC0_MCEO1 << TCC_EVCTRL_MCEO1_Pos) | (CONF_TCC0_MCEI1 << TCC_EVCTRL_MCEI1_Pos) \
+ | (CONF_TCC0_MCEO2 << TCC_EVCTRL_MCEO2_Pos) | (CONF_TCC0_MCEI2 << TCC_EVCTRL_MCEI2_Pos) \
+ | (CONF_TCC0_MCEO3 << TCC_EVCTRL_MCEO3_Pos) | (CONF_TCC0_MCEI3 << TCC_EVCTRL_MCEI3_Pos) \
+ | (CONF_TCC0_MCEO4 << TCC_EVCTRL_MCEO4_Pos) | (CONF_TCC0_MCEI4 << TCC_EVCTRL_MCEI4_Pos) \
+ | (CONF_TCC0_MCEO5 << TCC_EVCTRL_MCEO5_Pos) | (CONF_TCC0_MCEI5 << TCC_EVCTRL_MCEI5_Pos) \
+ | (CONF_TCC0_TCEI0 << TCC_EVCTRL_TCEI0_Pos) | (CONF_TCC0_TCEI1 << TCC_EVCTRL_TCEI1_Pos) \
+ | (CONF_TCC0_TCINV0 << TCC_EVCTRL_TCINV0_Pos) | (CONF_TCC0_TCINV1 << TCC_EVCTRL_TCINV1_Pos) \
+ | TCC_EVCTRL_EVACT1(CONF_TCC0_EVACT1) | TCC_EVCTRL_EVACT0(CONF_TCC0_EVACT0)
+
+#include
+#ifndef CONF_TCC1_ENABLE
+#define CONF_TCC1_ENABLE 1
+#endif
+
+#ifndef CONF_TCC1_PWM_ENABLE
+#define CONF_TCC1_PWM_ENABLE 1
+#endif
+
+// Basic settings
+// TCC1 Prescaler
+// No division
+// Divide by 2
+// Divide by 4
+// Divide by 8
+// Divide by 16
+// Divide by 64
+// Divide by 256
+// Divide by 1024
+// This defines the TCC1 prescaler value
+// tcc_prescaler
+#ifndef CONF_TCC1_PRESCALER
+#define CONF_TCC1_PRESCALER TCC_CTRLA_PRESCALER_DIV2_Val
+#endif
+
+//
+// TCC1 Period Value <0x000000-0xFFFFFF>
+// tcc_per
+#ifndef CONF_TCC1_PER
+#define CONF_TCC1_PER 0x2710
+#endif
+//
+
+//
+
+// PWM Waveform Output settings
+// TCC1 Waveform Period Value (uS) <0x00-0xFFFFFFFF>
+// The unit of this value is us.
+// tcc_arch_wave_per_val
+#ifndef CONF_TCC1_WAVE_PER_VAL
+#define CONF_TCC1_WAVE_PER_VAL 0x30
+#endif
+
+// TCC1 Waveform Duty Value (0.1%) <0x00-0x03E8>
+// The unit of this value is 1/1000.
+// tcc_arch_wave_duty_val
+#ifndef CONF_TCC1_WAVE_DUTY_VAL
+#define CONF_TCC1_WAVE_DUTY_VAL 0x1f4
+#endif
+
+// TCC1 Waveform Channel Select <0x00-0x03>
+// Index of the Compare Channel register, into which the Waveform Duty Value is written.
+// Give index of the Compare Channel register here in 0x00-0x03 range.
+// tcc_arch_sel_ch
+#ifndef CONF_TCC1_SEL_CH
+#define CONF_TCC1_SEL_CH 0x2
+#endif
+
+/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
+#if CONF_TCC1_PRESCALER < TCC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TCC1_PER_REG \
+ ((uint32_t)(((double)CONF_TCC1_WAVE_PER_VAL * CONF_GCLK_TCC1_FREQUENCY) / 1000000 / (1 << CONF_TCC1_PRESCALER) - 1))
+#define CONF_TCC1_CCX_REG ((uint32_t)(((double)(double)CONF_TCC1_PER_REG * CONF_TCC1_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC1_PRESCALER == TCC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TCC1_PER_REG ((uint32_t)(((double)CONF_TCC1_WAVE_PER_VAL * CONF_GCLK_TCC1_FREQUENCY) / 64000000 - 1))
+#define CONF_TCC1_CCX_REG ((uint32_t)(((double)CONF_TCC1_PER_REG * CONF_TCC1_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC1_PRESCALER == TCC_CTRLA_PRESCALER_DIV256_Val
+#define CONF_TCC1_PER_REG ((uint32_t)(((double)CONF_TCC1_WAVE_PER_VAL * CONF_GCLK_TCC1_FREQUENCY) / 256000000 - 1))
+#define CONF_TCC1_CCX_REG ((uint32_t)(((double)CONF_TCC1_PER_REG * CONF_TCC1_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC1_PRESCALER == TCC_CTRLA_PRESCALER_DIV1024_Val
+#define CONF_TCC1_PER_REG ((uint32_t)(((double)CONF_TCC1_WAVE_PER_VAL * CONF_GCLK_TCC1_FREQUENCY) / 1024000000 - 1))
+#define CONF_TCC1_CCX_REG ((uint32_t)(((double)CONF_TCC1_PER_REG * CONF_TCC1_WAVE_DUTY_VAL) / 1000))
+#endif
+//
+
+// Advanced settings
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL A register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC1_RESOLUTION TCC_CTRLA_RESOLUTION_NONE_Val
+// Run in standby
+// Indicates whether the TCC1 will continue running in standby sleep mode or not
+// tcc_arch_runstdby
+#ifndef CONF_TCC1_RUNSTDBY
+#define CONF_TCC1_RUNSTDBY 0
+#endif
+
+// TCC1 Prescaler and Counter Synchronization Selection
+// Reload or reset counter on next GCLK
+// Reload or reset counter on next prescaler clock
+// Reload or reset counter on next GCLK and reset prescaler counter
+// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock.
+// tcc_arch_prescsync
+#ifndef CONF_TCC1_PRESCSYNC
+#define CONF_TCC1_PRESCSYNC TCC_CTRLA_PRESCSYNC_GCLK_Val
+#endif
+
+// TCC1 Waveform Generation Selection
+// Single-slope PWM
+// Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
+// Dual-slope, interrupt/event at ZERO (DSBOTTOM)
+// Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
+// Dual-slope, interrupt/event at Top (DSTOP)
+// tcc_arch_wavegen
+#ifndef CONF_TCC1_WAVEGEN
+#define CONF_TCC1_WAVEGEN TCC_WAVE_WAVEGEN_DSBOTH_Val
+#endif
+// TCC1 Auto Lock
+// Indicates whether the TCC1 Auto Lock is enabled or not
+// tcc_arch_alock
+#ifndef CONF_TCC1_ALOCK
+#define CONF_TCC1_ALOCK 0
+#endif
+
+// TCC1 Capture Channel 0 Enable
+// Indicates whether the TCC1 Capture Channel 0 is enabled or not
+// tcc_arch_cpten0
+#ifndef CONF_TCC1_CPTEN0
+#define CONF_TCC1_CPTEN0 0
+#endif
+
+// TCC1 Capture Channel 1 Enable
+// Indicates whether the TCC1 Capture Channel 1 is enabled or not
+// tcc_arch_cpten1
+#ifndef CONF_TCC1_CPTEN1
+#define CONF_TCC1_CPTEN1 0
+#endif
+
+// TCC1 Capture Channel 2 Enable
+// Indicates whether the TCC1 Capture Channel 2 is enabled or not
+// tcc_arch_cpten2
+#ifndef CONF_TCC1_CPTEN2
+#define CONF_TCC1_CPTEN2 0
+#endif
+
+// TCC1 Capture Channel 3 Enable
+// Indicates whether the TCC1 Capture Channel 3 is enabled or not
+// tcc_arch_cpten3
+#ifndef CONF_TCC1_CPTEN3
+#define CONF_TCC1_CPTEN3 0
+#endif
+
+//
+// TCC1 Capture Channel 4 Enable
+// Indicates whether the TCC1 Capture Channel 4 is enabled or not
+// tcc_arch_cpten4
+#ifndef CONF_TCC1_CPTEN4
+#define CONF_TCC1_CPTEN4 0
+#endif
+//
+//
+// TCC1 Capture Channel 5 Enable
+// Indicates whether the TCC1 Capture Channel 5 is enabled or not
+// tcc_arch_cpten5
+#ifndef CONF_TCC1_CPTEN5
+#define CONF_TCC1_CPTEN5 0
+#endif
+//
+//
+// TCC1 Capture Channel 6 Enable
+// Indicates whether the TCC1 Capture Channel 6 is enabled or not
+// tcc_arch_cpten6
+#ifndef CONF_TCC1_CPTEN6
+#define CONF_TCC1_CPTEN6 0
+#endif
+//
+//
+// TCC1 Capture Channel 7 Enable
+// Indicates whether the TCC1 Capture Channel 7 is enabled or not
+// tcc_arch_cpten7
+#ifndef CONF_TCC1_CPTEN7
+#define CONF_TCC1_CPTEN7 0
+#endif
+//
+
+// TCC1 Lock update
+// Indicates whether the TCC1 Lock update is enabled or not
+// tcc_arch_lupd
+#ifndef CONF_TCC1_LUPD
+#define CONF_TCC1_LUPD 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL B register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC1_DIR 0
+//#define CONF_TCC1_ONESHOT 0
+
+/* Commented intentionally. No fault control for timers. */
+/*#define CONF_TCC1_FAULT_A_SRC TCC_FCTRLA_SRC_DISABLE_Val
+#define CONF_TCC1_FAULT_A_KEEP 0
+#define CONF_TCC1_FAULT_A_QUAL 0
+#define CONF_TCC1_FAULT_A_BLANK TCC_FCTRLA_BLANK_DISABLE_Val
+#define CONF_TCC1_FAULT_A_RESTART 0
+#define CONF_TCC1_FAULT_A_HALT TCC_FCTRLA_HALT_DISABLE_Val
+#define CONF_TCC1_FAULT_A_CHSEL TCC_FCTRLA_CHSEL_CC0_Val
+#define CONF_TCC1_FAULT_A_CAPTURE TCC_FCTRLA_CAPTURE_DISABLE_Val
+#define CONF_TCC1_FAULT_A_BLACNKPRESC 0
+#define CONF_TCC1_FAULT_A_BLANKVAL 0
+#define CONF_TCC1_FAULT_A_FILTERVAL 0
+
+#define CONF_TCC1_FAULT_B_SRC TCC_FCTRLB_SRC_DISABLE_Val
+#define CONF_TCC1_FAULT_B_KEEP 0
+#define CONF_TCC1_FAULT_B_QUAL 0
+#define CONF_TCC1_FAULT_B_BLANK TCC_FCTRLB_BLANK_DISABLE_Val
+#define CONF_TCC1_FAULT_B_RESTART 0
+#define CONF_TCC1_FAULT_B_HALT TCC_FCTRLB_HALT_DISABLE_Val
+#define CONF_TCC1_FAULT_B_CHSEL TCC_FCTRLB_CHSEL_CC0_Val
+#define CONF_TCC1_FAULT_B_CAPTURE TCC_FCTRLB_CAPTURE_DISABLE_Val
+#define CONF_TCC1_FAULT_B_BLACNKPRESC 0
+#define CONF_TCC1_FAULT_B_BLANKVAL 0
+#define CONF_TCC1_FAULT_B_FILTERVAL 0*/
+
+/* Commented intentionally. No dead-time control for timers. */
+/*#define CONF_TCC1_OTMX 0
+#define CONF_TCC1_DTIEN0 0
+#define CONF_TCC1_DTIEN1 0
+#define CONF_TCC1_DTIEN2 0
+#define CONF_TCC1_DTIEN3 0
+#define CONF_TCC1_DTHS 0*/
+
+/* Commented intentionally. No driver control for timers. */
+/*#define CONF_TCC1_NRE0 0
+#define CONF_TCC1_NRE1 0
+#define CONF_TCC1_NRE2 0
+#define CONF_TCC1_NRE3 0
+#define CONF_TCC1_NRE4 0
+#define CONF_TCC1_NRE5 0
+#define CONF_TCC1_NRE6 0
+#define CONF_TCC1_NRE7 0
+#define CONF_TCC1_NVR0 0
+#define CONF_TCC1_NVR1 0
+#define CONF_TCC1_NVR2 0
+#define CONF_TCC1_NVR3 0
+#define CONF_TCC1_NVR4 0
+#define CONF_TCC1_NVR5 0
+#define CONF_TCC1_NVR6 0
+#define CONF_TCC1_NVR7 0
+#define CONF_TCC1_INVEN0 0
+#define CONF_TCC1_INVEN1 0
+#define CONF_TCC1_INVEN2 0
+#define CONF_TCC1_INVEN3 0
+#define CONF_TCC1_INVEN4 0
+#define CONF_TCC1_INVEN5 0
+#define CONF_TCC1_INVEN6 0
+#define CONF_TCC1_INVEN7 0
+#define CONF_TCC1_FILTERVAL0 0
+#define CONF_TCC1_FILTERVAL1 0*/
+
+// TCC1 Debug Running Mode
+// Indicates whether the TCC1 Debug Running Mode is enabled or not
+// tcc_arch_dbgrun
+#ifndef CONF_TCC1_DBGRUN
+#define CONF_TCC1_DBGRUN 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of Debug Control register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC1_FDDBD 0
+
+// Event control
+// timer_event_control
+#ifndef CONF_TCC1_EVENT_CONTROL_ENABLE
+#define CONF_TCC1_EVENT_CONTROL_ENABLE 1
+#endif
+
+// Match or Capture Channel 0 Event Output
+// This bit indicates whether match/capture event on channel 0 is enabled and will be generated
+// tcc_arch_mceo0
+#ifndef CONF_TCC1_MCEO0
+#define CONF_TCC1_MCEO0 0
+#endif
+
+// Match or Capture Channel 0 Event Input
+// This bit indicates whether match/capture 0 incoming event is enabled
+// tcc_arch_mcei0
+#ifndef CONF_TCC1_MCEI0
+#define CONF_TCC1_MCEI0 0
+#endif
+// Match or Capture Channel 1 Event Output
+// This bit indicates whether match/capture event on channel 1 is enabled and will be generated
+// tcc_arch_mceo1
+#ifndef CONF_TCC1_MCEO1
+#define CONF_TCC1_MCEO1 0
+#endif
+
+// Match or Capture Channel 1 Event Input
+// This bit indicates whether match/capture 1 incoming event is enabled
+// tcc_arch_mcei1
+#ifndef CONF_TCC1_MCEI1
+#define CONF_TCC1_MCEI1 0
+#endif
+// Match or Capture Channel 2 Event Output
+// This bit indicates whether match/capture event on channel 2 is enabled and will be generated
+// tcc_arch_mceo2
+#ifndef CONF_TCC1_MCEO2
+#define CONF_TCC1_MCEO2 0
+#endif
+
+// Match or Capture Channel 2 Event Input
+// This bit indicates whether match/capture 2 incoming event is enabled
+// tcc_arch_mcei2
+#ifndef CONF_TCC1_MCEI2
+#define CONF_TCC1_MCEI2 0
+#endif
+// Match or Capture Channel 3 Event Output
+// This bit indicates whether match/capture event on channel 3 is enabled and will be generated
+// tcc_arch_mceo3
+#ifndef CONF_TCC1_MCEO3
+#define CONF_TCC1_MCEO3 0
+#endif
+
+// Match or Capture Channel 3 Event Input
+// This bit indicates whether match/capture 3 incoming event is enabled
+// tcc_arch_mcei3
+#ifndef CONF_TCC1_MCEI3
+#define CONF_TCC1_MCEI3 0
+#endif
+
+// Timer/Counter Event Input 0
+// This bit is used to enable input event 0 to the TCC
+// tcc_arch_tcei0
+#ifndef CONF_TCC1_TCEI0
+#define CONF_TCC1_TCEI0 0
+#endif
+
+// Timer/Counter Event Input 0 Invert
+// This bit inverts the event 0 input
+// tcc_arch_tceinv0
+#ifndef CONF_TCC1_TCINV0
+#define CONF_TCC1_TCINV0 0
+#endif
+// Timer/Counter Event Input 1
+// This bit is used to enable input event 1 to the TCC
+// tcc_arch_tcei1
+#ifndef CONF_TCC1_TCEI1
+#define CONF_TCC1_TCEI1 0
+#endif
+
+// Timer/Counter Event Input 1 Invert
+// This bit inverts the event 1 input
+// tcc_arch_tceinv1
+#ifndef CONF_TCC1_TCINV1
+#define CONF_TCC1_TCINV1 0
+#endif
+
+// Timer/Counter Event Output
+// This bit is used to enable the counter cycle event.
+// tcc_arch_cnteo
+#ifndef CONF_TCC1_CNTEO
+#define CONF_TCC1_CNTEO 0
+#endif
+
+// Re-trigger Event Output
+// This bit is used to enable the counter re-trigger event.
+// tcc_arch_trgeo
+#ifndef CONF_TCC1_TRGEO
+#define CONF_TCC1_TRGEO 0
+#endif
+
+// Overflow/Underflow Event Output
+// This bit is used to enable enable event on overflow/underflow.
+// tcc_arch_ovfeo
+#ifndef CONF_TCC1_OVFEO
+#define CONF_TCC1_OVFEO 0
+#endif
+
+// Timer/Counter Interrupt and Event Output Selection
+// <0=> An interrupt/event is generated when a new counter cycle starts
+// <1=> An interrupt/event is generated when a counter cycle ends
+// <2=> An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
+// <3=> An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
+// These bits define on which part of the counter cycle the counter event output is generated
+// tcc_arch_cntsel
+#ifndef CONF_TCC1_CNTSEL
+#define CONF_TCC1_CNTSEL 0
+#endif
+
+// Timer/Counter Event Input 0 Action
+// <0=>Event action disabled
+// <1=>Start restart or re-trigger on event
+// <2=>Count on event
+// <3=>Start on event
+// <4=>Increment on event
+// <5=>Count on active state of asynchronous event
+// <6=>Capture overflow times (Max value)
+// <7=>Non-recoverable fault
+// These bits define the action the TCC performs on TCE0 event input 0
+// tcc_arch_evact0
+#ifndef CONF_TCC1_EVACT0
+#define CONF_TCC1_EVACT0 0
+#endif
+
+// Timer/Counter Event Input 1 Action
+// <0=>Event action disabled
+// <1=>Re-trigger counter on event
+// <2=>Direction control
+// <3=>Stop counter on event
+// <4=>Decrement counter on event
+// <5=>Period capture value in CC0 register, pulse width capture value in CC1 register
+// <6=>Period capture value in CC1 register, pulse width capture value in CC0 register
+// <7=>Non-recoverable fault
+// These bits define the action the TCC performs on TCE0 event input 0
+// tcc_arch_evact1
+#ifndef CONF_TCC1_EVACT1
+#define CONF_TCC1_EVACT1 0
+#endif
+//
+
+/* Commented intentionally. No pattern control for timers. */
+/*#define CONF_TCC1_PGE0 0
+#define CONF_TCC1_PGE1 0
+#define CONF_TCC1_PGE2 0
+#define CONF_TCC1_PGE3 0
+#define CONF_TCC1_PGE4 0
+#define CONF_TCC1_PGE5 0
+#define CONF_TCC1_PGE6 0
+#define CONF_TCC1_PGE7 0
+#define CONF_TCC1_PGV0 0
+#define CONF_TCC1_PGV1 0
+#define CONF_TCC1_PGV2 0
+#define CONF_TCC1_PGV3 0
+#define CONF_TCC1_PGV4 0
+#define CONF_TCC1_PGV5 0
+#define CONF_TCC1_PGV6 0
+#define CONF_TCC1_PGV7 0*/
+
+/* Commented intentionally. No pattern waveform control for timers. */
+/*#define CONF_TCC1_WAVEGEN TCC_WAVE_WAVEGEN_MFRQ_Val
+#define CONF_TCC1_RAMP TCC_WAVE_RAMP_RAMP1_Val
+#define CONF_TCC1_CIPEREN 0
+#define CONF_TCC1_CICCEN0 0
+#define CONF_TCC1_CICCEN1 0
+#define CONF_TCC1_CICCEN2 0
+#define CONF_TCC1_CICCEN3 0
+#define CONF_TCC1_POL0 0
+#define CONF_TCC1_POL1 0
+#define CONF_TCC1_POL2 0
+#define CONF_TCC1_POL3 0
+#define CONF_TCC1_POL4 0
+#define CONF_TCC1_POL5 0
+#define CONF_TCC1_POL6 0
+#define CONF_TCC1_POL7 0
+#define CONF_TCC1_SWAP0 0
+#define CONF_TCC1_SWAP1 0
+#define CONF_TCC1_SWAP2 0
+#define CONF_TCC1_SWAP3 0*/
+
+// TCC1 Compare and Capture value 0 <0x00-0xFFFFFF>
+// tcc_arch_cc0
+#ifndef CONF_TCC1_CC0
+#define CONF_TCC1_CC0 0x0
+#endif
+
+// TCC1 Compare and Capture value 1 <0x00-0xFFFFFF>
+// tcc_arch_cc1
+#ifndef CONF_TCC1_CC1
+#define CONF_TCC1_CC1 0x0
+#endif
+
+// TCC1 Compare and Capture value 2 <0x00-0xFFFFFF>
+// tcc_arch_cc2
+#ifndef CONF_TCC1_CC2
+#define CONF_TCC1_CC2 0x0
+#endif
+
+// TCC1 Compare and Capture value 3 <0x00-0xFFFFFF>
+// tcc_arch_cc3
+#ifndef CONF_TCC1_CC3
+#define CONF_TCC1_CC3 0x0
+#endif
+
+/* Commented intentionally. No pattern control for timers. */
+/*#define CONF_TCC1_PATTB_PGEB0 0
+#define CONF_TCC1_PATTB_PGEB1 0
+#define CONF_TCC1_PATTB_PGEB2 0
+#define CONF_TCC1_PATTB_PGEB3 0
+#define CONF_TCC1_PATTB_PGEB4 0
+#define CONF_TCC1_PATTB_PGEB5 0
+#define CONF_TCC1_PATTB_PGEB6 0
+#define CONF_TCC1_PATTB_PGEB7 0
+#define CONF_TCC1_PATTB_PGVB0 0
+#define CONF_TCC1_PATTB_PGVB1 0
+#define CONF_TCC1_PATTB_PGVB2 0
+#define CONF_TCC1_PATTB_PGVB3 0
+#define CONF_TCC1_PATTB_PGVB4 0
+#define CONF_TCC1_PATTB_PGVB5 0
+#define CONF_TCC1_PATTB_PGVB6 0
+#define CONF_TCC1_PATTB_PGVB7 0*/
+
+/* Commented intentionally. No waveform control for timers. */
+/*#define CONF_TCC1_WAVEGENB TCC_WAVEB_WAVEGENB_MFRQ_Val
+#define CONF_TCC1_RAMPB TCC_WAVE_RAMP_RAMP1_Val
+#define CONF_TCC1_CIPERENB 0
+#define CONF_TCC1_CICCEN0B 0
+#define CONF_TCC1_CICCEN1B 0
+#define CONF_TCC1_CICCEN2B 0
+#define CONF_TCC1_CICCEN3B 0
+#define CONF_TCC1_POL0B 0
+#define CONF_TCC1_POL1B 0
+#define CONF_TCC1_POL2B 0
+#define CONF_TCC1_POL3B 0
+#define CONF_TCC1_POL4B 0
+#define CONF_TCC1_POL5B 0
+#define CONF_TCC1_POL6B 0
+#define CONF_TCC1_POL7B 0
+#define CONF_TCC1_SWAP0B 0
+#define CONF_TCC1_SWAP1B 0
+#define CONF_TCC1_SWAP2B 0
+#define CONF_TCC1_SWAP3B 0*/
+
+/* Commented intentionally. No buffering for timers. */
+/*#define CONF_TCC1_PERB 0
+#define CONF_TCC1_CCB0 0
+#define CONF_TCC1_CCB1 0
+#define CONF_TCC1_CCB2 0
+#define CONF_TCC1_CCB3 0*/
+//
+
+#define CONF_TCC1_CTRLA \
+ TCC_CTRLA_PRESCALER(CONF_TCC1_PRESCALER) | (CONF_TCC1_RUNSTDBY << TCC_CTRLA_RUNSTDBY_Pos) \
+ | TCC_CTRLA_PRESCSYNC(CONF_TCC1_PRESCSYNC) | (CONF_TCC1_CPTEN0 << TCC_CTRLA_CPTEN0_Pos) \
+ | (CONF_TCC1_CPTEN1 << TCC_CTRLA_CPTEN1_Pos) | (CONF_TCC1_CPTEN2 << TCC_CTRLA_CPTEN2_Pos) \
+ | (CONF_TCC1_CPTEN3 << TCC_CTRLA_CPTEN3_Pos) | (CONF_TCC1_ALOCK << TCC_CTRLA_ALOCK_Pos)
+#define CONF_TCC1_CTRLB (CONF_TCC1_LUPD << TCC_CTRLBSET_LUPD_Pos)
+#define CONF_TCC1_DBGCTRL (CONF_TCC1_DBGRUN << TCC_DBGCTRL_DBGRUN_Pos)
+#define CONF_TCC1_EVCTRL \
+ TCC_EVCTRL_CNTSEL(CONF_TCC1_CNTSEL) | (CONF_TCC1_OVFEO << TCC_EVCTRL_OVFEO_Pos) \
+ | (CONF_TCC1_TRGEO << TCC_EVCTRL_TRGEO_Pos) | (CONF_TCC1_CNTEO << TCC_EVCTRL_CNTEO_Pos) \
+ | (CONF_TCC1_MCEO0 << TCC_EVCTRL_MCEO0_Pos) | (CONF_TCC1_MCEI0 << TCC_EVCTRL_MCEI0_Pos) \
+ | (CONF_TCC1_MCEO1 << TCC_EVCTRL_MCEO1_Pos) | (CONF_TCC1_MCEI1 << TCC_EVCTRL_MCEI1_Pos) \
+ | (CONF_TCC1_MCEO2 << TCC_EVCTRL_MCEO2_Pos) | (CONF_TCC1_MCEI2 << TCC_EVCTRL_MCEI2_Pos) \
+ | (CONF_TCC1_MCEO3 << TCC_EVCTRL_MCEO3_Pos) | (CONF_TCC1_MCEI3 << TCC_EVCTRL_MCEI3_Pos) \
+ | (CONF_TCC1_TCEI0 << TCC_EVCTRL_TCEI0_Pos) | (CONF_TCC1_TCEI1 << TCC_EVCTRL_TCEI1_Pos) \
+ | (CONF_TCC1_TCINV0 << TCC_EVCTRL_TCINV0_Pos) | (CONF_TCC1_TCINV1 << TCC_EVCTRL_TCINV1_Pos) \
+ | TCC_EVCTRL_EVACT1(CONF_TCC1_EVACT1) | TCC_EVCTRL_EVACT0(CONF_TCC1_EVACT0)
+
+// <<< end of configuration section >>>
+
+#endif // HPL_TCC_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/peripheral_clk_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/peripheral_clk_config.h
new file mode 100644
index 0000000..5fb0e21
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/peripheral_clk_config.h
@@ -0,0 +1,1229 @@
+/* Auto-generated config file peripheral_clk_config.h */
+#ifndef PERIPHERAL_CLK_CONFIG_H
+#define PERIPHERAL_CLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// ADC Clock Source
+// adc_gclk_selection
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for ADC.
+#ifndef CONF_GCLK_ADC0_SRC
+#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_ADC0_FREQUENCY
+ * \brief ADC0's Clock frequency
+ */
+#ifndef CONF_GCLK_ADC0_FREQUENCY
+#define CONF_GCLK_ADC0_FREQUENCY 100000000
+#endif
+
+// ADC Clock Source
+// adc_gclk_selection
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for ADC.
+#ifndef CONF_GCLK_ADC1_SRC
+#define CONF_GCLK_ADC1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_ADC1_FREQUENCY
+ * \brief ADC1's Clock frequency
+ */
+#ifndef CONF_GCLK_ADC1_FREQUENCY
+#define CONF_GCLK_ADC1_FREQUENCY 100000000
+#endif
+
+// CCL Clock Source
+// ccl_gclk_selection
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for CCL.
+#ifndef CONF_GCLK_CCL_SRC
+#define CONF_GCLK_CCL_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_CCL_FREQUENCY
+ * \brief CCL's Clock frequency
+ */
+#ifndef CONF_GCLK_CCL_FREQUENCY
+#define CONF_GCLK_CCL_FREQUENCY 100000000
+#endif
+
+// EIC Clock Source
+// eic_gclk_selection
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for EIC.
+#ifndef CONF_GCLK_EIC_SRC
+#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EIC_FREQUENCY
+ * \brief EIC's Clock frequency
+ */
+#ifndef CONF_GCLK_EIC_FREQUENCY
+#define CONF_GCLK_EIC_FREQUENCY 100000000
+#endif
+
+// EVSYS Channel 0 Clock Source
+// evsys_clk_selection_0
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for channel 0.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 100000000
+#endif
+
+// EVSYS Channel 1 Clock Source
+// evsys_clk_selection_1
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for channel 1.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 100000000
+#endif
+
+// EVSYS Channel 2 Clock Source
+// evsys_clk_selection_2
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for channel 2.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 100000000
+#endif
+
+// EVSYS Channel 3 Clock Source
+// evsys_clk_selection_3
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for channel 3.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 100000000
+#endif
+
+// EVSYS Channel 4 Clock Source
+// evsys_clk_selection_4
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for channel 4.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 100000000
+#endif
+
+// EVSYS Channel 5 Clock Source
+// evsys_clk_selection_5
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for channel 5.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 100000000
+#endif
+
+// EVSYS Channel 6 Clock Source
+// evsys_clk_selection_6
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for channel 6.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 100000000
+#endif
+
+// EVSYS Channel 7 Clock Source
+// evsys_clk_selection_7
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for channel 7.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 100000000
+#endif
+
+// EVSYS Channel 8 Clock Source
+// evsys_clk_selection_8
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for channel 8.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 100000000
+#endif
+
+// EVSYS Channel 9 Clock Source
+// evsys_clk_selection_9
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+// Generic clock generator 11
+
+// Select the clock source for channel 9.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 100000000
+#endif
+
+// EVSYS Channel 10 Clock Source
+// evsys_clk_selection_10
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Generic clock generator 5
+
+// Generic clock generator 6
+
+// Generic clock generator 7
+
+// Generic clock generator 8
+
+// Generic clock generator 9
+
+// Generic clock generator 10
+
+//