From 8c9f4877777dba796a3a263e231145fbf52c95a5 Mon Sep 17 00:00:00 2001
From: Nicolas Trimborn <ge37vez@mytum.de>
Date: Sun, 5 Sep 2021 17:31:58 +0200
Subject: [PATCH] ported to d51, msif not triggering with event

---
 .../Two_Motor_D51/Two_Motor_D51.atsln         |    22 +
 .../.atmelstart/AtmelStart.env_conf           |     6 +
 .../.atmelstart/AtmelStart.gpdsc              |   251 +
 .../.atmelstart/atmel_start_config.atstart    |  2712 +++++
 .../Two_Motor_D51/Two_Motor_D51/ADS1299.c     |   330 +
 .../Two_Motor_D51/Two_Motor_D51/ADS1299.h     |   113 +
 .../Two_Motor_D51/Config/RTE_Components.h     |    54 +
 .../Two_Motor_D51/Config/hpl_adc_config.h     |   595 +
 .../Two_Motor_D51/Config/hpl_ccl_config.h     |   499 +
 .../Two_Motor_D51/Config/hpl_cmcc_config.h    |    54 +
 .../Two_Motor_D51/Config/hpl_dmac_config.h    |  7277 +++++++++++
 .../Two_Motor_D51/Config/hpl_eic_config.h     |   913 ++
 .../Two_Motor_D51/Config/hpl_evsys_config.h   |  8363 +++++++++++++
 .../Two_Motor_D51/Config/hpl_gclk_config.h    |   920 ++
 .../Two_Motor_D51/Config/hpl_mclk_config.h    |   104 +
 .../Config/hpl_osc32kctrl_config.h            |   165 +
 .../Two_Motor_D51/Config/hpl_oscctrl_config.h |   640 +
 .../Two_Motor_D51/Config/hpl_port_config.h    |   284 +
 .../Two_Motor_D51/Config/hpl_qspi_config.h    |    98 +
 .../Two_Motor_D51/Config/hpl_sercom_config.h  |   643 +
 .../Two_Motor_D51/Config/hpl_tcc_config.h     |  1124 ++
 .../Config/peripheral_clk_config.h            |  1229 ++
 .../Two_Motor_D51/Two_Motor_D51/Default.xml   |   475 +
 .../Device_Startup/samd51j18a_flash.ld        |   163 +
 .../Device_Startup/samd51j18a_sram.ld         |   162 +
 .../Device_Startup/startup_samd51.c           |   546 +
 .../Device_Startup/system_samd51.c            |    64 +
 .../Two_Motor_D51/Ethercat_QSPI.c             |   219 +
 .../Two_Motor_D51/Ethercat_QSPI.h             |    38 +
 .../Two_Motor_D51/Ethercat_SlaveDef.h         |   352 +
 .../Two_Motor_D51.componentinfo.xml           |   169 +
 .../Two_Motor_D51/Two_Motor_D51.cproj         |  1133 ++
 .../Two_Motor_D51/angle_sensors.c             |   130 +
 .../Two_Motor_D51/angle_sensors.h             |   111 +
 .../Two_Motor_D51/Two_Motor_D51/arm_math.h    |  7157 +++++++++++
 .../Two_Motor_D51/Two_Motor_D51/atmel_start.c |     9 +
 .../Two_Motor_D51/Two_Motor_D51/atmel_start.h |    18 +
 .../Two_Motor_D51/atmel_start_pins.h          |    80 +
 .../Two_Motor_D51/Two_Motor_D51/bldc.c        |   554 +
 .../Two_Motor_D51/Two_Motor_D51/bldc.h        |   110 +
 .../Two_Motor_D51/Two_Motor_D51/bldc_types.h  |   107 +
 .../Two_Motor_D51/cmsis/arm_math.h            |  7157 +++++++++++
 .../cmsis/libarm_cortexM4lf_math.a            |   Bin 0 -> 3193956 bytes
 .../Two_Motor_D51/configuration.h             |   286 +
 .../Two_Motor_D51/Two_Motor_D51/control.h     |   262 +
 .../Two_Motor_D51/Two_Motor_D51/driver_init.c |   833 ++
 .../Two_Motor_D51/Two_Motor_D51/driver_init.h |   133 +
 .../Two_Motor_D51/examples/driver_examples.c  |   196 +
 .../Two_Motor_D51/examples/driver_examples.h  |    36 +
 .../hal/documentation/adc_sync.rst            |    74 +
 .../hal/documentation/custom_logic.rst        |    32 +
 .../Two_Motor_D51/hal/documentation/evsys.rst |    24 +
 .../hal/documentation/ext_irq.rst             |    39 +
 .../hal/documentation/i2c_master_async.rst    |   110 +
 .../Two_Motor_D51/hal/documentation/pwm.rst   |    53 +
 .../hal/documentation/quad_spi_dma.rst        |    46 +
 .../hal/documentation/spi_master_dma.rst      |    56 +
 .../hal/documentation/spi_master_sync.rst     |    51 +
 .../Two_Motor_D51/hal/include/hal_adc_sync.h  |   277 +
 .../Two_Motor_D51/hal/include/hal_atomic.h    |   120 +
 .../Two_Motor_D51/hal/include/hal_cache.h     |    96 +
 .../hal/include/hal_custom_logic.h            |    89 +
 .../Two_Motor_D51/hal/include/hal_delay.h     |    89 +
 .../Two_Motor_D51/hal/include/hal_evsys.h     |   116 +
 .../Two_Motor_D51/hal/include/hal_ext_irq.h   |   118 +
 .../Two_Motor_D51/hal/include/hal_gpio.h      |   201 +
 .../hal/include/hal_i2c_m_async.h             |   327 +
 .../Two_Motor_D51/hal/include/hal_init.h      |    72 +
 .../Two_Motor_D51/hal/include/hal_io.h        |   110 +
 .../Two_Motor_D51/hal/include/hal_pwm.h       |   151 +
 .../Two_Motor_D51/hal/include/hal_qspi_dma.h  |   137 +
 .../Two_Motor_D51/hal/include/hal_sleep.h     |    74 +
 .../Two_Motor_D51/hal/include/hal_spi_m_dma.h |   257 +
 .../hal/include/hal_spi_m_sync.h              |   221 +
 .../Two_Motor_D51/hal/include/hpl_adc_async.h |   264 +
 .../Two_Motor_D51/hal/include/hpl_adc_dma.h   |   243 +
 .../Two_Motor_D51/hal/include/hpl_adc_sync.h  |   271 +
 .../Two_Motor_D51/hal/include/hpl_cmcc.h      |   277 +
 .../Two_Motor_D51/hal/include/hpl_core.h      |    56 +
 .../hal/include/hpl_custom_logic.h            |    69 +
 .../Two_Motor_D51/hal/include/hpl_delay.h     |    97 +
 .../Two_Motor_D51/hal/include/hpl_dma.h       |   176 +
 .../Two_Motor_D51/hal/include/hpl_evsys.h     |    94 +
 .../Two_Motor_D51/hal/include/hpl_ext_irq.h   |    95 +
 .../Two_Motor_D51/hal/include/hpl_gpio.h      |   185 +
 .../hal/include/hpl_i2c_m_async.h             |   205 +
 .../hal/include/hpl_i2c_m_sync.h              |   185 +
 .../hal/include/hpl_i2c_s_async.h             |   184 +
 .../hal/include/hpl_i2c_s_sync.h              |   184 +
 .../Two_Motor_D51/hal/include/hpl_init.h      |   124 +
 .../Two_Motor_D51/hal/include/hpl_irq.h       |   116 +
 .../hal/include/hpl_missing_features.h        |    37 +
 .../Two_Motor_D51/hal/include/hpl_pwm.h       |   193 +
 .../Two_Motor_D51/hal/include/hpl_qspi.h      |   149 +
 .../Two_Motor_D51/hal/include/hpl_qspi_dma.h  |   146 +
 .../Two_Motor_D51/hal/include/hpl_qspi_sync.h |   105 +
 .../Two_Motor_D51/hal/include/hpl_ramecc.h    |   100 +
 .../Two_Motor_D51/hal/include/hpl_reset.h     |    93 +
 .../Two_Motor_D51/hal/include/hpl_sleep.h     |    88 +
 .../Two_Motor_D51/hal/include/hpl_spi.h       |   163 +
 .../Two_Motor_D51/hal/include/hpl_spi_async.h |   131 +
 .../Two_Motor_D51/hal/include/hpl_spi_dma.h   |    88 +
 .../hal/include/hpl_spi_m_async.h             |   243 +
 .../Two_Motor_D51/hal/include/hpl_spi_m_dma.h |   182 +
 .../hal/include/hpl_spi_m_sync.h              |   166 +
 .../hal/include/hpl_spi_s_async.h             |   232 +
 .../hal/include/hpl_spi_s_sync.h              |   232 +
 .../Two_Motor_D51/hal/include/hpl_spi_sync.h  |    70 +
 .../Two_Motor_D51/hal/include/hpl_timer.h     |   160 +
 .../Two_Motor_D51/hal/include/hpl_usart.h     |   113 +
 .../hal/include/hpl_usart_async.h             |   270 +
 .../hal/include/hpl_usart_sync.h              |   254 +
 .../Two_Motor_D51/hal/src/hal_adc_sync.c      |   244 +
 .../Two_Motor_D51/hal/src/hal_atomic.c        |    66 +
 .../Two_Motor_D51/hal/src/hal_cache.c         |    78 +
 .../Two_Motor_D51/hal/src/hal_delay.c         |    80 +
 .../Two_Motor_D51/hal/src/hal_evsys.c         |    98 +
 .../Two_Motor_D51/hal/src/hal_ext_irq.c       |   188 +
 .../Two_Motor_D51/hal/src/hal_gpio.c          |    44 +
 .../Two_Motor_D51/hal/src/hal_i2c_m_async.c   |   389 +
 .../Two_Motor_D51/hal/src/hal_init.c          |    47 +
 .../Two_Motor_D51/hal/src/hal_io.c            |    63 +
 .../Two_Motor_D51/hal/src/hal_pwm.c           |   159 +
 .../Two_Motor_D51/hal/src/hal_qspi_dma.c      |    96 +
 .../Two_Motor_D51/hal/src/hal_sleep.c         |    73 +
 .../Two_Motor_D51/hal/src/hal_spi_m_dma.c     |   183 +
 .../Two_Motor_D51/hal/src/hal_spi_m_sync.c    |   201 +
 .../hal/utils/include/compiler.h              |    64 +
 .../hal/utils/include/err_codes.h             |    73 +
 .../Two_Motor_D51/hal/utils/include/events.h  |    54 +
 .../Two_Motor_D51/hal/utils/include/parts.h   |    41 +
 .../Two_Motor_D51/hal/utils/include/utils.h   |   368 +
 .../hal/utils/include/utils_assert.h          |    93 +
 .../hal/utils/include/utils_event.h           |   115 +
 .../hal/utils/include/utils_increment_macro.h |   308 +
 .../hal/utils/include/utils_list.h            |   164 +
 .../hal/utils/include/utils_repeat_macro.h    |   322 +
 .../hal/utils/src/utils_assert.c              |    46 +
 .../Two_Motor_D51/hal/utils/src/utils_event.c |   125 +
 .../Two_Motor_D51/hal/utils/src/utils_list.c  |   136 +
 .../hal/utils/src/utils_syscalls.c            |   152 +
 .../Two_Motor_D51/hpl/adc/hpl_adc.c           |   769 ++
 .../Two_Motor_D51/hpl/adc/hpl_adc_base.h      |    72 +
 .../Two_Motor_D51/hpl/ccl/hpl_ccl.c           |    97 +
 .../Two_Motor_D51/hpl/cmcc/hpl_cmcc.c         |   354 +
 .../Two_Motor_D51/hpl/core/hpl_core_m4.c      |   241 +
 .../Two_Motor_D51/hpl/core/hpl_core_port.h    |    61 +
 .../Two_Motor_D51/hpl/core/hpl_init.c         |    80 +
 .../Two_Motor_D51/hpl/dmac/hpl_dmac.c         |   260 +
 .../Two_Motor_D51/hpl/doc_lite/tc.rst         |    39 +
 .../Two_Motor_D51/hpl/eic/hpl_eic.c           |   299 +
 .../Two_Motor_D51/hpl/evsys/hpl_evsys.c       |   140 +
 .../Two_Motor_D51/hpl/gclk/hpl_gclk.c         |   312 +
 .../Two_Motor_D51/hpl/gclk/hpl_gclk_base.h    |    87 +
 .../Two_Motor_D51/hpl/mclk/hpl_mclk.c         |    44 +
 .../hpl/osc32kctrl/hpl_osc32kctrl.c           |    82 +
 .../Two_Motor_D51/hpl/oscctrl/hpl_oscctrl.c   |   230 +
 .../Two_Motor_D51/hpl/pm/hpl_pm.c             |    68 +
 .../Two_Motor_D51/hpl/pm/hpl_pm_base.h        |    45 +
 .../Two_Motor_D51/hpl/port/hpl_gpio_base.h    |   170 +
 .../Two_Motor_D51/hpl/qspi/hpl_qspi.c         |   331 +
 .../Two_Motor_D51/hpl/ramecc/hpl_ramecc.c     |    83 +
 .../Two_Motor_D51/hpl/sercom/hpl_sercom.c     |  3462 ++++++
 .../Two_Motor_D51/hpl/tc/tc_lite.c            |   309 +
 .../Two_Motor_D51/hpl/tc/tc_lite.h            |    82 +
 .../Two_Motor_D51/hpl/tcc/hpl_tcc.c           |   394 +
 .../Two_Motor_D51/hpl/tcc/hpl_tcc.h           |    77 +
 .../Two_Motor_D51/hri/hri_ac_d51.h            |  1836 +++
 .../Two_Motor_D51/hri/hri_adc_d51.h           |  3663 ++++++
 .../Two_Motor_D51/hri/hri_aes_d51.h           |  1287 ++
 .../Two_Motor_D51/hri/hri_ccl_d51.h           |   776 ++
 .../Two_Motor_D51/hri/hri_cmcc_d51.h          |   361 +
 .../Two_Motor_D51/Two_Motor_D51/hri/hri_d51.h |    75 +
 .../Two_Motor_D51/hri/hri_dac_d51.h           |  1706 +++
 .../Two_Motor_D51/hri/hri_dmac_d51.h          |  6800 +++++++++++
 .../Two_Motor_D51/hri/hri_dsu_d51.h           |  1256 ++
 .../Two_Motor_D51/hri/hri_eic_d51.h           |  1838 +++
 .../Two_Motor_D51/hri/hri_evsys_d51.h         |  1707 +++
 .../Two_Motor_D51/hri/hri_freqm_d51.h         |   464 +
 .../Two_Motor_D51/hri/hri_gclk_d51.h          |   805 ++
 .../Two_Motor_D51/hri/hri_hmatrixb_d51.h      |   237 +
 .../Two_Motor_D51/hri/hri_i2s_d51.h           |  3032 +++++
 .../Two_Motor_D51/hri/hri_icm_d51.h           |   761 ++
 .../Two_Motor_D51/hri/hri_mclk_d51.h          |  3396 ++++++
 .../Two_Motor_D51/hri/hri_nvmctrl_d51.h       |  1618 +++
 .../Two_Motor_D51/hri/hri_osc32kctrl_d51.h    |  1199 ++
 .../Two_Motor_D51/hri/hri_oscctrl_d51.h       |  4441 +++++++
 .../Two_Motor_D51/hri/hri_pac_d51.h           |  1469 +++
 .../Two_Motor_D51/hri/hri_pcc_d51.h           |   298 +
 .../Two_Motor_D51/hri/hri_pdec_d51.h          |  2684 ++++
 .../Two_Motor_D51/hri/hri_pm_d51.h            |   820 ++
 .../Two_Motor_D51/hri/hri_port_d51.h          |  2528 ++++
 .../Two_Motor_D51/hri/hri_qspi_d51.h          |  2058 ++++
 .../Two_Motor_D51/hri/hri_ramecc_d51.h        |   362 +
 .../Two_Motor_D51/hri/hri_rstc_d51.h          |   142 +
 .../Two_Motor_D51/hri/hri_rtc_d51.h           | 10139 ++++++++++++++++
 .../Two_Motor_D51/hri/hri_sdhc_d51.h          |  7477 ++++++++++++
 .../Two_Motor_D51/hri/hri_sercom_d51.h        |  8892 ++++++++++++++
 .../Two_Motor_D51/hri/hri_supc_d51.h          |  1769 +++
 .../Two_Motor_D51/hri/hri_tc_d51.h            |  3003 +++++
 .../Two_Motor_D51/hri/hri_tcc_d51.h           |  9992 +++++++++++++++
 .../Two_Motor_D51/hri/hri_trng_d51.h          |   380 +
 .../Two_Motor_D51/hri/hri_usb_d51.h           |  9335 ++++++++++++++
 .../Two_Motor_D51/hri/hri_wdt_d51.h           |   617 +
 .../Two_Motor_D51/Two_Motor_D51/interrupts.h  |   156 +
 .../Two_Motor_D51/Two_Motor_D51/main.c        |   291 +
 .../Two_Motor_D51/motorparameters.h           |   211 +
 .../Two_Motor_D51/statemachine.h              |    76 +
 .../Two_Motor_D51/Two_Motor_D51/utilities.h   |   181 +
 Twincat/MotorData/.vs/MotorData/v15/.suo      |   Bin 68096 -> 42496 bytes
 210 files changed, 168272 insertions(+)
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51.atsln
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.env_conf
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.gpdsc
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/atmel_start_config.atstart
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/RTE_Components.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_adc_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_ccl_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_cmcc_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_dmac_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_eic_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_evsys_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_gclk_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_mclk_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_osc32kctrl_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_oscctrl_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_port_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_qspi_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_sercom_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_tcc_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/peripheral_clk_config.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Default.xml
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/samd51j18a_flash.ld
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/samd51j18a_sram.ld
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/startup_samd51.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/system_samd51.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_QSPI.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_QSPI.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_SlaveDef.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.componentinfo.xml
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.cproj
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/angle_sensors.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/angle_sensors.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/arm_math.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start_pins.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc_types.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/cmsis/arm_math.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/cmsis/libarm_cortexM4lf_math.a
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/configuration.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/control.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/driver_init.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/driver_init.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/examples/driver_examples.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/examples/driver_examples.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/adc_sync.rst
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/custom_logic.rst
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/evsys.rst
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/ext_irq.rst
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/i2c_master_async.rst
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/pwm.rst
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/quad_spi_dma.rst
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/spi_master_dma.rst
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/spi_master_sync.rst
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_adc_sync.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_atomic.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_cache.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_custom_logic.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_delay.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_evsys.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_ext_irq.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_gpio.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_i2c_m_async.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_init.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_io.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_pwm.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_qspi_dma.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_sleep.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_spi_m_dma.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_spi_m_sync.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_adc_async.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_adc_dma.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_adc_sync.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_cmcc.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_core.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_custom_logic.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_delay.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_dma.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_evsys.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_ext_irq.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_gpio.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_m_async.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_m_sync.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_s_async.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_s_sync.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_init.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_irq.h
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 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_pwm.h
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 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_qspi_dma.h
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 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_reset.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_sleep.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi.h
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 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_evsys.c
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 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_gpio.c
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 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_init.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_io.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_pwm.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_qspi_dma.c
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 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/compiler.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/err_codes.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/events.h
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 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_assert.h
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 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_increment_macro.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_list.h
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 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_syscalls.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/adc/hpl_adc.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/adc/hpl_adc_base.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/ccl/hpl_ccl.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/cmcc/hpl_cmcc.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/core/hpl_core_m4.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/core/hpl_core_port.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/core/hpl_init.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/dmac/hpl_dmac.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/doc_lite/tc.rst
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/eic/hpl_eic.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/evsys/hpl_evsys.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/gclk/hpl_gclk.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/gclk/hpl_gclk_base.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/mclk/hpl_mclk.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/osc32kctrl/hpl_osc32kctrl.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/oscctrl/hpl_oscctrl.c
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 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/pm/hpl_pm_base.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/port/hpl_gpio_base.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/qspi/hpl_qspi.c
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 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/sercom/hpl_sercom.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tc/tc_lite.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tc/tc_lite.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tcc/hpl_tcc.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tcc/hpl_tcc.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_ac_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_adc_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_aes_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_ccl_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_cmcc_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_dac_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_dmac_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_dsu_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_eic_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_evsys_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_freqm_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_gclk_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_hmatrixb_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_i2s_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_icm_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_mclk_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_nvmctrl_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_osc32kctrl_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_oscctrl_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pac_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pcc_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pdec_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pm_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_port_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_qspi_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_ramecc_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_rstc_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_rtc_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_sdhc_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_sercom_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_supc_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_tc_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_tcc_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_trng_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_usb_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_wdt_d51.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/interrupts.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/main.c
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/motorparameters.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/statemachine.h
 create mode 100644 2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/utilities.h

diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51.atsln b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51.atsln
new file mode 100644
index 0000000..b6441c5
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51.atsln
@@ -0,0 +1,22 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "Two_Motor_D51", "Two_Motor_D51\Two_Motor_D51.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.env_conf b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.env_conf
new file mode 100644
index 0000000..d052f3a
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.env_conf
@@ -0,0 +1,6 @@
+<environment>
+  <configurations/>
+  <device-packs>
+    <device-pack device="ATSAMD51J18A" name="SAMD51_DFP" vendor="Atmel" version="1.2.139"/>
+  </device-packs>
+</environment>
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.gpdsc b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.gpdsc
new file mode 100644
index 0000000..4f2fef4
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.gpdsc
@@ -0,0 +1,251 @@
+<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
+  <vendor>Atmel</vendor>
+  <name>Two_Motor_D51</name>
+  <description>Project generated by Atmel Start</description>
+  <url>http://start.atmel.com/</url>
+  <releases>
+    <release version="1.0.1">Initial version</release>
+  </releases>
+  <taxonomy>
+    <description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
+  </taxonomy>
+  <generators>
+    <generator id="AtmelStart">
+      <description>Atmel Start</description>
+      <select Dname="ATSAMD51J18A" Dvendor="Atmel:3"/>
+      <command>http://start.atmel.com/</command>
+      <files>
+        <file category="generator" name="atmel_start_config.atstart"/>
+        <file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
+      </files>
+    </generator>
+  </generators>
+  <conditions>
+    <condition id="CMSIS Device Startup">
+      <description>Dependency on CMSIS core and Device Startup components</description>
+      <require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
+      <require Cclass="Device" Cgroup="Startup" Cversion="1.2.0"/>
+    </condition>
+    <condition id="ARMCC, GCC, IAR">
+      <require Dname="ATSAMD51J18A"/>
+      <accept Tcompiler="ARMCC"/>
+      <accept Tcompiler="GCC"/>
+      <accept Tcompiler="IAR"/>
+    </condition>
+    <condition id="GCC">
+      <require Dname="ATSAMD51J18A"/>
+      <accept Tcompiler="GCC"/>
+    </condition>
+  </conditions>
+  <components generator="AtmelStart">
+    <component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
+      <description>Atmel Start Framework</description>
+      <RTE_Components_h>#define ATMEL_START</RTE_Components_h>
+      <files>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/custom_logic.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/evsys.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/ext_irq.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_async.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/pwm.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/quad_spi_dma.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_dma.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_sync.rst"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_custom_logic.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_evsys.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_ext_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_i2c_m_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_qspi_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_cmcc.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_custom_logic.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_evsys.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ext_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_cache.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_evsys.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_async.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_qspi_dma.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
+        <file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hpl/doc_lite/tc.rst"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_cmcc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dac_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hmatrixb_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_i2s_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_icm_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pcc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pdec_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_qspi_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ramecc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sdhc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_d51.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_pwm.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_pwm.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_timer.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_ext_irq.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_pwm.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_dma.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_sync.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/ccl/hpl_ccl.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/cmcc/hpl_cmcc.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m4.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/eic/hpl_eic.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/evsys/hpl_evsys.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/qspi/hpl_qspi.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_adc_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_ccl_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_eic_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_evsys_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_qspi_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tcc_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="config"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/adc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/ccl"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/cmcc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/eic"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/evsys"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/qspi"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/ramecc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/tc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/tcc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+      </files>
+    </component>
+  </components>
+</package>
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/atmel_start_config.atstart b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/atmel_start_config.atstart
new file mode 100644
index 0000000..89c10b1
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/atmel_start_config.atstart
@@ -0,0 +1,2712 @@
+format_version: '2'
+name: Two_Motor_D51
+versions:
+  api: '1.0'
+  backend: 1.8.580
+  commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c
+  content: unknown
+  content_pack_name: unknown
+  format: '2'
+  frontend: 1.8.580
+  packs_version_avr8: 1.0.1463
+  packs_version_qtouch: unknown
+  packs_version_sam: 1.0.1726
+  version_backend: 1.8.580
+  version_frontend: ''
+board:
+  identifier: CustomBoard
+  device: SAMD51J18A-MF
+details: null
+application: null
+middlewares: {}
+drivers:
+  ADC_0:
+    user_label: ADC_0
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync
+    functionality: ADC
+    api: HAL:Driver:ADC_Sync
+    configuration:
+      adc_advanced_settings: false
+      adc_arch_adjres: 0
+      adc_arch_corren: false
+      adc_arch_dbgrun: false
+      adc_arch_event_settings: false
+      adc_arch_flushei: false
+      adc_arch_flushinv: false
+      adc_arch_gaincorr: 0
+      adc_arch_leftadj: false
+      adc_arch_offcomp: false
+      adc_arch_offsetcorr: 0
+      adc_arch_ondemand: false
+      adc_arch_refcomp: false
+      adc_arch_resrdyeo: false
+      adc_arch_runstdby: false
+      adc_arch_samplen: 0
+      adc_arch_samplenum: 1 sample
+      adc_arch_seqen: 0
+      adc_arch_startei: false
+      adc_arch_startinv: false
+      adc_arch_winlt: 0
+      adc_arch_winmode: No window mode
+      adc_arch_winmoneo: false
+      adc_arch_winut: 0
+      adc_differential_mode: false
+      adc_freerunning_mode: false
+      adc_pinmux_negative: ADC AIN0 pin
+      adc_pinmux_positive: ADC AIN0 pin
+      adc_prescaler: Peripheral clock divided by 2
+      adc_reference: Internal bandgap reference
+      adc_resolution: 12-bit
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: ADC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          adc_gclk_selection: Generic clock generator 0
+  ADC_1:
+    user_label: ADC_1
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::ADC1::driver_config_definition::ADC::HAL:Driver:ADC.Sync
+    functionality: ADC
+    api: HAL:Driver:ADC_Sync
+    configuration:
+      adc_advanced_settings: true
+      adc_arch_adjres: 0
+      adc_arch_corren: false
+      adc_arch_dbgrun: false
+      adc_arch_event_settings: true
+      adc_arch_flushei: false
+      adc_arch_flushinv: false
+      adc_arch_gaincorr: 0
+      adc_arch_leftadj: false
+      adc_arch_offcomp: false
+      adc_arch_offsetcorr: 0
+      adc_arch_ondemand: false
+      adc_arch_refcomp: false
+      adc_arch_resrdyeo: true
+      adc_arch_runstdby: false
+      adc_arch_samplen: 2
+      adc_arch_samplenum: 1 sample
+      adc_arch_seqen: 0
+      adc_arch_startei: false
+      adc_arch_startinv: false
+      adc_arch_winlt: 0
+      adc_arch_winmode: No window mode
+      adc_arch_winmoneo: false
+      adc_arch_winut: 0
+      adc_differential_mode: true
+      adc_freerunning_mode: false
+      adc_pinmux_negative: ADC AIN0 pin
+      adc_pinmux_positive: ADC AIN6 pin
+      adc_prescaler: Peripheral clock divided by 8
+      adc_reference: External reference A
+      adc_resolution: 12-bit
+    optional_signals:
+    - identifier: ADC_1:AIN/0
+      pad: PB08
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.0
+      name: ADC1/AIN/0
+      label: AIN/0
+    - identifier: ADC_1:AIN/6
+      pad: PB04
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.6
+      name: ADC1/AIN/6
+      label: AIN/6
+    - identifier: ADC_1:AIN/7
+      pad: PB05
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.7
+      name: ADC1/AIN/7
+      label: AIN/7
+    - identifier: ADC_1:AIN/8
+      pad: PB06
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.8
+      name: ADC1/AIN/8
+      label: AIN/8
+    - identifier: ADC_1:AIN/9
+      pad: PB07
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::ADC1.AIN.9
+      name: ADC1/AIN/9
+      label: AIN/9
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: ADC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          adc_gclk_selection: Generic clock generator 0
+  DIGITAL_GLUE_LOGIC_0:
+    user_label: DIGITAL_GLUE_LOGIC_0
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::CCL::driver_config_definition::CCL::HAL:Driver:CCL
+    functionality: Digital_Glue_Logic
+    api: HAL:Driver:CCL
+    configuration:
+      ccl_arch_advanced_settings: false
+      ccl_arch_edgesel_0: false
+      ccl_arch_edgesel_1: false
+      ccl_arch_edgesel_2: false
+      ccl_arch_edgesel_3: false
+      ccl_arch_filtsel_0: Disabled
+      ccl_arch_filtsel_1: Disabled
+      ccl_arch_filtsel_2: Disabled
+      ccl_arch_filtsel_3: Disabled
+      ccl_arch_insel0_0: IO pin input source
+      ccl_arch_insel0_1: IO pin input source
+      ccl_arch_insel0_2: IO pin input source
+      ccl_arch_insel0_3: IO pin input source
+      ccl_arch_insel1_0: IO pin input source
+      ccl_arch_insel1_1: IO pin input source
+      ccl_arch_insel1_2: IO pin input source
+      ccl_arch_insel1_3: IO pin input source
+      ccl_arch_insel2_0: IO pin input source
+      ccl_arch_insel2_1: IO pin input source
+      ccl_arch_insel2_2: IO pin input source
+      ccl_arch_insel2_3: IO pin input source
+      ccl_arch_invei_0: false
+      ccl_arch_invei_1: false
+      ccl_arch_invei_2: false
+      ccl_arch_invei_3: false
+      ccl_arch_lutctrl0: true
+      ccl_arch_lutctrl1: false
+      ccl_arch_lutctrl2: true
+      ccl_arch_lutctrl3: false
+      ccl_arch_lutei_0: false
+      ccl_arch_lutei_1: false
+      ccl_arch_lutei_2: false
+      ccl_arch_lutei_3: false
+      ccl_arch_luteo_0: true
+      ccl_arch_luteo_1: false
+      ccl_arch_luteo_2: true
+      ccl_arch_luteo_3: false
+      ccl_arch_runstdby: false
+      ccl_arch_seqsel_0: Sequential logic is disabled
+      ccl_arch_seqsel_1: Sequential logic is disabled
+      ccl_arch_truth_0: 150
+      ccl_arch_truth_1: 0
+      ccl_arch_truth_2: 150
+      ccl_arch_truth_3: 0
+      ccl_e_persistance_0: ''
+      ccl_e_persistance_1: ''
+      ccl_e_persistance_2: ''
+      ccl_e_persistance_3: ''
+      ccl_l_persistance_0: ''
+      ccl_l_persistance_1: ''
+      ccl_l_persistance_2: ''
+      ccl_l_persistance_3: ''
+    optional_signals:
+    - identifier: DIGITAL_GLUE_LOGIC_0:IN/0
+      pad: PA04
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.0
+      name: CCL/IN/0
+      label: IN/0
+    - identifier: DIGITAL_GLUE_LOGIC_0:IN/1
+      pad: PA05
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.1
+      name: CCL/IN/1
+      label: IN/1
+    - identifier: DIGITAL_GLUE_LOGIC_0:IN/2
+      pad: PA06
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.2
+      name: CCL/IN/2
+      label: IN/2
+    - identifier: DIGITAL_GLUE_LOGIC_0:IN/6
+      pad: PA22
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.6
+      name: CCL/IN/6
+      label: IN/6
+    - identifier: DIGITAL_GLUE_LOGIC_0:IN/7
+      pad: PA23
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.7
+      name: CCL/IN/7
+      label: IN/7
+    - identifier: DIGITAL_GLUE_LOGIC_0:IN/8
+      pad: PA24
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::CCL.IN.8
+      name: CCL/IN/8
+      label: IN/8
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: CCL
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          ccl_gclk_selection: Generic clock generator 0
+  CMCC:
+    user_label: CMCC
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC
+    functionality: System
+    api: HAL:HPL:CMCC
+    configuration:
+      cache_size: 4 KB
+      cmcc_advanced_configuration: false
+      cmcc_clock_gating_disable: false
+      cmcc_data_cache_disable: false
+      cmcc_enable: false
+      cmcc_inst_cache_disable: false
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  DMAC:
+    user_label: DMAC
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
+    functionality: System
+    api: HAL:HPL:DMAC
+    configuration:
+      dmac_beatsize_0: 32-bit bus transfer
+      dmac_beatsize_1: 32-bit bus transfer
+      dmac_beatsize_10: 8-bit bus transfer
+      dmac_beatsize_11: 8-bit bus transfer
+      dmac_beatsize_12: 8-bit bus transfer
+      dmac_beatsize_13: 8-bit bus transfer
+      dmac_beatsize_14: 8-bit bus transfer
+      dmac_beatsize_15: 8-bit bus transfer
+      dmac_beatsize_16: 8-bit bus transfer
+      dmac_beatsize_17: 8-bit bus transfer
+      dmac_beatsize_18: 8-bit bus transfer
+      dmac_beatsize_19: 8-bit bus transfer
+      dmac_beatsize_2: 32-bit bus transfer
+      dmac_beatsize_20: 8-bit bus transfer
+      dmac_beatsize_21: 8-bit bus transfer
+      dmac_beatsize_22: 8-bit bus transfer
+      dmac_beatsize_23: 8-bit bus transfer
+      dmac_beatsize_24: 8-bit bus transfer
+      dmac_beatsize_25: 8-bit bus transfer
+      dmac_beatsize_26: 8-bit bus transfer
+      dmac_beatsize_27: 8-bit bus transfer
+      dmac_beatsize_28: 8-bit bus transfer
+      dmac_beatsize_29: 8-bit bus transfer
+      dmac_beatsize_3: 16-bit bus transfer
+      dmac_beatsize_30: 8-bit bus transfer
+      dmac_beatsize_31: 8-bit bus transfer
+      dmac_beatsize_4: 32-bit bus transfer
+      dmac_beatsize_5: 32-bit bus transfer
+      dmac_beatsize_6: 32-bit bus transfer
+      dmac_beatsize_7: 32-bit bus transfer
+      dmac_beatsize_8: 8-bit bus transfer
+      dmac_beatsize_9: 8-bit bus transfer
+      dmac_blockact_0: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_1: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_10: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_11: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_12: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_13: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_14: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_15: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_16: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_17: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_18: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_19: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_2: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_20: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_21: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_22: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_23: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_24: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_25: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_26: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_27: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_28: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_29: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_3: Channel will be disabled if it is the last block transfer in
+        the transaction and block interrupt
+      dmac_blockact_30: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_31: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_4: Channel suspend operation is complete
+      dmac_blockact_5: Channel suspend operation is complete
+      dmac_blockact_6: Channel suspend operation is complete
+      dmac_blockact_7: Channel suspend operation is complete
+      dmac_blockact_8: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_9: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_channel_0_settings: true
+      dmac_channel_10_settings: false
+      dmac_channel_11_settings: false
+      dmac_channel_12_settings: false
+      dmac_channel_13_settings: false
+      dmac_channel_14_settings: false
+      dmac_channel_15_settings: false
+      dmac_channel_16_settings: false
+      dmac_channel_17_settings: false
+      dmac_channel_18_settings: false
+      dmac_channel_19_settings: false
+      dmac_channel_1_settings: true
+      dmac_channel_20_settings: false
+      dmac_channel_21_settings: false
+      dmac_channel_22_settings: false
+      dmac_channel_23_settings: false
+      dmac_channel_24_settings: false
+      dmac_channel_25_settings: false
+      dmac_channel_26_settings: false
+      dmac_channel_27_settings: false
+      dmac_channel_28_settings: false
+      dmac_channel_29_settings: false
+      dmac_channel_2_settings: true
+      dmac_channel_30_settings: false
+      dmac_channel_31_settings: false
+      dmac_channel_3_settings: true
+      dmac_channel_4_settings: true
+      dmac_channel_5_settings: true
+      dmac_channel_6_settings: true
+      dmac_channel_7_settings: true
+      dmac_channel_8_settings: false
+      dmac_channel_9_settings: false
+      dmac_dbgrun: false
+      dmac_dstinc_0: true
+      dmac_dstinc_1: true
+      dmac_dstinc_10: false
+      dmac_dstinc_11: false
+      dmac_dstinc_12: false
+      dmac_dstinc_13: false
+      dmac_dstinc_14: false
+      dmac_dstinc_15: false
+      dmac_dstinc_16: false
+      dmac_dstinc_17: false
+      dmac_dstinc_18: false
+      dmac_dstinc_19: false
+      dmac_dstinc_2: true
+      dmac_dstinc_20: false
+      dmac_dstinc_21: false
+      dmac_dstinc_22: false
+      dmac_dstinc_23: false
+      dmac_dstinc_24: false
+      dmac_dstinc_25: false
+      dmac_dstinc_26: false
+      dmac_dstinc_27: false
+      dmac_dstinc_28: false
+      dmac_dstinc_29: false
+      dmac_dstinc_3: true
+      dmac_dstinc_30: false
+      dmac_dstinc_31: false
+      dmac_dstinc_4: false
+      dmac_dstinc_5: false
+      dmac_dstinc_6: false
+      dmac_dstinc_7: false
+      dmac_dstinc_8: false
+      dmac_dstinc_9: false
+      dmac_enable: true
+      dmac_evact_0: No action
+      dmac_evact_1: No action
+      dmac_evact_10: No action
+      dmac_evact_11: No action
+      dmac_evact_12: No action
+      dmac_evact_13: No action
+      dmac_evact_14: No action
+      dmac_evact_15: No action
+      dmac_evact_16: No action
+      dmac_evact_17: No action
+      dmac_evact_18: No action
+      dmac_evact_19: No action
+      dmac_evact_2: No action
+      dmac_evact_20: No action
+      dmac_evact_21: No action
+      dmac_evact_22: No action
+      dmac_evact_23: No action
+      dmac_evact_24: No action
+      dmac_evact_25: No action
+      dmac_evact_26: No action
+      dmac_evact_27: No action
+      dmac_evact_28: No action
+      dmac_evact_29: No action
+      dmac_evact_3: No action
+      dmac_evact_30: No action
+      dmac_evact_31: No action
+      dmac_evact_4: Channel resume operation
+      dmac_evact_5: Channel resume operation
+      dmac_evact_6: Channel resume operation
+      dmac_evact_7: No action
+      dmac_evact_8: No action
+      dmac_evact_9: No action
+      dmac_evie_0: false
+      dmac_evie_1: false
+      dmac_evie_10: false
+      dmac_evie_11: false
+      dmac_evie_12: false
+      dmac_evie_13: false
+      dmac_evie_14: false
+      dmac_evie_15: false
+      dmac_evie_16: false
+      dmac_evie_17: false
+      dmac_evie_18: false
+      dmac_evie_19: false
+      dmac_evie_2: false
+      dmac_evie_20: false
+      dmac_evie_21: false
+      dmac_evie_22: false
+      dmac_evie_23: false
+      dmac_evie_24: false
+      dmac_evie_25: false
+      dmac_evie_26: false
+      dmac_evie_27: false
+      dmac_evie_28: false
+      dmac_evie_29: false
+      dmac_evie_3: false
+      dmac_evie_30: false
+      dmac_evie_31: false
+      dmac_evie_4: true
+      dmac_evie_5: true
+      dmac_evie_6: true
+      dmac_evie_7: true
+      dmac_evie_8: false
+      dmac_evie_9: false
+      dmac_evoe_0: true
+      dmac_evoe_1: true
+      dmac_evoe_10: false
+      dmac_evoe_11: false
+      dmac_evoe_12: false
+      dmac_evoe_13: false
+      dmac_evoe_14: false
+      dmac_evoe_15: false
+      dmac_evoe_16: false
+      dmac_evoe_17: false
+      dmac_evoe_18: false
+      dmac_evoe_19: false
+      dmac_evoe_2: true
+      dmac_evoe_20: false
+      dmac_evoe_21: false
+      dmac_evoe_22: false
+      dmac_evoe_23: false
+      dmac_evoe_24: false
+      dmac_evoe_25: false
+      dmac_evoe_26: false
+      dmac_evoe_27: false
+      dmac_evoe_28: false
+      dmac_evoe_29: false
+      dmac_evoe_3: false
+      dmac_evoe_30: false
+      dmac_evoe_31: false
+      dmac_evoe_4: false
+      dmac_evoe_5: false
+      dmac_evoe_6: false
+      dmac_evoe_7: false
+      dmac_evoe_8: false
+      dmac_evoe_9: false
+      dmac_evosel_0: Event strobe when block transfer complete
+      dmac_evosel_1: Event strobe when block transfer complete
+      dmac_evosel_10: Event generation disabled
+      dmac_evosel_11: Event generation disabled
+      dmac_evosel_12: Event generation disabled
+      dmac_evosel_13: Event generation disabled
+      dmac_evosel_14: Event generation disabled
+      dmac_evosel_15: Event generation disabled
+      dmac_evosel_16: Event generation disabled
+      dmac_evosel_17: Event generation disabled
+      dmac_evosel_18: Event generation disabled
+      dmac_evosel_19: Event generation disabled
+      dmac_evosel_2: Event strobe when block transfer complete
+      dmac_evosel_20: Event generation disabled
+      dmac_evosel_21: Event generation disabled
+      dmac_evosel_22: Event generation disabled
+      dmac_evosel_23: Event generation disabled
+      dmac_evosel_24: Event generation disabled
+      dmac_evosel_25: Event generation disabled
+      dmac_evosel_26: Event generation disabled
+      dmac_evosel_27: Event generation disabled
+      dmac_evosel_28: Event generation disabled
+      dmac_evosel_29: Event generation disabled
+      dmac_evosel_3: Event generation disabled
+      dmac_evosel_30: Event generation disabled
+      dmac_evosel_31: Event generation disabled
+      dmac_evosel_4: Event generation disabled
+      dmac_evosel_5: Event generation disabled
+      dmac_evosel_6: Event generation disabled
+      dmac_evosel_7: Event generation disabled
+      dmac_evosel_8: Event generation disabled
+      dmac_evosel_9: Event generation disabled
+      dmac_lvl_0: Channel priority 0
+      dmac_lvl_1: Channel priority 0
+      dmac_lvl_10: Channel priority 0
+      dmac_lvl_11: Channel priority 0
+      dmac_lvl_12: Channel priority 0
+      dmac_lvl_13: Channel priority 0
+      dmac_lvl_14: Channel priority 0
+      dmac_lvl_15: Channel priority 0
+      dmac_lvl_16: Channel priority 0
+      dmac_lvl_17: Channel priority 0
+      dmac_lvl_18: Channel priority 0
+      dmac_lvl_19: Channel priority 0
+      dmac_lvl_2: Channel priority 0
+      dmac_lvl_20: Channel priority 0
+      dmac_lvl_21: Channel priority 0
+      dmac_lvl_22: Channel priority 0
+      dmac_lvl_23: Channel priority 0
+      dmac_lvl_24: Channel priority 0
+      dmac_lvl_25: Channel priority 0
+      dmac_lvl_26: Channel priority 0
+      dmac_lvl_27: Channel priority 0
+      dmac_lvl_28: Channel priority 0
+      dmac_lvl_29: Channel priority 0
+      dmac_lvl_3: Channel priority 0
+      dmac_lvl_30: Channel priority 0
+      dmac_lvl_31: Channel priority 0
+      dmac_lvl_4: Channel priority 0
+      dmac_lvl_5: Channel priority 0
+      dmac_lvl_6: Channel priority 0
+      dmac_lvl_7: Channel priority 0
+      dmac_lvl_8: Channel priority 0
+      dmac_lvl_9: Channel priority 0
+      dmac_lvlen0: true
+      dmac_lvlen1: false
+      dmac_lvlen2: false
+      dmac_lvlen3: false
+      dmac_lvlpri0: 0
+      dmac_lvlpri1: 0
+      dmac_lvlpri2: 0
+      dmac_lvlpri3: 0
+      dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
+      dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
+      dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
+      dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
+      dmac_runstdby_0: true
+      dmac_runstdby_1: true
+      dmac_runstdby_10: false
+      dmac_runstdby_11: false
+      dmac_runstdby_12: false
+      dmac_runstdby_13: false
+      dmac_runstdby_14: false
+      dmac_runstdby_15: false
+      dmac_runstdby_16: false
+      dmac_runstdby_17: false
+      dmac_runstdby_18: false
+      dmac_runstdby_19: false
+      dmac_runstdby_2: true
+      dmac_runstdby_20: false
+      dmac_runstdby_21: false
+      dmac_runstdby_22: false
+      dmac_runstdby_23: false
+      dmac_runstdby_24: false
+      dmac_runstdby_25: false
+      dmac_runstdby_26: false
+      dmac_runstdby_27: false
+      dmac_runstdby_28: false
+      dmac_runstdby_29: false
+      dmac_runstdby_3: true
+      dmac_runstdby_30: false
+      dmac_runstdby_31: false
+      dmac_runstdby_4: true
+      dmac_runstdby_5: true
+      dmac_runstdby_6: true
+      dmac_runstdby_7: true
+      dmac_runstdby_8: false
+      dmac_runstdby_9: false
+      dmac_srcinc_0: false
+      dmac_srcinc_1: false
+      dmac_srcinc_10: false
+      dmac_srcinc_11: false
+      dmac_srcinc_12: false
+      dmac_srcinc_13: false
+      dmac_srcinc_14: false
+      dmac_srcinc_15: false
+      dmac_srcinc_16: false
+      dmac_srcinc_17: false
+      dmac_srcinc_18: false
+      dmac_srcinc_19: false
+      dmac_srcinc_2: false
+      dmac_srcinc_20: false
+      dmac_srcinc_21: false
+      dmac_srcinc_22: false
+      dmac_srcinc_23: false
+      dmac_srcinc_24: false
+      dmac_srcinc_25: false
+      dmac_srcinc_26: false
+      dmac_srcinc_27: false
+      dmac_srcinc_28: false
+      dmac_srcinc_29: false
+      dmac_srcinc_3: false
+      dmac_srcinc_30: false
+      dmac_srcinc_31: false
+      dmac_srcinc_4: true
+      dmac_srcinc_5: true
+      dmac_srcinc_6: true
+      dmac_srcinc_7: true
+      dmac_srcinc_8: false
+      dmac_srcinc_9: false
+      dmac_stepsel_0: Step size settings apply to the destination address
+      dmac_stepsel_1: Step size settings apply to the destination address
+      dmac_stepsel_10: Step size settings apply to the destination address
+      dmac_stepsel_11: Step size settings apply to the destination address
+      dmac_stepsel_12: Step size settings apply to the destination address
+      dmac_stepsel_13: Step size settings apply to the destination address
+      dmac_stepsel_14: Step size settings apply to the destination address
+      dmac_stepsel_15: Step size settings apply to the destination address
+      dmac_stepsel_16: Step size settings apply to the destination address
+      dmac_stepsel_17: Step size settings apply to the destination address
+      dmac_stepsel_18: Step size settings apply to the destination address
+      dmac_stepsel_19: Step size settings apply to the destination address
+      dmac_stepsel_2: Step size settings apply to the destination address
+      dmac_stepsel_20: Step size settings apply to the destination address
+      dmac_stepsel_21: Step size settings apply to the destination address
+      dmac_stepsel_22: Step size settings apply to the destination address
+      dmac_stepsel_23: Step size settings apply to the destination address
+      dmac_stepsel_24: Step size settings apply to the destination address
+      dmac_stepsel_25: Step size settings apply to the destination address
+      dmac_stepsel_26: Step size settings apply to the destination address
+      dmac_stepsel_27: Step size settings apply to the destination address
+      dmac_stepsel_28: Step size settings apply to the destination address
+      dmac_stepsel_29: Step size settings apply to the destination address
+      dmac_stepsel_3: Step size settings apply to the destination address
+      dmac_stepsel_30: Step size settings apply to the destination address
+      dmac_stepsel_31: Step size settings apply to the destination address
+      dmac_stepsel_4: Step size settings apply to the source address
+      dmac_stepsel_5: Step size settings apply to the source address
+      dmac_stepsel_6: Step size settings apply to the source address
+      dmac_stepsel_7: Step size settings apply to the source address
+      dmac_stepsel_8: Step size settings apply to the destination address
+      dmac_stepsel_9: Step size settings apply to the destination address
+      dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_trifsrc_0: SERCOM1 RX Trigger
+      dmac_trifsrc_1: SERCOM5 RX Trigger
+      dmac_trifsrc_10: Only software/event triggers
+      dmac_trifsrc_11: Only software/event triggers
+      dmac_trifsrc_12: Only software/event triggers
+      dmac_trifsrc_13: Only software/event triggers
+      dmac_trifsrc_14: Only software/event triggers
+      dmac_trifsrc_15: Only software/event triggers
+      dmac_trifsrc_16: Only software/event triggers
+      dmac_trifsrc_17: Only software/event triggers
+      dmac_trifsrc_18: Only software/event triggers
+      dmac_trifsrc_19: Only software/event triggers
+      dmac_trifsrc_2: SERCOM2 RX Trigger
+      dmac_trifsrc_20: Only software/event triggers
+      dmac_trifsrc_21: Only software/event triggers
+      dmac_trifsrc_22: Only software/event triggers
+      dmac_trifsrc_23: Only software/event triggers
+      dmac_trifsrc_24: Only software/event triggers
+      dmac_trifsrc_25: Only software/event triggers
+      dmac_trifsrc_26: Only software/event triggers
+      dmac_trifsrc_27: Only software/event triggers
+      dmac_trifsrc_28: Only software/event triggers
+      dmac_trifsrc_29: Only software/event triggers
+      dmac_trifsrc_3: ADC1 Result Ready Trigger
+      dmac_trifsrc_30: Only software/event triggers
+      dmac_trifsrc_31: Only software/event triggers
+      dmac_trifsrc_4: ADC1 Sequencing Trigger
+      dmac_trifsrc_5: SERCOM2 TX Trigger
+      dmac_trifsrc_6: SERCOM5 TX Trigger
+      dmac_trifsrc_7: SERCOM1 TX Trigger
+      dmac_trifsrc_8: Only software/event triggers
+      dmac_trifsrc_9: Only software/event triggers
+      dmac_trigact_0: One trigger required for each beat transfer
+      dmac_trigact_1: One trigger required for each beat transfer
+      dmac_trigact_10: One trigger required for each block transfer
+      dmac_trigact_11: One trigger required for each block transfer
+      dmac_trigact_12: One trigger required for each block transfer
+      dmac_trigact_13: One trigger required for each block transfer
+      dmac_trigact_14: One trigger required for each block transfer
+      dmac_trigact_15: One trigger required for each block transfer
+      dmac_trigact_16: One trigger required for each block transfer
+      dmac_trigact_17: One trigger required for each block transfer
+      dmac_trigact_18: One trigger required for each block transfer
+      dmac_trigact_19: One trigger required for each block transfer
+      dmac_trigact_2: One trigger required for each beat transfer
+      dmac_trigact_20: One trigger required for each block transfer
+      dmac_trigact_21: One trigger required for each block transfer
+      dmac_trigact_22: One trigger required for each block transfer
+      dmac_trigact_23: One trigger required for each block transfer
+      dmac_trigact_24: One trigger required for each block transfer
+      dmac_trigact_25: One trigger required for each block transfer
+      dmac_trigact_26: One trigger required for each block transfer
+      dmac_trigact_27: One trigger required for each block transfer
+      dmac_trigact_28: One trigger required for each block transfer
+      dmac_trigact_29: One trigger required for each block transfer
+      dmac_trigact_3: One trigger required for each beat transfer
+      dmac_trigact_30: One trigger required for each block transfer
+      dmac_trigact_31: One trigger required for each block transfer
+      dmac_trigact_4: One trigger required for each beat transfer
+      dmac_trigact_5: One trigger required for each beat transfer
+      dmac_trigact_6: One trigger required for each beat transfer
+      dmac_trigact_7: One trigger required for each beat transfer
+      dmac_trigact_8: One trigger required for each block transfer
+      dmac_trigact_9: One trigger required for each block transfer
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  EXTERNAL_IRQ_0:
+    user_label: EXTERNAL_IRQ_0
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ
+    functionality: External_IRQ
+    api: HAL:Driver:Ext_IRQ
+    configuration:
+      eic_arch_asynch0: false
+      eic_arch_asynch1: false
+      eic_arch_asynch10: false
+      eic_arch_asynch11: false
+      eic_arch_asynch12: false
+      eic_arch_asynch13: false
+      eic_arch_asynch14: false
+      eic_arch_asynch15: false
+      eic_arch_asynch2: true
+      eic_arch_asynch3: false
+      eic_arch_asynch4: false
+      eic_arch_asynch5: false
+      eic_arch_asynch6: false
+      eic_arch_asynch7: false
+      eic_arch_asynch8: false
+      eic_arch_asynch9: false
+      eic_arch_cksel: Clocked by GCLK
+      eic_arch_debounce_enable0: false
+      eic_arch_debounce_enable1: false
+      eic_arch_debounce_enable10: false
+      eic_arch_debounce_enable11: false
+      eic_arch_debounce_enable12: false
+      eic_arch_debounce_enable13: false
+      eic_arch_debounce_enable14: false
+      eic_arch_debounce_enable15: false
+      eic_arch_debounce_enable2: false
+      eic_arch_debounce_enable3: false
+      eic_arch_debounce_enable4: false
+      eic_arch_debounce_enable5: false
+      eic_arch_debounce_enable6: false
+      eic_arch_debounce_enable7: false
+      eic_arch_debounce_enable8: false
+      eic_arch_debounce_enable9: false
+      eic_arch_enable_irq_setting0: false
+      eic_arch_enable_irq_setting1: false
+      eic_arch_enable_irq_setting10: false
+      eic_arch_enable_irq_setting11: false
+      eic_arch_enable_irq_setting12: false
+      eic_arch_enable_irq_setting13: false
+      eic_arch_enable_irq_setting14: true
+      eic_arch_enable_irq_setting15: true
+      eic_arch_enable_irq_setting2: true
+      eic_arch_enable_irq_setting3: false
+      eic_arch_enable_irq_setting4: false
+      eic_arch_enable_irq_setting5: false
+      eic_arch_enable_irq_setting6: false
+      eic_arch_enable_irq_setting7: false
+      eic_arch_enable_irq_setting8: false
+      eic_arch_enable_irq_setting9: false
+      eic_arch_extinteo0: false
+      eic_arch_extinteo1: false
+      eic_arch_extinteo10: false
+      eic_arch_extinteo11: false
+      eic_arch_extinteo12: false
+      eic_arch_extinteo13: false
+      eic_arch_extinteo14: false
+      eic_arch_extinteo15: false
+      eic_arch_extinteo2: true
+      eic_arch_extinteo3: false
+      eic_arch_extinteo4: false
+      eic_arch_extinteo5: false
+      eic_arch_extinteo6: false
+      eic_arch_extinteo7: false
+      eic_arch_extinteo8: false
+      eic_arch_extinteo9: false
+      eic_arch_filten0: false
+      eic_arch_filten1: false
+      eic_arch_filten10: false
+      eic_arch_filten11: false
+      eic_arch_filten12: false
+      eic_arch_filten13: false
+      eic_arch_filten14: true
+      eic_arch_filten15: true
+      eic_arch_filten2: false
+      eic_arch_filten3: false
+      eic_arch_filten4: false
+      eic_arch_filten5: false
+      eic_arch_filten6: false
+      eic_arch_filten7: false
+      eic_arch_filten8: false
+      eic_arch_filten9: false
+      eic_arch_nmi_ctrl: false
+      eic_arch_nmiasynch: false
+      eic_arch_nmifilten: false
+      eic_arch_nmisense: No detection
+      eic_arch_prescaler0: Divided by 2
+      eic_arch_prescaler1: Divided by 2
+      eic_arch_sense0: No detection
+      eic_arch_sense1: No detection
+      eic_arch_sense10: No detection
+      eic_arch_sense11: No detection
+      eic_arch_sense12: No detection
+      eic_arch_sense13: No detection
+      eic_arch_sense14: Falling-edge detection
+      eic_arch_sense15: Falling-edge detection
+      eic_arch_sense2: Falling-edge detection
+      eic_arch_sense3: No detection
+      eic_arch_sense4: No detection
+      eic_arch_sense5: No detection
+      eic_arch_sense6: No detection
+      eic_arch_sense7: No detection
+      eic_arch_sense8: No detection
+      eic_arch_sense9: No detection
+      eic_arch_states0: '3'
+      eic_arch_states1: '3'
+      eic_arch_tickon: The sampling rate is EIC clock
+    optional_signals:
+    - identifier: EXTERNAL_IRQ_0:EXTINT/2
+      pad: PA02
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::EIC.EXTINT.2
+      name: EIC/EXTINT/2
+      label: EXTINT/2
+    - identifier: EXTERNAL_IRQ_0:EXTINT/7
+      pad: PA07
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::EIC.EXTINT.7
+      name: EIC/EXTINT/7
+      label: EXTINT/7
+    - identifier: EXTERNAL_IRQ_0:EXTINT/14
+      pad: PB30
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::EIC.EXTINT.14
+      name: EIC/EXTINT/14
+      label: EXTINT/14
+    - identifier: EXTERNAL_IRQ_0:EXTINT/15
+      pad: PB31
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::EIC.EXTINT.15
+      name: EIC/EXTINT/15
+      label: EXTINT/15
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: EIC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          eic_gclk_selection: Generic clock generator 0
+  EVENT_SYSTEM_0:
+    user_label: EVENT_SYSTEM_0
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::EVSYS::driver_config_definition::Event.System::HAL:Driver:Event.system
+    functionality: Event_System
+    api: HAL:Driver:Event_system
+    configuration:
+      evsys_channel_0: No channel output selected
+      evsys_channel_1: Channel 1
+      evsys_channel_10: Channel 5
+      evsys_channel_11: No channel output selected
+      evsys_channel_12: Channel 2
+      evsys_channel_17: No channel output selected
+      evsys_channel_18: No channel output selected
+      evsys_channel_19: No channel output selected
+      evsys_channel_2: Channel 6
+      evsys_channel_20: No channel output selected
+      evsys_channel_21: No channel output selected
+      evsys_channel_22: No channel output selected
+      evsys_channel_23: No channel output selected
+      evsys_channel_24: No channel output selected
+      evsys_channel_25: No channel output selected
+      evsys_channel_26: No channel output selected
+      evsys_channel_27: No channel output selected
+      evsys_channel_28: No channel output selected
+      evsys_channel_29: No channel output selected
+      evsys_channel_3: Channel 5
+      evsys_channel_30: No channel output selected
+      evsys_channel_31: No channel output selected
+      evsys_channel_32: No channel output selected
+      evsys_channel_33: No channel output selected
+      evsys_channel_34: No channel output selected
+      evsys_channel_35: No channel output selected
+      evsys_channel_36: No channel output selected
+      evsys_channel_37: No channel output selected
+      evsys_channel_38: No channel output selected
+      evsys_channel_39: No channel output selected
+      evsys_channel_4: Channel 8
+      evsys_channel_40: No channel output selected
+      evsys_channel_41: No channel output selected
+      evsys_channel_42: No channel output selected
+      evsys_channel_43: No channel output selected
+      evsys_channel_44: No channel output selected
+      evsys_channel_45: No channel output selected
+      evsys_channel_46: Channel 11
+      evsys_channel_47: No channel output selected
+      evsys_channel_48: Channel 12
+      evsys_channel_49: No channel output selected
+      evsys_channel_5: No channel output selected
+      evsys_channel_50: No channel output selected
+      evsys_channel_51: No channel output selected
+      evsys_channel_52: No channel output selected
+      evsys_channel_53: No channel output selected
+      evsys_channel_54: No channel output selected
+      evsys_channel_55: No channel output selected
+      evsys_channel_56: No channel output selected
+      evsys_channel_57: No channel output selected
+      evsys_channel_58: No channel output selected
+      evsys_channel_59: No channel output selected
+      evsys_channel_6: No channel output selected
+      evsys_channel_60: No channel output selected
+      evsys_channel_61: No channel output selected
+      evsys_channel_62: No channel output selected
+      evsys_channel_63: No channel output selected
+      evsys_channel_64: No channel output selected
+      evsys_channel_65: No channel output selected
+      evsys_channel_66: No channel output selected
+      evsys_channel_7: No channel output selected
+      evsys_channel_8: No channel output selected
+      evsys_channel_9: Channel 0
+      evsys_channel_setting_0: true
+      evsys_channel_setting_1: true
+      evsys_channel_setting_10: false
+      evsys_channel_setting_11: true
+      evsys_channel_setting_12: true
+      evsys_channel_setting_13: false
+      evsys_channel_setting_14: false
+      evsys_channel_setting_15: false
+      evsys_channel_setting_16: false
+      evsys_channel_setting_17: false
+      evsys_channel_setting_18: false
+      evsys_channel_setting_19: false
+      evsys_channel_setting_2: true
+      evsys_channel_setting_20: false
+      evsys_channel_setting_21: false
+      evsys_channel_setting_22: false
+      evsys_channel_setting_23: false
+      evsys_channel_setting_24: false
+      evsys_channel_setting_25: false
+      evsys_channel_setting_26: false
+      evsys_channel_setting_27: false
+      evsys_channel_setting_28: false
+      evsys_channel_setting_29: false
+      evsys_channel_setting_3: true
+      evsys_channel_setting_30: false
+      evsys_channel_setting_31: false
+      evsys_channel_setting_4: true
+      evsys_channel_setting_5: true
+      evsys_channel_setting_6: true
+      evsys_channel_setting_7: true
+      evsys_channel_setting_8: true
+      evsys_channel_setting_9: false
+      evsys_edgsel_0: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_1: Event is detected on the rising edge of the signal from event
+        generator
+      evsys_edgsel_10: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_11: Event is detected on the rising edge of the signal from event
+        generator
+      evsys_edgsel_12: Event is detected on the rising edge of the signal from event
+        generator
+      evsys_edgsel_13: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_14: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_15: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_16: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_17: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_18: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_19: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_2: Event is detected on the rising edge of the signal from event
+        generator
+      evsys_edgsel_20: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_21: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_22: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_23: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_24: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_25: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_26: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_27: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_28: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_29: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_3: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_30: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_31: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_4: No event output when using the resynchronized or synchronous
+        path
+      evsys_edgsel_5: Event is detected on the rising edge of the signal from event
+        generator
+      evsys_edgsel_6: Event is detected on the rising edge of the signal from event
+        generator
+      evsys_edgsel_7: Event is detected on the rising edge of the signal from event
+        generator
+      evsys_edgsel_8: Event is detected on the rising edge of the signal from event
+        generator
+      evsys_edgsel_9: No event output when using the resynchronized or synchronous
+        path
+      evsys_evd_0: false
+      evsys_evd_1: false
+      evsys_evd_10: false
+      evsys_evd_11: false
+      evsys_evd_12: false
+      evsys_evd_13: false
+      evsys_evd_14: false
+      evsys_evd_15: false
+      evsys_evd_16: false
+      evsys_evd_17: false
+      evsys_evd_18: false
+      evsys_evd_19: false
+      evsys_evd_2: false
+      evsys_evd_20: false
+      evsys_evd_21: false
+      evsys_evd_22: false
+      evsys_evd_23: false
+      evsys_evd_24: false
+      evsys_evd_25: false
+      evsys_evd_26: false
+      evsys_evd_27: false
+      evsys_evd_28: false
+      evsys_evd_29: false
+      evsys_evd_3: false
+      evsys_evd_30: false
+      evsys_evd_31: false
+      evsys_evd_4: false
+      evsys_evd_5: false
+      evsys_evd_6: true
+      evsys_evd_7: true
+      evsys_evd_8: false
+      evsys_evd_9: false
+      evsys_evgen_0: TCC0 overflow
+      evsys_evgen_1: TC0 match/capture 0
+      evsys_evgen_10: No event generator
+      evsys_evgen_11: CCL LUT output 0
+      evsys_evgen_12: CCL LUT output 2
+      evsys_evgen_13: No event generator
+      evsys_evgen_14: No event generator
+      evsys_evgen_15: No event generator
+      evsys_evgen_16: No event generator
+      evsys_evgen_17: No event generator
+      evsys_evgen_18: No event generator
+      evsys_evgen_19: No event generator
+      evsys_evgen_2: TC0 match/capture 1
+      evsys_evgen_20: No event generator
+      evsys_evgen_21: No event generator
+      evsys_evgen_22: No event generator
+      evsys_evgen_23: No event generator
+      evsys_evgen_24: No event generator
+      evsys_evgen_25: No event generator
+      evsys_evgen_26: No event generator
+      evsys_evgen_27: No event generator
+      evsys_evgen_28: No event generator
+      evsys_evgen_29: No event generator
+      evsys_evgen_3: TC1 match/capture 1
+      evsys_evgen_30: No event generator
+      evsys_evgen_31: No event generator
+      evsys_evgen_4: No event generator
+      evsys_evgen_5: EIC external interrupt 2
+      evsys_evgen_6: DMAC channel 0
+      evsys_evgen_7: DMAC channel 1
+      evsys_evgen_8: DMAC channel 2
+      evsys_evgen_9: No event generator
+      evsys_ondemand_0: false
+      evsys_ondemand_1: false
+      evsys_ondemand_10: false
+      evsys_ondemand_11: false
+      evsys_ondemand_12: false
+      evsys_ondemand_13: false
+      evsys_ondemand_14: false
+      evsys_ondemand_15: false
+      evsys_ondemand_16: false
+      evsys_ondemand_17: false
+      evsys_ondemand_18: false
+      evsys_ondemand_19: false
+      evsys_ondemand_2: false
+      evsys_ondemand_20: false
+      evsys_ondemand_21: false
+      evsys_ondemand_22: false
+      evsys_ondemand_23: false
+      evsys_ondemand_24: false
+      evsys_ondemand_25: false
+      evsys_ondemand_26: false
+      evsys_ondemand_27: false
+      evsys_ondemand_28: false
+      evsys_ondemand_29: false
+      evsys_ondemand_3: false
+      evsys_ondemand_30: false
+      evsys_ondemand_31: false
+      evsys_ondemand_4: false
+      evsys_ondemand_5: false
+      evsys_ondemand_6: false
+      evsys_ondemand_7: false
+      evsys_ondemand_8: false
+      evsys_ondemand_9: false
+      evsys_ovr_0: false
+      evsys_ovr_1: false
+      evsys_ovr_10: false
+      evsys_ovr_11: false
+      evsys_ovr_12: false
+      evsys_ovr_13: false
+      evsys_ovr_14: false
+      evsys_ovr_15: false
+      evsys_ovr_16: false
+      evsys_ovr_17: false
+      evsys_ovr_18: false
+      evsys_ovr_19: false
+      evsys_ovr_2: false
+      evsys_ovr_20: false
+      evsys_ovr_21: false
+      evsys_ovr_22: false
+      evsys_ovr_23: false
+      evsys_ovr_24: false
+      evsys_ovr_25: false
+      evsys_ovr_26: false
+      evsys_ovr_27: false
+      evsys_ovr_28: false
+      evsys_ovr_29: false
+      evsys_ovr_3: false
+      evsys_ovr_30: false
+      evsys_ovr_31: false
+      evsys_ovr_4: false
+      evsys_ovr_5: false
+      evsys_ovr_6: false
+      evsys_ovr_7: false
+      evsys_ovr_8: false
+      evsys_ovr_9: false
+      evsys_path_0: Asynchronous path
+      evsys_path_1: Asynchronous path
+      evsys_path_10: Synchronous path
+      evsys_path_11: Asynchronous path
+      evsys_path_12: Asynchronous path
+      evsys_path_13: Synchronous path
+      evsys_path_14: Synchronous path
+      evsys_path_15: Synchronous path
+      evsys_path_16: Synchronous path
+      evsys_path_17: Synchronous path
+      evsys_path_18: Synchronous path
+      evsys_path_19: Synchronous path
+      evsys_path_2: Synchronous path
+      evsys_path_20: Synchronous path
+      evsys_path_21: Synchronous path
+      evsys_path_22: Synchronous path
+      evsys_path_23: Synchronous path
+      evsys_path_24: Synchronous path
+      evsys_path_25: Synchronous path
+      evsys_path_26: Synchronous path
+      evsys_path_27: Synchronous path
+      evsys_path_28: Synchronous path
+      evsys_path_29: Synchronous path
+      evsys_path_3: Synchronous path
+      evsys_path_30: Synchronous path
+      evsys_path_31: Synchronous path
+      evsys_path_4: Synchronous path
+      evsys_path_5: Asynchronous path
+      evsys_path_6: Synchronous path
+      evsys_path_7: Synchronous path
+      evsys_path_8: Synchronous path
+      evsys_path_9: Synchronous path
+      evsys_runstdby_0: false
+      evsys_runstdby_1: false
+      evsys_runstdby_10: false
+      evsys_runstdby_11: false
+      evsys_runstdby_12: false
+      evsys_runstdby_13: false
+      evsys_runstdby_14: false
+      evsys_runstdby_15: false
+      evsys_runstdby_16: false
+      evsys_runstdby_17: false
+      evsys_runstdby_18: false
+      evsys_runstdby_19: false
+      evsys_runstdby_2: false
+      evsys_runstdby_20: false
+      evsys_runstdby_21: false
+      evsys_runstdby_22: false
+      evsys_runstdby_23: false
+      evsys_runstdby_24: false
+      evsys_runstdby_25: false
+      evsys_runstdby_26: false
+      evsys_runstdby_27: false
+      evsys_runstdby_28: false
+      evsys_runstdby_29: false
+      evsys_runstdby_3: false
+      evsys_runstdby_30: false
+      evsys_runstdby_31: false
+      evsys_runstdby_4: false
+      evsys_runstdby_5: false
+      evsys_runstdby_6: false
+      evsys_runstdby_7: false
+      evsys_runstdby_8: false
+      evsys_runstdby_9: false
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: Channel 0
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Channel 1
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Channel 2
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Channel 3
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Channel 4
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Channel 5
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Channel 6
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Channel 7
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Channel 8
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Channel 9
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Channel 10
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Channel 11
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          evsys_clk_selection_0: Generic clock generator 0
+          evsys_clk_selection_1: Generic clock generator 0
+          evsys_clk_selection_10: Generic clock generator 0
+          evsys_clk_selection_11: Generic clock generator 0
+          evsys_clk_selection_2: Generic clock generator 0
+          evsys_clk_selection_3: Generic clock generator 0
+          evsys_clk_selection_4: Generic clock generator 0
+          evsys_clk_selection_5: Generic clock generator 0
+          evsys_clk_selection_6: Generic clock generator 0
+          evsys_clk_selection_7: Generic clock generator 0
+          evsys_clk_selection_8: Generic clock generator 0
+          evsys_clk_selection_9: Generic clock generator 0
+  GCLK:
+    user_label: GCLK
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
+    functionality: System
+    api: HAL:HPL:GCLK
+    configuration:
+      $input: 12000000
+      $input_id: External Crystal Oscillator 8-48MHz (XOSC1)
+      RESERVED_InputFreq: 12000000
+      RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1)
+      _$freq_output_Generic clock generator 0: 100000000
+      _$freq_output_Generic clock generator 1: 2000000
+      _$freq_output_Generic clock generator 10: 12000000
+      _$freq_output_Generic clock generator 11: 12000000
+      _$freq_output_Generic clock generator 2: 32768
+      _$freq_output_Generic clock generator 3: 32768
+      _$freq_output_Generic clock generator 4: 12000000
+      _$freq_output_Generic clock generator 5: 12000000
+      _$freq_output_Generic clock generator 6: 12000000
+      _$freq_output_Generic clock generator 7: 12000000
+      _$freq_output_Generic clock generator 8: 12000000
+      _$freq_output_Generic clock generator 9: 12000000
+      enable_gclk_gen_0: true
+      enable_gclk_gen_0__externalclock: 1000000
+      enable_gclk_gen_1: true
+      enable_gclk_gen_10: false
+      enable_gclk_gen_10__externalclock: 1000000
+      enable_gclk_gen_11: false
+      enable_gclk_gen_11__externalclock: 1000000
+      enable_gclk_gen_1__externalclock: 1000000
+      enable_gclk_gen_2: true
+      enable_gclk_gen_2__externalclock: 1000000
+      enable_gclk_gen_3: false
+      enable_gclk_gen_3__externalclock: 1000000
+      enable_gclk_gen_4: false
+      enable_gclk_gen_4__externalclock: 1000000
+      enable_gclk_gen_5: false
+      enable_gclk_gen_5__externalclock: 1000000
+      enable_gclk_gen_6: false
+      enable_gclk_gen_6__externalclock: 1000000
+      enable_gclk_gen_7: false
+      enable_gclk_gen_7__externalclock: 1000000
+      enable_gclk_gen_8: false
+      enable_gclk_gen_8__externalclock: 1000000
+      enable_gclk_gen_9: false
+      enable_gclk_gen_9__externalclock: 1000000
+      gclk_arch_gen_0_enable: true
+      gclk_arch_gen_0_idc: false
+      gclk_arch_gen_0_oe: true
+      gclk_arch_gen_0_oov: false
+      gclk_arch_gen_0_runstdby: false
+      gclk_arch_gen_10_enable: false
+      gclk_arch_gen_10_idc: false
+      gclk_arch_gen_10_oe: false
+      gclk_arch_gen_10_oov: false
+      gclk_arch_gen_10_runstdby: false
+      gclk_arch_gen_11_enable: false
+      gclk_arch_gen_11_idc: false
+      gclk_arch_gen_11_oe: false
+      gclk_arch_gen_11_oov: false
+      gclk_arch_gen_11_runstdby: false
+      gclk_arch_gen_1_enable: true
+      gclk_arch_gen_1_idc: false
+      gclk_arch_gen_1_oe: true
+      gclk_arch_gen_1_oov: false
+      gclk_arch_gen_1_runstdby: false
+      gclk_arch_gen_2_enable: true
+      gclk_arch_gen_2_idc: false
+      gclk_arch_gen_2_oe: true
+      gclk_arch_gen_2_oov: false
+      gclk_arch_gen_2_runstdby: false
+      gclk_arch_gen_3_enable: false
+      gclk_arch_gen_3_idc: false
+      gclk_arch_gen_3_oe: false
+      gclk_arch_gen_3_oov: false
+      gclk_arch_gen_3_runstdby: false
+      gclk_arch_gen_4_enable: false
+      gclk_arch_gen_4_idc: false
+      gclk_arch_gen_4_oe: false
+      gclk_arch_gen_4_oov: false
+      gclk_arch_gen_4_runstdby: false
+      gclk_arch_gen_5_enable: false
+      gclk_arch_gen_5_idc: false
+      gclk_arch_gen_5_oe: false
+      gclk_arch_gen_5_oov: false
+      gclk_arch_gen_5_runstdby: false
+      gclk_arch_gen_6_enable: false
+      gclk_arch_gen_6_idc: false
+      gclk_arch_gen_6_oe: false
+      gclk_arch_gen_6_oov: false
+      gclk_arch_gen_6_runstdby: false
+      gclk_arch_gen_7_enable: false
+      gclk_arch_gen_7_idc: false
+      gclk_arch_gen_7_oe: false
+      gclk_arch_gen_7_oov: false
+      gclk_arch_gen_7_runstdby: false
+      gclk_arch_gen_8_enable: false
+      gclk_arch_gen_8_idc: false
+      gclk_arch_gen_8_oe: false
+      gclk_arch_gen_8_oov: false
+      gclk_arch_gen_8_runstdby: false
+      gclk_arch_gen_9_enable: false
+      gclk_arch_gen_9_idc: false
+      gclk_arch_gen_9_oe: false
+      gclk_arch_gen_9_oov: false
+      gclk_arch_gen_9_runstdby: false
+      gclk_gen_0_div: 1
+      gclk_gen_0_div_sel: false
+      gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL1)
+      gclk_gen_10_div: 1
+      gclk_gen_10_div_sel: false
+      gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+      gclk_gen_11_div: 1
+      gclk_gen_11_div_sel: false
+      gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+      gclk_gen_1_div: 24
+      gclk_gen_1_div_sel: false
+      gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M)
+      gclk_gen_2_div: 1
+      gclk_gen_2_div_sel: false
+      gclk_gen_2_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+      gclk_gen_3_div: 1
+      gclk_gen_3_div_sel: false
+      gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
+      gclk_gen_4_div: 1
+      gclk_gen_4_div_sel: false
+      gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+      gclk_gen_5_div: 1
+      gclk_gen_5_div_sel: false
+      gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+      gclk_gen_6_div: 1
+      gclk_gen_6_div_sel: false
+      gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+      gclk_gen_7_div: 1
+      gclk_gen_7_div_sel: false
+      gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+      gclk_gen_8_div: 1
+      gclk_gen_8_div_sel: false
+      gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+      gclk_gen_9_div: 1
+      gclk_gen_9_div_sel: false
+      gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  MCLK:
+    user_label: MCLK
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK
+    functionality: System
+    api: HAL:HPL:MCLK
+    configuration:
+      $input: 100000000
+      $input_id: Generic clock generator 0
+      RESERVED_InputFreq: 100000000
+      RESERVED_InputFreq_id: Generic clock generator 0
+      _$freq_output_CPU: 100000000
+      cpu_clock_source: Generic clock generator 0
+      cpu_div: '1'
+      enable_cpu_clock: true
+      mclk_arch_bupdiv: Divide by 8
+      mclk_arch_hsdiv: Divide by 1
+      mclk_arch_lpdiv: Divide by 4
+      nvm_wait_states: '0'
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: CPU
+          input: CPU
+          external: false
+          external_frequency: 0
+        configuration: {}
+  OSC32KCTRL:
+    user_label: OSC32KCTRL
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL
+    functionality: System
+    api: HAL:HPL:OSC32KCTRL
+    configuration:
+      $input: 32768
+      $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+      RESERVED_InputFreq: 32768
+      RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+      _$freq_output_RTC source: 32768
+      enable_osculp32k: true
+      enable_rtc_source: false
+      enable_xosc32k: false
+      osculp32k_calib: 0
+      osculp32k_calib_enable: false
+      rtc_1khz_selection: false
+      rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+      xosc32k_arch_cfden: false
+      xosc32k_arch_cfdeo: false
+      xosc32k_arch_cgm: Standard mode
+      xosc32k_arch_en1k: false
+      xosc32k_arch_en32k: false
+      xosc32k_arch_enable: false
+      xosc32k_arch_ondemand: true
+      xosc32k_arch_runstdby: false
+      xosc32k_arch_startup: 62592us
+      xosc32k_arch_swben: false
+      xosc32k_arch_xtalen: true
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  OSCCTRL:
+    user_label: OSCCTRL
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL
+    functionality: System
+    api: HAL:HPL:OSCCTRL
+    configuration:
+      $input: 2000000
+      $input_id: Generic clock generator 1
+      RESERVED_InputFreq: 2000000
+      RESERVED_InputFreq_id: Generic clock generator 1
+      _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
+      _$freq_output_Digital Phase Locked Loop (DPLL0): 47985664
+      _$freq_output_Digital Phase Locked Loop (DPLL1): 100000000
+      _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000
+      _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000
+      dfll_arch_bplckc: false
+      dfll_arch_calibration: false
+      dfll_arch_ccdis: false
+      dfll_arch_coarse: 31
+      dfll_arch_cstep: 1
+      dfll_arch_enable: true
+      dfll_arch_fine: 128
+      dfll_arch_fstep: 1
+      dfll_arch_llaw: false
+      dfll_arch_ondemand: false
+      dfll_arch_qldis: false
+      dfll_arch_runstdby: false
+      dfll_arch_stable: false
+      dfll_arch_usbcrm: false
+      dfll_arch_waitlock: true
+      dfll_mode: Open Loop Mode
+      dfll_mul: 0
+      dfll_ref_clock: Generic clock generator 2
+      enable_dfll: true
+      enable_fdpll0: false
+      enable_fdpll1: true
+      enable_xosc0: false
+      enable_xosc1: false
+      fdpll0_arch_dcoen: false
+      fdpll0_arch_enable: false
+      fdpll0_arch_filter: 0
+      fdpll0_arch_lbypass: false
+      fdpll0_arch_ltime: No time-out, automatic lock
+      fdpll0_arch_ondemand: false
+      fdpll0_arch_refclk: XOSC32K clock reference
+      fdpll0_arch_runstdby: false
+      fdpll0_arch_wuf: false
+      fdpll0_clock_dcofilter: 0
+      fdpll0_clock_div: 0
+      fdpll0_ldr: 1463
+      fdpll0_ldrfrac: 13
+      fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
+      fdpll1_arch_dcoen: false
+      fdpll1_arch_enable: true
+      fdpll1_arch_filter: 0
+      fdpll1_arch_lbypass: false
+      fdpll1_arch_ltime: No time-out, automatic lock
+      fdpll1_arch_ondemand: false
+      fdpll1_arch_refclk: GCLK clock reference
+      fdpll1_arch_runstdby: false
+      fdpll1_arch_wuf: false
+      fdpll1_clock_dcofilter: 0
+      fdpll1_clock_div: 0
+      fdpll1_ldr: 49
+      fdpll1_ldrfrac: 0
+      fdpll1_ref_clock: Generic clock generator 1
+      xosc0_arch_cfden: false
+      xosc0_arch_enable: false
+      xosc0_arch_enalc: false
+      xosc0_arch_lowbufgain: false
+      xosc0_arch_ondemand: false
+      xosc0_arch_runstdby: false
+      xosc0_arch_startup: 31us
+      xosc0_arch_swben: false
+      xosc0_arch_xtalen: false
+      xosc0_frequency: 12000000
+      xosc1_arch_cfden: false
+      xosc1_arch_enable: false
+      xosc1_arch_enalc: false
+      xosc1_arch_lowbufgain: false
+      xosc1_arch_ondemand: false
+      xosc1_arch_runstdby: false
+      xosc1_arch_startup: 31us
+      xosc1_arch_swben: false
+      xosc1_arch_xtalen: true
+      xosc1_frequency: 12000000
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  PORT:
+    user_label: PORT
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::PORT::driver_config_definition::PORT::HAL:HPL:PORT
+    functionality: System
+    api: HAL:HPL:PORT
+    configuration:
+      enable_port_input_event_0: true
+      enable_port_input_event_1: true
+      enable_port_input_event_2: true
+      enable_port_input_event_3: true
+      porta_event_action_0: Output register of pin will be set to level of event
+      porta_event_action_1: Output register of pin will be set to level of event
+      porta_event_action_2: Clear output register of pin on event
+      porta_event_action_3: Set output register of pin on event
+      porta_event_pin_identifier_0: 0
+      porta_event_pin_identifier_1: 0
+      porta_event_pin_identifier_2: 14
+      porta_event_pin_identifier_3: 14
+      porta_input_event_enable_0: false
+      porta_input_event_enable_1: false
+      porta_input_event_enable_2: true
+      porta_input_event_enable_3: true
+      portb_event_action_0: Clear output register of pin on event
+      portb_event_action_1: Set output register of pin on event
+      portb_event_action_2: Output register of pin will be set to level of event
+      portb_event_action_3: Output register of pin will be set to level of event
+      portb_event_pin_identifier_0: 22
+      portb_event_pin_identifier_1: 22
+      portb_event_pin_identifier_2: 0
+      portb_event_pin_identifier_3: 0
+      portb_input_event_enable_0: true
+      portb_input_event_enable_1: true
+      portb_input_event_enable_2: false
+      portb_input_event_enable_3: false
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  ECAT_QSPI:
+    user_label: ECAT_QSPI
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::QSPI::driver_config_definition::QSPI.Master::HAL:Driver:QSPI.DMA
+    functionality: Quad_SPI
+    api: HAL:Driver:QSPI_DMA
+    configuration:
+      qspi_advanced: false
+      qspi_baud_rate: 6000000
+      qspi_cpha: Data is changed on the leading edge of SPCK and captured on the following
+        edge of SPCK.
+      qspi_cpol: The inactive state value of SPCK is logic level zero.
+      qspi_dlybs: 0
+      qspi_dlycs: 0
+      qspi_dma_rx_channel: 0
+      qspi_dma_tx_channel: 1
+    optional_signals:
+    - identifier: ECAT_QSPI:CS
+      pad: PB11
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.CS
+      name: QSPI/CS
+      label: CS
+    - identifier: ECAT_QSPI:DATA/0
+      pad: PA08
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.DATA.0
+      name: QSPI/DATA/0
+      label: DATA/0
+    - identifier: ECAT_QSPI:DATA/1
+      pad: PA09
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.DATA.1
+      name: QSPI/DATA/1
+      label: DATA/1
+    - identifier: ECAT_QSPI:DATA/2
+      pad: PA10
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.DATA.2
+      name: QSPI/DATA/2
+      label: DATA/2
+    - identifier: ECAT_QSPI:DATA/3
+      pad: PA11
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.DATA.3
+      name: QSPI/DATA/3
+      label: DATA/3
+    - identifier: ECAT_QSPI:SCK
+      pad: PB10
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::QSPI.SCK
+      name: QSPI/SCK
+      label: SCK
+    variant: null
+    clocks:
+      domain_group: null
+  RAMECC:
+    user_label: RAMECC
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC
+    functionality: System
+    api: HAL:HPL:RAMECC
+    configuration: {}
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  I2C_0:
+    user_label: I2C_0
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Async
+    functionality: I2C
+    api: HAL:Driver:I2C_Master_Async
+    configuration:
+      i2c_master_advanced: false
+      i2c_master_arch_dbgstop: Keep running
+      i2c_master_arch_inactout: Disabled
+      i2c_master_arch_lowtout: false
+      i2c_master_arch_mexttoen: false
+      i2c_master_arch_runstdby: false
+      i2c_master_arch_sdahold: 300-600ns hold time
+      i2c_master_arch_sexttoen: false
+      i2c_master_arch_trise: 215
+      i2c_master_baud_rate: 100000
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Slow
+          input: Generic clock generator 3
+          external: false
+          external_frequency: 0
+        configuration:
+          core_gclk_selection: Generic clock generator 0
+          slow_gclk_selection: Generic clock generator 3
+  SPI_1_MSIF:
+    user_label: SPI_1_MSIF
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::SERCOM1::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.DMA
+    functionality: SPI
+    api: HAL:Driver:SPI_Master_DMA
+    configuration:
+      spi_master_advanced: true
+      spi_master_arch_cpha: Sample input on leading edge
+      spi_master_arch_cpol: SCK is low when idle
+      spi_master_arch_dbgstop: Keep running
+      spi_master_arch_dord: MSB first
+      spi_master_arch_ibon: In data stream
+      spi_master_arch_runstdby: false
+      spi_master_baud_rate: 1000000
+      spi_master_character_size: 8 bits
+      spi_master_dma_rx_channel: 0
+      spi_master_dma_tx_channel: 7
+      spi_master_dummybyte: 511
+      spi_master_rx_channel: true
+      spi_master_rx_enable: true
+    optional_signals: []
+    variant:
+      specification: TXPO=0, RXPO=3
+      required_signals:
+      - name: SERCOM1/PAD/0
+        pad: PA00
+        label: MOSI
+      - name: SERCOM1/PAD/1
+        pad: PA01
+        label: SCK
+      - name: SERCOM1/PAD/3
+        pad: PB23
+        label: MISO
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Slow
+          input: Generic clock generator 3
+          external: false
+          external_frequency: 0
+        configuration:
+          core_gclk_selection: Generic clock generator 0
+          slow_gclk_selection: Generic clock generator 3
+  SPI_2:
+    user_label: SPI_2
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::SERCOM2::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync
+    functionality: SPI
+    api: HAL:Driver:SPI_Master_Sync
+    configuration:
+      spi_master_advanced: true
+      spi_master_arch_cpha: Sample input on trailing edge
+      spi_master_arch_cpol: SCK is low when idle
+      spi_master_arch_dbgstop: Keep running
+      spi_master_arch_dord: MSB first
+      spi_master_arch_ibon: On buffer overflow
+      spi_master_arch_runstdby: false
+      spi_master_baud_rate: 1000000
+      spi_master_character_size: 8 bits
+      spi_master_dummybyte: 511
+      spi_master_rx_enable: true
+    optional_signals: []
+    variant:
+      specification: TXPO=0, RXPO=3
+      required_signals:
+      - name: SERCOM2/PAD/0
+        pad: PA12
+        label: MOSI
+      - name: SERCOM2/PAD/1
+        pad: PA13
+        label: SCK
+      - name: SERCOM2/PAD/3
+        pad: PA15
+        label: MISO
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Slow
+          input: Generic clock generator 3
+          external: false
+          external_frequency: 0
+        configuration:
+          core_gclk_selection: Generic clock generator 0
+          slow_gclk_selection: Generic clock generator 3
+  SPI_3:
+    user_label: SPI_3
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::SERCOM5::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync
+    functionality: SPI
+    api: HAL:Driver:SPI_Master_Sync
+    configuration:
+      spi_master_advanced: false
+      spi_master_arch_cpha: Sample input on leading edge
+      spi_master_arch_cpol: SCK is low when idle
+      spi_master_arch_dbgstop: Keep running
+      spi_master_arch_dord: MSB first
+      spi_master_arch_ibon: In data stream
+      spi_master_arch_runstdby: false
+      spi_master_baud_rate: 1000000
+      spi_master_character_size: 8 bits
+      spi_master_dummybyte: 511
+      spi_master_rx_enable: true
+    optional_signals: []
+    variant:
+      specification: TXPO=0, RXPO=3
+      required_signals:
+      - name: SERCOM5/PAD/0
+        pad: PB02
+        label: MOSI
+      - name: SERCOM5/PAD/1
+        pad: PB03
+        label: SCK
+      - name: SERCOM5/PAD/3
+        pad: PB01
+        label: MISO
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Slow
+          input: Generic clock generator 3
+          external: false
+          external_frequency: 0
+        configuration:
+          core_gclk_selection: Generic clock generator 0
+          slow_gclk_selection: Generic clock generator 3
+  TIMER_0:
+    user_label: TIMER_0
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TC0::driver_config_definition::8-bit.Counter.Mode::Lite:TC:Timer
+    functionality: Timer
+    api: Lite:TC:Timer
+    configuration:
+      cc_cc0: 10
+      cc_cc1: 60
+      cc_control: true
+      count_control: false
+      count_count: 0
+      ctrla_alock: false
+      ctrla_capten0: false
+      ctrla_capten1: false
+      ctrla_captmode0: DEFAULT
+      ctrla_captmode1: DEFAULT
+      ctrla_control: true
+      ctrla_copen0: false
+      ctrla_copen1: false
+      ctrla_enable: true
+      ctrla_mode: 1
+      ctrla_ondemand: false
+      ctrla_prescaler: DIV8
+      ctrla_prescsync: GCLK
+      ctrla_runstdby: false
+      ctrlbset_cmd: NONE
+      ctrlbset_control: false
+      ctrlbset_dir: false
+      ctrlbset_lupd: false
+      ctrlbset_oneshot: false
+      ctrlc_inven0: false
+      ctrlc_inven1: false
+      dbgctrl_control: false
+      dbgctrl_dbgrun: false
+      drvctrl_control: false
+      evctrl_control: true
+      evctrl_evact: 'OFF'
+      evctrl_mceo0: true
+      evctrl_mceo1: true
+      evctrl_ovfeo: false
+      evctrl_tcei: false
+      evctrl_tcinv: false
+      intenset_control: true
+      intenset_err: false
+      intenset_mc0: false
+      intenset_mc1: false
+      intenset_ovf: true
+      per_control: true
+      per_per: 250
+      wave_control: true
+      wave_wavegen: NFRQ
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: TC
+          input: Generic clock generator 1
+          external: false
+          external_frequency: 0
+        configuration:
+          tc_gclk_selection: Generic clock generator 1
+  TIMER_SPARE:
+    user_label: TIMER_SPARE
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TC1::driver_config_definition::8-bit.Counter.Mode::Lite:TC:Timer
+    functionality: Timer
+    api: Lite:TC:Timer
+    configuration:
+      cc_cc0: 10
+      cc_cc1: 60
+      cc_control: true
+      count_control: false
+      count_count: 0
+      ctrla_alock: false
+      ctrla_capten0: false
+      ctrla_capten1: false
+      ctrla_captmode0: DEFAULT
+      ctrla_captmode1: DEFAULT
+      ctrla_control: true
+      ctrla_copen0: false
+      ctrla_copen1: false
+      ctrla_enable: false
+      ctrla_mode: 1
+      ctrla_ondemand: false
+      ctrla_prescaler: DIV4
+      ctrla_prescsync: GCLK
+      ctrla_runstdby: false
+      ctrlbset_cmd: NONE
+      ctrlbset_control: false
+      ctrlbset_dir: false
+      ctrlbset_lupd: false
+      ctrlbset_oneshot: false
+      ctrlc_inven0: false
+      ctrlc_inven1: false
+      dbgctrl_control: false
+      dbgctrl_dbgrun: false
+      drvctrl_control: false
+      evctrl_control: true
+      evctrl_evact: 'OFF'
+      evctrl_mceo0: true
+      evctrl_mceo1: true
+      evctrl_ovfeo: true
+      evctrl_tcei: false
+      evctrl_tcinv: false
+      intenset_control: true
+      intenset_err: false
+      intenset_mc0: false
+      intenset_mc1: true
+      intenset_ovf: true
+      per_control: true
+      per_per: 250
+      wave_control: true
+      wave_wavegen: NFRQ
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: TC
+          input: Generic clock generator 1
+          external: false
+          external_frequency: 0
+        configuration:
+          tc_gclk_selection: Generic clock generator 1
+  TC_SPEED_M1:
+    user_label: TC_SPEED_M1
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TC2::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer
+    functionality: Timer
+    api: Lite:TC:Timer
+    configuration:
+      cc_cc0: 0
+      cc_cc1: 0
+      cc_control: false
+      count_control: false
+      count_count: 0
+      ctrla_alock: false
+      ctrla_capten0: true
+      ctrla_capten1: true
+      ctrla_captmode0: DEFAULT
+      ctrla_captmode1: DEFAULT
+      ctrla_control: true
+      ctrla_copen0: false
+      ctrla_copen1: false
+      ctrla_enable: true
+      ctrla_mode: 2
+      ctrla_ondemand: false
+      ctrla_prescaler: DIV4
+      ctrla_prescsync: GCLK
+      ctrla_runstdby: false
+      ctrlbset_cmd: NONE
+      ctrlbset_control: false
+      ctrlbset_dir: false
+      ctrlbset_lupd: false
+      ctrlbset_oneshot: false
+      ctrlc_inven0: false
+      ctrlc_inven1: false
+      dbgctrl_control: false
+      dbgctrl_dbgrun: false
+      drvctrl_control: false
+      evctrl_control: true
+      evctrl_evact: PPW
+      evctrl_mceo0: false
+      evctrl_mceo1: false
+      evctrl_ovfeo: true
+      evctrl_tcei: true
+      evctrl_tcinv: false
+      intenset_control: true
+      intenset_err: false
+      intenset_mc0: false
+      intenset_mc1: false
+      intenset_ovf: true
+      wave_control: true
+      wave_wavegen: NFRQ
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: TC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          tc_gclk_selection: Generic clock generator 0
+  TC_SPEED_M2:
+    user_label: TC_SPEED_M2
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TC4::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer
+    functionality: Timer
+    api: Lite:TC:Timer
+    configuration:
+      cc_cc0: 0
+      cc_cc1: 0
+      cc_control: false
+      count_control: false
+      count_count: 0
+      ctrla_alock: false
+      ctrla_capten0: true
+      ctrla_capten1: true
+      ctrla_captmode0: DEFAULT
+      ctrla_captmode1: DEFAULT
+      ctrla_control: true
+      ctrla_copen0: false
+      ctrla_copen1: false
+      ctrla_enable: true
+      ctrla_mode: 2
+      ctrla_ondemand: false
+      ctrla_prescaler: DIV4
+      ctrla_prescsync: GCLK
+      ctrla_runstdby: false
+      ctrlbset_cmd: NONE
+      ctrlbset_control: false
+      ctrlbset_dir: false
+      ctrlbset_lupd: false
+      ctrlbset_oneshot: false
+      ctrlc_inven0: false
+      ctrlc_inven1: false
+      dbgctrl_control: false
+      dbgctrl_dbgrun: false
+      drvctrl_control: false
+      evctrl_control: true
+      evctrl_evact: PPW
+      evctrl_mceo0: false
+      evctrl_mceo1: false
+      evctrl_ovfeo: true
+      evctrl_tcei: true
+      evctrl_tcinv: false
+      intenset_control: true
+      intenset_err: false
+      intenset_mc0: false
+      intenset_mc1: false
+      intenset_ovf: true
+      wave_control: true
+      wave_wavegen: NFRQ
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: TC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          tc_gclk_selection: Generic clock generator 0
+  PWM_0:
+    user_label: PWM_0
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TCC0::driver_config_definition::PWM::HAL:Driver:PWM
+    functionality: PWM
+    api: HAL:Driver:PWM
+    configuration:
+      tcc_arch_alock: false
+      tcc_arch_cc0: 0
+      tcc_arch_cc1: 0
+      tcc_arch_cc2: 0
+      tcc_arch_cc3: 0
+      tcc_arch_cc4: 0
+      tcc_arch_cc5: 0
+      tcc_arch_cnteo: false
+      tcc_arch_cntsel: An interrupt/event is generated when a new counter cycle starts
+      tcc_arch_cpten0: false
+      tcc_arch_cpten1: false
+      tcc_arch_cpten2: false
+      tcc_arch_cpten3: false
+      tcc_arch_cpten4: false
+      tcc_arch_cpten5: false
+      tcc_arch_cpten6: false
+      tcc_arch_cpten7: false
+      tcc_arch_dbgrun: false
+      tcc_arch_evact0: Event action disabled
+      tcc_arch_evact1: Event action disabled
+      tcc_arch_lupd: false
+      tcc_arch_mcei0: false
+      tcc_arch_mcei1: false
+      tcc_arch_mcei2: false
+      tcc_arch_mcei3: false
+      tcc_arch_mcei4: false
+      tcc_arch_mcei5: false
+      tcc_arch_mceo0: false
+      tcc_arch_mceo1: false
+      tcc_arch_mceo2: false
+      tcc_arch_mceo3: false
+      tcc_arch_mceo4: false
+      tcc_arch_mceo5: false
+      tcc_arch_ovfeo: true
+      tcc_arch_prescsync: Reload or reset counter on next GCLK
+      tcc_arch_runstdby: false
+      tcc_arch_sel_ch: 2
+      tcc_arch_tcei0: false
+      tcc_arch_tcei1: false
+      tcc_arch_tceinv0: false
+      tcc_arch_tceinv1: false
+      tcc_arch_trgeo: false
+      tcc_arch_wave_duty_val: 500
+      tcc_arch_wave_per_val: 48
+      tcc_arch_wavegen: Dual-slope, interrupt/event at ZERO (DSBOTTOM)
+      tcc_per: 10000
+      tcc_prescaler: Divide by 2
+      timer_event_control: true
+    optional_signals:
+    - identifier: PWM_0:WO/0
+      pad: PB12
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.0
+      name: TCC0/WO/0
+      label: WO/0
+    - identifier: PWM_0:WO/1
+      pad: PB13
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.1
+      name: TCC0/WO/1
+      label: WO/1
+    - identifier: PWM_0:WO/2
+      pad: PB14
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.2
+      name: TCC0/WO/2
+      label: WO/2
+    - identifier: PWM_0:WO/3
+      pad: PB15
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.3
+      name: TCC0/WO/3
+      label: WO/3
+    - identifier: PWM_0:WO/4
+      pad: PB16
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.4
+      name: TCC0/WO/4
+      label: WO/4
+    - identifier: PWM_0:WO/5
+      pad: PB17
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC0.WO.5
+      name: TCC0/WO/5
+      label: WO/5
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: TCC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          tcc_gclk_selection: Generic clock generator 0
+  PWM_1:
+    user_label: PWM_1
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::TCC1::driver_config_definition::PWM::HAL:Driver:PWM
+    functionality: PWM
+    api: HAL:Driver:PWM
+    configuration:
+      tcc_arch_alock: false
+      tcc_arch_cc0: 0
+      tcc_arch_cc1: 0
+      tcc_arch_cc2: 0
+      tcc_arch_cc3: 0
+      tcc_arch_cnteo: false
+      tcc_arch_cntsel: An interrupt/event is generated when a new counter cycle starts
+      tcc_arch_cpten0: false
+      tcc_arch_cpten1: false
+      tcc_arch_cpten2: false
+      tcc_arch_cpten3: false
+      tcc_arch_cpten4: false
+      tcc_arch_cpten5: false
+      tcc_arch_cpten6: false
+      tcc_arch_cpten7: false
+      tcc_arch_dbgrun: false
+      tcc_arch_evact0: Event action disabled
+      tcc_arch_evact1: Event action disabled
+      tcc_arch_lupd: false
+      tcc_arch_mcei0: false
+      tcc_arch_mcei1: false
+      tcc_arch_mcei2: false
+      tcc_arch_mcei3: false
+      tcc_arch_mceo0: false
+      tcc_arch_mceo1: false
+      tcc_arch_mceo2: false
+      tcc_arch_mceo3: false
+      tcc_arch_ovfeo: false
+      tcc_arch_prescsync: Reload or reset counter on next GCLK
+      tcc_arch_runstdby: false
+      tcc_arch_sel_ch: 2
+      tcc_arch_tcei0: false
+      tcc_arch_tcei1: false
+      tcc_arch_tceinv0: false
+      tcc_arch_tceinv1: false
+      tcc_arch_trgeo: false
+      tcc_arch_wave_duty_val: 500
+      tcc_arch_wave_per_val: 48
+      tcc_arch_wavegen: Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
+      tcc_per: 10000
+      tcc_prescaler: Divide by 2
+      timer_event_control: true
+    optional_signals:
+    - identifier: PWM_1:WO/0
+      pad: PA16
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.0
+      name: TCC1/WO/0
+      label: WO/0
+    - identifier: PWM_1:WO/1
+      pad: PA17
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.1
+      name: TCC1/WO/1
+      label: WO/1
+    - identifier: PWM_1:WO/2
+      pad: PA18
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.2
+      name: TCC1/WO/2
+      label: WO/2
+    - identifier: PWM_1:WO/3
+      pad: PA19
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.3
+      name: TCC1/WO/3
+      label: WO/3
+    - identifier: PWM_1:WO/4
+      pad: PA20
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.4
+      name: TCC1/WO/4
+      label: WO/4
+    - identifier: PWM_1:WO/5
+      pad: PA21
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::optional_signal_definition::TCC1.WO.5
+      name: TCC1/WO/5
+      label: WO/5
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: TCC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          tcc_gclk_selection: Generic clock generator 0
+pads:
+  SPI1_MOSI:
+    name: PA00
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA00
+    mode: Digital output
+    user_label: SPI1_MOSI
+    configuration: null
+  SPI1_SCK:
+    name: PA01
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA01
+    mode: Digital output
+    user_label: SPI1_SCK
+    configuration: null
+  ADS_DATA_RDY:
+    name: PA02
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA02
+    mode: Digital input
+    user_label: ADS_DATA_RDY
+    configuration: null
+  ANAREF_3V:
+    name: PA03
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA03
+    mode: Analog
+    user_label: ANAREF_3V
+    configuration: null
+  M1_IA:
+    name: PB04
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB04
+    mode: Analog
+    user_label: M1_IA
+    configuration: null
+  M1_IB:
+    name: PB05
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB05
+    mode: Analog
+    user_label: M1_IB
+    configuration: null
+  M2_IA:
+    name: PB06
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB06
+    mode: Analog
+    user_label: M2_IA
+    configuration: null
+  M2_IB:
+    name: PB07
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB07
+    mode: Analog
+    user_label: M2_IB
+    configuration: null
+  half_VREF:
+    name: PB08
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB08
+    mode: Analog
+    user_label: half_VREF
+    configuration: null
+  ADS_RESET:
+    name: PB09
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB09
+    mode: Digital output
+    user_label: ADS_RESET
+    configuration:
+      pad_initial_level: High
+  M1_HALLA:
+    name: PA04
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA04
+    mode: Peripheral IO
+    user_label: M1_HALLA
+    configuration: null
+  M1_HALLB:
+    name: PA05
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA05
+    mode: Peripheral IO
+    user_label: M1_HALLB
+    configuration: null
+  M1_HALLC:
+    name: PA06
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA06
+    mode: Peripheral IO
+    user_label: M1_HALLC
+    configuration: null
+  ECAT_SYNC:
+    name: PA07
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA07
+    mode: Digital input
+    user_label: ECAT_SYNC
+    configuration: null
+  ECAT_QSPI_MOSI:
+    name: PA08
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA08
+    mode: Advanced
+    user_label: ECAT_QSPI_MOSI
+    configuration: null
+  ECAT_QSPI_MISO:
+    name: PA09
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA09
+    mode: Advanced
+    user_label: ECAT_QSPI_MISO
+    configuration: null
+  ECAT_QSPI_DATA2:
+    name: PA10
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA10
+    mode: Advanced
+    user_label: ECAT_QSPI_DATA2
+    configuration: null
+  ECAT_QSPI_DATA3:
+    name: PA11
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA11
+    mode: Advanced
+    user_label: ECAT_QSPI_DATA3
+    configuration: null
+  ECAT_QSPI_SCK:
+    name: PB10
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB10
+    mode: Digital input
+    user_label: ECAT_QSPI_SCK
+    configuration: null
+  ECAT_QSPI_CS:
+    name: PB11
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB11
+    mode: Digital input
+    user_label: ECAT_QSPI_CS
+    configuration: null
+  M1_PWMA:
+    name: PB12
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB12
+    mode: Peripheral IO
+    user_label: M1_PWMA
+    configuration: null
+  M1_PWMB:
+    name: PB13
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB13
+    mode: Peripheral IO
+    user_label: M1_PWMB
+    configuration: null
+  M1_PWMC:
+    name: PB14
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB14
+    mode: Peripheral IO
+    user_label: M1_PWMC
+    configuration: null
+  M1_ENA:
+    name: PB15
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB15
+    mode: Peripheral IO
+    user_label: M1_ENA
+    configuration: null
+  SPI2_MOSI:
+    name: PA12
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA12
+    mode: Digital output
+    user_label: SPI2_MOSI
+    configuration: null
+  SPI2_SCK:
+    name: PA13
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA13
+    mode: Digital output
+    user_label: SPI2_SCK
+    configuration: null
+  SPI2_SS:
+    name: PA14
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA14
+    mode: Digital output
+    user_label: SPI2_SS
+    configuration:
+      pad_initial_level: High
+  SPI2_MISO:
+    name: PA15
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA15
+    mode: Digital input
+    user_label: SPI2_MISO
+    configuration: null
+  M2_PWMA:
+    name: PA16
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA16
+    mode: Peripheral IO
+    user_label: M2_PWMA
+    configuration: null
+  M2_PWMB:
+    name: PA17
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA17
+    mode: Peripheral IO
+    user_label: M2_PWMB
+    configuration: null
+  M2_PWMC:
+    name: PA18
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA18
+    mode: Peripheral IO
+    user_label: M2_PWMC
+    configuration: null
+  M2_ENA:
+    name: PA19
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA19
+    mode: Peripheral IO
+    user_label: M2_ENA
+    configuration: null
+  M1_ENB:
+    name: PB16
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB16
+    mode: Peripheral IO
+    user_label: M1_ENB
+    configuration: null
+  M1_ENC:
+    name: PB17
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB17
+    mode: Peripheral IO
+    user_label: M1_ENC
+    configuration: null
+  M2_ENB:
+    name: PA20
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA20
+    mode: Peripheral IO
+    user_label: M2_ENB
+    configuration: null
+  M2_ENC:
+    name: PA21
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA21
+    mode: Peripheral IO
+    user_label: M2_ENC
+    configuration: null
+  M2_HALLA:
+    name: PA22
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA22
+    mode: Peripheral IO
+    user_label: M2_HALLA
+    configuration: null
+  M2_HALLB:
+    name: PA23
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA23
+    mode: Peripheral IO
+    user_label: M2_HALLB
+    configuration: null
+  M2_HALLC:
+    name: PA24
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA24
+    mode: Peripheral IO
+    user_label: M2_HALLC
+    configuration: null
+  M1_RST:
+    name: PA25
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA25
+    mode: Digital output
+    user_label: M1_RST
+    configuration: null
+  SPI1_CS:
+    name: PB22
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB22
+    mode: Digital output
+    user_label: SPI1_CS
+    configuration:
+      pad_initial_level: High
+  SPI1_MISO:
+    name: PB23
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB23
+    mode: Digital input
+    user_label: SPI1_MISO
+    configuration: null
+  M2_RST:
+    name: PA27
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PA27
+    mode: Digital output
+    user_label: M2_RST
+    configuration: null
+  M1_RST_Bar:
+    name: PB30
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB30
+    mode: Digital input
+    user_label: M1_RST_Bar
+    configuration: null
+  M2_RST_Bar:
+    name: PB31
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB31
+    mode: Digital input
+    user_label: M2_RST_Bar
+    configuration: null
+  SPI3_SS:
+    name: PB00
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB00
+    mode: Digital output
+    user_label: SPI3_SS
+    configuration:
+      pad_initial_level: High
+  SPI3_MISO:
+    name: PB01
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB01
+    mode: Digital input
+    user_label: SPI3_MISO
+    configuration: null
+  SPI3_MOSI:
+    name: PB02
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB02
+    mode: Digital output
+    user_label: SPI3_MOSI
+    configuration: null
+  SPI3_SCK:
+    name: PB03
+    definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51J18A-MF::pad::PB03
+    mode: Digital output
+    user_label: SPI3_SCK
+    configuration: null
+toolchain_options: []
+static_files: []
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.c
new file mode 100644
index 0000000..545750c
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.c
@@ -0,0 +1,330 @@
+/*
+ * ADS1299.c
+ *
+ * Created: 8/22/2021 3:25:55 PM
+ *  Author: ge37vez
+ */ 
+
+#include "ADS1299.h"
+
+/* Settings 
+* No daisy:
+* 4 EMG channels channels at 1000.0 Hz.
+* Gain 24, SRB2 Open, Normal electrode input
+* Route all Channels_P to Bias derivation
+* Route all Channels_P to Bias derivation
+* Lead off functions off
+
+Expected ADS Board Registers
+* ADS_ID, 00, 3C, 0, 0, 1, 1, 1, 1, 1, 0
+* CONFIG1, 01, 94, 1, 0, 0, 1, 0, 1, 0, 0
+* CONFIG2, 02, C0, 1, 1, 0, 0, 0, 0, 0, 0
+* CONFIG3, 03, EC, 1, 1, 1, 0, 1, 1, 0, 0
+* LOFF, 04, 02, 0, 0, 0, 0, 0, 0, 1, 0
+* CH1SET, 05, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH2SET, 06, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH3SET, 07, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH4SET, 08, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH5SET, 09, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH6SET, 0A, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH7SET, 0B, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH8SET, 0C, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* BIAS_SENSP, 0D, FF, 1, 1, 1, 1, 1, 1, 1, 1
+* BIAS_SENSN, 0E, FF, 1, 1, 1, 1, 1, 1, 1, 1
+* LOFF_SENSP, 0F, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* LOFF_SENSN, 10, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* LOFF_FLIP, 11, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* LOFF_STATP, 12, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* LOFF_STATN, 13, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* GPIO, 14, 0F, 0, 0, 0, 0, 1, 1, 1, 1
+* MISC1, 15, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* MISC2, 16, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* CONFIG4, 17, 00, 0, 0, 0, 0, 0, 0, 0, 0
+*/
+
+void initialize_ads()
+{
+	spi_m_sync_disable(ADS1299.SPI_descr);
+	/* Set Mode 1 */
+	hri_sercomspi_write_CTRLA_CPOL_bit((SercomSpi *)(ADS1299.SPI_descr->dev.prvt), false);
+	hri_sercomspi_write_CTRLA_CPHA_bit((SercomSpi *)(ADS1299.SPI_descr->dev.prvt), true);
+	/* Init SPI*/
+	spi_m_sync_enable(ADS1299.SPI_descr);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+	delay_us(20);
+	
+	/* Reset ADS1299 - Reset Active Low*/
+	gpio_set_pin_level(ADS1299.reset_pin, false);
+	delay_us(20);
+	gpio_set_pin_level(ADS1299.reset_pin, true);
+	delay_us(20);
+	
+	ADS1299_RESET();					   // all registers set to default
+	ADS1299_SDATAC();					   // stop Read Data Continuous mode to communicate with ADS
+	ADS1299_RREGS(0x00, 0x17);			   // read ADS registers starting at 0x00 and ending at 0x17
+
+	/* Write Config Registers */
+	ADS1299_WREG(CONFIG1,0x94);			   // Set Config 1 Register
+	//ADS1299_WREG(CONFIG2,0xC0);		   // Set Config 2 Register - Standard
+	ADS1299_WREG(CONFIG2,0xD4);			   // Set Config 2 Register - internal test signal, pulsed
+	//ADS1299_WREG(CONFIG2,0xD7);		   // Set Config 2 Register - internal test signal, DC
+	ADS1299_WREG(CONFIG3,0xEC);			   // Set Config 3 Register
+	ADS1299_WREG(LOFF,0x02);			   // Set LOFF Register
+	for(uint8_t i=CH1SET; i<=CH4SET; i++)  // set up to modify the 4 channel setting registers
+	{  
+		//ADS1299.reg_data[i] = 0x68;        // the regData array mirrors the ADS1299 register addresses
+		ADS1299.reg_data[i] = 0x6D;          // Test signal
+	}
+	ADS1299_WREGS(CH1SET,3);               // write new channel settings
+	ADS1299_WREG(BIAS_SENSP,0xFF);		   // Set BIAS_SENSP Register
+	ADS1299_WREG(BIAS_SENSN,0xFF);		   // Set BIAS_SENSN Register
+	ADS1299_WREG(BIAS_SENSP,0xFF);		   // Set BIAS_SENSP Register
+	ADS1299_WREG(GPIO_REG,0x0F);		   // Set BIAS_SENSP Register
+	/* Remaining Registers left at 0x00 */
+	ADS1299_RREGS(0x00, 0x17);			   // read ADS registers to verify settings
+	ADS1299_RDATAC();					   // enter Read Data Continuous mode
+	volatile int x = 0;
+}
+
+uint8_t getDeviceID()
+{
+	uint8_t data = ADS1299_RREG(0x00);
+	return data;
+}
+
+// ----------------------------------------------------------------------
+// AS5048 Registers & Commands
+// ----------------------------------------------------------------------
+
+void ADS1299_WAKEUP() {
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _WAKEUP);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+	delay_us(3);  		//must wait 4 tCLK cycles before sending another command (Datasheet, pg. 35)
+}
+
+void ADS1299_STANDBY() {		// only allowed to send WAKEUP after sending STANDBY
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _STANDBY);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+}
+
+void ADS1299_RESET() {			// reset all the registers to default settings
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _RESET);
+	delay_us(12);   	//must wait 18 tCLK cycles to execute this command (Datasheet, pg. 35)
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+}
+
+void ADS1299_START() {			//start data conversion
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _START);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+	init_streaming_mode();
+	
+}
+
+void init_streaming_mode()
+{
+	spi_m_sync_disable(ADS1299.SPI_descr);
+	/* Change to 32-Bit Mode */
+	SERCOM2->SPI.CTRLC.bit.ICSPACE = 4;
+	SERCOM2->SPI.CTRLC.bit.DATA32B= true;
+	SERCOM2->SPI.LENGTH.bit.LENEN = true;
+	SERCOM2->SPI.LENGTH.bit.LEN = 3;
+	/* Init SPI*/
+	spi_m_sync_enable(ADS1299.SPI_descr);
+}
+void ADS1299_STOP() {			//stop data conversion
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _STOP);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+}
+
+void ADS1299_RDATAC() {
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _RDATAC);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+	delay_us(3);
+}
+void ADS1299_SDATAC() {
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _SDATAC);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+	delay_us(3);   //must wait 4 tCLK cycles after executing this command (Datasheet, pg. 37)
+}
+
+// ----------------------------------------------------------------------
+// SPI register Related Commands
+// ----------------------------------------------------------------------
+//  reads ONE register at _address
+uint8_t ADS1299_RREG(uint8_t _address) 
+{
+	uint8_t opcode1 = _address + 0x20; 							//  RREG expects 001rrrrr where rrrrr = _address
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, opcode1);
+	_transfer_byte(ADS1299.SPI_descr, 0x00);
+	ADS1299.reg_data[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+	return ADS1299.reg_data[_address];
+}
+
+// Read more than one register starting at _address
+void ADS1299_RREGS(uint8_t _address, uint8_t _numRegistersMinusOne) 
+{
+	uint8_t opcode1 = _address + 0x20; 							//  RREG expects 001rrrrr where rrrrr = _address
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, opcode1);
+	_transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne);
+	for(int i = 0; i <= _numRegistersMinusOne; i++){			//  add register uint8_t to mirror array
+        ADS1299.reg_data[_address + i] = _transfer_byte(ADS1299.SPI_descr, 0x00);	
+	}
+	//ADS1299.regData[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+}
+
+void ADS1299_WREG(uint8_t _address, uint8_t _value) {					//  Write ONE register at _address
+	uint8_t opcode1 = _address + 0x40; 							//  WREG expects 010rrrrr where rrrrr = _address
+	gpio_set_pin_level(ADS1299.SS_pin, false); 					//  open SPI
+	_transfer_byte(ADS1299.SPI_descr, opcode1);					//  Send WREG command & address
+	_transfer_byte(ADS1299.SPI_descr, 0x00);						//	Send number of registers to read -1
+	_transfer_byte(ADS1299.SPI_descr, _value);					//  Write the value to the register
+	gpio_set_pin_level(ADS1299.SS_pin, true);					//  close SPI
+	ADS1299.reg_data[_address] = _value;							//  update the mirror array
+}
+
+void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne) {
+	uint8_t opcode1 = _address + 0x40;							//  WREG expects 010rrrrr where rrrrr = _address
+	gpio_set_pin_level(ADS1299.SS_pin, false); 					//  open SPI
+	_transfer_byte(ADS1299.SPI_descr, opcode1);					//  Send WREG command & address
+	_transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne);	//	Send number of registers to read -1
+	for (int i=_address; i <=(_address + _numRegistersMinusOne); i++){
+		_transfer_byte(ADS1299.SPI_descr, ADS1299.reg_data[i]);	//  Write to the registers
+	}
+	gpio_set_pin_level(ADS1299.SS_pin, true);					//  close SPI
+}
+
+//read data
+void ADS1299_RDATA() {	//  use in Stop Read Continuous mode when DRDY goes low
+	uint8_t inByte;
+	ADS1299.stat_1 = 0;							//  clear the status registers
+	int nchan = 4;	//assume 4 channel.  
+	gpio_set_pin_level(ADS1299.SS_pin, false);				//  open SPI
+	_transfer_byte(ADS1299.SPI_descr, _RDATA);
+	
+	for(int i=0; i<3; i++){			//  read 3 byte status register (1100+LOFF_STATP+LOFF_STATN+GPIO[7:4])
+		inByte = _transfer_byte(ADS1299.SPI_descr, 0x00);
+		ADS1299.stat_1 = (ADS1299.stat_1<<8) | inByte;
+	}
+	
+	for(int i = 0; i<nchan; i++){
+		for(int j=0; j<3; j++){		//  read 24 bits of channel data from 1st ADS in 8 3 byte chunks
+			inByte = _transfer_byte(ADS1299.SPI_descr, 0x00);
+			ADS1299.channel_data[i] = (ADS1299.channel_data[i]<<8) | inByte;
+		}
+	}
+		
+	for(int i=0; i<nchan; i++){			// convert 3 byte 2's compliment to 4 byte 2's compliment
+		if(bitRead(ADS1299.channel_data[i],23) == 1){
+			ADS1299.channel_data[i] |= 0xFF000000;
+			}else{
+			ADS1299.channel_data[i] &= 0x00FFFFFF;
+		}
+	}
+}
+
+
+//int32_t* ADS1299_UPDATECHANNELDATA()
+//{
+	//uint8_t inByte;
+	//int nchan=4;  //assume 8 channel.  If needed, it automatically changes to 16 automatically in a later block.
+	//gpio_set_pin_level(ADS1299.SS_pin, false);				//  open SPI
+	//
+	//// READ CHANNEL DATA FROM FIRST ADS IN DAISY LINE
+	//for(int i=0; i<3; i++){		//  read 3 byte status register from ADS 1 (1100+LOFF_STATP+LOFF_STATN+GPIO[7:4])
+		//inByte = _transfer_byte(ADS1299.SPI_descr,0x00);
+		//ADS1299.stat_1 = (ADS1299.stat_1<<8) | inByte;				
+	//}
+	//
+	//for(int i = 0; i<8; i++){
+		//for(int j=0; j<3; j++){		//  read 24 bits of channel data from 1st ADS in 8 3 byte chunks
+			//inByte = _transfer_byte(ADS1299.SPI_descr, 0x00);
+			//ADS1299.channel_data[i] = (ADS1299.channel_data[i]<<8) | inByte;
+		//}
+	//}
+		//
+	//gpio_set_pin_level(ADS1299.SS_pin, true);				//  close SPI
+	//
+	////reformat the numbers
+	//for(int i=0; i<nchan; i++){			// convert 3 byte 2's compliment to 4 byte 2's compliment	
+		//if(bitRead(ADS1299.channel_data[i],23) == 1){	
+			//ADS1299.channel_data[i] |= 0xFF000000;
+		//}else{
+			//ADS1299.channel_data[i] &= 0x00FFFFFF;
+		//}
+	//}
+	//return &ADS1299.channel_data;
+//}
+
+int32_t* ADS1299_UPDATECHANNELDATA()
+{
+	uint8_t inByte;
+	int nchan=8;  //assume 8 channel.  If needed, it automatically changes to 16 automatically in a later block.
+	gpio_set_pin_level(ADS1299.SS_pin, false);				//  open SPI
+	
+	// READ CHANNEL DATA FROM FIRST ADS IN DAISY LINE
+	for(int i=0; i<3; i++){		//  read 3 byte status register from ADS 1 (1100+LOFF_STATP+LOFF_STATN+GPIO[7:4])
+		inByte = _transfer_byte(ADS1299.SPI_descr,0x00);
+		ADS1299.stat_1 = (ADS1299.stat_1<<8) | inByte;				
+	}
+	
+	for(int i = 0; i<8; i++){
+		for(int j=0; j<3; j++){		//  read 24 bits of channel data from 1st ADS in 8 3 byte chunks
+			inByte = _transfer_byte(ADS1299.SPI_descr, 0x00);
+			_ads1299_channel_data[i] = (_ads1299_channel_data[i]<<8) | inByte;
+		}
+	}
+		
+	gpio_set_pin_level(ADS1299.SS_pin, true);				//  close SPI
+	
+	//reformat the numbers
+	for(int i=0; i<nchan; i++){			// convert 3 byte 2's compliment to 4 byte 2's compliment	
+		if(bitRead(_ads1299_channel_data[i],23) == 1){	
+			_ads1299_channel_data[i] |= 0xFF000000;
+		}else{
+			_ads1299_channel_data[i] &= 0x00FFFFFF;
+		}
+	}
+	return &_ads1299_channel_data;
+}
+
+uint8_t _transfer_byte(struct spi_m_sync_descriptor *spi, uint8_t command)
+{
+	uint8_t in_buf[1], out_buf[1];
+	uint8_t wordRead;
+	
+	out_buf[0] = command; 
+	struct spi_xfer xfer;
+	xfer.rxbuf = in_buf;
+	xfer.txbuf = out_buf;
+	xfer.size  = 1;
+	spi_m_sync_transfer(ADS1299.SPI_descr, &xfer);
+	wordRead = in_buf[0];
+	return (wordRead);
+}
+
+uint16_t _transfer_word(struct spi_m_sync_descriptor *spi, uint16_t command)
+{
+	uint8_t in_buf[2], out_buf[2];
+	uint16_t wordRead;
+	
+	out_buf[1] = command & 0xFF;
+	out_buf[0] = ( command >> 8 ) & 0xFF;
+	struct spi_xfer  xfer;
+	xfer.rxbuf = in_buf;
+	xfer.txbuf = (uint8_t *)out_buf;
+	xfer.size  = 2;
+	spi_m_sync_transfer(ADS1299.SPI_descr, &xfer);
+	wordRead = (uint16_t)((in_buf[0] << 8) | in_buf[1]);
+	return (wordRead);
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.h
new file mode 100644
index 0000000..4fddcd2
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.h
@@ -0,0 +1,113 @@
+/*
+ * ADS1299.h
+ *
+ * Created: 8/22/2021 3:25:39 PM
+ *  Author: ge37vez
+ */ 
+
+
+#ifndef ADS1299_H_
+#define ADS1299_H_
+
+#include "atmel_start.h"
+
+#define bitRead(value, bit) (((value) >> (bit)) & 0x01)
+#define bitSet(value, bit) ((value) |= (1UL << (bit)))
+#define bitClear(value, bit) ((value) &= ~(1UL << (bit)))
+#define bitWrite(value, bit, bitvalue) ((bitvalue) ? bitSet(value, bit) : bitClear(value, bit))
+
+//SPI Command Definition Byte Assignments (Datasheet, p35)
+#define _WAKEUP		0x02 // Wake-up from standby mode
+#define _STANDBY	0x04 // Enter Standby mode
+#define _RESET		0x06 // Reset the device registers to default
+#define _START		0x08 // Start and restart (synchronize) conversions
+#define _STOP		0x0A // Stop conversion
+#define _RDATAC		0x10 // Enable Read Data Continuous mode (default mode at power-up)
+#define _SDATAC		0x11 // Stop Read Data Continuous mode
+#define _RDATA		0x12 // Read data by command; supports multiple read back
+
+//Register Addresses
+#define ID			0x00
+#define CONFIG1		0x01
+#define CONFIG2		0x02
+#define CONFIG3		0x03
+#define LOFF		0x04
+#define CH1SET		0x05
+#define CH2SET		0x06
+#define CH3SET		0x07
+#define CH4SET		0x08
+#define CH5SET		0x09
+#define CH6SET		0x0A
+#define CH7SET		0x0B
+#define CH8SET		0x0C
+#define BIAS_SENSP  0x0D
+#define BIAS_SENSN  0x0E
+#define LOFF_SENSP  0x0F
+#define LOFF_SENSN  0x10
+#define LOFF_FLIP   0x11
+#define LOFF_STATP  0x12
+#define LOFF_STATN  0x13
+#define GPIO_REG    0x14
+#define MISC1       0x15
+#define MISC2       0x16
+#define CONFIG4     0x17
+
+#define ADS_BUFFER_SIZE 9
+
+volatile int32_t _ads1299_channel_data[9];
+volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
+volatile uint8_t _ads1299_reg_data[24];
+
+/* Struct Definitions */
+volatile struct SPI_ADS1299 {
+	volatile struct spi_m_sync_descriptor *SPI_descr;
+	volatile bool data_ReadyFlag;
+	volatile uint32_t SS_pin;
+	volatile uint32_t reset_pin;
+	volatile uint8_t* reg_data;
+	volatile int32_t* channel_data; 
+	volatile int16_t  stat_1;
+};
+
+static volatile struct SPI_ADS1299 ADS1299 = {
+	.SPI_descr = &SPI_2,
+	.data_ReadyFlag = false,
+	.SS_pin = SPI2_SS,
+	.reset_pin = ADS_RESET,
+	.reg_data = &_ads1299_reg_data[0], 
+	.channel_data = &_ads1299_channel_data[0],
+};
+
+void initialize_ads();
+void init_streaming_mode();
+
+//ADS1299 SPI Command Definitions (Datasheet, p35)
+//System Commands
+void ADS1299_WAKEUP();
+void ADS1299_STANDBY();
+void ADS1299_RESET();
+void ADS1299_START();
+void ADS1299_STOP();
+
+//Data Read Commands
+void ADS1299_RDATAC();
+void ADS1299_SDATAC();
+void ADS1299_RDATA();
+
+//Register Read/Write Commands
+uint8_t getDeviceID();
+uint8_t ADS1299_RREG(uint8_t _address);
+void ADS1299_RREGS(uint8_t _address, uint8_t _numRegistersMinusOne);
+void printRegisterName(uint8_t _address);
+void ADS1299_WREG(uint8_t _address, uint8_t _value);
+void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne);
+void printHex(uint8_t _data);
+int32_t* ADS1299_UPDATECHANNELDATA();
+
+uint8_t _transfer_byte(struct spi_m_sync_descriptor *spi, uint8_t command);
+uint16_t _transfer_word(struct spi_m_sync_descriptor *spi, uint16_t command);
+//SPI Transfer function
+
+
+
+#endif /* ADS1299_H_ */
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/RTE_Components.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/RTE_Components.h
new file mode 100644
index 0000000..bc463d5
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/RTE_Components.h
@@ -0,0 +1,54 @@
+ /**
+ * \file
+ *
+ * \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
+ *
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.
+ *
+ * \acme_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \acme_license_stop
+ *
+ * Project: Two_Motor_D51
+ * Target:  ATSAMD51J18A 
+ *
+ **/
+
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+#define ATMEL_START
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_adc_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_adc_config.h
new file mode 100644
index 0000000..f3597b3
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_adc_config.h
@@ -0,0 +1,595 @@
+/* Auto-generated config file hpl_adc_config.h */
+#ifndef HPL_ADC_CONFIG_H
+#define HPL_ADC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#ifndef CONF_ADC_0_ENABLE
+#define CONF_ADC_0_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <o> Conversion Result Resolution
+// <0x0=>12-bit
+// <0x1=>16-bit (averaging must be enabled)
+// <0x2=>10-bit
+// <0x3=>8-bit
+// <i>  Defines the bit resolution for the ADC sample values (RESSEL)
+// <id> adc_resolution
+#ifndef CONF_ADC_0_RESSEL
+#define CONF_ADC_0_RESSEL 0x0
+#endif
+
+// <o> Reference Selection
+// <0x0=>Internal bandgap reference
+// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
+// <0x3=>VDDANA
+// <0x4=>External reference A
+// <0x5=>External reference B
+// <0x6=>External reference C
+// <i> Select the reference for the ADC (REFSEL)
+// <id> adc_reference
+#ifndef CONF_ADC_0_REFSEL
+#define CONF_ADC_0_REFSEL 0x0
+#endif
+
+// <o> Prescaler configuration
+// <0x0=>Peripheral clock divided by 2
+// <0x1=>Peripheral clock divided by 4
+// <0x2=>Peripheral clock divided by 8
+// <0x3=>Peripheral clock divided by 16
+// <0x4=>Peripheral clock divided by 32
+// <0x5=>Peripheral clock divided by 64
+// <0x6=>Peripheral clock divided by 128
+// <0x7=>Peripheral clock divided by 256
+// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
+// <id> adc_prescaler
+#ifndef CONF_ADC_0_PRESCALER
+#define CONF_ADC_0_PRESCALER 0x0
+#endif
+
+// <q> Free Running Mode
+// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
+// <id> adc_freerunning_mode
+#ifndef CONF_ADC_0_FREERUN
+#define CONF_ADC_0_FREERUN 0
+#endif
+
+// <q> Differential Mode
+// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
+// <id> adc_differential_mode
+#ifndef CONF_ADC_0_DIFFMODE
+#define CONF_ADC_0_DIFFMODE 0
+#endif
+
+// <o> Positive Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x08=>ADC AIN8 pin
+// <0x09=>ADC AIN9 pin
+// <0x0A=>ADC AIN10 pin
+// <0x0B=>ADC AIN11 pin
+// <0x0C=>ADC AIN12 pin
+// <0x0D=>ADC AIN13 pin
+// <0x0E=>ADC AIN14 pin
+// <0x0F=>ADC AIN15 pin
+// <0x18=>1/4 scaled core supply
+// <0x19=>1/4 Scaled VBAT Supply
+// <0x1A=>1/4 scaled I/O supply
+// <0x1B=>Bandgap voltage
+// <0x1C=>Temperature reference (PTAT)
+// <0x1D=>Temperature reference (CTAT)
+// <0x1E=>DAC Output
+// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
+// <id> adc_pinmux_positive
+#ifndef CONF_ADC_0_MUXPOS
+#define CONF_ADC_0_MUXPOS 0x0
+#endif
+
+// <o> Negative Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x18=>Internal ground
+// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
+// <id> adc_pinmux_negative
+#ifndef CONF_ADC_0_MUXNEG
+#define CONF_ADC_0_MUXNEG 0x0
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> adc_advanced_settings
+#ifndef CONF_ADC_0_ADVANCED
+#define CONF_ADC_0_ADVANCED 0
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
+// <id> adc_arch_runstdby
+#ifndef CONF_ADC_0_RUNSTDBY
+#define CONF_ADC_0_RUNSTDBY 0
+#endif
+
+// <q>Debug Run
+// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
+// <id> adc_arch_dbgrun
+#ifndef CONF_ADC_0_DBGRUN
+#define CONF_ADC_0_DBGRUN 0
+#endif
+
+// <q> On Demand Control
+// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
+// <id> adc_arch_ondemand
+#ifndef CONF_ADC_0_ONDEMAND
+#define CONF_ADC_0_ONDEMAND 0
+#endif
+
+// <q> Left-Adjusted Result
+// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
+// <id> adc_arch_leftadj
+#ifndef CONF_ADC_0_LEFTADJ
+#define CONF_ADC_0_LEFTADJ 0
+#endif
+
+// <q> Reference Buffer Offset Compensation Enable
+// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
+// <id> adc_arch_refcomp
+#ifndef CONF_ADC_0_REFCOMP
+#define CONF_ADC_0_REFCOMP 0
+#endif
+
+// <q>Comparator Offset Compensation Enable
+// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
+// <id> adc_arch_offcomp
+#ifndef CONF_ADC_0_OFFCOMP
+#define CONF_ADC_0_OFFCOMP 0
+#endif
+
+// <q> Digital Correction Logic Enabled
+// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
+// <id> adc_arch_corren
+#ifndef CONF_ADC_0_CORREN
+#define CONF_ADC_0_CORREN 0
+#endif
+
+// <o> Offset Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
+// <id> adc_arch_offsetcorr
+#ifndef CONF_ADC_0_OFFSETCORR
+#define CONF_ADC_0_OFFSETCORR 0
+#endif
+
+// <o> Gain Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
+// <id> adc_arch_gaincorr
+#ifndef CONF_ADC_0_GAINCORR
+#define CONF_ADC_0_GAINCORR 0
+#endif
+
+// <o> Adjusting Result / Division Coefficient <0-7>
+// <i> These bits define the division coefficient in 2n steps. (ADJRES)
+// <id> adc_arch_adjres
+#ifndef CONF_ADC_0_ADJRES
+#define CONF_ADC_0_ADJRES 0x0
+#endif
+
+// <o.0..10> Number of Samples to be Collected
+// <0x0=>1 sample
+// <0x1=>2 samples
+// <0x2=>4 samples
+// <0x3=>8 samples
+// <0x4=>16 samples
+// <0x5=>32 samples
+// <0x6=>64 samples
+// <0x7=>128 samples
+// <0x8=>256 samples
+// <0x9=>512 samples
+// <0xA=>1024 samples
+// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
+// <id> adc_arch_samplenum
+#ifndef CONF_ADC_0_SAMPLENUM
+#define CONF_ADC_0_SAMPLENUM 0x0
+#endif
+
+// <o> Sampling Time Length <0-63>
+// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
+// <id> adc_arch_samplen
+#ifndef CONF_ADC_0_SAMPLEN
+#define CONF_ADC_0_SAMPLEN 0
+#endif
+
+// <o> Window Monitor Mode
+// <0x0=>No window mode
+// <0x1=>Mode 1: RESULT above lower threshold
+// <0x2=>Mode 2: RESULT beneath upper threshold
+// <0x3=>Mode 3: RESULT inside lower and upper threshold
+// <0x4=>Mode 4: RESULT outside lower and upper threshold
+// <i> These bits enable and define the window monitor mode. (WINMODE)
+// <id> adc_arch_winmode
+#ifndef CONF_ADC_0_WINMODE
+#define CONF_ADC_0_WINMODE 0x0
+#endif
+
+// <o> Window Monitor Lower Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
+// <id> adc_arch_winlt
+#ifndef CONF_ADC_0_WINLT
+#define CONF_ADC_0_WINLT 0
+#endif
+
+// <o> Window Monitor Upper Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
+// <id> adc_arch_winut
+#ifndef CONF_ADC_0_WINUT
+#define CONF_ADC_0_WINUT 0
+#endif
+
+// <o> Bitmask for positive input sequence <0-4294967295>
+// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
+// <id> adc_arch_seqen
+#ifndef CONF_ADC_0_SEQEN
+#define CONF_ADC_0_SEQEN 0x0
+#endif
+
+// </e>
+
+// <e> Event Control
+// <id> adc_arch_event_settings
+#ifndef CONF_ADC_0_EVENT_CONTROL
+#define CONF_ADC_0_EVENT_CONTROL 0
+#endif
+
+// <q> Window Monitor Event Out
+// <i> Enables event output on window event (WINMONEO)
+// <id> adc_arch_winmoneo
+#ifndef CONF_ADC_0_WINMONEO
+#define CONF_ADC_0_WINMONEO 0
+#endif
+
+// <q> Result Ready Event Out
+// <i> Enables event output on result ready event (RESRDEO)
+// <id> adc_arch_resrdyeo
+#ifndef CONF_ADC_0_RESRDYEO
+#define CONF_ADC_0_RESRDYEO 0
+#endif
+
+// <q> Invert flush Event Signal
+// <i> Invert the flush event input signal (FLUSHINV)
+// <id> adc_arch_flushinv
+#ifndef CONF_ADC_0_FLUSHINV
+#define CONF_ADC_0_FLUSHINV 0
+#endif
+
+// <q> Trigger Flush On Event
+// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
+// <id> adc_arch_flushei
+#ifndef CONF_ADC_0_FLUSHEI
+#define CONF_ADC_0_FLUSHEI 0
+#endif
+
+// <q> Invert Start Conversion Event Signal
+// <i> Invert the start conversion event input signal (STARTINV)
+// <id> adc_arch_startinv
+#ifndef CONF_ADC_0_STARTINV
+#define CONF_ADC_0_STARTINV 0
+#endif
+
+// <q> Trigger Conversion On Event
+// <i> Trigger a conversion on event. (STARTEI)
+// <id> adc_arch_startei
+#ifndef CONF_ADC_0_STARTEI
+#define CONF_ADC_0_STARTEI 0
+#endif
+
+// </e>
+
+#ifndef CONF_ADC_1_ENABLE
+#define CONF_ADC_1_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <o> Conversion Result Resolution
+// <0x0=>12-bit
+// <0x1=>16-bit (averaging must be enabled)
+// <0x2=>10-bit
+// <0x3=>8-bit
+// <i>  Defines the bit resolution for the ADC sample values (RESSEL)
+// <id> adc_resolution
+#ifndef CONF_ADC_1_RESSEL
+#define CONF_ADC_1_RESSEL 0x0
+#endif
+
+// <o> Reference Selection
+// <0x0=>Internal bandgap reference
+// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
+// <0x3=>VDDANA
+// <0x4=>External reference A
+// <0x5=>External reference B
+// <0x6=>External reference C
+// <i> Select the reference for the ADC (REFSEL)
+// <id> adc_reference
+#ifndef CONF_ADC_1_REFSEL
+#define CONF_ADC_1_REFSEL 0x4
+#endif
+
+// <o> Prescaler configuration
+// <0x0=>Peripheral clock divided by 2
+// <0x1=>Peripheral clock divided by 4
+// <0x2=>Peripheral clock divided by 8
+// <0x3=>Peripheral clock divided by 16
+// <0x4=>Peripheral clock divided by 32
+// <0x5=>Peripheral clock divided by 64
+// <0x6=>Peripheral clock divided by 128
+// <0x7=>Peripheral clock divided by 256
+// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
+// <id> adc_prescaler
+#ifndef CONF_ADC_1_PRESCALER
+#define CONF_ADC_1_PRESCALER 0x2
+#endif
+
+// <q> Free Running Mode
+// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
+// <id> adc_freerunning_mode
+#ifndef CONF_ADC_1_FREERUN
+#define CONF_ADC_1_FREERUN 0
+#endif
+
+// <q> Differential Mode
+// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
+// <id> adc_differential_mode
+#ifndef CONF_ADC_1_DIFFMODE
+#define CONF_ADC_1_DIFFMODE 1
+#endif
+
+// <o> Positive Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x08=>ADC AIN8 pin
+// <0x09=>ADC AIN9 pin
+// <0x0A=>ADC AIN10 pin
+// <0x0B=>ADC AIN11 pin
+// <0x0C=>ADC AIN12 pin
+// <0x0D=>ADC AIN13 pin
+// <0x0E=>ADC AIN14 pin
+// <0x0F=>ADC AIN15 pin
+// <0x18=>1/4 scaled core supply
+// <0x19=>1/4 Scaled VBAT Supply
+// <0x1A=>1/4 scaled I/O supply
+// <0x1B=>Bandgap voltage
+// <0x1C=>Temperature reference (PTAT)
+// <0x1D=>Temperature reference (CTAT)
+// <0x1E=>DAC Output
+// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
+// <id> adc_pinmux_positive
+#ifndef CONF_ADC_1_MUXPOS
+#define CONF_ADC_1_MUXPOS 0x6
+#endif
+
+// <o> Negative Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x18=>Internal ground
+// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
+// <id> adc_pinmux_negative
+#ifndef CONF_ADC_1_MUXNEG
+#define CONF_ADC_1_MUXNEG 0x0
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> adc_advanced_settings
+#ifndef CONF_ADC_1_ADVANCED
+#define CONF_ADC_1_ADVANCED 1
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
+// <id> adc_arch_runstdby
+#ifndef CONF_ADC_1_RUNSTDBY
+#define CONF_ADC_1_RUNSTDBY 0
+#endif
+
+// <q>Debug Run
+// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
+// <id> adc_arch_dbgrun
+#ifndef CONF_ADC_1_DBGRUN
+#define CONF_ADC_1_DBGRUN 0
+#endif
+
+// <q> On Demand Control
+// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
+// <id> adc_arch_ondemand
+#ifndef CONF_ADC_1_ONDEMAND
+#define CONF_ADC_1_ONDEMAND 0
+#endif
+
+// <q> Left-Adjusted Result
+// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
+// <id> adc_arch_leftadj
+#ifndef CONF_ADC_1_LEFTADJ
+#define CONF_ADC_1_LEFTADJ 0
+#endif
+
+// <q> Reference Buffer Offset Compensation Enable
+// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
+// <id> adc_arch_refcomp
+#ifndef CONF_ADC_1_REFCOMP
+#define CONF_ADC_1_REFCOMP 0
+#endif
+
+// <q>Comparator Offset Compensation Enable
+// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
+// <id> adc_arch_offcomp
+#ifndef CONF_ADC_1_OFFCOMP
+#define CONF_ADC_1_OFFCOMP 0
+#endif
+
+// <q> Digital Correction Logic Enabled
+// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
+// <id> adc_arch_corren
+#ifndef CONF_ADC_1_CORREN
+#define CONF_ADC_1_CORREN 0
+#endif
+
+// <o> Offset Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
+// <id> adc_arch_offsetcorr
+#ifndef CONF_ADC_1_OFFSETCORR
+#define CONF_ADC_1_OFFSETCORR 0
+#endif
+
+// <o> Gain Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
+// <id> adc_arch_gaincorr
+#ifndef CONF_ADC_1_GAINCORR
+#define CONF_ADC_1_GAINCORR 0
+#endif
+
+// <o> Adjusting Result / Division Coefficient <0-7>
+// <i> These bits define the division coefficient in 2n steps. (ADJRES)
+// <id> adc_arch_adjres
+#ifndef CONF_ADC_1_ADJRES
+#define CONF_ADC_1_ADJRES 0x0
+#endif
+
+// <o.0..10> Number of Samples to be Collected
+// <0x0=>1 sample
+// <0x1=>2 samples
+// <0x2=>4 samples
+// <0x3=>8 samples
+// <0x4=>16 samples
+// <0x5=>32 samples
+// <0x6=>64 samples
+// <0x7=>128 samples
+// <0x8=>256 samples
+// <0x9=>512 samples
+// <0xA=>1024 samples
+// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
+// <id> adc_arch_samplenum
+#ifndef CONF_ADC_1_SAMPLENUM
+#define CONF_ADC_1_SAMPLENUM 0x0
+#endif
+
+// <o> Sampling Time Length <0-63>
+// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
+// <id> adc_arch_samplen
+#ifndef CONF_ADC_1_SAMPLEN
+#define CONF_ADC_1_SAMPLEN 2
+#endif
+
+// <o> Window Monitor Mode
+// <0x0=>No window mode
+// <0x1=>Mode 1: RESULT above lower threshold
+// <0x2=>Mode 2: RESULT beneath upper threshold
+// <0x3=>Mode 3: RESULT inside lower and upper threshold
+// <0x4=>Mode 4: RESULT outside lower and upper threshold
+// <i> These bits enable and define the window monitor mode. (WINMODE)
+// <id> adc_arch_winmode
+#ifndef CONF_ADC_1_WINMODE
+#define CONF_ADC_1_WINMODE 0x0
+#endif
+
+// <o> Window Monitor Lower Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
+// <id> adc_arch_winlt
+#ifndef CONF_ADC_1_WINLT
+#define CONF_ADC_1_WINLT 0
+#endif
+
+// <o> Window Monitor Upper Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
+// <id> adc_arch_winut
+#ifndef CONF_ADC_1_WINUT
+#define CONF_ADC_1_WINUT 0
+#endif
+
+// <o> Bitmask for positive input sequence <0-4294967295>
+// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
+// <id> adc_arch_seqen
+#ifndef CONF_ADC_1_SEQEN
+#define CONF_ADC_1_SEQEN 0x0
+#endif
+
+// </e>
+
+// <e> Event Control
+// <id> adc_arch_event_settings
+#ifndef CONF_ADC_1_EVENT_CONTROL
+#define CONF_ADC_1_EVENT_CONTROL 1
+#endif
+
+// <q> Window Monitor Event Out
+// <i> Enables event output on window event (WINMONEO)
+// <id> adc_arch_winmoneo
+#ifndef CONF_ADC_1_WINMONEO
+#define CONF_ADC_1_WINMONEO 0
+#endif
+
+// <q> Result Ready Event Out
+// <i> Enables event output on result ready event (RESRDEO)
+// <id> adc_arch_resrdyeo
+#ifndef CONF_ADC_1_RESRDYEO
+#define CONF_ADC_1_RESRDYEO 1
+#endif
+
+// <q> Invert flush Event Signal
+// <i> Invert the flush event input signal (FLUSHINV)
+// <id> adc_arch_flushinv
+#ifndef CONF_ADC_1_FLUSHINV
+#define CONF_ADC_1_FLUSHINV 0
+#endif
+
+// <q> Trigger Flush On Event
+// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
+// <id> adc_arch_flushei
+#ifndef CONF_ADC_1_FLUSHEI
+#define CONF_ADC_1_FLUSHEI 0
+#endif
+
+// <q> Invert Start Conversion Event Signal
+// <i> Invert the start conversion event input signal (STARTINV)
+// <id> adc_arch_startinv
+#ifndef CONF_ADC_1_STARTINV
+#define CONF_ADC_1_STARTINV 0
+#endif
+
+// <q> Trigger Conversion On Event
+// <i> Trigger a conversion on event. (STARTEI)
+// <id> adc_arch_startei
+#ifndef CONF_ADC_1_STARTEI
+#define CONF_ADC_1_STARTEI 0
+#endif
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_ADC_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_ccl_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_ccl_config.h
new file mode 100644
index 0000000..694e623
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_ccl_config.h
@@ -0,0 +1,499 @@
+/* Auto-generated config file hpl_ccl_config.h */
+#ifndef HPL_CCL_CONFIG_H
+#define HPL_CCL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <o> Sequential Control Logic 0
+// <0x0=> Sequential logic is disabled
+// <0x1=> D flip flop
+// <0x2=> JK flip flop
+// <0x3=> D latch
+// <0x4=> RS latch
+// <i> Selects mode for sequential module 0
+// <id> ccl_arch_seqsel_0
+#ifndef CONF_CCL_SEQSEL_0
+#define CONF_CCL_SEQSEL_0 0x0
+#endif
+
+// <o> Sequential Control Logic 1
+// <0x0=> Sequential logic is disabled
+// <0x1=> D flip flop
+// <0x2=> JK flip flop
+// <0x3=> D latch
+// <0x4=> RS latch
+// <i> Selects mode for sequential module 1
+// <id> ccl_arch_seqsel_1
+#ifndef CONF_CCL_SEQSEL_1
+#define CONF_CCL_SEQSEL_1 0x0
+#endif
+
+// <e> Lookup Table Control 0
+// <i> Enable and setup the lookup table module 0
+// <id> ccl_arch_lutctrl0
+#ifndef CONF_CCL_LUTCTRL_EN_0
+#define CONF_CCL_LUTCTRL_EN_0 1
+#endif
+
+// <o> Truth Table <0x00-0xFF>
+// <i> Define the value of truth logic according to inputs IN[2:0]
+// <id> ccl_arch_truth_0
+#ifndef CONF_CCL_TRUTH_0
+#define CONF_CCL_TRUTH_0 0x96
+#endif
+
+// <o> Input Source Selection 0
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel0_0
+#ifndef CONF_CCL_INSEL0_0
+#define CONF_CCL_INSEL0_0 0x4
+#endif
+
+// <o> Input Source Selection 1
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel1_0
+#ifndef CONF_CCL_INSEL1_0
+#define CONF_CCL_INSEL1_0 0x4
+#endif
+
+// <o> Input Source Selection 2
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel2_0
+#ifndef CONF_CCL_INSEL2_0
+#define CONF_CCL_INSEL2_0 0x4
+#endif
+
+// <q> Edge detector enable
+// <id> ccl_arch_edgesel_0
+#ifndef CONF_CCL_EDGESEL_0
+#define CONF_CCL_EDGESEL_0 0
+#endif
+
+// <o> Output Filter
+// <0x0=> Disabled
+// <0x1=> Synchronizer Enabled
+// <0x2=> Filter Enabled
+// <id> ccl_arch_filtsel_0
+#ifndef CONF_CCL_FILTSEL_0
+#define CONF_CCL_FILTSEL_0 0x0
+#endif
+
+// <h> Event settings 0
+
+// <q> Event output enable
+// <id> ccl_arch_luteo_0
+#ifndef CONF_CCL_LUTEO_0
+#define CONF_CCL_LUTEO_0 1
+#endif
+
+// <q> Event input enable
+// <id> ccl_arch_lutei_0
+#ifndef CONF_CCL_LUTEI_0
+#define CONF_CCL_LUTEI_0 0
+#endif
+
+// <q> Event input invert
+// <id> ccl_arch_invei_0
+#ifndef CONF_CCL_INVEI_0
+#define CONF_CCL_INVEI_0 0
+#endif
+
+// </h>
+
+// </e>
+
+// <hidden> Persistance settings 0
+
+// <s> Expression Persistance
+// <id> ccl_e_persistance_0
+#define EXPRESSION_PERSISTANCE_0 ""
+
+// <s> Logic Persistance
+// <id> ccl_l_persistance_0
+#define LOGIC_PERSISTANCE_0 ""
+
+// </hidden>
+
+// <e> Lookup Table Control 1
+// <i> Enable and setup the lookup table module 1
+// <id> ccl_arch_lutctrl1
+#ifndef CONF_CCL_LUTCTRL_EN_1
+#define CONF_CCL_LUTCTRL_EN_1 0
+#endif
+
+// <o> Truth Table <0x00-0xFF>
+// <i> Define the value of truth logic according to inputs IN[2:0]
+// <id> ccl_arch_truth_1
+#ifndef CONF_CCL_TRUTH_1
+#define CONF_CCL_TRUTH_1 0x0
+#endif
+
+// <o> Input Source Selection 0
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel0_1
+#ifndef CONF_CCL_INSEL0_1
+#define CONF_CCL_INSEL0_1 0x4
+#endif
+
+// <o> Input Source Selection 1
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel1_1
+#ifndef CONF_CCL_INSEL1_1
+#define CONF_CCL_INSEL1_1 0x4
+#endif
+
+// <o> Input Source Selection 2
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel2_1
+#ifndef CONF_CCL_INSEL2_1
+#define CONF_CCL_INSEL2_1 0x4
+#endif
+
+// <q> Edge detector enable
+// <id> ccl_arch_edgesel_1
+#ifndef CONF_CCL_EDGESEL_1
+#define CONF_CCL_EDGESEL_1 0
+#endif
+
+// <o> Output Filter
+// <0x0=> Disabled
+// <0x1=> Synchronizer Enabled
+// <0x2=> Filter Enabled
+// <id> ccl_arch_filtsel_1
+#ifndef CONF_CCL_FILTSEL_1
+#define CONF_CCL_FILTSEL_1 0x0
+#endif
+
+// <h> Event settings 1
+
+// <q> Event output enable
+// <id> ccl_arch_luteo_1
+#ifndef CONF_CCL_LUTEO_1
+#define CONF_CCL_LUTEO_1 0
+#endif
+
+// <q> Event input enable
+// <id> ccl_arch_lutei_1
+#ifndef CONF_CCL_LUTEI_1
+#define CONF_CCL_LUTEI_1 0
+#endif
+
+// <q> Event input invert
+// <id> ccl_arch_invei_1
+#ifndef CONF_CCL_INVEI_1
+#define CONF_CCL_INVEI_1 0
+#endif
+
+// </h>
+
+// </e>
+
+// <hidden> Persistance settings 1
+
+// <s> Expression Persistance
+// <id> ccl_e_persistance_1
+#define EXPRESSION_PERSISTANCE_1 ""
+
+// <s> Logic Persistance
+// <id> ccl_l_persistance_1
+#define LOGIC_PERSISTANCE_1 ""
+
+// </hidden>
+
+// <e> Lookup Table Control 2
+// <i> Enable and setup the lookup table module 2
+// <id> ccl_arch_lutctrl2
+#ifndef CONF_CCL_LUTCTRL_EN_2
+#define CONF_CCL_LUTCTRL_EN_2 1
+#endif
+
+// <o> Truth Table <0x00-0xFF>
+// <i> Define the value of truth logic according to inputs IN[2:0]
+// <id> ccl_arch_truth_2
+#ifndef CONF_CCL_TRUTH_2
+#define CONF_CCL_TRUTH_2 0x96
+#endif
+
+// <o> Input Source Selection 0
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel0_2
+#ifndef CONF_CCL_INSEL0_2
+#define CONF_CCL_INSEL0_2 0x4
+#endif
+
+// <o> Input Source Selection 1
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel1_2
+#ifndef CONF_CCL_INSEL1_2
+#define CONF_CCL_INSEL1_2 0x4
+#endif
+
+// <o> Input Source Selection 2
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel2_2
+#ifndef CONF_CCL_INSEL2_2
+#define CONF_CCL_INSEL2_2 0x4
+#endif
+
+// <q> Edge detector enable
+// <id> ccl_arch_edgesel_2
+#ifndef CONF_CCL_EDGESEL_2
+#define CONF_CCL_EDGESEL_2 0
+#endif
+
+// <o> Output Filter
+// <0x0=> Disabled
+// <0x1=> Synchronizer Enabled
+// <0x2=> Filter Enabled
+// <id> ccl_arch_filtsel_2
+#ifndef CONF_CCL_FILTSEL_2
+#define CONF_CCL_FILTSEL_2 0x0
+#endif
+
+// <h> Event settings 2
+
+// <q> Event output enable
+// <id> ccl_arch_luteo_2
+#ifndef CONF_CCL_LUTEO_2
+#define CONF_CCL_LUTEO_2 1
+#endif
+
+// <q> Event input enable
+// <id> ccl_arch_lutei_2
+#ifndef CONF_CCL_LUTEI_2
+#define CONF_CCL_LUTEI_2 0
+#endif
+
+// <q> Event input invert
+// <id> ccl_arch_invei_2
+#ifndef CONF_CCL_INVEI_2
+#define CONF_CCL_INVEI_2 0
+#endif
+
+// </h>
+
+// </e>
+
+// <hidden> Persistance settings 2
+
+// <s> Expression Persistance
+// <id> ccl_e_persistance_2
+#define EXPRESSION_PERSISTANCE_2 ""
+
+// <s> Logic Persistance
+// <id> ccl_l_persistance_2
+#define LOGIC_PERSISTANCE_2 ""
+
+// </hidden>
+
+// <e> Lookup Table Control 3
+// <i> Enable and setup the lookup table module 3
+// <id> ccl_arch_lutctrl3
+#ifndef CONF_CCL_LUTCTRL_EN_3
+#define CONF_CCL_LUTCTRL_EN_3 0
+#endif
+
+// <o> Truth Table <0x00-0xFF>
+// <i> Define the value of truth logic according to inputs IN[2:0]
+// <id> ccl_arch_truth_3
+#ifndef CONF_CCL_TRUTH_3
+#define CONF_CCL_TRUTH_3 0x0
+#endif
+
+// <o> Input Source Selection 0
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel0_3
+#ifndef CONF_CCL_INSEL0_3
+#define CONF_CCL_INSEL0_3 0x4
+#endif
+
+// <o> Input Source Selection 1
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel1_3
+#ifndef CONF_CCL_INSEL1_3
+#define CONF_CCL_INSEL1_3 0x4
+#endif
+
+// <o> Input Source Selection 2
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel2_3
+#ifndef CONF_CCL_INSEL2_3
+#define CONF_CCL_INSEL2_3 0x4
+#endif
+
+// <q> Edge detector enable
+// <id> ccl_arch_edgesel_3
+#ifndef CONF_CCL_EDGESEL_3
+#define CONF_CCL_EDGESEL_3 0
+#endif
+
+// <o> Output Filter
+// <0x0=> Disabled
+// <0x1=> Synchronizer Enabled
+// <0x2=> Filter Enabled
+// <id> ccl_arch_filtsel_3
+#ifndef CONF_CCL_FILTSEL_3
+#define CONF_CCL_FILTSEL_3 0x0
+#endif
+
+// <h> Event settings 3
+
+// <q> Event output enable
+// <id> ccl_arch_luteo_3
+#ifndef CONF_CCL_LUTEO_3
+#define CONF_CCL_LUTEO_3 0
+#endif
+
+// <q> Event input enable
+// <id> ccl_arch_lutei_3
+#ifndef CONF_CCL_LUTEI_3
+#define CONF_CCL_LUTEI_3 0
+#endif
+
+// <q> Event input invert
+// <id> ccl_arch_invei_3
+#ifndef CONF_CCL_INVEI_3
+#define CONF_CCL_INVEI_3 0
+#endif
+
+// </h>
+
+// </e>
+
+// <hidden> Persistance settings 3
+
+// <s> Expression Persistance
+// <id> ccl_e_persistance_3
+#define EXPRESSION_PERSISTANCE_3 ""
+
+// <s> Logic Persistance
+// <id> ccl_l_persistance_3
+#define LOGIC_PERSISTANCE_3 ""
+
+// </hidden>
+
+// <e> Advanced configurations
+// <id> ccl_arch_advanced_settings
+#ifndef CONF_CCL_ADVANCED
+#define CONF_CCL_ADVANCED 0
+#endif
+
+// <q> Run in Standby
+// <id> ccl_arch_runstdby
+#ifndef CONF_CCL_RUNSTDBY
+#define CONF_CCL_RUNSTDBY 0
+#endif
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_CCL_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_cmcc_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_cmcc_config.h
new file mode 100644
index 0000000..8590736
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_cmcc_config.h
@@ -0,0 +1,54 @@
+/* Auto-generated config file hpl_cmcc_config.h */
+#ifndef HPL_CMCC_CONFIG_H
+#define HPL_CMCC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic Configuration
+
+// <q> Cache enable
+//<i> Defines the cache should be enabled or not.
+// <id> cmcc_enable
+#ifndef CONF_CMCC_ENABLE
+#define CONF_CMCC_ENABLE 0x0
+#endif
+
+// <o> Cache Size
+//<i> Defines the cache memory size to be configured.
+// <0x0=>1 KB
+// <0x1=>2 KB
+// <0x2=>4 KB
+// <id> cache_size
+#ifndef CONF_CMCC_CACHE_SIZE
+#define CONF_CMCC_CACHE_SIZE 0x2
+#endif
+
+// <e> Advanced Configuration
+// <id> cmcc_advanced_configuration
+// <q> Data cache disable
+//<i> Defines the data cache should be disabled or not.
+// <id> cmcc_data_cache_disable
+#ifndef CONF_CMCC_DATA_CACHE_DISABLE
+#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
+#endif
+
+// <q> Instruction cache disable
+//<i> Defines the Instruction cache should be disabled or not.
+// <id> cmcc_inst_cache_disable
+#ifndef CONF_CMCC_INST_CACHE_DISABLE
+#define CONF_CMCC_INST_CACHE_DISABLE 0x0
+#endif
+
+// <q> Clock Gating disable
+//<i> Defines the clock gating should be disabled or not.
+// <id> cmcc_clock_gating_disable
+#ifndef CONF_CMCC_CLK_GATING_DISABLE
+#define CONF_CMCC_CLK_GATING_DISABLE 0x0
+#endif
+
+// </e>
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_CMCC_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_dmac_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_dmac_config.h
new file mode 100644
index 0000000..dbbe6bf
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_dmac_config.h
@@ -0,0 +1,7277 @@
+/* Auto-generated config file hpl_dmac_config.h */
+#ifndef HPL_DMAC_CONFIG_H
+#define HPL_DMAC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> DMAC enable
+// <i> Indicates whether dmac is enabled or not
+// <id> dmac_enable
+#ifndef CONF_DMAC_ENABLE
+#define CONF_DMAC_ENABLE 1
+#endif
+
+// <q> Priority Level 0
+// <i> Indicates whether Priority Level 0 is enabled or not
+// <id> dmac_lvlen0
+#ifndef CONF_DMAC_LVLEN0
+#define CONF_DMAC_LVLEN0 1
+#endif
+
+// <o> Level 0 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 0
+// <1=> Round-robin arbitration scheme for channel with priority 0
+// <i> Defines Level 0 Arbitration for DMA channels
+// <id> dmac_rrlvlen0
+#ifndef CONF_DMAC_RRLVLEN0
+#define CONF_DMAC_RRLVLEN0 0
+#endif
+
+// <o> Level 0 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri0
+#ifndef CONF_DMAC_LVLPRI0
+#define CONF_DMAC_LVLPRI0 0
+#endif
+// <q> Priority Level 1
+// <i> Indicates whether Priority Level 1 is enabled or not
+// <id> dmac_lvlen1
+#ifndef CONF_DMAC_LVLEN1
+#define CONF_DMAC_LVLEN1 0
+#endif
+
+// <o> Level 1 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 1
+// <1=> Round-robin arbitration scheme for channel with priority 1
+// <i> Defines Level 1 Arbitration for DMA channels
+// <id> dmac_rrlvlen1
+#ifndef CONF_DMAC_RRLVLEN1
+#define CONF_DMAC_RRLVLEN1 0
+#endif
+
+// <o> Level 1 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri1
+#ifndef CONF_DMAC_LVLPRI1
+#define CONF_DMAC_LVLPRI1 0
+#endif
+// <q> Priority Level 2
+// <i> Indicates whether Priority Level 2 is enabled or not
+// <id> dmac_lvlen2
+#ifndef CONF_DMAC_LVLEN2
+#define CONF_DMAC_LVLEN2 0
+#endif
+
+// <o> Level 2 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 2
+// <1=> Round-robin arbitration scheme for channel with priority 2
+// <i> Defines Level 2 Arbitration for DMA channels
+// <id> dmac_rrlvlen2
+#ifndef CONF_DMAC_RRLVLEN2
+#define CONF_DMAC_RRLVLEN2 0
+#endif
+
+// <o> Level 2 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri2
+#ifndef CONF_DMAC_LVLPRI2
+#define CONF_DMAC_LVLPRI2 0
+#endif
+// <q> Priority Level 3
+// <i> Indicates whether Priority Level 3 is enabled or not
+// <id> dmac_lvlen3
+#ifndef CONF_DMAC_LVLEN3
+#define CONF_DMAC_LVLEN3 0
+#endif
+
+// <o> Level 3 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 3
+// <1=> Round-robin arbitration scheme for channel with priority 3
+// <i> Defines Level 3 Arbitration for DMA channels
+// <id> dmac_rrlvlen3
+#ifndef CONF_DMAC_RRLVLEN3
+#define CONF_DMAC_RRLVLEN3 0
+#endif
+
+// <o> Level 3 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri3
+#ifndef CONF_DMAC_LVLPRI3
+#define CONF_DMAC_LVLPRI3 0
+#endif
+// <q> Debug Run
+// <i> Indicates whether Debug Run is enabled or not
+// <id> dmac_dbgrun
+#ifndef CONF_DMAC_DBGRUN
+#define CONF_DMAC_DBGRUN 0
+#endif
+
+// <e> Channel 0 settings
+// <id> dmac_channel_0_settings
+#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
+#define CONF_DMAC_CHANNEL_0_SETTINGS 1
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 0 is running in standby mode or not
+// <id> dmac_runstdby_0
+#ifndef CONF_DMAC_RUNSTDBY_0
+#define CONF_DMAC_RUNSTDBY_0 1
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_0
+#ifndef CONF_DMAC_TRIGACT_0
+#define CONF_DMAC_TRIGACT_0 2
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_0
+#ifndef CONF_DMAC_TRIGSRC_0
+#define CONF_DMAC_TRIGSRC_0 6
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_0
+#ifndef CONF_DMAC_LVL_0
+#define CONF_DMAC_LVL_0 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_0
+#ifndef CONF_DMAC_EVOE_0
+#define CONF_DMAC_EVOE_0 1
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_0
+#ifndef CONF_DMAC_EVIE_0
+#define CONF_DMAC_EVIE_0 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_0
+#ifndef CONF_DMAC_EVACT_0
+#define CONF_DMAC_EVACT_0 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_0
+#ifndef CONF_DMAC_STEPSIZE_0
+#define CONF_DMAC_STEPSIZE_0 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_0
+#ifndef CONF_DMAC_STEPSEL_0
+#define CONF_DMAC_STEPSEL_0 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_0
+#ifndef CONF_DMAC_SRCINC_0
+#define CONF_DMAC_SRCINC_0 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_0
+#ifndef CONF_DMAC_DSTINC_0
+#define CONF_DMAC_DSTINC_0 1
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_0
+#ifndef CONF_DMAC_BEATSIZE_0
+#define CONF_DMAC_BEATSIZE_0 2
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_0
+#ifndef CONF_DMAC_BLOCKACT_0
+#define CONF_DMAC_BLOCKACT_0 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_0
+#ifndef CONF_DMAC_EVOSEL_0
+#define CONF_DMAC_EVOSEL_0 1
+#endif
+// </e>
+
+// <e> Channel 1 settings
+// <id> dmac_channel_1_settings
+#ifndef CONF_DMAC_CHANNEL_1_SETTINGS
+#define CONF_DMAC_CHANNEL_1_SETTINGS 1
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 1 is running in standby mode or not
+// <id> dmac_runstdby_1
+#ifndef CONF_DMAC_RUNSTDBY_1
+#define CONF_DMAC_RUNSTDBY_1 1
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_1
+#ifndef CONF_DMAC_TRIGACT_1
+#define CONF_DMAC_TRIGACT_1 2
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_1
+#ifndef CONF_DMAC_TRIGSRC_1
+#define CONF_DMAC_TRIGSRC_1 14
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_1
+#ifndef CONF_DMAC_LVL_1
+#define CONF_DMAC_LVL_1 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_1
+#ifndef CONF_DMAC_EVOE_1
+#define CONF_DMAC_EVOE_1 1
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_1
+#ifndef CONF_DMAC_EVIE_1
+#define CONF_DMAC_EVIE_1 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_1
+#ifndef CONF_DMAC_EVACT_1
+#define CONF_DMAC_EVACT_1 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_1
+#ifndef CONF_DMAC_STEPSIZE_1
+#define CONF_DMAC_STEPSIZE_1 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_1
+#ifndef CONF_DMAC_STEPSEL_1
+#define CONF_DMAC_STEPSEL_1 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_1
+#ifndef CONF_DMAC_SRCINC_1
+#define CONF_DMAC_SRCINC_1 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_1
+#ifndef CONF_DMAC_DSTINC_1
+#define CONF_DMAC_DSTINC_1 1
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_1
+#ifndef CONF_DMAC_BEATSIZE_1
+#define CONF_DMAC_BEATSIZE_1 2
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_1
+#ifndef CONF_DMAC_BLOCKACT_1
+#define CONF_DMAC_BLOCKACT_1 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_1
+#ifndef CONF_DMAC_EVOSEL_1
+#define CONF_DMAC_EVOSEL_1 1
+#endif
+// </e>
+
+// <e> Channel 2 settings
+// <id> dmac_channel_2_settings
+#ifndef CONF_DMAC_CHANNEL_2_SETTINGS
+#define CONF_DMAC_CHANNEL_2_SETTINGS 1
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 2 is running in standby mode or not
+// <id> dmac_runstdby_2
+#ifndef CONF_DMAC_RUNSTDBY_2
+#define CONF_DMAC_RUNSTDBY_2 1
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_2
+#ifndef CONF_DMAC_TRIGACT_2
+#define CONF_DMAC_TRIGACT_2 2
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_2
+#ifndef CONF_DMAC_TRIGSRC_2
+#define CONF_DMAC_TRIGSRC_2 8
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_2
+#ifndef CONF_DMAC_LVL_2
+#define CONF_DMAC_LVL_2 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_2
+#ifndef CONF_DMAC_EVOE_2
+#define CONF_DMAC_EVOE_2 1
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_2
+#ifndef CONF_DMAC_EVIE_2
+#define CONF_DMAC_EVIE_2 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_2
+#ifndef CONF_DMAC_EVACT_2
+#define CONF_DMAC_EVACT_2 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_2
+#ifndef CONF_DMAC_STEPSIZE_2
+#define CONF_DMAC_STEPSIZE_2 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_2
+#ifndef CONF_DMAC_STEPSEL_2
+#define CONF_DMAC_STEPSEL_2 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_2
+#ifndef CONF_DMAC_SRCINC_2
+#define CONF_DMAC_SRCINC_2 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_2
+#ifndef CONF_DMAC_DSTINC_2
+#define CONF_DMAC_DSTINC_2 1
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_2
+#ifndef CONF_DMAC_BEATSIZE_2
+#define CONF_DMAC_BEATSIZE_2 2
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_2
+#ifndef CONF_DMAC_BLOCKACT_2
+#define CONF_DMAC_BLOCKACT_2 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_2
+#ifndef CONF_DMAC_EVOSEL_2
+#define CONF_DMAC_EVOSEL_2 1
+#endif
+// </e>
+
+// <e> Channel 3 settings
+// <id> dmac_channel_3_settings
+#ifndef CONF_DMAC_CHANNEL_3_SETTINGS
+#define CONF_DMAC_CHANNEL_3_SETTINGS 1
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 3 is running in standby mode or not
+// <id> dmac_runstdby_3
+#ifndef CONF_DMAC_RUNSTDBY_3
+#define CONF_DMAC_RUNSTDBY_3 1
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_3
+#ifndef CONF_DMAC_TRIGACT_3
+#define CONF_DMAC_TRIGACT_3 2
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_3
+#ifndef CONF_DMAC_TRIGSRC_3
+#define CONF_DMAC_TRIGSRC_3 70
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_3
+#ifndef CONF_DMAC_LVL_3
+#define CONF_DMAC_LVL_3 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_3
+#ifndef CONF_DMAC_EVOE_3
+#define CONF_DMAC_EVOE_3 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_3
+#ifndef CONF_DMAC_EVIE_3
+#define CONF_DMAC_EVIE_3 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_3
+#ifndef CONF_DMAC_EVACT_3
+#define CONF_DMAC_EVACT_3 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_3
+#ifndef CONF_DMAC_STEPSIZE_3
+#define CONF_DMAC_STEPSIZE_3 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_3
+#ifndef CONF_DMAC_STEPSEL_3
+#define CONF_DMAC_STEPSEL_3 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_3
+#ifndef CONF_DMAC_SRCINC_3
+#define CONF_DMAC_SRCINC_3 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_3
+#ifndef CONF_DMAC_DSTINC_3
+#define CONF_DMAC_DSTINC_3 1
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_3
+#ifndef CONF_DMAC_BEATSIZE_3
+#define CONF_DMAC_BEATSIZE_3 1
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_3
+#ifndef CONF_DMAC_BLOCKACT_3
+#define CONF_DMAC_BLOCKACT_3 1
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_3
+#ifndef CONF_DMAC_EVOSEL_3
+#define CONF_DMAC_EVOSEL_3 0
+#endif
+// </e>
+
+// <e> Channel 4 settings
+// <id> dmac_channel_4_settings
+#ifndef CONF_DMAC_CHANNEL_4_SETTINGS
+#define CONF_DMAC_CHANNEL_4_SETTINGS 1
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 4 is running in standby mode or not
+// <id> dmac_runstdby_4
+#ifndef CONF_DMAC_RUNSTDBY_4
+#define CONF_DMAC_RUNSTDBY_4 1
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_4
+#ifndef CONF_DMAC_TRIGACT_4
+#define CONF_DMAC_TRIGACT_4 2
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_4
+#ifndef CONF_DMAC_TRIGSRC_4
+#define CONF_DMAC_TRIGSRC_4 71
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_4
+#ifndef CONF_DMAC_LVL_4
+#define CONF_DMAC_LVL_4 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_4
+#ifndef CONF_DMAC_EVOE_4
+#define CONF_DMAC_EVOE_4 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_4
+#ifndef CONF_DMAC_EVIE_4
+#define CONF_DMAC_EVIE_4 1
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_4
+#ifndef CONF_DMAC_EVACT_4
+#define CONF_DMAC_EVACT_4 5
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_4
+#ifndef CONF_DMAC_STEPSIZE_4
+#define CONF_DMAC_STEPSIZE_4 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_4
+#ifndef CONF_DMAC_STEPSEL_4
+#define CONF_DMAC_STEPSEL_4 1
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_4
+#ifndef CONF_DMAC_SRCINC_4
+#define CONF_DMAC_SRCINC_4 1
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_4
+#ifndef CONF_DMAC_DSTINC_4
+#define CONF_DMAC_DSTINC_4 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_4
+#ifndef CONF_DMAC_BEATSIZE_4
+#define CONF_DMAC_BEATSIZE_4 2
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_4
+#ifndef CONF_DMAC_BLOCKACT_4
+#define CONF_DMAC_BLOCKACT_4 2
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_4
+#ifndef CONF_DMAC_EVOSEL_4
+#define CONF_DMAC_EVOSEL_4 0
+#endif
+// </e>
+
+// <e> Channel 5 settings
+// <id> dmac_channel_5_settings
+#ifndef CONF_DMAC_CHANNEL_5_SETTINGS
+#define CONF_DMAC_CHANNEL_5_SETTINGS 1
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 5 is running in standby mode or not
+// <id> dmac_runstdby_5
+#ifndef CONF_DMAC_RUNSTDBY_5
+#define CONF_DMAC_RUNSTDBY_5 1
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_5
+#ifndef CONF_DMAC_TRIGACT_5
+#define CONF_DMAC_TRIGACT_5 2
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_5
+#ifndef CONF_DMAC_TRIGSRC_5
+#define CONF_DMAC_TRIGSRC_5 9
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_5
+#ifndef CONF_DMAC_LVL_5
+#define CONF_DMAC_LVL_5 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_5
+#ifndef CONF_DMAC_EVOE_5
+#define CONF_DMAC_EVOE_5 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_5
+#ifndef CONF_DMAC_EVIE_5
+#define CONF_DMAC_EVIE_5 1
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_5
+#ifndef CONF_DMAC_EVACT_5
+#define CONF_DMAC_EVACT_5 5
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_5
+#ifndef CONF_DMAC_STEPSIZE_5
+#define CONF_DMAC_STEPSIZE_5 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_5
+#ifndef CONF_DMAC_STEPSEL_5
+#define CONF_DMAC_STEPSEL_5 1
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_5
+#ifndef CONF_DMAC_SRCINC_5
+#define CONF_DMAC_SRCINC_5 1
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_5
+#ifndef CONF_DMAC_DSTINC_5
+#define CONF_DMAC_DSTINC_5 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_5
+#ifndef CONF_DMAC_BEATSIZE_5
+#define CONF_DMAC_BEATSIZE_5 2
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_5
+#ifndef CONF_DMAC_BLOCKACT_5
+#define CONF_DMAC_BLOCKACT_5 2
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_5
+#ifndef CONF_DMAC_EVOSEL_5
+#define CONF_DMAC_EVOSEL_5 0
+#endif
+// </e>
+
+// <e> Channel 6 settings
+// <id> dmac_channel_6_settings
+#ifndef CONF_DMAC_CHANNEL_6_SETTINGS
+#define CONF_DMAC_CHANNEL_6_SETTINGS 1
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 6 is running in standby mode or not
+// <id> dmac_runstdby_6
+#ifndef CONF_DMAC_RUNSTDBY_6
+#define CONF_DMAC_RUNSTDBY_6 1
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_6
+#ifndef CONF_DMAC_TRIGACT_6
+#define CONF_DMAC_TRIGACT_6 2
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_6
+#ifndef CONF_DMAC_TRIGSRC_6
+#define CONF_DMAC_TRIGSRC_6 15
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_6
+#ifndef CONF_DMAC_LVL_6
+#define CONF_DMAC_LVL_6 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_6
+#ifndef CONF_DMAC_EVOE_6
+#define CONF_DMAC_EVOE_6 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_6
+#ifndef CONF_DMAC_EVIE_6
+#define CONF_DMAC_EVIE_6 1
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_6
+#ifndef CONF_DMAC_EVACT_6
+#define CONF_DMAC_EVACT_6 5
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_6
+#ifndef CONF_DMAC_STEPSIZE_6
+#define CONF_DMAC_STEPSIZE_6 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_6
+#ifndef CONF_DMAC_STEPSEL_6
+#define CONF_DMAC_STEPSEL_6 1
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_6
+#ifndef CONF_DMAC_SRCINC_6
+#define CONF_DMAC_SRCINC_6 1
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_6
+#ifndef CONF_DMAC_DSTINC_6
+#define CONF_DMAC_DSTINC_6 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_6
+#ifndef CONF_DMAC_BEATSIZE_6
+#define CONF_DMAC_BEATSIZE_6 2
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_6
+#ifndef CONF_DMAC_BLOCKACT_6
+#define CONF_DMAC_BLOCKACT_6 2
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_6
+#ifndef CONF_DMAC_EVOSEL_6
+#define CONF_DMAC_EVOSEL_6 0
+#endif
+// </e>
+
+// <e> Channel 7 settings
+// <id> dmac_channel_7_settings
+#ifndef CONF_DMAC_CHANNEL_7_SETTINGS
+#define CONF_DMAC_CHANNEL_7_SETTINGS 1
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 7 is running in standby mode or not
+// <id> dmac_runstdby_7
+#ifndef CONF_DMAC_RUNSTDBY_7
+#define CONF_DMAC_RUNSTDBY_7 1
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_7
+#ifndef CONF_DMAC_TRIGACT_7
+#define CONF_DMAC_TRIGACT_7 2
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_7
+#ifndef CONF_DMAC_TRIGSRC_7
+#define CONF_DMAC_TRIGSRC_7 7
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_7
+#ifndef CONF_DMAC_LVL_7
+#define CONF_DMAC_LVL_7 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_7
+#ifndef CONF_DMAC_EVOE_7
+#define CONF_DMAC_EVOE_7 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_7
+#ifndef CONF_DMAC_EVIE_7
+#define CONF_DMAC_EVIE_7 1
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_7
+#ifndef CONF_DMAC_EVACT_7
+#define CONF_DMAC_EVACT_7 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_7
+#ifndef CONF_DMAC_STEPSIZE_7
+#define CONF_DMAC_STEPSIZE_7 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_7
+#ifndef CONF_DMAC_STEPSEL_7
+#define CONF_DMAC_STEPSEL_7 1
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_7
+#ifndef CONF_DMAC_SRCINC_7
+#define CONF_DMAC_SRCINC_7 1
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_7
+#ifndef CONF_DMAC_DSTINC_7
+#define CONF_DMAC_DSTINC_7 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_7
+#ifndef CONF_DMAC_BEATSIZE_7
+#define CONF_DMAC_BEATSIZE_7 2
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_7
+#ifndef CONF_DMAC_BLOCKACT_7
+#define CONF_DMAC_BLOCKACT_7 2
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_7
+#ifndef CONF_DMAC_EVOSEL_7
+#define CONF_DMAC_EVOSEL_7 0
+#endif
+// </e>
+
+// <e> Channel 8 settings
+// <id> dmac_channel_8_settings
+#ifndef CONF_DMAC_CHANNEL_8_SETTINGS
+#define CONF_DMAC_CHANNEL_8_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 8 is running in standby mode or not
+// <id> dmac_runstdby_8
+#ifndef CONF_DMAC_RUNSTDBY_8
+#define CONF_DMAC_RUNSTDBY_8 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_8
+#ifndef CONF_DMAC_TRIGACT_8
+#define CONF_DMAC_TRIGACT_8 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_8
+#ifndef CONF_DMAC_TRIGSRC_8
+#define CONF_DMAC_TRIGSRC_8 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_8
+#ifndef CONF_DMAC_LVL_8
+#define CONF_DMAC_LVL_8 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_8
+#ifndef CONF_DMAC_EVOE_8
+#define CONF_DMAC_EVOE_8 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_8
+#ifndef CONF_DMAC_EVIE_8
+#define CONF_DMAC_EVIE_8 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_8
+#ifndef CONF_DMAC_EVACT_8
+#define CONF_DMAC_EVACT_8 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_8
+#ifndef CONF_DMAC_STEPSIZE_8
+#define CONF_DMAC_STEPSIZE_8 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_8
+#ifndef CONF_DMAC_STEPSEL_8
+#define CONF_DMAC_STEPSEL_8 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_8
+#ifndef CONF_DMAC_SRCINC_8
+#define CONF_DMAC_SRCINC_8 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_8
+#ifndef CONF_DMAC_DSTINC_8
+#define CONF_DMAC_DSTINC_8 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_8
+#ifndef CONF_DMAC_BEATSIZE_8
+#define CONF_DMAC_BEATSIZE_8 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_8
+#ifndef CONF_DMAC_BLOCKACT_8
+#define CONF_DMAC_BLOCKACT_8 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_8
+#ifndef CONF_DMAC_EVOSEL_8
+#define CONF_DMAC_EVOSEL_8 0
+#endif
+// </e>
+
+// <e> Channel 9 settings
+// <id> dmac_channel_9_settings
+#ifndef CONF_DMAC_CHANNEL_9_SETTINGS
+#define CONF_DMAC_CHANNEL_9_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 9 is running in standby mode or not
+// <id> dmac_runstdby_9
+#ifndef CONF_DMAC_RUNSTDBY_9
+#define CONF_DMAC_RUNSTDBY_9 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_9
+#ifndef CONF_DMAC_TRIGACT_9
+#define CONF_DMAC_TRIGACT_9 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_9
+#ifndef CONF_DMAC_TRIGSRC_9
+#define CONF_DMAC_TRIGSRC_9 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_9
+#ifndef CONF_DMAC_LVL_9
+#define CONF_DMAC_LVL_9 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_9
+#ifndef CONF_DMAC_EVOE_9
+#define CONF_DMAC_EVOE_9 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_9
+#ifndef CONF_DMAC_EVIE_9
+#define CONF_DMAC_EVIE_9 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_9
+#ifndef CONF_DMAC_EVACT_9
+#define CONF_DMAC_EVACT_9 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_9
+#ifndef CONF_DMAC_STEPSIZE_9
+#define CONF_DMAC_STEPSIZE_9 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_9
+#ifndef CONF_DMAC_STEPSEL_9
+#define CONF_DMAC_STEPSEL_9 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_9
+#ifndef CONF_DMAC_SRCINC_9
+#define CONF_DMAC_SRCINC_9 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_9
+#ifndef CONF_DMAC_DSTINC_9
+#define CONF_DMAC_DSTINC_9 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_9
+#ifndef CONF_DMAC_BEATSIZE_9
+#define CONF_DMAC_BEATSIZE_9 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_9
+#ifndef CONF_DMAC_BLOCKACT_9
+#define CONF_DMAC_BLOCKACT_9 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_9
+#ifndef CONF_DMAC_EVOSEL_9
+#define CONF_DMAC_EVOSEL_9 0
+#endif
+// </e>
+
+// <e> Channel 10 settings
+// <id> dmac_channel_10_settings
+#ifndef CONF_DMAC_CHANNEL_10_SETTINGS
+#define CONF_DMAC_CHANNEL_10_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 10 is running in standby mode or not
+// <id> dmac_runstdby_10
+#ifndef CONF_DMAC_RUNSTDBY_10
+#define CONF_DMAC_RUNSTDBY_10 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_10
+#ifndef CONF_DMAC_TRIGACT_10
+#define CONF_DMAC_TRIGACT_10 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_10
+#ifndef CONF_DMAC_TRIGSRC_10
+#define CONF_DMAC_TRIGSRC_10 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_10
+#ifndef CONF_DMAC_LVL_10
+#define CONF_DMAC_LVL_10 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_10
+#ifndef CONF_DMAC_EVOE_10
+#define CONF_DMAC_EVOE_10 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_10
+#ifndef CONF_DMAC_EVIE_10
+#define CONF_DMAC_EVIE_10 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_10
+#ifndef CONF_DMAC_EVACT_10
+#define CONF_DMAC_EVACT_10 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_10
+#ifndef CONF_DMAC_STEPSIZE_10
+#define CONF_DMAC_STEPSIZE_10 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_10
+#ifndef CONF_DMAC_STEPSEL_10
+#define CONF_DMAC_STEPSEL_10 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_10
+#ifndef CONF_DMAC_SRCINC_10
+#define CONF_DMAC_SRCINC_10 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_10
+#ifndef CONF_DMAC_DSTINC_10
+#define CONF_DMAC_DSTINC_10 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_10
+#ifndef CONF_DMAC_BEATSIZE_10
+#define CONF_DMAC_BEATSIZE_10 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_10
+#ifndef CONF_DMAC_BLOCKACT_10
+#define CONF_DMAC_BLOCKACT_10 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_10
+#ifndef CONF_DMAC_EVOSEL_10
+#define CONF_DMAC_EVOSEL_10 0
+#endif
+// </e>
+
+// <e> Channel 11 settings
+// <id> dmac_channel_11_settings
+#ifndef CONF_DMAC_CHANNEL_11_SETTINGS
+#define CONF_DMAC_CHANNEL_11_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 11 is running in standby mode or not
+// <id> dmac_runstdby_11
+#ifndef CONF_DMAC_RUNSTDBY_11
+#define CONF_DMAC_RUNSTDBY_11 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_11
+#ifndef CONF_DMAC_TRIGACT_11
+#define CONF_DMAC_TRIGACT_11 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_11
+#ifndef CONF_DMAC_TRIGSRC_11
+#define CONF_DMAC_TRIGSRC_11 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_11
+#ifndef CONF_DMAC_LVL_11
+#define CONF_DMAC_LVL_11 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_11
+#ifndef CONF_DMAC_EVOE_11
+#define CONF_DMAC_EVOE_11 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_11
+#ifndef CONF_DMAC_EVIE_11
+#define CONF_DMAC_EVIE_11 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_11
+#ifndef CONF_DMAC_EVACT_11
+#define CONF_DMAC_EVACT_11 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_11
+#ifndef CONF_DMAC_STEPSIZE_11
+#define CONF_DMAC_STEPSIZE_11 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_11
+#ifndef CONF_DMAC_STEPSEL_11
+#define CONF_DMAC_STEPSEL_11 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_11
+#ifndef CONF_DMAC_SRCINC_11
+#define CONF_DMAC_SRCINC_11 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_11
+#ifndef CONF_DMAC_DSTINC_11
+#define CONF_DMAC_DSTINC_11 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_11
+#ifndef CONF_DMAC_BEATSIZE_11
+#define CONF_DMAC_BEATSIZE_11 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_11
+#ifndef CONF_DMAC_BLOCKACT_11
+#define CONF_DMAC_BLOCKACT_11 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_11
+#ifndef CONF_DMAC_EVOSEL_11
+#define CONF_DMAC_EVOSEL_11 0
+#endif
+// </e>
+
+// <e> Channel 12 settings
+// <id> dmac_channel_12_settings
+#ifndef CONF_DMAC_CHANNEL_12_SETTINGS
+#define CONF_DMAC_CHANNEL_12_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 12 is running in standby mode or not
+// <id> dmac_runstdby_12
+#ifndef CONF_DMAC_RUNSTDBY_12
+#define CONF_DMAC_RUNSTDBY_12 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_12
+#ifndef CONF_DMAC_TRIGACT_12
+#define CONF_DMAC_TRIGACT_12 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_12
+#ifndef CONF_DMAC_TRIGSRC_12
+#define CONF_DMAC_TRIGSRC_12 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_12
+#ifndef CONF_DMAC_LVL_12
+#define CONF_DMAC_LVL_12 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_12
+#ifndef CONF_DMAC_EVOE_12
+#define CONF_DMAC_EVOE_12 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_12
+#ifndef CONF_DMAC_EVIE_12
+#define CONF_DMAC_EVIE_12 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_12
+#ifndef CONF_DMAC_EVACT_12
+#define CONF_DMAC_EVACT_12 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_12
+#ifndef CONF_DMAC_STEPSIZE_12
+#define CONF_DMAC_STEPSIZE_12 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_12
+#ifndef CONF_DMAC_STEPSEL_12
+#define CONF_DMAC_STEPSEL_12 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_12
+#ifndef CONF_DMAC_SRCINC_12
+#define CONF_DMAC_SRCINC_12 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_12
+#ifndef CONF_DMAC_DSTINC_12
+#define CONF_DMAC_DSTINC_12 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_12
+#ifndef CONF_DMAC_BEATSIZE_12
+#define CONF_DMAC_BEATSIZE_12 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_12
+#ifndef CONF_DMAC_BLOCKACT_12
+#define CONF_DMAC_BLOCKACT_12 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_12
+#ifndef CONF_DMAC_EVOSEL_12
+#define CONF_DMAC_EVOSEL_12 0
+#endif
+// </e>
+
+// <e> Channel 13 settings
+// <id> dmac_channel_13_settings
+#ifndef CONF_DMAC_CHANNEL_13_SETTINGS
+#define CONF_DMAC_CHANNEL_13_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 13 is running in standby mode or not
+// <id> dmac_runstdby_13
+#ifndef CONF_DMAC_RUNSTDBY_13
+#define CONF_DMAC_RUNSTDBY_13 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_13
+#ifndef CONF_DMAC_TRIGACT_13
+#define CONF_DMAC_TRIGACT_13 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_13
+#ifndef CONF_DMAC_TRIGSRC_13
+#define CONF_DMAC_TRIGSRC_13 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_13
+#ifndef CONF_DMAC_LVL_13
+#define CONF_DMAC_LVL_13 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_13
+#ifndef CONF_DMAC_EVOE_13
+#define CONF_DMAC_EVOE_13 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_13
+#ifndef CONF_DMAC_EVIE_13
+#define CONF_DMAC_EVIE_13 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_13
+#ifndef CONF_DMAC_EVACT_13
+#define CONF_DMAC_EVACT_13 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_13
+#ifndef CONF_DMAC_STEPSIZE_13
+#define CONF_DMAC_STEPSIZE_13 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_13
+#ifndef CONF_DMAC_STEPSEL_13
+#define CONF_DMAC_STEPSEL_13 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_13
+#ifndef CONF_DMAC_SRCINC_13
+#define CONF_DMAC_SRCINC_13 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_13
+#ifndef CONF_DMAC_DSTINC_13
+#define CONF_DMAC_DSTINC_13 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_13
+#ifndef CONF_DMAC_BEATSIZE_13
+#define CONF_DMAC_BEATSIZE_13 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_13
+#ifndef CONF_DMAC_BLOCKACT_13
+#define CONF_DMAC_BLOCKACT_13 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_13
+#ifndef CONF_DMAC_EVOSEL_13
+#define CONF_DMAC_EVOSEL_13 0
+#endif
+// </e>
+
+// <e> Channel 14 settings
+// <id> dmac_channel_14_settings
+#ifndef CONF_DMAC_CHANNEL_14_SETTINGS
+#define CONF_DMAC_CHANNEL_14_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 14 is running in standby mode or not
+// <id> dmac_runstdby_14
+#ifndef CONF_DMAC_RUNSTDBY_14
+#define CONF_DMAC_RUNSTDBY_14 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_14
+#ifndef CONF_DMAC_TRIGACT_14
+#define CONF_DMAC_TRIGACT_14 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_14
+#ifndef CONF_DMAC_TRIGSRC_14
+#define CONF_DMAC_TRIGSRC_14 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_14
+#ifndef CONF_DMAC_LVL_14
+#define CONF_DMAC_LVL_14 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_14
+#ifndef CONF_DMAC_EVOE_14
+#define CONF_DMAC_EVOE_14 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_14
+#ifndef CONF_DMAC_EVIE_14
+#define CONF_DMAC_EVIE_14 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_14
+#ifndef CONF_DMAC_EVACT_14
+#define CONF_DMAC_EVACT_14 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_14
+#ifndef CONF_DMAC_STEPSIZE_14
+#define CONF_DMAC_STEPSIZE_14 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_14
+#ifndef CONF_DMAC_STEPSEL_14
+#define CONF_DMAC_STEPSEL_14 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_14
+#ifndef CONF_DMAC_SRCINC_14
+#define CONF_DMAC_SRCINC_14 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_14
+#ifndef CONF_DMAC_DSTINC_14
+#define CONF_DMAC_DSTINC_14 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_14
+#ifndef CONF_DMAC_BEATSIZE_14
+#define CONF_DMAC_BEATSIZE_14 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_14
+#ifndef CONF_DMAC_BLOCKACT_14
+#define CONF_DMAC_BLOCKACT_14 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_14
+#ifndef CONF_DMAC_EVOSEL_14
+#define CONF_DMAC_EVOSEL_14 0
+#endif
+// </e>
+
+// <e> Channel 15 settings
+// <id> dmac_channel_15_settings
+#ifndef CONF_DMAC_CHANNEL_15_SETTINGS
+#define CONF_DMAC_CHANNEL_15_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 15 is running in standby mode or not
+// <id> dmac_runstdby_15
+#ifndef CONF_DMAC_RUNSTDBY_15
+#define CONF_DMAC_RUNSTDBY_15 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_15
+#ifndef CONF_DMAC_TRIGACT_15
+#define CONF_DMAC_TRIGACT_15 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_15
+#ifndef CONF_DMAC_TRIGSRC_15
+#define CONF_DMAC_TRIGSRC_15 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_15
+#ifndef CONF_DMAC_LVL_15
+#define CONF_DMAC_LVL_15 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_15
+#ifndef CONF_DMAC_EVOE_15
+#define CONF_DMAC_EVOE_15 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_15
+#ifndef CONF_DMAC_EVIE_15
+#define CONF_DMAC_EVIE_15 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_15
+#ifndef CONF_DMAC_EVACT_15
+#define CONF_DMAC_EVACT_15 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_15
+#ifndef CONF_DMAC_STEPSIZE_15
+#define CONF_DMAC_STEPSIZE_15 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_15
+#ifndef CONF_DMAC_STEPSEL_15
+#define CONF_DMAC_STEPSEL_15 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_15
+#ifndef CONF_DMAC_SRCINC_15
+#define CONF_DMAC_SRCINC_15 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_15
+#ifndef CONF_DMAC_DSTINC_15
+#define CONF_DMAC_DSTINC_15 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_15
+#ifndef CONF_DMAC_BEATSIZE_15
+#define CONF_DMAC_BEATSIZE_15 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_15
+#ifndef CONF_DMAC_BLOCKACT_15
+#define CONF_DMAC_BLOCKACT_15 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_15
+#ifndef CONF_DMAC_EVOSEL_15
+#define CONF_DMAC_EVOSEL_15 0
+#endif
+// </e>
+
+// <e> Channel 16 settings
+// <id> dmac_channel_16_settings
+#ifndef CONF_DMAC_CHANNEL_16_SETTINGS
+#define CONF_DMAC_CHANNEL_16_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 16 is running in standby mode or not
+// <id> dmac_runstdby_16
+#ifndef CONF_DMAC_RUNSTDBY_16
+#define CONF_DMAC_RUNSTDBY_16 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_16
+#ifndef CONF_DMAC_TRIGACT_16
+#define CONF_DMAC_TRIGACT_16 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_16
+#ifndef CONF_DMAC_TRIGSRC_16
+#define CONF_DMAC_TRIGSRC_16 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_16
+#ifndef CONF_DMAC_LVL_16
+#define CONF_DMAC_LVL_16 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_16
+#ifndef CONF_DMAC_EVOE_16
+#define CONF_DMAC_EVOE_16 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_16
+#ifndef CONF_DMAC_EVIE_16
+#define CONF_DMAC_EVIE_16 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_16
+#ifndef CONF_DMAC_EVACT_16
+#define CONF_DMAC_EVACT_16 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_16
+#ifndef CONF_DMAC_STEPSIZE_16
+#define CONF_DMAC_STEPSIZE_16 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_16
+#ifndef CONF_DMAC_STEPSEL_16
+#define CONF_DMAC_STEPSEL_16 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_16
+#ifndef CONF_DMAC_SRCINC_16
+#define CONF_DMAC_SRCINC_16 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_16
+#ifndef CONF_DMAC_DSTINC_16
+#define CONF_DMAC_DSTINC_16 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_16
+#ifndef CONF_DMAC_BEATSIZE_16
+#define CONF_DMAC_BEATSIZE_16 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_16
+#ifndef CONF_DMAC_BLOCKACT_16
+#define CONF_DMAC_BLOCKACT_16 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_16
+#ifndef CONF_DMAC_EVOSEL_16
+#define CONF_DMAC_EVOSEL_16 0
+#endif
+// </e>
+
+// <e> Channel 17 settings
+// <id> dmac_channel_17_settings
+#ifndef CONF_DMAC_CHANNEL_17_SETTINGS
+#define CONF_DMAC_CHANNEL_17_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 17 is running in standby mode or not
+// <id> dmac_runstdby_17
+#ifndef CONF_DMAC_RUNSTDBY_17
+#define CONF_DMAC_RUNSTDBY_17 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_17
+#ifndef CONF_DMAC_TRIGACT_17
+#define CONF_DMAC_TRIGACT_17 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_17
+#ifndef CONF_DMAC_TRIGSRC_17
+#define CONF_DMAC_TRIGSRC_17 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_17
+#ifndef CONF_DMAC_LVL_17
+#define CONF_DMAC_LVL_17 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_17
+#ifndef CONF_DMAC_EVOE_17
+#define CONF_DMAC_EVOE_17 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_17
+#ifndef CONF_DMAC_EVIE_17
+#define CONF_DMAC_EVIE_17 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_17
+#ifndef CONF_DMAC_EVACT_17
+#define CONF_DMAC_EVACT_17 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_17
+#ifndef CONF_DMAC_STEPSIZE_17
+#define CONF_DMAC_STEPSIZE_17 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_17
+#ifndef CONF_DMAC_STEPSEL_17
+#define CONF_DMAC_STEPSEL_17 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_17
+#ifndef CONF_DMAC_SRCINC_17
+#define CONF_DMAC_SRCINC_17 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_17
+#ifndef CONF_DMAC_DSTINC_17
+#define CONF_DMAC_DSTINC_17 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_17
+#ifndef CONF_DMAC_BEATSIZE_17
+#define CONF_DMAC_BEATSIZE_17 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_17
+#ifndef CONF_DMAC_BLOCKACT_17
+#define CONF_DMAC_BLOCKACT_17 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_17
+#ifndef CONF_DMAC_EVOSEL_17
+#define CONF_DMAC_EVOSEL_17 0
+#endif
+// </e>
+
+// <e> Channel 18 settings
+// <id> dmac_channel_18_settings
+#ifndef CONF_DMAC_CHANNEL_18_SETTINGS
+#define CONF_DMAC_CHANNEL_18_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 18 is running in standby mode or not
+// <id> dmac_runstdby_18
+#ifndef CONF_DMAC_RUNSTDBY_18
+#define CONF_DMAC_RUNSTDBY_18 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_18
+#ifndef CONF_DMAC_TRIGACT_18
+#define CONF_DMAC_TRIGACT_18 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_18
+#ifndef CONF_DMAC_TRIGSRC_18
+#define CONF_DMAC_TRIGSRC_18 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_18
+#ifndef CONF_DMAC_LVL_18
+#define CONF_DMAC_LVL_18 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_18
+#ifndef CONF_DMAC_EVOE_18
+#define CONF_DMAC_EVOE_18 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_18
+#ifndef CONF_DMAC_EVIE_18
+#define CONF_DMAC_EVIE_18 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_18
+#ifndef CONF_DMAC_EVACT_18
+#define CONF_DMAC_EVACT_18 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_18
+#ifndef CONF_DMAC_STEPSIZE_18
+#define CONF_DMAC_STEPSIZE_18 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_18
+#ifndef CONF_DMAC_STEPSEL_18
+#define CONF_DMAC_STEPSEL_18 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_18
+#ifndef CONF_DMAC_SRCINC_18
+#define CONF_DMAC_SRCINC_18 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_18
+#ifndef CONF_DMAC_DSTINC_18
+#define CONF_DMAC_DSTINC_18 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_18
+#ifndef CONF_DMAC_BEATSIZE_18
+#define CONF_DMAC_BEATSIZE_18 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_18
+#ifndef CONF_DMAC_BLOCKACT_18
+#define CONF_DMAC_BLOCKACT_18 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_18
+#ifndef CONF_DMAC_EVOSEL_18
+#define CONF_DMAC_EVOSEL_18 0
+#endif
+// </e>
+
+// <e> Channel 19 settings
+// <id> dmac_channel_19_settings
+#ifndef CONF_DMAC_CHANNEL_19_SETTINGS
+#define CONF_DMAC_CHANNEL_19_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 19 is running in standby mode or not
+// <id> dmac_runstdby_19
+#ifndef CONF_DMAC_RUNSTDBY_19
+#define CONF_DMAC_RUNSTDBY_19 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_19
+#ifndef CONF_DMAC_TRIGACT_19
+#define CONF_DMAC_TRIGACT_19 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_19
+#ifndef CONF_DMAC_TRIGSRC_19
+#define CONF_DMAC_TRIGSRC_19 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_19
+#ifndef CONF_DMAC_LVL_19
+#define CONF_DMAC_LVL_19 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_19
+#ifndef CONF_DMAC_EVOE_19
+#define CONF_DMAC_EVOE_19 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_19
+#ifndef CONF_DMAC_EVIE_19
+#define CONF_DMAC_EVIE_19 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_19
+#ifndef CONF_DMAC_EVACT_19
+#define CONF_DMAC_EVACT_19 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_19
+#ifndef CONF_DMAC_STEPSIZE_19
+#define CONF_DMAC_STEPSIZE_19 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_19
+#ifndef CONF_DMAC_STEPSEL_19
+#define CONF_DMAC_STEPSEL_19 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_19
+#ifndef CONF_DMAC_SRCINC_19
+#define CONF_DMAC_SRCINC_19 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_19
+#ifndef CONF_DMAC_DSTINC_19
+#define CONF_DMAC_DSTINC_19 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_19
+#ifndef CONF_DMAC_BEATSIZE_19
+#define CONF_DMAC_BEATSIZE_19 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_19
+#ifndef CONF_DMAC_BLOCKACT_19
+#define CONF_DMAC_BLOCKACT_19 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_19
+#ifndef CONF_DMAC_EVOSEL_19
+#define CONF_DMAC_EVOSEL_19 0
+#endif
+// </e>
+
+// <e> Channel 20 settings
+// <id> dmac_channel_20_settings
+#ifndef CONF_DMAC_CHANNEL_20_SETTINGS
+#define CONF_DMAC_CHANNEL_20_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 20 is running in standby mode or not
+// <id> dmac_runstdby_20
+#ifndef CONF_DMAC_RUNSTDBY_20
+#define CONF_DMAC_RUNSTDBY_20 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_20
+#ifndef CONF_DMAC_TRIGACT_20
+#define CONF_DMAC_TRIGACT_20 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_20
+#ifndef CONF_DMAC_TRIGSRC_20
+#define CONF_DMAC_TRIGSRC_20 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_20
+#ifndef CONF_DMAC_LVL_20
+#define CONF_DMAC_LVL_20 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_20
+#ifndef CONF_DMAC_EVOE_20
+#define CONF_DMAC_EVOE_20 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_20
+#ifndef CONF_DMAC_EVIE_20
+#define CONF_DMAC_EVIE_20 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_20
+#ifndef CONF_DMAC_EVACT_20
+#define CONF_DMAC_EVACT_20 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_20
+#ifndef CONF_DMAC_STEPSIZE_20
+#define CONF_DMAC_STEPSIZE_20 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_20
+#ifndef CONF_DMAC_STEPSEL_20
+#define CONF_DMAC_STEPSEL_20 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_20
+#ifndef CONF_DMAC_SRCINC_20
+#define CONF_DMAC_SRCINC_20 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_20
+#ifndef CONF_DMAC_DSTINC_20
+#define CONF_DMAC_DSTINC_20 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_20
+#ifndef CONF_DMAC_BEATSIZE_20
+#define CONF_DMAC_BEATSIZE_20 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_20
+#ifndef CONF_DMAC_BLOCKACT_20
+#define CONF_DMAC_BLOCKACT_20 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_20
+#ifndef CONF_DMAC_EVOSEL_20
+#define CONF_DMAC_EVOSEL_20 0
+#endif
+// </e>
+
+// <e> Channel 21 settings
+// <id> dmac_channel_21_settings
+#ifndef CONF_DMAC_CHANNEL_21_SETTINGS
+#define CONF_DMAC_CHANNEL_21_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 21 is running in standby mode or not
+// <id> dmac_runstdby_21
+#ifndef CONF_DMAC_RUNSTDBY_21
+#define CONF_DMAC_RUNSTDBY_21 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_21
+#ifndef CONF_DMAC_TRIGACT_21
+#define CONF_DMAC_TRIGACT_21 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_21
+#ifndef CONF_DMAC_TRIGSRC_21
+#define CONF_DMAC_TRIGSRC_21 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_21
+#ifndef CONF_DMAC_LVL_21
+#define CONF_DMAC_LVL_21 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_21
+#ifndef CONF_DMAC_EVOE_21
+#define CONF_DMAC_EVOE_21 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_21
+#ifndef CONF_DMAC_EVIE_21
+#define CONF_DMAC_EVIE_21 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_21
+#ifndef CONF_DMAC_EVACT_21
+#define CONF_DMAC_EVACT_21 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_21
+#ifndef CONF_DMAC_STEPSIZE_21
+#define CONF_DMAC_STEPSIZE_21 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_21
+#ifndef CONF_DMAC_STEPSEL_21
+#define CONF_DMAC_STEPSEL_21 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_21
+#ifndef CONF_DMAC_SRCINC_21
+#define CONF_DMAC_SRCINC_21 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_21
+#ifndef CONF_DMAC_DSTINC_21
+#define CONF_DMAC_DSTINC_21 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_21
+#ifndef CONF_DMAC_BEATSIZE_21
+#define CONF_DMAC_BEATSIZE_21 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_21
+#ifndef CONF_DMAC_BLOCKACT_21
+#define CONF_DMAC_BLOCKACT_21 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_21
+#ifndef CONF_DMAC_EVOSEL_21
+#define CONF_DMAC_EVOSEL_21 0
+#endif
+// </e>
+
+// <e> Channel 22 settings
+// <id> dmac_channel_22_settings
+#ifndef CONF_DMAC_CHANNEL_22_SETTINGS
+#define CONF_DMAC_CHANNEL_22_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 22 is running in standby mode or not
+// <id> dmac_runstdby_22
+#ifndef CONF_DMAC_RUNSTDBY_22
+#define CONF_DMAC_RUNSTDBY_22 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_22
+#ifndef CONF_DMAC_TRIGACT_22
+#define CONF_DMAC_TRIGACT_22 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_22
+#ifndef CONF_DMAC_TRIGSRC_22
+#define CONF_DMAC_TRIGSRC_22 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_22
+#ifndef CONF_DMAC_LVL_22
+#define CONF_DMAC_LVL_22 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_22
+#ifndef CONF_DMAC_EVOE_22
+#define CONF_DMAC_EVOE_22 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_22
+#ifndef CONF_DMAC_EVIE_22
+#define CONF_DMAC_EVIE_22 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_22
+#ifndef CONF_DMAC_EVACT_22
+#define CONF_DMAC_EVACT_22 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_22
+#ifndef CONF_DMAC_STEPSIZE_22
+#define CONF_DMAC_STEPSIZE_22 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_22
+#ifndef CONF_DMAC_STEPSEL_22
+#define CONF_DMAC_STEPSEL_22 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_22
+#ifndef CONF_DMAC_SRCINC_22
+#define CONF_DMAC_SRCINC_22 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_22
+#ifndef CONF_DMAC_DSTINC_22
+#define CONF_DMAC_DSTINC_22 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_22
+#ifndef CONF_DMAC_BEATSIZE_22
+#define CONF_DMAC_BEATSIZE_22 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_22
+#ifndef CONF_DMAC_BLOCKACT_22
+#define CONF_DMAC_BLOCKACT_22 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_22
+#ifndef CONF_DMAC_EVOSEL_22
+#define CONF_DMAC_EVOSEL_22 0
+#endif
+// </e>
+
+// <e> Channel 23 settings
+// <id> dmac_channel_23_settings
+#ifndef CONF_DMAC_CHANNEL_23_SETTINGS
+#define CONF_DMAC_CHANNEL_23_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 23 is running in standby mode or not
+// <id> dmac_runstdby_23
+#ifndef CONF_DMAC_RUNSTDBY_23
+#define CONF_DMAC_RUNSTDBY_23 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_23
+#ifndef CONF_DMAC_TRIGACT_23
+#define CONF_DMAC_TRIGACT_23 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_23
+#ifndef CONF_DMAC_TRIGSRC_23
+#define CONF_DMAC_TRIGSRC_23 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_23
+#ifndef CONF_DMAC_LVL_23
+#define CONF_DMAC_LVL_23 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_23
+#ifndef CONF_DMAC_EVOE_23
+#define CONF_DMAC_EVOE_23 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_23
+#ifndef CONF_DMAC_EVIE_23
+#define CONF_DMAC_EVIE_23 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_23
+#ifndef CONF_DMAC_EVACT_23
+#define CONF_DMAC_EVACT_23 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_23
+#ifndef CONF_DMAC_STEPSIZE_23
+#define CONF_DMAC_STEPSIZE_23 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_23
+#ifndef CONF_DMAC_STEPSEL_23
+#define CONF_DMAC_STEPSEL_23 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_23
+#ifndef CONF_DMAC_SRCINC_23
+#define CONF_DMAC_SRCINC_23 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_23
+#ifndef CONF_DMAC_DSTINC_23
+#define CONF_DMAC_DSTINC_23 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_23
+#ifndef CONF_DMAC_BEATSIZE_23
+#define CONF_DMAC_BEATSIZE_23 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_23
+#ifndef CONF_DMAC_BLOCKACT_23
+#define CONF_DMAC_BLOCKACT_23 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_23
+#ifndef CONF_DMAC_EVOSEL_23
+#define CONF_DMAC_EVOSEL_23 0
+#endif
+// </e>
+
+// <e> Channel 24 settings
+// <id> dmac_channel_24_settings
+#ifndef CONF_DMAC_CHANNEL_24_SETTINGS
+#define CONF_DMAC_CHANNEL_24_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 24 is running in standby mode or not
+// <id> dmac_runstdby_24
+#ifndef CONF_DMAC_RUNSTDBY_24
+#define CONF_DMAC_RUNSTDBY_24 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_24
+#ifndef CONF_DMAC_TRIGACT_24
+#define CONF_DMAC_TRIGACT_24 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_24
+#ifndef CONF_DMAC_TRIGSRC_24
+#define CONF_DMAC_TRIGSRC_24 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_24
+#ifndef CONF_DMAC_LVL_24
+#define CONF_DMAC_LVL_24 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_24
+#ifndef CONF_DMAC_EVOE_24
+#define CONF_DMAC_EVOE_24 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_24
+#ifndef CONF_DMAC_EVIE_24
+#define CONF_DMAC_EVIE_24 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_24
+#ifndef CONF_DMAC_EVACT_24
+#define CONF_DMAC_EVACT_24 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_24
+#ifndef CONF_DMAC_STEPSIZE_24
+#define CONF_DMAC_STEPSIZE_24 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_24
+#ifndef CONF_DMAC_STEPSEL_24
+#define CONF_DMAC_STEPSEL_24 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_24
+#ifndef CONF_DMAC_SRCINC_24
+#define CONF_DMAC_SRCINC_24 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_24
+#ifndef CONF_DMAC_DSTINC_24
+#define CONF_DMAC_DSTINC_24 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_24
+#ifndef CONF_DMAC_BEATSIZE_24
+#define CONF_DMAC_BEATSIZE_24 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_24
+#ifndef CONF_DMAC_BLOCKACT_24
+#define CONF_DMAC_BLOCKACT_24 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_24
+#ifndef CONF_DMAC_EVOSEL_24
+#define CONF_DMAC_EVOSEL_24 0
+#endif
+// </e>
+
+// <e> Channel 25 settings
+// <id> dmac_channel_25_settings
+#ifndef CONF_DMAC_CHANNEL_25_SETTINGS
+#define CONF_DMAC_CHANNEL_25_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 25 is running in standby mode or not
+// <id> dmac_runstdby_25
+#ifndef CONF_DMAC_RUNSTDBY_25
+#define CONF_DMAC_RUNSTDBY_25 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_25
+#ifndef CONF_DMAC_TRIGACT_25
+#define CONF_DMAC_TRIGACT_25 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_25
+#ifndef CONF_DMAC_TRIGSRC_25
+#define CONF_DMAC_TRIGSRC_25 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_25
+#ifndef CONF_DMAC_LVL_25
+#define CONF_DMAC_LVL_25 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_25
+#ifndef CONF_DMAC_EVOE_25
+#define CONF_DMAC_EVOE_25 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_25
+#ifndef CONF_DMAC_EVIE_25
+#define CONF_DMAC_EVIE_25 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_25
+#ifndef CONF_DMAC_EVACT_25
+#define CONF_DMAC_EVACT_25 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_25
+#ifndef CONF_DMAC_STEPSIZE_25
+#define CONF_DMAC_STEPSIZE_25 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_25
+#ifndef CONF_DMAC_STEPSEL_25
+#define CONF_DMAC_STEPSEL_25 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_25
+#ifndef CONF_DMAC_SRCINC_25
+#define CONF_DMAC_SRCINC_25 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_25
+#ifndef CONF_DMAC_DSTINC_25
+#define CONF_DMAC_DSTINC_25 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_25
+#ifndef CONF_DMAC_BEATSIZE_25
+#define CONF_DMAC_BEATSIZE_25 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_25
+#ifndef CONF_DMAC_BLOCKACT_25
+#define CONF_DMAC_BLOCKACT_25 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_25
+#ifndef CONF_DMAC_EVOSEL_25
+#define CONF_DMAC_EVOSEL_25 0
+#endif
+// </e>
+
+// <e> Channel 26 settings
+// <id> dmac_channel_26_settings
+#ifndef CONF_DMAC_CHANNEL_26_SETTINGS
+#define CONF_DMAC_CHANNEL_26_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 26 is running in standby mode or not
+// <id> dmac_runstdby_26
+#ifndef CONF_DMAC_RUNSTDBY_26
+#define CONF_DMAC_RUNSTDBY_26 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_26
+#ifndef CONF_DMAC_TRIGACT_26
+#define CONF_DMAC_TRIGACT_26 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_26
+#ifndef CONF_DMAC_TRIGSRC_26
+#define CONF_DMAC_TRIGSRC_26 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_26
+#ifndef CONF_DMAC_LVL_26
+#define CONF_DMAC_LVL_26 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_26
+#ifndef CONF_DMAC_EVOE_26
+#define CONF_DMAC_EVOE_26 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_26
+#ifndef CONF_DMAC_EVIE_26
+#define CONF_DMAC_EVIE_26 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_26
+#ifndef CONF_DMAC_EVACT_26
+#define CONF_DMAC_EVACT_26 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_26
+#ifndef CONF_DMAC_STEPSIZE_26
+#define CONF_DMAC_STEPSIZE_26 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_26
+#ifndef CONF_DMAC_STEPSEL_26
+#define CONF_DMAC_STEPSEL_26 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_26
+#ifndef CONF_DMAC_SRCINC_26
+#define CONF_DMAC_SRCINC_26 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_26
+#ifndef CONF_DMAC_DSTINC_26
+#define CONF_DMAC_DSTINC_26 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_26
+#ifndef CONF_DMAC_BEATSIZE_26
+#define CONF_DMAC_BEATSIZE_26 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_26
+#ifndef CONF_DMAC_BLOCKACT_26
+#define CONF_DMAC_BLOCKACT_26 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_26
+#ifndef CONF_DMAC_EVOSEL_26
+#define CONF_DMAC_EVOSEL_26 0
+#endif
+// </e>
+
+// <e> Channel 27 settings
+// <id> dmac_channel_27_settings
+#ifndef CONF_DMAC_CHANNEL_27_SETTINGS
+#define CONF_DMAC_CHANNEL_27_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 27 is running in standby mode or not
+// <id> dmac_runstdby_27
+#ifndef CONF_DMAC_RUNSTDBY_27
+#define CONF_DMAC_RUNSTDBY_27 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_27
+#ifndef CONF_DMAC_TRIGACT_27
+#define CONF_DMAC_TRIGACT_27 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_27
+#ifndef CONF_DMAC_TRIGSRC_27
+#define CONF_DMAC_TRIGSRC_27 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_27
+#ifndef CONF_DMAC_LVL_27
+#define CONF_DMAC_LVL_27 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_27
+#ifndef CONF_DMAC_EVOE_27
+#define CONF_DMAC_EVOE_27 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_27
+#ifndef CONF_DMAC_EVIE_27
+#define CONF_DMAC_EVIE_27 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_27
+#ifndef CONF_DMAC_EVACT_27
+#define CONF_DMAC_EVACT_27 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_27
+#ifndef CONF_DMAC_STEPSIZE_27
+#define CONF_DMAC_STEPSIZE_27 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_27
+#ifndef CONF_DMAC_STEPSEL_27
+#define CONF_DMAC_STEPSEL_27 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_27
+#ifndef CONF_DMAC_SRCINC_27
+#define CONF_DMAC_SRCINC_27 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_27
+#ifndef CONF_DMAC_DSTINC_27
+#define CONF_DMAC_DSTINC_27 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_27
+#ifndef CONF_DMAC_BEATSIZE_27
+#define CONF_DMAC_BEATSIZE_27 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_27
+#ifndef CONF_DMAC_BLOCKACT_27
+#define CONF_DMAC_BLOCKACT_27 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_27
+#ifndef CONF_DMAC_EVOSEL_27
+#define CONF_DMAC_EVOSEL_27 0
+#endif
+// </e>
+
+// <e> Channel 28 settings
+// <id> dmac_channel_28_settings
+#ifndef CONF_DMAC_CHANNEL_28_SETTINGS
+#define CONF_DMAC_CHANNEL_28_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 28 is running in standby mode or not
+// <id> dmac_runstdby_28
+#ifndef CONF_DMAC_RUNSTDBY_28
+#define CONF_DMAC_RUNSTDBY_28 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_28
+#ifndef CONF_DMAC_TRIGACT_28
+#define CONF_DMAC_TRIGACT_28 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_28
+#ifndef CONF_DMAC_TRIGSRC_28
+#define CONF_DMAC_TRIGSRC_28 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_28
+#ifndef CONF_DMAC_LVL_28
+#define CONF_DMAC_LVL_28 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_28
+#ifndef CONF_DMAC_EVOE_28
+#define CONF_DMAC_EVOE_28 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_28
+#ifndef CONF_DMAC_EVIE_28
+#define CONF_DMAC_EVIE_28 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_28
+#ifndef CONF_DMAC_EVACT_28
+#define CONF_DMAC_EVACT_28 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_28
+#ifndef CONF_DMAC_STEPSIZE_28
+#define CONF_DMAC_STEPSIZE_28 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_28
+#ifndef CONF_DMAC_STEPSEL_28
+#define CONF_DMAC_STEPSEL_28 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_28
+#ifndef CONF_DMAC_SRCINC_28
+#define CONF_DMAC_SRCINC_28 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_28
+#ifndef CONF_DMAC_DSTINC_28
+#define CONF_DMAC_DSTINC_28 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_28
+#ifndef CONF_DMAC_BEATSIZE_28
+#define CONF_DMAC_BEATSIZE_28 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_28
+#ifndef CONF_DMAC_BLOCKACT_28
+#define CONF_DMAC_BLOCKACT_28 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_28
+#ifndef CONF_DMAC_EVOSEL_28
+#define CONF_DMAC_EVOSEL_28 0
+#endif
+// </e>
+
+// <e> Channel 29 settings
+// <id> dmac_channel_29_settings
+#ifndef CONF_DMAC_CHANNEL_29_SETTINGS
+#define CONF_DMAC_CHANNEL_29_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 29 is running in standby mode or not
+// <id> dmac_runstdby_29
+#ifndef CONF_DMAC_RUNSTDBY_29
+#define CONF_DMAC_RUNSTDBY_29 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_29
+#ifndef CONF_DMAC_TRIGACT_29
+#define CONF_DMAC_TRIGACT_29 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_29
+#ifndef CONF_DMAC_TRIGSRC_29
+#define CONF_DMAC_TRIGSRC_29 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_29
+#ifndef CONF_DMAC_LVL_29
+#define CONF_DMAC_LVL_29 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_29
+#ifndef CONF_DMAC_EVOE_29
+#define CONF_DMAC_EVOE_29 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_29
+#ifndef CONF_DMAC_EVIE_29
+#define CONF_DMAC_EVIE_29 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_29
+#ifndef CONF_DMAC_EVACT_29
+#define CONF_DMAC_EVACT_29 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_29
+#ifndef CONF_DMAC_STEPSIZE_29
+#define CONF_DMAC_STEPSIZE_29 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_29
+#ifndef CONF_DMAC_STEPSEL_29
+#define CONF_DMAC_STEPSEL_29 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_29
+#ifndef CONF_DMAC_SRCINC_29
+#define CONF_DMAC_SRCINC_29 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_29
+#ifndef CONF_DMAC_DSTINC_29
+#define CONF_DMAC_DSTINC_29 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_29
+#ifndef CONF_DMAC_BEATSIZE_29
+#define CONF_DMAC_BEATSIZE_29 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_29
+#ifndef CONF_DMAC_BLOCKACT_29
+#define CONF_DMAC_BLOCKACT_29 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_29
+#ifndef CONF_DMAC_EVOSEL_29
+#define CONF_DMAC_EVOSEL_29 0
+#endif
+// </e>
+
+// <e> Channel 30 settings
+// <id> dmac_channel_30_settings
+#ifndef CONF_DMAC_CHANNEL_30_SETTINGS
+#define CONF_DMAC_CHANNEL_30_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 30 is running in standby mode or not
+// <id> dmac_runstdby_30
+#ifndef CONF_DMAC_RUNSTDBY_30
+#define CONF_DMAC_RUNSTDBY_30 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_30
+#ifndef CONF_DMAC_TRIGACT_30
+#define CONF_DMAC_TRIGACT_30 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_30
+#ifndef CONF_DMAC_TRIGSRC_30
+#define CONF_DMAC_TRIGSRC_30 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_30
+#ifndef CONF_DMAC_LVL_30
+#define CONF_DMAC_LVL_30 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_30
+#ifndef CONF_DMAC_EVOE_30
+#define CONF_DMAC_EVOE_30 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_30
+#ifndef CONF_DMAC_EVIE_30
+#define CONF_DMAC_EVIE_30 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_30
+#ifndef CONF_DMAC_EVACT_30
+#define CONF_DMAC_EVACT_30 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_30
+#ifndef CONF_DMAC_STEPSIZE_30
+#define CONF_DMAC_STEPSIZE_30 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_30
+#ifndef CONF_DMAC_STEPSEL_30
+#define CONF_DMAC_STEPSEL_30 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_30
+#ifndef CONF_DMAC_SRCINC_30
+#define CONF_DMAC_SRCINC_30 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_30
+#ifndef CONF_DMAC_DSTINC_30
+#define CONF_DMAC_DSTINC_30 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_30
+#ifndef CONF_DMAC_BEATSIZE_30
+#define CONF_DMAC_BEATSIZE_30 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_30
+#ifndef CONF_DMAC_BLOCKACT_30
+#define CONF_DMAC_BLOCKACT_30 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_30
+#ifndef CONF_DMAC_EVOSEL_30
+#define CONF_DMAC_EVOSEL_30 0
+#endif
+// </e>
+
+// <e> Channel 31 settings
+// <id> dmac_channel_31_settings
+#ifndef CONF_DMAC_CHANNEL_31_SETTINGS
+#define CONF_DMAC_CHANNEL_31_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 31 is running in standby mode or not
+// <id> dmac_runstdby_31
+#ifndef CONF_DMAC_RUNSTDBY_31
+#define CONF_DMAC_RUNSTDBY_31 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_31
+#ifndef CONF_DMAC_TRIGACT_31
+#define CONF_DMAC_TRIGACT_31 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_31
+#ifndef CONF_DMAC_TRIGSRC_31
+#define CONF_DMAC_TRIGSRC_31 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_31
+#ifndef CONF_DMAC_LVL_31
+#define CONF_DMAC_LVL_31 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_31
+#ifndef CONF_DMAC_EVOE_31
+#define CONF_DMAC_EVOE_31 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_31
+#ifndef CONF_DMAC_EVIE_31
+#define CONF_DMAC_EVIE_31 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_31
+#ifndef CONF_DMAC_EVACT_31
+#define CONF_DMAC_EVACT_31 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_31
+#ifndef CONF_DMAC_STEPSIZE_31
+#define CONF_DMAC_STEPSIZE_31 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_31
+#ifndef CONF_DMAC_STEPSEL_31
+#define CONF_DMAC_STEPSEL_31 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_31
+#ifndef CONF_DMAC_SRCINC_31
+#define CONF_DMAC_SRCINC_31 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_31
+#ifndef CONF_DMAC_DSTINC_31
+#define CONF_DMAC_DSTINC_31 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_31
+#ifndef CONF_DMAC_BEATSIZE_31
+#define CONF_DMAC_BEATSIZE_31 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_31
+#ifndef CONF_DMAC_BLOCKACT_31
+#define CONF_DMAC_BLOCKACT_31 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_31
+#ifndef CONF_DMAC_EVOSEL_31
+#define CONF_DMAC_EVOSEL_31 0
+#endif
+// </e>
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_DMAC_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_eic_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_eic_config.h
new file mode 100644
index 0000000..4b92f33
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_eic_config.h
@@ -0,0 +1,913 @@
+/* Auto-generated config file hpl_eic_config.h */
+#ifndef HPL_EIC_CONFIG_H
+#define HPL_EIC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic Settings
+// <o> Clock Selection
+// <i> Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or
+// <i> either by CLK_ULP32K when power consumption is the priority.
+// <0x0=> Clocked by GCLK
+// <0x1=> Clocked by ULPOSC32K
+// <id> eic_arch_cksel
+#ifndef CONF_EIC_CKSEL
+#define CONF_EIC_CKSEL 0
+#endif
+
+// <o> Pin Sampler frequency selection
+// <i> Indicates the sampling rate of the EXTINT pin.
+// <0x0=> The sampling rate is EIC clock
+// <0x1=> The sampling rate is the prescaled clock
+// <id> eic_arch_tickon
+#ifndef CONF_EIC_TICKON
+#define CONF_EIC_TICKON 0
+#endif
+
+// </h>
+
+// <e> Non-Maskable Interrupt Control
+// <id> eic_arch_nmi_ctrl
+#ifndef CONF_EIC_ENABLE_NMI_CTRL
+#define CONF_EIC_ENABLE_NMI_CTRL 0
+#endif
+
+// <q> Non-Maskable Interrupt Filter Enable
+// <i> Indicates whether the mon-maskable interrupt filter is enabled or not
+// <id> eic_arch_nmifilten
+#ifndef CONF_EIC_NMIFILTEN
+#define CONF_EIC_NMIFILTEN 0
+#endif
+
+// <y> Non-Maskable Interrupt Sense
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines non-maskable interrupt sense
+// <id> eic_arch_nmisense
+#ifndef CONF_EIC_NMISENSE
+#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> Asynchronous Edge Detection Mode
+// <i> Indicates the interrupt detection mode operated synchronously or asynchronousl
+// <id> eic_arch_nmiasynch
+#ifndef CONF_EIC_NMIASYNCH
+#define CONF_EIC_NMIASYNCH 0
+#endif
+// </e>
+
+// <e> Interrupt 0 Settings
+// <id> eic_arch_enable_irq_setting0
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING0
+#define CONF_EIC_ENABLE_IRQ_SETTING0 0
+#endif
+
+// <q> External Interrupt 0 Filter Enable
+// <i> Indicates whether the external interrupt 0 filter is enabled or not
+// <id> eic_arch_filten0
+#ifndef CONF_EIC_FILTEN0
+#define CONF_EIC_FILTEN0 0
+#endif
+
+// <q> External Interrupt 0 Debounce Enable
+// <i> Indicates whether the external interrupt 0 debounce is enabled or not
+// <id> eic_arch_debounce_enable0
+#ifndef CONF_EIC_DEBOUNCE_ENABLE0
+#define CONF_EIC_DEBOUNCE_ENABLE0 0
+#endif
+
+// <q> External Interrupt 0 Event Output Enable
+// <i> Indicates whether the external interrupt 0 event output is enabled or not
+// <id> eic_arch_extinteo0
+#ifndef CONF_EIC_EXTINTEO0
+#define CONF_EIC_EXTINTEO0 0
+#endif
+
+// <y> Input 0 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense0
+#ifndef CONF_EIC_SENSE0
+#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 0 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch0
+#ifndef CONF_EIC_ASYNCH0
+#define CONF_EIC_ASYNCH0 0
+#endif
+
+// </e>
+
+// <e> Interrupt 1 Settings
+// <id> eic_arch_enable_irq_setting1
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING1
+#define CONF_EIC_ENABLE_IRQ_SETTING1 0
+#endif
+
+// <q> External Interrupt 1 Filter Enable
+// <i> Indicates whether the external interrupt 1 filter is enabled or not
+// <id> eic_arch_filten1
+#ifndef CONF_EIC_FILTEN1
+#define CONF_EIC_FILTEN1 0
+#endif
+
+// <q> External Interrupt 1 Debounce Enable
+// <i> Indicates whether the external interrupt 1 debounce is enabled or not
+// <id> eic_arch_debounce_enable1
+#ifndef CONF_EIC_DEBOUNCE_ENABLE1
+#define CONF_EIC_DEBOUNCE_ENABLE1 0
+#endif
+
+// <q> External Interrupt 1 Event Output Enable
+// <i> Indicates whether the external interrupt 1 event output is enabled or not
+// <id> eic_arch_extinteo1
+#ifndef CONF_EIC_EXTINTEO1
+#define CONF_EIC_EXTINTEO1 0
+#endif
+
+// <y> Input 1 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense1
+#ifndef CONF_EIC_SENSE1
+#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 1 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch1
+#ifndef CONF_EIC_ASYNCH1
+#define CONF_EIC_ASYNCH1 0
+#endif
+
+// </e>
+
+// <e> Interrupt 2 Settings
+// <id> eic_arch_enable_irq_setting2
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING2
+#define CONF_EIC_ENABLE_IRQ_SETTING2 1
+#endif
+
+// <q> External Interrupt 2 Filter Enable
+// <i> Indicates whether the external interrupt 2 filter is enabled or not
+// <id> eic_arch_filten2
+#ifndef CONF_EIC_FILTEN2
+#define CONF_EIC_FILTEN2 0
+#endif
+
+// <q> External Interrupt 2 Debounce Enable
+// <i> Indicates whether the external interrupt 2 debounce is enabled or not
+// <id> eic_arch_debounce_enable2
+#ifndef CONF_EIC_DEBOUNCE_ENABLE2
+#define CONF_EIC_DEBOUNCE_ENABLE2 0
+#endif
+
+// <q> External Interrupt 2 Event Output Enable
+// <i> Indicates whether the external interrupt 2 event output is enabled or not
+// <id> eic_arch_extinteo2
+#ifndef CONF_EIC_EXTINTEO2
+#define CONF_EIC_EXTINTEO2 1
+#endif
+
+// <y> Input 2 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense2
+#ifndef CONF_EIC_SENSE2
+#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_FALL_Val
+#endif
+
+// <q> External Interrupt 2 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch2
+#ifndef CONF_EIC_ASYNCH2
+#define CONF_EIC_ASYNCH2 1
+#endif
+
+// </e>
+
+// <e> Interrupt 3 Settings
+// <id> eic_arch_enable_irq_setting3
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING3
+#define CONF_EIC_ENABLE_IRQ_SETTING3 0
+#endif
+
+// <q> External Interrupt 3 Filter Enable
+// <i> Indicates whether the external interrupt 3 filter is enabled or not
+// <id> eic_arch_filten3
+#ifndef CONF_EIC_FILTEN3
+#define CONF_EIC_FILTEN3 0
+#endif
+
+// <q> External Interrupt 3 Debounce Enable
+// <i> Indicates whether the external interrupt 3 debounce is enabled or not
+// <id> eic_arch_debounce_enable3
+#ifndef CONF_EIC_DEBOUNCE_ENABLE3
+#define CONF_EIC_DEBOUNCE_ENABLE3 0
+#endif
+
+// <q> External Interrupt 3 Event Output Enable
+// <i> Indicates whether the external interrupt 3 event output is enabled or not
+// <id> eic_arch_extinteo3
+#ifndef CONF_EIC_EXTINTEO3
+#define CONF_EIC_EXTINTEO3 0
+#endif
+
+// <y> Input 3 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense3
+#ifndef CONF_EIC_SENSE3
+#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 3 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch3
+#ifndef CONF_EIC_ASYNCH3
+#define CONF_EIC_ASYNCH3 0
+#endif
+
+// </e>
+
+// <e> Interrupt 4 Settings
+// <id> eic_arch_enable_irq_setting4
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING4
+#define CONF_EIC_ENABLE_IRQ_SETTING4 0
+#endif
+
+// <q> External Interrupt 4 Filter Enable
+// <i> Indicates whether the external interrupt 4 filter is enabled or not
+// <id> eic_arch_filten4
+#ifndef CONF_EIC_FILTEN4
+#define CONF_EIC_FILTEN4 0
+#endif
+
+// <q> External Interrupt 4 Debounce Enable
+// <i> Indicates whether the external interrupt 4 debounce is enabled or not
+// <id> eic_arch_debounce_enable4
+#ifndef CONF_EIC_DEBOUNCE_ENABLE4
+#define CONF_EIC_DEBOUNCE_ENABLE4 0
+#endif
+
+// <q> External Interrupt 4 Event Output Enable
+// <i> Indicates whether the external interrupt 4 event output is enabled or not
+// <id> eic_arch_extinteo4
+#ifndef CONF_EIC_EXTINTEO4
+#define CONF_EIC_EXTINTEO4 0
+#endif
+
+// <y> Input 4 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense4
+#ifndef CONF_EIC_SENSE4
+#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 4 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch4
+#ifndef CONF_EIC_ASYNCH4
+#define CONF_EIC_ASYNCH4 0
+#endif
+
+// </e>
+
+// <e> Interrupt 5 Settings
+// <id> eic_arch_enable_irq_setting5
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING5
+#define CONF_EIC_ENABLE_IRQ_SETTING5 0
+#endif
+
+// <q> External Interrupt 5 Filter Enable
+// <i> Indicates whether the external interrupt 5 filter is enabled or not
+// <id> eic_arch_filten5
+#ifndef CONF_EIC_FILTEN5
+#define CONF_EIC_FILTEN5 0
+#endif
+
+// <q> External Interrupt 5 Debounce Enable
+// <i> Indicates whether the external interrupt 5 debounce is enabled or not
+// <id> eic_arch_debounce_enable5
+#ifndef CONF_EIC_DEBOUNCE_ENABLE5
+#define CONF_EIC_DEBOUNCE_ENABLE5 0
+#endif
+
+// <q> External Interrupt 5 Event Output Enable
+// <i> Indicates whether the external interrupt 5 event output is enabled or not
+// <id> eic_arch_extinteo5
+#ifndef CONF_EIC_EXTINTEO5
+#define CONF_EIC_EXTINTEO5 0
+#endif
+
+// <y> Input 5 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense5
+#ifndef CONF_EIC_SENSE5
+#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 5 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch5
+#ifndef CONF_EIC_ASYNCH5
+#define CONF_EIC_ASYNCH5 0
+#endif
+
+// </e>
+
+// <e> Interrupt 6 Settings
+// <id> eic_arch_enable_irq_setting6
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING6
+#define CONF_EIC_ENABLE_IRQ_SETTING6 0
+#endif
+
+// <q> External Interrupt 6 Filter Enable
+// <i> Indicates whether the external interrupt 6 filter is enabled or not
+// <id> eic_arch_filten6
+#ifndef CONF_EIC_FILTEN6
+#define CONF_EIC_FILTEN6 0
+#endif
+
+// <q> External Interrupt 6 Debounce Enable
+// <i> Indicates whether the external interrupt 6 debounce is enabled or not
+// <id> eic_arch_debounce_enable6
+#ifndef CONF_EIC_DEBOUNCE_ENABLE6
+#define CONF_EIC_DEBOUNCE_ENABLE6 0
+#endif
+
+// <q> External Interrupt 6 Event Output Enable
+// <i> Indicates whether the external interrupt 6 event output is enabled or not
+// <id> eic_arch_extinteo6
+#ifndef CONF_EIC_EXTINTEO6
+#define CONF_EIC_EXTINTEO6 0
+#endif
+
+// <y> Input 6 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense6
+#ifndef CONF_EIC_SENSE6
+#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 6 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch6
+#ifndef CONF_EIC_ASYNCH6
+#define CONF_EIC_ASYNCH6 0
+#endif
+
+// </e>
+
+// <e> Interrupt 7 Settings
+// <id> eic_arch_enable_irq_setting7
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING7
+#define CONF_EIC_ENABLE_IRQ_SETTING7 0
+#endif
+
+// <q> External Interrupt 7 Filter Enable
+// <i> Indicates whether the external interrupt 7 filter is enabled or not
+// <id> eic_arch_filten7
+#ifndef CONF_EIC_FILTEN7
+#define CONF_EIC_FILTEN7 0
+#endif
+
+// <q> External Interrupt 7 Debounce Enable
+// <i> Indicates whether the external interrupt 7 debounce is enabled or not
+// <id> eic_arch_debounce_enable7
+#ifndef CONF_EIC_DEBOUNCE_ENABLE7
+#define CONF_EIC_DEBOUNCE_ENABLE7 0
+#endif
+
+// <q> External Interrupt 7 Event Output Enable
+// <i> Indicates whether the external interrupt 7 event output is enabled or not
+// <id> eic_arch_extinteo7
+#ifndef CONF_EIC_EXTINTEO7
+#define CONF_EIC_EXTINTEO7 0
+#endif
+
+// <y> Input 7 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense7
+#ifndef CONF_EIC_SENSE7
+#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 7 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch7
+#ifndef CONF_EIC_ASYNCH7
+#define CONF_EIC_ASYNCH7 0
+#endif
+
+// </e>
+
+// <e> Interrupt 8 Settings
+// <id> eic_arch_enable_irq_setting8
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING8
+#define CONF_EIC_ENABLE_IRQ_SETTING8 0
+#endif
+
+// <q> External Interrupt 8 Filter Enable
+// <i> Indicates whether the external interrupt 8 filter is enabled or not
+// <id> eic_arch_filten8
+#ifndef CONF_EIC_FILTEN8
+#define CONF_EIC_FILTEN8 0
+#endif
+
+// <q> External Interrupt 8 Debounce Enable
+// <i> Indicates whether the external interrupt 8 debounce is enabled or not
+// <id> eic_arch_debounce_enable8
+#ifndef CONF_EIC_DEBOUNCE_ENABLE8
+#define CONF_EIC_DEBOUNCE_ENABLE8 0
+#endif
+
+// <q> External Interrupt 8 Event Output Enable
+// <i> Indicates whether the external interrupt 8 event output is enabled or not
+// <id> eic_arch_extinteo8
+#ifndef CONF_EIC_EXTINTEO8
+#define CONF_EIC_EXTINTEO8 0
+#endif
+
+// <y> Input 8 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense8
+#ifndef CONF_EIC_SENSE8
+#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 8 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch8
+#ifndef CONF_EIC_ASYNCH8
+#define CONF_EIC_ASYNCH8 0
+#endif
+
+// </e>
+
+// <e> Interrupt 9 Settings
+// <id> eic_arch_enable_irq_setting9
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING9
+#define CONF_EIC_ENABLE_IRQ_SETTING9 0
+#endif
+
+// <q> External Interrupt 9 Filter Enable
+// <i> Indicates whether the external interrupt 9 filter is enabled or not
+// <id> eic_arch_filten9
+#ifndef CONF_EIC_FILTEN9
+#define CONF_EIC_FILTEN9 0
+#endif
+
+// <q> External Interrupt 9 Debounce Enable
+// <i> Indicates whether the external interrupt 9 debounce is enabled or not
+// <id> eic_arch_debounce_enable9
+#ifndef CONF_EIC_DEBOUNCE_ENABLE9
+#define CONF_EIC_DEBOUNCE_ENABLE9 0
+#endif
+
+// <q> External Interrupt 9 Event Output Enable
+// <i> Indicates whether the external interrupt 9 event output is enabled or not
+// <id> eic_arch_extinteo9
+#ifndef CONF_EIC_EXTINTEO9
+#define CONF_EIC_EXTINTEO9 0
+#endif
+
+// <y> Input 9 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense9
+#ifndef CONF_EIC_SENSE9
+#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 9 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch9
+#ifndef CONF_EIC_ASYNCH9
+#define CONF_EIC_ASYNCH9 0
+#endif
+
+// </e>
+
+// <e> Interrupt 10 Settings
+// <id> eic_arch_enable_irq_setting10
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING10
+#define CONF_EIC_ENABLE_IRQ_SETTING10 0
+#endif
+
+// <q> External Interrupt 10 Filter Enable
+// <i> Indicates whether the external interrupt 10 filter is enabled or not
+// <id> eic_arch_filten10
+#ifndef CONF_EIC_FILTEN10
+#define CONF_EIC_FILTEN10 0
+#endif
+
+// <q> External Interrupt 10 Debounce Enable
+// <i> Indicates whether the external interrupt 10 debounce is enabled or not
+// <id> eic_arch_debounce_enable10
+#ifndef CONF_EIC_DEBOUNCE_ENABLE10
+#define CONF_EIC_DEBOUNCE_ENABLE10 0
+#endif
+
+// <q> External Interrupt 10 Event Output Enable
+// <i> Indicates whether the external interrupt 10 event output is enabled or not
+// <id> eic_arch_extinteo10
+#ifndef CONF_EIC_EXTINTEO10
+#define CONF_EIC_EXTINTEO10 0
+#endif
+
+// <y> Input 10 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense10
+#ifndef CONF_EIC_SENSE10
+#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 10 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch10
+#ifndef CONF_EIC_ASYNCH10
+#define CONF_EIC_ASYNCH10 0
+#endif
+
+// </e>
+
+// <e> Interrupt 11 Settings
+// <id> eic_arch_enable_irq_setting11
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING11
+#define CONF_EIC_ENABLE_IRQ_SETTING11 0
+#endif
+
+// <q> External Interrupt 11 Filter Enable
+// <i> Indicates whether the external interrupt 11 filter is enabled or not
+// <id> eic_arch_filten11
+#ifndef CONF_EIC_FILTEN11
+#define CONF_EIC_FILTEN11 0
+#endif
+
+// <q> External Interrupt 11 Debounce Enable
+// <i> Indicates whether the external interrupt 11 debounce is enabled or not
+// <id> eic_arch_debounce_enable11
+#ifndef CONF_EIC_DEBOUNCE_ENABLE11
+#define CONF_EIC_DEBOUNCE_ENABLE11 0
+#endif
+
+// <q> External Interrupt 11 Event Output Enable
+// <i> Indicates whether the external interrupt 11 event output is enabled or not
+// <id> eic_arch_extinteo11
+#ifndef CONF_EIC_EXTINTEO11
+#define CONF_EIC_EXTINTEO11 0
+#endif
+
+// <y> Input 11 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense11
+#ifndef CONF_EIC_SENSE11
+#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 11 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch11
+#ifndef CONF_EIC_ASYNCH11
+#define CONF_EIC_ASYNCH11 0
+#endif
+
+// </e>
+
+// <e> Interrupt 12 Settings
+// <id> eic_arch_enable_irq_setting12
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING12
+#define CONF_EIC_ENABLE_IRQ_SETTING12 0
+#endif
+
+// <q> External Interrupt 12 Filter Enable
+// <i> Indicates whether the external interrupt 12 filter is enabled or not
+// <id> eic_arch_filten12
+#ifndef CONF_EIC_FILTEN12
+#define CONF_EIC_FILTEN12 0
+#endif
+
+// <q> External Interrupt 12 Debounce Enable
+// <i> Indicates whether the external interrupt 12 debounce is enabled or not
+// <id> eic_arch_debounce_enable12
+#ifndef CONF_EIC_DEBOUNCE_ENABLE12
+#define CONF_EIC_DEBOUNCE_ENABLE12 0
+#endif
+
+// <q> External Interrupt 12 Event Output Enable
+// <i> Indicates whether the external interrupt 12 event output is enabled or not
+// <id> eic_arch_extinteo12
+#ifndef CONF_EIC_EXTINTEO12
+#define CONF_EIC_EXTINTEO12 0
+#endif
+
+// <y> Input 12 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense12
+#ifndef CONF_EIC_SENSE12
+#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 12 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch12
+#ifndef CONF_EIC_ASYNCH12
+#define CONF_EIC_ASYNCH12 0
+#endif
+
+// </e>
+
+// <e> Interrupt 13 Settings
+// <id> eic_arch_enable_irq_setting13
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING13
+#define CONF_EIC_ENABLE_IRQ_SETTING13 0
+#endif
+
+// <q> External Interrupt 13 Filter Enable
+// <i> Indicates whether the external interrupt 13 filter is enabled or not
+// <id> eic_arch_filten13
+#ifndef CONF_EIC_FILTEN13
+#define CONF_EIC_FILTEN13 0
+#endif
+
+// <q> External Interrupt 13 Debounce Enable
+// <i> Indicates whether the external interrupt 13 debounce is enabled or not
+// <id> eic_arch_debounce_enable13
+#ifndef CONF_EIC_DEBOUNCE_ENABLE13
+#define CONF_EIC_DEBOUNCE_ENABLE13 0
+#endif
+
+// <q> External Interrupt 13 Event Output Enable
+// <i> Indicates whether the external interrupt 13 event output is enabled or not
+// <id> eic_arch_extinteo13
+#ifndef CONF_EIC_EXTINTEO13
+#define CONF_EIC_EXTINTEO13 0
+#endif
+
+// <y> Input 13 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense13
+#ifndef CONF_EIC_SENSE13
+#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 13 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch13
+#ifndef CONF_EIC_ASYNCH13
+#define CONF_EIC_ASYNCH13 0
+#endif
+
+// </e>
+
+// <e> Interrupt 14 Settings
+// <id> eic_arch_enable_irq_setting14
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING14
+#define CONF_EIC_ENABLE_IRQ_SETTING14 1
+#endif
+
+// <q> External Interrupt 14 Filter Enable
+// <i> Indicates whether the external interrupt 14 filter is enabled or not
+// <id> eic_arch_filten14
+#ifndef CONF_EIC_FILTEN14
+#define CONF_EIC_FILTEN14 1
+#endif
+
+// <q> External Interrupt 14 Debounce Enable
+// <i> Indicates whether the external interrupt 14 debounce is enabled or not
+// <id> eic_arch_debounce_enable14
+#ifndef CONF_EIC_DEBOUNCE_ENABLE14
+#define CONF_EIC_DEBOUNCE_ENABLE14 0
+#endif
+
+// <q> External Interrupt 14 Event Output Enable
+// <i> Indicates whether the external interrupt 14 event output is enabled or not
+// <id> eic_arch_extinteo14
+#ifndef CONF_EIC_EXTINTEO14
+#define CONF_EIC_EXTINTEO14 0
+#endif
+
+// <y> Input 14 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense14
+#ifndef CONF_EIC_SENSE14
+#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_FALL_Val
+#endif
+
+// <q> External Interrupt 14 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch14
+#ifndef CONF_EIC_ASYNCH14
+#define CONF_EIC_ASYNCH14 0
+#endif
+
+// </e>
+
+// <e> Interrupt 15 Settings
+// <id> eic_arch_enable_irq_setting15
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING15
+#define CONF_EIC_ENABLE_IRQ_SETTING15 1
+#endif
+
+// <q> External Interrupt 15 Filter Enable
+// <i> Indicates whether the external interrupt 15 filter is enabled or not
+// <id> eic_arch_filten15
+#ifndef CONF_EIC_FILTEN15
+#define CONF_EIC_FILTEN15 1
+#endif
+
+// <q> External Interrupt 15 Debounce Enable
+// <i> Indicates whether the external interrupt 15 debounce is enabled or not
+// <id> eic_arch_debounce_enable15
+#ifndef CONF_EIC_DEBOUNCE_ENABLE15
+#define CONF_EIC_DEBOUNCE_ENABLE15 0
+#endif
+
+// <q> External Interrupt 15 Event Output Enable
+// <i> Indicates whether the external interrupt 15 event output is enabled or not
+// <id> eic_arch_extinteo15
+#ifndef CONF_EIC_EXTINTEO15
+#define CONF_EIC_EXTINTEO15 0
+#endif
+
+// <y> Input 15 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense15
+#ifndef CONF_EIC_SENSE15
+#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_FALL_Val
+#endif
+
+// <q> External Interrupt 15 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch15
+#ifndef CONF_EIC_ASYNCH15
+#define CONF_EIC_ASYNCH15 0
+#endif
+
+// </e>
+
+// <h> Debouncer 0 Settings
+// <o> Debouncer Frequency Selection
+// <0x0=>Divided by 2
+// <0x1=>Divided by 4
+// <0x2=>Divided by 8
+// <0x3=>Divided by 16
+// <0x4=>Divided by 32
+// <0x5=>Divided by 64
+// <0x6=>Divided by 128
+// <0x7=>Divided by 256
+// <i> Select the debouncer low frequency clock for pins
+
+//   <i> EXTINT[7:0].
+
+// <id> eic_arch_prescaler0
+#ifndef CONF_EIC_DPRESCALER0
+#define CONF_EIC_DPRESCALER0 EIC_DPRESCALER_PRESCALER0(0x0)
+#endif
+
+// <o> Low frequency samples
+// <0x0=>3
+// <0x1=>7
+// <i> Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from
+// <i> current pin state to next pin state in synchronous debouncing mode.
+// <id> eic_arch_states0
+#ifndef CONF_EIC_STATES0
+#define CONF_EIC_STATES0 0x0
+#endif
+
+// </h>
+
+// <h> Debouncer 1 Settings
+// <o> Debouncer Frequency Selection
+// <0x0=>Divided by 2
+// <0x1=>Divided by 4
+// <0x2=>Divided by 8
+// <0x3=>Divided by 16
+// <0x4=>Divided by 32
+// <0x5=>Divided by 64
+// <0x6=>Divided by 128
+// <0x7=>Divided by 256
+// <i> Select the debouncer low frequency clock for pins
+
+//   <i> EXTINT[15:8].
+
+// <id> eic_arch_prescaler1
+#ifndef CONF_EIC_DPRESCALER1
+#define CONF_EIC_DPRESCALER1 EIC_DPRESCALER_PRESCALER1(0x0)
+#endif
+
+// <o> Low frequency samples
+// <0x0=>3
+// <0x1=>7
+// <i> Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from
+// <i> current pin state to next pin state in synchronous debouncing mode.
+// <id> eic_arch_states1
+#ifndef CONF_EIC_STATES1
+#define CONF_EIC_STATES1 0x0
+#endif
+
+// </h>
+
+#define CONFIG_EIC_EXTINT_MAP {2, PIN_PA02}, {7, PIN_PA07}, {14, PIN_PB30}, {15, PIN_PB31},
+
+// <<< end of configuration section >>>
+
+#endif // HPL_EIC_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_evsys_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_evsys_config.h
new file mode 100644
index 0000000..b193999
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_evsys_config.h
@@ -0,0 +1,8363 @@
+/* Auto-generated config file hpl_evsys_config.h */
+#ifndef HPL_EVSYS_CONFIG_H
+#define HPL_EVSYS_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> Channel 0 settings
+// <id> evsys_channel_setting_0
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_0
+#define CONF_EVSYS_CHANNEL_SETTINGS_0 1
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_0
+#ifndef CONF_EDGSEL_0
+#define CONF_EDGSEL_0 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_0
+#ifndef CONF_PATH_0
+#define CONF_PATH_0 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_0
+#ifndef CONF_EVGEN_0
+#define CONF_EVGEN_0 41
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_0
+#ifndef CONF_OVR_0
+#define CONF_OVR_0 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_0
+#ifndef CONF_EVD_0
+#define CONF_EVD_0 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_0
+#ifndef CONF_ONDEMAND_0
+#define CONF_ONDEMAND_0 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_0
+#ifndef CONF_RUNSTDBY_0
+#define CONF_RUNSTDBY_0 0
+#endif
+
+// </e>
+
+// <e> Channel 1 settings
+// <id> evsys_channel_setting_1
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_1
+#define CONF_EVSYS_CHANNEL_SETTINGS_1 1
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_1
+#ifndef CONF_EDGSEL_1
+#define CONF_EDGSEL_1 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_1
+#ifndef CONF_PATH_1
+#define CONF_PATH_1 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_1
+#ifndef CONF_EVGEN_1
+#define CONF_EVGEN_1 74
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_1
+#ifndef CONF_OVR_1
+#define CONF_OVR_1 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_1
+#ifndef CONF_EVD_1
+#define CONF_EVD_1 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_1
+#ifndef CONF_ONDEMAND_1
+#define CONF_ONDEMAND_1 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_1
+#ifndef CONF_RUNSTDBY_1
+#define CONF_RUNSTDBY_1 0
+#endif
+
+// </e>
+
+// <e> Channel 2 settings
+// <id> evsys_channel_setting_2
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_2
+#define CONF_EVSYS_CHANNEL_SETTINGS_2 1
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_2
+#ifndef CONF_EDGSEL_2
+#define CONF_EDGSEL_2 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_2
+#ifndef CONF_PATH_2
+#define CONF_PATH_2 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_2
+#ifndef CONF_EVGEN_2
+#define CONF_EVGEN_2 75
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_2
+#ifndef CONF_OVR_2
+#define CONF_OVR_2 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_2
+#ifndef CONF_EVD_2
+#define CONF_EVD_2 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_2
+#ifndef CONF_ONDEMAND_2
+#define CONF_ONDEMAND_2 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_2
+#ifndef CONF_RUNSTDBY_2
+#define CONF_RUNSTDBY_2 0
+#endif
+
+// </e>
+
+// <e> Channel 3 settings
+// <id> evsys_channel_setting_3
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_3
+#define CONF_EVSYS_CHANNEL_SETTINGS_3 1
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_3
+#ifndef CONF_EDGSEL_3
+#define CONF_EDGSEL_3 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_3
+#ifndef CONF_PATH_3
+#define CONF_PATH_3 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_3
+#ifndef CONF_EVGEN_3
+#define CONF_EVGEN_3 78
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_3
+#ifndef CONF_OVR_3
+#define CONF_OVR_3 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_3
+#ifndef CONF_EVD_3
+#define CONF_EVD_3 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_3
+#ifndef CONF_ONDEMAND_3
+#define CONF_ONDEMAND_3 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_3
+#ifndef CONF_RUNSTDBY_3
+#define CONF_RUNSTDBY_3 0
+#endif
+
+// </e>
+
+// <e> Channel 4 settings
+// <id> evsys_channel_setting_4
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_4
+#define CONF_EVSYS_CHANNEL_SETTINGS_4 1
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_4
+#ifndef CONF_EDGSEL_4
+#define CONF_EDGSEL_4 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_4
+#ifndef CONF_PATH_4
+#define CONF_PATH_4 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_4
+#ifndef CONF_EVGEN_4
+#define CONF_EVGEN_4 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_4
+#ifndef CONF_OVR_4
+#define CONF_OVR_4 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_4
+#ifndef CONF_EVD_4
+#define CONF_EVD_4 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_4
+#ifndef CONF_ONDEMAND_4
+#define CONF_ONDEMAND_4 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_4
+#ifndef CONF_RUNSTDBY_4
+#define CONF_RUNSTDBY_4 0
+#endif
+
+// </e>
+
+// <e> Channel 5 settings
+// <id> evsys_channel_setting_5
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_5
+#define CONF_EVSYS_CHANNEL_SETTINGS_5 1
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_5
+#ifndef CONF_EDGSEL_5
+#define CONF_EDGSEL_5 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_5
+#ifndef CONF_PATH_5
+#define CONF_PATH_5 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_5
+#ifndef CONF_EVGEN_5
+#define CONF_EVGEN_5 20
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_5
+#ifndef CONF_OVR_5
+#define CONF_OVR_5 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_5
+#ifndef CONF_EVD_5
+#define CONF_EVD_5 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_5
+#ifndef CONF_ONDEMAND_5
+#define CONF_ONDEMAND_5 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_5
+#ifndef CONF_RUNSTDBY_5
+#define CONF_RUNSTDBY_5 0
+#endif
+
+// </e>
+
+// <e> Channel 6 settings
+// <id> evsys_channel_setting_6
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_6
+#define CONF_EVSYS_CHANNEL_SETTINGS_6 1
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_6
+#ifndef CONF_EDGSEL_6
+#define CONF_EDGSEL_6 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_6
+#ifndef CONF_PATH_6
+#define CONF_PATH_6 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_6
+#ifndef CONF_EVGEN_6
+#define CONF_EVGEN_6 34
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_6
+#ifndef CONF_OVR_6
+#define CONF_OVR_6 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_6
+#ifndef CONF_EVD_6
+#define CONF_EVD_6 1
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_6
+#ifndef CONF_ONDEMAND_6
+#define CONF_ONDEMAND_6 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_6
+#ifndef CONF_RUNSTDBY_6
+#define CONF_RUNSTDBY_6 0
+#endif
+
+// </e>
+
+// <e> Channel 7 settings
+// <id> evsys_channel_setting_7
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_7
+#define CONF_EVSYS_CHANNEL_SETTINGS_7 1
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_7
+#ifndef CONF_EDGSEL_7
+#define CONF_EDGSEL_7 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_7
+#ifndef CONF_PATH_7
+#define CONF_PATH_7 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_7
+#ifndef CONF_EVGEN_7
+#define CONF_EVGEN_7 35
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_7
+#ifndef CONF_OVR_7
+#define CONF_OVR_7 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_7
+#ifndef CONF_EVD_7
+#define CONF_EVD_7 1
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_7
+#ifndef CONF_ONDEMAND_7
+#define CONF_ONDEMAND_7 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_7
+#ifndef CONF_RUNSTDBY_7
+#define CONF_RUNSTDBY_7 0
+#endif
+
+// </e>
+
+// <e> Channel 8 settings
+// <id> evsys_channel_setting_8
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_8
+#define CONF_EVSYS_CHANNEL_SETTINGS_8 1
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_8
+#ifndef CONF_EDGSEL_8
+#define CONF_EDGSEL_8 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_8
+#ifndef CONF_PATH_8
+#define CONF_PATH_8 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_8
+#ifndef CONF_EVGEN_8
+#define CONF_EVGEN_8 36
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_8
+#ifndef CONF_OVR_8
+#define CONF_OVR_8 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_8
+#ifndef CONF_EVD_8
+#define CONF_EVD_8 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_8
+#ifndef CONF_ONDEMAND_8
+#define CONF_ONDEMAND_8 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_8
+#ifndef CONF_RUNSTDBY_8
+#define CONF_RUNSTDBY_8 0
+#endif
+
+// </e>
+
+// <e> Channel 9 settings
+// <id> evsys_channel_setting_9
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_9
+#define CONF_EVSYS_CHANNEL_SETTINGS_9 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_9
+#ifndef CONF_EDGSEL_9
+#define CONF_EDGSEL_9 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_9
+#ifndef CONF_PATH_9
+#define CONF_PATH_9 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_9
+#ifndef CONF_EVGEN_9
+#define CONF_EVGEN_9 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_9
+#ifndef CONF_OVR_9
+#define CONF_OVR_9 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_9
+#ifndef CONF_EVD_9
+#define CONF_EVD_9 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_9
+#ifndef CONF_ONDEMAND_9
+#define CONF_ONDEMAND_9 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_9
+#ifndef CONF_RUNSTDBY_9
+#define CONF_RUNSTDBY_9 0
+#endif
+
+// </e>
+
+// <e> Channel 10 settings
+// <id> evsys_channel_setting_10
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_10
+#define CONF_EVSYS_CHANNEL_SETTINGS_10 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_10
+#ifndef CONF_EDGSEL_10
+#define CONF_EDGSEL_10 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_10
+#ifndef CONF_PATH_10
+#define CONF_PATH_10 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_10
+#ifndef CONF_EVGEN_10
+#define CONF_EVGEN_10 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_10
+#ifndef CONF_OVR_10
+#define CONF_OVR_10 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_10
+#ifndef CONF_EVD_10
+#define CONF_EVD_10 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_10
+#ifndef CONF_ONDEMAND_10
+#define CONF_ONDEMAND_10 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_10
+#ifndef CONF_RUNSTDBY_10
+#define CONF_RUNSTDBY_10 0
+#endif
+
+// </e>
+
+// <e> Channel 11 settings
+// <id> evsys_channel_setting_11
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_11
+#define CONF_EVSYS_CHANNEL_SETTINGS_11 1
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_11
+#ifndef CONF_EDGSEL_11
+#define CONF_EDGSEL_11 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_11
+#ifndef CONF_PATH_11
+#define CONF_PATH_11 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_11
+#ifndef CONF_EVGEN_11
+#define CONF_EVGEN_11 116
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_11
+#ifndef CONF_OVR_11
+#define CONF_OVR_11 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_11
+#ifndef CONF_EVD_11
+#define CONF_EVD_11 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_11
+#ifndef CONF_ONDEMAND_11
+#define CONF_ONDEMAND_11 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_11
+#ifndef CONF_RUNSTDBY_11
+#define CONF_RUNSTDBY_11 0
+#endif
+
+// </e>
+
+// <e> Channel 12 settings
+// <id> evsys_channel_setting_12
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_12
+#define CONF_EVSYS_CHANNEL_SETTINGS_12 1
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_12
+#ifndef CONF_EDGSEL_12
+#define CONF_EDGSEL_12 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_12
+#ifndef CONF_PATH_12
+#define CONF_PATH_12 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_12
+#ifndef CONF_EVGEN_12
+#define CONF_EVGEN_12 118
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_12
+#ifndef CONF_OVR_12
+#define CONF_OVR_12 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_12
+#ifndef CONF_EVD_12
+#define CONF_EVD_12 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_12
+#ifndef CONF_ONDEMAND_12
+#define CONF_ONDEMAND_12 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_12
+#ifndef CONF_RUNSTDBY_12
+#define CONF_RUNSTDBY_12 0
+#endif
+
+// </e>
+
+// <e> Channel 13 settings
+// <id> evsys_channel_setting_13
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_13
+#define CONF_EVSYS_CHANNEL_SETTINGS_13 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_13
+#ifndef CONF_EDGSEL_13
+#define CONF_EDGSEL_13 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_13
+#ifndef CONF_PATH_13
+#define CONF_PATH_13 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_13
+#ifndef CONF_EVGEN_13
+#define CONF_EVGEN_13 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_13
+#ifndef CONF_OVR_13
+#define CONF_OVR_13 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_13
+#ifndef CONF_EVD_13
+#define CONF_EVD_13 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_13
+#ifndef CONF_ONDEMAND_13
+#define CONF_ONDEMAND_13 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_13
+#ifndef CONF_RUNSTDBY_13
+#define CONF_RUNSTDBY_13 0
+#endif
+
+// </e>
+
+// <e> Channel 14 settings
+// <id> evsys_channel_setting_14
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_14
+#define CONF_EVSYS_CHANNEL_SETTINGS_14 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_14
+#ifndef CONF_EDGSEL_14
+#define CONF_EDGSEL_14 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_14
+#ifndef CONF_PATH_14
+#define CONF_PATH_14 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_14
+#ifndef CONF_EVGEN_14
+#define CONF_EVGEN_14 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_14
+#ifndef CONF_OVR_14
+#define CONF_OVR_14 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_14
+#ifndef CONF_EVD_14
+#define CONF_EVD_14 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_14
+#ifndef CONF_ONDEMAND_14
+#define CONF_ONDEMAND_14 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_14
+#ifndef CONF_RUNSTDBY_14
+#define CONF_RUNSTDBY_14 0
+#endif
+
+// </e>
+
+// <e> Channel 15 settings
+// <id> evsys_channel_setting_15
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_15
+#define CONF_EVSYS_CHANNEL_SETTINGS_15 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_15
+#ifndef CONF_EDGSEL_15
+#define CONF_EDGSEL_15 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_15
+#ifndef CONF_PATH_15
+#define CONF_PATH_15 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_15
+#ifndef CONF_EVGEN_15
+#define CONF_EVGEN_15 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_15
+#ifndef CONF_OVR_15
+#define CONF_OVR_15 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_15
+#ifndef CONF_EVD_15
+#define CONF_EVD_15 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_15
+#ifndef CONF_ONDEMAND_15
+#define CONF_ONDEMAND_15 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_15
+#ifndef CONF_RUNSTDBY_15
+#define CONF_RUNSTDBY_15 0
+#endif
+
+// </e>
+
+// <e> Channel 16 settings
+// <id> evsys_channel_setting_16
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_16
+#define CONF_EVSYS_CHANNEL_SETTINGS_16 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_16
+#ifndef CONF_EDGSEL_16
+#define CONF_EDGSEL_16 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_16
+#ifndef CONF_PATH_16
+#define CONF_PATH_16 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_16
+#ifndef CONF_EVGEN_16
+#define CONF_EVGEN_16 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_16
+#ifndef CONF_OVR_16
+#define CONF_OVR_16 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_16
+#ifndef CONF_EVD_16
+#define CONF_EVD_16 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_16
+#ifndef CONF_ONDEMAND_16
+#define CONF_ONDEMAND_16 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_16
+#ifndef CONF_RUNSTDBY_16
+#define CONF_RUNSTDBY_16 0
+#endif
+
+// </e>
+
+// <e> Channel 17 settings
+// <id> evsys_channel_setting_17
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_17
+#define CONF_EVSYS_CHANNEL_SETTINGS_17 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_17
+#ifndef CONF_EDGSEL_17
+#define CONF_EDGSEL_17 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_17
+#ifndef CONF_PATH_17
+#define CONF_PATH_17 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_17
+#ifndef CONF_EVGEN_17
+#define CONF_EVGEN_17 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_17
+#ifndef CONF_OVR_17
+#define CONF_OVR_17 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_17
+#ifndef CONF_EVD_17
+#define CONF_EVD_17 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_17
+#ifndef CONF_ONDEMAND_17
+#define CONF_ONDEMAND_17 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_17
+#ifndef CONF_RUNSTDBY_17
+#define CONF_RUNSTDBY_17 0
+#endif
+
+// </e>
+
+// <e> Channel 18 settings
+// <id> evsys_channel_setting_18
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_18
+#define CONF_EVSYS_CHANNEL_SETTINGS_18 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_18
+#ifndef CONF_EDGSEL_18
+#define CONF_EDGSEL_18 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_18
+#ifndef CONF_PATH_18
+#define CONF_PATH_18 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_18
+#ifndef CONF_EVGEN_18
+#define CONF_EVGEN_18 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_18
+#ifndef CONF_OVR_18
+#define CONF_OVR_18 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_18
+#ifndef CONF_EVD_18
+#define CONF_EVD_18 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_18
+#ifndef CONF_ONDEMAND_18
+#define CONF_ONDEMAND_18 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_18
+#ifndef CONF_RUNSTDBY_18
+#define CONF_RUNSTDBY_18 0
+#endif
+
+// </e>
+
+// <e> Channel 19 settings
+// <id> evsys_channel_setting_19
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_19
+#define CONF_EVSYS_CHANNEL_SETTINGS_19 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_19
+#ifndef CONF_EDGSEL_19
+#define CONF_EDGSEL_19 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_19
+#ifndef CONF_PATH_19
+#define CONF_PATH_19 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_19
+#ifndef CONF_EVGEN_19
+#define CONF_EVGEN_19 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_19
+#ifndef CONF_OVR_19
+#define CONF_OVR_19 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_19
+#ifndef CONF_EVD_19
+#define CONF_EVD_19 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_19
+#ifndef CONF_ONDEMAND_19
+#define CONF_ONDEMAND_19 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_19
+#ifndef CONF_RUNSTDBY_19
+#define CONF_RUNSTDBY_19 0
+#endif
+
+// </e>
+
+// <e> Channel 20 settings
+// <id> evsys_channel_setting_20
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_20
+#define CONF_EVSYS_CHANNEL_SETTINGS_20 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_20
+#ifndef CONF_EDGSEL_20
+#define CONF_EDGSEL_20 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_20
+#ifndef CONF_PATH_20
+#define CONF_PATH_20 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_20
+#ifndef CONF_EVGEN_20
+#define CONF_EVGEN_20 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_20
+#ifndef CONF_OVR_20
+#define CONF_OVR_20 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_20
+#ifndef CONF_EVD_20
+#define CONF_EVD_20 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_20
+#ifndef CONF_ONDEMAND_20
+#define CONF_ONDEMAND_20 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_20
+#ifndef CONF_RUNSTDBY_20
+#define CONF_RUNSTDBY_20 0
+#endif
+
+// </e>
+
+// <e> Channel 21 settings
+// <id> evsys_channel_setting_21
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_21
+#define CONF_EVSYS_CHANNEL_SETTINGS_21 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_21
+#ifndef CONF_EDGSEL_21
+#define CONF_EDGSEL_21 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_21
+#ifndef CONF_PATH_21
+#define CONF_PATH_21 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_21
+#ifndef CONF_EVGEN_21
+#define CONF_EVGEN_21 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_21
+#ifndef CONF_OVR_21
+#define CONF_OVR_21 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_21
+#ifndef CONF_EVD_21
+#define CONF_EVD_21 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_21
+#ifndef CONF_ONDEMAND_21
+#define CONF_ONDEMAND_21 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_21
+#ifndef CONF_RUNSTDBY_21
+#define CONF_RUNSTDBY_21 0
+#endif
+
+// </e>
+
+// <e> Channel 22 settings
+// <id> evsys_channel_setting_22
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_22
+#define CONF_EVSYS_CHANNEL_SETTINGS_22 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_22
+#ifndef CONF_EDGSEL_22
+#define CONF_EDGSEL_22 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_22
+#ifndef CONF_PATH_22
+#define CONF_PATH_22 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_22
+#ifndef CONF_EVGEN_22
+#define CONF_EVGEN_22 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_22
+#ifndef CONF_OVR_22
+#define CONF_OVR_22 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_22
+#ifndef CONF_EVD_22
+#define CONF_EVD_22 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_22
+#ifndef CONF_ONDEMAND_22
+#define CONF_ONDEMAND_22 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_22
+#ifndef CONF_RUNSTDBY_22
+#define CONF_RUNSTDBY_22 0
+#endif
+
+// </e>
+
+// <e> Channel 23 settings
+// <id> evsys_channel_setting_23
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_23
+#define CONF_EVSYS_CHANNEL_SETTINGS_23 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_23
+#ifndef CONF_EDGSEL_23
+#define CONF_EDGSEL_23 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_23
+#ifndef CONF_PATH_23
+#define CONF_PATH_23 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_23
+#ifndef CONF_EVGEN_23
+#define CONF_EVGEN_23 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_23
+#ifndef CONF_OVR_23
+#define CONF_OVR_23 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_23
+#ifndef CONF_EVD_23
+#define CONF_EVD_23 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_23
+#ifndef CONF_ONDEMAND_23
+#define CONF_ONDEMAND_23 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_23
+#ifndef CONF_RUNSTDBY_23
+#define CONF_RUNSTDBY_23 0
+#endif
+
+// </e>
+
+// <e> Channel 24 settings
+// <id> evsys_channel_setting_24
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_24
+#define CONF_EVSYS_CHANNEL_SETTINGS_24 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_24
+#ifndef CONF_EDGSEL_24
+#define CONF_EDGSEL_24 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_24
+#ifndef CONF_PATH_24
+#define CONF_PATH_24 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_24
+#ifndef CONF_EVGEN_24
+#define CONF_EVGEN_24 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_24
+#ifndef CONF_OVR_24
+#define CONF_OVR_24 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_24
+#ifndef CONF_EVD_24
+#define CONF_EVD_24 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_24
+#ifndef CONF_ONDEMAND_24
+#define CONF_ONDEMAND_24 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_24
+#ifndef CONF_RUNSTDBY_24
+#define CONF_RUNSTDBY_24 0
+#endif
+
+// </e>
+
+// <e> Channel 25 settings
+// <id> evsys_channel_setting_25
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_25
+#define CONF_EVSYS_CHANNEL_SETTINGS_25 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_25
+#ifndef CONF_EDGSEL_25
+#define CONF_EDGSEL_25 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_25
+#ifndef CONF_PATH_25
+#define CONF_PATH_25 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_25
+#ifndef CONF_EVGEN_25
+#define CONF_EVGEN_25 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_25
+#ifndef CONF_OVR_25
+#define CONF_OVR_25 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_25
+#ifndef CONF_EVD_25
+#define CONF_EVD_25 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_25
+#ifndef CONF_ONDEMAND_25
+#define CONF_ONDEMAND_25 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_25
+#ifndef CONF_RUNSTDBY_25
+#define CONF_RUNSTDBY_25 0
+#endif
+
+// </e>
+
+// <e> Channel 26 settings
+// <id> evsys_channel_setting_26
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_26
+#define CONF_EVSYS_CHANNEL_SETTINGS_26 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_26
+#ifndef CONF_EDGSEL_26
+#define CONF_EDGSEL_26 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_26
+#ifndef CONF_PATH_26
+#define CONF_PATH_26 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_26
+#ifndef CONF_EVGEN_26
+#define CONF_EVGEN_26 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_26
+#ifndef CONF_OVR_26
+#define CONF_OVR_26 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_26
+#ifndef CONF_EVD_26
+#define CONF_EVD_26 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_26
+#ifndef CONF_ONDEMAND_26
+#define CONF_ONDEMAND_26 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_26
+#ifndef CONF_RUNSTDBY_26
+#define CONF_RUNSTDBY_26 0
+#endif
+
+// </e>
+
+// <e> Channel 27 settings
+// <id> evsys_channel_setting_27
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_27
+#define CONF_EVSYS_CHANNEL_SETTINGS_27 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_27
+#ifndef CONF_EDGSEL_27
+#define CONF_EDGSEL_27 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_27
+#ifndef CONF_PATH_27
+#define CONF_PATH_27 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_27
+#ifndef CONF_EVGEN_27
+#define CONF_EVGEN_27 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_27
+#ifndef CONF_OVR_27
+#define CONF_OVR_27 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_27
+#ifndef CONF_EVD_27
+#define CONF_EVD_27 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_27
+#ifndef CONF_ONDEMAND_27
+#define CONF_ONDEMAND_27 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_27
+#ifndef CONF_RUNSTDBY_27
+#define CONF_RUNSTDBY_27 0
+#endif
+
+// </e>
+
+// <e> Channel 28 settings
+// <id> evsys_channel_setting_28
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_28
+#define CONF_EVSYS_CHANNEL_SETTINGS_28 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_28
+#ifndef CONF_EDGSEL_28
+#define CONF_EDGSEL_28 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_28
+#ifndef CONF_PATH_28
+#define CONF_PATH_28 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_28
+#ifndef CONF_EVGEN_28
+#define CONF_EVGEN_28 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_28
+#ifndef CONF_OVR_28
+#define CONF_OVR_28 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_28
+#ifndef CONF_EVD_28
+#define CONF_EVD_28 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_28
+#ifndef CONF_ONDEMAND_28
+#define CONF_ONDEMAND_28 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_28
+#ifndef CONF_RUNSTDBY_28
+#define CONF_RUNSTDBY_28 0
+#endif
+
+// </e>
+
+// <e> Channel 29 settings
+// <id> evsys_channel_setting_29
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_29
+#define CONF_EVSYS_CHANNEL_SETTINGS_29 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_29
+#ifndef CONF_EDGSEL_29
+#define CONF_EDGSEL_29 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_29
+#ifndef CONF_PATH_29
+#define CONF_PATH_29 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_29
+#ifndef CONF_EVGEN_29
+#define CONF_EVGEN_29 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_29
+#ifndef CONF_OVR_29
+#define CONF_OVR_29 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_29
+#ifndef CONF_EVD_29
+#define CONF_EVD_29 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_29
+#ifndef CONF_ONDEMAND_29
+#define CONF_ONDEMAND_29 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_29
+#ifndef CONF_RUNSTDBY_29
+#define CONF_RUNSTDBY_29 0
+#endif
+
+// </e>
+
+// <e> Channel 30 settings
+// <id> evsys_channel_setting_30
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_30
+#define CONF_EVSYS_CHANNEL_SETTINGS_30 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_30
+#ifndef CONF_EDGSEL_30
+#define CONF_EDGSEL_30 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_30
+#ifndef CONF_PATH_30
+#define CONF_PATH_30 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_30
+#ifndef CONF_EVGEN_30
+#define CONF_EVGEN_30 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_30
+#ifndef CONF_OVR_30
+#define CONF_OVR_30 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_30
+#ifndef CONF_EVD_30
+#define CONF_EVD_30 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_30
+#ifndef CONF_ONDEMAND_30
+#define CONF_ONDEMAND_30 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_30
+#ifndef CONF_RUNSTDBY_30
+#define CONF_RUNSTDBY_30 0
+#endif
+
+// </e>
+
+// <e> Channel 31 settings
+// <id> evsys_channel_setting_31
+#ifndef CONF_EVSYS_CHANNEL_SETTINGS_31
+#define CONF_EVSYS_CHANNEL_SETTINGS_31 0
+#endif
+
+// <y> Edge detection
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val"> No event output when using the resynchronized or synchronous path
+// <EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val"> Event is detected on the rising edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val"> Event is detected on the falling edge of the signal from event generator
+// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
+// <id> evsys_edgsel_31
+#ifndef CONF_EDGSEL_31
+#define CONF_EDGSEL_31 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#endif
+
+// <y> Path selection
+// <i> Indicates which path for the event signal is chosen
+// <EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val"> Synchronous path
+// <EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val"> Resynchronized path
+// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
+// <id> evsys_path_31
+#ifndef CONF_PATH_31
+#define CONF_PATH_31 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#endif
+
+// <o> Event generator
+// <i> Determines event generator for channel
+// <0x0=>No event generator
+// <0x1=>XOSC Clock Failure 0
+// <0x2=>XOSC Clock Failure 1
+// <0x3=>XOSC32K Clock Failure
+// <0x4=>RTC period 0
+// <0x5=>RTC period 1
+// <0x6=>RTC period 2
+// <0x7=>RTC period 3
+// <0x8=>RTC period 4
+// <0x9=>RTC period 5
+// <0xA=>RTC period 6
+// <0xB=>RTC period 7
+// <0xC=>RTC compare 0
+// <0xD=>RTC compare 1
+// <0xE=>RTC compare 2
+// <0xF=>RTC compare 3
+// <0x10=>RTC Tamper Detection
+// <0x11=>RTC overflow
+// <0x12=>EIC external interrupt 0
+// <0x13=>EIC external interrupt 1
+// <0x14=>EIC external interrupt 2
+// <0x15=>EIC external interrupt 3
+// <0x16=>EIC external interrupt 4
+// <0x17=>EIC external interrupt 5
+// <0x18=>EIC external interrupt 6
+// <0x19=>EIC external interrupt 7
+// <0x1A=>EIC external interrupt 8
+// <0x1B=>EIC external interrupt 9
+// <0x1C=>EIC external interrupt 10
+// <0x1D=>EIC external interrupt 11
+// <0x1E=>EIC external interrupt 12
+// <0x1F=>EIC external interrupt 13
+// <0x20=>EIC external interrupt 14
+// <0x21=>EIC external interrupt 15
+// <0x22=>DMAC channel 0
+// <0x23=>DMAC channel 1
+// <0x24=>DMAC channel 2
+// <0x25=>DMAC channel 3
+// <0x28=>PAC access error
+// <0x29=>TCC0 overflow
+// <0x2A=>TCC0 trig
+// <0x2B=>TCC0 counter
+// <0x2C=>TCC0 match/capture 0
+// <0x2D=>TCC0 match/capture 1
+// <0x2E=>TCC0 match/capture 2
+// <0x2F=>TCC0 match/capture 3
+// <0x30=>TCC0 match/capture 4
+// <0x31=>TCC0 match/capture 5
+// <0x32=>TCC1 overflow
+// <0x33=>TCC1 trig
+// <0x34=>TCC1 counter
+// <0x35=>TCC1 match/capture 0
+// <0x36=>TCC1 match/capture 1
+// <0x37=>TCC1 match/capture 2
+// <0x38=>TCC1 match/capture 3
+// <0x39=>TCC2 overflow
+// <0x3A=>TCC2 trig
+// <0x3B=>TCC2 counter
+// <0x3C=>TCC2 match/capture 0
+// <0x3D=>TCC2 match/capture 1
+// <0x3E=>TCC2 match/capture 2
+// <0x3F=>TCC3 overflow
+// <0x40=>TCC3 trig
+// <0x41=>TCC3 counter
+// <0x42=>TCC3 match/capture 0
+// <0x43=>TCC3 match/capture 1
+// <0x44=>TCC4 overflow
+// <0x45=>TCC4 trig
+// <0x46=>TCC4 counter
+// <0x47=>TCC4 match/capture 0
+// <0x48=>TCC4 match/capture 1
+// <0x49=>TC0 overflow
+// <0x4A=>TC0 match/capture 0
+// <0x4B=>TC0 match/capture 1
+// <0x4C=>TC1 overflow
+// <0x4D=>TC1 match/capture 0
+// <0x4E=>TC1 match/capture 1
+// <0x4F=>TC2 overflow
+// <0x50=>TC2 match/capture 0
+// <0x51=>TC2 match/capture 1
+// <0x52=>TC3 overflow
+// <0x53=>TC3 match/capture 0
+// <0x54=>TC3 match/capture 1
+// <0x55=>TC4 overflow
+// <0x56=>TC4 match/capture 0
+// <0x57=>TC4 match/capture 1
+// <0x58=>TC5 overflow
+// <0x59=>TC5 match/capture 0
+// <0x5A=>TC5 match/capture 1
+// <0x5B=>TC6 overflow
+// <0x5C=>TC6 match/capture 0
+// <0x5D=>TC6 match/capture 1
+// <0x5E=>TC7 overflow
+// <0x5F=>TC7 match/capture 0
+// <0x60=>TC7 match/capture 1
+// <0x61=>PDEC overflow
+// <0x62=>PDEC error
+// <0x63=>PDEC direction
+// <0x64=>PDEC VLC
+// <0x65=>PDEC match channel 0
+// <0x66=>PDEC match channel 1
+// <0x67=>ADC0 result ready
+// <0x68=>ADC0 window monitor
+// <0x69=>ADC1 result ready
+// <0x6A=>ADC1 window monitor
+// <0x6B=>AC comparator 0
+// <0x6C=>AC comparator 1
+// <0x6D=>AC window 0
+// <0x6E=>DAC data buffer empty 0
+// <0x6F=>DAC data buffer empty 1
+// <0x70=>DAC result ready 0
+// <0x71=>DAC result ready 1
+// <0x73=>TRNG Data Ready
+// <0x74=>CCL LUT output 0
+// <0x75=>CCL LUT output 1
+// <0x76=>CCL LUT output 2
+// <0x77=>CCL LUT output 3
+// <id> evsys_evgen_31
+#ifndef CONF_EVGEN_31
+#define CONF_EVGEN_31 0
+#endif
+
+// <q> Overrun channel interrupt
+// <i> Indicates whether overrun channel interrupt is enabled or not
+// <id> evsys_ovr_31
+#ifndef CONF_OVR_31
+#define CONF_OVR_31 0
+#endif
+
+// <q> Event detected interrupt
+// <i> Indicates whether event detected interrupt is enabled or not
+// <id> evsys_evd_31
+#ifndef CONF_EVD_31
+#define CONF_EVD_31 0
+#endif
+
+// <q> On demand clock
+// <i> Indicates whether clock for channel is requested on demand or not
+// <id> evsys_ondemand_31
+#ifndef CONF_ONDEMAND_31
+#define CONF_ONDEMAND_31 0
+#endif
+
+// <q> Run is standby mode
+// <i> Indicates whether channel is enabled in standby sleep mode
+// <id> evsys_runstdby_31
+#ifndef CONF_RUNSTDBY_31
+#define CONF_RUNSTDBY_31 0
+#endif
+
+// </e>
+
+// <h>  Event User Security Attribution Settings
+
+//</h>
+
+// <h> RTC events
+// <o> Channel selection for RTC Tamper Event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_0
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_0
+#define CONF_CHANNEL_0 0
+#endif
+//</h>
+
+// <h> PORT events
+// <o> Channel selection for PORT event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_1
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_1
+#define CONF_CHANNEL_1 2
+#endif
+
+// <o> Channel selection for PORT event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_2
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_2
+#define CONF_CHANNEL_2 7
+#endif
+
+// <o> Channel selection for PORT event 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_3
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_3
+#define CONF_CHANNEL_3 6
+#endif
+
+// <o> Channel selection for PORT event 3
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_4
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_4
+#define CONF_CHANNEL_4 9
+#endif
+//</h>
+
+// <h> DMAC events
+// <o> Channel selection for DMAC channel 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_5
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_5
+#define CONF_CHANNEL_5 0
+#endif
+
+// <o> Channel selection for DMAC channel 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_6
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_6
+#define CONF_CHANNEL_6 0
+#endif
+
+// <o> Channel selection for DMAC channel 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_7
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_7
+#define CONF_CHANNEL_7 0
+#endif
+
+// <o> Channel selection for DMAC channel 3
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_8
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_8
+#define CONF_CHANNEL_8 0
+#endif
+
+// <o> Channel selection for DMAC channel 4
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_9
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_9
+#define CONF_CHANNEL_9 1
+#endif
+
+// <o> Channel selection for DMAC channel 5
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_10
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_10
+#define CONF_CHANNEL_10 6
+#endif
+
+// <o> Channel selection for DMAC channel 6
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_11
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_11
+#define CONF_CHANNEL_11 0
+#endif
+
+// <o> Channel selection for DMAC channel 7
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_12
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_12
+#define CONF_CHANNEL_12 3
+#endif
+//</h>
+
+// <h> Reserved
+#ifndef CONF_CHANNEL_13
+#define CONF_CHANNEL_13 0
+#endif
+
+#ifndef CONF_CHANNEL_14
+#define CONF_CHANNEL_14 0
+#endif
+
+#ifndef CONF_CHANNEL_15
+#define CONF_CHANNEL_15 0
+#endif
+
+#ifndef CONF_CHANNEL_16
+#define CONF_CHANNEL_16 0
+#endif
+//</h>
+
+// <h> TCC events
+// <o> Channel selection for TCC0 Event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_17
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_17
+#define CONF_CHANNEL_17 0
+#endif
+
+// <o> Channel selection for TCC0 Event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_18
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_18
+#define CONF_CHANNEL_18 0
+#endif
+
+// <o> Channel selection for TCC0 match/capture 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_19
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_19
+#define CONF_CHANNEL_19 0
+#endif
+
+// <o> Channel selection for TCC0 match/capture 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_20
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_20
+#define CONF_CHANNEL_20 0
+#endif
+
+// <o> Channel selection for TCC0 match/capture 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_21
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_21
+#define CONF_CHANNEL_21 0
+#endif
+
+// <o> Channel selection for TCC0 match/capture 3
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_22
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_22
+#define CONF_CHANNEL_22 0
+#endif
+
+// <o> Channel selection for TCC0 match/capture 4
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_23
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_23
+#define CONF_CHANNEL_23 0
+#endif
+
+// <o> Channel selection for TCC0 match/capture 5
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_24
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_24
+#define CONF_CHANNEL_24 0
+#endif
+
+// <o> Channel selection for TCC1 Event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_25
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_25
+#define CONF_CHANNEL_25 0
+#endif
+
+// <o> Channel selection for TCC1 Event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_26
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_26
+#define CONF_CHANNEL_26 0
+#endif
+
+// <o> Channel selection for TCC1 match/capture 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_27
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_27
+#define CONF_CHANNEL_27 0
+#endif
+
+// <o> Channel selection for TCC1 match/capture 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_28
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_28
+#define CONF_CHANNEL_28 0
+#endif
+
+// <o> Channel selection for TCC1 match/capture 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_29
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_29
+#define CONF_CHANNEL_29 0
+#endif
+
+// <o> Channel selection for TCC1 match/capture 3
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_30
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_30
+#define CONF_CHANNEL_30 0
+#endif
+
+// <o> Channel selection for TCC2 Event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_31
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_31
+#define CONF_CHANNEL_31 0
+#endif
+
+// <o> Channel selection for TCC2 Event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_32
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_32
+#define CONF_CHANNEL_32 0
+#endif
+
+// <o> Channel selection for TCC2 match/capture 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_33
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_33
+#define CONF_CHANNEL_33 0
+#endif
+
+// <o> Channel selection for TCC2 match/capture 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_34
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_34
+#define CONF_CHANNEL_34 0
+#endif
+
+// <o> Channel selection for TCC2 match/capture 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_35
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_35
+#define CONF_CHANNEL_35 0
+#endif
+
+// <o> Channel selection for TCC3 Event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_36
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_36
+#define CONF_CHANNEL_36 0
+#endif
+
+// <o> Channel selection for TCC3 Event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_37
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_37
+#define CONF_CHANNEL_37 0
+#endif
+
+// <o> Channel selection for TCC3 match/capture 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_38
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_38
+#define CONF_CHANNEL_38 0
+#endif
+
+// <o> Channel selection for TCC3 match/capture 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_39
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_39
+#define CONF_CHANNEL_39 0
+#endif
+
+// <o> Channel selection for TCC4 Event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_40
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_40
+#define CONF_CHANNEL_40 0
+#endif
+
+// <o> Channel selection for TCC4 Event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_41
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_41
+#define CONF_CHANNEL_41 0
+#endif
+
+// <o> Channel selection for TCC4 match/capture 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_42
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_42
+#define CONF_CHANNEL_42 0
+#endif
+
+// <o> Channel selection for TCC4 match/capture 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_43
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_43
+#define CONF_CHANNEL_43 0
+#endif
+//</h>
+
+// <h> TC events
+// <o> Channel selection for TC0 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_44
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_44
+#define CONF_CHANNEL_44 0
+#endif
+
+// <o> Channel selection for TC1 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_45
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_45
+#define CONF_CHANNEL_45 0
+#endif
+
+// <o> Channel selection for TC2 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_46
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_46
+#define CONF_CHANNEL_46 12
+#endif
+
+// <o> Channel selection for TC3 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_47
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_47
+#define CONF_CHANNEL_47 0
+#endif
+
+// <o> Channel selection for TC4 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_48
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_48
+#define CONF_CHANNEL_48 13
+#endif
+
+// <o> Channel selection for TC5 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_49
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_49
+#define CONF_CHANNEL_49 0
+#endif
+
+// <o> Channel selection for TC6 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_50
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_50
+#define CONF_CHANNEL_50 0
+#endif
+
+// <o> Channel selection for TC7 event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_51
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_51
+#define CONF_CHANNEL_51 0
+#endif
+//</h>
+
+// <h> PDEC events
+// <o> Channel selection for PDEC event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_52
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_52
+#define CONF_CHANNEL_52 0
+#endif
+
+// <o> Channel selection for PDEC event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_53
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_53
+#define CONF_CHANNEL_53 0
+#endif
+
+// <o> Channel selection for PDEC event 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_54
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_54
+#define CONF_CHANNEL_54 0
+#endif
+//</h>
+
+// <h> ADC events
+// <o> Channel selection for ADC0 start conversion event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_55
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_55
+#define CONF_CHANNEL_55 0
+#endif
+
+// <o> Channel selection for ADC0 flush event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_56
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_56
+#define CONF_CHANNEL_56 0
+#endif
+
+// <o> Channel selection for ADC1 start conversion event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_57
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_57
+#define CONF_CHANNEL_57 0
+#endif
+
+// <o> Channel selection for ADC1 flush event
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_58
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_58
+#define CONF_CHANNEL_58 0
+#endif
+//</h>
+
+// <h> AC events
+// <o> Channel selection for Start comparator event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_59
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_59
+#define CONF_CHANNEL_59 0
+#endif
+
+// <o> Channel selection for Start comparator event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_60
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_60
+#define CONF_CHANNEL_60 0
+#endif
+//</h>
+
+// <h> DAC events
+// <o> Channel selection for DAC Start event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_61
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_61
+#define CONF_CHANNEL_61 0
+#endif
+
+// <o> Channel selection for DAC Start event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_62
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_62
+#define CONF_CHANNEL_62 0
+#endif
+//</h>
+
+// <h> CCL events
+// <o> Channel selection for CCL input event 0
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_63
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_63
+#define CONF_CHANNEL_63 0
+#endif
+
+// <o> Channel selection for CCL input event 1
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_64
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_64
+#define CONF_CHANNEL_64 0
+#endif
+
+// <o> Channel selection for CCL input event 2
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_65
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_65
+#define CONF_CHANNEL_65 0
+#endif
+
+// <o> Channel selection for CCL input event 3
+// <0x0=>No channel output selected
+// <0x1=>Channel 0
+// <0x2=>Channel 1
+// <0x3=>Channel 2
+// <0x4=>Channel 3
+// <0x5=>Channel 4
+// <0x6=>Channel 5
+// <0x7=>Channel 6
+// <0x8=>Channel 7
+// <0x9=>Channel 8
+// <0xA=>Channel 9
+// <0xB=>Channel 10
+// <0xC=>Channel 11
+// <0xD=>Channel 12
+// <0xE=>Channel 13
+// <0xF=>Channel 14
+// <0x10=>Channel 15
+// <0x11=>Channel 16
+// <0x12=>Channel 17
+// <0x13=>Channel 18
+// <0x14=>Channel 19
+// <0x15=>Channel 20
+// <0x16=>Channel 21
+// <0x17=>Channel 22
+// <0x18=>Channel 23
+// <0x19=>Channel 24
+// <0x1A=>Channel 25
+// <0x1B=>Channel 26
+// <0x1C=>Channel 27
+// <0x1D=>Channel 28
+// <0x1E=>Channel 29
+// <0x1F=>Channel 30
+// <0x20=>Channel 31
+// <id> evsys_channel_66
+// <i> Indicates which channel is chosen for user
+#ifndef CONF_CHANNEL_66
+#define CONF_CHANNEL_66 0
+#endif
+//</h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_EVSYS_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_gclk_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_gclk_config.h
new file mode 100644
index 0000000..1d59d98
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_gclk_config.h
@@ -0,0 +1,920 @@
+/* Auto-generated config file hpl_gclk_config.h */
+#ifndef HPL_GCLK_CONFIG_H
+#define HPL_GCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> Generic clock generator 0 configuration
+// <i> Indicates whether generic clock 0 configuration is enabled or not
+// <id> enable_gclk_gen_0
+#ifndef CONF_GCLK_GENERATOR_0_CONFIG
+#define CONF_GCLK_GENERATOR_0_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 0 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 0
+// <id> gclk_gen_0_oscillator
+#ifndef CONF_GCLK_GEN_0_SOURCE
+#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_0_runstdby
+#ifndef CONF_GCLK_GEN_0_RUNSTDBY
+#define CONF_GCLK_GEN_0_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_0_div_sel
+#ifndef CONF_GCLK_GEN_0_DIVSEL
+#define CONF_GCLK_GEN_0_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_0_oe
+#ifndef CONF_GCLK_GEN_0_OE
+#define CONF_GCLK_GEN_0_OE 1
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_0_oov
+#ifndef CONF_GCLK_GEN_0_OOV
+#define CONF_GCLK_GEN_0_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_0_idc
+#ifndef CONF_GCLK_GEN_0_IDC
+#define CONF_GCLK_GEN_0_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_0_enable
+#ifndef CONF_GCLK_GEN_0_GENEN
+#define CONF_GCLK_GEN_0_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 0 division <0x0000-0xFFFF>
+// <id> gclk_gen_0_div
+#ifndef CONF_GCLK_GEN_0_DIV
+#define CONF_GCLK_GEN_0_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 1 configuration
+// <i> Indicates whether generic clock 1 configuration is enabled or not
+// <id> enable_gclk_gen_1
+#ifndef CONF_GCLK_GENERATOR_1_CONFIG
+#define CONF_GCLK_GENERATOR_1_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 1 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 1
+// <id> gclk_gen_1_oscillator
+#ifndef CONF_GCLK_GEN_1_SOURCE
+#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_1_runstdby
+#ifndef CONF_GCLK_GEN_1_RUNSTDBY
+#define CONF_GCLK_GEN_1_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_1_div_sel
+#ifndef CONF_GCLK_GEN_1_DIVSEL
+#define CONF_GCLK_GEN_1_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_1_oe
+#ifndef CONF_GCLK_GEN_1_OE
+#define CONF_GCLK_GEN_1_OE 1
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_1_oov
+#ifndef CONF_GCLK_GEN_1_OOV
+#define CONF_GCLK_GEN_1_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_1_idc
+#ifndef CONF_GCLK_GEN_1_IDC
+#define CONF_GCLK_GEN_1_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_1_enable
+#ifndef CONF_GCLK_GEN_1_GENEN
+#define CONF_GCLK_GEN_1_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 1 division <0x0000-0xFFFF>
+// <id> gclk_gen_1_div
+#ifndef CONF_GCLK_GEN_1_DIV
+#define CONF_GCLK_GEN_1_DIV 24
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 2 configuration
+// <i> Indicates whether generic clock 2 configuration is enabled or not
+// <id> enable_gclk_gen_2
+#ifndef CONF_GCLK_GENERATOR_2_CONFIG
+#define CONF_GCLK_GENERATOR_2_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 2 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 2
+// <id> gclk_gen_2_oscillator
+#ifndef CONF_GCLK_GEN_2_SOURCE
+#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSCULP32K
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_2_runstdby
+#ifndef CONF_GCLK_GEN_2_RUNSTDBY
+#define CONF_GCLK_GEN_2_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_2_div_sel
+#ifndef CONF_GCLK_GEN_2_DIVSEL
+#define CONF_GCLK_GEN_2_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_2_oe
+#ifndef CONF_GCLK_GEN_2_OE
+#define CONF_GCLK_GEN_2_OE 1
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_2_oov
+#ifndef CONF_GCLK_GEN_2_OOV
+#define CONF_GCLK_GEN_2_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_2_idc
+#ifndef CONF_GCLK_GEN_2_IDC
+#define CONF_GCLK_GEN_2_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_2_enable
+#ifndef CONF_GCLK_GEN_2_GENEN
+#define CONF_GCLK_GEN_2_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 2 division <0x0000-0xFFFF>
+// <id> gclk_gen_2_div
+#ifndef CONF_GCLK_GEN_2_DIV
+#define CONF_GCLK_GEN_2_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 3 configuration
+// <i> Indicates whether generic clock 3 configuration is enabled or not
+// <id> enable_gclk_gen_3
+#ifndef CONF_GCLK_GENERATOR_3_CONFIG
+#define CONF_GCLK_GENERATOR_3_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 3 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 3
+// <id> gclk_gen_3_oscillator
+#ifndef CONF_GCLK_GEN_3_SOURCE
+#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_3_runstdby
+#ifndef CONF_GCLK_GEN_3_RUNSTDBY
+#define CONF_GCLK_GEN_3_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_3_div_sel
+#ifndef CONF_GCLK_GEN_3_DIVSEL
+#define CONF_GCLK_GEN_3_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_3_oe
+#ifndef CONF_GCLK_GEN_3_OE
+#define CONF_GCLK_GEN_3_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_3_oov
+#ifndef CONF_GCLK_GEN_3_OOV
+#define CONF_GCLK_GEN_3_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_3_idc
+#ifndef CONF_GCLK_GEN_3_IDC
+#define CONF_GCLK_GEN_3_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_3_enable
+#ifndef CONF_GCLK_GEN_3_GENEN
+#define CONF_GCLK_GEN_3_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 3 division <0x0000-0xFFFF>
+// <id> gclk_gen_3_div
+#ifndef CONF_GCLK_GEN_3_DIV
+#define CONF_GCLK_GEN_3_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 4 configuration
+// <i> Indicates whether generic clock 4 configuration is enabled or not
+// <id> enable_gclk_gen_4
+#ifndef CONF_GCLK_GENERATOR_4_CONFIG
+#define CONF_GCLK_GENERATOR_4_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 4 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 4
+// <id> gclk_gen_4_oscillator
+#ifndef CONF_GCLK_GEN_4_SOURCE
+#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_4_runstdby
+#ifndef CONF_GCLK_GEN_4_RUNSTDBY
+#define CONF_GCLK_GEN_4_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_4_div_sel
+#ifndef CONF_GCLK_GEN_4_DIVSEL
+#define CONF_GCLK_GEN_4_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_4_oe
+#ifndef CONF_GCLK_GEN_4_OE
+#define CONF_GCLK_GEN_4_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_4_oov
+#ifndef CONF_GCLK_GEN_4_OOV
+#define CONF_GCLK_GEN_4_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_4_idc
+#ifndef CONF_GCLK_GEN_4_IDC
+#define CONF_GCLK_GEN_4_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_4_enable
+#ifndef CONF_GCLK_GEN_4_GENEN
+#define CONF_GCLK_GEN_4_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 4 division <0x0000-0xFFFF>
+// <id> gclk_gen_4_div
+#ifndef CONF_GCLK_GEN_4_DIV
+#define CONF_GCLK_GEN_4_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 5 configuration
+// <i> Indicates whether generic clock 5 configuration is enabled or not
+// <id> enable_gclk_gen_5
+#ifndef CONF_GCLK_GENERATOR_5_CONFIG
+#define CONF_GCLK_GENERATOR_5_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 5 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 5
+// <id> gclk_gen_5_oscillator
+#ifndef CONF_GCLK_GEN_5_SOURCE
+#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_5_runstdby
+#ifndef CONF_GCLK_GEN_5_RUNSTDBY
+#define CONF_GCLK_GEN_5_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_5_div_sel
+#ifndef CONF_GCLK_GEN_5_DIVSEL
+#define CONF_GCLK_GEN_5_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_5_oe
+#ifndef CONF_GCLK_GEN_5_OE
+#define CONF_GCLK_GEN_5_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_5_oov
+#ifndef CONF_GCLK_GEN_5_OOV
+#define CONF_GCLK_GEN_5_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_5_idc
+#ifndef CONF_GCLK_GEN_5_IDC
+#define CONF_GCLK_GEN_5_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_5_enable
+#ifndef CONF_GCLK_GEN_5_GENEN
+#define CONF_GCLK_GEN_5_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 5 division <0x0000-0xFFFF>
+// <id> gclk_gen_5_div
+#ifndef CONF_GCLK_GEN_5_DIV
+#define CONF_GCLK_GEN_5_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 6 configuration
+// <i> Indicates whether generic clock 6 configuration is enabled or not
+// <id> enable_gclk_gen_6
+#ifndef CONF_GCLK_GENERATOR_6_CONFIG
+#define CONF_GCLK_GENERATOR_6_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 6 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 6
+// <id> gclk_gen_6_oscillator
+#ifndef CONF_GCLK_GEN_6_SOURCE
+#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_6_runstdby
+#ifndef CONF_GCLK_GEN_6_RUNSTDBY
+#define CONF_GCLK_GEN_6_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_6_div_sel
+#ifndef CONF_GCLK_GEN_6_DIVSEL
+#define CONF_GCLK_GEN_6_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_6_oe
+#ifndef CONF_GCLK_GEN_6_OE
+#define CONF_GCLK_GEN_6_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_6_oov
+#ifndef CONF_GCLK_GEN_6_OOV
+#define CONF_GCLK_GEN_6_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_6_idc
+#ifndef CONF_GCLK_GEN_6_IDC
+#define CONF_GCLK_GEN_6_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_6_enable
+#ifndef CONF_GCLK_GEN_6_GENEN
+#define CONF_GCLK_GEN_6_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 6 division <0x0000-0xFFFF>
+// <id> gclk_gen_6_div
+#ifndef CONF_GCLK_GEN_6_DIV
+#define CONF_GCLK_GEN_6_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 7 configuration
+// <i> Indicates whether generic clock 7 configuration is enabled or not
+// <id> enable_gclk_gen_7
+#ifndef CONF_GCLK_GENERATOR_7_CONFIG
+#define CONF_GCLK_GENERATOR_7_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 7 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 7
+// <id> gclk_gen_7_oscillator
+#ifndef CONF_GCLK_GEN_7_SOURCE
+#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_7_runstdby
+#ifndef CONF_GCLK_GEN_7_RUNSTDBY
+#define CONF_GCLK_GEN_7_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_7_div_sel
+#ifndef CONF_GCLK_GEN_7_DIVSEL
+#define CONF_GCLK_GEN_7_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_7_oe
+#ifndef CONF_GCLK_GEN_7_OE
+#define CONF_GCLK_GEN_7_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_7_oov
+#ifndef CONF_GCLK_GEN_7_OOV
+#define CONF_GCLK_GEN_7_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_7_idc
+#ifndef CONF_GCLK_GEN_7_IDC
+#define CONF_GCLK_GEN_7_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_7_enable
+#ifndef CONF_GCLK_GEN_7_GENEN
+#define CONF_GCLK_GEN_7_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 7 division <0x0000-0xFFFF>
+// <id> gclk_gen_7_div
+#ifndef CONF_GCLK_GEN_7_DIV
+#define CONF_GCLK_GEN_7_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 8 configuration
+// <i> Indicates whether generic clock 8 configuration is enabled or not
+// <id> enable_gclk_gen_8
+#ifndef CONF_GCLK_GENERATOR_8_CONFIG
+#define CONF_GCLK_GENERATOR_8_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 8 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 8
+// <id> gclk_gen_8_oscillator
+#ifndef CONF_GCLK_GEN_8_SOURCE
+#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_8_runstdby
+#ifndef CONF_GCLK_GEN_8_RUNSTDBY
+#define CONF_GCLK_GEN_8_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_8_div_sel
+#ifndef CONF_GCLK_GEN_8_DIVSEL
+#define CONF_GCLK_GEN_8_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_8_oe
+#ifndef CONF_GCLK_GEN_8_OE
+#define CONF_GCLK_GEN_8_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_8_oov
+#ifndef CONF_GCLK_GEN_8_OOV
+#define CONF_GCLK_GEN_8_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_8_idc
+#ifndef CONF_GCLK_GEN_8_IDC
+#define CONF_GCLK_GEN_8_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_8_enable
+#ifndef CONF_GCLK_GEN_8_GENEN
+#define CONF_GCLK_GEN_8_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 8 division <0x0000-0xFFFF>
+// <id> gclk_gen_8_div
+#ifndef CONF_GCLK_GEN_8_DIV
+#define CONF_GCLK_GEN_8_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 9 configuration
+// <i> Indicates whether generic clock 9 configuration is enabled or not
+// <id> enable_gclk_gen_9
+#ifndef CONF_GCLK_GENERATOR_9_CONFIG
+#define CONF_GCLK_GENERATOR_9_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 9 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 9
+// <id> gclk_gen_9_oscillator
+#ifndef CONF_GCLK_GEN_9_SOURCE
+#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_9_runstdby
+#ifndef CONF_GCLK_GEN_9_RUNSTDBY
+#define CONF_GCLK_GEN_9_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_9_div_sel
+#ifndef CONF_GCLK_GEN_9_DIVSEL
+#define CONF_GCLK_GEN_9_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_9_oe
+#ifndef CONF_GCLK_GEN_9_OE
+#define CONF_GCLK_GEN_9_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_9_oov
+#ifndef CONF_GCLK_GEN_9_OOV
+#define CONF_GCLK_GEN_9_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_9_idc
+#ifndef CONF_GCLK_GEN_9_IDC
+#define CONF_GCLK_GEN_9_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_9_enable
+#ifndef CONF_GCLK_GEN_9_GENEN
+#define CONF_GCLK_GEN_9_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 9 division <0x0000-0xFFFF>
+// <id> gclk_gen_9_div
+#ifndef CONF_GCLK_GEN_9_DIV
+#define CONF_GCLK_GEN_9_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 10 configuration
+// <i> Indicates whether generic clock 10 configuration is enabled or not
+// <id> enable_gclk_gen_10
+#ifndef CONF_GCLK_GENERATOR_10_CONFIG
+#define CONF_GCLK_GENERATOR_10_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 10 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 10
+// <id> gclk_gen_10_oscillator
+#ifndef CONF_GCLK_GEN_10_SOURCE
+#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_10_runstdby
+#ifndef CONF_GCLK_GEN_10_RUNSTDBY
+#define CONF_GCLK_GEN_10_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_10_div_sel
+#ifndef CONF_GCLK_GEN_10_DIVSEL
+#define CONF_GCLK_GEN_10_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_10_oe
+#ifndef CONF_GCLK_GEN_10_OE
+#define CONF_GCLK_GEN_10_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_10_oov
+#ifndef CONF_GCLK_GEN_10_OOV
+#define CONF_GCLK_GEN_10_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_10_idc
+#ifndef CONF_GCLK_GEN_10_IDC
+#define CONF_GCLK_GEN_10_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_10_enable
+#ifndef CONF_GCLK_GEN_10_GENEN
+#define CONF_GCLK_GEN_10_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 10 division <0x0000-0xFFFF>
+// <id> gclk_gen_10_div
+#ifndef CONF_GCLK_GEN_10_DIV
+#define CONF_GCLK_GEN_10_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 11 configuration
+// <i> Indicates whether generic clock 11 configuration is enabled or not
+// <id> enable_gclk_gen_11
+#ifndef CONF_GCLK_GENERATOR_11_CONFIG
+#define CONF_GCLK_GENERATOR_11_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 11 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 11
+// <id> gclk_gen_11_oscillator
+#ifndef CONF_GCLK_GEN_11_SOURCE
+#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_11_runstdby
+#ifndef CONF_GCLK_GEN_11_RUNSTDBY
+#define CONF_GCLK_GEN_11_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_11_div_sel
+#ifndef CONF_GCLK_GEN_11_DIVSEL
+#define CONF_GCLK_GEN_11_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_11_oe
+#ifndef CONF_GCLK_GEN_11_OE
+#define CONF_GCLK_GEN_11_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_11_oov
+#ifndef CONF_GCLK_GEN_11_OOV
+#define CONF_GCLK_GEN_11_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_11_idc
+#ifndef CONF_GCLK_GEN_11_IDC
+#define CONF_GCLK_GEN_11_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_11_enable
+#ifndef CONF_GCLK_GEN_11_GENEN
+#define CONF_GCLK_GEN_11_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 11 division <0x0000-0xFFFF>
+// <id> gclk_gen_11_div
+#ifndef CONF_GCLK_GEN_11_DIV
+#define CONF_GCLK_GEN_11_DIV 1
+#endif
+// </h>
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_GCLK_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_mclk_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_mclk_config.h
new file mode 100644
index 0000000..a5a7de5
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_mclk_config.h
@@ -0,0 +1,104 @@
+/* Auto-generated config file hpl_mclk_config.h */
+#ifndef HPL_MCLK_CONFIG_H
+#define HPL_MCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+// <e> System Configuration
+// <i> Indicates whether configuration for system is enabled or not
+// <id> enable_cpu_clock
+#ifndef CONF_SYSTEM_CONFIG
+#define CONF_SYSTEM_CONFIG 1
+#endif
+
+// <h> Basic settings
+// <y> CPU Clock source
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <i> This defines the clock source for the CPU
+// <id> cpu_clock_source
+#ifndef CONF_CPU_SRC
+#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> CPU Clock Division Factor
+// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
+// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
+// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
+// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
+// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
+// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
+// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
+// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
+// <i> Prescalar for CPU clock
+// <id> cpu_div
+#ifndef CONF_MCLK_CPUDIV
+#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
+#endif
+// <y> Low Power Clock Division
+// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
+// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
+// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
+// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
+// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
+// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
+// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
+// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
+// <id> mclk_arch_lpdiv
+#ifndef CONF_MCLK_LPDIV
+#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
+#endif
+
+// <y> Backup Clock Division
+// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
+// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
+// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
+// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
+// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
+// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
+// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
+// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
+// <id> mclk_arch_bupdiv
+#ifndef CONF_MCLK_BUPDIV
+#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
+#endif
+// <y> High-Speed Clock Division
+// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
+// <id> mclk_arch_hsdiv
+#ifndef CONF_MCLK_HSDIV
+#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
+#endif
+// </h>
+
+// <h> NVM Settings
+// <o> NVM Wait States
+// <i> These bits select the number of wait states for a read operation.
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <id> nvm_wait_states
+#ifndef CONF_NVM_WAIT_STATE
+#define CONF_NVM_WAIT_STATE 0
+#endif
+
+// </h>
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_MCLK_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_osc32kctrl_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_osc32kctrl_config.h
new file mode 100644
index 0000000..e7fddd2
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_osc32kctrl_config.h
@@ -0,0 +1,165 @@
+/* Auto-generated config file hpl_osc32kctrl_config.h */
+#ifndef HPL_OSC32KCTRL_CONFIG_H
+#define HPL_OSC32KCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> RTC Source configuration
+// <id> enable_rtc_source
+#ifndef CONF_RTCCTRL_CONFIG
+#define CONF_RTCCTRL_CONFIG 0
+#endif
+
+// <h> RTC source control
+// <y> RTC Clock Source Selection
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <i> This defines the clock source for RTC
+// <id> rtc_source_oscillator
+#ifndef CONF_RTCCTRL_SRC
+#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
+#endif
+
+// <q> Use 1 kHz output
+// <id> rtc_1khz_selection
+#ifndef CONF_RTCCTRL_1KHZ
+
+#define CONF_RTCCTRL_1KHZ 0
+
+#endif
+
+#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
+#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
+#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
+#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
+#else
+#error unexpected CONF_RTCCTRL_SRC
+#endif
+
+// </h>
+// </e>
+
+// <e> 32kHz External Crystal Oscillator Configuration
+// <i> Indicates whether configuration for External 32K Osc is enabled or not
+// <id> enable_xosc32k
+#ifndef CONF_XOSC32K_CONFIG
+#define CONF_XOSC32K_CONFIG 0
+#endif
+
+// <h> 32kHz External Crystal Oscillator Control
+// <q> Oscillator enable
+// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
+// <id> xosc32k_arch_enable
+#ifndef CONF_XOSC32K_ENABLE
+#define CONF_XOSC32K_ENABLE 0
+#endif
+
+// <o> Start-Up Time
+// <0x0=>62592us
+// <0x1=>125092us
+// <0x2=>500092us
+// <0x3=>1000092us
+// <0x4=>2000092us
+// <0x5=>4000092us
+// <0x6=>8000092us
+// <id> xosc32k_arch_startup
+#ifndef CONF_XOSC32K_STARTUP
+#define CONF_XOSC32K_STARTUP 0x0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> xosc32k_arch_ondemand
+#ifndef CONF_XOSC32K_ONDEMAND
+#define CONF_XOSC32K_ONDEMAND 1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> xosc32k_arch_runstdby
+#ifndef CONF_XOSC32K_RUNSTDBY
+#define CONF_XOSC32K_RUNSTDBY 0
+#endif
+
+// <q> 1kHz Output Enable
+// <i> Indicates whether 1kHz Output is enabled or not
+// <id> xosc32k_arch_en1k
+#ifndef CONF_XOSC32K_EN1K
+#define CONF_XOSC32K_EN1K 0
+#endif
+
+// <q> 32kHz Output Enable
+// <i> Indicates whether 32kHz Output is enabled or not
+// <id> xosc32k_arch_en32k
+#ifndef CONF_XOSC32K_EN32K
+#define CONF_XOSC32K_EN32K 0
+#endif
+
+// <q> Clock Switch Back
+// <i> Indicates whether Clock Switch Back is enabled or not
+// <id> xosc32k_arch_swben
+#ifndef CONF_XOSC32K_SWBEN
+#define CONF_XOSC32K_SWBEN 0
+#endif
+
+// <q> Clock Failure Detector
+// <i> Indicates whether Clock Failure Detector is enabled or not
+// <id> xosc32k_arch_cfden
+#ifndef CONF_XOSC32K_CFDEN
+#define CONF_XOSC32K_CFDEN 0
+#endif
+
+// <q> Clock Failure Detector Event Out
+// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
+// <id> xosc32k_arch_cfdeo
+#ifndef CONF_XOSC32K_CFDEO
+#define CONF_XOSC32K_CFDEO 0
+#endif
+
+// <q> Crystal connected to XIN32/XOUT32 Enable
+// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// <id> xosc32k_arch_xtalen
+#ifndef CONF_XOSC32K_XTALEN
+#define CONF_XOSC32K_XTALEN 1
+#endif
+
+// <o> Control Gain Mode
+// <0x0=>Low Power mode
+// <0x1=>Standard mode
+// <0x2=>High Speed mode
+// <id> xosc32k_arch_cgm
+#ifndef CONF_XOSC32K_CGM
+#define CONF_XOSC32K_CGM 0x1
+#endif
+
+// </h>
+// </e>
+
+// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
+// <i> Indicates whether configuration for OSCULP32K is enabled or not
+// <id> enable_osculp32k
+#ifndef CONF_OSCULP32K_CONFIG
+#define CONF_OSCULP32K_CONFIG 1
+#endif
+
+// <h> 32kHz Ultra Low Power Internal Oscillator Control
+
+// <q> Oscillator Calibration Control
+// <i> Indicates whether Oscillator Calibration is enabled or not
+// <id> osculp32k_calib_enable
+#ifndef CONF_OSCULP32K_CALIB_ENABLE
+#define CONF_OSCULP32K_CALIB_ENABLE 0
+#endif
+
+// <o> Oscillator Calibration <0x0-0x3F>
+// <id> osculp32k_calib
+#ifndef CONF_OSCULP32K_CALIB
+#define CONF_OSCULP32K_CALIB 0x0
+#endif
+
+// </h>
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_OSC32KCTRL_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_oscctrl_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_oscctrl_config.h
new file mode 100644
index 0000000..b62c2bc
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_oscctrl_config.h
@@ -0,0 +1,640 @@
+/* Auto-generated config file hpl_oscctrl_config.h */
+#ifndef HPL_OSCCTRL_CONFIG_H
+#define HPL_OSCCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> External Multipurpose Crystal Oscillator Configuration
+// <i> Indicates whether configuration for XOSC0 is enabled or not
+// <id> enable_xosc0
+#ifndef CONF_XOSC0_CONFIG
+#define CONF_XOSC0_CONFIG 0
+#endif
+
+// <o> Frequency <8000000-48000000>
+// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
+// <id> xosc0_frequency
+#ifndef CONF_XOSC_FREQUENCY
+#define CONF_XOSC0_FREQUENCY 12000000
+#endif
+
+// <h> External Multipurpose Crystal Oscillator Control
+// <q> Oscillator enable
+// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
+// <id> xosc0_arch_enable
+#ifndef CONF_XOSC0_ENABLE
+#define CONF_XOSC0_ENABLE 0
+#endif
+
+// <o> Start-Up Time
+// <0x0=>31us
+// <0x1=>61us
+// <0x2=>122us
+// <0x3=>244us
+// <0x4=>488us
+// <0x5=>977us
+// <0x6=>1953us
+// <0x7=>3906us
+// <0x8=>7813us
+// <0x9=>15625us
+// <0xA=>31250us
+// <0xB=>62500us
+// <0xC=>125000us
+// <0xD=>250000us
+// <0xE=>500000us
+// <0xF=>1000000us
+// <id> xosc0_arch_startup
+#ifndef CONF_XOSC0_STARTUP
+#define CONF_XOSC0_STARTUP 0
+#endif
+
+// <q> Clock Switch Back
+// <i> Indicates whether Clock Switch Back is enabled or not
+// <id> xosc0_arch_swben
+#ifndef CONF_XOSC0_SWBEN
+#define CONF_XOSC0_SWBEN 0
+#endif
+
+// <q> Clock Failure Detector
+// <i> Indicates whether Clock Failure Detector is enabled or not
+// <id> xosc0_arch_cfden
+#ifndef CONF_XOSC0_CFDEN
+#define CONF_XOSC0_CFDEN 0
+#endif
+
+// <q> Automatic Loop Control Enable
+// <i> Indicates whether Automatic Loop Control is enabled or not
+// <id> xosc0_arch_enalc
+#ifndef CONF_XOSC0_ENALC
+#define CONF_XOSC0_ENALC 0
+#endif
+
+// <q> Low Buffer Gain Enable
+// <i> Indicates whether Low Buffer Gain is enabled or not
+// <id> xosc0_arch_lowbufgain
+#ifndef CONF_XOSC0_LOWBUFGAIN
+#define CONF_XOSC0_LOWBUFGAIN 0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> xosc0_arch_ondemand
+#ifndef CONF_XOSC0_ONDEMAND
+#define CONF_XOSC0_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> xosc0_arch_runstdby
+#ifndef CONF_XOSC0_RUNSTDBY
+#define CONF_XOSC0_RUNSTDBY 0
+#endif
+
+// <q> Crystal connected to XIN/XOUT Enable
+// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// <id> xosc0_arch_xtalen
+#ifndef CONF_XOSC0_XTALEN
+#define CONF_XOSC0_XTALEN 0
+#endif
+//</h>
+//</e>
+
+#if CONF_XOSC0_FREQUENCY >= 32000000
+#define CONF_XOSC0_CFDPRESC 0x0
+#define CONF_XOSC0_IMULT 0x7
+#define CONF_XOSC0_IPTAT 0x3
+#elif CONF_XOSC0_FREQUENCY >= 24000000
+#define CONF_XOSC0_CFDPRESC 0x1
+#define CONF_XOSC0_IMULT 0x6
+#define CONF_XOSC0_IPTAT 0x3
+#elif CONF_XOSC0_FREQUENCY >= 16000000
+#define CONF_XOSC0_CFDPRESC 0x2
+#define CONF_XOSC0_IMULT 0x5
+#define CONF_XOSC0_IPTAT 0x3
+#elif CONF_XOSC0_FREQUENCY >= 8000000
+#define CONF_XOSC0_CFDPRESC 0x3
+#define CONF_XOSC0_IMULT 0x4
+#define CONF_XOSC0_IPTAT 0x3
+#endif
+
+// <e> External Multipurpose Crystal Oscillator Configuration
+// <i> Indicates whether configuration for XOSC1 is enabled or not
+// <id> enable_xosc1
+#ifndef CONF_XOSC1_CONFIG
+#define CONF_XOSC1_CONFIG 0
+#endif
+
+// <o> Frequency <8000000-48000000>
+// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
+// <id> xosc1_frequency
+#ifndef CONF_XOSC_FREQUENCY
+#define CONF_XOSC1_FREQUENCY 12000000
+#endif
+
+// <h> External Multipurpose Crystal Oscillator Control
+// <q> Oscillator enable
+// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
+// <id> xosc1_arch_enable
+#ifndef CONF_XOSC1_ENABLE
+#define CONF_XOSC1_ENABLE 0
+#endif
+
+// <o> Start-Up Time
+// <0x0=>31us
+// <0x1=>61us
+// <0x2=>122us
+// <0x3=>244us
+// <0x4=>488us
+// <0x5=>977us
+// <0x6=>1953us
+// <0x7=>3906us
+// <0x8=>7813us
+// <0x9=>15625us
+// <0xA=>31250us
+// <0xB=>62500us
+// <0xC=>125000us
+// <0xD=>250000us
+// <0xE=>500000us
+// <0xF=>1000000us
+// <id> xosc1_arch_startup
+#ifndef CONF_XOSC1_STARTUP
+#define CONF_XOSC1_STARTUP 0
+#endif
+
+// <q> Clock Switch Back
+// <i> Indicates whether Clock Switch Back is enabled or not
+// <id> xosc1_arch_swben
+#ifndef CONF_XOSC1_SWBEN
+#define CONF_XOSC1_SWBEN 0
+#endif
+
+// <q> Clock Failure Detector
+// <i> Indicates whether Clock Failure Detector is enabled or not
+// <id> xosc1_arch_cfden
+#ifndef CONF_XOSC1_CFDEN
+#define CONF_XOSC1_CFDEN 0
+#endif
+
+// <q> Automatic Loop Control Enable
+// <i> Indicates whether Automatic Loop Control is enabled or not
+// <id> xosc1_arch_enalc
+#ifndef CONF_XOSC1_ENALC
+#define CONF_XOSC1_ENALC 0
+#endif
+
+// <q> Low Buffer Gain Enable
+// <i> Indicates whether Low Buffer Gain is enabled or not
+// <id> xosc1_arch_lowbufgain
+#ifndef CONF_XOSC1_LOWBUFGAIN
+#define CONF_XOSC1_LOWBUFGAIN 0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> xosc1_arch_ondemand
+#ifndef CONF_XOSC1_ONDEMAND
+#define CONF_XOSC1_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> xosc1_arch_runstdby
+#ifndef CONF_XOSC1_RUNSTDBY
+#define CONF_XOSC1_RUNSTDBY 0
+#endif
+
+// <q> Crystal connected to XIN/XOUT Enable
+// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// <id> xosc1_arch_xtalen
+#ifndef CONF_XOSC1_XTALEN
+#define CONF_XOSC1_XTALEN 1
+#endif
+//</h>
+//</e>
+
+#if CONF_XOSC1_FREQUENCY >= 32000000
+#define CONF_XOSC1_CFDPRESC 0x0
+#define CONF_XOSC1_IMULT 0x7
+#define CONF_XOSC1_IPTAT 0x3
+#elif CONF_XOSC1_FREQUENCY >= 24000000
+#define CONF_XOSC1_CFDPRESC 0x1
+#define CONF_XOSC1_IMULT 0x6
+#define CONF_XOSC1_IPTAT 0x3
+#elif CONF_XOSC1_FREQUENCY >= 16000000
+#define CONF_XOSC1_CFDPRESC 0x2
+#define CONF_XOSC1_IMULT 0x5
+#define CONF_XOSC1_IPTAT 0x3
+#elif CONF_XOSC1_FREQUENCY >= 8000000
+#define CONF_XOSC1_CFDPRESC 0x3
+#define CONF_XOSC1_IMULT 0x4
+#define CONF_XOSC1_IPTAT 0x3
+#endif
+
+// <e> DFLL Configuration
+// <i> Indicates whether configuration for DFLL is enabled or not
+// <id> enable_dfll
+#ifndef CONF_DFLL_CONFIG
+#define CONF_DFLL_CONFIG 1
+#endif
+
+// <y> Reference Clock Source
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+// <i> Select the clock source
+// <id> dfll_ref_clock
+#ifndef CONF_DFLL_GCLK
+#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK2_Val
+#endif
+
+// <h> Digital Frequency Locked Loop Control
+// <q> DFLL Enable
+// <i> Indicates whether DFLL is enabled or not
+// <id> dfll_arch_enable
+#ifndef CONF_DFLL_ENABLE
+#define CONF_DFLL_ENABLE 1
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> dfll_arch_ondemand
+#ifndef CONF_DFLL_ONDEMAND
+#define CONF_DFLL_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> dfll_arch_runstdby
+#ifndef CONF_DFLL_RUNSTDBY
+#define CONF_DFLL_RUNSTDBY 0
+#endif
+
+// <q> USB Clock Recovery Mode
+// <i> Indicates whether USB Clock Recovery Mode is enabled or not
+// <id> dfll_arch_usbcrm
+#ifndef CONF_DFLL_USBCRM
+#define CONF_DFLL_USBCRM 0
+#endif
+
+// <q> Wait Lock
+// <i> Indicates whether Wait Lock is enabled or not
+// <id> dfll_arch_waitlock
+#ifndef CONF_DFLL_WAITLOCK
+#define CONF_DFLL_WAITLOCK 1
+#endif
+
+// <q> Bypass Coarse Lock
+// <i> Indicates whether Bypass Coarse Lock is enabled or not
+// <id> dfll_arch_bplckc
+#ifndef CONF_DFLL_BPLCKC
+#define CONF_DFLL_BPLCKC 0
+#endif
+
+// <q> Quick Lock Disable
+// <i> Indicates whether Quick Lock Disable is enabled or not
+// <id> dfll_arch_qldis
+#ifndef CONF_DFLL_QLDIS
+#define CONF_DFLL_QLDIS 0
+#endif
+
+// <q> Chill Cycle Disable
+// <i> Indicates whether Chill Cycle Disable is enabled or not
+// <id> dfll_arch_ccdis
+#ifndef CONF_DFLL_CCDIS
+#define CONF_DFLL_CCDIS 0
+#endif
+
+// <q> Lose Lock After Wake
+// <i> Indicates whether Lose Lock After Wake is enabled or not
+// <id> dfll_arch_llaw
+#ifndef CONF_DFLL_LLAW
+#define CONF_DFLL_LLAW 0
+#endif
+
+// <q> Stable DFLL Frequency
+// <i> Indicates whether Stable DFLL Frequency is enabled or not
+// <id> dfll_arch_stable
+#ifndef CONF_DFLL_STABLE
+#define CONF_DFLL_STABLE 0
+#endif
+
+// <o> Operating Mode Selection
+// <0=>Open Loop Mode
+// <1=>Closed Loop Mode
+// <id> dfll_mode
+#ifndef CONF_DFLL_MODE
+#define CONF_DFLL_MODE 0x0
+#endif
+
+// <o> Coarse Maximum Step <0x0-0x1F>
+// <id> dfll_arch_cstep
+#ifndef CONF_DFLL_CSTEP
+#define CONF_DFLL_CSTEP 0x1
+#endif
+
+// <o> Fine Maximum Step <0x0-0xFF>
+// <id> dfll_arch_fstep
+#ifndef CONF_DFLL_FSTEP
+#define CONF_DFLL_FSTEP 0x1
+#endif
+
+// <o> DFLL Multiply Factor <0x0-0xFFFF>
+//  <id> dfll_mul
+#ifndef CONF_DFLL_MUL
+#define CONF_DFLL_MUL 0x0
+#endif
+
+// <e> DFLL Calibration Overwrite
+// <i> Indicates whether Overwrite Calibration value of DFLL
+// <id> dfll_arch_calibration
+#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
+#define CONF_DFLL_OVERWRITE_CALIBRATION 0
+#endif
+
+// <o> Coarse Value <0x0-0x3F>
+// <id> dfll_arch_coarse
+#ifndef CONF_DFLL_COARSE
+#define CONF_DFLL_COARSE (0x1f / 4)
+#endif
+
+// <o> Fine Value <0x0-0xFF>
+// <id> dfll_arch_fine
+#ifndef CONF_DFLL_FINE
+#define CONF_DFLL_FINE (0x80)
+#endif
+
+//</e>
+
+//</h>
+
+//</e>
+
+// <e> FDPLL0 Configuration
+// <i> Indicates whether configuration for FDPLL0 is enabled or not
+// <id> enable_fdpll0
+#ifndef CONF_FDPLL0_CONFIG
+#define CONF_FDPLL0_CONFIG 0
+#endif
+
+// <y> Reference Clock Source
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+// <i> Select the clock source.
+// <id> fdpll0_ref_clock
+#ifndef CONF_FDPLL0_GCLK
+#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// <h> Digital Phase Locked Loop Control
+// <q> Enable
+// <i> Indicates whether Digital Phase Locked Loop is enabled or not
+// <id> fdpll0_arch_enable
+#ifndef CONF_FDPLL0_ENABLE
+#define CONF_FDPLL0_ENABLE 0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> fdpll0_arch_ondemand
+#ifndef CONF_FDPLL0_ONDEMAND
+#define CONF_FDPLL0_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> fdpll0_arch_runstdby
+#ifndef CONF_FDPLL0_RUNSTDBY
+#define CONF_FDPLL0_RUNSTDBY 0
+#endif
+
+// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
+// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
+// <id> fdpll0_ldrfrac
+#ifndef CONF_FDPLL0_LDRFRAC
+#define CONF_FDPLL0_LDRFRAC 0xd
+#endif
+
+// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
+// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
+// <id> fdpll0_ldr
+#ifndef CONF_FDPLL0_LDR
+#define CONF_FDPLL0_LDR 0x5b7
+#endif
+
+// <o> Clock Divider <0x0-0x7FF>
+// <i> This Clock divider is only for XOSC clock input to DPLL
+// <id> fdpll0_clock_div
+#ifndef CONF_FDPLL0_DIV
+#define CONF_FDPLL0_DIV 0x0
+#endif
+
+// <q> DCO Filter Enable
+// <i> Indicates whether DCO Filter Enable is enabled or not
+// <id> fdpll0_arch_dcoen
+#ifndef CONF_FDPLL0_DCOEN
+#define CONF_FDPLL0_DCOEN 0
+#endif
+
+// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
+// <id> fdpll0_clock_dcofilter
+#ifndef CONF_FDPLL0_DCOFILTER
+#define CONF_FDPLL0_DCOFILTER 0x0
+#endif
+
+// <q> Lock Bypass
+// <i> Indicates whether Lock Bypass is enabled or not
+// <id> fdpll0_arch_lbypass
+#ifndef CONF_FDPLL0_LBYPASS
+#define CONF_FDPLL0_LBYPASS 0
+#endif
+
+// <o> Lock Time
+// <0x0=>No time-out, automatic lock
+// <0x4=>The Time-out if no lock within 800 us
+// <0x5=>The Time-out if no lock within 900 us
+// <0x6=>The Time-out if no lock within 1 ms
+// <0x7=>The Time-out if no lock within 11 ms
+// <id> fdpll0_arch_ltime
+#ifndef CONF_FDPLL0_LTIME
+#define CONF_FDPLL0_LTIME 0x0
+#endif
+
+// <o> Reference Clock Selection
+// <0x0=>GCLK clock reference
+// <0x1=>XOSC32K clock reference
+// <0x2=>XOSC0 clock reference
+// <0x3=>XOSC1 clock reference
+// <id> fdpll0_arch_refclk
+#ifndef CONF_FDPLL0_REFCLK
+#define CONF_FDPLL0_REFCLK 0x1
+#endif
+
+// <q> Wake Up Fast
+// <i> Indicates whether Wake Up Fast is enabled or not
+// <id> fdpll0_arch_wuf
+#ifndef CONF_FDPLL0_WUF
+#define CONF_FDPLL0_WUF 0
+#endif
+
+// <o> Proportional Integral Filter Selection <0x0-0xF>
+// <id> fdpll0_arch_filter
+#ifndef CONF_FDPLL0_FILTER
+#define CONF_FDPLL0_FILTER 0x0
+#endif
+
+//</h>
+//</e>
+// <e> FDPLL1 Configuration
+// <i> Indicates whether configuration for FDPLL1 is enabled or not
+// <id> enable_fdpll1
+#ifndef CONF_FDPLL1_CONFIG
+#define CONF_FDPLL1_CONFIG 1
+#endif
+
+// <y> Reference Clock Source
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+// <i> Select the clock source.
+// <id> fdpll1_ref_clock
+#ifndef CONF_FDPLL1_GCLK
+#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+// <h> Digital Phase Locked Loop Control
+// <q> Enable
+// <i> Indicates whether Digital Phase Locked Loop is enabled or not
+// <id> fdpll1_arch_enable
+#ifndef CONF_FDPLL1_ENABLE
+#define CONF_FDPLL1_ENABLE 1
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> fdpll1_arch_ondemand
+#ifndef CONF_FDPLL1_ONDEMAND
+#define CONF_FDPLL1_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> fdpll1_arch_runstdby
+#ifndef CONF_FDPLL1_RUNSTDBY
+#define CONF_FDPLL1_RUNSTDBY 0
+#endif
+
+// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
+// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
+// <id> fdpll1_ldrfrac
+#ifndef CONF_FDPLL1_LDRFRAC
+#define CONF_FDPLL1_LDRFRAC 0x0
+#endif
+
+// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
+// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
+// <id> fdpll1_ldr
+#ifndef CONF_FDPLL1_LDR
+#define CONF_FDPLL1_LDR 0x31
+#endif
+
+// <o> Clock Divider <0x0-0x7FF>
+// <i> This Clock divider is only for XOSC clock input to DPLL
+// <id> fdpll1_clock_div
+#ifndef CONF_FDPLL1_DIV
+#define CONF_FDPLL1_DIV 0x0
+#endif
+
+// <q> DCO Filter Enable
+// <i> Indicates whether DCO Filter Enable is enabled or not
+// <id> fdpll1_arch_dcoen
+#ifndef CONF_FDPLL1_DCOEN
+#define CONF_FDPLL1_DCOEN 0
+#endif
+
+// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
+// <id> fdpll1_clock_dcofilter
+#ifndef CONF_FDPLL1_DCOFILTER
+#define CONF_FDPLL1_DCOFILTER 0x0
+#endif
+
+// <q> Lock Bypass
+// <i> Indicates whether Lock Bypass is enabled or not
+// <id> fdpll1_arch_lbypass
+#ifndef CONF_FDPLL1_LBYPASS
+#define CONF_FDPLL1_LBYPASS 0
+#endif
+
+// <o> Lock Time
+// <0x0=>No time-out, automatic lock
+// <0x4=>The Time-out if no lock within 800 us
+// <0x5=>The Time-out if no lock within 900 us
+// <0x6=>The Time-out if no lock within 1 ms
+// <0x7=>The Time-out if no lock within 11 ms
+// <id> fdpll1_arch_ltime
+#ifndef CONF_FDPLL1_LTIME
+#define CONF_FDPLL1_LTIME 0x0
+#endif
+
+// <o> Reference Clock Selection
+// <0x0=>GCLK clock reference
+// <0x1=>XOSC32K clock reference
+// <0x2=>XOSC0 clock reference
+// <0x3=>XOSC1 clock reference
+// <id> fdpll1_arch_refclk
+#ifndef CONF_FDPLL1_REFCLK
+#define CONF_FDPLL1_REFCLK 0x0
+#endif
+
+// <q> Wake Up Fast
+// <i> Indicates whether Wake Up Fast is enabled or not
+// <id> fdpll1_arch_wuf
+#ifndef CONF_FDPLL1_WUF
+#define CONF_FDPLL1_WUF 0
+#endif
+
+// <o> Proportional Integral Filter Selection <0x0-0xF>
+// <id> fdpll1_arch_filter
+#ifndef CONF_FDPLL1_FILTER
+#define CONF_FDPLL1_FILTER 0x0
+#endif
+
+//</h>
+//</e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_OSCCTRL_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_port_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_port_config.h
new file mode 100644
index 0000000..7e6e94f
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_port_config.h
@@ -0,0 +1,284 @@
+/* Auto-generated config file hpl_port_config.h */
+#ifndef HPL_PORT_CONFIG_H
+#define HPL_PORT_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> PORT Input Event 0 configuration
+// <id> enable_port_input_event_0
+#ifndef CONF_PORT_EVCTRL_PORT_0
+#define CONF_PORT_EVCTRL_PORT_0 1
+#endif
+
+// <h> PORT Input Event 0 configuration on PORT A
+
+// <q> PORTA Input Event 0 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
+// <id> porta_input_event_enable_0
+#ifndef CONF_PORTA_EVCTRL_PORTEI_0
+#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
+#endif
+
+// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_0
+#ifndef CONF_PORTA_EVCTRL_PID_0
+#define CONF_PORTA_EVCTRL_PID_0 0x0
+#endif
+
+// <o> PORTA Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 0
+// <id> porta_event_action_0
+#ifndef CONF_PORTA_EVCTRL_EVACT_0
+#define CONF_PORTA_EVCTRL_EVACT_0 0
+#endif
+
+// </h>
+// <h> PORT Input Event 0 configuration on PORT B
+
+// <q> PORTB Input Event 0 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
+// <id> portb_input_event_enable_0
+#ifndef CONF_PORTB_EVCTRL_PORTEI_0
+#define CONF_PORTB_EVCTRL_PORTEI_0 0x1
+#endif
+
+// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_0
+#ifndef CONF_PORTB_EVCTRL_PID_0
+#define CONF_PORTB_EVCTRL_PID_0 0x16
+#endif
+
+// <o> PORTB Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 0
+// <id> portb_event_action_0
+#ifndef CONF_PORTB_EVCTRL_EVACT_0
+#define CONF_PORTB_EVCTRL_EVACT_0 2
+#endif
+
+// </h>
+
+// </e>
+
+// <e> PORT Input Event 1 configuration
+// <id> enable_port_input_event_1
+#ifndef CONF_PORT_EVCTRL_PORT_1
+#define CONF_PORT_EVCTRL_PORT_1 1
+#endif
+
+// <h> PORT Input Event 1 configuration on PORT A
+
+// <q> PORTA Input Event 1 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
+// <id> porta_input_event_enable_1
+#ifndef CONF_PORTA_EVCTRL_PORTEI_1
+#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
+#endif
+
+// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_1
+#ifndef CONF_PORTA_EVCTRL_PID_1
+#define CONF_PORTA_EVCTRL_PID_1 0x0
+#endif
+
+// <o> PORTA Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 1
+// <id> porta_event_action_1
+#ifndef CONF_PORTA_EVCTRL_EVACT_1
+#define CONF_PORTA_EVCTRL_EVACT_1 0
+#endif
+
+// </h>
+// <h> PORT Input Event 1 configuration on PORT B
+
+// <q> PORTB Input Event 1 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
+// <id> portb_input_event_enable_1
+#ifndef CONF_PORTB_EVCTRL_PORTEI_1
+#define CONF_PORTB_EVCTRL_PORTEI_1 0x1
+#endif
+
+// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_1
+#ifndef CONF_PORTB_EVCTRL_PID_1
+#define CONF_PORTB_EVCTRL_PID_1 0x16
+#endif
+
+// <o> PORTB Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 1
+// <id> portb_event_action_1
+#ifndef CONF_PORTB_EVCTRL_EVACT_1
+#define CONF_PORTB_EVCTRL_EVACT_1 1
+#endif
+
+// </h>
+
+// </e>
+
+// <e> PORT Input Event 2 configuration
+// <id> enable_port_input_event_2
+#ifndef CONF_PORT_EVCTRL_PORT_2
+#define CONF_PORT_EVCTRL_PORT_2 1
+#endif
+
+// <h> PORT Input Event 2 configuration on PORT A
+
+// <q> PORTA Input Event 2 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
+// <id> porta_input_event_enable_2
+#ifndef CONF_PORTA_EVCTRL_PORTEI_2
+#define CONF_PORTA_EVCTRL_PORTEI_2 0x1
+#endif
+
+// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_2
+#ifndef CONF_PORTA_EVCTRL_PID_2
+#define CONF_PORTA_EVCTRL_PID_2 0xe
+#endif
+
+// <o> PORTA Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 2
+// <id> porta_event_action_2
+#ifndef CONF_PORTA_EVCTRL_EVACT_2
+#define CONF_PORTA_EVCTRL_EVACT_2 2
+#endif
+
+// </h>
+// <h> PORT Input Event 2 configuration on PORT B
+
+// <q> PORTB Input Event 2 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
+// <id> portb_input_event_enable_2
+#ifndef CONF_PORTB_EVCTRL_PORTEI_2
+#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
+#endif
+
+// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_2
+#ifndef CONF_PORTB_EVCTRL_PID_2
+#define CONF_PORTB_EVCTRL_PID_2 0x0
+#endif
+
+// <o> PORTB Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 2
+// <id> portb_event_action_2
+#ifndef CONF_PORTB_EVCTRL_EVACT_2
+#define CONF_PORTB_EVCTRL_EVACT_2 0
+#endif
+
+// </h>
+
+// </e>
+
+// <e> PORT Input Event 3 configuration
+// <id> enable_port_input_event_3
+#ifndef CONF_PORT_EVCTRL_PORT_3
+#define CONF_PORT_EVCTRL_PORT_3 1
+#endif
+
+// <h> PORT Input Event 3 configuration on PORT A
+
+// <q> PORTA Input Event 3 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
+// <id> porta_input_event_enable_3
+#ifndef CONF_PORTA_EVCTRL_PORTEI_3
+#define CONF_PORTA_EVCTRL_PORTEI_3 0x1
+#endif
+
+// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_3
+#ifndef CONF_PORTA_EVCTRL_PID_3
+#define CONF_PORTA_EVCTRL_PID_3 0xe
+#endif
+
+// <o> PORTA Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 3
+// <id> porta_event_action_3
+#ifndef CONF_PORTA_EVCTRL_EVACT_3
+#define CONF_PORTA_EVCTRL_EVACT_3 1
+#endif
+
+// </h>
+// <h> PORT Input Event 3 configuration on PORT B
+
+// <q> PORTB Input Event 3 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
+// <id> portb_input_event_enable_3
+#ifndef CONF_PORTB_EVCTRL_PORTEI_3
+#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
+#endif
+
+// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_3
+#ifndef CONF_PORTB_EVCTRL_PID_3
+#define CONF_PORTB_EVCTRL_PID_3 0x0
+#endif
+
+// <o> PORTB Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 3
+// <id> portb_event_action_3
+#ifndef CONF_PORTB_EVCTRL_EVACT_3
+#define CONF_PORTB_EVCTRL_EVACT_3 0
+#endif
+
+// </h>
+
+// </e>
+
+#define CONF_PORTA_EVCTRL                                                                                              \
+	(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos         \
+	 | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1)                       \
+	 | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1)               \
+	 | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos           \
+	 | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3)                       \
+	 | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
+#define CONF_PORTB_EVCTRL                                                                                              \
+	(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos         \
+	 | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1)                       \
+	 | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1)               \
+	 | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos           \
+	 | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3)                       \
+	 | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
+
+// <<< end of configuration section >>>
+
+#endif // HPL_PORT_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_qspi_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_qspi_config.h
new file mode 100644
index 0000000..1dbf955
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_qspi_config.h
@@ -0,0 +1,98 @@
+/* Auto-generated config file hpl_qspi_config.h */
+#ifndef HPL_QSPI_CONFIG_H
+#define HPL_QSPI_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+// <h> Basic settings
+
+#ifndef CONF_CONF_QSPI_ENABLE
+#define CONF_CONF_QSPI_ENABLE 1
+#endif
+
+// <o> Baud rate <1-150000000>
+// <i> The SPI data transfer rate. Note: (fqspi_clock / baudrate) < 255
+// <id> qspi_baud_rate
+#ifndef CONF_QSPI_BAUD
+#define CONF_QSPI_BAUD 6000000
+#endif
+
+// <o> Clock Polarity
+// <0x0=>The inactive state value of SPCK is logic level zero.
+// <0x1=>The inactive state value of SPCK is logic level one.
+// <i> Determines the inactive state value of the serial clock (SPCK).
+// <id> qspi_cpol
+#ifndef CONF_QSPI_CPOL
+#define CONF_QSPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
+// <0x1=>Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
+// <i> Determines which edge of SPCK causes data to change and which edge causes data to be captured.
+// <id> qspi_cpha
+#ifndef CONF_QSPI_CPHA
+#define CONF_QSPI_CPHA 0x0
+#endif
+
+//<o> QSPI DMA TX Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> qspi_dma_tx_channel
+#ifndef CONF_QSPI_DMA_TX_CHANNEL
+#define CONF_QSPI_DMA_TX_CHANNEL 1
+#endif
+
+//<o> QSPI DMA RX  Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> qspi_dma_rx_channel
+#ifndef CONF_QSPI_DMA_RX_CHANNEL
+#define CONF_QSPI_DMA_RX_CHANNEL 0
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> qspi_advanced
+#ifndef CONF_QSPI_ADVANCED
+#define CONF_QSPI_ADVANCED 0
+#endif
+
+// <o> Delay Before QSCK (ns) <0-255000>
+// <i> This field defines the delay from QCS falling edge (activation) to the first valid QSCK transition (in ns).
+// <id> qspi_dlybs
+#ifndef CONF_QSPI_DLY_BS
+#define CONF_QSPI_DLY_BS 0
+#endif
+
+// <o> Minimum Inactive QCS Delay (ns) <0-8160000>
+// <i> This field defines the minimum delay between the deactivation and the activation of QCS (in ns).
+// <id> qspi_dlycs
+#ifndef CONF_QSPI_DLY_CS
+#define CONF_QSPI_DLY_CS 0
+#endif
+
+// </e>
+
+/* Calculate baud register value from requested baudrate value */
+#ifndef CONF_QSPI_BAUD_RATE
+#define CONF_QSPI_BAUD_RATE ((CONF_CPU_FREQUENCY / CONF_QSPI_BAUD) - 1)
+#if CONF_QSPI_BAUD > CONF_CPU_FREQUENCY || CONF_QSPI_BAUD_RATE > 255
+#warning Invalid baudrate, please check.
+#endif
+#endif
+
+/* Calculates the value of the CSR DLYCS field given the desired delay (in ns) */
+#ifndef CONF_QSPI_DLYCS
+#define CONF_QSPI_DLYCS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_CS) / 1000)
+#endif
+
+/* Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
+#ifndef CONF_QSPI_DLYBS
+#define CONF_QSPI_DLYBS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_BS) / 1000)
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_QSPI_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_sercom_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_sercom_config.h
new file mode 100644
index 0000000..1d01fe3
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_sercom_config.h
@@ -0,0 +1,643 @@
+/* Auto-generated config file hpl_sercom_config.h */
+#ifndef HPL_SERCOM_CONFIG_H
+#define HPL_SERCOM_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+#endif
+
+#ifndef CONF_SERCOM_0_I2CM_ENABLE
+#define CONF_SERCOM_0_I2CM_ENABLE 1
+#endif
+
+// <h> Basic
+
+// <o> I2C Bus clock speed (Hz) <1-400000>
+// <i> I2C Bus clock (SCL) speed measured in Hz
+// <id> i2c_master_baud_rate
+#ifndef CONF_SERCOM_0_I2CM_BAUD
+#define CONF_SERCOM_0_I2CM_BAUD 100000
+#endif
+
+// </h>
+
+// <e> Advanced
+// <id> i2c_master_advanced
+#ifndef CONF_SERCOM_0_I2CM_ADVANCED_CONFIG
+#define CONF_SERCOM_0_I2CM_ADVANCED_CONFIG 0
+#endif
+
+// <o> TRise (ns) <0-300>
+// <i> Determined by the bus impedance, check electric characteristics in the datasheet
+// <i> Standard Fast Mode: typical 215ns, max 300ns
+// <i> Fast Mode +: typical 60ns, max 100ns
+// <i> High Speed Mode: typical 20ns, max 40ns
+// <id> i2c_master_arch_trise
+
+#ifndef CONF_SERCOM_0_I2CM_TRISE
+#define CONF_SERCOM_0_I2CM_TRISE 215
+#endif
+
+// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
+// <i> This enables the master SCL low extend time-out
+// <id> i2c_master_arch_mexttoen
+#ifndef CONF_SERCOM_0_I2CM_MEXTTOEN
+#define CONF_SERCOM_0_I2CM_MEXTTOEN 0
+#endif
+
+// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
+// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
+// <id> i2c_master_arch_sexttoen
+#ifndef CONF_SERCOM_0_I2CM_SEXTTOEN
+#define CONF_SERCOM_0_I2CM_SEXTTOEN 0
+#endif
+
+// <q> SCL Low Time-Out (LOWTOUT)
+// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
+// <id> i2c_master_arch_lowtout
+#ifndef CONF_SERCOM_0_I2CM_LOWTOUT
+#define CONF_SERCOM_0_I2CM_LOWTOUT 0
+#endif
+
+// <o> Inactive Time-Out (INACTOUT)
+// <0x0=>Disabled
+// <0x1=>5-6 SCL cycle time-out(50-60us)
+// <0x2=>10-11 SCL cycle time-out(100-110us)
+// <0x3=>20-21 SCL cycle time-out(200-210us)
+// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
+// <id> i2c_master_arch_inactout
+#ifndef CONF_SERCOM_0_I2CM_INACTOUT
+#define CONF_SERCOM_0_I2CM_INACTOUT 0x0
+#endif
+
+// <o> SDA Hold Time (SDAHOLD)
+// <0=>Disabled
+// <1=>50-100ns hold time
+// <2=>300-600ns hold time
+// <3=>400-800ns hold time
+// <i> Defines the SDA hold time with respect to the negative edge of SCL
+// <id> i2c_master_arch_sdahold
+#ifndef CONF_SERCOM_0_I2CM_SDAHOLD
+#define CONF_SERCOM_0_I2CM_SDAHOLD 0x2
+#endif
+
+// <q> Run in stand-by
+// <i> Determine if the module shall run in standby sleep mode
+// <id> i2c_master_arch_runstdby
+#ifndef CONF_SERCOM_0_I2CM_RUNSTDBY
+#define CONF_SERCOM_0_I2CM_RUNSTDBY 0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> i2c_master_arch_dbgstop
+#ifndef CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE
+#define CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE 0
+#endif
+
+// </e>
+
+#ifndef CONF_SERCOM_0_I2CM_SPEED
+#define CONF_SERCOM_0_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
+#endif
+#if CONF_SERCOM_0_I2CM_TRISE < 215 || CONF_SERCOM_0_I2CM_TRISE > 300
+#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
+#undef CONF_SERCOM_0_I2CM_TRISE
+#define CONF_SERCOM_0_I2CM_TRISE 215U
+#endif
+
+//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
+// BAUD + BAUDLOW = --------------------------------------------------------------------
+//                  i2c_scl_freq
+// BAUD:    register value low  [7:0]
+// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
+#define CONF_SERCOM_0_I2CM_BAUD_BAUDLOW                                                                                \
+	(((CONF_GCLK_SERCOM0_CORE_FREQUENCY - (CONF_SERCOM_0_I2CM_BAUD * 10U)                                              \
+	   - (CONF_SERCOM_0_I2CM_TRISE * (CONF_SERCOM_0_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM0_CORE_FREQUENCY / 10000U)    \
+	      / 1000U))                                                                                                    \
+	      * 10U                                                                                                        \
+	  + 5U)                                                                                                            \
+	 / (CONF_SERCOM_0_I2CM_BAUD * 10U))
+#ifndef CONF_SERCOM_0_I2CM_BAUD_RATE
+#if CONF_SERCOM_0_I2CM_BAUD_BAUDLOW > (0xFF * 2)
+#warning Requested I2C baudrate too low, please check
+#define CONF_SERCOM_0_I2CM_BAUD_RATE 0xFF
+#elif CONF_SERCOM_0_I2CM_BAUD_BAUDLOW <= 1
+#warning Requested I2C baudrate too high, please check
+#define CONF_SERCOM_0_I2CM_BAUD_RATE 1
+#else
+#define CONF_SERCOM_0_I2CM_BAUD_RATE                                                                                   \
+	((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
+	     ? (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
+	     : (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2))
+#endif
+#endif
+
+#include <peripheral_clk_config.h>
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_1_SPI_ENABLE
+#define CONF_SERCOM_1_SPI_ENABLE 1
+#endif
+
+//<o> SPI DMA TX Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> spi_master_dma_tx_channel
+#ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 7
+#endif
+
+// <e> SPI RX Channel Enable
+// <id> spi_master_rx_channel
+#ifndef CONF_SERCOM_1_SPI_RX_CHANNEL
+#define CONF_SERCOM_1_SPI_RX_CHANNEL 1
+#endif
+
+//<o> DMA Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> spi_master_dma_rx_channel
+#ifndef CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 0
+#endif
+
+// </e>
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_1_SPI_MODE
+#define CONF_SERCOM_1_SPI_MODE 0x03
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave (RXEN)
+// <id> spi_master_rx_enable
+#ifndef CONF_SERCOM_1_SPI_RXEN
+#define CONF_SERCOM_1_SPI_RXEN 0x1
+#endif
+
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_master_character_size
+#ifndef CONF_SERCOM_1_SPI_CHSIZE
+#define CONF_SERCOM_1_SPI_CHSIZE 0x0
+#endif
+// <o> Baud rate <1-18000000>
+// <i> The SPI data transfer rate
+// <id> spi_master_baud_rate
+#ifndef CONF_SERCOM_1_SPI_BAUD
+#define CONF_SERCOM_1_SPI_BAUD 1000000
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> spi_master_advanced
+#ifndef CONF_SERCOM_1_SPI_ADVANCED
+#define CONF_SERCOM_1_SPI_ADVANCED 1
+#endif
+
+// <o> Dummy byte <0x00-0x1ff>
+// <id> spi_master_dummybyte
+// <i> Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_1_SPI_DUMMYBYTE
+#define CONF_SERCOM_1_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first (DORD)
+// <id> spi_master_arch_dord
+#ifndef CONF_SERCOM_1_SPI_DORD
+#define CONF_SERCOM_1_SPI_DORD 0x0
+#endif
+
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_master_arch_cpol
+#ifndef CONF_SERCOM_1_SPI_CPOL
+#define CONF_SERCOM_1_SPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_master_arch_cpha
+#ifndef CONF_SERCOM_1_SPI_CPHA
+#define CONF_SERCOM_1_SPI_CPHA 0x0
+#endif
+
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_master_arch_ibon
+#ifndef CONF_SERCOM_1_SPI_IBON
+#define CONF_SERCOM_1_SPI_IBON 0x0
+#endif
+
+// <q> Run in stand-by
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_master_arch_runstdby
+#ifndef CONF_SERCOM_1_SPI_RUNSTDBY
+#define CONF_SERCOM_1_SPI_RUNSTDBY 0x0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// <id> spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_1_SPI_DBGSTOP
+#define CONF_SERCOM_1_SPI_DBGSTOP 0
+#endif
+
+// </e>
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_1_SPI_AMODE_EN
+#define CONF_SERCOM_1_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_AMODE
+#define CONF_SERCOM_1_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_ADDR
+#define CONF_SERCOM_1_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_ADDRMASK
+#define CONF_SERCOM_1_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_SSDE
+#define CONF_SERCOM_1_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_MSSEN
+#define CONF_SERCOM_1_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_PLOADEN
+#define CONF_SERCOM_1_SPI_PLOADEN 0
+#endif
+
+// <o> Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// <id> spi_master_rxpo
+#ifndef CONF_SERCOM_1_SPI_RXPO
+#define CONF_SERCOM_1_SPI_RXPO 3
+#endif
+
+// <o> Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// <id> spi_master_txpo
+#ifndef CONF_SERCOM_1_SPI_TXPO
+#define CONF_SERCOM_1_SPI_TXPO 0
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_1_SPI_BAUD_RATE
+#define CONF_SERCOM_1_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM1_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_1_SPI_BAUD)) - 1
+#endif
+
+#include <peripheral_clk_config.h>
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_2_SPI_ENABLE
+#define CONF_SERCOM_2_SPI_ENABLE 1
+#endif
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_2_SPI_MODE
+#define CONF_SERCOM_2_SPI_MODE 0x03
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave (RXEN)
+// <id> spi_master_rx_enable
+#ifndef CONF_SERCOM_2_SPI_RXEN
+#define CONF_SERCOM_2_SPI_RXEN 0x1
+#endif
+
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_master_character_size
+#ifndef CONF_SERCOM_2_SPI_CHSIZE
+#define CONF_SERCOM_2_SPI_CHSIZE 0x0
+#endif
+// <o> Baud rate <1-18000000>
+// <i> The SPI data transfer rate
+// <id> spi_master_baud_rate
+#ifndef CONF_SERCOM_2_SPI_BAUD
+#define CONF_SERCOM_2_SPI_BAUD 1000000
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> spi_master_advanced
+#ifndef CONF_SERCOM_2_SPI_ADVANCED
+#define CONF_SERCOM_2_SPI_ADVANCED 1
+#endif
+
+// <o> Dummy byte <0x00-0x1ff>
+// <id> spi_master_dummybyte
+// <i> Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_2_SPI_DUMMYBYTE
+#define CONF_SERCOM_2_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first (DORD)
+// <id> spi_master_arch_dord
+#ifndef CONF_SERCOM_2_SPI_DORD
+#define CONF_SERCOM_2_SPI_DORD 0x0
+#endif
+
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_master_arch_cpol
+#ifndef CONF_SERCOM_2_SPI_CPOL
+#define CONF_SERCOM_2_SPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_master_arch_cpha
+#ifndef CONF_SERCOM_2_SPI_CPHA
+#define CONF_SERCOM_2_SPI_CPHA 0x1
+#endif
+
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_master_arch_ibon
+#ifndef CONF_SERCOM_2_SPI_IBON
+#define CONF_SERCOM_2_SPI_IBON 0x1
+#endif
+
+// <q> Run in stand-by
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_master_arch_runstdby
+#ifndef CONF_SERCOM_2_SPI_RUNSTDBY
+#define CONF_SERCOM_2_SPI_RUNSTDBY 0x0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// <id> spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_2_SPI_DBGSTOP
+#define CONF_SERCOM_2_SPI_DBGSTOP 0
+#endif
+
+// </e>
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_2_SPI_AMODE_EN
+#define CONF_SERCOM_2_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_AMODE
+#define CONF_SERCOM_2_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_ADDR
+#define CONF_SERCOM_2_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_ADDRMASK
+#define CONF_SERCOM_2_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_SSDE
+#define CONF_SERCOM_2_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_MSSEN
+#define CONF_SERCOM_2_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_PLOADEN
+#define CONF_SERCOM_2_SPI_PLOADEN 0
+#endif
+
+// <o> Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// <id> spi_master_rxpo
+#ifndef CONF_SERCOM_2_SPI_RXPO
+#define CONF_SERCOM_2_SPI_RXPO 3
+#endif
+
+// <o> Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// <id> spi_master_txpo
+#ifndef CONF_SERCOM_2_SPI_TXPO
+#define CONF_SERCOM_2_SPI_TXPO 0
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_2_SPI_BAUD_RATE
+#define CONF_SERCOM_2_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM2_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_2_SPI_BAUD)) - 1
+#endif
+
+#include <peripheral_clk_config.h>
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_5_SPI_ENABLE
+#define CONF_SERCOM_5_SPI_ENABLE 1
+#endif
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_5_SPI_MODE
+#define CONF_SERCOM_5_SPI_MODE 0x03
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave (RXEN)
+// <id> spi_master_rx_enable
+#ifndef CONF_SERCOM_5_SPI_RXEN
+#define CONF_SERCOM_5_SPI_RXEN 0x1
+#endif
+
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_master_character_size
+#ifndef CONF_SERCOM_5_SPI_CHSIZE
+#define CONF_SERCOM_5_SPI_CHSIZE 0x0
+#endif
+// <o> Baud rate <1-18000000>
+// <i> The SPI data transfer rate
+// <id> spi_master_baud_rate
+#ifndef CONF_SERCOM_5_SPI_BAUD
+#define CONF_SERCOM_5_SPI_BAUD 1000000
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> spi_master_advanced
+#ifndef CONF_SERCOM_5_SPI_ADVANCED
+#define CONF_SERCOM_5_SPI_ADVANCED 0
+#endif
+
+// <o> Dummy byte <0x00-0x1ff>
+// <id> spi_master_dummybyte
+// <i> Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_5_SPI_DUMMYBYTE
+#define CONF_SERCOM_5_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first (DORD)
+// <id> spi_master_arch_dord
+#ifndef CONF_SERCOM_5_SPI_DORD
+#define CONF_SERCOM_5_SPI_DORD 0x0
+#endif
+
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_master_arch_cpol
+#ifndef CONF_SERCOM_5_SPI_CPOL
+#define CONF_SERCOM_5_SPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_master_arch_cpha
+#ifndef CONF_SERCOM_5_SPI_CPHA
+#define CONF_SERCOM_5_SPI_CPHA 0x0
+#endif
+
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_master_arch_ibon
+#ifndef CONF_SERCOM_5_SPI_IBON
+#define CONF_SERCOM_5_SPI_IBON 0x0
+#endif
+
+// <q> Run in stand-by
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_master_arch_runstdby
+#ifndef CONF_SERCOM_5_SPI_RUNSTDBY
+#define CONF_SERCOM_5_SPI_RUNSTDBY 0x0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// <id> spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_5_SPI_DBGSTOP
+#define CONF_SERCOM_5_SPI_DBGSTOP 0
+#endif
+
+// </e>
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_5_SPI_AMODE_EN
+#define CONF_SERCOM_5_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_AMODE
+#define CONF_SERCOM_5_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_ADDR
+#define CONF_SERCOM_5_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_ADDRMASK
+#define CONF_SERCOM_5_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_SSDE
+#define CONF_SERCOM_5_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_MSSEN
+#define CONF_SERCOM_5_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_PLOADEN
+#define CONF_SERCOM_5_SPI_PLOADEN 0
+#endif
+
+// <o> Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// <id> spi_master_rxpo
+#ifndef CONF_SERCOM_5_SPI_RXPO
+#define CONF_SERCOM_5_SPI_RXPO 3
+#endif
+
+// <o> Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// <id> spi_master_txpo
+#ifndef CONF_SERCOM_5_SPI_TXPO
+#define CONF_SERCOM_5_SPI_TXPO 0
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_5_SPI_BAUD_RATE
+#define CONF_SERCOM_5_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM5_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_5_SPI_BAUD)) - 1
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SERCOM_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_tcc_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_tcc_config.h
new file mode 100644
index 0000000..ccac794
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_tcc_config.h
@@ -0,0 +1,1124 @@
+/* Auto-generated config file hpl_tcc_config.h */
+#ifndef HPL_TCC_CONFIG_H
+#define HPL_TCC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+#ifndef CONF_TCC0_ENABLE
+#define CONF_TCC0_ENABLE 1
+#endif
+
+#ifndef CONF_TCC0_PWM_ENABLE
+#define CONF_TCC0_PWM_ENABLE 1
+#endif
+
+// <h> Basic settings
+// <y> TCC0 Prescaler
+// <TCC_CTRLA_PRESCALER_DIV1_Val"> No division
+// <TCC_CTRLA_PRESCALER_DIV2_Val"> Divide by 2
+// <TCC_CTRLA_PRESCALER_DIV4_Val"> Divide by 4
+// <TCC_CTRLA_PRESCALER_DIV8_Val"> Divide by 8
+// <TCC_CTRLA_PRESCALER_DIV16_Val"> Divide by 16
+// <TCC_CTRLA_PRESCALER_DIV64_Val"> Divide by 64
+// <TCC_CTRLA_PRESCALER_DIV256_Val"> Divide by 256
+// <TCC_CTRLA_PRESCALER_DIV1024_Val"> Divide by 1024
+// <i> This defines the TCC0 prescaler value
+// <id> tcc_prescaler
+#ifndef CONF_TCC0_PRESCALER
+#define CONF_TCC0_PRESCALER TCC_CTRLA_PRESCALER_DIV2_Val
+#endif
+
+// <hidden>
+//<o> TCC0 Period Value <0x000000-0xFFFFFF>
+// <id> tcc_per
+#ifndef CONF_TCC0_PER
+#define CONF_TCC0_PER 0x2710
+#endif
+// </hidden>
+
+// </h>
+
+// <h> PWM Waveform Output settings
+// <o> TCC0 Waveform Period Value (uS) <0x00-0xFFFFFFFF>
+// <i> The unit of this value is us.
+// <id> tcc_arch_wave_per_val
+#ifndef CONF_TCC0_WAVE_PER_VAL
+#define CONF_TCC0_WAVE_PER_VAL 0x30
+#endif
+
+// <o> TCC0 Waveform Duty Value (0.1%) <0x00-0x03E8>
+// <i> The unit of this value is 1/1000.
+// <id> tcc_arch_wave_duty_val
+#ifndef CONF_TCC0_WAVE_DUTY_VAL
+#define CONF_TCC0_WAVE_DUTY_VAL 0x1f4
+#endif
+
+// <o> TCC0 Waveform Channel Select <0x00-0x05>
+// <i> Index of the Compare Channel register, into which the Waveform Duty Value is written.
+// <i> Give index of the Compare Channel register here in 0x00-0x05 range.
+// <id> tcc_arch_sel_ch
+#ifndef CONF_TCC0_SEL_CH
+#define CONF_TCC0_SEL_CH 0x2
+#endif
+
+/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
+#if CONF_TCC0_PRESCALER < TCC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TCC0_PER_REG                                                                                              \
+	((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1000000 / (1 << CONF_TCC0_PRESCALER) - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)(double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 64000000 - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV256_Val
+#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 256000000 - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV1024_Val
+#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1024000000 - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+#endif
+// </h>
+
+// <h> Advanced settings
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL A register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC0_RESOLUTION TCC_CTRLA_RESOLUTION_NONE_Val
+// <q> Run in standby
+// <i> Indicates whether the TCC0 will continue running in standby sleep mode or not
+// <id> tcc_arch_runstdby
+#ifndef CONF_TCC0_RUNSTDBY
+#define CONF_TCC0_RUNSTDBY 0
+#endif
+
+// <y> TCC0 Prescaler and Counter Synchronization Selection
+// <TCC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
+// <TCC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
+// <TCC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
+// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock.
+// <id> tcc_arch_prescsync
+#ifndef CONF_TCC0_PRESCSYNC
+#define CONF_TCC0_PRESCSYNC TCC_CTRLA_PRESCSYNC_GCLK_Val
+#endif
+
+// <y> TCC0 Waveform Generation Selection
+// <TCC_WAVE_WAVEGEN_NPWM_Val"> Single-slope PWM
+// <TCC_WAVE_WAVEGEN_DSCRITICAL_Val"> Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
+// <TCC_WAVE_WAVEGEN_DSBOTTOM_Val"> Dual-slope, interrupt/event at ZERO (DSBOTTOM)
+// <TCC_WAVE_WAVEGEN_DSBOTH_Val"> Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
+// <TCC_WAVE_WAVEGEN_DSTOP_Val"> Dual-slope, interrupt/event at Top (DSTOP)
+// <id> tcc_arch_wavegen
+#ifndef CONF_TCC0_WAVEGEN
+#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_DSBOTTOM_Val
+#endif
+// <q> TCC0 Auto Lock
+// <i> Indicates whether the TCC0 Auto Lock is enabled or not
+// <id> tcc_arch_alock
+#ifndef CONF_TCC0_ALOCK
+#define CONF_TCC0_ALOCK 0
+#endif
+
+// <q> TCC0 Capture Channel 0 Enable
+// <i> Indicates whether the TCC0 Capture Channel 0 is enabled or not
+// <id> tcc_arch_cpten0
+#ifndef CONF_TCC0_CPTEN0
+#define CONF_TCC0_CPTEN0 0
+#endif
+
+// <q> TCC0 Capture Channel 1 Enable
+// <i> Indicates whether the TCC0 Capture Channel 1 is enabled or not
+// <id> tcc_arch_cpten1
+#ifndef CONF_TCC0_CPTEN1
+#define CONF_TCC0_CPTEN1 0
+#endif
+
+// <q> TCC0 Capture Channel 2 Enable
+// <i> Indicates whether the TCC0 Capture Channel 2 is enabled or not
+// <id> tcc_arch_cpten2
+#ifndef CONF_TCC0_CPTEN2
+#define CONF_TCC0_CPTEN2 0
+#endif
+
+// <q> TCC0 Capture Channel 3 Enable
+// <i> Indicates whether the TCC0 Capture Channel 3 is enabled or not
+// <id> tcc_arch_cpten3
+#ifndef CONF_TCC0_CPTEN3
+#define CONF_TCC0_CPTEN3 0
+#endif
+
+// <q> TCC0 Capture Channel 4 Enable
+// <i> Indicates whether the TCC0 Capture Channel 4 is enabled or not
+// <id> tcc_arch_cpten4
+#ifndef CONF_TCC0_CPTEN4
+#define CONF_TCC0_CPTEN4 0
+#endif
+
+// <q> TCC0 Capture Channel 5 Enable
+// <i> Indicates whether the TCC0 Capture Channel 5 is enabled or not
+// <id> tcc_arch_cpten5
+#ifndef CONF_TCC0_CPTEN5
+#define CONF_TCC0_CPTEN5 0
+#endif
+
+// <hidden>
+// <q> TCC0 Capture Channel 6 Enable
+// <i> Indicates whether the TCC0 Capture Channel 6 is enabled or not
+// <id> tcc_arch_cpten6
+#ifndef CONF_TCC0_CPTEN6
+#define CONF_TCC0_CPTEN6 0
+#endif
+// </hidden>
+// <hidden>
+// <q> TCC0 Capture Channel 7 Enable
+// <i> Indicates whether the TCC0 Capture Channel 7 is enabled or not
+// <id> tcc_arch_cpten7
+#ifndef CONF_TCC0_CPTEN7
+#define CONF_TCC0_CPTEN7 0
+#endif
+// </hidden>
+
+// <q> TCC0 Lock update
+// <i> Indicates whether the TCC0 Lock update is enabled or not
+// <id> tcc_arch_lupd
+#ifndef CONF_TCC0_LUPD
+#define CONF_TCC0_LUPD 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL B register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC0_DIR     0
+//#define CONF_TCC0_ONESHOT 0
+
+/* Commented intentionally. No fault control for timers. */
+/*#define CONF_TCC0_FAULT_A_SRC       TCC_FCTRLA_SRC_DISABLE_Val
+#define CONF_TCC0_FAULT_A_KEEP        0
+#define CONF_TCC0_FAULT_A_QUAL        0
+#define CONF_TCC0_FAULT_A_BLANK       TCC_FCTRLA_BLANK_DISABLE_Val
+#define CONF_TCC0_FAULT_A_RESTART     0
+#define CONF_TCC0_FAULT_A_HALT        TCC_FCTRLA_HALT_DISABLE_Val
+#define CONF_TCC0_FAULT_A_CHSEL       TCC_FCTRLA_CHSEL_CC0_Val
+#define CONF_TCC0_FAULT_A_CAPTURE     TCC_FCTRLA_CAPTURE_DISABLE_Val
+#define CONF_TCC0_FAULT_A_BLACNKPRESC 0
+#define CONF_TCC0_FAULT_A_BLANKVAL    0
+#define CONF_TCC0_FAULT_A_FILTERVAL   0
+
+#define CONF_TCC0_FAULT_B_SRC         TCC_FCTRLB_SRC_DISABLE_Val
+#define CONF_TCC0_FAULT_B_KEEP        0
+#define CONF_TCC0_FAULT_B_QUAL        0
+#define CONF_TCC0_FAULT_B_BLANK       TCC_FCTRLB_BLANK_DISABLE_Val
+#define CONF_TCC0_FAULT_B_RESTART     0
+#define CONF_TCC0_FAULT_B_HALT        TCC_FCTRLB_HALT_DISABLE_Val
+#define CONF_TCC0_FAULT_B_CHSEL       TCC_FCTRLB_CHSEL_CC0_Val
+#define CONF_TCC0_FAULT_B_CAPTURE     TCC_FCTRLB_CAPTURE_DISABLE_Val
+#define CONF_TCC0_FAULT_B_BLACNKPRESC 0
+#define CONF_TCC0_FAULT_B_BLANKVAL    0
+#define CONF_TCC0_FAULT_B_FILTERVAL   0*/
+
+/* Commented intentionally. No dead-time control for timers. */
+/*#define CONF_TCC0_OTMX   0
+#define CONF_TCC0_DTIEN0 0
+#define CONF_TCC0_DTIEN1 0
+#define CONF_TCC0_DTIEN2 0
+#define CONF_TCC0_DTIEN3 0
+#define CONF_TCC0_DTHS   0*/
+
+/* Commented intentionally. No driver control for timers. */
+/*#define CONF_TCC0_NRE0       0
+#define CONF_TCC0_NRE1       0
+#define CONF_TCC0_NRE2       0
+#define CONF_TCC0_NRE3       0
+#define CONF_TCC0_NRE4       0
+#define CONF_TCC0_NRE5       0
+#define CONF_TCC0_NRE6       0
+#define CONF_TCC0_NRE7       0
+#define CONF_TCC0_NVR0       0
+#define CONF_TCC0_NVR1       0
+#define CONF_TCC0_NVR2       0
+#define CONF_TCC0_NVR3       0
+#define CONF_TCC0_NVR4       0
+#define CONF_TCC0_NVR5       0
+#define CONF_TCC0_NVR6       0
+#define CONF_TCC0_NVR7       0
+#define CONF_TCC0_INVEN0     0
+#define CONF_TCC0_INVEN1     0
+#define CONF_TCC0_INVEN2     0
+#define CONF_TCC0_INVEN3     0
+#define CONF_TCC0_INVEN4     0
+#define CONF_TCC0_INVEN5     0
+#define CONF_TCC0_INVEN6     0
+#define CONF_TCC0_INVEN7     0
+#define CONF_TCC0_FILTERVAL0 0
+#define CONF_TCC0_FILTERVAL1 0*/
+
+// <q> TCC0 Debug Running Mode
+// <i> Indicates whether the TCC0 Debug Running Mode is enabled or not
+// <id> tcc_arch_dbgrun
+#ifndef CONF_TCC0_DBGRUN
+#define CONF_TCC0_DBGRUN 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of Debug Control register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC0_FDDBD  0
+
+// <e> Event control
+// <id> timer_event_control
+#ifndef CONF_TCC0_EVENT_CONTROL_ENABLE
+#define CONF_TCC0_EVENT_CONTROL_ENABLE 1
+#endif
+
+// <q> Match or Capture Channel 0 Event Output
+// <i> This bit indicates whether match/capture event on channel 0 is enabled and will be generated
+// <id> tcc_arch_mceo0
+#ifndef CONF_TCC0_MCEO0
+#define CONF_TCC0_MCEO0 0
+#endif
+
+// <q> Match or Capture Channel 0 Event Input
+// <i> This bit indicates whether match/capture 0 incoming event is enabled
+// <id> tcc_arch_mcei0
+#ifndef CONF_TCC0_MCEI0
+#define CONF_TCC0_MCEI0 0
+#endif
+// <q> Match or Capture Channel 1 Event Output
+// <i> This bit indicates whether match/capture event on channel 1 is enabled and will be generated
+// <id> tcc_arch_mceo1
+#ifndef CONF_TCC0_MCEO1
+#define CONF_TCC0_MCEO1 0
+#endif
+
+// <q> Match or Capture Channel 1 Event Input
+// <i> This bit indicates whether match/capture 1 incoming event is enabled
+// <id> tcc_arch_mcei1
+#ifndef CONF_TCC0_MCEI1
+#define CONF_TCC0_MCEI1 0
+#endif
+// <q> Match or Capture Channel 2 Event Output
+// <i> This bit indicates whether match/capture event on channel 2 is enabled and will be generated
+// <id> tcc_arch_mceo2
+#ifndef CONF_TCC0_MCEO2
+#define CONF_TCC0_MCEO2 0
+#endif
+
+// <q> Match or Capture Channel 2 Event Input
+// <i> This bit indicates whether match/capture 2 incoming event is enabled
+// <id> tcc_arch_mcei2
+#ifndef CONF_TCC0_MCEI2
+#define CONF_TCC0_MCEI2 0
+#endif
+// <q> Match or Capture Channel 3 Event Output
+// <i> This bit indicates whether match/capture event on channel 3 is enabled and will be generated
+// <id> tcc_arch_mceo3
+#ifndef CONF_TCC0_MCEO3
+#define CONF_TCC0_MCEO3 0
+#endif
+
+// <q> Match or Capture Channel 3 Event Input
+// <i> This bit indicates whether match/capture 3 incoming event is enabled
+// <id> tcc_arch_mcei3
+#ifndef CONF_TCC0_MCEI3
+#define CONF_TCC0_MCEI3 0
+#endif
+// <q> Match or Capture Channel 4 Event Output
+// <i> This bit indicates whether match/capture event on channel 4 is enabled and will be generated
+// <id> tcc_arch_mceo4
+#ifndef CONF_TCC0_MCEO4
+#define CONF_TCC0_MCEO4 0
+#endif
+
+// <q> Match or Capture Channel 4 Event Input
+// <i> This bit indicates whether match/capture 4 incoming event is enabled
+// <id> tcc_arch_mcei4
+#ifndef CONF_TCC0_MCEI4
+#define CONF_TCC0_MCEI4 0
+#endif
+// <q> Match or Capture Channel 5 Event Output
+// <i> This bit indicates whether match/capture event on channel 5 is enabled and will be generated
+// <id> tcc_arch_mceo5
+#ifndef CONF_TCC0_MCEO5
+#define CONF_TCC0_MCEO5 0
+#endif
+
+// <q> Match or Capture Channel 5 Event Input
+// <i> This bit indicates whether match/capture 5 incoming event is enabled
+// <id> tcc_arch_mcei5
+#ifndef CONF_TCC0_MCEI5
+#define CONF_TCC0_MCEI5 0
+#endif
+
+// <q> Timer/Counter Event Input 0
+// <i> This bit is used to enable input event 0 to the TCC
+// <id> tcc_arch_tcei0
+#ifndef CONF_TCC0_TCEI0
+#define CONF_TCC0_TCEI0 0
+#endif
+
+// <q> Timer/Counter Event Input 0 Invert
+// <i> This bit inverts the event 0 input
+// <id> tcc_arch_tceinv0
+#ifndef CONF_TCC0_TCINV0
+#define CONF_TCC0_TCINV0 0
+#endif
+// <q> Timer/Counter Event Input 1
+// <i> This bit is used to enable input event 1 to the TCC
+// <id> tcc_arch_tcei1
+#ifndef CONF_TCC0_TCEI1
+#define CONF_TCC0_TCEI1 0
+#endif
+
+// <q> Timer/Counter Event Input 1 Invert
+// <i> This bit inverts the event 1 input
+// <id> tcc_arch_tceinv1
+#ifndef CONF_TCC0_TCINV1
+#define CONF_TCC0_TCINV1 0
+#endif
+
+// <q> Timer/Counter Event Output
+// <i> This bit is used to enable the counter cycle event.
+//<id> tcc_arch_cnteo
+#ifndef CONF_TCC0_CNTEO
+#define CONF_TCC0_CNTEO 0
+#endif
+
+// <q> Re-trigger Event Output
+// <i> This bit is used to enable the counter re-trigger event.
+//<id> tcc_arch_trgeo
+#ifndef CONF_TCC0_TRGEO
+#define CONF_TCC0_TRGEO 0
+#endif
+
+// <q> Overflow/Underflow Event Output
+// <i> This bit is used to enable enable event on overflow/underflow.
+//<id> tcc_arch_ovfeo
+#ifndef CONF_TCC0_OVFEO
+#define CONF_TCC0_OVFEO 1
+#endif
+
+// <o> Timer/Counter Interrupt and Event Output Selection
+// <0=> An interrupt/event is generated when a new counter cycle starts
+// <1=> An interrupt/event is generated when a counter cycle ends
+// <2=> An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
+// <3=> An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
+// <i> These bits define on which part of the counter cycle the counter event output is generated
+// <id> tcc_arch_cntsel
+#ifndef CONF_TCC0_CNTSEL
+#define CONF_TCC0_CNTSEL 0
+#endif
+
+// <o> Timer/Counter Event Input 0 Action
+// <0=>Event action disabled
+// <1=>Start restart or re-trigger on event
+// <2=>Count on event
+// <3=>Start on event
+// <4=>Increment on event
+// <5=>Count on active state of asynchronous event
+// <6=>Capture overflow times (Max value)
+// <7=>Non-recoverable fault
+// <i> These bits define the action the TCC performs on TCE0 event input 0
+// <id> tcc_arch_evact0
+#ifndef CONF_TCC0_EVACT0
+#define CONF_TCC0_EVACT0 0
+#endif
+
+// <o> Timer/Counter Event Input 1 Action
+// <0=>Event action disabled
+// <1=>Re-trigger counter on event
+// <2=>Direction control
+// <3=>Stop counter on event
+// <4=>Decrement counter on event
+// <5=>Period capture value in CC0 register, pulse width capture value in CC1 register
+// <6=>Period capture value in CC1 register, pulse width capture value in CC0 register
+// <7=>Non-recoverable fault
+// <i> These bits define the action the TCC performs on TCE0 event input 0
+// <id> tcc_arch_evact1
+#ifndef CONF_TCC0_EVACT1
+#define CONF_TCC0_EVACT1 0
+#endif
+// </e>
+
+/* Commented intentionally. No pattern control for timers. */
+/*#define CONF_TCC0_PGE0 0
+#define CONF_TCC0_PGE1 0
+#define CONF_TCC0_PGE2 0
+#define CONF_TCC0_PGE3 0
+#define CONF_TCC0_PGE4 0
+#define CONF_TCC0_PGE5 0
+#define CONF_TCC0_PGE6 0
+#define CONF_TCC0_PGE7 0
+#define CONF_TCC0_PGV0 0
+#define CONF_TCC0_PGV1 0
+#define CONF_TCC0_PGV2 0
+#define CONF_TCC0_PGV3 0
+#define CONF_TCC0_PGV4 0
+#define CONF_TCC0_PGV5 0
+#define CONF_TCC0_PGV6 0
+#define CONF_TCC0_PGV7 0*/
+
+/* Commented intentionally. No pattern waveform control for timers. */
+/*#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_MFRQ_Val
+#define CONF_TCC0_RAMP    TCC_WAVE_RAMP_RAMP1_Val
+#define CONF_TCC0_CIPEREN 0
+#define CONF_TCC0_CICCEN0 0
+#define CONF_TCC0_CICCEN1 0
+#define CONF_TCC0_CICCEN2 0
+#define CONF_TCC0_CICCEN3 0
+#define CONF_TCC0_POL0    0
+#define CONF_TCC0_POL1    0
+#define CONF_TCC0_POL2    0
+#define CONF_TCC0_POL3    0
+#define CONF_TCC0_POL4    0
+#define CONF_TCC0_POL5    0
+#define CONF_TCC0_POL6    0
+#define CONF_TCC0_POL7    0
+#define CONF_TCC0_SWAP0   0
+#define CONF_TCC0_SWAP1   0
+#define CONF_TCC0_SWAP2   0
+#define CONF_TCC0_SWAP3   0*/
+
+//<o> TCC0 Compare and Capture value 0 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc0
+#ifndef CONF_TCC0_CC0
+#define CONF_TCC0_CC0 0x0
+#endif
+
+//<o> TCC0 Compare and Capture value 1 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc1
+#ifndef CONF_TCC0_CC1
+#define CONF_TCC0_CC1 0x0
+#endif
+
+//<o> TCC0 Compare and Capture value 2 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc2
+#ifndef CONF_TCC0_CC2
+#define CONF_TCC0_CC2 0x0
+#endif
+
+//<o> TCC0 Compare and Capture value 3 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc3
+#ifndef CONF_TCC0_CC3
+#define CONF_TCC0_CC3 0x0
+#endif
+
+//<o> TCC0 Compare and Capture value 4 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc4
+#ifndef CONF_TCC0_CC4
+#define CONF_TCC0_CC4 0x0
+#endif
+
+//<o> TCC0 Compare and Capture value 5 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc5
+#ifndef CONF_TCC0_CC5
+#define CONF_TCC0_CC5 0x0
+#endif
+
+/* Commented intentionally. No pattern control for timers. */
+/*#define CONF_TCC0_PATTB_PGEB0 0
+#define CONF_TCC0_PATTB_PGEB1 0
+#define CONF_TCC0_PATTB_PGEB2 0
+#define CONF_TCC0_PATTB_PGEB3 0
+#define CONF_TCC0_PATTB_PGEB4 0
+#define CONF_TCC0_PATTB_PGEB5 0
+#define CONF_TCC0_PATTB_PGEB6 0
+#define CONF_TCC0_PATTB_PGEB7 0
+#define CONF_TCC0_PATTB_PGVB0 0
+#define CONF_TCC0_PATTB_PGVB1 0
+#define CONF_TCC0_PATTB_PGVB2 0
+#define CONF_TCC0_PATTB_PGVB3 0
+#define CONF_TCC0_PATTB_PGVB4 0
+#define CONF_TCC0_PATTB_PGVB5 0
+#define CONF_TCC0_PATTB_PGVB6 0
+#define CONF_TCC0_PATTB_PGVB7 0*/
+
+/* Commented intentionally. No waveform control for timers. */
+/*#define CONF_TCC0_WAVEGENB TCC_WAVEB_WAVEGENB_MFRQ_Val
+#define CONF_TCC0_RAMPB    TCC_WAVE_RAMP_RAMP1_Val
+#define CONF_TCC0_CIPERENB 0
+#define CONF_TCC0_CICCEN0B 0
+#define CONF_TCC0_CICCEN1B 0
+#define CONF_TCC0_CICCEN2B 0
+#define CONF_TCC0_CICCEN3B 0
+#define CONF_TCC0_POL0B    0
+#define CONF_TCC0_POL1B    0
+#define CONF_TCC0_POL2B    0
+#define CONF_TCC0_POL3B    0
+#define CONF_TCC0_POL4B    0
+#define CONF_TCC0_POL5B    0
+#define CONF_TCC0_POL6B    0
+#define CONF_TCC0_POL7B    0
+#define CONF_TCC0_SWAP0B   0
+#define CONF_TCC0_SWAP1B   0
+#define CONF_TCC0_SWAP2B   0
+#define CONF_TCC0_SWAP3B   0*/
+
+/* Commented intentionally. No buffering for timers. */
+/*#define CONF_TCC0_PERB 0
+#define CONF_TCC0_CCB0 0
+#define CONF_TCC0_CCB1 0
+#define CONF_TCC0_CCB2 0
+#define CONF_TCC0_CCB3 0*/
+// </h>
+
+#define CONF_TCC0_CTRLA                                                                                                \
+	TCC_CTRLA_PRESCALER(CONF_TCC0_PRESCALER) | (CONF_TCC0_RUNSTDBY << TCC_CTRLA_RUNSTDBY_Pos)                          \
+	    | TCC_CTRLA_PRESCSYNC(CONF_TCC0_PRESCSYNC) | (CONF_TCC0_CPTEN0 << TCC_CTRLA_CPTEN0_Pos)                        \
+	    | (CONF_TCC0_CPTEN1 << TCC_CTRLA_CPTEN1_Pos) | (CONF_TCC0_CPTEN2 << TCC_CTRLA_CPTEN2_Pos)                      \
+	    | (CONF_TCC0_CPTEN3 << TCC_CTRLA_CPTEN3_Pos) | (CONF_TCC0_CPTEN4 << TCC_CTRLA_CPTEN4_Pos)                      \
+	    | (CONF_TCC0_CPTEN5 << TCC_CTRLA_CPTEN5_Pos) | (CONF_TCC0_ALOCK << TCC_CTRLA_ALOCK_Pos)
+#define CONF_TCC0_CTRLB (CONF_TCC0_LUPD << TCC_CTRLBSET_LUPD_Pos)
+#define CONF_TCC0_DBGCTRL (CONF_TCC0_DBGRUN << TCC_DBGCTRL_DBGRUN_Pos)
+#define CONF_TCC0_EVCTRL                                                                                               \
+	TCC_EVCTRL_CNTSEL(CONF_TCC0_CNTSEL) | (CONF_TCC0_OVFEO << TCC_EVCTRL_OVFEO_Pos)                                    \
+	    | (CONF_TCC0_TRGEO << TCC_EVCTRL_TRGEO_Pos) | (CONF_TCC0_CNTEO << TCC_EVCTRL_CNTEO_Pos)                        \
+	    | (CONF_TCC0_MCEO0 << TCC_EVCTRL_MCEO0_Pos) | (CONF_TCC0_MCEI0 << TCC_EVCTRL_MCEI0_Pos)                        \
+	    | (CONF_TCC0_MCEO1 << TCC_EVCTRL_MCEO1_Pos) | (CONF_TCC0_MCEI1 << TCC_EVCTRL_MCEI1_Pos)                        \
+	    | (CONF_TCC0_MCEO2 << TCC_EVCTRL_MCEO2_Pos) | (CONF_TCC0_MCEI2 << TCC_EVCTRL_MCEI2_Pos)                        \
+	    | (CONF_TCC0_MCEO3 << TCC_EVCTRL_MCEO3_Pos) | (CONF_TCC0_MCEI3 << TCC_EVCTRL_MCEI3_Pos)                        \
+	    | (CONF_TCC0_MCEO4 << TCC_EVCTRL_MCEO4_Pos) | (CONF_TCC0_MCEI4 << TCC_EVCTRL_MCEI4_Pos)                        \
+	    | (CONF_TCC0_MCEO5 << TCC_EVCTRL_MCEO5_Pos) | (CONF_TCC0_MCEI5 << TCC_EVCTRL_MCEI5_Pos)                        \
+	    | (CONF_TCC0_TCEI0 << TCC_EVCTRL_TCEI0_Pos) | (CONF_TCC0_TCEI1 << TCC_EVCTRL_TCEI1_Pos)                        \
+	    | (CONF_TCC0_TCINV0 << TCC_EVCTRL_TCINV0_Pos) | (CONF_TCC0_TCINV1 << TCC_EVCTRL_TCINV1_Pos)                    \
+	    | TCC_EVCTRL_EVACT1(CONF_TCC0_EVACT1) | TCC_EVCTRL_EVACT0(CONF_TCC0_EVACT0)
+
+#include <peripheral_clk_config.h>
+#ifndef CONF_TCC1_ENABLE
+#define CONF_TCC1_ENABLE 1
+#endif
+
+#ifndef CONF_TCC1_PWM_ENABLE
+#define CONF_TCC1_PWM_ENABLE 1
+#endif
+
+// <h> Basic settings
+// <y> TCC1 Prescaler
+// <TCC_CTRLA_PRESCALER_DIV1_Val"> No division
+// <TCC_CTRLA_PRESCALER_DIV2_Val"> Divide by 2
+// <TCC_CTRLA_PRESCALER_DIV4_Val"> Divide by 4
+// <TCC_CTRLA_PRESCALER_DIV8_Val"> Divide by 8
+// <TCC_CTRLA_PRESCALER_DIV16_Val"> Divide by 16
+// <TCC_CTRLA_PRESCALER_DIV64_Val"> Divide by 64
+// <TCC_CTRLA_PRESCALER_DIV256_Val"> Divide by 256
+// <TCC_CTRLA_PRESCALER_DIV1024_Val"> Divide by 1024
+// <i> This defines the TCC1 prescaler value
+// <id> tcc_prescaler
+#ifndef CONF_TCC1_PRESCALER
+#define CONF_TCC1_PRESCALER TCC_CTRLA_PRESCALER_DIV2_Val
+#endif
+
+// <hidden>
+//<o> TCC1 Period Value <0x000000-0xFFFFFF>
+// <id> tcc_per
+#ifndef CONF_TCC1_PER
+#define CONF_TCC1_PER 0x2710
+#endif
+// </hidden>
+
+// </h>
+
+// <h> PWM Waveform Output settings
+// <o> TCC1 Waveform Period Value (uS) <0x00-0xFFFFFFFF>
+// <i> The unit of this value is us.
+// <id> tcc_arch_wave_per_val
+#ifndef CONF_TCC1_WAVE_PER_VAL
+#define CONF_TCC1_WAVE_PER_VAL 0x30
+#endif
+
+// <o> TCC1 Waveform Duty Value (0.1%) <0x00-0x03E8>
+// <i> The unit of this value is 1/1000.
+// <id> tcc_arch_wave_duty_val
+#ifndef CONF_TCC1_WAVE_DUTY_VAL
+#define CONF_TCC1_WAVE_DUTY_VAL 0x1f4
+#endif
+
+// <o> TCC1 Waveform Channel Select <0x00-0x03>
+// <i> Index of the Compare Channel register, into which the Waveform Duty Value is written.
+// <i> Give index of the Compare Channel register here in 0x00-0x03 range.
+// <id> tcc_arch_sel_ch
+#ifndef CONF_TCC1_SEL_CH
+#define CONF_TCC1_SEL_CH 0x2
+#endif
+
+/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
+#if CONF_TCC1_PRESCALER < TCC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TCC1_PER_REG                                                                                              \
+	((uint32_t)(((double)CONF_TCC1_WAVE_PER_VAL * CONF_GCLK_TCC1_FREQUENCY) / 1000000 / (1 << CONF_TCC1_PRESCALER) - 1))
+#define CONF_TCC1_CCX_REG ((uint32_t)(((double)(double)CONF_TCC1_PER_REG * CONF_TCC1_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC1_PRESCALER == TCC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TCC1_PER_REG ((uint32_t)(((double)CONF_TCC1_WAVE_PER_VAL * CONF_GCLK_TCC1_FREQUENCY) / 64000000 - 1))
+#define CONF_TCC1_CCX_REG ((uint32_t)(((double)CONF_TCC1_PER_REG * CONF_TCC1_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC1_PRESCALER == TCC_CTRLA_PRESCALER_DIV256_Val
+#define CONF_TCC1_PER_REG ((uint32_t)(((double)CONF_TCC1_WAVE_PER_VAL * CONF_GCLK_TCC1_FREQUENCY) / 256000000 - 1))
+#define CONF_TCC1_CCX_REG ((uint32_t)(((double)CONF_TCC1_PER_REG * CONF_TCC1_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC1_PRESCALER == TCC_CTRLA_PRESCALER_DIV1024_Val
+#define CONF_TCC1_PER_REG ((uint32_t)(((double)CONF_TCC1_WAVE_PER_VAL * CONF_GCLK_TCC1_FREQUENCY) / 1024000000 - 1))
+#define CONF_TCC1_CCX_REG ((uint32_t)(((double)CONF_TCC1_PER_REG * CONF_TCC1_WAVE_DUTY_VAL) / 1000))
+#endif
+// </h>
+
+// <h> Advanced settings
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL A register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC1_RESOLUTION TCC_CTRLA_RESOLUTION_NONE_Val
+// <q> Run in standby
+// <i> Indicates whether the TCC1 will continue running in standby sleep mode or not
+// <id> tcc_arch_runstdby
+#ifndef CONF_TCC1_RUNSTDBY
+#define CONF_TCC1_RUNSTDBY 0
+#endif
+
+// <y> TCC1 Prescaler and Counter Synchronization Selection
+// <TCC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
+// <TCC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
+// <TCC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
+// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock.
+// <id> tcc_arch_prescsync
+#ifndef CONF_TCC1_PRESCSYNC
+#define CONF_TCC1_PRESCSYNC TCC_CTRLA_PRESCSYNC_GCLK_Val
+#endif
+
+// <y> TCC1 Waveform Generation Selection
+// <TCC_WAVE_WAVEGEN_NPWM_Val"> Single-slope PWM
+// <TCC_WAVE_WAVEGEN_DSCRITICAL_Val"> Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
+// <TCC_WAVE_WAVEGEN_DSBOTTOM_Val"> Dual-slope, interrupt/event at ZERO (DSBOTTOM)
+// <TCC_WAVE_WAVEGEN_DSBOTH_Val"> Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
+// <TCC_WAVE_WAVEGEN_DSTOP_Val"> Dual-slope, interrupt/event at Top (DSTOP)
+// <id> tcc_arch_wavegen
+#ifndef CONF_TCC1_WAVEGEN
+#define CONF_TCC1_WAVEGEN TCC_WAVE_WAVEGEN_DSBOTH_Val
+#endif
+// <q> TCC1 Auto Lock
+// <i> Indicates whether the TCC1 Auto Lock is enabled or not
+// <id> tcc_arch_alock
+#ifndef CONF_TCC1_ALOCK
+#define CONF_TCC1_ALOCK 0
+#endif
+
+// <q> TCC1 Capture Channel 0 Enable
+// <i> Indicates whether the TCC1 Capture Channel 0 is enabled or not
+// <id> tcc_arch_cpten0
+#ifndef CONF_TCC1_CPTEN0
+#define CONF_TCC1_CPTEN0 0
+#endif
+
+// <q> TCC1 Capture Channel 1 Enable
+// <i> Indicates whether the TCC1 Capture Channel 1 is enabled or not
+// <id> tcc_arch_cpten1
+#ifndef CONF_TCC1_CPTEN1
+#define CONF_TCC1_CPTEN1 0
+#endif
+
+// <q> TCC1 Capture Channel 2 Enable
+// <i> Indicates whether the TCC1 Capture Channel 2 is enabled or not
+// <id> tcc_arch_cpten2
+#ifndef CONF_TCC1_CPTEN2
+#define CONF_TCC1_CPTEN2 0
+#endif
+
+// <q> TCC1 Capture Channel 3 Enable
+// <i> Indicates whether the TCC1 Capture Channel 3 is enabled or not
+// <id> tcc_arch_cpten3
+#ifndef CONF_TCC1_CPTEN3
+#define CONF_TCC1_CPTEN3 0
+#endif
+
+// <hidden>
+// <q> TCC1 Capture Channel 4 Enable
+// <i> Indicates whether the TCC1 Capture Channel 4 is enabled or not
+// <id> tcc_arch_cpten4
+#ifndef CONF_TCC1_CPTEN4
+#define CONF_TCC1_CPTEN4 0
+#endif
+// </hidden>
+// <hidden>
+// <q> TCC1 Capture Channel 5 Enable
+// <i> Indicates whether the TCC1 Capture Channel 5 is enabled or not
+// <id> tcc_arch_cpten5
+#ifndef CONF_TCC1_CPTEN5
+#define CONF_TCC1_CPTEN5 0
+#endif
+// </hidden>
+// <hidden>
+// <q> TCC1 Capture Channel 6 Enable
+// <i> Indicates whether the TCC1 Capture Channel 6 is enabled or not
+// <id> tcc_arch_cpten6
+#ifndef CONF_TCC1_CPTEN6
+#define CONF_TCC1_CPTEN6 0
+#endif
+// </hidden>
+// <hidden>
+// <q> TCC1 Capture Channel 7 Enable
+// <i> Indicates whether the TCC1 Capture Channel 7 is enabled or not
+// <id> tcc_arch_cpten7
+#ifndef CONF_TCC1_CPTEN7
+#define CONF_TCC1_CPTEN7 0
+#endif
+// </hidden>
+
+// <q> TCC1 Lock update
+// <i> Indicates whether the TCC1 Lock update is enabled or not
+// <id> tcc_arch_lupd
+#ifndef CONF_TCC1_LUPD
+#define CONF_TCC1_LUPD 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL B register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC1_DIR     0
+//#define CONF_TCC1_ONESHOT 0
+
+/* Commented intentionally. No fault control for timers. */
+/*#define CONF_TCC1_FAULT_A_SRC       TCC_FCTRLA_SRC_DISABLE_Val
+#define CONF_TCC1_FAULT_A_KEEP        0
+#define CONF_TCC1_FAULT_A_QUAL        0
+#define CONF_TCC1_FAULT_A_BLANK       TCC_FCTRLA_BLANK_DISABLE_Val
+#define CONF_TCC1_FAULT_A_RESTART     0
+#define CONF_TCC1_FAULT_A_HALT        TCC_FCTRLA_HALT_DISABLE_Val
+#define CONF_TCC1_FAULT_A_CHSEL       TCC_FCTRLA_CHSEL_CC0_Val
+#define CONF_TCC1_FAULT_A_CAPTURE     TCC_FCTRLA_CAPTURE_DISABLE_Val
+#define CONF_TCC1_FAULT_A_BLACNKPRESC 0
+#define CONF_TCC1_FAULT_A_BLANKVAL    0
+#define CONF_TCC1_FAULT_A_FILTERVAL   0
+
+#define CONF_TCC1_FAULT_B_SRC         TCC_FCTRLB_SRC_DISABLE_Val
+#define CONF_TCC1_FAULT_B_KEEP        0
+#define CONF_TCC1_FAULT_B_QUAL        0
+#define CONF_TCC1_FAULT_B_BLANK       TCC_FCTRLB_BLANK_DISABLE_Val
+#define CONF_TCC1_FAULT_B_RESTART     0
+#define CONF_TCC1_FAULT_B_HALT        TCC_FCTRLB_HALT_DISABLE_Val
+#define CONF_TCC1_FAULT_B_CHSEL       TCC_FCTRLB_CHSEL_CC0_Val
+#define CONF_TCC1_FAULT_B_CAPTURE     TCC_FCTRLB_CAPTURE_DISABLE_Val
+#define CONF_TCC1_FAULT_B_BLACNKPRESC 0
+#define CONF_TCC1_FAULT_B_BLANKVAL    0
+#define CONF_TCC1_FAULT_B_FILTERVAL   0*/
+
+/* Commented intentionally. No dead-time control for timers. */
+/*#define CONF_TCC1_OTMX   0
+#define CONF_TCC1_DTIEN0 0
+#define CONF_TCC1_DTIEN1 0
+#define CONF_TCC1_DTIEN2 0
+#define CONF_TCC1_DTIEN3 0
+#define CONF_TCC1_DTHS   0*/
+
+/* Commented intentionally. No driver control for timers. */
+/*#define CONF_TCC1_NRE0       0
+#define CONF_TCC1_NRE1       0
+#define CONF_TCC1_NRE2       0
+#define CONF_TCC1_NRE3       0
+#define CONF_TCC1_NRE4       0
+#define CONF_TCC1_NRE5       0
+#define CONF_TCC1_NRE6       0
+#define CONF_TCC1_NRE7       0
+#define CONF_TCC1_NVR0       0
+#define CONF_TCC1_NVR1       0
+#define CONF_TCC1_NVR2       0
+#define CONF_TCC1_NVR3       0
+#define CONF_TCC1_NVR4       0
+#define CONF_TCC1_NVR5       0
+#define CONF_TCC1_NVR6       0
+#define CONF_TCC1_NVR7       0
+#define CONF_TCC1_INVEN0     0
+#define CONF_TCC1_INVEN1     0
+#define CONF_TCC1_INVEN2     0
+#define CONF_TCC1_INVEN3     0
+#define CONF_TCC1_INVEN4     0
+#define CONF_TCC1_INVEN5     0
+#define CONF_TCC1_INVEN6     0
+#define CONF_TCC1_INVEN7     0
+#define CONF_TCC1_FILTERVAL0 0
+#define CONF_TCC1_FILTERVAL1 0*/
+
+// <q> TCC1 Debug Running Mode
+// <i> Indicates whether the TCC1 Debug Running Mode is enabled or not
+// <id> tcc_arch_dbgrun
+#ifndef CONF_TCC1_DBGRUN
+#define CONF_TCC1_DBGRUN 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of Debug Control register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC1_FDDBD  0
+
+// <e> Event control
+// <id> timer_event_control
+#ifndef CONF_TCC1_EVENT_CONTROL_ENABLE
+#define CONF_TCC1_EVENT_CONTROL_ENABLE 1
+#endif
+
+// <q> Match or Capture Channel 0 Event Output
+// <i> This bit indicates whether match/capture event on channel 0 is enabled and will be generated
+// <id> tcc_arch_mceo0
+#ifndef CONF_TCC1_MCEO0
+#define CONF_TCC1_MCEO0 0
+#endif
+
+// <q> Match or Capture Channel 0 Event Input
+// <i> This bit indicates whether match/capture 0 incoming event is enabled
+// <id> tcc_arch_mcei0
+#ifndef CONF_TCC1_MCEI0
+#define CONF_TCC1_MCEI0 0
+#endif
+// <q> Match or Capture Channel 1 Event Output
+// <i> This bit indicates whether match/capture event on channel 1 is enabled and will be generated
+// <id> tcc_arch_mceo1
+#ifndef CONF_TCC1_MCEO1
+#define CONF_TCC1_MCEO1 0
+#endif
+
+// <q> Match or Capture Channel 1 Event Input
+// <i> This bit indicates whether match/capture 1 incoming event is enabled
+// <id> tcc_arch_mcei1
+#ifndef CONF_TCC1_MCEI1
+#define CONF_TCC1_MCEI1 0
+#endif
+// <q> Match or Capture Channel 2 Event Output
+// <i> This bit indicates whether match/capture event on channel 2 is enabled and will be generated
+// <id> tcc_arch_mceo2
+#ifndef CONF_TCC1_MCEO2
+#define CONF_TCC1_MCEO2 0
+#endif
+
+// <q> Match or Capture Channel 2 Event Input
+// <i> This bit indicates whether match/capture 2 incoming event is enabled
+// <id> tcc_arch_mcei2
+#ifndef CONF_TCC1_MCEI2
+#define CONF_TCC1_MCEI2 0
+#endif
+// <q> Match or Capture Channel 3 Event Output
+// <i> This bit indicates whether match/capture event on channel 3 is enabled and will be generated
+// <id> tcc_arch_mceo3
+#ifndef CONF_TCC1_MCEO3
+#define CONF_TCC1_MCEO3 0
+#endif
+
+// <q> Match or Capture Channel 3 Event Input
+// <i> This bit indicates whether match/capture 3 incoming event is enabled
+// <id> tcc_arch_mcei3
+#ifndef CONF_TCC1_MCEI3
+#define CONF_TCC1_MCEI3 0
+#endif
+
+// <q> Timer/Counter Event Input 0
+// <i> This bit is used to enable input event 0 to the TCC
+// <id> tcc_arch_tcei0
+#ifndef CONF_TCC1_TCEI0
+#define CONF_TCC1_TCEI0 0
+#endif
+
+// <q> Timer/Counter Event Input 0 Invert
+// <i> This bit inverts the event 0 input
+// <id> tcc_arch_tceinv0
+#ifndef CONF_TCC1_TCINV0
+#define CONF_TCC1_TCINV0 0
+#endif
+// <q> Timer/Counter Event Input 1
+// <i> This bit is used to enable input event 1 to the TCC
+// <id> tcc_arch_tcei1
+#ifndef CONF_TCC1_TCEI1
+#define CONF_TCC1_TCEI1 0
+#endif
+
+// <q> Timer/Counter Event Input 1 Invert
+// <i> This bit inverts the event 1 input
+// <id> tcc_arch_tceinv1
+#ifndef CONF_TCC1_TCINV1
+#define CONF_TCC1_TCINV1 0
+#endif
+
+// <q> Timer/Counter Event Output
+// <i> This bit is used to enable the counter cycle event.
+//<id> tcc_arch_cnteo
+#ifndef CONF_TCC1_CNTEO
+#define CONF_TCC1_CNTEO 0
+#endif
+
+// <q> Re-trigger Event Output
+// <i> This bit is used to enable the counter re-trigger event.
+//<id> tcc_arch_trgeo
+#ifndef CONF_TCC1_TRGEO
+#define CONF_TCC1_TRGEO 0
+#endif
+
+// <q> Overflow/Underflow Event Output
+// <i> This bit is used to enable enable event on overflow/underflow.
+//<id> tcc_arch_ovfeo
+#ifndef CONF_TCC1_OVFEO
+#define CONF_TCC1_OVFEO 0
+#endif
+
+// <o> Timer/Counter Interrupt and Event Output Selection
+// <0=> An interrupt/event is generated when a new counter cycle starts
+// <1=> An interrupt/event is generated when a counter cycle ends
+// <2=> An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
+// <3=> An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
+// <i> These bits define on which part of the counter cycle the counter event output is generated
+// <id> tcc_arch_cntsel
+#ifndef CONF_TCC1_CNTSEL
+#define CONF_TCC1_CNTSEL 0
+#endif
+
+// <o> Timer/Counter Event Input 0 Action
+// <0=>Event action disabled
+// <1=>Start restart or re-trigger on event
+// <2=>Count on event
+// <3=>Start on event
+// <4=>Increment on event
+// <5=>Count on active state of asynchronous event
+// <6=>Capture overflow times (Max value)
+// <7=>Non-recoverable fault
+// <i> These bits define the action the TCC performs on TCE0 event input 0
+// <id> tcc_arch_evact0
+#ifndef CONF_TCC1_EVACT0
+#define CONF_TCC1_EVACT0 0
+#endif
+
+// <o> Timer/Counter Event Input 1 Action
+// <0=>Event action disabled
+// <1=>Re-trigger counter on event
+// <2=>Direction control
+// <3=>Stop counter on event
+// <4=>Decrement counter on event
+// <5=>Period capture value in CC0 register, pulse width capture value in CC1 register
+// <6=>Period capture value in CC1 register, pulse width capture value in CC0 register
+// <7=>Non-recoverable fault
+// <i> These bits define the action the TCC performs on TCE0 event input 0
+// <id> tcc_arch_evact1
+#ifndef CONF_TCC1_EVACT1
+#define CONF_TCC1_EVACT1 0
+#endif
+// </e>
+
+/* Commented intentionally. No pattern control for timers. */
+/*#define CONF_TCC1_PGE0 0
+#define CONF_TCC1_PGE1 0
+#define CONF_TCC1_PGE2 0
+#define CONF_TCC1_PGE3 0
+#define CONF_TCC1_PGE4 0
+#define CONF_TCC1_PGE5 0
+#define CONF_TCC1_PGE6 0
+#define CONF_TCC1_PGE7 0
+#define CONF_TCC1_PGV0 0
+#define CONF_TCC1_PGV1 0
+#define CONF_TCC1_PGV2 0
+#define CONF_TCC1_PGV3 0
+#define CONF_TCC1_PGV4 0
+#define CONF_TCC1_PGV5 0
+#define CONF_TCC1_PGV6 0
+#define CONF_TCC1_PGV7 0*/
+
+/* Commented intentionally. No pattern waveform control for timers. */
+/*#define CONF_TCC1_WAVEGEN TCC_WAVE_WAVEGEN_MFRQ_Val
+#define CONF_TCC1_RAMP    TCC_WAVE_RAMP_RAMP1_Val
+#define CONF_TCC1_CIPEREN 0
+#define CONF_TCC1_CICCEN0 0
+#define CONF_TCC1_CICCEN1 0
+#define CONF_TCC1_CICCEN2 0
+#define CONF_TCC1_CICCEN3 0
+#define CONF_TCC1_POL0    0
+#define CONF_TCC1_POL1    0
+#define CONF_TCC1_POL2    0
+#define CONF_TCC1_POL3    0
+#define CONF_TCC1_POL4    0
+#define CONF_TCC1_POL5    0
+#define CONF_TCC1_POL6    0
+#define CONF_TCC1_POL7    0
+#define CONF_TCC1_SWAP0   0
+#define CONF_TCC1_SWAP1   0
+#define CONF_TCC1_SWAP2   0
+#define CONF_TCC1_SWAP3   0*/
+
+//<o> TCC1 Compare and Capture value 0 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc0
+#ifndef CONF_TCC1_CC0
+#define CONF_TCC1_CC0 0x0
+#endif
+
+//<o> TCC1 Compare and Capture value 1 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc1
+#ifndef CONF_TCC1_CC1
+#define CONF_TCC1_CC1 0x0
+#endif
+
+//<o> TCC1 Compare and Capture value 2 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc2
+#ifndef CONF_TCC1_CC2
+#define CONF_TCC1_CC2 0x0
+#endif
+
+//<o> TCC1 Compare and Capture value 3 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc3
+#ifndef CONF_TCC1_CC3
+#define CONF_TCC1_CC3 0x0
+#endif
+
+/* Commented intentionally. No pattern control for timers. */
+/*#define CONF_TCC1_PATTB_PGEB0 0
+#define CONF_TCC1_PATTB_PGEB1 0
+#define CONF_TCC1_PATTB_PGEB2 0
+#define CONF_TCC1_PATTB_PGEB3 0
+#define CONF_TCC1_PATTB_PGEB4 0
+#define CONF_TCC1_PATTB_PGEB5 0
+#define CONF_TCC1_PATTB_PGEB6 0
+#define CONF_TCC1_PATTB_PGEB7 0
+#define CONF_TCC1_PATTB_PGVB0 0
+#define CONF_TCC1_PATTB_PGVB1 0
+#define CONF_TCC1_PATTB_PGVB2 0
+#define CONF_TCC1_PATTB_PGVB3 0
+#define CONF_TCC1_PATTB_PGVB4 0
+#define CONF_TCC1_PATTB_PGVB5 0
+#define CONF_TCC1_PATTB_PGVB6 0
+#define CONF_TCC1_PATTB_PGVB7 0*/
+
+/* Commented intentionally. No waveform control for timers. */
+/*#define CONF_TCC1_WAVEGENB TCC_WAVEB_WAVEGENB_MFRQ_Val
+#define CONF_TCC1_RAMPB    TCC_WAVE_RAMP_RAMP1_Val
+#define CONF_TCC1_CIPERENB 0
+#define CONF_TCC1_CICCEN0B 0
+#define CONF_TCC1_CICCEN1B 0
+#define CONF_TCC1_CICCEN2B 0
+#define CONF_TCC1_CICCEN3B 0
+#define CONF_TCC1_POL0B    0
+#define CONF_TCC1_POL1B    0
+#define CONF_TCC1_POL2B    0
+#define CONF_TCC1_POL3B    0
+#define CONF_TCC1_POL4B    0
+#define CONF_TCC1_POL5B    0
+#define CONF_TCC1_POL6B    0
+#define CONF_TCC1_POL7B    0
+#define CONF_TCC1_SWAP0B   0
+#define CONF_TCC1_SWAP1B   0
+#define CONF_TCC1_SWAP2B   0
+#define CONF_TCC1_SWAP3B   0*/
+
+/* Commented intentionally. No buffering for timers. */
+/*#define CONF_TCC1_PERB 0
+#define CONF_TCC1_CCB0 0
+#define CONF_TCC1_CCB1 0
+#define CONF_TCC1_CCB2 0
+#define CONF_TCC1_CCB3 0*/
+// </h>
+
+#define CONF_TCC1_CTRLA                                                                                                \
+	TCC_CTRLA_PRESCALER(CONF_TCC1_PRESCALER) | (CONF_TCC1_RUNSTDBY << TCC_CTRLA_RUNSTDBY_Pos)                          \
+	    | TCC_CTRLA_PRESCSYNC(CONF_TCC1_PRESCSYNC) | (CONF_TCC1_CPTEN0 << TCC_CTRLA_CPTEN0_Pos)                        \
+	    | (CONF_TCC1_CPTEN1 << TCC_CTRLA_CPTEN1_Pos) | (CONF_TCC1_CPTEN2 << TCC_CTRLA_CPTEN2_Pos)                      \
+	    | (CONF_TCC1_CPTEN3 << TCC_CTRLA_CPTEN3_Pos) | (CONF_TCC1_ALOCK << TCC_CTRLA_ALOCK_Pos)
+#define CONF_TCC1_CTRLB (CONF_TCC1_LUPD << TCC_CTRLBSET_LUPD_Pos)
+#define CONF_TCC1_DBGCTRL (CONF_TCC1_DBGRUN << TCC_DBGCTRL_DBGRUN_Pos)
+#define CONF_TCC1_EVCTRL                                                                                               \
+	TCC_EVCTRL_CNTSEL(CONF_TCC1_CNTSEL) | (CONF_TCC1_OVFEO << TCC_EVCTRL_OVFEO_Pos)                                    \
+	    | (CONF_TCC1_TRGEO << TCC_EVCTRL_TRGEO_Pos) | (CONF_TCC1_CNTEO << TCC_EVCTRL_CNTEO_Pos)                        \
+	    | (CONF_TCC1_MCEO0 << TCC_EVCTRL_MCEO0_Pos) | (CONF_TCC1_MCEI0 << TCC_EVCTRL_MCEI0_Pos)                        \
+	    | (CONF_TCC1_MCEO1 << TCC_EVCTRL_MCEO1_Pos) | (CONF_TCC1_MCEI1 << TCC_EVCTRL_MCEI1_Pos)                        \
+	    | (CONF_TCC1_MCEO2 << TCC_EVCTRL_MCEO2_Pos) | (CONF_TCC1_MCEI2 << TCC_EVCTRL_MCEI2_Pos)                        \
+	    | (CONF_TCC1_MCEO3 << TCC_EVCTRL_MCEO3_Pos) | (CONF_TCC1_MCEI3 << TCC_EVCTRL_MCEI3_Pos)                        \
+	    | (CONF_TCC1_TCEI0 << TCC_EVCTRL_TCEI0_Pos) | (CONF_TCC1_TCEI1 << TCC_EVCTRL_TCEI1_Pos)                        \
+	    | (CONF_TCC1_TCINV0 << TCC_EVCTRL_TCINV0_Pos) | (CONF_TCC1_TCINV1 << TCC_EVCTRL_TCINV1_Pos)                    \
+	    | TCC_EVCTRL_EVACT1(CONF_TCC1_EVACT1) | TCC_EVCTRL_EVACT0(CONF_TCC1_EVACT0)
+
+// <<< end of configuration section >>>
+
+#endif // HPL_TCC_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/peripheral_clk_config.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/peripheral_clk_config.h
new file mode 100644
index 0000000..5fb0e21
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/peripheral_clk_config.h
@@ -0,0 +1,1229 @@
+/* Auto-generated config file peripheral_clk_config.h */
+#ifndef PERIPHERAL_CLK_CONFIG_H
+#define PERIPHERAL_CLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <y> ADC Clock Source
+// <id> adc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for ADC.
+#ifndef CONF_GCLK_ADC0_SRC
+#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_ADC0_FREQUENCY
+ * \brief ADC0's Clock frequency
+ */
+#ifndef CONF_GCLK_ADC0_FREQUENCY
+#define CONF_GCLK_ADC0_FREQUENCY 100000000
+#endif
+
+// <y> ADC Clock Source
+// <id> adc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for ADC.
+#ifndef CONF_GCLK_ADC1_SRC
+#define CONF_GCLK_ADC1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_ADC1_FREQUENCY
+ * \brief ADC1's Clock frequency
+ */
+#ifndef CONF_GCLK_ADC1_FREQUENCY
+#define CONF_GCLK_ADC1_FREQUENCY 100000000
+#endif
+
+// <y> CCL Clock Source
+// <id> ccl_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CCL.
+#ifndef CONF_GCLK_CCL_SRC
+#define CONF_GCLK_CCL_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_CCL_FREQUENCY
+ * \brief CCL's Clock frequency
+ */
+#ifndef CONF_GCLK_CCL_FREQUENCY
+#define CONF_GCLK_CCL_FREQUENCY 100000000
+#endif
+
+// <y> EIC Clock Source
+// <id> eic_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for EIC.
+#ifndef CONF_GCLK_EIC_SRC
+#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EIC_FREQUENCY
+ * \brief EIC's Clock frequency
+ */
+#ifndef CONF_GCLK_EIC_FREQUENCY
+#define CONF_GCLK_EIC_FREQUENCY 100000000
+#endif
+
+// <y> EVSYS Channel 0 Clock Source
+// <id> evsys_clk_selection_0
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 0.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 100000000
+#endif
+
+// <y> EVSYS Channel 1 Clock Source
+// <id> evsys_clk_selection_1
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 1.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 100000000
+#endif
+
+// <y> EVSYS Channel 2 Clock Source
+// <id> evsys_clk_selection_2
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 2.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 100000000
+#endif
+
+// <y> EVSYS Channel 3 Clock Source
+// <id> evsys_clk_selection_3
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 3.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 100000000
+#endif
+
+// <y> EVSYS Channel 4 Clock Source
+// <id> evsys_clk_selection_4
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 4.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 100000000
+#endif
+
+// <y> EVSYS Channel 5 Clock Source
+// <id> evsys_clk_selection_5
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 5.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 100000000
+#endif
+
+// <y> EVSYS Channel 6 Clock Source
+// <id> evsys_clk_selection_6
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 6.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 100000000
+#endif
+
+// <y> EVSYS Channel 7 Clock Source
+// <id> evsys_clk_selection_7
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 7.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 100000000
+#endif
+
+// <y> EVSYS Channel 8 Clock Source
+// <id> evsys_clk_selection_8
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 8.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 100000000
+#endif
+
+// <y> EVSYS Channel 9 Clock Source
+// <id> evsys_clk_selection_9
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 9.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 100000000
+#endif
+
+// <y> EVSYS Channel 10 Clock Source
+// <id> evsys_clk_selection_10
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 10.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 100000000
+#endif
+
+// <y> EVSYS Channel 11 Clock Source
+// <id> evsys_clk_selection_11
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 11.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_CPU_FREQUENCY
+ * \brief CPU's Clock frequency
+ */
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 100000000
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM0_CORE_SRC
+#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM0_SLOW_SRC
+#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY
+ * \brief SERCOM0's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY
+ * \brief SERCOM0's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM1_CORE_SRC
+#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
+#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
+ * \brief SERCOM1's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+ * \brief SERCOM1's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM2_CORE_SRC
+#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
+#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
+ * \brief SERCOM2's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
+ * \brief SERCOM2's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM5_CORE_SRC
+#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM5_SLOW_SRC
+#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM5_CORE_FREQUENCY
+ * \brief SERCOM5's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM5_SLOW_FREQUENCY
+ * \brief SERCOM5's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM5_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768
+#endif
+
+// <y> TC Clock Source
+// <id> tc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for TC.
+#ifndef CONF_GCLK_TC0_SRC
+#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TC0_FREQUENCY
+ * \brief TC0's Clock frequency
+ */
+#ifndef CONF_GCLK_TC0_FREQUENCY
+#define CONF_GCLK_TC0_FREQUENCY 2000000
+#endif
+
+// <y> TC Clock Source
+// <id> tc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for TC.
+#ifndef CONF_GCLK_TC1_SRC
+#define CONF_GCLK_TC1_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TC1_FREQUENCY
+ * \brief TC1's Clock frequency
+ */
+#ifndef CONF_GCLK_TC1_FREQUENCY
+#define CONF_GCLK_TC1_FREQUENCY 2000000
+#endif
+
+// <y> TC Clock Source
+// <id> tc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for TC.
+#ifndef CONF_GCLK_TC2_SRC
+#define CONF_GCLK_TC2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TC2_FREQUENCY
+ * \brief TC2's Clock frequency
+ */
+#ifndef CONF_GCLK_TC2_FREQUENCY
+#define CONF_GCLK_TC2_FREQUENCY 100000000
+#endif
+
+// <y> TC Clock Source
+// <id> tc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for TC.
+#ifndef CONF_GCLK_TC4_SRC
+#define CONF_GCLK_TC4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TC4_FREQUENCY
+ * \brief TC4's Clock frequency
+ */
+#ifndef CONF_GCLK_TC4_FREQUENCY
+#define CONF_GCLK_TC4_FREQUENCY 100000000
+#endif
+
+// <y> TCC Clock Source
+// <id> tcc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for TCC.
+#ifndef CONF_GCLK_TCC0_SRC
+#define CONF_GCLK_TCC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TCC0_FREQUENCY
+ * \brief TCC0's Clock frequency
+ */
+#ifndef CONF_GCLK_TCC0_FREQUENCY
+#define CONF_GCLK_TCC0_FREQUENCY 100000000
+#endif
+
+// <y> TCC Clock Source
+// <id> tcc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for TCC.
+#ifndef CONF_GCLK_TCC1_SRC
+#define CONF_GCLK_TCC1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TCC1_FREQUENCY
+ * \brief TCC1's Clock frequency
+ */
+#ifndef CONF_GCLK_TCC1_FREQUENCY
+#define CONF_GCLK_TCC1_FREQUENCY 100000000
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // PERIPHERAL_CLK_CONFIG_H
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Default.xml b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Default.xml
new file mode 100644
index 0000000..61fd46c
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Default.xml
@@ -0,0 +1,475 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Configurations xmlns:i="http://www.w3.org/2001/XMLSchema-instance" z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/" xmlns="DefaultValues">
+	<Configurations>
+		<Configuration z:Id="i2">
+			<Compiler_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>DebugLevel</d4p1:Key>
+					<d4p1:Value>None</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>IncludePaths</d4p1:Key>
+					<d4p1:Value>NDEBUG</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>MiscellaneousSettings</d4p1:Key>
+					<d4p1:Value>-std=gnu99</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>OptimizationLevel</d4p1:Key>
+					<d4p1:Value>Optimize for size (-Os)</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>SymbolDefines</d4p1:Key>
+					<d4p1:Value>NDEBUG</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>SymbolUndefines</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>Verbose</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>WarningsAsErrors</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.CLanguageExp</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.ChangeDefaultCharTypeUnsigned</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.ChangeDefaultBitFieldUnsigned</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.processormode</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.preprocessor.DoNotSearchSystemDirectories</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.preprocessor.PreprocessOnly</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.symbols.Default</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.directories.DefaultIncludePath</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.OtherFlags</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.PrepareDataForGarbageCollection</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.EnableFastMath</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.GeneratePositionIndependentCode</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.EnableLongCalls</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.OtherDebuggingFlags</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.GenerateGprofInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.GenerateProfInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.AllWarnings</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.ExtraWarnings</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.Undefined</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.CheckSyntaxOnly</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.Pedantic</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.PedanticWarningsAsErrors</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.InhibitAllWarnings</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.Device</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.CompileOnly</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.SupportAnsiPrograms</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.MakeFileDependent</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+			</Compiler_dictionary>
+			<Linker_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>Libraries</d4p1:Key>
+					<d4p1:Value>libm</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>LibrarySearchPath</d4p1:Key>
+					<d4p1:Value>$(ProjectDir)\Device_Startup</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>MiscellaneousSettings</d4p1:Key>
+					<d4p1:Value>-Tsamd51j18a_flash.ld</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.DoNotUseStandardStartFiles</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.DoNotUseDefaultLibraries</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.NoStartupOrDefaultLibs</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.OmitAllSymbolInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.NoSharedLibraries</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.GenerateMAPFile</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.UseNewlibNano</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.AdditionalSpecs</d4p1:Key>
+					<d4p1:Value>None</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.GarbageCollectUnusedSections</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.EnableFastMath</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.GeneratePositionIndependentCode</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.Flash</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.Sram</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.ExternalRAM</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.miscellaneous.OtherOptions</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.miscellaneous.OtherObjects</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+			</Linker_dictionary>
+			<Name>Release</Name>
+		</Configuration>
+		<Configuration z:Id="i3">
+			<Compiler_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>DebugLevel</d4p1:Key>
+					<d4p1:Value>Maximum (-g3)</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>IncludePaths</d4p1:Key>
+					<d4p1:Value>DEBUG</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>MiscellaneousSettings</d4p1:Key>
+					<d4p1:Value>-std=gnu99</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>OptimizationLevel</d4p1:Key>
+					<d4p1:Value>Optimize debugging experience (-Og)</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>SymbolDefines</d4p1:Key>
+					<d4p1:Value>DEBUG</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>SymbolUndefines</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>Verbose</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>WarningsAsErrors</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.CLanguageExp</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.ChangeDefaultCharTypeUnsigned</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.ChangeDefaultBitFieldUnsigned</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.processormode</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.preprocessor.DoNotSearchSystemDirectories</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.preprocessor.PreprocessOnly</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.symbols.Default</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.directories.DefaultIncludePath</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.OtherFlags</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.PrepareDataForGarbageCollection</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.EnableFastMath</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.GeneratePositionIndependentCode</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.EnableLongCalls</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.OtherDebuggingFlags</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.GenerateGprofInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.GenerateProfInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.AllWarnings</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.ExtraWarnings</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.Undefined</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.CheckSyntaxOnly</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.Pedantic</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.PedanticWarningsAsErrors</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.InhibitAllWarnings</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.Device</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.CompileOnly</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.SupportAnsiPrograms</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.MakeFileDependent</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+			</Compiler_dictionary>
+			<Linker_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>Libraries</d4p1:Key>
+					<d4p1:Value>libm</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>LibrarySearchPath</d4p1:Key>
+					<d4p1:Value>$(ProjectDir)\Device_Startup</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>MiscellaneousSettings</d4p1:Key>
+					<d4p1:Value>-Tsamd51j18a_flash.ld</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.DoNotUseStandardStartFiles</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.DoNotUseDefaultLibraries</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.NoStartupOrDefaultLibs</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.OmitAllSymbolInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.NoSharedLibraries</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.GenerateMAPFile</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.UseNewlibNano</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.AdditionalSpecs</d4p1:Key>
+					<d4p1:Value>None</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.GarbageCollectUnusedSections</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.EnableFastMath</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.GeneratePositionIndependentCode</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.Flash</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.Sram</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.ExternalRAM</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.miscellaneous.OtherOptions</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.miscellaneous.OtherObjects</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+			</Linker_dictionary>
+			<Name>Debug</Name>
+		</Configuration>
+	</Configurations>
+</Configurations>
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/samd51j18a_flash.ld b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/samd51j18a_flash.ld
new file mode 100644
index 0000000..ddc516e
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/samd51j18a_flash.ld
@@ -0,0 +1,163 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD51J18A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
+  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    .bkupram (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sbkupram = .;
+        *(.bkupram .bkupram.*);
+        . = ALIGN(8);
+        _ebkupram = .;
+    } > bkupram
+
+    .qspi (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sqspi = .;
+        *(.qspi .qspi.*);
+        . = ALIGN(8);
+        _eqspi = .;
+    } > qspi
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/samd51j18a_sram.ld b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/samd51j18a_sram.ld
new file mode 100644
index 0000000..dd16147
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/samd51j18a_sram.ld
@@ -0,0 +1,162 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD51J18A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
+  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    .bkupram (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sbkupram = .;
+        *(.bkupram .bkupram.*);
+        . = ALIGN(8);
+        _ebkupram = .;
+    } > bkupram
+
+    .qspi (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sqspi = .;
+        *(.qspi .qspi.*);
+        . = ALIGN(8);
+        _eqspi = .;
+    } > qspi
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/startup_samd51.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/startup_samd51.c
new file mode 100644
index 0000000..30b0b19
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/startup_samd51.c
@@ -0,0 +1,546 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAMD51
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd51.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&_estack),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+        uint32_t *pSrc, *pDest;
+
+        /* Initialize the relocate segment */
+        pSrc = &_etext;
+        pDest = &_srelocate;
+
+        if (pSrc != pDest) {
+                for (; pDest < &_erelocate;) {
+                        *pDest++ = *pSrc++;
+                }
+        }
+
+        /* Clear the zero segment */
+        for (pDest = &_szero; pDest < &_ezero;) {
+                *pDest++ = 0;
+        }
+
+        /* Set the vector table base address */
+        pSrc = (uint32_t *) & _sfixed;
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+#if __FPU_USED
+        /* Enable FPU */
+        SCB->CPACR |=  (0xFu << 20);
+        __DSB();
+        __ISB();
+#endif
+
+        /* Initialize the C library */
+        __libc_init_array();
+
+        /* Branch to main function */
+        main();
+
+        /* Infinite loop */
+        while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/system_samd51.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/system_samd51.c
new file mode 100644
index 0000000..bdf4be2
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/system_samd51.c
@@ -0,0 +1,64 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd51.h"
+
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ *  the source for the main clock at chip startup.
+ */
+#define __SYSTEM_CLOCK    (48000000)
+
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Initialize the system
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void)
+{
+        // Keep the default device state after reset
+        SystemCoreClock = __SYSTEM_CLOCK;
+        return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+        // Not implemented
+        SystemCoreClock = __SYSTEM_CLOCK;
+        return;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_QSPI.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_QSPI.c
new file mode 100644
index 0000000..680b127
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_QSPI.c
@@ -0,0 +1,219 @@
+/*
+ * Ethercat_QSPI.c
+ *
+ * Created: 31/07/2021 17:52:21
+ *  Author: Nick-XMG
+ */ 
+
+#include "Ethercat_QSPI.h"
+#include <hpl_qspi_config.h>
+#include <hpl_sercom_config.h>
+
+#define SQI_READ				(0x0B<<16)
#define SQI_WRITE				(0x02<<16)
#define SQI_INC					(0x40<<8)
#define SQI_DEC					(0x80<<8)
+#define ECAT_PRAM_RD_DATA		0x0000
#define ECAT_PRAM_WR_DATA		0x0020
#define HW_CFG					0x0074
#define	BYTE_TEST				0x0064
#define ECAT_PRAM_RD_ADDR_LEN	0x0308
#define ECAT_PRAM_RD_CMD		0x030C
#define ECAT_PRAM_WR_ADDR_LEN	0x0310
#define ECAT_PRAM_WR_CMD		0x0314

#define LAN9252_RDY				(1<<27)

#define PDRAM_RD_ADDRESS		0x1100
#define PDRAM_RD_LENGTH			ECAT_SIZE_RD //do the math later to automatize. fixed to 64 for now.
#define PDRAM_WR_ADDRESS		0x1800
#define PDRAM_WR_LENGTH			ECAT_SIZE_WR
#define PDRAM_LENGTH_MAX		64
+#define PDRAM_LENGTH_SHORT		32
+#define FIFO_DEPTH				16
+#define PDRAM_REG_MAX			PDRAM_LENGTH_SHORT/4
+#define PRAM_X_ABORT			(1<<30)
+#define CSR_BUSY				0x80000000
+
+COMPILER_ALIGNED(16)
+DmacDescriptor dummy_rx_descriptor;
+DmacDescriptor dummy_tx_descriptor;
+
+volatile uint32_t QSPI_tx_buffer[buffer_size]={0};
+volatile uint32_t QSPI_rx_buffer[buffer_size]={0};
+
+volatile enum ecat_states ecat_state = wait;
+volatile enum ecat_states next_ecat_state = wait;
+
+volatile uint8_t wr_cnt = 0;
+volatile uint8_t rd_cnt = 0;
+
+static uint8_t sync_rx_buffer[2*2*buffer_size/3]={0};
+static uint8_t sync_tx_buffer[2*2*buffer_size/3]={0xED};
+
+
+static uint32_t QSPI_cmds[]={0,PRAM_X_ABORT,0,PRAM_X_ABORT,
+							 ((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS,						CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS,CSR_BUSY,
+							 ((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX,	CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX,CSR_BUSY,
+							 ((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX*2,	CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX*2,CSR_BUSY,
+							 };
+			
+static uint32_t zero[FIFO_DEPTH]={0};	
+				
+volatile uint32_t status = 0;	
+	
+	struct _qspi_command rd_cmd = {
+	.inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
+	 .inst_frame.bits.inst_en = 0,
+	 .inst_frame.bits.data_en = 1,
+	 .inst_frame.bits.addr_en = 1,
+	 .inst_frame.bits.dummy_cycles = 6,
+	 .inst_frame.bits.tfr_type = QSPI_READMEM_ACCESS,
+ };	
+ 
+ struct _qspi_command wr_cmd = {
+	 .inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
+	 .inst_frame.bits.inst_en = 0,
+	 .inst_frame.bits.data_en = 1,
+	 .inst_frame.bits.addr_en = 1,
+	 .inst_frame.bits.dummy_cycles = 0,
+	 .inst_frame.bits.tfr_type = QSPI_WRITEMEM_ACCESS,
+ };	
+ 
+ struct _qspi_command qspi_cmd = {
+	 .inst_frame.bits.width = QSPI_INST1_ADDR1_DATA1,
+	 .inst_frame.bits.inst_en = 1,
+	 .inst_frame.bits.data_en = 0,
+	 .inst_frame.bits.addr_en = 0,
+	 .inst_frame.bits.dummy_cycles = 0,
+	 .instruction = 0x38,
+	 .inst_frame.bits.tfr_type = QSPI_WRITE_ACCESS,
+ };
+ 
+struct _qspi_command *spi_cmd= &wr_cmd;
+volatile uint8_t tx_complete =3;
+volatile uint32_t *ECAT_BYTE_TEST=			QSPI_AHB+BYTE_TEST+SQI_READ;
+volatile uint32_t *ECAT_FIFO_RD_RD=			QSPI_AHB+SQI_READ +ECAT_PRAM_RD_DATA;
+//volatile uint32_t *ECAT_FIFO_RD_RD=			QSPI_AHB+SQI_READ +SQI_INC+ECAT_PRAM_RD_DATA;
+
+volatile uint32_t *ECAT_FIFO_WR_WR=			QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_DATA;
+//volatile uint32_t *ECAT_FIFO_WR_WR=			QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_DATA;
+
+volatile uint32_t *ECAT_HW_CFG_RD=			QSPI_AHB+SQI_READ+HW_CFG;
+volatile uint32_t *ECAT_FIFO_RD_ADLEN_WR=   QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_RD_ADDR_LEN;
+volatile uint32_t *ECAT_FIFO_WR_ADLEN_WR=   QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
+volatile uint32_t *ECAT_FIFO_WR_ADLEN_RD=   QSPI_AHB+SQI_READ+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
+volatile uint32_t *ECAT_FIFO_WR_CMD_RD=		QSPI_AHB+SQI_READ+ECAT_PRAM_WR_CMD;
+volatile uint32_t *ECAT_FIFO_WR_CMD_WR=		QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_CMD;
+ 
+volatile uint32_t *INPUT_ADDRESS ;
+volatile uint32_t *OUTPUT_ADDRESS;
+volatile uint32_t read_buffer =0;
+volatile uint8_t ecat_length= 0;
+
+volatile bool run_ECAT = false;
+volatile bool synced = false;
+
+void ECAT_STATE_MACHINE(void){
+	if ((ecat_state != wait)&(ecat_state != wait2)){
+		run_ECAT = false;
+		switch(ecat_state){
+		case en_SQI:
+			spi_cmd = &qspi_cmd;
+			QSPI->INSTRCTRL.bit.INSTR=spi_cmd->instruction;
+			OUTPUT_ADDRESS = ECAT_FIFO_RD_ADLEN_WR;
+			INPUT_ADDRESS = &QSPI_cmds[0];
+			ecat_length = 0;
+			next_ecat_state = rd_rdy;
+			
+			break;
+		case rd_rdy:
+			if (QSPI_rx_buffer[0]==LAN9252_RDY){
+				next_ecat_state = abort_fifo;
+			}
+			else if (QSPI_rx_buffer[0]== 0xFFFFFFFF){
+				next_ecat_state = en_SQI;
+				QSPI_rx_buffer[0] = 0;
+			}
+			else{
+			spi_cmd = &rd_cmd;
+			OUTPUT_ADDRESS = &QSPI_rx_buffer[0];
+			INPUT_ADDRESS = ECAT_HW_CFG_RD;
+			ecat_length = 1;
+			wr_cnt=0;
+			}
+		
+		break;
+		case abort_fifo:	
+			spi_cmd = &wr_cmd;
+			OUTPUT_ADDRESS = ECAT_FIFO_WR_CMD_WR;
+			INPUT_ADDRESS = &QSPI_cmds[1];
+			ecat_length = 1;
+			next_ecat_state = dlt_rdram;
+			wr_cnt=0;
+			rd_cnt=0;
+		break;
+		case dlt_rdram:
+			spi_cmd = &wr_cmd;
+			OUTPUT_ADDRESS = ECAT_FIFO_WR_WR;
+			INPUT_ADDRESS = &zero[0];
+			//if (wr_cnt >= 1) ecat_length = FIFO_DEPTH/2;
+			//else ecat_length = FIFO_DEPTH;
+			ecat_length = FIFO_DEPTH;
+			next_ecat_state = cf_dlt_rdram;
+		break;
+		case cf_dlt_rdram:
+			spi_cmd = &wr_cmd;
+			OUTPUT_ADDRESS = ECAT_FIFO_WR_ADLEN_WR;
+			INPUT_ADDRESS = &QSPI_cmds[4*(wr_cnt+1)];
+			ecat_length = 2;
+			if (wr_cnt >= 2) {
+				next_ecat_state = wait;
+				wr_cnt =0;
+			} else {
+				next_ecat_state = dlt_rdram;
+				wr_cnt++;
+			}
+			
+		break;
+		case write_fifo:
+			spi_cmd = &wr_cmd;
+			OUTPUT_ADDRESS = ECAT_FIFO_WR_WR;
+			INPUT_ADDRESS = &QSPI_tx_buffer[wr_cnt*FIFO_DEPTH];
+			/*if (wr_cnt >= 1) ecat_length = FIFO_DEPTH/2;
+			else ecat_length = FIFO_DEPTH;*/
+			ecat_length = FIFO_DEPTH;
+			next_ecat_state = config_fifo;
+		break;
+		case config_fifo:	
+			spi_cmd = &wr_cmd;
+			OUTPUT_ADDRESS = ECAT_FIFO_RD_ADLEN_WR;
+			INPUT_ADDRESS = &QSPI_cmds[4*(wr_cnt+1)];
+			ecat_length = 4;
+			next_ecat_state = read_fifo;
+		break;
+		case read_fifo:	
+			spi_cmd = &rd_cmd;
+			OUTPUT_ADDRESS = &QSPI_rx_buffer[wr_cnt*FIFO_DEPTH];
+			INPUT_ADDRESS = ECAT_FIFO_RD_RD;
+			ecat_length = FIFO_DEPTH;
+			if (wr_cnt >= 2) {
+//				ecat_length = FIFO_DEPTH/2;
+				next_ecat_state = wait2;
+				wr_cnt=0;
+				}
+			else {
+//				ecat_length = FIFO_DEPTH;
+				next_ecat_state = write_fifo;
+				wr_cnt++;
+			}	
+		break;
+		}
+		qspi_dma_enable(&ECAT_QSPI);
+		QSPI->INSTRFRAME.reg = ((*spi_cmd).inst_frame.word);
+		for (uint8_t i=0;i<ecat_length;i++)
+		{
+		*(OUTPUT_ADDRESS+i) = *(INPUT_ADDRESS+i);
+		}
+		QSPI->CTRLA.bit.LASTXFER = 1;	
+		ecat_state = next_ecat_state; 
+	}
+}
+
+void config_qspi()
+{
+	QSPI->INTENSET.bit.CSRISE = 1;
+	NVIC_EnableIRQ(QSPI_IRQn);
+	NVIC_SetPriority(QSPI_IRQn, 3);
+	ecat_state =en_SQI;
+}
+
+QSPI_Handler(){
+	if (QSPI->INTFLAG.bit.CSRISE == 1){
+		QSPI->INTFLAG.bit.CSRISE = 1;
+		run_ECAT =true;
+	}
+}
+
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_QSPI.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_QSPI.h
new file mode 100644
index 0000000..d64c935
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_QSPI.h
@@ -0,0 +1,38 @@
+/*
+ * EtherCAT_QSPI.h
+ *
+ * Created: 31/07/2021 17:51:24
+ *  Author: Nick-XMG
+ */ 
+#ifndef ETHERCAT_QSPI_H_
+#define ETHERCAT_QSPI_H_
+
+#include "atmel_start.h"
+
+
+#define ECAT_SIZE_WR			64 //max fifo size
+#define ECAT_SIZE_RD			ECAT_SIZE_WR
+#define ECAT_SIZE_WR_REG		ECAT_SIZE_WR/4
+#define ECAT_SIZE_RD_REG		ECAT_SIZE_WR/4
+
+#define buffer_size			3*ECAT_SIZE_WR_REG  //changed to double
+#define motor_buffer_size	buffer_size/3
+
+
+extern enum ecat_states {abort_fifo,dlt_rdram,cf_dlt_rdram,write_fifo,config_fifo,read_fifo,wait,wait2,en_SQI,temp,rd_rdy};
+extern volatile enum ecat_states ecat_state;
+extern volatile enum ecat_states next_ecat_state;
+
+volatile uint32_t QSPI_tx_buffer[buffer_size];
+volatile uint32_t QSPI_rx_buffer[buffer_size];
+
+//static uint32_t QSPI_tx_buffer[buffer_size] =  {47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,
+												 //31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,
+												 //15,14,13,12,11,10, 9,8,7,6,5,4,3,2,1,0};
+//static uint32_t QSPI_rx_buffer[buffer_size] =	{0};
+extern volatile bool run_ECAT;
+void config_qspi(void);
+
+
+
+#endif /* ETHERCAT_QSPI_H_ */
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_SlaveDef.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_SlaveDef.h
new file mode 100644
index 0000000..dfc6c65
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_SlaveDef.h
@@ -0,0 +1,352 @@
+/*
+ * EtherCAT_SlaveDef.h
+ *
+ * Created: 01/08/2021 12:56:16
+ *  Author: Nick-XMG
+ */ 
+
+
+#ifndef ETHERCAT_SLAVEDEF_H_
+#define ETHERCAT_SLAVEDEF_H_
+
+#include "Ethercat_QSPI.h"
+#include "arm_math.h"
+#include "ADS1299.h"
+
+extern volatile uint8_t _ads1299_reg_data[24];
+extern volatile int32_t _ads1299_channel_data[9];
+extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
+
+
+//Write To Ecat Total Bytes (XX bytes)
+/* Motor 1*/
+static volatile uint8_t  *M1_Status				    =	(uint8_t *)&QSPI_tx_buffer[0];
+static volatile uint8_t	 *M1_Mode					= (((uint8_t *)&QSPI_tx_buffer[0])+1);
+static volatile int16_t  *M1_Joint_rel_position		= (((int16_t *)&QSPI_tx_buffer[0])+1);
+static volatile int16_t  *M1_Joint_abs_position		=  ((int16_t *)&QSPI_tx_buffer[1]);
+static volatile int16_t  *M1_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[1])+1);
+static volatile int16_t  *M1_Motor_current_bus		=  ((int16_t *)&QSPI_tx_buffer[2]);
+static volatile int16_t  *M1_Motor_currentPhA		= (((int16_t *)&QSPI_tx_buffer[2])+1);
+static volatile int16_t  *M1_Motor_currentPhB		=  ((int16_t *)&QSPI_tx_buffer[3]);
+static volatile int16_t  *M1_Motor_currentPhC		= (((int16_t *)&QSPI_tx_buffer[3])+1);
+static volatile int16_t  *M1_Motor__hallState		=  ((int16_t *)&QSPI_tx_buffer[4]);
+static volatile int16_t  *M1_Motor_dutyCycle		= (((int16_t *)&QSPI_tx_buffer[4])+1);
+/* Motor 2*/
+static volatile uint8_t  *M2_Status				    =	(uint8_t *)&QSPI_tx_buffer[5];
+static volatile uint8_t	 *M2_Mode					= (((uint8_t *)&QSPI_tx_buffer[5])+1);
+static volatile int16_t  *M2_Joint_rel_position		= (((int16_t *)&QSPI_tx_buffer[5])+1);
+static volatile int16_t  *M2_Joint_abs_position		=  ((int16_t *)&QSPI_tx_buffer[6]);
+static volatile int16_t  *M2_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[6])+1);
+static volatile int16_t  *M2_Motor_current_bus		=  ((int16_t *)&QSPI_tx_buffer[7]);
+static volatile int16_t  *M2_Motor_currentPhA		= (((int16_t *)&QSPI_tx_buffer[7])+1);
+static volatile int16_t  *M2_Motor_currentPhB		=  ((int16_t *)&QSPI_tx_buffer[8]);
+static volatile int16_t  *M2_Motor_currentPhC		= (((int16_t *)&QSPI_tx_buffer[8])+1);
+static volatile int16_t  *M2_Motor__hallState		=  ((int16_t *)&QSPI_tx_buffer[9]);
+static volatile int16_t  *M2_Motor_dutyCycle		= (((int16_t *)&QSPI_tx_buffer[9])+1);
+/* EMG */
+static volatile int32_t  *EMG_CH1					= (((int32_t *)&QSPI_tx_buffer[10]));
+static volatile int32_t  *EMG_CH2					= (((int32_t *)&QSPI_tx_buffer[11]));
+static volatile int32_t  *EMG_CH3					= (((int32_t *)&QSPI_tx_buffer[12]));
+static volatile int32_t  *EMG_CH4					= (((int32_t *)&QSPI_tx_buffer[13]));
+
+/* Reserved space */
+static volatile int16_t  *Spare1_tx					= (((int16_t *)&QSPI_tx_buffer[14]));
+static volatile int16_t  *Spare2_tx					= (((int16_t *)&QSPI_tx_buffer[14])+1);
+static volatile int16_t  *Spare3_tx					= (((int16_t *)&QSPI_tx_buffer[15]));
+static volatile int16_t  *Spare4_tx					= (((int16_t *)&QSPI_tx_buffer[15])+1);
+
+/* Motor 3*/
+static volatile uint8_t  *M3_Status				    =	(uint8_t *)&QSPI_tx_buffer[16];
+static volatile uint8_t	 *M3_Mode					= (((uint8_t *)&QSPI_tx_buffer[16])+1);
+static volatile int16_t  *M3_Joint_rel_position		= (((int16_t *)&QSPI_tx_buffer[16])+1);
+static volatile int16_t  *M3_Joint_abs_position		=  ((int16_t *)&QSPI_tx_buffer[17]);
+static volatile int16_t  *M3_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[17])+1);
+static volatile int16_t  *M3_Motor_current_bus		=  ((int16_t *)&QSPI_tx_buffer[18]);
+static volatile int16_t  *M3_Motor_currentPhA		= (((int16_t *)&QSPI_tx_buffer[18])+1);
+static volatile int16_t  *M3_Motor_currentPhB		=  ((int16_t *)&QSPI_tx_buffer[19]);
+static volatile int16_t  *M3_Motor_currentPhC		= (((int16_t *)&QSPI_tx_buffer[19])+1);
+static volatile int16_t  *M3_Motor__hallState		=  ((int16_t *)&QSPI_tx_buffer[20]);
+static volatile int16_t  *M3_Motor_dutyCycle		= (((int16_t *)&QSPI_tx_buffer[20])+1);
+/* Motor 4*/
+static volatile uint8_t  *M4_Status				    =	(uint8_t *)&QSPI_tx_buffer[21];
+static volatile uint8_t	 *M4_Mode					= (((uint8_t *)&QSPI_tx_buffer[21])+1);
+static volatile int16_t  *M4_Joint_rel_position		= (((int16_t *)&QSPI_tx_buffer[21])+1);
+static volatile int16_t  *M4_Joint_abs_position		=  ((int16_t *)&QSPI_tx_buffer[22]);
+static volatile int16_t  *M4_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[22])+1);
+static volatile int16_t  *M4_Motor_current_bus		=  ((int16_t *)&QSPI_tx_buffer[23]);
+static volatile int16_t  *M4_Motor_currentPhA		= (((int16_t *)&QSPI_tx_buffer[23])+1);
+static volatile int16_t  *M4_Motor_currentPhB		=  ((int16_t *)&QSPI_tx_buffer[24]);
+static volatile int16_t  *M4_Motor_currentPhC		= (((int16_t *)&QSPI_tx_buffer[24])+1);
+static volatile int16_t  *M4_Motor__hallState		=  ((int16_t *)&QSPI_tx_buffer[25]);
+static volatile int16_t  *M4_Motor_dutyCycle		= (((int16_t *)&QSPI_tx_buffer[25])+1);
+/* IMU */
+static volatile int16_t  *q_x0						= (((int16_t *)&QSPI_tx_buffer[26]));
+static volatile int16_t  *q_y0						= (((int16_t *)&QSPI_tx_buffer[26])+1);
+static volatile int16_t  *q_z0						= (((int16_t *)&QSPI_tx_buffer[27]));
+static volatile int16_t  *q_w0						= (((int16_t *)&QSPI_tx_buffer[27])+1);
+/* EMG */
+static volatile int16_t  *FSR_CH1					= (((int16_t *)&QSPI_tx_buffer[28]));
+static volatile int16_t  *FSR_CH2					= (((int16_t *)&QSPI_tx_buffer[28])+1);
+static volatile int16_t  *FSR_CH3					= (((int16_t *)&QSPI_tx_buffer[29]));
+static volatile int16_t  *FSR_CH4					= (((int16_t *)&QSPI_tx_buffer[29])+1);
+static volatile int16_t  *FSR_CH5					= (((int16_t *)&QSPI_tx_buffer[30]));
+static volatile int16_t  *Pressure_CH1				= (((int16_t *)&QSPI_tx_buffer[30])+1);
+static volatile int16_t  *Pressure_CH2				= (((int16_t *)&QSPI_tx_buffer[31]));
+static volatile int16_t  *Pressure_CH3				= (((int16_t *)&QSPI_tx_buffer[31])+1);
+
+//Read From Ecat Total (XX Bytes)
+//QSPI_rx_buffer
+/* Motor 1*/
+static volatile uint8_t  *M1_Control_mode			= ((uint8_t *)&QSPI_rx_buffer[0]);
+static volatile uint8_t	 *M1_Control_set			= (((uint8_t *)&QSPI_rx_buffer[0])+1);
+static volatile int16_t  *M1_Desired_pos			= ((int16_t *)&QSPI_rx_buffer[0]+1);
+static volatile int16_t  *M1_Desired_speed			= ((int16_t *)&QSPI_rx_buffer[1]);
+static volatile int16_t  *M1_Desired_current		= ((int16_t *)&QSPI_rx_buffer[1]+1);
+static volatile int16_t  *M1_Max_pos				= ((int16_t *)&QSPI_rx_buffer[2]);
+static volatile int16_t  *M1_Max_velocity			= ((int16_t *)&QSPI_rx_buffer[2]+1);
+static volatile int16_t  *M1_Max_current			= ((int16_t *)&QSPI_rx_buffer[3]);
+static volatile int16_t  *M1_Desired_dc				= ((int16_t *)&QSPI_rx_buffer[3]+1); //Spare
+///* Motor 2*/
+static volatile uint8_t  *M2_Control_mode			= ((uint8_t *)&QSPI_rx_buffer[4]);
+static volatile uint8_t	 *M2_Control_set			= (((uint8_t *)&QSPI_rx_buffer[4])+1);
+static volatile int16_t  *M2_Desired_pos			= ((int16_t *)&QSPI_rx_buffer[4]+1);
+static volatile int16_t  *M2_Desired_speed			= ((int16_t *)&QSPI_rx_buffer[5]);
+static volatile int16_t  *M2_Desired_current		= ((int16_t *)&QSPI_rx_buffer[5]+1);
+static volatile int16_t  *M2_Max_pos				= ((int16_t *)&QSPI_rx_buffer[6]);
+static volatile int16_t  *M2_Max_velocity			= ((int16_t *)&QSPI_rx_buffer[6]+1);
+static volatile int16_t  *M2_Max_current			= ((int16_t *)&QSPI_rx_buffer[7]);
+static volatile int16_t  *M2_Desired_dc				= ((int16_t *)&QSPI_rx_buffer[7]+1); //Spare
+
+/* Reserved space */
+/* 64 bytes reserved for each */
+static volatile int16_t  *Spare1_rx					= ((int16_t *)&QSPI_rx_buffer[8]);		//Spare
+static volatile int16_t  *Spare2_rx					= ((int16_t *)&QSPI_rx_buffer[8]+1);	//Spare
+static volatile int16_t  *Spare3_rx					= ((int16_t *)&QSPI_rx_buffer[9]);		//Spare
+static volatile int16_t  *Spare4_rx					= ((int16_t *)&QSPI_rx_buffer[9]+1);	//Spare
+static volatile int16_t  *Spare5_rx					= ((int16_t *)&QSPI_rx_buffer[10]);		//Spare
+static volatile int16_t  *Spare6_rx					= ((int16_t *)&QSPI_rx_buffer[10]+1);	//Spare
+static volatile int16_t  *Spare7_rx					= ((int16_t *)&QSPI_rx_buffer[11]);		//Spare
+static volatile int16_t  *Spare8_rx					= ((int16_t *)&QSPI_rx_buffer[11]+1);	//Spare
+static volatile int16_t  *Spare9_rx					= ((int16_t *)&QSPI_rx_buffer[12]);		//Spare
+static volatile int16_t  *Spare10_rx				= ((int16_t *)&QSPI_rx_buffer[12]+1);	//Spare
+static volatile int16_t  *Spare11_rx				= ((int16_t *)&QSPI_rx_buffer[13]);		//Spare
+static volatile int16_t  *Spare12_rx				= ((int16_t *)&QSPI_rx_buffer[13]+1);	//Spare
+static volatile int16_t  *Spare13_rx				= ((int16_t *)&QSPI_rx_buffer[14]);		//Spare
+static volatile int16_t  *Spare14_rx				= ((int16_t *)&QSPI_rx_buffer[14]+1);	//Spare
+static volatile int16_t  *Spare15_rx				= ((int16_t *)&QSPI_rx_buffer[15]);		//Spare
+static volatile int16_t  *Spare16_rx				= ((int16_t *)&QSPI_rx_buffer[15]+1);	//Spare
+
+///* Motor 3*/
+static volatile uint8_t  *M3_Control_mode			= ((uint8_t *)&QSPI_rx_buffer[16]);
+static volatile uint8_t	 *M3_Control_set			= (((uint8_t *)&QSPI_rx_buffer[16])+1);
+static volatile int16_t  *M3_Desired_pos			= ((int16_t *)&QSPI_rx_buffer[16]+1);
+static volatile int16_t  *M3_Desired_speed			= ((int16_t *)&QSPI_rx_buffer[17]);
+static volatile int16_t  *M3_Desired_current		= ((int16_t *)&QSPI_rx_buffer[17]+1);
+static volatile int16_t  *M3_Max_pos				= ((int16_t *)&QSPI_rx_buffer[18]);
+static volatile int16_t  *M3_Max_velocity			= ((int16_t *)&QSPI_rx_buffer[18]+1);
+static volatile int16_t  *M3_Max_current			= ((int16_t *)&QSPI_rx_buffer[19]);
+static volatile int16_t  *M3_Spare					= ((int16_t *)&QSPI_rx_buffer[19]+1); //Spare
+///* Motor 4*/
+static volatile uint8_t  *M4_Control_mode			= ((uint8_t *)&QSPI_rx_buffer[20]);
+static volatile uint8_t	 *M4_Control_set			= (((uint8_t *)&QSPI_rx_buffer[20])+1);
+static volatile int16_t  *M4_Desired_pos			= ((int16_t *)&QSPI_rx_buffer[20]+1);
+static volatile int16_t  *M4_Desired_speed			= ((int16_t *)&QSPI_rx_buffer[21]);
+static volatile int16_t  *M4_Desired_current		= ((int16_t *)&QSPI_rx_buffer[21]+1);
+static volatile int16_t  *M4_Max_pos				= ((int16_t *)&QSPI_rx_buffer[22]);
+static volatile int16_t  *M4_Max_velocity			= ((int16_t *)&QSPI_rx_buffer[22]+1);
+static volatile int16_t  *M4_Max_current			= ((int16_t *)&QSPI_rx_buffer[23]);
+static volatile int16_t  *M4_Spare					= ((int16_t *)&QSPI_rx_buffer[23]+1); //Spare
+
+static void update_telemetry(void)
+{
+	inline int16_t convert_to_mA(volatile float32_t current_PU)
+	{
+		return (int16_t)(current_PU*1000.0f);
+	}
+	//
+	//*M1_Status				    = 0;
+	//*M1_Mode					= 0;
+	
+	/* Motor 1 */
+	*M1_Status					= Motor1.motor_state.fault;
+	*M1_Mode					= Motor1.motor_state.currentstate;
+	*M1_Joint_rel_position		= Motor1.motor_status.Num_Steps;
+	*M1_Joint_abs_position		= Motor1.motor_setpoints.desired_position + 1 ;
+	//*M1_Joint_abs_position		= Motor1.motor_status.abs_position;
+	//*M1_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[1])+1);
+	*M1_Motor_current_bus		= convert_to_mA(Motor1.Iphase_pu.Bus);
+	*M1_Motor_currentPhA		= convert_to_mA(Motor1.Iphase_pu.A);
+	*M1_Motor_currentPhB		= convert_to_mA(Motor1.Iphase_pu.B);
+	*M1_Motor_currentPhC		= convert_to_mA(Motor1.Iphase_pu.C);
+	*M1_Motor__hallState		= Motor1.motor_status.currentHallPattern;
+	*M1_Motor_dutyCycle			= Motor1.motor_status.duty_cycle;
+	*M1_Motor_speed				= (int16_t)Motor1.motor_status.calc_rpm;
+	//*M1_Joint_abs_position		= Motor1.motor_status.actualDirection;
+	/* Motor 2 */
+	*M2_Status					= Motor2.motor_state.fault;
+	*M2_Mode					= Motor2.motor_state.currentstate;
+	*M2_Joint_rel_position		= Motor2.motor_status.Num_Steps;
+	//*M2_Joint_abs_position		= Motor2.motor_status.abs_position;
+	*M2_Joint_abs_position		= Motor2.motor_setpoints.desired_position + 1 ;
+	//*M1_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[1])+1);
+	*M2_Motor_current_bus		= convert_to_mA( Motor2.Iphase_pu.Bus);
+	*M2_Motor_currentPhA		= convert_to_mA( Motor2.Iphase_pu.A); 
+	*M2_Motor_currentPhB		= convert_to_mA( Motor2.Iphase_pu.B); 
+	*M2_Motor_currentPhC		= convert_to_mA(Motor2.Iphase_pu.C);
+	*M2_Motor__hallState		= Motor2.motor_status.currentHallPattern;
+	*M2_Motor_dutyCycle			= Motor2.motor_status.duty_cycle;
+	*M2_Motor_speed				= (int16_t)Motor2.motor_status.calc_rpm;
+	//*M2_Joint_abs_position		= Motor2.motor_status.actualDirection;
+	
+	*EMG_CH1					= _ads1299_channel_data[0];
+	*EMG_CH2					= _ads1299_channel_data[1];
+	*EMG_CH3					= _ads1299_channel_data[2];
+	*EMG_CH4					= _ads1299_channel_data[3];
+	//*EMG_CH1					= 1;
+	//*EMG_CH2					= 2;
+	//*EMG_CH3					= 3;
+	//*EMG_CH4					= 4;
+}
+
+static void update_setpoints(void)
+{
+	Motor1.motor_setpoints.desired_position	= *M1_Desired_pos;
+	Motor1.motor_setpoints.desired_speed	= *M1_Desired_speed;
+	Motor1.motor_setpoints.desired_torque	= *M1_Desired_current;
+	Motor1.motor_setpoints.max_current		= *M1_Max_current;
+	Motor1.motor_setpoints.max_torque		= *M1_Max_current;
+	Motor1.motor_setpoints.max_velocity		= *M1_Max_velocity;
+	
+	Motor2.motor_setpoints.desired_position	= *M2_Desired_pos;
+	Motor2.motor_setpoints.desired_speed	= *M2_Desired_speed;
+	Motor2.motor_setpoints.desired_torque	= *M2_Desired_current;
+	Motor2.motor_setpoints.max_current		= *M2_Max_current;
+	Motor2.motor_setpoints.max_torque		= *M2_Max_current;
+	Motor2.motor_setpoints.max_velocity		= *M2_Max_velocity;
+	
+	//*M3_Desired_pos			= 1;
+	//*M3_Desired_speed		= 2;
+	//*M3_Desired_current		= 3;
+	//*M3_Max_current			= 4;
+	//*M3_Max_current			= 5;
+	//*M3_Max_velocity		= 6;
+	//
+	//*M4_Desired_pos			= 7;
+	//*M4_Desired_speed		= 8;
+	//*M4_Desired_current		= 9;
+	//*M4_Max_current         = 10;
+	//*M4_Max_current			= 11;
+	//*M4_Max_velocity		= 12;
+	
+	
+	//volatile uint8_t a = *M1_Control_mode;
+	//volatile uint8_t b = *M1_Control_set;
+	//volatile int16_t c = *M1_Desired_pos;
+	//volatile int16_t d = *M1_Desired_speed;
+	//volatile int16_t e = *M1_Desired_current;
+	//volatile int16_t f = *M1_Max_pos;
+	//volatile int16_t g = *M1_Max_velocity;
+	//volatile int16_t h = *M1_Max_current;
+	//volatile int16_t i = *M1_Spare;
+	//inline float32_t convert_int_to_PU(volatile int16_t input)
+	//{
+		//return ((float32_t)(input/1000.0f));
+	//}
+	////Motor1.des_mode						= 0;
+	////Motor1.set							= 0;
+	//Motor1.motor_setpoints.desired_position	= *desired_position;
+	//Motor1.motor_setpoints.desired_speed	= *desired_speed;
+	////Motor1.desired_speed					= 1500;
+	//Motor1.motor_setpoints.desired_torque	= convert_int_to_PU(*desired_torque);
+	////Motor1.controllerParam.I_kp			= 0;
+	////Motor1.controllerParam.I_ki			= 0;
+	////Motor1.controllerParam.V_kp			= 0;
+	////Motor1.controllerParam.V_kd			= 0;
+	////Motor1.controllerParam.V_kd			= 0;
+	////Motor1.controllerParam.P_kp			= 0;
+	////Motor1.controllerParam.P_ki			= 0;
+	////Motor1.reductionRatio					= 0;
+	//Motor1.motor_setpoints.max_velocity		= *max_velocity;
+	//Motor1.motor_setpoints.max_current		= convert_int_to_PU(*max_current);
+	//Motor1.motor_setpoints.max_torque		= convert_int_to_PU(*max_torque);	 
+	////Motor1.Spare1							= 0;
+	////Motor1.Spare2							= 0;
+	////Motor1.Spare3							= 0;
+	////Motor1.Spare4							= 0;	 
+}
+
+
+static inline void comms_check(void)
+{
+	/* Motor 1*/
+	*M1_Status				    = 1;
+	*M1_Mode					= 2;
+	*M1_Joint_rel_position		= -3;
+	//*M1_Joint_abs_position		= 4;
+	*M1_Motor_speed				= -5;
+	*M1_Motor_current_bus		= 6;
+	*M1_Motor_currentPhA		= -7;
+	*M1_Motor_currentPhB		= 8;
+	*M1_Motor_currentPhC		= -9;
+	*M1_Motor__hallState		= 10;
+	*M1_Motor_dutyCycle			= -11;
+	/* Motor 2*/
+	*M2_Status				    = 12;
+	*M2_Mode					= 13;
+	*M2_Joint_rel_position		= 14;
+	//*M2_Joint_abs_position		= -15;
+	*M2_Motor_speed				= 16;
+	*M2_Motor_current_bus		= -17;
+	*M2_Motor_currentPhA		= 18;
+	*M2_Motor_currentPhB		= -19;
+	*M2_Motor_currentPhC		= 20;
+	*M2_Motor__hallState		= -21;
+	*M3_Motor_dutyCycle			= 22;
+	/* EMG */
+	*EMG_CH1					= -23;
+	*EMG_CH2					= 24;
+	*EMG_CH3					= -25;
+	*EMG_CH4					= 26;
+	
+	
+	/* Motor 3*/
+	*M3_Status				    = 1;
+	*M3_Mode					= 2;
+	*M3_Joint_rel_position		= -3;
+	*M3_Joint_abs_position		= 4;
+	*M3_Motor_speed				= -5;
+	*M3_Motor_current_bus		= 6;
+	*M3_Motor_currentPhA		= -7;
+	*M3_Motor_currentPhB		= 8;
+	*M3_Motor_currentPhC		= -9;
+	*M3_Motor__hallState		= 10;
+	*M3_Motor_dutyCycle			= -11;
+	/* Motor 4*/
+	*M4_Status				    = 12;
+	*M4_Mode					= 13;
+	*M4_Joint_rel_position		= 14;
+	*M4_Joint_abs_position		= -15;
+	*M4_Motor_speed				= 16;
+	*M4_Motor_current_bus		= -17;
+	*M4_Motor_currentPhA		= 18;
+	*M4_Motor_currentPhB		= -19;
+	*M4_Motor_currentPhC		= 20;
+	*M4_Motor__hallState		= -21;
+	*M4_Motor_dutyCycle			= 22;
+	/* IMU */
+	*q_x0						= 23;
+	*q_y0						= -24;
+	*q_z0						= 25;
+	*q_w0						= -26;
+	/* EMG */
+	*FSR_CH1					= 27;
+	*FSR_CH2					= -28;
+	*FSR_CH3					= 29;
+	*FSR_CH4					= -30;
+	*FSR_CH5					= 31;
+	*Pressure_CH1				= -32;
+	*Pressure_CH2				= 33;
+	*Pressure_CH3				= -34;	
+}
+
+#endif /* ETHERCAT_SLAVEDEF_H_ */
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.componentinfo.xml b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.componentinfo.xml
new file mode 100644
index 0000000..0526dbb
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.componentinfo.xml
@@ -0,0 +1,169 @@
+<?xml version="1.0" encoding="utf-8"?>
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diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.cproj b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.cproj
new file mode 100644
index 0000000..e089fa0
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.cproj
@@ -0,0 +1,1133 @@
+<?xml version="1.0" encoding="utf-8"?>
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+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
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+    <Name>Two_Motor_D51</Name>
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+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_cmcc_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_dac_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_dmac_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_dsu_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_eic_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_evsys_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_freqm_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_gclk_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_hmatrixb_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_i2s_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_icm_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_mclk_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_nvmctrl_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_osc32kctrl_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_oscctrl_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_pac_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_pcc_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_pdec_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_pm_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_port_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_qspi_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_ramecc_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_rstc_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_rtc_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_sdhc_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_sercom_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_supc_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_tcc_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_tc_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_trng_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_usb_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_wdt_d51.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="interrupts.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="main.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="motorparameters.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="statemachine.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="utilities.h">
+      <SubType>compile</SubType>
+    </Compile>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Config\" />
+    <Folder Include="Device_Startup\" />
+    <Folder Include="examples\" />
+    <Folder Include="hal\" />
+    <Folder Include="hal\documentation\" />
+    <Folder Include="hal\include\" />
+    <Folder Include="hal\src\" />
+    <Folder Include="hal\utils\" />
+    <Folder Include="hal\utils\include\" />
+    <Folder Include="hal\utils\src\" />
+    <Folder Include="hpl\" />
+    <Folder Include="hpl\adc\" />
+    <Folder Include="hpl\ccl\" />
+    <Folder Include="hpl\cmcc\" />
+    <Folder Include="hpl\core\" />
+    <Folder Include="hpl\dmac\" />
+    <Folder Include="hpl\doc_lite\" />
+    <Folder Include="hpl\eic\" />
+    <Folder Include="hpl\evsys\" />
+    <Folder Include="hpl\gclk\" />
+    <Folder Include="hpl\mclk\" />
+    <Folder Include="hpl\osc32kctrl\" />
+    <Folder Include="hpl\oscctrl\" />
+    <Folder Include="hpl\pm\" />
+    <Folder Include="hpl\port\" />
+    <Folder Include="hpl\qspi\" />
+    <Folder Include="hpl\ramecc\" />
+    <Folder Include="hpl\sercom\" />
+    <Folder Include="hpl\tcc\" />
+    <Folder Include="hpl\tc\" />
+    <Folder Include="hri\" />
+  </ItemGroup>
+  <ItemGroup>
+    <None Include="Device_Startup\samd51j18a_flash.ld">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="Device_Startup\samd51j18a_sram.ld">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\adc_sync.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\custom_logic.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\evsys.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\ext_irq.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\i2c_master_async.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\pwm.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\quad_spi_dma.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\spi_master_dma.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\spi_master_sync.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hpl\doc_lite\tc.rst">
+      <SubType>compile</SubType>
+    </None>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/angle_sensors.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/angle_sensors.c
new file mode 100644
index 0000000..61b2507
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/angle_sensors.c
@@ -0,0 +1,130 @@
+
+/*
+ * angle_sensors.c
+ *
+ * Created: 8/21/2021 11:34:44 AM
+ *  Author: ge37vez
+ */ 
+
+#include "angle_sensors.h"
+#define	AS5048A_MAX_VALUE					   (8191.0f)
+#include "arm_math.h"
+
+void angle_sensor_init()
+{
+	spi_m_sync_disable(ANGLESENSOR.SPI_descr);
+	// Set Mode 1 : CPOL = 0; CPHA = 1;
+	
+	#ifdef AS5048
+	/* Set Mode 1 */
+	hri_sercomspi_write_CTRLA_CPOL_bit((SercomSpi *)(ANGLESENSOR.SPI_descr->dev.prvt), false);
+	hri_sercomspi_write_CTRLA_CPHA_bit((SercomSpi *)(ANGLESENSOR.SPI_descr->dev.prvt), true);
+	#elif defined A1335
+	/* Set Mode 3 */
+	hri_sercomspi_write_CTRLA_CPOL_bit((SercomSpi *)(ANGLESENSOR.SPI_descr->dev.prvt), true);
+	hri_sercomspi_write_CTRLA_CPHA_bit((SercomSpi *)(ANGLESENSOR.SPI_descr->dev.prvt), true);	
+	#endif 
+	
+	spi_m_sync_enable(ANGLESENSOR.SPI_descr);
+	gpio_set_pin_level(ANGLESENSOR.SS_pin, true);
+}
+
+int16_t* ang_sense_read(ASCommand command)
+{
+	_read(command); // Send command to device(s)
+	return _read(command); // Read-out device(s)
+}
+
+int16_t* read_angle()
+{
+	_read(AS_CMD_ANGLE); // Send command to device(s)
+	return _read(AS_CMD_ANGLE); // Read-out device(s)
+}
+
+int16_t* _read(ASCommand command)
+{
+	
+	if(ANGLESENSOR.n_dev == 1)
+	{
+		// Give command to start reading the angle
+		gpio_set_pin_level(ANGLESENSOR.SS_pin, false);
+		uint16_t temp = _spi_transfer16(&ANGLESENSOR, command);
+		ANGLESENSOR._readBuffer[0] = (int16_t)(temp & AS_MASK);
+		gpio_set_pin_level(ANGLESENSOR.SS_pin, true);
+		//delay_us(1); // Wait at least 350ns after chip select
+	} else {
+		// Enable the sensor on the chain
+		gpio_set_pin_level(ANGLESENSOR.SS_pin, false);
+		//delay_us(1); // Wait at least 350ns after chip select
+		for(int i = 0; i < ANGLESENSOR.n_dev; ++i)
+		{
+			uint16_t temp = _spi_transfer16(&ANGLESENSOR, command);
+			ANGLESENSOR._readBuffer[i] = (int16_t)(temp & AS_MASK);
+		}
+		gpio_set_pin_level(ANGLESENSOR.SS_pin, true);
+		//delay_us(1); // Wait at least 350ns after chip select
+	}
+	return &ANGLESENSOR._readBuffer;
+}
+
+
+bool parity_check(int16_t sensor_result)
+{
+	// Use the LSb of result to keep track of parity (0 = even, 1 = odd)
+	int16_t result = sensor_result;
+	    
+	for(int i = 1; i <= 15; ++i) {
+		sensor_result >>= 1;
+		result ^= sensor_result;
+	}
+	// Parity should be even
+	return (result & 0x0001) == 0;
+}
+
+int16_t degrees(int16_t sensor_result)
+{
+	uint16_t data;
+	int16_t rotation;
+	
+	#ifdef AS5048
+	
+	rotation = (int16_t)(sensor_result & AS_MASK); //- static_cast<int16_t>(this->position);
+	if (rotation > AS5048A_MAX_VALUE) {
+		rotation = -((0x3FFF) - rotation); //more than -180
+	}
+		
+	float angleDegrees = 360.0 * ((rotation) + AS5048A_MAX_VALUE) / (AS5048A_MAX_VALUE * 2.0);
+	//float angleDegrees = 360.0 * ((sensor_result &= 0x3FFF) + AS5048A_MAX_VALUE) / (AS5048A_MAX_VALUE * 2.0);
+	//float32_t angleDegrees = 360.0 * (rotation + AS5048A_MAX_VALUE) * 0.000061042607;
+	
+	return (int16_t)(angleDegrees * 10 + .5);
+	
+	#elif defined A1335
+	float angleDegrees = ((sensor_result & AS_MASK) * 360.0 / 4096.0);
+	
+	//int16_t angle_deg = (sensor_result &= 0x3FFF) * 36000 / 0x4000;
+	//return angle_deg;
+	return (int16_t)(angleDegrees * 10 + .5);
+	#endif
+}
+
+int16_t mask(int16_t sensor_results)
+{
+	return (sensor_results &= 0x3FFF);
+}
+
+uint16_t _spi_transfer16(struct spi_m_sync_descriptor *spi, uint16_t command)
+{
+	uint8_t in_buf[2], out_buf[2];
+	uint16_t wordRead;
+	
+	out_buf[1] = command & 0xFF;
+	out_buf[0] = ( command >> 8 ) & 0xFF;
+	struct spi_xfer  xfer;
+	xfer.rxbuf = in_buf;
+	xfer.txbuf = (uint8_t *)out_buf;
+	xfer.size  = 2;
+	spi_m_sync_transfer(&SPI_3, &xfer);
+	wordRead = (uint16_t)((in_buf[0] << 8) | in_buf[1]);
+	return (wordRead);
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/angle_sensors.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/angle_sensors.h
new file mode 100644
index 0000000..2e4be9c
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/angle_sensors.h
@@ -0,0 +1,111 @@
+/*
+ * angle_sensors.h
+ *
+ * Created: 8/21/2021 11:16:13 AM
+ *  Author: ge37vez
+ */ 
+
+
+#ifndef ANGLE_SENSORS_H_
+#define ANGLE_SENSORS_H_
+
+#include "atmel_start.h"
+
+//Define Sensor type (One one at at time supported)
+//#define AS5048
+#define A1335
+
+// ----------------------------------------------------------------------
+// AS5048 Registers & Commands
+// ----------------------------------------------------------------------
+#ifdef AS5048
+
+typedef enum {
+	AS_FLAG_PARITY = 0x8000,
+	AS_FLAG_READ = 0x4000,
+	AS_MASK = 0x3FFF,
+} ASFlag;
+
+typedef enum {
+	AS_CMD_NOP = 0x0000,
+	AS_CMD_ERROR = 0x0001 | AS_FLAG_READ,       // Reads error register of sensor and clear error flags
+	AS_CMD_DIAGNOSTICS = 0x3FFD |  AS_FLAG_READ, // Reads automatic gain control and diagnostics info
+	AS_CMD_MAGNITUDE = 0x3FFE | AS_FLAG_READ,
+	AS_CMD_ANGLE = 0x3FFF| AS_FLAG_PARITY | AS_FLAG_READ,
+} ASCommand;
+
+// Masks for bits in the result of the AS_CMD_DIAGNOSTICS command
+typedef enum {
+	AS_DIAG_CORDIC_OVERFLOW = 0x0200,
+	AS_DIAG_HIGH_MAGNETIC = 0x0400,
+	AS_DIAG_LOW_MAGNETIC = 0x0800,
+} ASDiagnostics;
+
+// ----------------------------------------------------------------------
+// A1335 Registers & Commands
+// ----------------------------------------------------------------------
+#elif defined A1335
+
+typedef enum {
+	AS_FLAG_PARITY = 0x8000,
+	AS_FLAG_READ = 0x00,
+	AS_ADDRESS_MASK = 0x3F,
+	AS_MASK = 0x0FFF,
+} ASFlag;
+
+typedef enum {
+	AS_CMD_NOP = 0x0000,
+	AS_CMD_ERROR = 0x0001 | AS_FLAG_READ,       // Reads error register of sensor and clear error flags
+	AS_CMD_DIAGNOSTICS = 0x3FFD |  AS_FLAG_READ, // Reads automatic gain control and diagnostics info
+	AS_CMD_MAGNITUDE = (uint16_t)(((0x2A & AS_ADDRESS_MASK) | AS_FLAG_READ) << 8),
+	AS_CMD_ANGLE = (uint16_t)(((0x20 & AS_ADDRESS_MASK) | AS_FLAG_READ) << 8),
+	AS_CMD_TEMP = ((0x28 & AS_ADDRESS_MASK) | AS_FLAG_READ) << 8,
+} ASCommand;
+
+// Masks for bits in the result of the AS_CMD_DIAGNOSTICS command
+typedef enum {
+	AS_DIAG_CORDIC_OVERFLOW = 0x0200,
+	AS_DIAG_HIGH_MAGNETIC = 0x0400,
+	AS_DIAG_LOW_MAGNETIC = 0x0800,
+} ASDiagnostics;
+
+#endif
+
+/* Struct Definitions */
+struct SPI_ANGLE_SENSOR {
+	struct spi_m_sync_descriptor *SPI_descr;
+	uint8_t flags;
+	uint32_t SS_pin;
+	uint8_t n_dev;
+	int16_t _readBuffer[2]; // Must Equal n_dev
+};
+
+static struct SPI_ANGLE_SENSOR ANGLESENSOR = {
+	.SPI_descr = &SPI_3,
+	.flags = 0,
+	.SS_pin = SPI3_SS,
+	.n_dev = 2,
+	._readBuffer = {0} // Must Equal n_dev
+};
+
+void angle_sensor_init();
+int16_t* ang_sense_read(ASCommand command);
+// Performs a single angle measurement on all sensors
+// @return Array of raw angle data. To get the 14-bit value representing
+//     the angle, apply the mask() to the result.
+int16_t* read_angle();
+// Applies the mask to the first n bytes in the read buffer (for daisychained sensors).
+static int16_t mask(int16_t sensor_results);
+// Checks if the return value from the sensor has the right parity
+// @return true if ok
+static bool parity_check(int16_t sensor_result);
+// Returns an angle from 0 to 36000 (degrees times 100).
+// @param sensor_result is one of the values returned by read_angle or read_angle_sequential
+int16_t degrees(int16_t sensor_result);
+    
+// Intended to be used Internally
+int16_t* _read(ASCommand command);	
+uint16_t _spi_transfer16(struct spi_m_sync_descriptor *spi, uint16_t value);
+	
+
+#endif /* ANGLE_SENSORS_H_ */
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/arm_math.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/arm_math.h
new file mode 100644
index 0000000..ea9dd26
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/arm_math.h
@@ -0,0 +1,7157 @@
+/******************************************************************************
+ * @file     arm_math.h
+ * @brief    Public header file for CMSIS DSP LibraryU
+ * @version  V1.5.3
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+   * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
+   * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
+   * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
+   * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
+   * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+   * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
+   * 
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
+   *
+   * Preprocessor Macros
+   * ------------
+   *
+   * Each library project have different preprocessor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - ARM_MATH_ARMV8MxL:
+   *
+   * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
+   * on Armv8-M Mainline target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+   *
+   * - __DSP_PRESENT:
+   *
+   * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   *
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   *
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+  #include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+  #include "core_armv8mbl.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+  #include "core_armv8mml.h"
+  #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+    #define ARM_MATH_DSP
+  #endif
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31          (0x100)
+#define DELTA_Q15          0x5
+#define INDEX_MASK         0x0000003F
+#ifndef PI
+  #define PI               3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SPACING_Q31     0x400000
+#define TABLE_SPACING_Q15     0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING         0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if   defined ( __CC_ARM )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+#define __SIMD64(addr)        (*(int64_t **) & (addr))
+
+#if !defined (ARM_MATH_DSP)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
+                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
+                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+    q31_t out;
+    uint32_t tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t) (__CLZ( in) - 1));
+    }
+    else
+    {
+      signBits = ((uint32_t) (__CLZ(-in) - 1));
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >> 24);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0U; i < 2U; i++)
+    {
+      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+      tempVal = 0x7FFFFFFFu - tempVal;
+      /*      1.31 with exp 1 */
+      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1U);
+  }
+
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+    q15_t out = 0;
+    uint32_t tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t)(__CLZ( in) - 17));
+    }
+    else
+    {
+      signBits = ((uint32_t)(__CLZ(-in) - 17));
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >>  8);
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0U; i < 2U; i++)
+    {
+      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFFu - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+  }
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if !defined (ARM_MATH_DSP)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
+    q31_t r = 0, s = 0;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+  uint32_t x)
+  {
+    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
+  }
+
+  /*
+   * @brief C custom defined SMMLA for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+  int32_t x,
+  int32_t y,
+  int32_t sum)
+  {
+    return (sum + (int32_t) (((int64_t) x * y) >> 32));
+  }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed.
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in]  S          points to an instance of the Q15 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in]  S          points to an instance of the floating-point FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q15;
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_casd_df1_inst_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q31;
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]   pSrcA  points to the first input matrix structure
+   * @param[in]   pSrcB  points to the second input matrix structure
+   * @param[out]  pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  pSrc   points to the input matrix
+   * @param[in]  scale  scale factor
+   * @param[out] pDst   points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];     /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;          /**< The proportional gain. */
+    float32_t Ki;          /**< The integral gain. */
+    float32_t Kd;          /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] S               points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] S  is an instance of the floating-point PID Control structure
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] S   points to an instance of the Q31 PID Control structure
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] S  points to an instance of the q15 PID Control structure
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;        /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+    const arm_cfft_instance_q15 * S,
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+    const arm_cfft_instance_q31 * S,
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;             /**< length of the real sequence */
+    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+   arm_rfft_fast_instance_f32 * S,
+   uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    float32_t normalize;                 /**< normalizing factor. */
+    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;               /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q31_t normalize;                     /**< normalizing factor. */
+    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q15_t normalize;                     /**< normalizing factor. */
+    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  scale      scale factor to be applied
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q15(
+          q15_t * pSrcA,
+          uint32_t srcALen,
+          q15_t * pSrcB,
+          uint32_t srcBLen,
+          q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc  points to the block of input data.
+   * @param[out] pDst  points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   */
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.   The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S          points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages.
+ */
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize  number of samples to process per call.
+ */
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] S          points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to the state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] S          points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;         /**< step size that control filter coefficient updates. */
+    float32_t energy;     /**< saves previous frame energy. */
+    float32_t x0;         /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
+    q15_t energy;         /**< saves previous frame energy. */
+    q15_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta   input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cos output.
+   */
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal);
+
+
+  /**
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cosine output.
+   */
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] S   is an instance of the floating-point PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] S  points to an instance of the Q31 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31U);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] S   points to an instance of the Q15 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#if defined (ARM_MATH_DSP)
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+  }
+
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+  }
+
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output   rotor reference frame d
+   * @param[out] pIq     points to output   rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+  }
+
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output rotor reference frame d
+   * @param[out] pIq     points to output rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for   Q31 version
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
+   * @param[in]     x  input sample to process
+   * @return y processed output sample.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if (i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if ((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 +  i      * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q31 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (q31_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1U);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q15 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (int32_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (q15_t) (y >> 20);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q7 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+    if (index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (q7_t) (y >> 20);
+     }
+  }
+
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  sin(x).
+   */
+  float32_t arm_sin_f32(
+  float32_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q31_t arm_sin_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q15_t arm_sin_q15(
+  q15_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  cos(x).
+   */
+  float32_t arm_cos_f32(
+  float32_t x);
+
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q31_t arm_cos_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in    input value.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if (in >= 0.0f)
+    {
+
+#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] result     is output pointer
+   * @param[in]  index      is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q31 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q15 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q7 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate.
+  * @param[in]     Y  interpolation coordinate.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11U;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
+    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11U;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
+    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return ((q31_t)(acc << 2));
+  }
+
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return ((q15_t)(acc >> 36));
+  }
+
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return ((q7_t)(acc >> 40));
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if   defined ( __CC_ARM )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("push")         \
+       _Pragma ("O1")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_EXIT \
+       _Pragma ("pop")
+  #else
+    #define LOW_OPTIMIZATION_EXIT
+  #endif
+
+  /* Enter low optimization region - place directly above function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+  #define LOW_OPTIMIZATION_ENTER \
+       __attribute__(( optimize("-O1") ))
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define LOW_OPTIMIZATION_EXIT
+
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef   __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start.c
new file mode 100644
index 0000000..79f252a
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start.c
@@ -0,0 +1,9 @@
+#include <atmel_start.h>
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void)
+{
+	system_init();
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start.h
new file mode 100644
index 0000000..0de62f5
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start.h
@@ -0,0 +1,18 @@
+#ifndef ATMEL_START_H_INCLUDED
+#define ATMEL_START_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "driver_init.h"
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start_pins.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start_pins.h
new file mode 100644
index 0000000..9dc2130
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start_pins.h
@@ -0,0 +1,80 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef ATMEL_START_PINS_H_INCLUDED
+#define ATMEL_START_PINS_H_INCLUDED
+
+#include <hal_gpio.h>
+
+// SAMD51 has 14 pin functions
+
+#define GPIO_PIN_FUNCTION_A 0
+#define GPIO_PIN_FUNCTION_B 1
+#define GPIO_PIN_FUNCTION_C 2
+#define GPIO_PIN_FUNCTION_D 3
+#define GPIO_PIN_FUNCTION_E 4
+#define GPIO_PIN_FUNCTION_F 5
+#define GPIO_PIN_FUNCTION_G 6
+#define GPIO_PIN_FUNCTION_H 7
+#define GPIO_PIN_FUNCTION_I 8
+#define GPIO_PIN_FUNCTION_J 9
+#define GPIO_PIN_FUNCTION_K 10
+#define GPIO_PIN_FUNCTION_L 11
+#define GPIO_PIN_FUNCTION_M 12
+#define GPIO_PIN_FUNCTION_N 13
+
+#define SPI1_MOSI GPIO(GPIO_PORTA, 0)
+#define SPI1_SCK GPIO(GPIO_PORTA, 1)
+#define ADS_DATA_RDY GPIO(GPIO_PORTA, 2)
+#define ANAREF_3V GPIO(GPIO_PORTA, 3)
+#define M1_HALLA GPIO(GPIO_PORTA, 4)
+#define M1_HALLB GPIO(GPIO_PORTA, 5)
+#define M1_HALLC GPIO(GPIO_PORTA, 6)
+#define ECAT_SYNC GPIO(GPIO_PORTA, 7)
+#define ECAT_QSPI_MOSI GPIO(GPIO_PORTA, 8)
+#define ECAT_QSPI_MISO GPIO(GPIO_PORTA, 9)
+#define ECAT_QSPI_DATA2 GPIO(GPIO_PORTA, 10)
+#define ECAT_QSPI_DATA3 GPIO(GPIO_PORTA, 11)
+#define SPI2_MOSI GPIO(GPIO_PORTA, 12)
+#define SPI2_SCK GPIO(GPIO_PORTA, 13)
+#define SPI2_SS GPIO(GPIO_PORTA, 14)
+#define SPI2_MISO GPIO(GPIO_PORTA, 15)
+#define M2_PWMA GPIO(GPIO_PORTA, 16)
+#define M2_PWMB GPIO(GPIO_PORTA, 17)
+#define M2_PWMC GPIO(GPIO_PORTA, 18)
+#define M2_ENA GPIO(GPIO_PORTA, 19)
+#define M2_ENB GPIO(GPIO_PORTA, 20)
+#define M2_ENC GPIO(GPIO_PORTA, 21)
+#define M2_HALLA GPIO(GPIO_PORTA, 22)
+#define M2_HALLB GPIO(GPIO_PORTA, 23)
+#define M2_HALLC GPIO(GPIO_PORTA, 24)
+#define M1_RST GPIO(GPIO_PORTA, 25)
+#define M2_RST GPIO(GPIO_PORTA, 27)
+#define SPI3_SS GPIO(GPIO_PORTB, 0)
+#define SPI3_MISO GPIO(GPIO_PORTB, 1)
+#define SPI3_MOSI GPIO(GPIO_PORTB, 2)
+#define SPI3_SCK GPIO(GPIO_PORTB, 3)
+#define M1_IA GPIO(GPIO_PORTB, 4)
+#define M1_IB GPIO(GPIO_PORTB, 5)
+#define M2_IA GPIO(GPIO_PORTB, 6)
+#define M2_IB GPIO(GPIO_PORTB, 7)
+#define half_VREF GPIO(GPIO_PORTB, 8)
+#define ADS_RESET GPIO(GPIO_PORTB, 9)
+#define ECAT_QSPI_SCK GPIO(GPIO_PORTB, 10)
+#define ECAT_QSPI_CS GPIO(GPIO_PORTB, 11)
+#define M1_PWMA GPIO(GPIO_PORTB, 12)
+#define M1_PWMB GPIO(GPIO_PORTB, 13)
+#define M1_PWMC GPIO(GPIO_PORTB, 14)
+#define M1_ENA GPIO(GPIO_PORTB, 15)
+#define M1_ENB GPIO(GPIO_PORTB, 16)
+#define M1_ENC GPIO(GPIO_PORTB, 17)
+#define SPI1_CS GPIO(GPIO_PORTB, 22)
+#define SPI1_MISO GPIO(GPIO_PORTB, 23)
+#define M1_RST_Bar GPIO(GPIO_PORTB, 30)
+#define M2_RST_Bar GPIO(GPIO_PORTB, 31)
+
+#endif // ATMEL_START_PINS_H_INCLUDED
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc.c
new file mode 100644
index 0000000..6770eda
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc.c
@@ -0,0 +1,554 @@
+/*
+ * bldc.c
+ *
+ * Created: 31/07/2021 14:56:17
+ *  Author: Nick-XMG
+ */ 
+
+#include "bldc.h"
+
+#include "utilities.h"
+#include "Ethercat_SlaveDef.h"
+
+void motor_StateMachine(BLDCMotor_t* const motor)
+{
+	
+	//if (motor->motor_state.fault)
+	//{
+		//motor->motor_state.previousstate = motor->motor_state.currentstate;
+		//motor->motor_state.currentstate = MOTOR_FAULT;
+	//}
+	
+	switch (motor->motor_state.currentstate)
+	{
+		case MOTOR_INIT: ;
+			volatile uint8_t currentHall = motor->readHall();
+			if((currentHall > 6) || (currentHall < 1) )  {
+				motor->motor_state.fault = MOTOR_HALLSENSORINVALID;
+				motor->motor_state.currentstate = MOTOR_FAULT;
+				break;	
+			} 
+			motor->motor_state.previousstate = motor->motor_state.currentstate;
+			motor->motor_state.currentstate = MOTOR_IDLE;
+		break;
+		case  MOTOR_IDLE:
+			//hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw,  DISABLE_PATTERN);
+			motor->motor_state.previousstate = motor->motor_state.currentstate;
+			motor->motor_state.currentstate = MOTOR_PVI_CTRL_STATE;
+		break;
+		case MOTOR_OPEN_LOOP_STATE:
+			BLDC_runOpenLoop(motor, 100);
+			calculate_motor_speed(motor);
+			motor->motor_state.previousstate = motor->motor_state.currentstate;
+		break;
+		case MOTOR_V_CTRL_STATE:
+			calculate_motor_speed(motor);
+			BLDC_runSpeedCntl(motor, (float32_t)motor->motor_status.calc_rpm, (float32_t)motor->motor_setpoints.desired_speed);
+			motor->motor_state.previousstate = motor->motor_state.currentstate;	
+		break;	
+		case MOTOR_VI_CTRL_STATE:	
+			switch (motor->regulation_loop_count) {
+				case 0: /* PWM FREQ / 25 - 1kHz */	
+				//case 5: case 10: case 15: case 20:/* PWM FREQ / 5 - 5kHz */
+				case 5: case 15: /* PWM FREQ / 5 - 5kHz */
+					calculate_motor_speed(motor);
+					BLDC_runSpeedCntl(motor, (float32_t)motor->motor_status.calc_rpm, (float32_t)motor->motor_setpoints.desired_speed);	
+				default: /* PWM FREQ - 25kHz */
+					select_active_phase(motor);
+					BLDC_runCurrentCntl(motor,(float32_t)motor->Iphase_pu.Bus, (float32_t)motor->controllers.Pi_Idc.Ref_pu);
+				break;
+			} // end switch(regulation_loop_count)
+			if(motor->regulation_loop_count > 23) motor->regulation_loop_count = 0;
+			else motor->regulation_loop_count++;
+		break;
+		case MOTOR_PVI_CTRL_STATE:	
+			switch (motor->regulation_loop_count) {
+				case 0: /* PWM FREQ / 25 - 1kHz */
+					BLDC_runPosCntl(motor, motor->motor_status.Num_Steps, motor->motor_setpoints.desired_position);	
+				case 5: case 10: case 15: case 20:/* PWM FREQ / 5 - 5kHz */
+					calculate_motor_speed(motor);	
+					BLDC_runSpeedCntl(motor, (float32_t)motor->motor_status.calc_rpm, (float32_t)motor->controllers.Pid_Speed.Ref_pu);
+				default: /* PWM FREQ - 25kHz */
+					select_active_phase(motor);
+					//select_active_phase(&Motor2, Motor2.motor_status.currentHallPattern);
+					BLDC_runCurrentCntl(motor, motor->Iphase_pu.Bus, motor->controllers.Pi_Idc.Ref_pu);
+				break;
+			} // end switch(regulation_loop_count)
+			if(motor->regulation_loop_count > 23) motor->regulation_loop_count = 0;
+			else motor->regulation_loop_count++;
+		break;
+		case MOTOR_FAULT:
+			disable_phases(motor);
+		break;
+	} //end switch (motor->motor_state.currentstate)
+	
+	// ----------------------------------------------------------------------
+	// Run Commutation
+	// ----------------------------------------------------------------------
+	
+}
+
+void BldcInitStruct(BLDCMotor_t* const motor, BLDCMotor_param_t * const motor_param)
+{
+	// ----------------------------------------------------------------------
+	//  Assign Motor Parameters:
+	// ----------------------------------------------------------------------
+	motor->motor_param						 = motor_param;
+							
+	
+	// ----------------------------------------------------------------------
+	// Initialize State Machine:
+	// ----------------------------------------------------------------------
+	motor->motor_state.currentstate			 = 	MOTOR_INIT;
+	motor->motor_state.previousstate		 =	MOTOR_INIT;
+	motor->motor_state.fault				 =	MOTOR_NOFAULT;			
+	// ----------------------------------------------------------------------
+	//  Initialize Status Struct:
+	// ----------------------------------------------------------------------
+	motor->motor_status.actualDirection		 = 0;
+	motor->motor_status.duty_cycle			 = 0;
+	motor->motor_status.calc_rpm			 = 0;
+	motor->motor_status.abs_position		 = 0;
+	motor->motor_status.Num_Steps			 = 0;
+	motor->motor_status.cur_comm_step		 = 0;
+	motor->motor_status.currentHallPattern	 = 1;
+	//motor->motor_status.nextHallPattern	 = 3;
+	
+	motor->motor_status.speed_average		 = 0;
+	motor->motor_status.count				 = 1;
+		
+	// ----------------------------------------------------------------------
+	//  Initialize Phase Current Struct:
+	// ----------------------------------------------------------------------
+	motor->Iphase_pu.A						 = 0;
+	motor->Iphase_pu.B						 = 0;
+	motor->Iphase_pu.C						 = 0;
+	motor->Iphase_pu.Bus					 = 0;
+		
+	// ----------------------------------------------------------------------
+	//  Initialize Timers:
+	// ----------------------------------------------------------------------
+	motor->timerflags.pwm_cycle_tic			 = false;
+	motor->timerflags.control_loop_tic		 = false;
+	motor->timerflags.motor_telemetry_flag	 = false;
+	motor->timerflags.control_loop_tic		 = false;
+	motor->timerflags.adc_readings_ready_tic = false;
+	
+	// ----------------------------------------------------------------------
+	//  Current Sensors Calibration offsets:
+	// ----------------------------------------------------------------------
+	motor->Voffset_lsb.A					 = 0;
+	motor->Voffset_lsb.B					 = 0;
+	
+	// ----------------------------------------------------------------------
+	//  Regulation Loop Counter
+	// ----------------------------------------------------------------------
+	motor->regulation_loop_count			 = 0;
+
+	// ----------------------------------------------------------------------
+	//  Initialize Bus Voltage:
+	// ----------------------------------------------------------------------
+	motor->VdcBus_pu						 = DEVICE_DC_VOLTAGE_V;
+	motor->VoneByDcBus_pu					 = 1.0f/DEVICE_DC_VOLTAGE_V;
+	
+	// ----------------------------------------------------------------------
+	//  Initialize Setpoints Struct:
+	// ----------------------------------------------------------------------
+	motor->motor_setpoints.desiredDirection	 = 0;
+	motor->motor_setpoints.desired_torque	 = 0.0;
+	motor->motor_setpoints.desired_speed	 = 0;
+	motor->motor_setpoints.desired_position  = 0;
+	motor->motor_setpoints.max_current		 = 0.0;
+	motor->motor_setpoints.max_torque		 = 0.0;
+	motor->motor_setpoints.max_velocity		 = 0;
+	motor->motor_setpoints.directionOffset	 = 0;
+		
+	//// ------------------------------------------------------------------------------
+	//// Initialize PI current control 
+	//// ------------------------------------------------------------------------------
+	PI_objectInit(&motor->controllers.Pi_Idc);
+	float32_t motorLs_H   = motor_param->motor_LQ_H	  * 2.0f;
+	float32_t motorRs_OHM = motor_param->motor_RS_Ohm * 2.0f;
+	motor->controllers.Pi_Idc.Kp = PI_calcKp(motorLs_H, DEVICE_SHUNT_CURRENT_A, DEVICE_DC_VOLTAGE_V, DEVICE_ISR_PERIOD_Sec);
+	motor->controllers.Pi_Idc.Ki = PI_calcKi(motorRs_OHM, motorLs_H, DEVICE_ISR_PERIOD_Sec);
+	
+	//// ------------------------------------------------------------------------------
+	//// Initialize PD Vel control 
+	//// ------------------------------------------------------------------------------
+	PID_objectInit(&motor->controllers.Pid_Speed);
+	/* V Control Gains */
+	//motor->controllers.Pid_Speed.Kp = 0.005f;
+	//motor->controllers.Pid_Speed.Ki = 0.00001f;
+	//motor->controllers.Pid_Speed.Kd = 0.001f;
+		
+	/* VI Control Gains */
+	//motor->controllers.Pid_Speed.Kp = 0.0002f;
+	//motor->controllers.Pid_Speed.Ki = 0.0000001f;
+	motor->controllers.Pid_Speed.Kp = motor_param->controller_param.Pid_Speed.Kp;
+	motor->controllers.Pid_Speed.Ki = motor_param->controller_param.Pid_Speed.Ki;
+	
+	//motor->controllers.Pid_Speed.Kp = 0.0005f;
+	//motor->controllers.Pid_Speed.Ki = 0.0f;
+	//motor->controllers.Pid_Speed.Kd = 0.0001f;
+	
+	/* Limits */
+	motor->controllers.Pid_Speed.OutMax_pu =  (motor_param->motor_Max_Current_IDC_A);
+	motor->controllers.Pid_Speed.OutMin_pu = -(motor_param->motor_Max_Current_IDC_A);
+	
+	//// ------------------------------------------------------------------------------
+	////  Initialize PI Position control
+	//// ------------------------------------------------------------------------------
+	PI_objectInit(&motor->controllers.Pi_Pos);
+	//motor->controllers.Pi_Pos.Kp = 40.0f;
+	//motor->controllers.Pi_Pos.Ki = 0.0f;	
+	motor->controllers.Pi_Pos.Kp = motor_param->controller_param.Pi_Pos.Kp;
+	motor->controllers.Pi_Pos.Ki = motor_param->controller_param.Pi_Pos.Ki;
+	motor->controllers.Pi_Pos.OutMax_pu =  (motor_param->motor_Max_Spd_RPM);
+	motor->controllers.Pi_Pos.OutMin_pu = -(motor_param->motor_Max_Spd_RPM);
+}
+
+void exec_commutation(BLDCMotor_t* const motor)
+{
+	
+	// ----------------------------------------------------------------------
+	// Read Motor Hall Sensors
+	// ----------------------------------------------------------------------
+	//tic_port(DEBUG_2_PORT);
+	//motor->motor_status.currentHallPattern = readM1Hall();
+	volatile uint8_t currentHall = motor->readHall();
+	motor->motor_status.currentHallPattern = currentHall;
+		
+	if (currentHall == INVALID_HALL_7)
+	{
+		///motor->motor_state.currentstate == MOTOR_FAULT;
+		//motor->motor_state.fault == MOTOR_HALLSENSORINVALID;
+		//return;
+	}
+																		   
+	// ----------------------------------------------------------------------
+	// Set Pattern Buffers
+	// ----------------------------------------------------------------------
+	volatile uint16_t temp_M1	= COMMUTATION_PATTERN[currentHall + 
+													  motor->motor_setpoints.directionOffset];
+
+	//TCC0->PATTBUF.reg = temp_M1;
+	Tcc * tmp = (Tcc *)motor->pwm_desc->device.hw;
+	tmp->PATTBUF.reg = (uint16_t)temp_M1;
+	//motor->motor_param->pwm_desc->device.hw->PATTBUF.reg = temp_M1;
+	//hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw,  temp_M1);
+	
+	// ----------------------------------------------------------------------
+	// Set Calculated Duty Cycle
+	// ----------------------------------------------------------------------
+	//hri_tcc_write_CCBUF_CCBUF_bf(motor->motor_param->pwm_desc->device.hw, 0, motor->motor_status.duty_cycle);
+	tmp->CCBUF[0].reg = (uint32_t)motor->motor_status.duty_cycle;
+
+
+	volatile uint8_t cur_comm_step = MOTOR_COMMUTATION_STEPS[currentHall];
+	motor->motor_status.cur_comm_step = cur_comm_step;
+	volatile int8_t step_change = (cur_comm_step - motor->motor_status.prev_comm_step);
+	
+	switch(step_change)
+	{
+		case 1: case -5:
+			motor->motor_status.Num_Steps += 1;
+			motor->motor_status.actualDirection = CW;
+		//Motor1.motor_setpoints.directionOffset = DIRECTION_CW_OFFSET;
+		break;
+		case -1: case 5:
+			motor->motor_status.Num_Steps -= 1;
+			motor->motor_status.actualDirection = CCW;
+		//Motor1.motor_setpoints.directionOffset = DIRECTION_CCW_OFFSET;
+		break;
+		default:
+		// do nothing
+		break;
+	}
+	motor->motor_status.prev_comm_step = cur_comm_step;
+	//toc_port(DEBUG_2_PORT);
+}
+
+//// ------------------------------------------------------------------------------
+// Current Selection Based on Hall State
+// Direction":
+// CW  -> Always positive current
+// CCW -> Always negative current
+//// ------------------------------------------------------------------------------
+void select_active_phase(BLDCMotor_t* const Motor)
+{
+	uint8_t hall_state = Motor->motor_status.currentHallPattern;
+	volatile float32_t phase_current = 0;
+	switch(hall_state)
+	{
+		case 0b001:	case 0b011:
+		phase_current = Motor->Iphase_pu.C;
+		break;
+			
+		case 0b010:	case 0b110:
+		phase_current = Motor->Iphase_pu.B;
+		break;
+			
+		case 0b100: case 0b101:
+		phase_current = Motor->Iphase_pu.A;
+		break;
+			
+		default :
+		//phase_current = 0;	// Invalid hall code
+		break;
+	}	
+	Motor->Iphase_pu.Bus = phase_current;
+}
+
+void calculate_motor_speed(BLDCMotor_t* const motor)
+{	
+	//tic_port(DEBUG_2_PORT);
+	volatile uint32_t temp_rpm = 0;
+	hri_tccount32_read_CC_reg(motor->speedtimer_hw, 0); /* Read CC0 but throw away)*/
+	volatile uint32_t period_after_capture = hri_tccount32_read_CC_reg(motor->speedtimer_hw, 1);
+	if((period_after_capture >= UINT32_MAX)||(period_after_capture == 0)||(period_after_capture > 600000))  {
+		motor->motor_status.calc_rpm = 0;
+	} else {
+		////uint32_t test = (SPEEDFACTOR, period_after_capture);
+		////temp_rpm = SPEEDFACTOR / period_after_capture;
+		////tic_port(DEBUG_3_PORT);
+		temp_rpm = HZ_TO_RPM / (period_after_capture * motor->motor_param->motor_commutationStates);
+		//temp_rpm = HZ_TO_RPM * period_after_capture;
+		////toc_port(DEBUG_3_PORT);
+		
+		//uint32_t muti = DEVICE_SPEEDTC_FREQUENCY_Hz*60;
+		//temp_rpm = (muti) / (period_after_capture*42);
+	}
+	
+	if(motor->motor_status.actualDirection == CCW) /* Changed from CCW */
+	{
+		//*motor_speed = -1* Motor1.calc_rpm;
+		temp_rpm = -1 * temp_rpm;
+	} else { 
+		//*motor_speed = Motor1.calc_rpm;
+		temp_rpm = temp_rpm;
+	}
+		
+	//motor->motor_status.calc_rpm = (int16_t)temp_rpm;
+	
+	#ifdef AVERAGE_SPEED_MEASURE
+		
+		// To avoid noise an average is realized on 8 samples
+		motor->motor_status.speed_average += temp_rpm;
+		if(motor->motor_status.count >= n_SAMPLE)
+		{
+			
+			motor->motor_status.count = 1;
+			motor->motor_status.calc_rpm = (motor->motor_status.speed_average >> 3); // divide by 8
+			//Motor1.motor_status.calc_rpm = (speed_average); // divide by 8
+			motor->motor_status.speed_average = 0;
+			//*Spare_byte1 = motorState.actualDirection;
+			if(motor->motor_status.actualDirection == CCW) /* Changed from CCW */
+			{
+				//*motor_speed = -1* Motor1.calc_rpm;
+				motor->motor_status.calc_rpm = -1* motor->motor_status.calc_rpm;
+			} else { 
+				//*motor_speed = Motor1.calc_rpm;
+				motor->motor_status.calc_rpm = motor->motor_status.calc_rpm;
+			}
+			return;
+		}
+		else motor->motor_status.count++;
+	#endif
+	
+	motor->motor_status.calc_rpm = (int16_t)temp_rpm;
+	//toc_port(DEBUG_2_PORT);	
+}
+
+
+void disable_phases(BLDCMotor_t* const motor)
+{
+	Tcc * tmp = (Tcc *)motor->pwm_desc->device.hw;
+	tmp->PATTBUF.reg = DISABLE_PATTERN;
+}
+
+//------------------------------------------------------------------------------
+// pi current control
+//------------------------------------------------------------------------------
+void BLDC_runCurrentCntl(BLDCMotor_t *motor, const float32_t curfbk, const float32_t curRef)
+{
+	motor->controllers.Pi_Idc.Fbk_pu = f_clamp(curfbk, -DEVICE_SHUNT_CURRENT_A, DEVICE_SHUNT_CURRENT_A); // Clamped to max current sensor readingspeedfbk;
+	motor->controllers.Pi_Idc.Ref_pu = f_clamp(curRef, -motor->motor_param->motor_Max_Current_IDC_A, 
+														motor->motor_param->motor_Max_Current_IDC_A);	// Clamp desired to Motor Max Current i_ref_clamped;
+	
+	//*Spare_1 = (int16_t)(motor->controllers.Pi_Idc.Ref_pu * 1000);  // Send Req Current to TC
+
+	motor->controllers.Pi_Idc.OutMax_pu = motor->VdcBus_pu;
+	motor->controllers.Pi_Idc.OutMin_pu = -motor->VdcBus_pu;
+	PI_run_series(&motor->controllers.Pi_Idc);
+	
+	if(motor->controllers.Pi_Idc.Out_pu > 0) {
+		motor->motor_setpoints.desiredDirection = 0; 
+		motor->motor_setpoints.directionOffset = 0;
+	} else {
+		motor->motor_setpoints.desiredDirection = 1;
+		motor->motor_setpoints.directionOffset = 8;
+	}
+
+	volatile float32_t duty_pu = f_abs((motor->controllers.Pi_Idc.Out_pu * motor->VoneByDcBus_pu));
+	//motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
+	//motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
+	motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * motor->motor_param->motor_MaxPWM, 0.0f, (float32_t)MAX_PWM);
+	// Remove Low duty cycle values
+	//if(duty_cycle < 80.0) motor->duty_cycle = (uint16_t)0;
+	//else motor->duty_cycle = (uint16_t)duty_cycle;
+	
+}
+
+//// ------------------------------------------------------------------------------
+// Speed Control: Input in RPM units (int16_t)
+//------------------------------------------------------------------------------
+void BLDC_runSpeedCntl(BLDCMotor_t *motor, const float32_t speedfbk, const float32_t speedRef)
+{
+	//tic_port(DEBUG_3_PORT);
+	motor->controllers.Pid_Speed.Fbk_pu = speedfbk; 
+	motor->controllers.Pid_Speed.Ref_pu = f_clamp(speedRef, -motor->motor_param->motor_Max_Spd_RPM, 
+															 motor->motor_param->motor_Max_Spd_RPM);	
+	
+	if (motor->motor_state.currentstate == MOTOR_V_CTRL_STATE)
+	{
+		/* Output Pu in Volts (PWM %) */
+		motor->controllers.Pid_Speed.OutMax_pu = motor->VdcBus_pu;
+		motor->controllers.Pid_Speed.OutMin_pu = -motor->VdcBus_pu;
+		
+		PID_run_parallel(&motor->controllers.Pid_Speed);
+		
+		if(motor->controllers.Pid_Speed.Out_pu > 0) {
+			motor->motor_setpoints.desiredDirection = 0; 
+			motor->motor_setpoints.directionOffset = 0;
+		} else {
+			motor->motor_setpoints.desiredDirection = 1;
+			motor->motor_setpoints.directionOffset = 8;
+		}
+		/* Process unit is Volts */
+		volatile float32_t duty_pu = f_abs((motor->controllers.Pid_Speed.Out_pu * motor->VoneByDcBus_pu));
+		volatile float32_t duty_cycle = f_clamp(duty_pu *  (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
+		motor->motor_status.duty_cycle = (uint16_t)duty_cycle;
+	} else 	{
+		/* Pu in Current (Amps) */
+		motor->controllers.Pid_Speed.OutMax_pu =  (motor->motor_param->motor_Max_Current_IDC_A);
+		motor->controllers.Pid_Speed.OutMin_pu = -(motor->motor_param->motor_Max_Current_IDC_A);
+		PID_run_parallel(&motor->controllers.Pid_Speed);
+		motor->controllers.Pi_Idc.Ref_pu = motor->controllers.Pid_Speed.Out_pu;
+	}
+	//toc_port(DEBUG_3_PORT);
+}
+
+//// ------------------------------------------------------------------------------
+// Position Control:Input in Hall step units (int16_t)
+//------------------------------------------------------------------------------
+void BLDC_runPosCntl(BLDCMotor_t *motor, const int16_t posfbk, const int16_t posRef)
+{
+	/* Output Pu in RPM */
+	motor->controllers.Pi_Pos.OutMax_pu = motor->motor_param->motor_Max_Spd_RPM;
+	motor->controllers.Pi_Pos.OutMin_pu = -motor->motor_param->motor_Max_Spd_RPM;
+	motor->controllers.Pi_Pos.Fbk_pu = posfbk;	
+	motor->controllers.Pi_Pos.Ref_pu = posRef;	
+	PI_run_series(&motor->controllers.Pi_Pos);
+	motor->controllers.Pid_Speed.Ref_pu = motor->controllers.Pi_Pos.Out_pu;
+}
+
+void BLDC_runOpenLoop(BLDCMotor_t *motor, int16_t duty)
+{
+	if (duty < 0){
+		motor->motor_setpoints.directionOffset = DIRECTION_CCW_OFFSET;
+	} else {
+		motor->motor_setpoints.directionOffset = DIRECTION_CW_OFFSET;
+	}
+	motor->motor_status.duty_cycle = u_clamp(abs(duty), 0, MAX_PWM); 
+}
+
+volatile uint8_t readHallSensorM1(void)
+{
+	
+	volatile uint8_t motor_read = 0;
+	motor_read = (motor_read & M1_HALL_A_MASK) | (uint8_t)((PORT->Group[M1_HALL_A_GROUP].IN.reg & M1_HALL_A_PORT)>>(M1_HALL_A_LSR));
+	motor_read = (motor_read & M1_HALL_B_MASK) | (uint8_t)((PORT->Group[M1_HALL_B_GROUP].IN.reg & M1_HALL_B_PORT)>>(M1_HALL_B_LSR));
+	motor_read = (motor_read & M1_HALL_C_MASK) | (uint8_t)((PORT->Group[M1_HALL_C_GROUP].IN.reg & M1_HALL_C_PORT)>>(M1_HALL_C_LSR));
+	return motor_read;
+	
+	//volatile uint8_t a = gpio_get_pin_level(M1_HALL_A_PIN);
+	//volatile uint8_t b = gpio_get_pin_level(M1_HALL_B_PIN);
+	//volatile uint8_t c = gpio_get_pin_level(M1_HALL_C_PIN);
+	//return ((a << 2)	|
+			//(b << 1)	|
+			//(c << 0));
+	
+}
+
+volatile uint8_t readHallSensorM2(void)
+{
+	
+	volatile uint8_t motor_read = 0;
+	motor_read = (motor_read & M2_HALL_A_MASK) | (uint8_t)((PORT->Group[M2_HALL_A_GROUP].IN.reg & M2_HALL_A_PORT)>>(M2_HALL_A_LSR)); 
+	motor_read = (motor_read & M2_HALL_B_MASK) | (uint8_t)((PORT->Group[M2_HALL_B_GROUP].IN.reg & M2_HALL_B_PORT)>>(M2_HALL_B_LSR)); 
+	motor_read = (motor_read & M2_HALL_C_MASK) | (uint8_t)((PORT->Group[M2_HALL_C_GROUP].IN.reg & M2_HALL_C_PORT)>>(M2_HALL_C_LSR)); 
+	
+	return motor_read;
+	//if(((motor_read == INVALID_HALL_0) || (motor_read == INVALID_HALL_7))) {
+		//Motor2.motor_state.fault = MOTOR_HALLSENSORINVALID;
+		//Motor2.motor_state.currentstate = MOTOR_FAULT;
+		////applicationStatus.currentstate = APP_FAULT;
+	//}
+		
+	//volatile uint8_t a = gpio_get_pin_level(M2_HALL_A_PIN);
+	//volatile uint8_t b = gpio_get_pin_level(M2_HALL_B_PIN);
+	//volatile uint8_t c = gpio_get_pin_level(M2_HALL_C_PIN);	
+	//volatile uint8_t motor_read2 = ((a << 2)|(b << 1)|(c << 0));
+	//return ((a << 2)	|
+			//(b << 1)	|
+			//(c << 0));
+	
+}
+
+// ----------------------------------------------------------------------
+// Before Power up, Measure and average offset voltage for Current Sensor
+// This voltage is subtracted from all reading for Bi-Directional Current
+// Measurement
+// ----------------------------------------------------------------------
+void read_zero_current_offset_value(BLDCMotor_t *motor1, BLDCMotor_t *motor2)
+{
+	volatile int32_t phase_zero_current_offset [NUM_CUR_SENSORS] = {0};
+	volatile int16_t zero_current_offset_temp = 0;
+	const uint8_t samples = 32;
+	
+	adc_sync_enable_channel(&ADC_1, 9);
+	for (int n=0; n<NUM_CUR_SENSORS; n++)
+	{
+		ADC1->INPUTCTRL.reg = adc1_seq_regs[n];
+		for (int i=0; i<samples; i++)
+		{
+			while (ADC1->STATUS.bit.ADCBUSY) {};					 /* Wait for bus synchronization. */
+			ADC1->SWTRIG.bit.START = true;							 /* Start the ADC using a software trigger. */
+			while (ADC1->INTFLAG.bit.RESRDY == 0);					 /* Wait for the result ready flag to be set. */
+			ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY;					 /* Clear the flag. */
+			zero_current_offset_temp	= (int16_t)ADC1->RESULT.reg; /* Read the value. */
+			phase_zero_current_offset[n] += zero_current_offset_temp;
+		}
+		phase_zero_current_offset[n] = 	phase_zero_current_offset[n]/samples;
+	}
+	adc_sync_disable_channel(&ADC_1, 9);
+	
+	motor1->Voffset_lsb.A = phase_zero_current_offset[0];
+	motor1->Voffset_lsb.B = phase_zero_current_offset[1];
+	motor2->Voffset_lsb.A = phase_zero_current_offset[2];
+	motor2->Voffset_lsb.B = phase_zero_current_offset[3];
+	
+	/* Check for Defective current sensor based on offset from nominal 1.5V (O current voltage) */
+	
+	if ((abs(motor1->Voffset_lsb.A) > MAX_CUR_SENSE_OFFSET) || (abs(motor1->Voffset_lsb.B) > MAX_CUR_SENSE_OFFSET))
+	{
+		motor1->motor_state.currentstate = MOTOR_FAULT;
+		motor1->motor_state.fault = MOTOR_CURRENTS_SENSOR;
+	}
+	
+	if ((abs(motor2->Voffset_lsb.A) > MAX_CUR_SENSE_OFFSET) || (abs(motor2->Voffset_lsb.B) > MAX_CUR_SENSE_OFFSET))
+	{
+		motor2->motor_state.currentstate = MOTOR_FAULT;
+		motor2->motor_state.fault = MOTOR_CURRENTS_SENSOR;
+	}
+}
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc.h
new file mode 100644
index 0000000..324ff3b
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc.h
@@ -0,0 +1,110 @@
+/*
+ * bldc.h
+ *
+ * Created: 31/07/2021 14:56:02
+ *  Author: Nick-XMG
+ */ 
+
+#ifndef BLDC_H_
+#define BLDC_H_
+
+// ----------------------------------------------------------------------
+// 	header files
+// ----------------------------------------------------------------------
+#include "atmel_start.h"
+#include "bldc_types.h"
+#include "motorparameters.h"
+#include "statemachine.h"
+
+#define PWM_TOP					(1000)
+#define MAX_PWM					(800)
+//#define MAX_VEL					3800
+
+#define CW						(0) //CBA
+#define DIRECTION_CW_OFFSET		(0) //CBA
+#define CCW						(1) //ABC
+#define DIRECTION_CCW_OFFSET	(8) //CBA
+
+/* if the Hall sensor reads 0x0 or 0x7 that means either one of the hall sensor is damaged or disconnected*/
+#define INVALID_HALL_0              (0)
+#define INVALID_HALL_7              (7)
+
+//#define AVERAGE_SPEED_MEASURE		1
+#define n_SAMPLE 8
+
+// ----------------------------------------------------------------------
+// 	ADC Parameters
+// ----------------------------------------------------------------------
+#define ADC_VOLTAGE_REFERENCE		(3.0f)
+#define ADC_RESOLUTION				(12)
+#define ADC_MAX_COUNTS				(1<<ADC_RESOLUTION)
+#define ADC_LSB_SIZE				(ADC_VOLTAGE_REFERENCE/ADC_MAX_COUNTS)
+#define LSB_TO_PU					(ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY)
+
+//static const uint32_t adc1_seq_regs[4]	= {0x0089, 0x0088, 0x0087, 0x0086};
+//static volatile int16_t adc0_res[4]	= {0};
+//static volatile int16_t adc1_res[4]	= {0};
+	
+extern const uint32_t adc1_seq_regs[4];
+extern volatile int16_t adc1_res[4];
+
+// ----------------------------------------------------------------------
+// Define the control and PWM frequencies:
+// ----------------------------------------------------------------------
+#define DEVICE_MCU_FREQUENCY_Hz        (120000000U)
+#define DEVICE_SPEEDTC_DIV			   (4U)
+#define DEVICE_SPEEDTC_FREQUENCY_Hz    (DEVICE_MCU_FREQUENCY_Hz/DEVICE_SPEEDTC_DIV)
+#define DEVICE_PWM_FREQUENCY_kHz       (25.0f)
+#define DEVICE_ISR_FREQUENCY_kHz       DEVICE_PWM_FREQUENCY_kHz
+#define DEVICE_ISR_PERIOD_Sec		   (0.001f/DEVICE_ISR_FREQUENCY_kHz)
+#define HZ_TO_RPM					   (DEVICE_SPEEDTC_FREQUENCY_Hz * 60)
+//#define HZ_TO_RPM					   MOTOR_COMUTATION_STATES/(DEVICE_SPEEDTC_FREQUENCY_Hz * 60)
+
+// ----------------------------------------------------------------------
+// Define the device quantities (voltage, current, speed)
+// ----------------------------------------------------------------------
+#define DEVICE_DC_VOLTAGE_V					24.0f   // max. ADC bus voltage(PEAK) [V]
+#define DEVICE_SHUNT_CURRENT_A				2.5f    // phase current(PEAK) [A]
+#define CURRENT_SENSOR_SENSITIVITY			0.4f    //V/A
+#define ONEON_CURRENT_SENSOR_SENSITIVITY	2.5f    //V/A
+#define MAX_CUR_SENSE_OFFSET				100
+#define NUM_CUR_SENSORS						4
+// ----------------------------------------------------------------------
+// 	global variables
+// ----------------------------------------------------------------------
+
+static const uint8_t HALL_PATTERN_ARRAY[16]		= {0, 5, 3, 1, 6, 4, 2, 0, 0, 3, 6, 2, 5, 1, 4, 0 };
+static const uint8_t MOTOR_COMMUTATION_STEPS[8]		= {9, 1, 3, 2, 5, 6, 4, 9};
+
+static volatile BLDCMotor_t Motor1 = {
+	.pwm_desc = &PWM_0,
+	.speedtimer_hw = TC2,
+};
+static volatile BLDCMotor_t Motor2  = {
+	.pwm_desc = &PWM_1,
+	.speedtimer_hw = TC4,
+};
+
+static volatile MOTOR_STATE_t Motor1_Status;
+static volatile MOTOR_STATE_t Motor2_Status;
+
+// ----------------------------------------------------------------------
+// 	functions
+// ----------------------------------------------------------------------
+void motor_StateMachine(BLDCMotor_t* const motor);
+void BldcInitStruct(BLDCMotor_t* const motor, BLDCMotor_param_t* constmotor_param);
+void exec_commutation(BLDCMotor_t* const motor);
+void select_active_phase(BLDCMotor_t* const Motor);
+void calculate_motor_speed(BLDCMotor_t* const motor);
+void disable_phases(BLDCMotor_t* const motor);
+// ----------------------------------------------------------------------
+// 	Static Functions
+// ----------------------------------------------------------------------
+static void BLDC_runSpeedCntl(BLDCMotor_t *motor, const float32_t speedfbk, const float32_t speedRef);
+static void BLDC_runCurrentCntl(BLDCMotor_t *motor, const float32_t curfbk, const float32_t curRef);
+static void BLDC_runPosCntl(BLDCMotor_t *motor, int16_t posfbk, int16_t posRef);
+static void BLDC_runOpenLoop(BLDCMotor_t *motor, int16_t duty);
+volatile uint8_t readHallSensorM1(void);
+volatile uint8_t readHallSensorM2(void);
+
+#endif /* BLDC_H_ */
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc_types.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc_types.h
new file mode 100644
index 0000000..4939018
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc_types.h
@@ -0,0 +1,107 @@
+/*
+ * bldc_types.h
+ *
+ * Created: 8/5/2021 9:40:45 AM
+ *  Author: ge37vez
+ */ 
+
+
+#ifndef BLDC_TYPES_H_
+#define BLDC_TYPES_H_
+
+#include "atmel_start.h"
+#include "control.h"
+#include "motorparameters.h"
+#include "statemachine.h"
+
+// ----------------------------------------------------------------------
+// 	function Pointer
+// ----------------------------------------------------------------------
+typedef uint8_t (*readHallSensor)(void);
+
+// ----------------------------------------------------------------------
+// 	Type Definitions
+// ----------------------------------------------------------------------
+volatile typedef struct
+{
+	volatile float32_t A;          // Phase A
+	volatile float32_t B;          // Phase B
+	volatile float32_t C;          // Phase C
+	volatile float32_t Bus;        // Currently Active Phase Current
+} MOTOR_PHASES_t;
+
+volatile typedef struct
+{
+	volatile int16_t A;          // Phase A measured offset
+	volatile int16_t B;          // Phase B measured offset
+} MOTOR_phase_offset_t;
+
+volatile typedef struct timerflags
+{
+	volatile bool pwm_cycle_tic;
+	volatile bool current_loop_tic;
+	volatile bool control_loop_tic;
+	volatile bool adc_readings_ready_tic;
+	volatile bool motor_telemetry_flag;
+}	TIMERflags_t;
+
+volatile typedef struct
+{
+	volatile uint8_t   desiredDirection;	//! The desired direction of rotation.
+	volatile uint8_t   directionOffset;
+	volatile float32_t desired_torque;
+	volatile int16_t   desired_speed;
+	volatile int16_t   desired_position;
+	volatile float32_t max_torque;
+	volatile float32_t max_current;
+	volatile int16_t   max_velocity;
+}	MOTOR_Setpoints;
+
+volatile typedef struct
+{
+	volatile uint8_t   actualDirection;	//! The actual direction of rotation.
+	volatile uint16_t  duty_cycle;
+	volatile int16_t   calc_rpm;
+	volatile int16_t   abs_position;
+	volatile int16_t   Num_Steps;
+	/* Hall States */
+	//volatile uint8_t   prevHallPattern;
+	volatile uint8_t   currentHallPattern;
+	//volatile uint8_t   nextHallPattern;
+	/* Commutation State */
+	volatile uint8_t   cur_comm_step;
+	volatile uint8_t   prev_comm_step;
+	volatile uint32_t speed_average;
+	volatile uint8_t count;
+}	MOTOR_Status;
+
+// ----------------------------------------------------------------------
+// 	Main BLDC Struct
+// ----------------------------------------------------------------------
+volatile typedef struct BLDCmotor
+{
+	/* Hardware */
+	volatile BLDCMotor_param_t *motor_param;
+	struct pwm_descriptor const *pwm_desc;
+	void *const speedtimer_hw;
+	/* Status */
+	volatile MOTOR_STATE_t motor_state;
+	volatile MOTOR_Status motor_status;
+	/* Measured Values */
+	volatile MOTOR_PHASES_t Iphase_pu;
+	volatile MOTOR_phase_offset_t Voffset_lsb;
+	volatile float32_t VdcBus_pu, VoneByDcBus_pu;
+	/* Motor Flags */
+	volatile TIMERflags_t timerflags;
+	volatile uint8_t regulation_loop_count;
+	/* Controllers */
+	volatile MOTOR_Control_Structs controllers;
+	/* Setpoints */
+	volatile MOTOR_Setpoints motor_setpoints;
+	/* Function Pointers*/
+	volatile readHallSensor readHall;
+} BLDCMotor_t;
+
+
+
+#endif /* BLDC_TYPES_H_ */
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/cmsis/arm_math.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/cmsis/arm_math.h
new file mode 100644
index 0000000..ea9dd26
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/cmsis/arm_math.h
@@ -0,0 +1,7157 @@
+/******************************************************************************
+ * @file     arm_math.h
+ * @brief    Public header file for CMSIS DSP LibraryU
+ * @version  V1.5.3
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+   * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
+   * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
+   * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
+   * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
+   * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+   * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
+   * 
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
+   *
+   * Preprocessor Macros
+   * ------------
+   *
+   * Each library project have different preprocessor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - ARM_MATH_ARMV8MxL:
+   *
+   * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
+   * on Armv8-M Mainline target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+   *
+   * - __DSP_PRESENT:
+   *
+   * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   *
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   *
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+  #include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+  #include "core_armv8mbl.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+  #include "core_armv8mml.h"
+  #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+    #define ARM_MATH_DSP
+  #endif
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31          (0x100)
+#define DELTA_Q15          0x5
+#define INDEX_MASK         0x0000003F
+#ifndef PI
+  #define PI               3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SPACING_Q31     0x400000
+#define TABLE_SPACING_Q15     0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING         0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if   defined ( __CC_ARM )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+#define __SIMD64(addr)        (*(int64_t **) & (addr))
+
+#if !defined (ARM_MATH_DSP)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
+                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
+                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+    q31_t out;
+    uint32_t tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t) (__CLZ( in) - 1));
+    }
+    else
+    {
+      signBits = ((uint32_t) (__CLZ(-in) - 1));
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >> 24);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0U; i < 2U; i++)
+    {
+      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+      tempVal = 0x7FFFFFFFu - tempVal;
+      /*      1.31 with exp 1 */
+      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1U);
+  }
+
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+    q15_t out = 0;
+    uint32_t tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t)(__CLZ( in) - 17));
+    }
+    else
+    {
+      signBits = ((uint32_t)(__CLZ(-in) - 17));
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >>  8);
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0U; i < 2U; i++)
+    {
+      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFFu - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+  }
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if !defined (ARM_MATH_DSP)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
+    q31_t r = 0, s = 0;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+  uint32_t x)
+  {
+    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
+  }
+
+  /*
+   * @brief C custom defined SMMLA for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+  int32_t x,
+  int32_t y,
+  int32_t sum)
+  {
+    return (sum + (int32_t) (((int64_t) x * y) >> 32));
+  }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed.
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in]  S          points to an instance of the Q15 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in]  S          points to an instance of the floating-point FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q15;
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_casd_df1_inst_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q31;
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]   pSrcA  points to the first input matrix structure
+   * @param[in]   pSrcB  points to the second input matrix structure
+   * @param[out]  pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  pSrc   points to the input matrix
+   * @param[in]  scale  scale factor
+   * @param[out] pDst   points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];     /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;          /**< The proportional gain. */
+    float32_t Ki;          /**< The integral gain. */
+    float32_t Kd;          /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] S               points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] S  is an instance of the floating-point PID Control structure
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] S   points to an instance of the Q31 PID Control structure
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] S  points to an instance of the q15 PID Control structure
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;        /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+    const arm_cfft_instance_q15 * S,
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+    const arm_cfft_instance_q31 * S,
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;             /**< length of the real sequence */
+    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+   arm_rfft_fast_instance_f32 * S,
+   uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    float32_t normalize;                 /**< normalizing factor. */
+    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;               /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q31_t normalize;                     /**< normalizing factor. */
+    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q15_t normalize;                     /**< normalizing factor. */
+    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  scale      scale factor to be applied
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q15(
+          q15_t * pSrcA,
+          uint32_t srcALen,
+          q15_t * pSrcB,
+          uint32_t srcBLen,
+          q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc  points to the block of input data.
+   * @param[out] pDst  points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   */
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.   The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S          points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages.
+ */
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize  number of samples to process per call.
+ */
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] S          points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to the state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] S          points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;         /**< step size that control filter coefficient updates. */
+    float32_t energy;     /**< saves previous frame energy. */
+    float32_t x0;         /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
+    q15_t energy;         /**< saves previous frame energy. */
+    q15_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta   input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cos output.
+   */
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal);
+
+
+  /**
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cosine output.
+   */
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] S   is an instance of the floating-point PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] S  points to an instance of the Q31 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31U);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] S   points to an instance of the Q15 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#if defined (ARM_MATH_DSP)
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+  }
+
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+  }
+
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output   rotor reference frame d
+   * @param[out] pIq     points to output   rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+  }
+
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output rotor reference frame d
+   * @param[out] pIq     points to output rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for   Q31 version
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
+   * @param[in]     x  input sample to process
+   * @return y processed output sample.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if (i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if ((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 +  i      * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q31 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (q31_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1U);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q15 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (int32_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (q15_t) (y >> 20);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q7 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+    if (index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (q7_t) (y >> 20);
+     }
+  }
+
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  sin(x).
+   */
+  float32_t arm_sin_f32(
+  float32_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q31_t arm_sin_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q15_t arm_sin_q15(
+  q15_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  cos(x).
+   */
+  float32_t arm_cos_f32(
+  float32_t x);
+
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q31_t arm_cos_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in    input value.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if (in >= 0.0f)
+    {
+
+#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] result     is output pointer
+   * @param[in]  index      is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q31 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q15 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q7 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate.
+  * @param[in]     Y  interpolation coordinate.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11U;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
+    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11U;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
+    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return ((q31_t)(acc << 2));
+  }
+
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return ((q15_t)(acc >> 36));
+  }
+
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return ((q7_t)(acc >> 40));
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if   defined ( __CC_ARM )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("push")         \
+       _Pragma ("O1")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_EXIT \
+       _Pragma ("pop")
+  #else
+    #define LOW_OPTIMIZATION_EXIT
+  #endif
+
+  /* Enter low optimization region - place directly above function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+  #define LOW_OPTIMIZATION_ENTER \
+       __attribute__(( optimize("-O1") ))
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define LOW_OPTIMIZATION_EXIT
+
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef   __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/cmsis/libarm_cortexM4lf_math.a b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/cmsis/libarm_cortexM4lf_math.a
new file mode 100644
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HcmV?d00001

diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/configuration.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/configuration.h
new file mode 100644
index 0000000..5254044
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/configuration.h
@@ -0,0 +1,286 @@
+/*
+ * configuration.h
+ *
+ * Created: 02/08/2021 21:15:49
+ *  Author: Nick-XMG
+ */ 
+
+
+#ifndef CONFIGURATION_H_
+#define CONFIGURATION_H_
+
+// ----------------------------------------------------------------------
+// Header Files
+// ----------------------------------------------------------------------
+#include "atmel_start_pins.h"
+#include "bldc.h"
+#include "interrupts.h"
+#include "hpl_sercom_config.h"
+#include "ADS1299.h"
+#include "hpl_spi_m_dma.h"
+
+// ----------------------------------------------------------------------
+// PWM Timer Initialization
+// ----------------------------------------------------------------------
+static void configure_tcc_pwm(void)
+{	
+	/* TCC0 */
+	hri_tcc_set_WEXCTRL_OTMX_bf(TCC0, 0x02);
+	
+	hri_tcc_set_WAVE_POL0_bit(TCC0);
+	hri_tcc_set_WAVE_POL1_bit(TCC0);
+	hri_tcc_set_WAVE_POL2_bit(TCC0);
+	hri_tcc_set_WAVE_POL3_bit(TCC0);
+	hri_tcc_set_WAVE_POL4_bit(TCC0);
+	hri_tcc_set_WAVE_POL5_bit(TCC0);
+	hri_tcc_write_CC_CC_bf(TCC0, 0, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 1, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 2, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 3, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 4, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 5, 0);
+	hri_tcc_write_PER_reg(TCC0,1200);
+	//hri_tcc_write_CCBUF_CCBUF_bf(TCC0, 0,250);
+	hri_tcc_write_CTRLA_ENABLE_bit(TCC0, 1 << TCC_CTRLA_ENABLE_Pos);	
+	
+	/* TCC1 */
+	hri_tcc_set_WEXCTRL_OTMX_bf(TCC1, 0x02);
+	hri_tcc_write_CC_CC_bf(TCC1, 0, 0);
+	hri_tcc_write_CC_CC_bf(TCC1, 1, 0);
+	hri_tcc_write_CC_CC_bf(TCC1, 2, 0);
+	hri_tcc_write_CC_CC_bf(TCC1, 3, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 4, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 5, 0);
+	//
+	////pwm_set_parameters(&TCC_PWM, 1000, 250);
+	hri_tcc_set_WAVE_POL0_bit(TCC1);
+	hri_tcc_set_WAVE_POL1_bit(TCC1);
+	hri_tcc_set_WAVE_POL2_bit(TCC1);
+	hri_tcc_set_WAVE_POL3_bit(TCC1);
+	hri_tcc_set_WAVE_POL4_bit(TCC1);
+	hri_tcc_set_WAVE_POL5_bit(TCC1);
+	
+	hri_tcc_write_PER_reg(TCC1,1200);
+	//hri_tcc_write_CCBUF_CCBUF_bf(TCC1, 0, 250);
+	hri_tcc_clear_CTRLA_ENABLE_bit(TCC1);
+	hri_tcc_write_CTRLA_MSYNC_bit(TCC1, true);
+	//hri_tcc_write_CTRLA_ENABLE_bit(TCC1, 1 << TCC_CTRLA_ENABLE_Pos); /* Enable: enabled */
+	
+	//pwm_register_callback(&PWM_0, PWM_PERIOD_CB, pwm_cb);
+	pwm_enable(&PWM_0);
+	pwm_enable(&PWM_1);
+
+}
+
+// ----------------------------------------------------------------------
+// ADC DMA Initialization
+// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
+// ----------------------------------------------------------------------
+
+//#define CONF_ADC_0_ADC_RES_READY_CHANNEL 4U
+#define CONF_ADC_1_ADC_RES_READY_CHANNEL 3U
+//#define CONF_ADC_0_SEQUENCER_CHANNEL	 6U
+#define CONF_ADC_1_SEQUENCER_CHANNEL	 4U
+
+const uint32_t adc0_seq_regs[4]	= {0};
+const uint32_t adc1_seq_regs[4]	= {0x0089, 0x0088, 0x0087, 0x0086}; /* Differential */
+//const uint32_t adc1_seq_regs[4]	= {0x1807, 0x1806, 0x1809, 0x1808}; /* Single Ended */
+volatile int16_t adc0_res[4]	= {0};
+volatile int16_t adc1_res[4]	= {0};
+
+struct _dma_resource *adc_sram_dma_resource;
+struct _dma_resource *adc_dmac_sequence_resource;
+
+
+
+static void adc_dmac_sequence_init()
+{
+	/* Configure the DMAC source address, destination address,
+	 * next descriptor address, data count and Enable the DMAC Channel 
+	 */
+	_dma_set_source_address(CONF_ADC_1_SEQUENCER_CHANNEL, (const void *)adc1_seq_regs);
+	_dma_set_destination_address(CONF_ADC_1_SEQUENCER_CHANNEL, (const void *)&ADC1->DSEQDATA.reg);
+	_dma_set_data_amount(CONF_ADC_1_SEQUENCER_CHANNEL, 4);
+	_dma_set_next_descriptor(CONF_ADC_1_SEQUENCER_CHANNEL, CONF_ADC_1_SEQUENCER_CHANNEL);
+	_dma_enable_transaction(CONF_ADC_1_SEQUENCER_CHANNEL, false);
+	hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[CONF_ADC_1_SEQUENCER_CHANNEL], 0x01);	//Suspend
+}
+
+static void adc_sram_dmac_init()
+{
+	_dma_set_source_address(CONF_ADC_1_ADC_RES_READY_CHANNEL, (const void *)&ADC1->RESULT.reg);
+	_dma_set_destination_address(CONF_ADC_1_ADC_RES_READY_CHANNEL, (const void *)adc1_res);
+	_dma_set_data_amount(CONF_ADC_1_ADC_RES_READY_CHANNEL, 4);
+	_dma_set_irq_state(CONF_ADC_1_ADC_RES_READY_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
+	_dma_get_channel_resource(&adc_sram_dma_resource, CONF_ADC_1_ADC_RES_READY_CHANNEL);
+	adc_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback;
+	_dma_set_next_descriptor(CONF_ADC_1_ADC_RES_READY_CHANNEL, CONF_ADC_1_ADC_RES_READY_CHANNEL); /*?????*/
+	_dma_enable_transaction(CONF_ADC_1_ADC_RES_READY_CHANNEL, false);
+}
+
+
+// ----------------------------------------------------------------------
+// ADC Initialization
+// ----------------------------------------------------------------------
+static void adc_init_dma_descriptors(void)
+{
+	adc_sram_dmac_init();
+	adc_dmac_sequence_init();
+	hri_adc_set_DSEQCTRL_INPUTCTRL_bit(ADC1);
+	hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC1);
+}
+
+
+// ----------------------------------------------------------------------
+// SPI DMA communication between Master & Slave Board
+// ----------------------------------------------------------------------
+
+#define MASTER_BUFFER_SIZE	64
+#define MASTER_BUFFER_SIZE_LONG	MASTER_BUFFER_SIZE/4
+
+/* DMA channel Descriptor */
+extern DmacDescriptor _descriptor_section[DMAC_CH_NUM];
+extern DmacDescriptor _write_back_section[DMAC_CH_NUM];
+
+static void boardToBoardTransferInit(void)
+{
+	struct io_descriptor *io;
+	spi_m_dma_get_io_descriptor(&SPI_1_MSIF, &io);
+	//spi_m_dma_register_callback(&SPI_1_MSIF, SPI_M_DMA_CB_RX_DONE, b2bTransferComplete_cb);
+	//SERCOM4->SPI.CTRLC.bit.DATA32B = true;
+	//SERCOM1->SPI.LENGTH.bit.LENEN = true;
+	//SERCOM1->SPI.LENGTH.bit.LEN = 64;
+	
+	SERCOM1->SPI.CTRLC.bit.ICSPACE = 4;
+	SERCOM1->SPI.CTRLC.bit.DATA32B= true;
+	gpio_set_pin_level(SPI1_CS, true);
+	spi_m_dma_enable(&SPI_1_MSIF);
+}
+
+static void spi_master_init_dma_descriptors()
+{
+	_dma_set_source_address(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL,
+							(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
+	_dma_set_destination_address(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, &QSPI_tx_buffer[16]);
+	_dma_set_data_amount(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, MASTER_BUFFER_SIZE_LONG);
+	_dma_set_next_descriptor(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL);
+	
+	
+	_dma_set_source_address(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, &QSPI_rx_buffer[16]);
+	_dma_set_destination_address(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL,
+								(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
+	_dma_set_data_amount(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, MASTER_BUFFER_SIZE_LONG);
+	_dma_set_next_descriptor(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL);
+	
+	
+	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL]);
+	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL]);
+	
+	
+	/* callback */
+	//struct _dma_resource *resource_rx, *resource_tx;
+	//_dma_get_channel_resource(&resource_rx, CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL);
+	//_dma_get_channel_resource(&resource_tx, CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL);
+	//resource_rx->dma_cb.transfer_done = spi_slave_rx_complete_cb;
+	//resource_tx->dma_cb.transfer_done = b2bTransferComplete_cb;
+
+	/* Enable DMA transfer complete interrupt */
+	//_dma_set_irq_state(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, DMA_TRANSFER_COMPLETE_CB, true);
+	
+}
+
+// ----------------------------------------------------------------------
+// SPI DMA communication ADS1299
+// ----------------------------------------------------------------------
+//
+
+#define CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL	2U
+#define CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL	5U
+
+
+/*  219 Bites total 
+* Number format is 24 bit
+* 7 (uint_32) - 24 bits
+*/
+extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
+//
+static void spi_ads1299_init_dma_descriptors()
+{
+	_dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL,
+						   (uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg));
+	_dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL,  &_ads1299_channel_data[0]);
+	_dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, ADS_BUFFER_SIZE);
+	_dma_set_next_descriptor(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL);
+	
+	
+	_dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, &ads1299_buffer[0]);
+	_dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL,
+							(uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg));
+	_dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, ADS_BUFFER_SIZE);
+	_dma_set_next_descriptor(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL);
+	
+	
+	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL]);
+	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL]);
+	
+	
+	/* callback */
+	struct _dma_resource *resource_rx, *resource_tx;
+	_dma_get_channel_resource(&resource_rx, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL);
+	_dma_get_channel_resource(&resource_tx, CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL);
+	resource_rx->dma_cb.transfer_done = ADS1299_Transfer_Complete_cb;
+	//resource_rx->dma_cb.error = ADS1299_Transfer_error_cb;
+
+	/* Enable DMA transfer complete interrupt */
+	_dma_set_irq_state(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
+	//_dma_set_irq_state(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, DMA_TRANSFER_ERROR_CB, true);
+	
+
+	
+	
+}
+
+// ----------------------------------------------------------------------
+// Overall DMA Init
+// ----------------------------------------------------------------------
+
+/* Peripherals should be configured before interacting with dma
+* CH0 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin
+* CH1 - SERCOM5_RX(SPI3) - Angle Sensor
+* CH2 - SERCOM2_RX(SPI2) - Expansion IF (EMG) - Beat Transfer Event Drives CS Pin
+* CH3 - ADC1 - Result Ready
+* CH4 - ADC1 - Sequencer - Triggered by TCC0 overflow event
+* CH5 - SERCOM2_TX(SPI2) - Expansion IF (EMG)
+* CH6 - SERCOM5_TX(SPI3) - Angle Sensor
+* CH7 - SERCOM1_TX(SPI1) - Master-Slave IF
+*/
+
+static void init_dma(void)
+{
+	spi_master_init_dma_descriptors();
+	spi_ads1299_init_dma_descriptors();
+	adc_init_dma_descriptors();
+	
+}
+
+
+// ----------------------------------------------------------------------
+// Overall DMA Init
+// ----------------------------------------------------------------------
+
+/* Peripherals should be configured before interacting with dma
+* CH0 - QSPI_RX - For ECAT DMA Mode - Currently Disabled in ASTART
+* CH1 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin
+* CH2 - SERCOM2_RX(SPI2) - Expansion IF (EMG) - Beat Transfer Event Drives CS Pin
+* CH3 - SERCOM5_RX(SPI3) - Angle Sensor
+* CH4 - ADC0 - Result Ready (Unused on master) - Currently Disabled in ASTART
+* CH5 - ADC1 - Result Ready
+* CH6 - ADC0 - Sequencer (Unused on master) - Currently Disabled in ASTART
+* CH7 - ADC1 - Sequencer - Triggered by TCC0 overflow event
+* CH8 - SERCOM2_TX(SPI2) - Expansion IF (EMG)
+* CH9 - SERCOM5_TX(SPI3) - Angle Sensor
+* CH10 - SERCOM1_TX(SPI1) - Master-Slave IF
+* CH11 - QSPI_TX - For ECAT DMA Mode - Currently Disabled in ASTART
+*/
+
+#endif /* CONFIGURATION_H_ */
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/control.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/control.h
new file mode 100644
index 0000000..ca1adaa
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/control.h
@@ -0,0 +1,262 @@
+/*
+ * pi.h
+ *
+ * Created: 01/02/2021 21:36:11
+ *  Author: Nick-XMG
+ */ 
+#ifndef CONTROL_H_
+#define CONTROL_H_
+
+// ----------------------------------------------------------------------
+// 	history
+// ----------------------------------------------------------------------
+// 	01.02.2021 - initial Revision
+
+// ----------------------------------------------------------------------
+// 	header files
+// ----------------------------------------------------------------------
+#include "arm_math.h"
+#include "atmel_start.h"
+#include "utilities.h"
+// ----------------------------------------------------------------------
+// 	#defines
+// ----------------------------------------------------------------------
+// ----------------------------------------------------------------------
+// 	global variables
+// ----------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+	#endif
+	
+/* PI Structure */
+typedef volatile struct
+{
+	volatile float32_t Kp;          // the proportional gain for the PI controller
+	volatile float32_t Ki;          // the integral gain for the PI controller
+
+	volatile float32_t Ref_pu;      // the reference value [pu]
+	volatile float32_t Fbk_pu;      // the feedback value [pu]
+	volatile float32_t Ff_pu;       // the feedForward value [pu]
+
+	volatile float32_t OutMin_pu;   // the saturation low limit for the controller output [pu]
+	volatile float32_t OutMax_pu;   // the saturation high limit for the controller output [pu]
+	volatile float32_t Out_pu;      // the controller output [pu]
+
+	volatile float32_t Ui;          // the integrator value for the PI controller
+	volatile float32_t error;          // the integrator value for the PI controller
+	volatile bool SatFlag;   // flag to signal controller saturation
+} PI_t;
+
+/* PID Structure */
+typedef volatile struct
+{
+	volatile float32_t  Kp;                //!< the proportional gain for the PID controller
+	volatile float32_t  Ki;                //!< the integral gain for the PID controller
+	volatile float32_t  Kd;                //!< the derivative gain for the PID controller
+
+	volatile float32_t  Ref_pu;          //!< the reference input value
+	volatile float32_t  Fbk_pu;        //!< the feedback input value
+	volatile float32_t  Ff_pu;         //!< the feedforward input value
+	
+	volatile float32_t  OutMin_pu;            //!< the minimum output value allowed for the PID controller
+	volatile float32_t  OutMax_pu;            //!< the maximum output value allowed for the PID controller
+	volatile float32_t	Out_pu;      // the controller output [pu]
+	
+	volatile float32_t  Ui;                //!< the integrator start value for the PID controller
+	volatile float32_t  Ud;
+	volatile float32_t error;          // the integrator value for the PI controller
+	
+	//FILTER_FO_Handle derFilterHandle;   //!< the derivative filter handle
+	//FILTER_FO_Obj    derFilter;         //!< the derivative filter object
+} PID_t;
+
+volatile typedef struct
+{
+	volatile PI_t	Pi_Idc;
+	volatile PID_t	Pid_Speed;
+	volatile PI_t	Pi_Pos;
+}	MOTOR_Control_Structs;
+
+// ----------------------------------------------------------------------
+// 	functions
+// ----------------------------------------------------------------------
+// function to set default values for the object
+
+//inline float32_t clamp(const float32_t d, const float32_t min, const float32_t max) {
+	//const float32_t t = d < min ? min : d;
+	//return t > max ? max : t;
+//}
+
+
+static inline void PI_objectInit(volatile PI_t *pPi_obj)
+{
+	PI_t *obj = (PI_t *)pPi_obj;
+
+	// Function initializes the object with default values
+	//fix16_t Kp = fix16_from_float32_t(1.0);
+	obj->Kp			= 0.0f;
+	obj->Ki			= 0.0f;
+	obj->Fbk_pu		= 0.0f;
+	obj->Ref_pu		= 0.0f;
+	obj->Ff_pu		= 0.0f;
+	obj->Out_pu		= 0.0f;
+	obj->OutMax_pu	= 0.0f;
+	obj->OutMin_pu	= 0.0f;
+	obj->Ui			= 0.0f;
+	obj->SatFlag	= false;
+}
+
+static inline void PID_objectInit(volatile PID_t *pPiD_obj)
+{
+	PID_t *obj = (PID_t *)pPiD_obj;
+
+	// Function initializes the object with default values
+	//fix16_t Kp = fix16_from_float32_t(1.0);
+	obj->Kp			= 0.0f;
+	obj->Ki			= 0.0f;
+	obj->Kd			= 0.0f;
+	obj->Fbk_pu		= 0.0f;
+	obj->Ref_pu		= 0.0f;
+	obj->Ff_pu		= 0.0f;
+	obj->Out_pu		= 0.0f;
+	obj->OutMax_pu	= 0.0f;
+	obj->OutMin_pu	= 0.0f;
+	obj->Ui			= 0.0f;
+	obj->Ud			= 0.0f;
+}
+
+// ----------------------------------------------------------------------
+//	PI Calculation
+// ----------------------------------------------------------------------
+static inline void PI_run_series(volatile PI_t *pPi_obj)
+{
+	PI_t *obj = (PI_t *)pPi_obj;
+	volatile float32_t Up;
+
+	// Compute the controller error
+	obj->error = obj->Ref_pu - obj->Fbk_pu;
+
+	// Compute the proportional term
+	Up = obj->Kp *obj->error;
+
+	// Compute the integral term in series form and saturate	
+	obj->Ui = f_clamp((obj->Ui + (obj->Ki * Up)), obj->OutMin_pu, obj->OutMax_pu);
+
+	// Saturate the output
+ 	obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);
+}
+
+static inline void PI_run_parallel(volatile PI_t *pPi_obj)
+{
+	PI_t *obj = (PI_t *)pPi_obj;
+	volatile float32_t Up;
+	
+	// Compute the controller error
+	obj->error = obj->Ref_pu - obj->Fbk_pu;
+	
+	// Compute the proportional term
+	Up = obj->Kp * obj->error;
+	
+	// Compute the integral term in parallel form and saturate
+	obj->Ui = f_clamp((obj->Ui + (obj->Ki * obj->error)), obj->OutMin_pu, obj->OutMax_pu);
+	
+	obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);  // Saturate the output
+} // end of PI_run_parallel() function
+
+
+// ----------------------------------------------------------------------
+//	PID Calculation
+// ----------------------------------------------------------------------
+static inline void PID_run_series(volatile PID_t *pPid_obj)
+{
+	PID_t *obj = (PID_t *)pPid_obj;
+	volatile float32_t Up, Ud_tmp;
+	
+	// Compute the controller error
+	obj->error = obj->Ref_pu - obj->Fbk_pu;
+	
+	// Compute the proportional term
+	Up = obj->Kp * obj->error;
+	
+	if(obj->Ki>0.0f){
+		// Compute the integral term in parallel form and saturate
+		obj->Ui = f_clamp((obj->Ui + (obj->Ki * Up)), obj->OutMin_pu, obj->OutMax_pu);
+	}
+	
+	Ud_tmp = obj->Kd * obj->Ui; // Compute the derivative term
+	
+	obj->Ud = Ud_tmp; // Replace with filter
+
+	obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ud + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);  // Saturate the output
+	
+}
+
+static inline void PID_run_parallel(volatile PID_t *pPid_obj)
+{
+	PID_t *obj = (PID_t *)pPid_obj;
+	volatile float32_t Up, Ud_tmp;
+
+	
+	// Compute the controller error
+	obj->error = obj->Ref_pu - obj->Fbk_pu;
+	
+	// Compute the proportional term
+	Up = obj->Kp * obj->error;
+	
+	if(obj->Ki>0.0f){
+		// Compute the integral term in parallel form and saturate
+		obj->Ui = f_clamp((obj->Ui + (obj->Ki * obj->error)), obj->OutMin_pu, obj->OutMax_pu);
+	}
+	
+	Ud_tmp = obj->Kd * obj->error;   // Compute the derivative term
+
+	obj->Ud = Ud_tmp; // Replace with filter
+
+	obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ud + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);  // Saturate the output
+}
+
+
+// ----------------------------------------------------------------------
+// Calculate Current Parameters
+// ----------------------------------------------------------------------
+
+static inline float32_t PI_calcKp(const float32_t Ls_H, const float32_t deviceCurrent_A, const float32_t deviceVoltage_V,
+const float32_t deviceCtrlPeriode_Sec)
+{
+	// calculation is based on "Betragsoptimum"
+	// Kp = Ls/(2*tau)
+	float32_t x1;
+	float32_t y1;
+	float32_t Kp;
+
+	// multiplication with deviceCurrent_A is to get per unit values
+	x1 = (float32_t)(Ls_H * deviceCurrent_A);
+
+	y1 = (float32_t)(2.0f * deviceCtrlPeriode_Sec);
+
+	// multiplication with deviceVoltage_V is to get per unit values
+	y1 = (float32_t)(y1 * deviceVoltage_V);
+
+	Kp = (x1 / y1);
+	return Kp;
+}
+
+static inline float32_t PI_calcKi(const float32_t Rs_Ohm, const float32_t Ls_H, const float32_t deviceCtrlPeriode_Sec)
+{
+	// calculation is based on "TI - MotorWare's documentation"
+	float32_t RsByLs = (float32_t)(Rs_Ohm / Ls_H);
+	float32_t Ki = RsByLs * deviceCtrlPeriode_Sec;
+	//fix16_t Ki = 0;
+	return Ki;
+}
+
+// ----------------------------------------------------------------------
+// 	end of file
+// ----------------------------------------------------------------------
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+#endif /* BLDC_PI_H_ */
+
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/driver_init.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/driver_init.c
new file mode 100644
index 0000000..037d81d
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/driver_init.c
@@ -0,0 +1,833 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+
+#include "driver_init.h"
+#include <peripheral_clk_config.h>
+#include <utils.h>
+#include <hal_init.h>
+
+#include <hpl_adc_base.h>
+#include <hpl_adc_base.h>
+
+struct spi_m_sync_descriptor SPI_2;
+struct spi_m_sync_descriptor SPI_3;
+
+struct adc_sync_descriptor ADC_0;
+
+struct adc_sync_descriptor ADC_1;
+
+struct qspi_dma_descriptor ECAT_QSPI;
+
+struct i2c_m_async_desc I2C_0;
+
+struct spi_m_dma_descriptor SPI_1_MSIF;
+
+struct pwm_descriptor PWM_0;
+
+struct pwm_descriptor PWM_1;
+
+void ADC_0_PORT_init(void)
+{
+}
+
+void ADC_0_CLOCK_init(void)
+{
+	hri_mclk_set_APBDMASK_ADC0_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void ADC_0_init(void)
+{
+	ADC_0_CLOCK_init();
+	ADC_0_PORT_init();
+	adc_sync_init(&ADC_0, ADC0, (void *)NULL);
+}
+
+void ADC_1_PORT_init(void)
+{
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(half_VREF, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(half_VREF, PINMUX_PB08B_ADC1_AIN0);
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(M1_IA, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(M1_IA, PINMUX_PB04B_ADC1_AIN6);
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(M1_IB, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(M1_IB, PINMUX_PB05B_ADC1_AIN7);
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(M2_IA, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(M2_IA, PINMUX_PB06B_ADC1_AIN8);
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(M2_IB, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(M2_IB, PINMUX_PB07B_ADC1_AIN9);
+}
+
+void ADC_1_CLOCK_init(void)
+{
+	hri_mclk_set_APBDMASK_ADC1_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, ADC1_GCLK_ID, CONF_GCLK_ADC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void ADC_1_init(void)
+{
+	ADC_1_CLOCK_init();
+	ADC_1_PORT_init();
+	adc_sync_init(&ADC_1, ADC1, (void *)NULL);
+}
+
+void DIGITAL_GLUE_LOGIC_0_PORT_init(void)
+{
+
+	gpio_set_pin_function(M1_HALLA, PINMUX_PA04N_CCL_IN0);
+
+	gpio_set_pin_function(M1_HALLB, PINMUX_PA05N_CCL_IN1);
+
+	gpio_set_pin_function(M1_HALLC, PINMUX_PA06N_CCL_IN2);
+
+	gpio_set_pin_function(M2_HALLA, PINMUX_PA22N_CCL_IN6);
+
+	gpio_set_pin_function(M2_HALLB, PINMUX_PA23N_CCL_IN7);
+
+	gpio_set_pin_function(M2_HALLC, PINMUX_PA24N_CCL_IN8);
+}
+
+void DIGITAL_GLUE_LOGIC_0_CLOCK_init(void)
+{
+	hri_mclk_set_APBCMASK_CCL_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, CCL_GCLK_ID, CONF_GCLK_CCL_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void DIGITAL_GLUE_LOGIC_0_init(void)
+{
+	DIGITAL_GLUE_LOGIC_0_CLOCK_init();
+	custom_logic_init();
+	DIGITAL_GLUE_LOGIC_0_PORT_init();
+}
+
+void EXTERNAL_IRQ_0_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_mclk_set_APBAMASK_EIC_bit(MCLK);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(ADS_DATA_RDY, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(ADS_DATA_RDY,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ADS_DATA_RDY, PINMUX_PA02A_EIC_EXTINT2);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(ECAT_SYNC, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(ECAT_SYNC,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_SYNC, PINMUX_PA07A_EIC_EXTINT7);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(M1_RST_Bar, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(M1_RST_Bar,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(M1_RST_Bar, PINMUX_PB30A_EIC_EXTINT14);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(M2_RST_Bar, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(M2_RST_Bar,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(M2_RST_Bar, PINMUX_PB31A_EIC_EXTINT15);
+
+	ext_irq_init();
+}
+
+void EVENT_SYSTEM_0_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_1, CONF_GCLK_EVSYS_CHANNEL_1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_2, CONF_GCLK_EVSYS_CHANNEL_2_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_3, CONF_GCLK_EVSYS_CHANNEL_3_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_5, CONF_GCLK_EVSYS_CHANNEL_5_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_6, CONF_GCLK_EVSYS_CHANNEL_6_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_7, CONF_GCLK_EVSYS_CHANNEL_7_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_8, CONF_GCLK_EVSYS_CHANNEL_8_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_11, CONF_GCLK_EVSYS_CHANNEL_11_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);
+
+	event_system_init();
+}
+
+void ECAT_QSPI_PORT_init(void)
+{
+
+	// Set pin direction to input
+	gpio_set_pin_direction(ECAT_QSPI_CS, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(ECAT_QSPI_CS,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_QSPI_CS, PINMUX_PB11H_QSPI_CS);
+
+	gpio_set_pin_direction(ECAT_QSPI_MOSI,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(ECAT_QSPI_MOSI,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(ECAT_QSPI_MOSI,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_QSPI_MOSI,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PA08H_QSPI_DATA0"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA08H_QSPI_DATA0);
+
+	gpio_set_pin_direction(ECAT_QSPI_MISO,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(ECAT_QSPI_MISO,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(ECAT_QSPI_MISO,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_QSPI_MISO,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PA09H_QSPI_DATA1"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA09H_QSPI_DATA1);
+
+	gpio_set_pin_direction(ECAT_QSPI_DATA2,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(ECAT_QSPI_DATA2,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(ECAT_QSPI_DATA2,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_QSPI_DATA2,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PA10H_QSPI_DATA2"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA10H_QSPI_DATA2);
+
+	gpio_set_pin_direction(ECAT_QSPI_DATA3,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(ECAT_QSPI_DATA3,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(ECAT_QSPI_DATA3,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_QSPI_DATA3,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PA11H_QSPI_DATA3"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA11H_QSPI_DATA3);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(ECAT_QSPI_SCK, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(ECAT_QSPI_SCK,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_QSPI_SCK, PINMUX_PB10H_QSPI_SCK);
+}
+
+void ECAT_QSPI_CLOCK_init(void)
+{
+	hri_mclk_set_AHBMASK_QSPI_bit(MCLK);
+	hri_mclk_set_AHBMASK_QSPI_2X_bit(MCLK);
+	hri_mclk_set_APBCMASK_QSPI_bit(MCLK);
+}
+
+void ECAT_QSPI_init(void)
+{
+	ECAT_QSPI_CLOCK_init();
+	qspi_dma_init(&ECAT_QSPI, QSPI);
+	ECAT_QSPI_PORT_init();
+}
+
+void I2C_0_PORT_init(void)
+{
+}
+
+void I2C_0_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK);
+}
+
+void I2C_0_init(void)
+{
+	I2C_0_CLOCK_init();
+	i2c_m_async_init(&I2C_0, SERCOM0);
+	I2C_0_PORT_init();
+}
+
+void SPI_1_MSIF_PORT_init(void)
+{
+
+	gpio_set_pin_level(SPI1_MOSI,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI1_MOSI, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI1_MOSI, PINMUX_PA00D_SERCOM1_PAD0);
+
+	gpio_set_pin_level(SPI1_SCK,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI1_SCK, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI1_SCK, PINMUX_PA01D_SERCOM1_PAD1);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(SPI1_MISO, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(SPI1_MISO,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(SPI1_MISO, PINMUX_PB23C_SERCOM1_PAD3);
+}
+
+void SPI_1_MSIF_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBAMASK_SERCOM1_bit(MCLK);
+}
+
+void SPI_1_MSIF_init(void)
+{
+	SPI_1_MSIF_CLOCK_init();
+	spi_m_dma_init(&SPI_1_MSIF, SERCOM1);
+	SPI_1_MSIF_PORT_init();
+}
+
+void SPI_2_PORT_init(void)
+{
+
+	gpio_set_pin_level(SPI2_MOSI,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI2_MOSI, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI2_MOSI, PINMUX_PA12C_SERCOM2_PAD0);
+
+	gpio_set_pin_level(SPI2_SCK,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI2_SCK, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI2_SCK, PINMUX_PA13C_SERCOM2_PAD1);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(SPI2_MISO, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(SPI2_MISO,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(SPI2_MISO, PINMUX_PA15C_SERCOM2_PAD3);
+}
+
+void SPI_2_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
+}
+
+void SPI_2_init(void)
+{
+	SPI_2_CLOCK_init();
+	spi_m_sync_init(&SPI_2, SERCOM2);
+	SPI_2_PORT_init();
+}
+
+void SPI_3_PORT_init(void)
+{
+
+	gpio_set_pin_level(SPI3_MOSI,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI3_MOSI, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI3_MOSI, PINMUX_PB02D_SERCOM5_PAD0);
+
+	gpio_set_pin_level(SPI3_SCK,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI3_SCK, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI3_SCK, PINMUX_PB03D_SERCOM5_PAD1);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(SPI3_MISO, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(SPI3_MISO,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(SPI3_MISO, PINMUX_PB01D_SERCOM5_PAD3);
+}
+
+void SPI_3_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_CORE, CONF_GCLK_SERCOM5_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_SLOW, CONF_GCLK_SERCOM5_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBDMASK_SERCOM5_bit(MCLK);
+}
+
+void SPI_3_init(void)
+{
+	SPI_3_CLOCK_init();
+	spi_m_sync_init(&SPI_3, SERCOM5);
+	SPI_3_PORT_init();
+}
+
+void TIMER_0_CLOCK_init(void)
+{
+	hri_mclk_set_APBAMASK_TC0_bit(MCLK);
+
+	hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void TIMER_SPARE_CLOCK_init(void)
+{
+	hri_mclk_set_APBAMASK_TC1_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TC1_GCLK_ID, CONF_GCLK_TC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void TC_SPEED_M1_CLOCK_init(void)
+{
+	hri_mclk_set_APBBMASK_TC2_bit(MCLK);
+
+	hri_mclk_set_APBBMASK_TC3_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TC2_GCLK_ID, CONF_GCLK_TC2_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void TC_SPEED_M2_CLOCK_init(void)
+{
+	hri_mclk_set_APBCMASK_TC4_bit(MCLK);
+
+	hri_mclk_set_APBCMASK_TC5_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TC4_GCLK_ID, CONF_GCLK_TC4_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void PWM_0_PORT_init(void)
+{
+
+	gpio_set_pin_function(M1_PWMA, PINMUX_PB12G_TCC0_WO0);
+
+	gpio_set_pin_function(M1_PWMB, PINMUX_PB13G_TCC0_WO1);
+
+	gpio_set_pin_function(M1_PWMC, PINMUX_PB14G_TCC0_WO2);
+
+	gpio_set_pin_function(M1_ENA, PINMUX_PB15G_TCC0_WO3);
+
+	gpio_set_pin_function(M1_ENB, PINMUX_PB16G_TCC0_WO4);
+
+	gpio_set_pin_function(M1_ENC, PINMUX_PB17G_TCC0_WO5);
+}
+
+void PWM_0_CLOCK_init(void)
+{
+
+	hri_mclk_set_APBBMASK_TCC0_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, CONF_GCLK_TCC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void PWM_0_init(void)
+{
+	PWM_0_CLOCK_init();
+	PWM_0_PORT_init();
+	pwm_init(&PWM_0, TCC0, _tcc_get_pwm());
+}
+
+void PWM_1_PORT_init(void)
+{
+
+	gpio_set_pin_function(M2_PWMA, PINMUX_PA16F_TCC1_WO0);
+
+	gpio_set_pin_function(M2_PWMB, PINMUX_PA17F_TCC1_WO1);
+
+	gpio_set_pin_function(M2_PWMC, PINMUX_PA18F_TCC1_WO2);
+
+	gpio_set_pin_function(M2_ENA, PINMUX_PA19F_TCC1_WO3);
+
+	gpio_set_pin_function(M2_ENB, PINMUX_PA20F_TCC1_WO4);
+
+	gpio_set_pin_function(M2_ENC, PINMUX_PA21F_TCC1_WO5);
+}
+
+void PWM_1_CLOCK_init(void)
+{
+
+	hri_mclk_set_APBBMASK_TCC1_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TCC1_GCLK_ID, CONF_GCLK_TCC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void PWM_1_init(void)
+{
+	PWM_1_CLOCK_init();
+	PWM_1_PORT_init();
+	pwm_init(&PWM_1, TCC1, _tcc_get_pwm());
+}
+
+void system_init(void)
+{
+	init_mcu();
+
+	// GPIO on PA03
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(ANAREF_3V, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(ANAREF_3V, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PA14
+
+	gpio_set_pin_level(SPI2_SS,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   true);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI2_SS, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI2_SS, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PA25
+
+	gpio_set_pin_level(M1_RST,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(M1_RST, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(M1_RST, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PA27
+
+	gpio_set_pin_level(M2_RST,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(M2_RST, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(M2_RST, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PB00
+
+	gpio_set_pin_level(SPI3_SS,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   true);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI3_SS, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI3_SS, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PB09
+
+	gpio_set_pin_level(ADS_RESET,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   true);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(ADS_RESET, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(ADS_RESET, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PB22
+
+	gpio_set_pin_level(SPI1_CS,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   true);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI1_CS, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI1_CS, GPIO_PIN_FUNCTION_OFF);
+
+	ADC_0_init();
+
+	ADC_1_init();
+
+	DIGITAL_GLUE_LOGIC_0_init();
+
+	EXTERNAL_IRQ_0_init();
+
+	EVENT_SYSTEM_0_init();
+
+	ECAT_QSPI_init();
+
+	I2C_0_init();
+
+	SPI_1_MSIF_init();
+
+	SPI_2_init();
+
+	SPI_3_init();
+
+	TIMER_0_CLOCK_init();
+
+	TIMER_0_init();
+
+	TIMER_SPARE_CLOCK_init();
+
+	TIMER_SPARE_init();
+
+	TC_SPEED_M1_CLOCK_init();
+
+	TC_SPEED_M1_init();
+
+	TC_SPEED_M2_CLOCK_init();
+
+	TC_SPEED_M2_init();
+
+	PWM_0_init();
+
+	PWM_1_init();
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/driver_init.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/driver_init.h
new file mode 100644
index 0000000..bab8991
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/driver_init.h
@@ -0,0 +1,133 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef DRIVER_INIT_INCLUDED
+#define DRIVER_INIT_INCLUDED
+
+#include "atmel_start_pins.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <hal_atomic.h>
+#include <hal_delay.h>
+#include <hal_gpio.h>
+#include <hal_init.h>
+#include <hal_io.h>
+#include <hal_sleep.h>
+
+#include <hal_adc_sync.h>
+
+#include <hal_adc_sync.h>
+
+#include <hal_custom_logic.h>
+
+#include <hal_ext_irq.h>
+
+#include <hal_evsys.h>
+
+#include <hal_qspi_dma.h>
+
+#include <hal_i2c_m_async.h>
+
+#include <hal_spi_m_dma.h>
+#include <hal_spi_m_sync.h>
+#include <hal_spi_m_sync.h>
+#include <tc_lite.h>
+#include <tc_lite.h>
+#include <tc_lite.h>
+#include <tc_lite.h>
+
+#include <hal_pwm.h>
+#include <hpl_tcc.h>
+
+#include <hal_pwm.h>
+#include <hpl_tcc.h>
+
+extern struct adc_sync_descriptor ADC_0;
+
+extern struct adc_sync_descriptor ADC_1;
+
+extern struct qspi_dma_descriptor ECAT_QSPI;
+
+extern struct i2c_m_async_desc I2C_0;
+
+extern struct spi_m_dma_descriptor  SPI_1_MSIF;
+extern struct spi_m_sync_descriptor SPI_2;
+extern struct spi_m_sync_descriptor SPI_3;
+
+extern struct pwm_descriptor PWM_0;
+
+extern struct pwm_descriptor PWM_1;
+
+void ADC_0_PORT_init(void);
+void ADC_0_CLOCK_init(void);
+void ADC_0_init(void);
+
+void ADC_1_PORT_init(void);
+void ADC_1_CLOCK_init(void);
+void ADC_1_init(void);
+
+void DIGITAL_GLUE_LOGIC_0_PORT_init(void);
+void DIGITAL_GLUE_LOGIC_0_CLOCK_init(void);
+void DIGITAL_GLUE_LOGIC_0_init(void);
+
+void ECAT_QSPI_PORT_init(void);
+void ECAT_QSPI_CLOCK_init(void);
+void ECAT_QSPI_init(void);
+
+void I2C_0_PORT_init(void);
+void I2C_0_CLOCK_init(void);
+void I2C_0_init(void);
+
+void SPI_1_MSIF_PORT_init(void);
+void SPI_1_MSIF_CLOCK_init(void);
+void SPI_1_MSIF_init(void);
+
+void SPI_2_PORT_init(void);
+void SPI_2_CLOCK_init(void);
+void SPI_2_init(void);
+
+void SPI_3_PORT_init(void);
+void SPI_3_CLOCK_init(void);
+void SPI_3_init(void);
+
+void TIMER_0_CLOCK_init(void);
+
+int8_t TIMER_0_init(void);
+
+void TIMER_SPARE_CLOCK_init(void);
+
+int8_t TIMER_SPARE_init(void);
+
+void TC_SPEED_M1_CLOCK_init(void);
+
+int8_t TC_SPEED_M1_init(void);
+
+void TC_SPEED_M2_CLOCK_init(void);
+
+int8_t TC_SPEED_M2_init(void);
+
+void PWM_0_PORT_init(void);
+void PWM_0_CLOCK_init(void);
+void PWM_0_init(void);
+
+void PWM_1_PORT_init(void);
+void PWM_1_CLOCK_init(void);
+void PWM_1_init(void);
+
+/**
+ * \brief Perform system initialization, initialize pins and clocks for
+ * peripherals
+ */
+void system_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif // DRIVER_INIT_INCLUDED
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/examples/driver_examples.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/examples/driver_examples.c
new file mode 100644
index 0000000..2adbb38
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/examples/driver_examples.c
@@ -0,0 +1,196 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+
+#include "driver_examples.h"
+#include "driver_init.h"
+#include "utils.h"
+
+/**
+ * Example of using ADC_0 to generate waveform.
+ */
+void ADC_0_example(void)
+{
+	uint8_t buffer[2];
+
+	adc_sync_enable_channel(&ADC_0, 0);
+
+	while (1) {
+		adc_sync_read_channel(&ADC_0, 0, buffer, 2);
+	}
+}
+
+/**
+ * Example of using ADC_1 to generate waveform.
+ */
+void ADC_1_example(void)
+{
+	uint8_t buffer[2];
+
+	adc_sync_enable_channel(&ADC_1, 0);
+
+	while (1) {
+		adc_sync_read_channel(&ADC_1, 0, buffer, 2);
+	}
+}
+
+/**
+ * Example of using DIGITAL_GLUE_LOGIC_0.
+ */
+void DIGITAL_GLUE_LOGIC_0_example(void)
+{
+	custom_logic_enable();
+	/* Customer logic now works. */
+}
+
+static void button_on_PA02_pressed(void)
+{
+}
+
+static void button_on_PA07_pressed(void)
+{
+}
+
+static void button_on_PB30_pressed(void)
+{
+}
+
+static void button_on_PB31_pressed(void)
+{
+}
+
+/**
+ * Example of using EXTERNAL_IRQ_0
+ */
+void EXTERNAL_IRQ_0_example(void)
+{
+
+	ext_irq_register(PIN_PA02, button_on_PA02_pressed);
+	ext_irq_register(PIN_PA07, button_on_PA07_pressed);
+	ext_irq_register(PIN_PB30, button_on_PB30_pressed);
+	ext_irq_register(PIN_PB31, button_on_PB31_pressed);
+}
+
+static uint8_t buf[16] = {0x0};
+
+static void xfer_complete_cb_ECAT_QSPI(struct _dma_resource *resource)
+{
+	/* Transfer completed */
+}
+
+/**
+ * Example of using ECAT_QSPI to get N25Q256A status value,
+ * and check bit 0 which indicate embedded operation is busy or not.
+ */
+void ECAT_QSPI_example(void)
+{
+	struct _qspi_command cmd = {
+	    .inst_frame.bits.inst_en      = 1,
+	    .inst_frame.bits.data_en      = 1,
+	    .inst_frame.bits.addr_en      = 1,
+	    .inst_frame.bits.dummy_cycles = 8,
+	    .inst_frame.bits.tfr_type     = QSPI_READMEM_ACCESS,
+	    .instruction                  = 0x0B,
+	    .address                      = 0,
+	    .buf_len                      = 14,
+	    .rx_buf                       = buf,
+	};
+
+	qspi_dma_register_callback(&ECAT_QSPI, QSPI_DMA_CB_XFER_DONE, xfer_complete_cb_ECAT_QSPI);
+	qspi_dma_enable(&ECAT_QSPI);
+	qspi_dma_serial_run_command(&ECAT_QSPI, &cmd);
+}
+
+static uint8_t I2C_0_example_str[12] = "Hello World!";
+
+void I2C_0_tx_complete(struct i2c_m_async_desc *const i2c)
+{
+}
+
+void I2C_0_example(void)
+{
+	struct io_descriptor *I2C_0_io;
+
+	i2c_m_async_get_io_descriptor(&I2C_0, &I2C_0_io);
+	i2c_m_async_enable(&I2C_0);
+	i2c_m_async_register_callback(&I2C_0, I2C_M_ASYNC_TX_COMPLETE, (FUNC_PTR)I2C_0_tx_complete);
+	i2c_m_async_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
+
+	io_write(I2C_0_io, I2C_0_example_str, 12);
+}
+
+/**
+ * Example of using SPI_1_MSIF to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
+ */
+
+static uint8_t example_SPI_1_MSIF[12] = "Hello World!";
+
+static void tx_complete_cb_SPI_1_MSIF(struct _dma_resource *resource)
+{
+	/* Transfer completed */
+}
+
+void SPI_1_MSIF_example(void)
+{
+	struct io_descriptor *io;
+	spi_m_dma_get_io_descriptor(&SPI_1_MSIF, &io);
+
+	spi_m_dma_register_callback(&SPI_1_MSIF, SPI_M_DMA_CB_TX_DONE, tx_complete_cb_SPI_1_MSIF);
+	spi_m_dma_enable(&SPI_1_MSIF);
+	io_write(io, example_SPI_1_MSIF, 12);
+}
+
+/**
+ * Example of using SPI_2 to write "Hello World" using the IO abstraction.
+ */
+static uint8_t example_SPI_2[12] = "Hello World!";
+
+void SPI_2_example(void)
+{
+	struct io_descriptor *io;
+	spi_m_sync_get_io_descriptor(&SPI_2, &io);
+
+	spi_m_sync_enable(&SPI_2);
+	io_write(io, example_SPI_2, 12);
+}
+
+/**
+ * Example of using SPI_3 to write "Hello World" using the IO abstraction.
+ */
+static uint8_t example_SPI_3[12] = "Hello World!";
+
+void SPI_3_example(void)
+{
+	struct io_descriptor *io;
+	spi_m_sync_get_io_descriptor(&SPI_3, &io);
+
+	spi_m_sync_enable(&SPI_3);
+	io_write(io, example_SPI_3, 12);
+}
+
+/**
+ * Example of using PWM_0.
+ */
+void PWM_0_example(void)
+{
+	pwm_set_parameters(&PWM_0, 10000, 5000);
+	pwm_enable(&PWM_0);
+}
+
+/**
+ * Example of using PWM_1.
+ */
+void PWM_1_example(void)
+{
+	pwm_set_parameters(&PWM_1, 10000, 5000);
+	pwm_enable(&PWM_1);
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/examples/driver_examples.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/examples/driver_examples.h
new file mode 100644
index 0000000..9defce7
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/examples/driver_examples.h
@@ -0,0 +1,36 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef DRIVER_EXAMPLES_H_INCLUDED
+#define DRIVER_EXAMPLES_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void ADC_0_example(void);
+
+void ADC_1_example(void);
+
+void DIGITAL_GLUE_LOGIC_0_example(void);
+
+void EXTERNAL_IRQ_0_example(void);
+
+void ECAT_QSPI_example(void);
+
+void I2C_0_example(void);
+
+void SPI_1_MSIF_example(void);
+
+void PWM_0_example(void);
+
+void PWM_1_example(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif // DRIVER_EXAMPLES_H_INCLUDED
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/adc_sync.rst b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/adc_sync.rst
new file mode 100644
index 0000000..d189565
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/adc_sync.rst
@@ -0,0 +1,74 @@
+======================
+ADC Synchronous driver
+======================
+
+An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
+A reference signal with a known voltage level is quantified into equally
+sized chunks, each representing a digital value from 0 to the highest number
+possible with the bit resolution supported by the ADC. The input voltage
+measured by the ADC is compared against these chunks and the chunk with the
+closest voltage level defines the digital value that can be used to represent
+the analog input voltage level.
+
+Usually an ADC can operate in either differential or single-ended mode.
+In differential mode two signals (V+ and V-) are compared against each other
+and the resulting digital value represents the relative voltage level between
+V+ and V-. This means that if the input voltage level on V+ is lower than on
+V- the digital value is negative, which also means that in differential
+mode one bit is lost to the sign. In single-ended mode only V+ is compared
+against the reference voltage, and the resulting digital value can only be
+positive, but the full bit-range of the ADC can be used.
+
+Usually multiple resolutions are supported by the ADC, lower resolution can
+reduce the conversion time, but lose accuracy.
+
+Some ADCs has a gain stage on the input lines which can be used to increase the
+dynamic range. The default gain value is usually x1, which means that the
+conversion range is from 0V to the reference voltage.
+Applications can change the gain stage, to increase or reduce the conversion
+range.
+
+The window mode allows the conversion result to be compared to a set of
+predefined threshold values. Applications can use callback function to monitor
+if the conversion result exceeds predefined threshold value.
+
+Usually multiple reference voltages are supported by the ADC, both internal and
+external with difference voltage levels. The reference voltage have an impact
+on the accuracy, and should be selected to cover the full range of the analog
+input signal and never less than the expected maximum input voltage.
+
+There are two conversion modes supported by ADC, single shot and free running.
+In single shot mode the ADC only make one conversion when triggered by the
+application, in free running mode it continues to make conversion from it
+is triggered until it is stopped by the application. When window monitoring,
+the ADC should be set to free running mode.
+
+Features
+--------
+* Initialization and de-initialization
+* Support multiple Conversion Mode, Single or Free run
+* Start ADC Conversion
+* Read Conversion Result
+
+Applications
+------------
+* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
+* Measurement of external sensor. E.g., Temperature, humidity sensor value.
+* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
+
+Dependencies
+------------
+* ADC hardware
+
+Concurrency
+-----------
+N/A
+
+Limitations
+-----------
+N/A
+
+Knows issues and workarounds
+----------------------------
+N/A
+
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/custom_logic.rst b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/custom_logic.rst
new file mode 100644
index 0000000..08c8515
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/custom_logic.rst
@@ -0,0 +1,32 @@
+===========================================================
+Digital Glue Logic based on Configurable Custom Logic (CCL)
+===========================================================
+
+Custom logic driver offers a way to initialize on-chip programmable logic
+units, so that a specific logic box is built. Then this "box" can be connected
+to internal or external circuit to perform the logic operations.
+
+Features
+--------
+* Initialization and de-initialization
+* Enabling and disabling
+
+Applications
+------------
+* Connected to external circuit, as a logic operation box, e.g., as adder.
+
+Dependencies
+------------
+* Programmable logic control units
+
+Concurrency
+-----------
+N/A
+
+Limitations
+-----------
+N/A
+
+Knows issues and workarounds
+----------------------------
+N/A
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/evsys.rst b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/evsys.rst
new file mode 100644
index 0000000..01d40bc
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/evsys.rst
@@ -0,0 +1,24 @@
+===================
+Event system driver
+===================
+
+Event system allows autonomous, low-latency and configurable communication between peripherals.
+
+Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition
+to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that
+respond to events are event users, peripherals that generate events are called event generators. A peripheral can have
+one or more event generators and can have one or more event users.
+
+Communication is made without CPU intervention and without consuming system resources such as bus or RAM bandwidth. This
+reduces the load on the CPU and system resources, compared to a traditional interrupt-based system.
+
+The Event System consists of several channels which route the internal events from generators
+to users. Each event generator can be selected as source for multiple channels, but a channel cannot
+be set to use multiple event generators at the same time.
+
+Event system driver allows to configure event system of an MCU.
+
+Limitations
+-----------
+
+ - Event channel configuration is static
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/ext_irq.rst b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/ext_irq.rst
new file mode 100644
index 0000000..7dcdc7c
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/ext_irq.rst
@@ -0,0 +1,39 @@
+==============
+EXT IRQ driver
+==============
+
+The External Interrupt driver allows external pins to be
+configured as interrupt lines. Each interrupt line can be
+individually masked and can generate an interrupt on rising,
+falling or both edges, or on high or low levels. Some of
+external pin can also be configured to wake up the device
+from sleep modes where all clocks have been disabled.
+External pins can also generate an event.
+
+Features
+--------
+* Initialization and de-initialization
+* Enabling and disabling
+* Detect external pins interrupt
+
+Applications
+------------
+* Generate an interrupt on rising, falling or both edges,
+  or on high or low levels.
+
+Dependencies
+------------
+* GPIO hardware
+
+Concurrency
+-----------
+N/A
+
+Limitations
+-----------
+N/A
+
+Knows issues and workarounds
+----------------------------
+N/A
+
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/i2c_master_async.rst b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/i2c_master_async.rst
new file mode 100644
index 0000000..877b451
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/i2c_master_async.rst
@@ -0,0 +1,110 @@
+==============================
+I2C Master asynchronous driver
+==============================
+
+I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
+for on-board low-speed bi-directional communication between controllers and
+peripherals. The master device is responsible for initiating and controlling
+all transfers on the I2C bus. Only one master device can be active on the I2C
+bus at the time, but the master role can be transferred between devices on the
+same I2C bus. I2C uses only two bidirectional open-drain lines, usually
+designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
+resistors.
+
+The stop condition is automatically controlled by the driver if the I/O write and
+read functions are used, but can be manually controlled by using the
+i2c_m_async_transfer function.
+
+Often a master accesses different information in the slave by accessing
+different registers in the slave. This is done by first sending a message to
+the target slave containing the register address, followed by a repeated start
+condition (no stop condition between) ending with transferring register data.
+This scheme is supported by the i2c_m_async_cmd_write and i2c_m_async_cmd_read
+function, but limited to 8-bit register addresses.
+
+Transfer callbacks are executed at the end of a full transfer, that is when
+a complete message with address is either sent or read from the slave. When the
+i2c_m_async_transfer function is used the tx and rx callbacks are triggered
+regardless of if a stop condition is generated at the end of the message.
+
+The tx and rx callbacks are reused for the cmd functions and are triggered at
+the end of a full register write or read, that is after the register address has
+been written to the slave and data has been transferred to or from the master.
+
+The error callback is executed as soon as an error is detected, the error
+situation can both be detected while processing an interrupt or detected by
+the hardware which may trigger a special error interrupt. In situations where
+errors are detected by software, there will be a slight delay from the error
+occurs until the error callback is triggered due to software processing.
+
+I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
+Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
+stick within the SCL clock frequency range supported by the selected mode.
+The requested SCL clock frequency is not validated by the
+i2c_m_async_set_baudrate function against the selected I2C mode.
+
+Features
+--------
+
+	* I2C Master support
+	* Initialization and de-initialization
+	* Enabling and disabling
+	* Run-time bus speed configuration
+	* Write and read I2C messages
+	* Slave register access functions (limited to 8-bit address)
+	* Manual or automatic stop condition generation
+	* 10- and 7- bit addressing
+	* I2C Modes supported
+	       +----------------------+-------------------+
+	       |* Standard/Fast mode  | (SCL: 1 - 400kHz) |
+	       +----------------------+-------------------+
+	       |* Fastmode+           | (SCL: 1 - 1000kHz)|
+	       +----------------------+-------------------+
+	       |* Highspeed mode      | (SCL: 1 - 3400kHz)|
+	       +----------------------+-------------------+
+	* Callback on buffer transfer complete and error events
+
+Applications
+------------
+
+* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
+* Data communication between micro controllers
+* Controlling displays
+
+Dependencies
+------------
+
+* I2C Master capable hardware with char transfer complete and error interrupt
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+General
+^^^^^^^
+
+	* System Management Bus (SMBus) not supported
+	* Power Management Bus (PMBus) not supported
+	* Buffer content should not be changed before transfer is complete
+	* Due to software processing some errors may have a detection delay.
+
+Clock considerations
+^^^^^^^^^^^^^^^^^^^^
+
+The register value for the requested I2C speed is calculated and placed in the
+correct register, but not validated if it works correctly with the
+clock/prescaler settings used for the module. To validate the I2C speed
+setting use the formula found in the configuration file for the module.
+Selectable speed is automatically limited within the speed range defined by
+the I2C mode selected.
+
+Known issues and workarounds
+----------------------------
+
+N/A
+
+
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/pwm.rst b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/pwm.rst
new file mode 100644
index 0000000..71785c6
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/pwm.rst
@@ -0,0 +1,53 @@
+The PWM Driver(bare-bone)
+=========================
+
+Pulse-width modulation (PWM) is used to create an analog behavior
+digitally by controlling the amount of power transferred to the
+connected peripheral. This is achieved by controlling the high period
+(duty-cycle) of a periodic signal.
+
+User can change the period or duty cycle whenever PWM is running. The
+function pwm_set_parameters is used to configure these two parameters.
+Note these are raw register values and the parameter duty_cycle means
+the period of first half during one cycle, which should be not beyond
+total period value.
+
+In addition, user can also get multi PWM channels output from different
+peripherals at the same time, which is implemented more flexible by the
+function pointers.
+
+Features
+--------
+
+* Initialization/de-initialization
+* Enabling/disabling
+* Run-time control of PWM duty-cycle and period
+* Notifications about errors and one PWM cycle is done
+
+Applications
+------------
+
+Motor control, ballast, LED, H-bridge, power converters, and
+other types of power control applications.
+
+Dependencies
+------------
+
+The peripheral which can perform waveform generation like frequency
+generation and pulse-width modulation, such as Timer/Counter.
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+The current driver doesn't support the features like recoverable,
+non-recoverable faults, dithering, dead-time insertion.
+
+Known issues and workarounds
+----------------------------
+
+N/A
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/quad_spi_dma.rst b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/quad_spi_dma.rst
new file mode 100644
index 0000000..4ab9a12
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/quad_spi_dma.rst
@@ -0,0 +1,46 @@
+The Quad SPI DMA Driver
+=================================
+
+The Quad SPI Interface (QSPI) is a synchronous serial data link that provides
+communication with external devices in master mode.
+
+The QSPI DMA driver uses DMA system to transfer data between QSPI Memory region
+and external device. User must configure DMAC system driver accordingly. Callback 
+function is called when all the data is transferred or transfer error occurred, 
+if it is registered via qspi_dma_register_callback() function.
+
+
+Features
+--------
+
+* Initialization/de-initialization
+* Enabling/disabling
+* Register callback function
+* Execute command in Serial Memory Mode
+
+Applications
+------------
+
+They are commonly used in an application for using serial flash memory operating
+in single-bit SPI, Dual SPI and Quad SPI. 
+
+Dependencies
+------------
+
+Serial NOR flash with Multiple I/O hardware
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+N.A
+
+Known issues and workarounds
+----------------------------
+
+N/A
+
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/spi_master_dma.rst b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/spi_master_dma.rst
new file mode 100644
index 0000000..475b317
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/spi_master_dma.rst
@@ -0,0 +1,56 @@
+The SPI Master DMA Driver
+==================================
+
+The serial peripheral interface (SPI) is a DMA serial communication
+interface.
+
+The SPI Master DMA driver uses DMA system to transfer data from
+a memory buffer to SPI (Memory to Peripheral), and receive data
+from SPI to a memory buffer (Peripheral to Memory).User must configure
+DMA system driver accordingly. A callback is called when all the data
+is transfered or all the data is received, if it is registered via 
+spi_m_dma_register_callback function.
+
+Features
+--------
+
+* Initialization/de-initialization
+* Enabling/disabling
+* Control of the following settings:
+
+  * Baudrate
+  * SPI mode
+  * Character size
+  * Data order
+* Data transfer: transmission, reception and full-duplex
+* Notifications about transfer completion and errors via callbacks
+
+Applications
+------------
+
+Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card,
+LCD controller, etc.
+
+Dependencies
+------------
+
+SPI master capable hardware and DMA hardware, with data sent/received.
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+When only uses DMA channel to receive data, the transfer channel must enable to
+send dummy data to the slave.
+
+While read/write/transfer is in progress, the data buffer used must be kept
+unchanged.
+
+Known issues and workarounds
+----------------------------
+
+N/A
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/spi_master_sync.rst b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/spi_master_sync.rst
new file mode 100644
index 0000000..4fbe45e
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/spi_master_sync.rst
@@ -0,0 +1,51 @@
+The SPI Master Synchronous Driver
+=================================
+
+The serial peripheral interface (SPI) is a synchronous serial communication
+interface.
+
+SPI devices communicate in full duplex mode using a master-slave
+architecture with a single master. The master device originates the frame for
+reading and writing. Multiple slave devices are supported through selection
+with individual slave select (SS) lines.
+
+Features
+--------
+
+* Initialization/de-initialization
+* Enabling/disabling
+* Control of the following settings:
+
+  * Baudrate
+  * SPI mode
+  * Character size
+  * Data order
+* Data transfer: transmission, reception and full-duplex
+
+Applications
+------------
+
+Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card,
+LCD controller, etc.
+
+Dependencies
+------------
+
+SPI master capable hardware
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+The slave select (SS) is not automatically inserted during read/write/transfer,
+user must use I/O to control the devices' SS.
+
+Known issues and workarounds
+----------------------------
+
+N/A
+
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_adc_sync.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_adc_sync.h
new file mode 100644
index 0000000..1b66e3d
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_adc_sync.h
@@ -0,0 +1,277 @@
+/**
+ * \file
+ *
+ * \brief ADC functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_ADC_SYNC_H_INCLUDED
+#define _HAL_ADC_SYNC_H_INCLUDED
+
+#include <hpl_adc_sync.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_adc_sync
+ *
+ * @{
+ */
+
+/**
+ * \brief ADC descriptor
+ *
+ * The ADC descriptor forward declaration.
+ */
+struct adc_sync_descriptor;
+
+/**
+ * \brief ADC descriptor
+ */
+struct adc_sync_descriptor {
+	/** ADC device */
+	struct _adc_sync_device device;
+};
+
+/**
+ * \brief Initialize ADC
+ *
+ * This function initializes the given ADC descriptor.
+ * It checks if the given hardware is not initialized and if the given hardware
+ * is permitted to be initialized.
+ *
+ * \param[out] descr An ADC descriptor to initialize
+ * \param[in] hw     The pointer to hardware instance
+ * \param[in] func   The pointer to a set of functions pointers
+ *
+ * \return Initialization status.
+ */
+int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * This function deinitializes the given ADC descriptor.
+ * It checks if the given hardware is initialized and if the given hardware is
+ * permitted to be deinitialized.
+ *
+ * \param[in] descr An ADC descriptor to deinitialize
+ *
+ * \return De-initialization status.
+ */
+int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr);
+
+/**
+ * \brief Enable ADC
+ *
+ * Use this function to set the ADC peripheral to enabled state.
+ *
+ * \param[in] descr    Pointer to the ADC descriptor
+ * \param[in] channel  Channel number
+ *
+ * \return Operation status
+ *
+ */
+int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Disable ADC
+ *
+ * Use this function to set the ADC peripheral to disabled state.
+ *
+ * \param[in] descr   Pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ *
+ * \return Operation status
+ *
+ */
+int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Read data from ADC
+ *
+ * \param[in] descr    The pointer to the ADC descriptor
+ * \param[in] channel  Channel number
+ * \param[in] buf      A buffer to read data to
+ * \param[in] length   The size of a buffer
+ *
+ * \return The number of bytes read.
+ */
+int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
+                              const uint16_t length);
+
+/**
+ * \brief Set ADC reference source
+ *
+ * This function sets ADC reference source.
+ *
+ * \param[in] descr     The pointer to the ADC descriptor
+ * \param[in] reference A reference source to set
+ *
+ * \return Status of the ADC reference source setting.
+ */
+int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference);
+
+/**
+ * \brief Set ADC resolution
+ *
+ * This function sets ADC resolution.
+ *
+ * \param[in] descr      The pointer to the ADC descriptor
+ * \param[in] resolution A resolution to set
+ *
+ * \return Status of the ADC resolution setting.
+ */
+int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * This function sets ADC positive and negative input sources.
+ *
+ * \param[in] descr     The pointer to the ADC descriptor
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ *
+ * \return Status of the ADC channels setting.
+ */
+int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
+                            const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set ADC conversion mode
+ *
+ * This function sets ADC conversion mode.
+ *
+ * \param[in] descr The pointer to the ADC descriptor
+ * \param[in] mode  A conversion mode to set
+ *
+ * \return Status of the ADC conversion mode setting.
+ */
+int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set ADC differential mode
+ *
+ * This function sets ADC differential mode.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ *
+ * \return Status of the ADC differential mode setting.
+ */
+int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                               const enum adc_differential_mode mode);
+
+/**
+ * \brief Set ADC channel gain
+ *
+ * This function sets ADC channel gain.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ * \param[in] gain    A gain to set
+ *
+ * \return Status of the ADC gain setting.
+ */
+int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                  const adc_gain_t gain);
+
+/**
+ * \brief Set ADC window mode
+ *
+ * This function sets ADC window mode.
+ *
+ * \param[in] descr The pointer to the ADC descriptor
+ * \param[in] mode  A window mode to set
+ *
+ * \return Status of the ADC window mode setting.
+ */
+int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode);
+
+/**
+ * \brief Set ADC thresholds
+ *
+ * This function sets ADC positive and negative thresholds.
+ *
+ * \param[in] descr         The pointer to the ADC descriptor
+ * \param[in] low_threshold A lower thresholds to set
+ * \param[in] up_threshold  An upper thresholds to set
+ *
+ * \return Status of the ADC thresholds setting.
+ */
+int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
+                                const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * This function retrieves ADC threshold state.
+ *
+ * \param[in] descr  The pointer to the ADC descriptor
+ * \param[out] state The threshold state
+ *
+ * \return The state of ADC thresholds state retrieving.
+ */
+int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr,
+                                     adc_threshold_status_t *const           state);
+
+/**
+ * \brief Check if conversion is complete
+ *
+ * This function checks if the ADC has finished the conversion.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ *
+ * \return The status of ADC conversion completion checking.
+ * \retval 1 The conversion is complete
+ * \retval 0 The conversion is not complete
+ */
+int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t adc_sync_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#include <hpl_missing_features.h>
+
+#endif /* _HAL_ADC_SYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_atomic.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_atomic.h
new file mode 100644
index 0000000..82151fc
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_atomic.h
@@ -0,0 +1,120 @@
+/**
+ * \file
+ *
+ * \brief Critical sections related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_ATOMIC_H_INCLUDED
+#define _HAL_ATOMIC_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_helper_atomic
+ *
+ *@{
+ */
+
+/**
+ * \brief Type for the register holding global interrupt enable flag
+ */
+typedef uint32_t hal_atomic_t;
+
+/**
+ * \brief Helper macro for entering critical sections
+ *
+ * This macro is recommended to be used instead of a direct call
+ * hal_enterCritical() function to enter critical
+ * sections. No semicolon is required after the macro.
+ *
+ * \section atomic_usage Usage Example
+ * \code
+ * CRITICAL_SECTION_ENTER()
+ * Critical code
+ * CRITICAL_SECTION_LEAVE()
+ * \endcode
+ */
+#define CRITICAL_SECTION_ENTER()                                                                                       \
+	{                                                                                                                  \
+		volatile hal_atomic_t __atomic;                                                                                \
+		atomic_enter_critical(&__atomic);
+
+/**
+ * \brief Helper macro for leaving critical sections
+ *
+ * This macro is recommended to be used instead of a direct call
+ * hal_leaveCritical() function to leave critical
+ * sections. No semicolon is required after the macro.
+ */
+#define CRITICAL_SECTION_LEAVE()                                                                                       \
+	atomic_leave_critical(&__atomic);                                                                                  \
+	}
+
+/**
+ * \brief Disable interrupts, enter critical section
+ *
+ * Disables global interrupts. Supports nested critical sections,
+ * so that global interrupts are only re-enabled
+ * upon leaving the outermost nested critical section.
+ *
+ * \param[out] atomic The pointer to a variable to store the value of global
+ * interrupt enable flag
+ */
+void atomic_enter_critical(hal_atomic_t volatile *atomic);
+
+/**
+ * \brief Exit atomic section
+ *
+ * Enables global interrupts. Supports nested critical sections,
+ * so that global interrupts are only re-enabled
+ * upon leaving the outermost nested critical section.
+ *
+ * \param[in] atomic The pointer to a variable, which stores the latest stored
+ * value of the global interrupt enable flag
+ */
+void atomic_leave_critical(hal_atomic_t volatile *atomic);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t atomic_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_ATOMIC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_cache.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_cache.h
new file mode 100644
index 0000000..071486b
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_cache.h
@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief HAL cache functionality implementation.
+ *
+ * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".  NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef HAL_CACHE_H_
+#define HAL_CACHE_H_
+
+#include <hpl_cmcc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Enable cache module
+ *
+ * \param[in] pointer pointing to the starting address of cache module
+ *
+ * \return status of operation
+ */
+int32_t cache_enable(const void *hw);
+
+/**
+ * \brief Disable cache module
+ *
+ * \param[in] pointer pointing to the starting address of cache module
+ *
+ * \return status of operation
+ */
+int32_t cache_disable(const void *hw);
+
+/**
+ * \brief Initialize cache module
+ *
+ * This function initialize cache module configuration.
+ *
+ * \return status of operation
+ */
+int32_t cache_init(void);
+
+/**
+ * \brief Configure cache module
+ *
+ * \param[in] pointer pointing to the starting address of cache module
+ * \param[in] cache configuration structure pointer
+ *
+ * \return status of operation
+ */
+int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
+
+/**
+ * \brief Invalidate entire cache entries
+ *
+ * \param[in] pointer pointing to the starting address of cache module
+ *
+ * \return status of operation
+ */
+int32_t cache_invalidate_all(const void *hw);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_CACHE_H_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_custom_logic.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_custom_logic.h
new file mode 100644
index 0000000..b3f31f6
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_custom_logic.h
@@ -0,0 +1,89 @@
+/**
+ * \file
+ *
+ * \brief Custom Control Logic functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hpl_custom_logic.h"
+
+#ifndef _HAL_CUSTOM_LOGIC_H_INCLUDED
+#define _HAL_CUSTOM_LOGIC_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_custom_logic
+ *
+ *@{
+ */
+
+/**
+ *  \brief Initialize the custom logic hardware
+ *  \return Initialization operation status
+ */
+static inline int32_t custom_logic_init(void)
+{
+	return _custom_logic_init();
+}
+
+/**
+ *  \brief Disable and reset the custom logic hardware
+ */
+static inline void custom_logic_deinit(void)
+{
+	_custom_logic_deinit();
+}
+
+/**
+ *  \brief Enable the custom logic hardware
+ *  \return Initialization operation status
+ */
+static inline int32_t custom_logic_enable(void)
+{
+	return _custom_logic_enable();
+}
+
+/**
+ *  \brief Disable the custom logic hardware
+ */
+static inline void custom_logic_disable(void)
+{
+	_custom_logic_disable();
+}
+
+	/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_CUSTOM_LOGIC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_delay.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_delay.h
new file mode 100644
index 0000000..9d4aa5c
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_delay.h
@@ -0,0 +1,89 @@
+/**
+ * \file
+ *
+ * \brief HAL delay related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_irq.h>
+#include <hpl_reset.h>
+#include <hpl_sleep.h>
+
+#ifndef _HAL_DELAY_H_INCLUDED
+#define _HAL_DELAY_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_delay Delay Driver
+ *
+ *@{
+ */
+
+/**
+ * \brief Initialize Delay driver
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+void delay_init(void *const hw);
+
+/**
+ * \brief Perform delay in us
+ *
+ * This function performs delay for the given amount of microseconds.
+ *
+ * \param[in] us The amount delay in us
+ */
+void delay_us(const uint16_t us);
+
+/**
+ * \brief Perform delay in ms
+ *
+ * This function performs delay for the given amount of milliseconds.
+ *
+ * \param[in] ms The amount delay in ms
+ */
+void delay_ms(const uint16_t ms);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t delay_get_version(void);
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HAL_DELAY_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_evsys.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_evsys.h
new file mode 100644
index 0000000..3f68540
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_evsys.h
@@ -0,0 +1,116 @@
+/**
+ * \file
+ *
+ * \brief HAL event system related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_evsys.h>
+
+#ifndef _HAL_EVSYS_H_INCLUDED
+#define _HAL_EVSYS_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_evsys
+ *
+ * @{
+ */
+
+/**
+ * \brief Initialize event system.
+ *
+ * \return Initialization status.
+ */
+int32_t event_system_init(void);
+
+/**
+ * \brief Deinitialize event system.
+ *
+ * \return De-initialization status.
+ */
+int32_t event_system_deinit(void);
+
+/**
+ * \brief Enable event reception by the given user from the given channel
+ *
+ * \param[in] user A user to enable
+ * \param[in] channel A channel the user is assigned to
+ *
+ * \return Status of operation.
+ */
+int32_t event_system_enable_user(const uint16_t user, const uint16_t channel);
+
+/**
+ * \brief Disable event reception by the given user from the given channel
+ *
+ * \param[in] user A user to disable
+ * \param[in] channel A channel the user is assigned to
+ *
+ * \return Status of operation.
+ */
+int32_t event_system_disable_user(const uint16_t user, const uint16_t channel);
+
+/**
+ * \brief Enable event generation by the given generator for the given channel
+ *
+ * \param[in] generator A generator to disable
+ * \param[in] channel A channel the generator is assigned to
+ *
+ * \return Status of operation.
+ */
+int32_t event_system_enable_generator(const uint16_t generator, const uint16_t channel);
+
+/**
+ * \brief Disable event generation by the given generator for the given channel
+ *
+ * \param[in] generator A generator to disable
+ * \param[in] channel A channel the generator is assigned to
+ *
+ * \return Status of operation.
+ */
+int32_t event_system_disable_generator(const uint16_t generator, const uint16_t channel);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t event_system_get_version(void);
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HAL_EVSYS_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_ext_irq.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_ext_irq.h
new file mode 100644
index 0000000..a7c2600
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_ext_irq.h
@@ -0,0 +1,118 @@
+/**
+ * \file
+ *
+ * \brief External interrupt functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_EXT_IRQ_H_INCLUDED
+#define _HAL_EXT_IRQ_H_INCLUDED
+
+#include <hpl_ext_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_ext_irq
+ *
+ * @{
+ */
+
+/**
+ * \brief External IRQ callback type
+ */
+typedef void (*ext_irq_cb_t)(void);
+
+/**
+ * \brief Initialize external IRQ component, if any
+ *
+ * \return Initialization status.
+ * \retval -1 External IRQ module is already initialized
+ * \retval 0 The initialization is completed successfully
+ */
+int32_t ext_irq_init(void);
+
+/**
+ * \brief Deinitialize external IRQ, if any
+ *
+ * \return De-initialization status.
+ * \retval -1 External IRQ module is already deinitialized
+ * \retval 0 The de-initialization is completed successfully
+ */
+int32_t ext_irq_deinit(void);
+
+/**
+ * \brief Register callback for the given external interrupt
+ *
+ * \param[in] pin Pin to enable external IRQ on
+ * \param[in] cb Callback function
+ *
+ * \return Registration status.
+ * \retval -1 Passed parameters were invalid
+ * \retval 0 The callback registration is completed successfully
+ */
+int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb);
+
+/**
+ * \brief Enable external IRQ
+ *
+ * \param[in] pin Pin to enable external IRQ on
+ *
+ * \return Enabling status.
+ * \retval -1 Passed parameters were invalid
+ * \retval 0 The enabling is completed successfully
+ */
+int32_t ext_irq_enable(const uint32_t pin);
+
+/**
+ * \brief Disable external IRQ
+ *
+ * \param[in] pin Pin to enable external IRQ on
+ *
+ * \return Disabling status.
+ * \retval -1 Passed parameters were invalid
+ * \retval 0 The disabling is completed successfully
+ */
+int32_t ext_irq_disable(const uint32_t pin);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t ext_irq_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_EXT_IRQ_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_gpio.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_gpio.h
new file mode 100644
index 0000000..fbfa2d4
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_gpio.h
@@ -0,0 +1,201 @@
+/**
+ * \file
+ *
+ * \brief Port
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+#ifndef _HAL_GPIO_INCLUDED_
+#define _HAL_GPIO_INCLUDED_
+
+#include <hpl_gpio.h>
+#include <utils_assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Set gpio pull mode
+ *
+ * Set pin pull mode, non existing pull modes throws an fatal assert
+ *
+ * \param[in] pin       The pin number for device
+ * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor
+ *                      GPIO_PULL_UP   = Pull pin high with internal resistor
+ *                      GPIO_PULL_OFF  = Disable pin pull mode
+ */
+static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode)
+{
+	_gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode);
+}
+
+/**
+ * \brief Set pin function
+ *
+ * Select which function a pin will be used for
+ *
+ * \param[in] pin       The pin number for device
+ * \param[in] function  The pin function is given by a 32-bit wide bitfield
+ *                      found in the header files for the device
+ *
+ */
+static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
+{
+	_gpio_set_pin_function(pin, function);
+}
+
+/**
+ * \brief Set port data direction
+ *
+ * Select if the pin data direction is input, output or disabled.
+ * If disabled state is not possible, this function throws an assert.
+ *
+ * \param[in] port      Ports are grouped into groups of maximum 32 pins,
+ *                      GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask      Bit mask where 1 means apply direction setting to the
+ *                      corresponding pin
+ * \param[in] direction GPIO_DIRECTION_IN  = Data direction in
+ *                      GPIO_DIRECTION_OUT = Data direction out
+ *                      GPIO_DIRECTION_OFF = Disables the pin
+ *                      (low power state)
+ */
+static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask,
+                                           const enum gpio_direction direction)
+{
+	_gpio_set_direction(port, mask, direction);
+}
+
+/**
+ * \brief Set gpio data direction
+ *
+ * Select if the pin data direction is input, output or disabled.
+ * If disabled state is not possible, this function throws an assert.
+ *
+ * \param[in] pin       The pin number for device
+ * \param[in] direction GPIO_DIRECTION_IN  = Data direction in
+ *                      GPIO_DIRECTION_OUT = Data direction out
+ *                      GPIO_DIRECTION_OFF = Disables the pin
+ *                      (low power state)
+ */
+static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
+{
+	_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
+}
+
+/**
+ * \brief Set port level
+ *
+ * Sets output level on the pins defined by the bit mask
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask  Bit mask where 1 means apply port level to the corresponding
+ *                  pin
+ * \param[in] level true  = Pin levels set to "high" state
+ *                  false = Pin levels set to "low" state
+ */
+static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level)
+{
+	_gpio_set_level(port, mask, level);
+}
+
+/**
+ * \brief Set gpio level
+ *
+ * Sets output level on a pin
+ *
+ * \param[in] pin       The pin number for device
+ * \param[in] level true  = Pin level set to "high" state
+ *                  false = Pin level set to "low" state
+ */
+static inline void gpio_set_pin_level(const uint8_t pin, const bool level)
+{
+	_gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level);
+}
+
+/**
+ * \brief Toggle out level on pins
+ *
+ * Toggle the pin levels on pins defined by bit mask
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask  Bit mask where 1 means toggle pin level to the corresponding
+ *                  pin
+ */
+static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask)
+{
+	_gpio_toggle_level(port, mask);
+}
+
+/**
+ * \brief Toggle output level on pin
+ *
+ * Toggle the pin levels on pins defined by bit mask
+ *
+ * \param[in] pin       The pin number for device
+ */
+static inline void gpio_toggle_pin_level(const uint8_t pin)
+{
+	_gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin));
+}
+
+/**
+ * \brief Get input level on pins
+ *
+ * Read the input level on pins connected to a port
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ */
+static inline uint32_t gpio_get_port_level(const enum gpio_port port)
+{
+	return _gpio_get_level(port);
+}
+
+/**
+ * \brief Get level on pin
+ *
+ * Reads the level on pins connected to a port
+ *
+ * \param[in] pin       The pin number for device
+ */
+static inline bool gpio_get_pin_level(const uint8_t pin)
+{
+	return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
+}
+/**
+ * \brief Get current driver version
+ */
+uint32_t gpio_get_version(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_i2c_m_async.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_i2c_m_async.h
new file mode 100644
index 0000000..7bde18b
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_i2c_m_async.h
@@ -0,0 +1,327 @@
+/**
+ * \file
+ *
+ * \brief Async I2C Hardware Abstraction Layer(HAL) declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_I2C_M_ASYNC_H_INCLUDED
+#define _HAL_I2C_M_ASYNC_H_INCLUDED
+
+#include <hpl_i2c_m_async.h>
+#include <hal_io.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_i2c_master_async
+ *
+ * @{
+ */
+
+#define I2C_M_MAX_RETRY 1
+
+/**
+ * \brief I2C master callback names
+ */
+enum i2c_m_async_callback_type { I2C_M_ASYNC_ERROR, I2C_M_ASYNC_TX_COMPLETE, I2C_M_ASYNC_RX_COMPLETE };
+
+/**
+ * \brief Forward declaration of the descriptor type
+ */
+struct i2c_m_async_desc;
+
+/**
+ * \brief The I2C master callback function type for completion of RX or TX
+ */
+typedef void (*i2c_complete_cb_t)(struct i2c_m_async_desc *const i2c);
+
+/**
+ * \brief The I2C master callback function type for error
+ */
+typedef void (*i2c_error_cb_t)(struct i2c_m_async_desc *const i2c, int32_t error);
+
+/** \brief I2C status
+ *
+ *  Status descriptor holds the current status of transfer.
+ */
+struct i2c_m_async_status {
+	/** Status flags */
+	uint16_t flags;
+	/** The number of characters left in the message buffer*/
+	int32_t left;
+};
+
+/**
+ * \brief I2C master callback pointers structure
+ */
+struct i2c_m_async_callback {
+	i2c_error_cb_t    error;
+	i2c_complete_cb_t tx_complete;
+	i2c_complete_cb_t rx_complete;
+};
+
+/**
+ * \brief I2C descriptor structure, embed i2c_device & i2c_interface
+ */
+struct i2c_m_async_desc {
+	struct _i2c_m_async_device  device;
+	struct io_descriptor        io;
+	struct i2c_m_async_callback i2c_cb;
+	uint16_t                    slave_addr;
+};
+
+/**
+ * \brief Initialize the asynchronous I2C master interface
+ *
+ * This function initializes the given I2C descriptor to be used as asynchronous
+ * I2C master interface descriptor.
+ * It checks if the given hardware is not initialized and if the given hardware
+ * is permitted to be initialized.
+ *
+ * \param[in] i2c An I2C master descriptor, which is used to communicate through I2C
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status.
+ */
+int32_t i2c_m_async_init(struct i2c_m_async_desc *const i2c, void *const hw);
+
+/**
+ * \brief Deinitialize asynchronous I2C master interface
+ *
+ * This function deinitializes the given asynchronous I2C master descriptor.
+ * It checks if the given hardware is initialized and if the given hardware is
+ * permitted to be deinitialized.
+ *
+ * \param[in] i2c An I2C master descriptor, which is used to communicate through
+ *                I2C
+ *
+ * \return De-initialization status.
+ * \retval -1 The passed parameters were invalid or the interface is already
+ *            deinitialized
+ * \retval 0 The de-initialization is completed successfully
+ */
+int32_t i2c_m_async_deinit(struct i2c_m_async_desc *const i2c);
+
+/**
+ * \brief Set the slave device address
+ *
+ * This function sets the next transfer target slave I2C device address.
+ * It takes no effect to an already started access.
+ *
+ * \param[in] i2c An I2C master descriptor, which is used to communicate through
+ *                I2C
+ * \param[in] addr The slave address to access
+ * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN
+ *
+ * \return Masked slave address. The mask is maximum a 10-bit address, and the 10th
+ *         bit set if 10-bit address is used
+ */
+int32_t i2c_m_async_set_slaveaddr(struct i2c_m_async_desc *const i2c, int16_t addr, int32_t addr_len);
+
+/**
+ * \brief Register callback function
+ *
+ * This function registers one callback function to the I2C master device specified
+ * by the given descriptor
+ *
+ * \param[in] i2c An I2C master descriptor, which is used to communicate through
+ *                I2C
+ * \param[in] type Type of a callback to set
+ * \param[in] func Callback function pointer
+ *
+ * \return Callback setting status
+ * \retval -1 The passed parameters were invalid
+ * \retval 0 The callback set is completed successfully
+ */
+int32_t i2c_m_async_register_callback(struct i2c_m_async_desc *const i2c, enum i2c_m_async_callback_type type,
+                                      FUNC_PTR func);
+
+/**
+ * \brief Set baudrate
+ *
+ * This function sets the I2C master device to a specified baudrate.
+ * It only takes effect when the hardware is disabled.
+ *
+ * \param[in] i2c An I2C master descriptor, which is used to communicate through
+ *                I2C
+ * \param[in] clkrate Unused parameter, should always be 0
+ * \param[in] baudrate The baudrate value set to master
+ *
+ * \return The status whether successfully set the baudrate
+ * \retval -1 The passed parameters were invalid or the device is already enabled
+ * \retval 0 The baudrate set is completed successfully
+ */
+int32_t i2c_m_async_set_baudrate(struct i2c_m_async_desc *const i2c, uint32_t clkrate, uint32_t baudrate);
+
+/**
+ * \brief Async version of enable hardware
+ *
+ * This function enables the I2C master device and then waits for this enabling
+ * operation to be done.
+ *
+ * \param[in] i2c An I2C master descriptor, which is used to communicate through
+ *                I2C
+ *
+ * \return The status whether successfully enabled
+ * \retval -1 The passed parameters were invalid or the device enable failed
+ * \retval 0 The hardware enabling is completed successfully
+ */
+int32_t i2c_m_async_enable(struct i2c_m_async_desc *const i2c);
+
+/**
+ * \brief Async version of disable hardware
+ *
+ * This function disables the I2C master device and then waits for this disabling
+ * operation to be done.
+ *
+ * \param[in] i2c An I2C master descriptor, which is used to communicate through
+ *                I2C
+ *
+ * \return The status whether successfully disabled
+ * \retval -1 The passed parameters were invalid or the device disable failed
+ * \retval 0 The hardware disabling is completed successfully
+ */
+int32_t i2c_m_async_disable(struct i2c_m_async_desc *const i2c);
+
+/**
+ * \brief Async version of the write command to I2C slave
+ *
+ * This function will write the value to a specified register in the I2C slave device,
+ * and then return before the last sub-operation is done.
+ *
+ * The sequence of this routine is
+ * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg
+ * value->nack->stt
+ *
+ * \param[in] i2c An I2C master descriptor, which is used to communicate through
+ *                I2C
+ * \param[in] reg The internal address/register of the I2C slave device
+ * \param[in] value The value write to the I2C slave device
+ *
+ * \return The status whether successfully write to the device
+ * \retval <0 The passed parameters were invalid or write fail
+ * \retval 0 Writing to register is completed successfully
+ */
+int32_t i2c_m_async_cmd_write(struct i2c_m_async_desc *const i2c, uint8_t reg, uint8_t value);
+
+/**
+ * \brief Async version of read register value from the I2C slave
+ *
+ * This function will read a byte value from a specified reg in the I2C slave device
+ * and then return before the last sub-operation is done.
+ *
+ * The sequence of this routine is
+ * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg
+ * value->nack->stt
+ *
+ * \param[in] i2c An I2C master descriptor, which is used to communicate through
+ *                I2C
+ * \param[in] reg The internal address/register of the I2C slave device
+ * \param[in] value The value read from the I2C slave device
+ *
+ * \return The status whether successfully read from the device
+ * \retval <0 The passed parameters were invalid or read fail
+ * \retval 0 Reading from register is completed successfully
+ */
+int32_t i2c_m_async_cmd_read(struct i2c_m_async_desc *const i2c, uint8_t reg, uint8_t *value);
+
+/**
+ * \brief Async version of transfer message to/from I2C slave
+ *
+ * This function will transfer a message between the I2C slave and the master.
+ * This function will not wait for the transfer to complete.
+ *
+ * \param[in] i2c An I2C master descriptor, which is used to communicate through
+ *                I2C
+ * \param[in] msg  An i2c_m_msg struct
+ *
+ * \return The status of the operation
+ * \retval 0 Operation completed successfully
+ * \retval <0 Operation failed
+ */
+int32_t i2c_m_async_transfer(struct i2c_m_async_desc *const i2c, struct _i2c_m_msg *msg);
+
+/**
+ * \brief Generate stop condition on the I2C bus
+ *
+ * This function will generate a stop condition on the I2C bus
+ *
+ * \param[in] i2c An I2C master descriptor, which is used to communicate through
+ *                I2C
+ *
+ * \return Operation status
+ * \retval 0 Operation executed successfully
+ * \retval <0 Operation failed
+ */
+int32_t i2c_m_async_send_stop(struct i2c_m_async_desc *const i2c);
+
+/**
+ * \brief Returns the status during the transfer
+ *
+ * \param[in] i2c An i2c descriptor which is used to communicate through I2C
+ * \param[out] stat Pointer to the detailed status descriptor, set to NULL
+ *
+ * \return Status of transfer
+ * \retval 0 No error detected
+ * \retval <0 Error code
+ */
+int32_t i2c_m_async_get_status(struct i2c_m_async_desc *const i2c, struct i2c_m_async_status *stat);
+
+/**
+ * \brief Return I/O descriptor for this I2C instance
+ *
+ * This function will return an I/O instance for this I2C driver instance
+ *
+ * \param[in] i2c An I2C master descriptor, which is used to communicate through
+ *                I2C
+ * \param[in] io A pointer to an I/O descriptor pointer type
+ *
+ * \return Error code
+ * \retval 0 No error detected
+ * \retval <0 Error code
+ */
+int32_t i2c_m_async_get_io_descriptor(struct i2c_m_async_desc *const i2c, struct io_descriptor **io);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t i2c_m_get_version(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_init.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_init.h
new file mode 100644
index 0000000..d7bc6fe
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_init.h
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief HAL initialization related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_INIT_H_INCLUDED
+#define _HAL_INIT_H_INCLUDED
+
+#include <hpl_init.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_helper_init Init Driver
+ *
+ *@{
+ */
+
+/**
+ * \brief Initialize the hardware abstraction layer
+ *
+ * This function calls the various initialization functions.
+ * Currently the following initialization functions are supported:
+ *  - System clock initialization
+ */
+static inline void init_mcu(void)
+{
+	_init_chip();
+}
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t init_get_version(void);
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HAL_INIT_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_io.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_io.h
new file mode 100644
index 0000000..f50401d
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_io.h
@@ -0,0 +1,110 @@
+/**
+ * \file
+ *
+ * \brief I/O related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_IO_INCLUDED
+#define _HAL_IO_INCLUDED
+
+/**
+ * \addtogroup doc_driver_hal_helper_io I/O Driver
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief I/O descriptor
+ *
+ * The I/O descriptor forward declaration.
+ */
+struct io_descriptor;
+
+/**
+ * \brief I/O write function pointer type
+ */
+typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
+
+/**
+ * \brief I/O read function pointer type
+ */
+typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
+
+/**
+ * \brief I/O descriptor
+ */
+struct io_descriptor {
+	io_write_t write; /*! The write function pointer. */
+	io_read_t  read;  /*! The read function pointer. */
+};
+
+/**
+ * \brief I/O write interface
+ *
+ * This function writes up to \p length of bytes to a given I/O descriptor.
+ * It returns the number of bytes actually write.
+ *
+ * \param[in] descr  An I/O descriptor to write
+ * \param[in] buf    The buffer pointer to story the write data
+ * \param[in] length The number of bytes to write
+ *
+ * \return The number of bytes written
+ */
+int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
+
+/**
+ * \brief I/O read interface
+ *
+ * This function reads up to \p length bytes from a given I/O descriptor, and
+ * stores it in the buffer pointed to by \p buf. It returns the number of bytes
+ * actually read.
+ *
+ * \param[in] descr  An I/O descriptor to read
+ * \param[in] buf    The buffer pointer to story the read data
+ * \param[in] length The number of bytes to read
+ *
+ * \return The number of bytes actually read. This number can be less than the
+ *         requested length. E.g., in a driver that uses ring buffer for
+ *         reception, it may depend on the availability of data in the
+ *         ring buffer.
+ */
+int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HAL_IO_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_pwm.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_pwm.h
new file mode 100644
index 0000000..c8ed842
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_pwm.h
@@ -0,0 +1,151 @@
+/**
+ * \file
+ *
+ * \brief PWM functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef HAL_PWM_H_INCLUDED
+#define HAL_PWM_H_INCLUDED
+
+#include <hpl_pwm.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_pwm_async
+ *
+ *@{
+ */
+
+/**
+ * \brief PWM descriptor
+ *
+ * The PWM descriptor forward declaration.
+ */
+struct pwm_descriptor;
+
+/**
+ * \brief PWM callback type
+ */
+typedef void (*pwm_cb_t)(const struct pwm_descriptor *const descr);
+
+/**
+ * \brief PWM callback types
+ */
+enum pwm_callback_type { PWM_PERIOD_CB, PWM_ERROR_CB };
+
+/**
+ * \brief PWM callbacks
+ */
+struct pwm_callbacks {
+	pwm_cb_t period;
+	pwm_cb_t error;
+};
+
+/** \brief PWM descriptor
+ */
+struct pwm_descriptor {
+	/** PWM device */
+	struct _pwm_device device;
+	/** PWM callback structure */
+	struct pwm_callbacks pwm_cb;
+};
+
+/** \brief Initialize the PWM HAL instance and hardware
+ *
+ *  \param[in] descr Pointer to the HAL PWM descriptor
+ *  \param[in] hw The pointer to hardware instance
+ *  \param[in] func The pointer to a set of functions pointers
+ *
+ *  \return Operation status.
+ */
+int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func);
+
+/** \brief Deinitialize the PWM HAL instance and hardware
+ *
+ *  \param[in] descr Pointer to the HAL PWM descriptor
+ *
+ *  \return Operation status.
+ */
+int32_t pwm_deinit(struct pwm_descriptor *const descr);
+
+/** \brief PWM output start
+ *
+ *  \param[in] descr Pointer to the HAL PWM descriptor
+ *
+ *  \return Operation status.
+ */
+int32_t pwm_enable(struct pwm_descriptor *const descr);
+
+/** \brief PWM output stop
+ *
+ *  \param[in] descr Pointer to the HAL PWM descriptor
+ *
+ *  \return Operation status.
+ */
+int32_t pwm_disable(struct pwm_descriptor *const descr);
+
+/** \brief Register PWM callback
+ *
+ *  \param[in] descr Pointer to the HAL PWM descriptor
+ *  \param[in] type Callback type
+ *  \param[in] cb A callback function, passing NULL de-registers callback
+ *
+ *  \return Operation status.
+ *  \retval 0 Success
+ *  \retval -1 Error
+ */
+int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb);
+
+/** \brief Change PWM parameter
+ *
+ *  \param[in] descr Pointer to the HAL PWM descriptor
+ *  \param[in] period Total period of one PWM cycle
+ *  \param[in] duty_cycle Period of PWM first half during one cycle
+ *
+ *  \return Operation status.
+ */
+int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period,
+                           const pwm_period_t duty_cycle);
+
+/** \brief Get PWM driver version
+ *
+ *  \return Current driver version.
+ */
+uint32_t pwm_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_PWM;_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_qspi_dma.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_qspi_dma.h
new file mode 100644
index 0000000..b3ee49d
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_qspi_dma.h
@@ -0,0 +1,137 @@
+/**
+ * \file
+ *
+ * \brief Quad SPI dma related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_QSPI_DMA_INCLUDED
+#define _HAL_QSPI_DMA_INCLUDED
+
+#include <hpl_qspi_dma.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_quad_spi_dma
+ *
+ *@{
+ */
+
+/**
+ * \brief QSPI descriptor structure
+ */
+struct qspi_dma_descriptor {
+	/** Pointer to QSPI device instance */
+	struct _qspi_dma_dev dev;
+};
+
+/**
+ *  \brief Initialize QSPI low level driver.
+ *
+ *  \param[in] qspi Pointer to the QSPI device instance
+ *  \param[in] hw Pointer to the hardware base
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success
+ */
+int32_t qspi_dma_init(struct qspi_dma_descriptor *qspi, void *hw);
+
+/**
+ *  \brief Deinitialize QSPI low level driver.
+ *
+ *  \param[in] qspi Pointer to the QSPI device instance
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success
+ */
+int32_t qspi_dma_deinit(struct qspi_dma_descriptor *qspi);
+
+/**
+ *  \brief Enable QSPI for access without interrupts
+ *
+ *  \param[in] qspi Pointer to the QSPI device instance.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success
+ */
+int32_t qspi_dma_enable(struct qspi_dma_descriptor *qspi);
+
+/**
+ *  \brief Disable QSPI for access without interrupts
+ *
+ *  Disable QSPI. Deactivate all CS pins if it works as master.
+ *
+ *  \param[in] qspi Pointer to the QSPI device instance.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success
+ */
+int32_t qspi_dma_disable(struct qspi_dma_descriptor *qspi);
+
+/** \brief Execute command in Serial Memory Mode.
+ *
+ *  \param[in] qspi Pointer to the HAL QSPI instance
+ *  \param[in] cmd Pointer to the command structure
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success
+ */
+int32_t qspi_dma_serial_run_command(struct qspi_dma_descriptor *qspi, const struct _qspi_command *cmd);
+
+/** \brief Register a function as QSPI transfer completion callback
+ *
+ *  Register callback function specified by its \c type.
+ *  - QSPI_DMA_CB_XFER_DONE: set the function that will be called on QSPI transfer
+ *    completion including deactivate the CS.
+ *  - QSPI_DMA_CB_ERROR: set the function that will be called on QSPI transfer error.
+ *  Register NULL function to not use the callback.
+ *
+ *  \param[in] qspi Pointer to the HAL QSPI instance
+ *  \param[in] type Callback type (\ref _qspi_dma_cb_type)
+ *  \param[in] cb Pointer to callback function
+ */
+void qspi_dma_register_callback(struct qspi_dma_descriptor *qspi, const enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb);
+
+/**
+ *  \brief Retrieve the current driver version
+ *
+ *  \return Current driver version.
+ */
+uint32_t qspi_dma_get_version(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_QSPI_DMA_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_sleep.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_sleep.h
new file mode 100644
index 0000000..b90ef6a
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_sleep.h
@@ -0,0 +1,74 @@
+/**
+ * \file
+ *
+ * \brief Sleep related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_SLEEP_H_INCLUDED
+#define _HAL_SLEEP_H_INCLUDED
+
+#include <hpl_sleep.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_helper_sleep
+ *
+ *@{
+ */
+
+/**
+ * \brief Set the sleep mode of the device and put the MCU to sleep
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see the data sheet.
+ *
+ * \param[in] mode Sleep mode to use
+ *
+ * \return The status of a sleep request
+ * \retval -1 The requested sleep mode was invalid or not available
+ * \retval  0 The operation completed successfully, returned after leaving the
+ *            sleep
+ */
+int sleep(const uint8_t mode);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t sleep_get_version(void);
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HAL_SLEEP_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_spi_m_dma.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_spi_m_dma.h
new file mode 100644
index 0000000..24e7b11
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_spi_m_dma.h
@@ -0,0 +1,257 @@
+/**
+ * \file
+ *
+ * \brief SPI DMA related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_SPI_M_DMA_H_INCLUDED
+#define _HAL_SPI_M_DMA_H_INCLUDED
+
+#include <hal_io.h>
+#include <hpl_spi_m_dma.h>
+
+/**
+ * \addtogroup doc_driver_hal_spi_master_dma
+ *
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Forward declaration of spi_descriptor. */
+struct spi_m_dma_descriptor;
+
+/** The callback types */
+enum spi_m_dma_cb_type {
+	/** Callback type for DMA transfer buffer done */
+	SPI_M_DMA_CB_TX_DONE,
+	/** Callback type for DMA receive buffer done */
+	SPI_M_DMA_CB_RX_DONE,
+	/** Callback type for DMA errors */
+	SPI_M_DMA_CB_ERROR,
+	SPI_M_DMA_CB_N
+};
+
+/**
+ * \brief SPI Master DMA callback type
+ */
+typedef void (*spi_m_dma_cb_t)(struct _dma_resource *resource);
+
+/** \brief SPI HAL driver struct for DMA access
+ */
+struct spi_m_dma_descriptor {
+	struct _spi_m_dma_hpl_interface *func;
+	/** Pointer to SPI device instance */
+	struct _spi_m_dma_dev dev;
+	/** I/O read/write */
+	struct io_descriptor io;
+	/** DMA resource */
+	struct _dma_resource *resource;
+};
+
+/** \brief Set the SPI HAL instance function pointer for HPL APIs.
+ *
+ *  Set SPI HAL instance function pointer for HPL APIs.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] func Pointer to the HPL api structure.
+ *
+ */
+void spi_m_dma_set_func_ptr(struct spi_m_dma_descriptor *spi, void *const func);
+
+/** \brief Initialize the SPI HAL instance and hardware for DMA mode
+ *
+ *  Initialize SPI HAL with dma mode.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_INVALID_DATA Error, initialized.
+ */
+int32_t spi_m_dma_init(struct spi_m_dma_descriptor *spi, void *const hw);
+
+/** \brief Deinitialize the SPI HAL instance
+ *
+ *  Abort transfer, disable and reset SPI, de-init software.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval <0 Error code.
+ */
+void spi_m_dma_deinit(struct spi_m_dma_descriptor *spi);
+
+/** \brief Enable SPI
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval <0 Error code.
+ */
+void spi_m_dma_enable(struct spi_m_dma_descriptor *spi);
+
+/** \brief Disable SPI
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval <0 Error code.
+ */
+void spi_m_dma_disable(struct spi_m_dma_descriptor *spi);
+
+/** \brief Set SPI baudrate
+ *
+ *  Works if SPI is initialized as master.
+ *  In the function a sanity check is used to confirm it's called in the correct mode.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] baud_val The target baudrate value
+ *                  (See "baudrate calculation" for calculating the value).
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_BUSY Busy.
+ *
+ *  note: This api should be used to write the baudrate register with the given baud_val
+ *  paramter, the user has to calculate the baud_val for required baud rate and pass it as
+ *  argument(baud_val) to this api
+ */
+int32_t spi_m_dma_set_baudrate(struct spi_m_dma_descriptor *spi, const uint32_t baud_val);
+
+/** \brief Set SPI mode
+ *
+ *  Set SPI transfer mode (\ref spi_transfer_mode),
+ * which controls clock polarity and clock phase:
+ *  - Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  - Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  - Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  - Mode 3: leading edge is falling edge, data sample on trailing edge.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] mode The mode (\ref spi_transfer_mode).
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_BUSY Busy, CS activated.
+ */
+int32_t spi_m_dma_set_mode(struct spi_m_dma_descriptor *spi, const enum spi_transfer_mode mode);
+
+/** \brief Set the SPI transfer character size in number of bits
+ *
+ *  The character size (\ref spi_char_size) influence the way the data is
+ *  sent/received.
+ *  For char size <= 8-bit, data is stored byte by byte.
+ *  For char size between 9-bit ~ 16-bit, data is stored in 2-byte length.
+ *  Note that the default and recommended char size is 8-bit since it's
+ *  supported by all system.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] char_size The char size (\ref spi_char_size).
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_BUSY Busy, CS activated.
+ *  \retval ERR_INVALID_ARG The char size is not supported.
+ */
+int32_t spi_m_dma_set_char_size(struct spi_m_dma_descriptor *spi, const enum spi_char_size char_size);
+
+/** \brief Set SPI transfer data order
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] dord The data order: send LSB/MSB first.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_BUSY Busy, CS activated.
+ *  \retval ERR_INVALID The data order is not supported.
+ */
+int32_t spi_m_dma_set_data_order(struct spi_m_dma_descriptor *spi, const enum spi_data_order dord);
+
+/** \brief Perform the SPI data transfer (TX and RX) with the DMA
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] txbuf Pointer to the transfer information.
+ *  \param[out] rxbuf Pointer to the receiver information.
+ *  \param[in] length SPI transfer data length.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_BUSY Busy.
+ */
+int32_t spi_m_dma_transfer(struct spi_m_dma_descriptor *spi, uint8_t const *txbuf, uint8_t *const rxbuf,
+                           const uint16_t length);
+
+/** \brief Register a function as an SPI transfer completion callback
+ *
+ *  Register a callback function specified by its \c type.
+ *  - SPI_CB_COMPLETE: set the function that will be called on the SPI transfer
+ *    completion including deactivating the CS.
+ *  - SPI_CB_XFER: set the function that will be called on the SPI buffer transfer
+ *    completion.
+ *  Register a NULL function to not use the callback.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] type Callback type (\ref spi_m_dma_cb_type).
+ *  \param[in] func Pointer to callback function.
+ */
+void spi_m_dma_register_callback(struct spi_m_dma_descriptor *spi, const enum spi_m_dma_cb_type type,
+                                 spi_m_dma_cb_t func);
+
+/**
+ * \brief Return I/O descriptor for this SPI instance
+ *
+ * This function will return an I/O instance for this SPI driver instance
+ *
+ * \param[in] spi An SPI master descriptor, which is used to communicate through
+ *                SPI
+ * \param[in, out] io A pointer to an I/O descriptor pointer type
+ *
+ * \retval ERR_NONE
+ */
+int32_t spi_m_dma_get_io_descriptor(struct spi_m_dma_descriptor *const spi, struct io_descriptor **io);
+
+/** \brief Retrieve the current driver version
+ *
+ *  \return Current driver version.
+ */
+uint32_t spi_m_dma_get_version(void);
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* ifndef _HAL_SPI_M_DMA_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_spi_m_sync.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_spi_m_sync.h
new file mode 100644
index 0000000..5d04055
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_spi_m_sync.h
@@ -0,0 +1,221 @@
+/**
+ * \file
+ *
+ * \brief SPI related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_SPI_M_SYNC_H_INCLUDED
+#define _HAL_SPI_M_SYNC_H_INCLUDED
+
+#include <hal_io.h>
+#include <hpl_spi_m_sync.h>
+
+/**
+ * \addtogroup doc_driver_hal_spi_master_sync
+ *
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \brief SPI HAL driver struct for polling mode
+ *
+ */
+struct spi_m_sync_descriptor {
+	struct _spi_m_sync_hpl_interface *func;
+	/** SPI device instance */
+	struct _spi_sync_dev dev;
+	/** I/O read/write */
+	struct io_descriptor io;
+	/** Flags for HAL driver */
+	uint16_t flags;
+};
+
+/** \brief Set the SPI HAL instance function pointer for HPL APIs.
+ *
+ *  Set SPI HAL instance function pointer for HPL APIs.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] func Pointer to the HPL api structure.
+ *
+ */
+void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func);
+
+/** \brief Initialize SPI HAL instance and hardware for polling mode
+ *
+ *  Initialize SPI HAL with polling mode.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_INVALID_DATA Error, initialized.
+ */
+int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw);
+
+/** \brief Deinitialize the SPI HAL instance and hardware
+ *
+ *  Abort transfer, disable and reset SPI, deinit software.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval <0 Error code.
+ */
+void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi);
+
+/** \brief Enable SPI
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval <0 Error code.
+ */
+void spi_m_sync_enable(struct spi_m_sync_descriptor *spi);
+
+/** \brief Disable SPI
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval <0 Error code.
+ */
+void spi_m_sync_disable(struct spi_m_sync_descriptor *spi);
+
+/** \brief Set SPI baudrate
+ *
+ *  Works if SPI is initialized as master, it sets the baudrate.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] baud_val The target baudrate value
+ *                  (see "baudrate calculation" for calculating the value).
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_BUSY Busy
+ *  \retval ERR_INVALID_ARG The baudrate is not supported.
+ */
+int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val);
+
+/** \brief Set SPI mode
+ *
+ *  Set the SPI transfer mode (\ref spi_transfer_mode),
+ *  which controls the clock polarity and clock phase:
+ *  - Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  - Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  - Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  - Mode 3: leading edge is falling edge, data sample on trailing edge.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] mode The mode (0~3).
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_BUSY Busy
+ *  \retval ERR_INVALID_ARG The mode is not supported.
+ */
+int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode);
+
+/** \brief Set SPI transfer character size in number of bits
+ *
+ *  The character size (\ref spi_char_size) influence the way the data is
+ *  sent/received.
+ *  For char size <= 8-bit, data is stored byte by byte.
+ *  For char size between 9-bit ~ 16-bit, data is stored in 2-byte length.
+ *  Note that the default and recommended char size is 8-bit since it's
+ *  supported by all system.
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] char_size The char size (~16, recommended 8).
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_BUSY Busy
+ *  \retval ERR_INVALID_ARG The char size is not supported.
+ */
+int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size);
+
+/** \brief Set SPI transfer data order
+ *
+ *  \param[in] spi Pointer to the HAL SPI instance.
+ *  \param[in] dord The data order: send LSB/MSB first.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_BUSY Busy
+ *  \retval ERR_INVALID_ARG The data order is not supported.
+ */
+int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord);
+
+/** \brief Perform the SPI data transfer (TX and RX) in polling way
+ *
+ *  Activate CS, do TX and RX and deactivate CS. It blocks.
+ *
+ *  \param[in, out] spi Pointer to the HAL SPI instance.
+ *  \param[in] xfer Pointer to the transfer information (\ref spi_xfer).
+ *
+ *  \retval size Success.
+ *  \retval >=0 Timeout, with number of characters transferred.
+ *  \retval ERR_BUSY SPI is busy
+ */
+int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *xfer);
+
+/**
+ * \brief Return the I/O descriptor for this SPI instance
+ *
+ * This function will return an I/O instance for this SPI driver instance.
+ *
+ * \param[in] spi An SPI master descriptor, which is used to communicate through
+ *                SPI
+ * \param[in, out] io A pointer to an I/O descriptor pointer type
+ *
+ * \retval ERR_NONE
+ */
+int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io);
+
+/** \brief Retrieve the current driver version
+ *
+ *  \return Current driver version.
+ */
+uint32_t spi_m_sync_get_version(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _HAL_SPI_M_SYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_adc_async.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_adc_async.h
new file mode 100644
index 0000000..1aa4162
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_adc_async.h
@@ -0,0 +1,264 @@
+/**
+ * \file
+ *
+ * \brief ADC related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_ADC_ASYNC_H_INCLUDED
+#define _HPL_ADC_ASYNC_H_INCLUDED
+
+/**
+ * \addtogroup HPL ADC
+ *
+ * \section hpl_async_adc_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include "hpl_adc_sync.h"
+#include "hpl_irq.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief ADC device structure
+ *
+ * The ADC device structure forward declaration.
+ */
+struct _adc_async_device;
+
+/**
+ * \brief ADC callback types
+ */
+enum _adc_async_callback_type { ADC_ASYNC_DEVICE_CONVERT_CB, ADC_ASYNC_DEVICE_MONITOR_CB, ADC_ASYNC_DEVICE_ERROR_CB };
+
+/**
+ * \brief ADC interrupt callbacks
+ */
+struct _adc_async_callbacks {
+	void (*window_cb)(struct _adc_async_device *device, const uint8_t channel);
+	void (*error_cb)(struct _adc_async_device *device, const uint8_t channel);
+};
+
+/**
+ * \brief ADC channel interrupt callbacks
+ */
+struct _adc_async_ch_callbacks {
+	void (*convert_done)(struct _adc_async_device *device, const uint8_t channel, const uint16_t data);
+};
+
+/**
+ * \brief ADC descriptor device structure
+ */
+struct _adc_async_device {
+	struct _adc_async_callbacks    adc_async_cb;
+	struct _adc_async_ch_callbacks adc_async_ch_cb;
+	struct _irq_descriptor         irq;
+	void *                         hw;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize synchronous ADC
+ *
+ * This function does low level ADC configuration.
+ *
+ * param[in] device The pointer to ADC device instance
+ * param[in] hw     The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_async_deinit(struct _adc_async_device *const device);
+
+/**
+ * \brief Enable ADC peripheral
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel);
+
+/**
+ * \brief Disable ADC peripheral
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel);
+
+/**
+ * \brief Retrieve ADC conversion data size
+ *
+ * \param[in] device The pointer to ADC device instance
+ *
+ * \return The data size in bytes
+ */
+uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device);
+
+/**
+ * \brief Check if conversion is done
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ *
+ * \return The status of conversion
+ * \retval true The conversion is done
+ * \retval false The conversion is not done
+ */
+bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel);
+
+/**
+ * \brief Make conversion
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_async_convert(struct _adc_async_device *const device);
+
+/**
+ * \brief Retrieve the conversion result
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ *
+ * The result value
+ */
+uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel);
+
+/**
+ * \brief Set reference source
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] reference A reference source to set
+ */
+void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference);
+
+/**
+ * \brief Set resolution
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] resolution A resolution to set
+ */
+void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * \param[in] device    The pointer to ADC device instance
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ */
+void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
+                           const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set conversion mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode A conversion mode to set
+ */
+void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set differential mode
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ */
+void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
+                                              const enum adc_differential_mode mode);
+
+/**
+ * \brief Set gain
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ * \param[in] gain     A gain to set
+ */
+void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain);
+
+/**
+ * \brief Set window mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode   A mode to set
+ */
+void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode);
+
+/**
+ * \brief Set lower threshold
+ *
+ * \param[in] device        The pointer to ADC device instance
+ * \param[in] low_threshold  A lower threshold to set
+ * \param[in] up_threshold   An upper thresholds to set
+ */
+void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
+                               const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[out] state The threshold state
+ */
+void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state);
+
+/**
+ * \brief Enable/disable ADC channel interrupt
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ * \param[in] type     The type of interrupt to disable/enable if applicable
+ * \param[in] state    Enable or disable
+ */
+void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
+                              const enum _adc_async_callback_type type, const bool state);
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_ADC_ASYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_adc_dma.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_adc_dma.h
new file mode 100644
index 0000000..bb3a054
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_adc_dma.h
@@ -0,0 +1,243 @@
+/**
+ * \file
+ *
+ * \brief ADC related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_ADC_DMA_H_INCLUDED
+#define _HPL_ADC_DMA_H_INCLUDED
+
+/**
+ * \addtogroup HPL ADC
+ *
+ * \section hpl_dma_adc_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <hpl_adc_sync.h>
+#include <hpl_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief ADC device structure
+ *
+ * The ADC device structure forward declaration.
+ */
+struct _adc_dma_device;
+
+/**
+ * \brief ADC callback types
+ */
+enum _adc_dma_callback_type { ADC_DMA_DEVICE_COMPLETE_CB, ADC_DMA_DEVICE_ERROR_CB };
+
+/**
+ * \brief ADC interrupt callbacks
+ */
+struct _adc_dma_callbacks {
+	void (*complete)(struct _adc_dma_device *device, const uint16_t data);
+	void (*error)(struct _adc_dma_device *device);
+};
+
+/**
+ * \brief ADC descriptor device structure
+ */
+struct _adc_dma_device {
+	struct _adc_dma_callbacks adc_dma_cb;
+	struct _irq_descriptor    irq;
+	void *                    hw;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize synchronous ADC
+ *
+ * This function does low level ADC configuration.
+ *
+ * param[in] device The pointer to ADC device instance
+ * param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_dma_deinit(struct _adc_dma_device *const device);
+
+/**
+ * \brief Enable ADC peripheral
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel);
+
+/**
+ * \brief Disable ADC peripheral
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel);
+
+/**
+ * \brief Return address of ADC DMA source
+ *
+ * \param[in] device The pointer to ADC device instance
+ *
+ * \return ADC DMA source address
+ */
+uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device);
+
+/**
+ * \brief Retrieve ADC conversion data size
+ *
+ * \param[in] device The pointer to ADC device instance
+ *
+ * \return The data size in bytes
+ */
+uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device);
+
+/**
+ * \brief Check if conversion is done
+ *
+ * \param[in] device   The pointer to ADC device instance
+ *
+ * \return The status of conversion
+ * \retval true The conversion is done
+ * \retval false The conversion is not done
+ */
+bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device);
+
+/**
+ * \brief Make conversion
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_dma_convert(struct _adc_dma_device *const device);
+
+/**
+ * \brief Set reference source
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] reference A reference source to set
+ */
+void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference);
+
+/**
+ * \brief Set resolution
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] resolution A resolution to set
+ */
+void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * \param[in] device    The pointer to ADC device instance
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ */
+void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input,
+                         const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set conversion mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode A conversion mode to set
+ */
+void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set differential mode
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ */
+void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel,
+                                            const enum adc_differential_mode mode);
+
+/**
+ * \brief Set gain
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ * \param[in] gain    A gain to set
+ */
+void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain);
+
+/**
+ * \brief Set window mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode A mode to set
+ */
+void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode);
+
+/**
+ * \brief Set thresholds
+ *
+ * \param[in] device        The pointer to ADC device instance
+ * \param[in] low_threshold A lower thresholds to set
+ * \param[in] up_threshold  An upper thresholds to set
+ */
+void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold,
+                             const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[out] state The threshold state
+ */
+void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state);
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_ADC_DMA_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_adc_sync.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_adc_sync.h
new file mode 100644
index 0000000..3bfbc61
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_adc_sync.h
@@ -0,0 +1,271 @@
+/**
+ * \file
+ *
+ * \brief ADC related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_ADC_SYNC_H_INCLUDED
+#define _HPL_ADC_SYNC_H_INCLUDED
+
+/**
+ * \addtogroup HPL ADC
+ *
+ * \section hpl_adc_sync_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief ADC reference source
+ */
+typedef uint8_t adc_reference_t;
+
+/**
+ * \brief ADC resolution
+ */
+typedef uint8_t adc_resolution_t;
+
+/**
+ * \brief ADC positive input for channel
+ */
+typedef uint8_t adc_pos_input_t;
+
+/**
+ * \brief ADC negative input for channel
+ */
+typedef uint8_t adc_neg_input_t;
+
+/**
+ * \brief ADC threshold
+ */
+typedef uint16_t adc_threshold_t;
+
+/**
+ * \brief ADC gain
+ */
+typedef uint8_t adc_gain_t;
+
+/**
+ * \brief ADC conversion mode
+ */
+enum adc_conversion_mode { ADC_CONVERSION_MODE_SINGLE_CONVERSION = 0, ADC_CONVERSION_MODE_FREERUN };
+
+/**
+ * \brief ADC differential mode
+ */
+enum adc_differential_mode { ADC_DIFFERENTIAL_MODE_SINGLE_ENDED = 0, ADC_DIFFERENTIAL_MODE_DIFFERENTIAL };
+
+/**
+ * \brief ADC window mode
+ */
+typedef uint8_t adc_window_mode_t;
+
+/**
+ * \brief ADC threshold status
+ */
+typedef bool adc_threshold_status_t;
+
+/**
+ * \brief ADC sync descriptor device structure
+ */
+struct _adc_sync_device {
+	void *hw;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize synchronous ADC
+ *
+ * This function does low level ADC configuration.
+ *
+ * param[in] device The pointer to ADC device instance
+ * param[in] hw     The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_sync_deinit(struct _adc_sync_device *const device);
+
+/**
+ * \brief Enable ADC
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel);
+
+/**
+ * \brief Disable ADC
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel);
+
+/**
+ * \brief Retrieve ADC conversion data size
+ *
+ * \param[in] device The pointer to ADC device instance
+ *
+ * \return The data size in bytes
+ */
+uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device);
+
+/**
+ * \brief Check if conversion is done
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ *
+ * \return The status of conversion
+ * \retval true The conversion is done
+ * \retval false The conversion is not done
+ */
+bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel);
+
+/**
+ * \brief Make conversion
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_sync_convert(struct _adc_sync_device *const device);
+
+/**
+ * \brief Retrieve the conversion result
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ *
+ * \return The result value of channel
+ */
+uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel);
+
+/**
+ * \brief Set reference source
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] reference A reference source to set
+ */
+void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference);
+
+/**
+ * \brief Set resolution
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] resolution A resolution to set
+ */
+void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * \param[in] device    The pointer to ADC device instance
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ */
+void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
+                          const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set conversion mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode A conversion mode to set
+ */
+void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set differential mode
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ */
+void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
+                                             const enum adc_differential_mode mode);
+
+/**
+ * \brief Set gain
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ * \param[in] gain     A gain to set
+ */
+void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain);
+
+/**
+ * \brief Set window mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode   A mode to set
+ */
+void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode);
+
+/**
+ * \brief Set threshold
+ *
+ * \param[in] device        The pointer to ADC device instance
+ * \param[in] low_threshold  A lower threshold to set
+ * \param[in] up_threshold   An upper thresholds to set
+ */
+void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
+                              const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[out] state The threshold state
+ */
+void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_ADC_SYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_cmcc.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_cmcc.h
new file mode 100644
index 0000000..cb26091
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_cmcc.h
@@ -0,0 +1,277 @@
+/**
+ * \file
+ *
+ * \brief Generic CMCC(Cortex M Cache Controller) related functionality.
+ *
+ * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".  NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef HPL_CMCC_H_
+#define HPL_CMCC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * \Cache driver MACROS
+ */
+#define CMCC_DISABLE 0U
+#define CMCC_ENABLE 1U
+#define IS_CMCC_DISABLED 0U
+#define IS_CMCC_ENABLED 1U
+#define CMCC_WAY_NOS 4U
+#define CMCC_LINE_NOS 64U
+#define CMCC_MONITOR_DISABLE 0U
+
+/**
+ * \brief Cache size configurations
+ */
+enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB };
+
+/**
+ * \brief Way Numbers
+ */
+enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 };
+
+/**
+ * \brief Cache monitor configurations
+ */
+enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT };
+
+/**
+ * \brief Cache configuration structure
+ */
+struct _cache_cfg {
+	enum conf_cache_size cache_size;
+	bool                 data_cache_disable;
+	bool                 inst_cache_disable;
+	bool                 gclk_gate_disable;
+};
+
+/**
+ * \brief Cache enable status
+ */
+static inline bool _is_cache_enabled(const void *hw)
+{
+	return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false);
+}
+
+/**
+ * \brief Cache disable status
+ */
+static inline bool _is_cache_disabled(const void *hw)
+{
+	return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false);
+}
+
+/**
+ * \brief Cache enable
+ */
+static inline int32_t _cmcc_enable(const void *hw)
+{
+	int32_t return_value;
+
+	if (_is_cache_disabled(hw)) {
+		hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN);
+		return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE;
+	} else {
+		return_value = ERR_NO_CHANGE;
+	}
+
+	return return_value;
+}
+
+/**
+ * \brief Cache disable
+ */
+static inline int32_t _cmcc_disable(const void *hw)
+{
+	hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos));
+	while (!(_is_cache_disabled(hw)))
+		;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Initialize Cache Module
+ *
+ * This function initialize low level cmcc module configuration.
+ *
+ * \return initialize status
+ */
+int32_t _cmcc_init(void);
+
+/**
+ * \brief Configure CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] cache configuration structure pointer
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl);
+
+/**
+ * \brief Enable data cache in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_enable_data_cache(const void *hw, bool value);
+
+/**
+ * \brief Enable instruction cache in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_enable_inst_cache(const void *hw, bool value);
+
+/**
+ * \brief Enable clock gating in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_enable_clock_gating(const void *hw, bool value);
+
+/**
+ * \brief Configure the cache size in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from cache size configuration enumerator
+ *				0->1K, 1->2K, 2->4K(default)
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size);
+
+/**
+ * \brief Lock the mentioned WAY in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from "way_num_index" enumerator
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_lock_way(const void *hw, enum way_num_index);
+
+/**
+ * \brief Unlock the mentioned WAY in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from "way_num_index" enumerator
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_unlock_way(const void *hw, enum way_num_index);
+
+/**
+ * \brief Invalidate the mentioned cache line in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from "way_num" enumerator (valid arg is 0-3)
+ * \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num);
+
+/**
+ * \brief Invalidate entire cache entries in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_invalidate_all(const void *hw);
+
+/**
+ * \brief Configure cache monitor in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from cache monitor configurations enumerator
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg);
+
+/**
+ * \brief Enable cache monitor in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_enable_monitor(const void *hw);
+
+/**
+ * \brief Disable cache monitor in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_disable_monitor(const void *hw);
+
+/**
+ * \brief Reset cache monitor in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_reset_monitor(const void *hw);
+
+/**
+ * \brief Get cache monitor event counter value from CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return event counter value
+ */
+uint32_t _cmcc_get_monitor_event_count(const void *hw);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* HPL_CMCC_H_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_core.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_core.h
new file mode 100644
index 0000000..9324c43
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_core.h
@@ -0,0 +1,56 @@
+/**
+ * \file
+ *
+ * \brief CPU core related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_CORE_H_INCLUDED
+#define _HPL_CORE_H_INCLUDED
+
+/**
+ * \addtogroup HPL Core
+ *
+ * \section hpl_core_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include "hpl_core_port.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_CORE_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_custom_logic.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_custom_logic.h
new file mode 100644
index 0000000..e9cc1df
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_custom_logic.h
@@ -0,0 +1,69 @@
+/**
+ * \file
+ *
+ * \brief Custom Control Logic functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_CUSTOM_LOGIC_H_INCLUDED
+#define _HPL_CUSTOM_LOGIC_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *  \brief Initialize the custom logic hardware
+ *  \return Initialization operation status
+ */
+int32_t _custom_logic_init(void);
+
+/**
+ *  \brief Disable and reset the custom logic hardware
+ */
+void _custom_logic_deinit(void);
+
+/**
+ *  \brief Enable the custom logic hardware
+ *  \return Initialization operation status
+ */
+int32_t _custom_logic_enable(void);
+
+/**
+ *  \brief Disable the custom logic hardware
+ */
+void _custom_logic_disable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_CUSTOM_LOGIC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_delay.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_delay.h
new file mode 100644
index 0000000..a0f1ac8
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_delay.h
@@ -0,0 +1,97 @@
+/**
+ * \file
+ *
+ * \brief Delay related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_DELAY_H_INCLUDED
+#define _HPL_DELAY_H_INCLUDED
+
+/**
+ * \addtogroup HPL Delay
+ *
+ * \section hpl_delay_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#ifndef _UNIT_TEST_
+#include <compiler.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name HPL functions
+ */
+//@{
+
+/**
+ * \brief Initialize delay functionality
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+void _delay_init(void *const hw);
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of us
+ *
+ * \param[in] us The amount of us to delay for
+ *
+ * \return The amount of cycles
+ */
+uint32_t _get_cycles_for_us(const uint16_t us);
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of ms
+ *
+ * \param[in] ms The amount of ms to delay for
+ *
+ * \return The amount of cycles
+ */
+uint32_t _get_cycles_for_ms(const uint16_t ms);
+
+/**
+ * \brief Delay loop to delay n number of cycles
+ *
+ * \param[in] hw The pointer to hardware instance
+ * \param[in] cycles The amount of cycles to delay for
+ */
+void _delay_cycles(void *const hw, uint32_t cycles);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_DELAY_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_dma.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_dma.h
new file mode 100644
index 0000000..1e08434
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_dma.h
@@ -0,0 +1,176 @@
+/**
+ * \file
+ *
+ * \brief DMA related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_DMA_H_INCLUDED
+#define _HPL_DMA_H_INCLUDED
+
+/**
+ * \addtogroup HPL DMA
+ *
+ * \section hpl_dma_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+#include <hpl_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct _dma_resource;
+
+/**
+ * \brief DMA callback types
+ */
+enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB };
+
+/**
+ * \brief DMA interrupt callbacks
+ */
+struct _dma_callbacks {
+	void (*transfer_done)(struct _dma_resource *resource);
+	void (*error)(struct _dma_resource *resource);
+};
+
+/**
+ * \brief DMA resource structure
+ */
+struct _dma_resource {
+	struct _dma_callbacks dma_cb;
+	void *                back;
+};
+
+/**
+ * \brief Initialize DMA
+ *
+ * This function does low level DMA configuration.
+ *
+ * \return initialize status
+ */
+int32_t _dma_init(void);
+
+/**
+ * \brief Set destination address
+ *
+ * \param[in] channel DMA channel to set destination address for
+ * \param[in] dst Destination address
+ *
+ * \return setting status
+ */
+int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst);
+
+/**
+ * \brief Set source address
+ *
+ * \param[in] channel DMA channel to set source address for
+ * \param[in] src Source address
+ *
+ * \return setting status
+ */
+int32_t _dma_set_source_address(const uint8_t channel, const void *const src);
+
+/**
+ * \brief Set next descriptor address
+ *
+ * \param[in] current_channel Current DMA channel to set next descriptor address
+ * \param[in] next_channel Next DMA channel used as next descriptor
+ *
+ * \return setting status
+ */
+int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel);
+
+/**
+ * \brief Enable/disable source address incrementation during DMA transaction
+ *
+ * \param[in] channel DMA channel to set source address for
+ * \param[in] enable True to enable, false to disable
+ *
+ * \return status of operation
+ */
+int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable);
+
+/**
+ * \brief Enable/disable Destination address incrementation during DMA transaction
+ *
+ * \param[in] channel DMA channel to set destination address for
+ * \param[in] enable True to enable, false to disable
+ *
+ * \return status of operation
+ */
+int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable);
+/**
+ * \brief Set the amount of data to be transfered per transaction
+ *
+ * \param[in] channel DMA channel to set data amount for
+ * \param[in] amount Data amount
+ *
+ * \return status of operation
+ */
+int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount);
+
+/**
+ * \brief Trigger DMA transaction on the given channel
+ *
+ * \param[in] channel DMA channel to trigger transaction on
+ *
+ * \return status of operation
+ */
+int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger);
+
+/**
+ * \brief Retrieves DMA resource structure
+ *
+ * \param[out] resource The resource to be retrieved
+ * \param[in] channel DMA channel to retrieve structure for
+ *
+ * \return status of operation
+ */
+int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel);
+
+/**
+ * \brief Enable/disable DMA interrupt
+ *
+ * \param[in] channel DMA channel to enable/disable interrupt for
+ * \param[in] type The type of interrupt to disable/enable if applicable
+ * \param[in] state Enable or disable
+ */
+void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HPL_DMA_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_evsys.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_evsys.h
new file mode 100644
index 0000000..e7fc7b4
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_evsys.h
@@ -0,0 +1,94 @@
+/**
+ * \file
+ *
+ * \brief Event system related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_EVSYS_H_INCLUDED
+#define _HPL_EVSYS_H_INCLUDED
+
+/**
+ * \addtogroup HPL EVSYS
+ *
+ * \section hpl_eveys_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Initialize event system.
+ *
+ * \return Status of operation.
+ */
+int32_t _event_system_init(void);
+
+/**
+ * \brief Deinitialize event system.
+ *
+ * \return Status of operation.
+ */
+int32_t _event_system_deinit(void);
+
+/**
+ * \brief Enable/disable event reception by the given user from the given
+ *        channel
+ *
+ * \param[in] user A user to enable
+ * \param[in] channel A channel the user is assigned to
+ * \param[in] on true to enable, false to disable
+ *
+ * \return Status of operation.
+ */
+int32_t _event_system_enable_user(const uint16_t user, const uint16_t channel, const bool on);
+
+/**
+ * \brief Enable/disable event generation by the given generator for the given
+ *        channel
+ *
+ * \param[in] generator A generator to enable
+ * \param[in] channel A channel the user is assigned to
+ * \param[in] on true to enable, false to disable
+ *
+ * \return Status of operation.
+ */
+int32_t _event_system_enable_generator(const uint16_t generator, const uint16_t channel, const bool on);
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_EVSYS_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_ext_irq.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_ext_irq.h
new file mode 100644
index 0000000..3a169b6
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_ext_irq.h
@@ -0,0 +1,95 @@
+/**
+ * \file
+ *
+ * \brief External IRQ related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_EXT_IRQ_H_INCLUDED
+#define _HPL_EXT_IRQ_H_INCLUDED
+
+/**
+ * \addtogroup HPL EXT IRQ
+ *
+ * \section hpl_ext_irq_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize external interrupt module
+ *
+ * This function does low level external interrupt configuration.
+ *
+ * \param[in] cb The pointer to callback function from external interrupt
+ *
+ * \return Initialization status.
+ * \retval -1 External irq module is already initialized
+ * \retval 0 The initialization is completed successfully
+ */
+int32_t _ext_irq_init(void (*cb)(const uint32_t pin));
+
+/**
+ * \brief Deinitialize external interrupt module
+ *
+ * \return Initialization status.
+ * \retval -1 External irq module is already deinitialized
+ * \retval 0 The de-initialization is completed successfully
+ */
+int32_t _ext_irq_deinit(void);
+
+/**
+ * \brief Enable / disable external irq
+ *
+ * \param[in] pin Pin to enable external irq on
+ * \param[in] enable True to enable, false to disable
+ *
+ * \return Status of external irq enabling / disabling
+ * \retval -1 External irq module can't be enabled / disabled
+ * \retval 0 External irq module is enabled / disabled successfully
+ */
+int32_t _ext_irq_enable(const uint32_t pin, const bool enable);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_EXT_IRQ_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_gpio.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_gpio.h
new file mode 100644
index 0000000..5cdd387
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_gpio.h
@@ -0,0 +1,185 @@
+/**
+ * \file
+ *
+ * \brief Port related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_GPIO_H_INCLUDED
+#define _HPL_GPIO_H_INCLUDED
+
+/**
+ * \addtogroup HPL Port
+ *
+ * \section hpl_port_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+ * \brief Macros for the pin and port group, lower 5
+ * bits stands for pin number in the group, higher 3
+ * bits stands for port group
+ */
+#define GPIO_PIN(n) (((n)&0x1Fu) << 0)
+#define GPIO_PORT(n) ((n) >> 5)
+#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu))
+#define GPIO_PIN_FUNCTION_OFF 0xffffffff
+
+/**
+ * \brief PORT pull mode settings
+ */
+enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN };
+
+/**
+ * \brief PORT direction settins
+ */
+enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT };
+
+/**
+ * \brief PORT group abstraction
+ */
+
+enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE };
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Port initialization function
+ *
+ * Port initialization function should setup the port module based
+ * on a static configuration file, this function should normally
+ * not be called directly, but is a part of hal_init()
+ */
+void _gpio_init(void);
+
+/**
+ * \brief Set direction on port with mask
+ *
+ * Set data direction for each pin, or disable the pin
+ *
+ * \param[in] port      Ports are grouped into groups of maximum 32 pins,
+ *                      GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask      Bit mask where 1 means apply direction setting to the
+ *                      corresponding pin
+ * \param[in] direction GPIO_DIRECTION_OFF  = set pin direction to input
+ *                      and disable input buffer to disable the pin
+ *                      GPIO_DIRECTION_IN   = set pin direction to input
+ *                      and enable input buffer to enable the pin
+ *                      GPIO_DIRECTION_OUT  = set pin direction to output
+ *                      and disable input buffer
+ */
+static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
+                                       const enum gpio_direction direction);
+
+/**
+ * \brief Set output level on port with mask
+ *
+ * Sets output state on pin to high or low with pin masking
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask  Bit mask where 1 means apply direction setting to
+ *                  the corresponding pin
+ * \param[in] level true  = pin level is set to 1
+ *                  false = pin level is set to 0
+ */
+static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level);
+
+/**
+ * \brief Change output level to the opposite with mask
+ *
+ * Change pin output level to the opposite with pin masking
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask  Bit mask where 1 means apply direction setting to
+ *                  the corresponding pin
+ */
+static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask);
+
+/**
+ * \brief Get input levels on all port pins
+ *
+ * Get input level on all port pins, will read IN register if configured to
+ * input and OUT register if configured as output
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ */
+static inline uint32_t _gpio_get_level(const enum gpio_port port);
+
+/**
+ * \brief Set pin pull mode
+ *
+ * Set pull mode on a single pin
+ *
+ * \notice This function will automatically change pin direction to input
+ *
+ * \param[in] port      Ports are grouped into groups of maximum 32 pins,
+ *                      GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] pin       The pin in the group that pull mode should be selected
+ *                      for
+ * \param[in] pull_mode GPIO_PULL_OFF  = pull resistor on pin is disabled
+ *                      GPIO_PULL_DOWN = pull resistor on pin will pull pin
+ *                      level to ground level
+ *                      GPIO_PULL_UP   = pull resistor on pin will pull pin
+ *                      level to VCC
+ */
+static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
+                                           const enum gpio_pull_mode pull_mode);
+
+/**
+ * \brief Set gpio function
+ *
+ * Select which function a gpio is used for
+ *
+ * \param[in] gpio     The gpio to set function for
+ * \param[in] function The gpio function is given by a 32-bit wide bitfield
+ *                     found in the header files for the device
+ *
+ */
+static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function);
+
+#include <hpl_gpio_base.h>
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_GPIO_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_m_async.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_m_async.h
new file mode 100644
index 0000000..8a9491d
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_m_async.h
@@ -0,0 +1,205 @@
+/**
+ * \file
+ *
+ * \brief I2C Master Hardware Proxy Layer(HPL) declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED
+#define _HPL_I2C_M_ASYNC_H_INCLUDED
+
+#include "hpl_i2c_m_sync.h"
+#include "hpl_irq.h"
+#include "utils.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief i2c master callback names
+ */
+enum _i2c_m_async_callback_type {
+	I2C_M_ASYNC_DEVICE_ERROR,
+	I2C_M_ASYNC_DEVICE_TX_COMPLETE,
+	I2C_M_ASYNC_DEVICE_RX_COMPLETE
+};
+
+struct _i2c_m_async_device;
+
+typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev);
+typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode);
+
+/**
+ * \brief i2c callback pointers structure
+ */
+struct _i2c_m_async_callback {
+	_i2c_error_cb_t    error;
+	_i2c_complete_cb_t tx_complete;
+	_i2c_complete_cb_t rx_complete;
+};
+
+/**
+ * \brief i2c device structure
+ */
+struct _i2c_m_async_device {
+	struct _i2c_m_service        service;
+	void *                       hw;
+	struct _i2c_m_async_callback cb;
+	struct _irq_descriptor       irq;
+};
+
+/**
+ * \name HPL functions
+ */
+
+/**
+ * \brief Initialize I2C in interrupt mode
+ *
+ * This function does low level I2C configuration.
+ *
+ * \param[in] i2c_dev The pointer to i2c interrupt device structure
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw);
+
+/**
+ * \brief Deinitialize I2C in interrupt mode
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev);
+
+/**
+ * \brief Enable I2C module
+ *
+ * This function does low level I2C enable.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev);
+
+/**
+ * \brief Disable I2C module
+ *
+ * This function does low level I2C disable.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev);
+
+/**
+ * \brief Transfer data by I2C
+ *
+ * This function does low level I2C data transfer.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ * \param[in] msg The pointer to i2c msg structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg);
+
+/**
+ * \brief Set baud rate of I2C
+ *
+ * This function does low level I2C set baud rate.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ * \param[in] clkrate The clock rate(KHz) input to i2c module
+ * \param[in] baudrate The demand baud rate(KHz) of i2c module
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
+
+/**
+ * \brief Register callback to I2C
+ *
+ * This function does low level I2C callback register.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ * \param[in] cb_type The callback type request
+ * \param[in] func The callback function pointer
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type,
+                                       FUNC_PTR func);
+
+/**
+ * \brief Generate stop condition on the I2C bus
+ *
+ * This function will generate a stop condition on the I2C bus
+ *
+ * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
+ *
+ * \return Operation status
+ * \retval 0 Operation executed successfully
+ * \retval <0 Operation failed
+ */
+int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev);
+
+/**
+ * \brief Returns the number of bytes left or not used in the I2C message buffer
+ *
+ * This function will return the number of bytes left (not written to the bus) or still free
+ * (not received from the bus) in the message buffer, depending on direction of transmission.
+ *
+ * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
+ *
+ * \return Number of bytes or error code
+ * \retval >0 Positive number indicating bytes left
+ * \retval 0  Buffer is full/empty depending on direction
+ * \retval <0 Error code
+ */
+int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev);
+
+/**
+ * \brief Enable/disable I2C master interrupt
+ *
+ * param[in] device The pointer to I2C master device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] state Enable or disable
+ */
+void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type,
+                                const bool state);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_m_sync.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_m_sync.h
new file mode 100644
index 0000000..ce173ae
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_m_sync.h
@@ -0,0 +1,185 @@
+/**
+ * \file
+ *
+ * \brief I2C Master Hardware Proxy Layer(HPL) declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _HPL_I2C_M_SYNC_H_INCLUDED
+#define _HPL_I2C_M_SYNC_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief i2c flags
+ */
+#define I2C_M_RD 0x0001 /* read data, from slave to master */
+#define I2C_M_BUSY 0x0100
+#define I2C_M_TEN 0x0400   /* this is a ten bit chip address */
+#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */
+#define I2C_M_FAIL 0x1000
+#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+
+/**
+ * \brief i2c Return codes
+ */
+#define I2C_OK 0                     /* Operation successful */
+#define I2C_ACK -1                   /* Received ACK from device on I2C bus */
+#define I2C_NACK -2                  /* Received NACK from device on I2C bus */
+#define I2C_ERR_ARBLOST -3           /* Arbitration lost */
+#define I2C_ERR_BAD_ADDRESS -4       /* Bad address */
+#define I2C_ERR_BUS -5               /* Bus error */
+#define I2C_ERR_BUSY -6              /* Device busy */
+#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */
+
+/**
+ * \brief i2c I2C Modes
+ */
+#define I2C_STANDARD_MODE 0x00
+#define I2C_FASTMODE 0x01
+#define I2C_HIGHSPEED_MODE 0x02
+
+/**
+ * \brief i2c master message structure
+ */
+struct _i2c_m_msg {
+	uint16_t          addr;
+	volatile uint16_t flags;
+	int32_t           len;
+	uint8_t *         buffer;
+};
+
+/**
+ * \brief i2c master service
+ */
+struct _i2c_m_service {
+	struct _i2c_m_msg msg;
+	uint16_t          mode;
+	uint16_t          trise;
+};
+
+/**
+ * \brief i2c sync master device structure
+ */
+struct _i2c_m_sync_device {
+	struct _i2c_m_service service;
+	void *                hw;
+};
+
+/**
+ * \name HPL functions
+ */
+
+/**
+ * \brief Initialize I2C
+ *
+ * This function does low level I2C configuration.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw);
+
+/**
+ * \brief Deinitialize I2C
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev);
+
+/**
+ * \brief Enable I2C module
+ *
+ * This function does low level I2C enable.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev);
+
+/**
+ * \brief Disable I2C module
+ *
+ * This function does low level I2C disable.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev);
+
+/**
+ * \brief Transfer data by I2C
+ *
+ * This function does low level I2C data transfer.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ * \param[in] msg The pointer to i2c msg structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg);
+
+/**
+ * \brief Set baud rate of I2C
+ *
+ * This function does low level I2C set baud rate.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ * \param[in] clkrate The clock rate(KHz) input to i2c module
+ * \param[in] baudrate The demand baud rate(KHz) of i2c module
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
+
+/**
+ * \brief Send send condition on the I2C bus
+ *
+ * This function will generate a stop condition on the I2C bus
+ *
+ * \param[in] i2c_dev The pointer to i2c device struct
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_s_async.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_s_async.h
new file mode 100644
index 0000000..92a5765
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_s_async.h
@@ -0,0 +1,184 @@
+/**
+ * \file
+ *
+ * \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED
+#define _HPL_I2C_S_ASYNC_H_INCLUDED
+
+#include "hpl_i2c_s_sync.h"
+#include "hpl_irq.h"
+#include "utils.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief i2c callback types
+ */
+enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE };
+
+/**
+ * \brief Forward declaration of I2C Slave device
+ */
+struct _i2c_s_async_device;
+
+/**
+ * \brief i2c slave callback function type
+ */
+typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device);
+
+/**
+ * \brief i2c slave callback pointers structure
+ */
+struct _i2c_s_async_callback {
+	void (*error)(struct _i2c_s_async_device *const device);
+	void (*tx)(struct _i2c_s_async_device *const device);
+	void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data);
+};
+
+/**
+ * \brief i2c slave device structure
+ */
+struct _i2c_s_async_device {
+	void *                       hw;
+	struct _i2c_s_async_callback cb;
+	struct _irq_descriptor       irq;
+};
+
+/**
+ * \name HPL functions
+ */
+
+/**
+ * \brief Initialize asynchronous I2C slave
+ *
+ * This function does low level I2C configuration.
+ *
+ * \param[in] device The pointer to i2c interrupt device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize asynchronous I2C in interrupt mode
+ *
+ * \param[in] device The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device);
+
+/**
+ * \brief Enable I2C module
+ *
+ * This function does low level I2C enable.
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device);
+
+/**
+ * \brief Disable I2C module
+ *
+ * This function does low level I2C disable.
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device);
+
+/**
+ * \brief Check if 10-bit addressing mode is on
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Cheking status
+ * \retval 1 10-bit addressing mode is on
+ * \retval 0 10-bit addressing mode is off
+ */
+int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device);
+
+/**
+ * \brief Set I2C slave address
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ * \param[in] address Address to set
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address);
+
+/**
+ * \brief Write a byte to the given I2C instance
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ * \param[in] data Data to write
+ */
+void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data);
+
+/**
+ * \brief Retrieve I2C slave status
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ *\return I2C slave status
+ */
+i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device);
+
+/**
+ * \brief Abort data transmission
+ *
+ * \param[in] device The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device);
+
+/**
+ * \brief Enable/disable I2C slave interrupt
+ *
+ * param[in] device The pointer to I2C slave device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] disable Enable or disable
+ */
+int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type,
+                                   const bool disable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_s_sync.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_s_sync.h
new file mode 100644
index 0000000..93b5934
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_i2c_s_sync.h
@@ -0,0 +1,184 @@
+/**
+ * \file
+ *
+ * \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _HPL_I2C_S_SYNC_H_INCLUDED
+#define _HPL_I2C_S_SYNC_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief I2C Slave status type
+ */
+typedef uint32_t i2c_s_status_t;
+
+/**
+ * \brief i2c slave device structure
+ */
+struct _i2c_s_sync_device {
+	void *hw;
+};
+
+#include <compiler.h>
+
+/**
+ * \name HPL functions
+ */
+
+/**
+ * \brief Initialize synchronous I2C slave
+ *
+ * This function does low level I2C configuration.
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize synchronous I2C slave
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Enable I2C module
+ *
+ * This function does low level I2C enable.
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Disable I2C module
+ *
+ * This function does low level I2C disable.
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Check if 10-bit addressing mode is on
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Cheking status
+ * \retval 1 10-bit addressing mode is on
+ * \retval 0 10-bit addressing mode is off
+ */
+int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Set I2C slave address
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ * \param[in] address Address to set
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address);
+
+/**
+ * \brief Write a byte to the given I2C instance
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ * \param[in] data Data to write
+ */
+void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data);
+
+/**
+ * \brief Retrieve I2C slave status
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ *\return I2C slave status
+ */
+i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Clear the Data Ready interrupt flag
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Read a byte from the given I2C instance
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Data received via I2C interface.
+ */
+uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Check if I2C is ready to send next byte
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Status of the ready check.
+ * \retval true if the I2C is ready to send next byte
+ * \retval false if the I2C is not ready to send next byte
+ */
+bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Check if there is data received by I2C
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Status of the data received check.
+ * \retval true if the I2C has received a byte
+ * \retval false if the I2C has not received a byte
+ */
+bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_init.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_init.h
new file mode 100644
index 0000000..71bf49c
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_init.h
@@ -0,0 +1,124 @@
+/**
+ * \file
+ *
+ * \brief Init related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_INIT_H_INCLUDED
+#define _HPL_INIT_H_INCLUDED
+
+/**
+ * \addtogroup HPL Init
+ *
+ * \section hpl_init_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initializes clock sources
+ */
+void _sysctrl_init_sources(void);
+
+/**
+ * \brief Initializes Power Manager
+ */
+void _pm_init(void);
+
+/**
+ * \brief Initialize generators
+ */
+void _gclk_init_generators(void);
+
+/**
+ * \brief Initialize 32 kHz clock sources
+ */
+void _osc32kctrl_init_sources(void);
+
+/**
+ * \brief Initialize clock sources
+ */
+void _oscctrl_init_sources(void);
+
+/**
+ * \brief Initialize clock sources that need input reference clocks
+ */
+void _sysctrl_init_referenced_generators(void);
+
+/**
+ * \brief Initialize clock sources that need input reference clocks
+ */
+void _oscctrl_init_referenced_generators(void);
+
+/**
+ * \brief Initialize master clock generator
+ */
+void _mclk_init(void);
+
+/**
+ * \brief Initialize clock generator
+ */
+void _lpmcu_misc_regs_init(void);
+
+/**
+ * \brief Initialize clock generator
+ */
+void _pmc_init(void);
+
+/**
+ * \brief Set performance level
+ *
+ * \param[in] level The performance level to set
+ */
+void _set_performance_level(const uint8_t level);
+
+/**
+ * \brief Initialize the chip
+ */
+void _init_chip(void);
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_INIT_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_irq.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_irq.h
new file mode 100644
index 0000000..2894944
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_irq.h
@@ -0,0 +1,116 @@
+/**
+ * \file
+ *
+ * \brief IRQ related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_IRQ_H_INCLUDED
+#define _HPL_IRQ_H_INCLUDED
+
+/**
+ * \addtogroup HPL IRQ
+ *
+ * \section hpl_irq_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief IRQ descriptor
+ */
+struct _irq_descriptor {
+	void (*handler)(void *parameter);
+	void *parameter;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Retrieve current IRQ number
+ *
+ * \return The current IRQ number
+ */
+uint8_t _irq_get_current(void);
+
+/**
+ * \brief Disable the given IRQ
+ *
+ * \param[in] n The number of IRQ to disable
+ */
+void _irq_disable(uint8_t n);
+
+/**
+ * \brief Set the given IRQ
+ *
+ * \param[in] n The number of IRQ to set
+ */
+void _irq_set(uint8_t n);
+
+/**
+ * \brief Clear the given IRQ
+ *
+ * \param[in] n The number of IRQ to clear
+ */
+void _irq_clear(uint8_t n);
+
+/**
+ * \brief Enable the given IRQ
+ *
+ * \param[in] n The number of IRQ to enable
+ */
+void _irq_enable(uint8_t n);
+
+/**
+ * \brief Register IRQ handler
+ *
+ * \param[in] number The number registered IRQ
+ * \param[in] irq The pointer to irq handler to register
+ *
+ * \return The status of IRQ handler registering
+ * \retval -1 Passed parameters were invalid
+ * \retval 0 The registering is completed successfully
+ */
+void _irq_register(const uint8_t number, struct _irq_descriptor *const irq);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_IRQ_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_missing_features.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_missing_features.h
new file mode 100644
index 0000000..7071db2
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_missing_features.h
@@ -0,0 +1,37 @@
+/**
+ * \file
+ *
+ * \brief Family-dependent missing features expected by HAL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_MISSING_FEATURES
+#define _HPL_MISSING_FEATURES
+
+#endif /* _HPL_MISSING_FEATURES */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_pwm.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_pwm.h
new file mode 100644
index 0000000..ff87052
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_pwm.h
@@ -0,0 +1,193 @@
+/**
+ * \file
+ *
+ * \brief PWM related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _HPL_PWM_H_INCLUDED
+#define _HPL_PWM_H_INCLUDED
+
+/**
+ * \addtogroup HPL PWM
+ *
+ * \section hpl_pwm_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+#include "hpl_irq.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief PWM callback types
+ */
+enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB };
+
+/**
+ * \brief PWM pulse-width period
+ */
+typedef uint32_t pwm_period_t;
+
+/**
+ * \brief PWM device structure
+ *
+ * The PWM device structure forward declaration.
+ */
+struct _pwm_device;
+
+/**
+ * \brief PWM interrupt callbacks
+ */
+struct _pwm_callback {
+	void (*pwm_period_cb)(struct _pwm_device *device);
+	void (*pwm_error_cb)(struct _pwm_device *device);
+};
+
+/**
+ * \brief PWM descriptor device structure
+ */
+struct _pwm_device {
+	struct _pwm_callback   callback;
+	struct _irq_descriptor irq;
+	void *                 hw;
+};
+
+/**
+ * \brief PWM functions, pointers to low-level functions
+ */
+struct _pwm_hpl_interface {
+	int32_t (*init)(struct _pwm_device *const device, void *const hw);
+	void (*deinit)(struct _pwm_device *const device);
+	void (*start_pwm)(struct _pwm_device *const device);
+	void (*stop_pwm)(struct _pwm_device *const device);
+	void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
+	bool (*is_pwm_enabled)(const struct _pwm_device *const device);
+	pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device);
+	uint32_t (*pwm_get_duty)(const struct _pwm_device *const device);
+	void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
+};
+/**
+ * \brief Initialize TC
+ *
+ * This function does low level TC configuration.
+ *
+ * \param[in] device The pointer to PWM device instance
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status.
+ */
+int32_t _pwm_init(struct _pwm_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize TC
+ *
+ * \param[in] device The pointer to PWM device instance
+ */
+void _pwm_deinit(struct _pwm_device *const device);
+
+/**
+ * \brief Retrieve offset of the given tc hardware instance
+ *
+ * \param[in] device The pointer to PWM device instance
+ *
+ * \return The offset of the given tc hardware instance
+ */
+uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device);
+
+/**
+ * \brief Start hardware pwm
+ *
+ * \param[in] device The pointer to PWM device instance
+ */
+void _pwm_enable(struct _pwm_device *const device);
+
+/**
+ * \brief Stop hardware pwm
+ *
+ * \param[in] device The pointer to PWM device instance
+ */
+void _pwm_disable(struct _pwm_device *const device);
+
+/**
+ * \brief Set pwm parameter
+ *
+ * \param[in] device The pointer to PWM device instance
+ * \param[in] period Total period of one PWM cycle.
+ * \param[in] duty_cycle Period of PWM first half during one cycle.
+ */
+void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
+
+/**
+ * \brief Check if pwm is working
+ *
+ * \param[in] device The pointer to PWM device instance
+ *
+ * \return Check status.
+ * \retval true The given pwm is working
+ * \retval false The given pwm is not working
+ */
+bool _pwm_is_enabled(const struct _pwm_device *const device);
+
+/**
+ * \brief Get pwm waveform period value
+ *
+ * \param[in] device The pointer to PWM device instance
+ *
+ * \return Period value.
+ */
+pwm_period_t _pwm_get_period(const struct _pwm_device *const device);
+
+/**
+ * \brief Get pwm waveform duty cycle value
+ *
+ * \param[in] device The pointer to PWM device instance
+ *
+ * \return Duty cycle value
+ */
+uint32_t _pwm_get_duty(const struct _pwm_device *const device);
+
+/**
+ * \brief Enable/disable PWM interrupt
+ *
+ * param[in] device The pointer to PWM device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] disable Enable or disable
+ */
+void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_PWM_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_qspi.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_qspi.h
new file mode 100644
index 0000000..f95ac3b
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_qspi.h
@@ -0,0 +1,149 @@
+/**
+ * \file
+ *
+ * \brief Quad SPI related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_QSPI_H_INCLUDED
+#define _HPL_QSPI_H_INCLUDED
+
+#include "compiler.h"
+
+/**
+ * \addtogroup hpl_qspi HPL QSPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Qspi access modes
+ */
+enum qspi_access {
+	/* Read access */
+	QSPI_READ_ACCESS = 0,
+	/* Read memory access */
+	QSPI_READMEM_ACCESS,
+	/* Write access */
+	QSPI_WRITE_ACCESS,
+	/* Write memory access */
+	QSPI_WRITEMEM_ACCESS
+};
+
+/**
+ * \brief QSPI command instruction/address/data width
+ */
+enum qspi_cmd_width {
+	/** Instruction: Single-bit, Address: Single-bit, Data: Single-bit */
+	QSPI_INST1_ADDR1_DATA1,
+	/** Instruction: Single-bit, Address: Single-bit, Data: Dual-bit */
+	QSPI_INST1_ADDR1_DATA2,
+	/** Instruction: Single-bit, Address: Single-bit, Data: Quad-bit */
+	QSPI_INST1_ADDR1_DATA4,
+	/** Instruction: Single-bit, Address: Dual-bit, Data: Dual-bit */
+	QSPI_INST1_ADDR2_DATA2,
+	/** Instruction: Single-bit, Address: Quad-bit, Data: Quad-bit */
+	QSPI_INST1_ADDR4_DATA4,
+	/** Instruction: Dual-bit, Address: Dual-bit, Data: Dual-bit */
+	QSPI_INST2_ADDR2_DATA2,
+	/** Instruction: Quad-bit, Address: Quad-bit, Data: Quad-bit */
+	QSPI_INST4_ADDR4_DATA4
+};
+
+/**
+ * \brief QSPI command option code length in bits
+ */
+enum qspi_cmd_opt_len {
+	/** The option code is 1 bit long */
+	QSPI_OPT_1BIT,
+	/** The option code is 2 bits long */
+	QSPI_OPT_2BIT,
+	/** The option code is 4 bits long */
+	QSPI_OPT_4BIT,
+	/** The option code is 8 bits long */
+	QSPI_OPT_8BIT
+};
+
+/**
+ * \brief Qspi command structure
+ */
+struct _qspi_command {
+	union {
+		struct {
+			/* Width of QSPI Addr , inst data */
+			uint32_t width : 3;
+			/* Reserved */
+			uint32_t reserved0 : 1;
+			/* Enable Instruction */
+			uint32_t inst_en : 1;
+			/* Enable Address */
+			uint32_t addr_en : 1;
+			/* Enable Option */
+			uint32_t opt_en : 1;
+			/* Enable Data */
+			uint32_t data_en : 1;
+			/* Option Length */
+			uint32_t opt_len : 2;
+			/* Address Length */
+			uint32_t addr_len : 1;
+			/* Option Length */
+			uint32_t reserved1 : 1;
+			/* Transfer type */
+			uint32_t tfr_type : 2;
+			/* Continuous read mode */
+			uint32_t continues_read : 1;
+			/* Enable Double Data Rate */
+			uint32_t ddr_enable : 1;
+			/* Dummy Cycles Length */
+			uint32_t dummy_cycles : 5;
+			/* Reserved */
+			uint32_t reserved3 : 11;
+		} bits;
+		uint32_t word;
+	} inst_frame;
+
+	uint8_t  instruction;
+	uint8_t  option;
+	uint32_t address;
+
+	size_t      buf_len;
+	const void *tx_buf;
+	void *      rx_buf;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_QSPI_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_qspi_dma.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_qspi_dma.h
new file mode 100644
index 0000000..7c6019a
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_qspi_dma.h
@@ -0,0 +1,146 @@
+/**
+ * \file
+ *
+ * \brief Quad SPI dma related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_QSPI_DMA_H_INCLUDED
+#define _HPL_QSPI_DMA_H_INCLUDED
+
+#include <hpl_qspi.h>
+#include "hpl_irq.h"
+#include "hpl_dma.h"
+
+/**
+ * \addtogroup hpl_qspi_dma HPL QSPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** The callback types */
+enum _qspi_dma_cb_type {
+	/** Callback type for DMA transfer done */
+	QSPI_DMA_CB_XFER_DONE,
+	/** Callback type for DMA errors */
+	QSPI_DMA_CB_ERROR,
+};
+
+/**
+ * \brief QSPI DMA callback type
+ */
+typedef void (*_qspi_dma_cb_t)(struct _dma_resource *resource);
+
+/**
+ *  \brief The callbacks offered by QSPI driver
+ */
+struct _qspi_dma_callbacks {
+	_qspi_dma_cb_t xfer_done;
+	_qspi_dma_cb_t error;
+};
+
+/**
+ * QSPI dma driver instance.
+ */
+struct _qspi_dma_dev {
+	/** Pointer to private data or hardware base */
+	void *prvt;
+	/**
+	 *  Pointer to the callback functions so that initialize the driver to
+	 *  handle interrupts.
+	 */
+	struct _qspi_dma_callbacks cb;
+	/** DMA resource */
+	struct _dma_resource *resource;
+};
+
+/**
+ *  \brief Initialize QSPI for access without interrupts
+ *  It will load default hardware configuration and software struct.
+ *  \param[in, out] dev Pointer to the QSPI device instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *  \return Operation status.
+ *  \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_dma_init(struct _qspi_dma_dev *dev, void *const hw);
+
+/**
+ *  \brief Deinitialize QSPI
+ *  Disable, reset the hardware and the software struct.
+ *  \param[in, out] dev Pointer to the QSPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_dma_deinit(struct _qspi_dma_dev *dev);
+
+/**
+ *  \brief Enable QSPI for access without interrupts
+ *  \param[in, out] dev Pointer to the QSPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_dma_enable(struct _qspi_dma_dev *dev);
+
+/**
+ *  \brief Disable QSPI for access without interrupts
+ *  \param[in, out] dev Pointer to the QSPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_dma_disable(struct _qspi_dma_dev *dev);
+
+/**
+ * \brief Execute command in Serial Memory Mode.
+ *
+ * \param[in] dev The pointer to QSPI device instance
+ * \param[in] cmd The pointer to the command information
+ *  \return Operation status.
+ *  \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_dma_serial_run_command(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd);
+
+/**
+ *  \brief Register the QSPI device callback
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \param[in] type The callback type.
+ *  \param[in] cb The callback function to register. NULL to disable callback.
+ *  \return Always 0.
+ */
+void _qspi_dma_register_callback(struct _qspi_dma_dev *dev, const enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_QSPI_DMA_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_qspi_sync.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_qspi_sync.h
new file mode 100644
index 0000000..6958e10
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_qspi_sync.h
@@ -0,0 +1,105 @@
+/**
+ * \file
+ *
+ * \brief Quad SPI Sync related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_QSPI_SYNC_H_INCLUDED
+#define _HPL_QSPI_SYNC_H_INCLUDED
+
+#include <hpl_qspi.h>
+
+/**
+ * \addtogroup hpl_qspi HPL QSPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Quad SPI polling driver instance. */
+struct _qspi_sync_dev {
+	/** Pointer to private data or hardware base */
+	void *prvt;
+};
+
+/**
+ *  \brief Initialize QSPI for access without interrupts
+ *  It will load default hardware configuration and software struct.
+ *  \param[in, out] dev Pointer to the QSPI device instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *  \return Operation status.
+ *  \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_sync_init(struct _qspi_sync_dev *dev, void *const hw);
+
+/**
+ *  \brief Deinitialize QSPI
+ *  Disable, reset the hardware and the software struct.
+ *  \param[in, out] dev Pointer to the QSPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_sync_deinit(struct _qspi_sync_dev *dev);
+
+/**
+ *  \brief Enable QSPI for access without interrupts
+ *  \param[in, out] dev Pointer to the QSPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_sync_enable(struct _qspi_sync_dev *dev);
+
+/**
+ *  \brief Disable QSPI for access without interrupts
+ *  \param[in, out] dev Pointer to the QSPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_sync_disable(struct _qspi_sync_dev *dev);
+
+/**
+ * \brief Execute command in Serial Memory Mode.
+ *
+ * \param[in] dev The pointer to QSPI device instance
+ * \param[in] cmd The pointer to the command information
+ *  \return Operation status.
+ *  \retval ERR_NONE Operation done successfully.
+ */
+int32_t _qspi_sync_serial_run_command(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_QSPI_SYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_ramecc.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_ramecc.h
new file mode 100644
index 0000000..d79d514
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_ramecc.h
@@ -0,0 +1,100 @@
+/**
+ * \file
+ *
+ * \brief RAMECC related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_RAMECC_H_INCLUDED
+#define _HPL_RAMECC_H_INCLUDED
+
+/**
+ * \addtogroup HPL RAMECC
+ *
+ * \section hpl_ramecc_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+#include <hpl_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief RAMECC callback type
+ */
+typedef void (*ramecc_cb_t)(const uint32_t data);
+
+/**
+ * \brief RAMECC callback types
+ */
+enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB };
+
+/**
+ * \brief RAMECC interrupt callbacks
+ */
+struct _ramecc_callbacks {
+	ramecc_cb_t dual_bit_err;
+	ramecc_cb_t single_bit_err;
+};
+
+/**
+ * \brief RAMECC device structure
+ */
+struct _ramecc_device {
+	struct _ramecc_callbacks ramecc_cb;
+	struct _irq_descriptor   irq;
+};
+
+/**
+ * \brief Initialize RAMECC
+ *
+ * This function does low level RAMECC configuration.
+ *
+ * \return initialize status
+ */
+int32_t _ramecc_init(void);
+
+/**
+ * \brief Register RAMECC callback
+ *
+ * \param[in] type The type of callback
+ * \param[in] cb A callback function
+ */
+void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_RAMECC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_reset.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_reset.h
new file mode 100644
index 0000000..d627ea6
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_reset.h
@@ -0,0 +1,93 @@
+/**
+ * \file
+ *
+ * \brief Reset related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_RESET_H_INCLUDED
+#define _HPL_RESET_H_INCLUDED
+
+/**
+ * \addtogroup HPL Reset
+ *
+ * \section hpl_reset_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#ifndef _UNIT_TEST_
+#include <compiler.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Reset reason enumeration
+ *
+ * The list of possible reset reasons.
+ */
+enum reset_reason {
+	RESET_REASON_POR    = 1,
+	RESET_REASON_BOD12  = 2,
+	RESET_REASON_BOD33  = 4,
+	RESET_REASON_NVM    = 8,
+	RESET_REASON_EXT    = 16,
+	RESET_REASON_WDT    = 32,
+	RESET_REASON_SYST   = 64,
+	RESET_REASON_BACKUP = 128
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Retrieve the reset reason
+ *
+ * Retrieves the reset reason of the last MCU reset.
+ *
+ *\return An enum value indicating the reason of the last reset.
+ */
+enum reset_reason _get_reset_reason(void);
+
+/**
+ * \brief Reset MCU
+ */
+void _reset_mcu(void);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_RESET_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_sleep.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_sleep.h
new file mode 100644
index 0000000..6731ec3
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_sleep.h
@@ -0,0 +1,88 @@
+/**
+ * \file
+ *
+ * \brief Sleep related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SLEEP_H_INCLUDED
+#define _HPL_SLEEP_H_INCLUDED
+
+/**
+ * \addtogroup HPL Sleep
+ *
+ * \section hpl_sleep_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#ifndef _UNIT_TEST_
+#include <compiler.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Set the sleep mode for the device
+ *
+ * This function sets the sleep mode for the device.
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes see datasheet.
+ *
+ * \param[in] mode Sleep mode to use
+ *
+ * \return the status of a sleep request
+ * \retval -1 The requested sleep mode was invalid
+ * \retval  0 The operation completed successfully, sleep mode is set
+ */
+int32_t _set_sleep_mode(const uint8_t mode);
+
+/**
+ * \brief Reset MCU
+ */
+void _reset_mcu(void);
+
+/**
+ * \brief Put MCU to sleep
+ */
+void _go_to_sleep(void);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_SLEEP_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi.h
new file mode 100644
index 0000000..a5652e5
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi.h
@@ -0,0 +1,163 @@
+/**
+ * \file
+ *
+ * \brief SPI related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_H_INCLUDED
+#define _HPL_SPI_H_INCLUDED
+
+#include <compiler.h>
+#include <utils.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief SPI Dummy char is used when reading data from the SPI slave
+ */
+#define SPI_DUMMY_CHAR 0x1ff
+
+/**
+ *  \brief SPI message to let driver to process
+ */
+//@{
+struct spi_msg {
+	/** Pointer to the output data buffer */
+	uint8_t *txbuf;
+	/** Pointer to the input data buffer */
+	uint8_t *rxbuf;
+	/** Size of the message data in SPI characters */
+	uint32_t size;
+};
+//@}
+
+/**
+ *  \brief SPI transfer modes
+ *  SPI transfer mode controls clock polarity and clock phase.
+ *  Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  Mode 3: leading edge is falling edge, data sample on trailing edge.
+ */
+enum spi_transfer_mode {
+	/** Leading edge is rising edge, data sample on leading edge. */
+	SPI_MODE_0,
+	/** Leading edge is rising edge, data sample on trailing edge. */
+	SPI_MODE_1,
+	/** Leading edge is falling edge, data sample on leading edge. */
+	SPI_MODE_2,
+	/** Leading edge is falling edge, data sample on trailing edge. */
+	SPI_MODE_3
+};
+
+/**
+ *  \brief SPI character sizes
+ *  The character size influence the way the data is sent/received.
+ *  For char size <= 8 data is stored byte by byte.
+ *  For char size between 9 ~ 16 data is stored in 2-byte length.
+ *  Note that the default and recommended char size is 8 bit since it's
+ *  supported by all system.
+ */
+enum spi_char_size {
+	/** Character size is 8 bit. */
+	SPI_CHAR_SIZE_8 = 0,
+	/** Character size is 9 bit. */
+	SPI_CHAR_SIZE_9 = 1,
+	/** Character size is 10 bit. */
+	SPI_CHAR_SIZE_10 = 2,
+	/** Character size is 11 bit. */
+	SPI_CHAR_SIZE_11 = 3,
+	/** Character size is 12 bit. */
+	SPI_CHAR_SIZE_12 = 4,
+	/** Character size is 13 bit. */
+	SPI_CHAR_SIZE_13 = 5,
+	/** Character size is 14 bit. */
+	SPI_CHAR_SIZE_14 = 6,
+	/** Character size is 15 bit. */
+	SPI_CHAR_SIZE_15 = 7,
+	/** Character size is 16 bit. */
+	SPI_CHAR_SIZE_16 = 8
+};
+
+/**
+ *  \brief SPI data order
+ */
+enum spi_data_order {
+	/** MSB goes first. */
+	SPI_DATA_ORDER_MSB_1ST = 0,
+	/** LSB goes first. */
+	SPI_DATA_ORDER_LSB_1ST = 1
+};
+
+/** \brief Transfer descriptor for SPI
+ *  Transfer descriptor holds TX and RX buffers
+ */
+struct spi_xfer {
+	/** Pointer to data buffer to TX */
+	uint8_t *txbuf;
+	/** Pointer to data buffer to RX */
+	uint8_t *rxbuf;
+	/** Size of data characters to TX & RX */
+	uint32_t size;
+};
+
+/** SPI generic driver. */
+struct spi_dev {
+	/** Pointer to the hardware base or private data for special device. */
+	void *prvt;
+	/** Reference start of sync/async variables */
+	uint32_t sync_async_misc[1];
+};
+
+/**
+ *  \brief Calculate the baudrate value for hardware to use to set baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] clk Clock frequency (Hz) for baudrate generation.
+ *  \param[in] baud Target baudrate (bps).
+ *  \return Error or baudrate value.
+ *  \retval >0 Baudrate value.
+ *  \retval ERR_INVALID_ARG Calculation fail.
+ */
+int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_async.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_async.h
new file mode 100644
index 0000000..8e5a848
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_async.h
@@ -0,0 +1,131 @@
+/**
+ * \file
+ *
+ * \brief Common SPI related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_ASYNC_H_INCLUDED
+#define _HPL_SPI_ASYNC_H_INCLUDED
+
+#include <hpl_spi.h>
+#include <hpl_irq.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *  \brief Callbacks the SPI driver must offer in async mode
+ */
+//@{
+/** The callback types */
+enum _spi_async_dev_cb_type {
+	/** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */
+	SPI_DEV_CB_TX,
+	/** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */
+	SPI_DEV_CB_RX,
+	/** Callback type for \ref _spi_async_dev_cb_complete_t. */
+	SPI_DEV_CB_COMPLETE,
+	/** Callback type for error */
+	SPI_DEV_CB_ERROR,
+	/** Number of callbacks. */
+	SPI_DEV_CB_N
+};
+
+struct _spi_async_dev;
+
+/** \brief The prototype for callback on SPI transfer error.
+ *  If status code is zero, it indicates the normal completion, that is,
+ *  SS deactivation.
+ *  If status code belows zero, it indicates complete.
+ */
+typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status);
+
+/** \brief The prototype for callback on SPI transmit/receive event
+ *  For TX, the callback is invoked when transmit is done or ready to start
+ *  transmit.
+ *  For RX, the callback is invoked when receive is done or ready to read data,
+ *  see \ref _spi_async_dev_read_one_t on data reading.
+ *  Without DMA enabled, the callback is invoked on each character event.
+ *  With DMA enabled, the callback is invoked on DMA buffer done.
+ */
+typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev);
+
+/**
+ *  \brief The callbacks offered by SPI driver
+ */
+struct _spi_async_dev_callbacks {
+	/** TX callback, see \ref _spi_async_dev_cb_xfer_t. */
+	_spi_async_dev_cb_xfer_t tx;
+	/** RX callback, see \ref _spi_async_dev_cb_xfer_t. */
+	_spi_async_dev_cb_xfer_t rx;
+	/** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */
+	_spi_async_dev_cb_xfer_t complete;
+	/** Error callback, see \ref */
+	_spi_async_dev_cb_error_t err;
+};
+//@}
+
+/**
+ *  \brief SPI async driver
+ */
+//@{
+
+/** SPI driver to support async HAL */
+struct _spi_async_dev {
+	/** Pointer to the hardware base or private data for special device. */
+	void *prvt;
+	/** Data size, number of bytes for each character */
+	uint8_t char_size;
+	/** Dummy byte used in master mode when reading the slave */
+	uint16_t dummy_byte;
+
+	/** \brief Pointer to callback functions, ignored for polling mode
+	 *  Pointer to the callback functions so that initialize the driver to
+	 *  handle interrupts.
+	 */
+	struct _spi_async_dev_callbacks callbacks;
+	/** IRQ instance for SPI device. */
+	struct _irq_descriptor irq;
+};
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_dma.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_dma.h
new file mode 100644
index 0000000..04a3015
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_dma.h
@@ -0,0 +1,88 @@
+/**
+ * \file
+ *
+ * \brief Common SPI DMA related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_DMA_H_INCLUDED
+#define _HPL_SPI_DMA_H_INCLUDED
+
+#include <hpl_irq.h>
+#include <hpl_dma.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** The callback types */
+enum _spi_dma_dev_cb_type {
+	/** Callback type for DMA transmit. */
+	SPI_DEV_CB_DMA_TX,
+	/** Callback type for DMA receive. */
+	SPI_DEV_CB_DMA_RX,
+	/** Callback type for DMA error. */
+	SPI_DEV_CB_DMA_ERROR,
+	/** Number of callbacks. */
+	SPI_DEV_CB_DMA_N
+};
+
+struct _spi_dma_dev;
+
+/**
+ *  \brief The prototype for callback on SPI DMA.
+ */
+typedef void (*_spi_dma_cb_t)(struct _dma_resource *resource);
+
+/**
+ *  \brief The callbacks offered by SPI driver
+ */
+struct _spi_dma_dev_callbacks {
+	_spi_dma_cb_t tx;
+	_spi_dma_cb_t rx;
+	_spi_dma_cb_t error;
+};
+
+/** SPI driver to support DMA HAL */
+struct _spi_dma_dev {
+	/** Pointer to the hardware base or private data for special device. */
+	void *prvt;
+	/** Pointer to callback functions */
+	struct _spi_dma_dev_callbacks callbacks;
+	/** IRQ instance for SPI device. */
+	struct _irq_descriptor irq;
+	/** DMA resource */
+	struct _dma_resource *resource;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _HPL_SPI_DMA_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_m_async.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_m_async.h
new file mode 100644
index 0000000..8d3555e
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_m_async.h
@@ -0,0 +1,243 @@
+/**
+ * \file
+ *
+ * \brief SPI Slave Async related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED
+#define _HPL_SPI_M_ASYNC_H_INCLUDED
+
+#include <hpl_spi.h>
+#include <hpl_spi_async.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Uses common SPI async device driver. */
+#define _spi_m_async_dev _spi_async_dev
+
+#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type
+
+/** Uses common SPI async device driver complete callback type. */
+#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
+
+/** Uses common SPI async device driver transfer callback type. */
+#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  It will load default hardware configuration and software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval ERR_DENIED SPI has been enabled.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw);
+
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  Disable, reset the hardware and the software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev);
+
+/**
+ *  \brief Enable SPI for access with interrupts
+ *  Enable the SPI and enable callback generation of receive and error
+ *  interrupts.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev);
+
+/**
+ *  \brief Disable SPI for access without interrupts
+ *  Disable SPI and interrupts. Deactivate all CS pins if works as master.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev);
+
+/**
+ *  \brief Set SPI transfer mode
+ *  Set SPI transfer mode (\ref spi_transfer_mode),
+ *  which controls clock polarity and clock phase.
+ *  Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  Mode 3: leading edge is falling edge, data sample on trailing edge.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] mode The SPI transfer mode.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
+ *                  how it's generated.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] char_size The character size, see \ref spi_char_size.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size);
+
+/**
+ *  \brief Set SPI data order
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] dord SPI data order (LSB/MSB first).
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord);
+
+/**
+ * \brief Enable interrupt on character output
+ *
+ * Enable interrupt when a new character can be written
+ * to the SPI device.
+ *
+ * \param[in] dev   Pointer to the SPI device instance
+ * \param[in] state true  = enable output interrupt
+ *                  false = disable output interrupt
+ *
+ * \return Status code
+ * \retval 0 Ok status
+ */
+int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state);
+
+/**
+ * \brief Enable interrupt on character input
+ *
+ * Enable interrupt when a new character is ready to be
+ * read from the SPI device.
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ * \param[in] state true  = enable input interrupts
+ *                  false = disable input interrupt
+ *
+ * \return Status code
+ * \retvat 0 OK Status
+ */
+int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state);
+
+/**
+ * \brief Enable interrupt on after data transmission complate
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ * \param[in] state true  = enable input interrupts
+ *                  false = disable input interrupt
+ *
+ * \return Status code
+ * \retvat 0 OK Status
+ */
+int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state);
+
+/**
+ *  \brief Read one character to SPI device instance
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *
+ *  \return Character read from SPI module
+ */
+uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev);
+
+/**
+ *  \brief Write one character to assigned buffer
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] data
+ *
+ *  \return Status code of write operation
+ *  \retval 0 Write operation OK
+ */
+int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data);
+
+/**
+ *  \brief Register the SPI device callback
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] cb_type The callback type.
+ *  \param[in] func The callback function to register. NULL to disable callback.
+ *  \return Always 0.
+ */
+int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type,
+                                       const FUNC_PTR func);
+
+/**
+ * \brief Enable/disable SPI master interrupt
+ *
+ * param[in] device The pointer to SPI master device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] state Enable or disable
+ */
+void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type,
+                                const bool state);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_m_dma.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_m_dma.h
new file mode 100644
index 0000000..2b48300
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_m_dma.h
@@ -0,0 +1,182 @@
+/**
+ * \file
+ *
+ * \brief SPI Master DMA related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_M_DMA_H_INCLUDED
+#define _HPL_SPI_M_DMA_H_INCLUDED
+
+#include <hpl_spi.h>
+#include <hpl_spi_dma.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Uses common SPI dma device driver. */
+#define _spi_m_dma_dev _spi_dma_dev
+
+#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  It will load default hardware configuration and software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval ERR_DENIED SPI has been enabled.
+ *  \retval 0 ERR_NONE is operation done successfully.
+ */
+int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw);
+
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  Disable, reset the hardware and the software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 ERR_NONE is operation done successfully.
+ */
+int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev);
+
+/**
+ *  \brief Enable SPI for access with interrupts
+ *  Enable the SPI and enable callback generation of receive and error
+ *  interrupts.
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval 0 ERR_NONE is operation done successfully.
+ */
+int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev);
+
+/**
+ *  \brief Disable SPI for access without interrupts
+ *  Disable SPI and interrupts. Deactivate all CS pins if works as master.
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 ERR_NONE is operation done successfully.
+ */
+int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev);
+
+/**
+ *  \brief Set SPI transfer mode
+ *  Set SPI transfer mode (\ref spi_transfer_mode),
+ *  which controls clock polarity and clock phase.
+ *  Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  Mode 3: leading edge is falling edge, data sample on trailing edge.
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \param[in] mode The SPI transfer mode.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 ERR_NONE is operation done successfully.
+ */
+int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
+ *                  how it's generated.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] char_size The character size, see \ref spi_char_size.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size);
+
+/**
+ *  \brief Set SPI data order
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \param[in] dord SPI data order (LSB/MSB first).
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord);
+
+/**
+ *  \brief Register the SPI device callback
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \param[in] cb_type The callback type.
+ *  \param[in] func The callback function to register. NULL to disable callback.
+ *  \return Always 0.
+ */
+void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func);
+
+/** \brief Do SPI data transfer (TX & RX) with DMA
+ *  Log the TX & RX buffers and transfer them in background. It never blocks.
+ *
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \param[in] txbuf Pointer to the transfer information (\ref spi_transfer).
+ *  \param[out] rxbuf Pointer to the receiver information (\ref spi_receive).
+ *  \param[in] length spi transfer data length.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_BUSY Busy.
+ */
+int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf,
+                            const uint16_t length);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_m_sync.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_m_sync.h
new file mode 100644
index 0000000..38df15b
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_m_sync.h
@@ -0,0 +1,166 @@
+/**
+ * \file
+ *
+ * \brief SPI related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_M_SYNC_H_INCLUDED
+#define _HPL_SPI_M_SYNC_H_INCLUDED
+
+#include <hpl_spi.h>
+#include <hpl_spi_sync.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Uses common SPI sync device driver. */
+#define _spi_m_sync_dev _spi_sync_dev
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ *  \brief Initialize SPI for access without interrupts
+ *  It will load default hardware configuration and software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval ERR_DENIED SPI has been enabled.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw);
+
+/**
+ *  \brief Deinitialize SPI
+ *  Disable, reset the hardware and the software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev);
+
+/**
+ *  \brief Enable SPI for access without interrupts
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev);
+
+/**
+ *  \brief Disable SPI for access without interrupts
+ *  Disable SPI. Deactivate all CS pins if works as master.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev);
+
+/**
+ *  \brief Set SPI transfer mode
+ *  Set SPI transfer mode (\ref spi_transfer_mode),
+ *  which controls clock polarity and clock phase.
+ *  Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  Mode 3: leading edge is falling edge, data sample on trailing edge.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] mode The SPI transfer mode.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
+ *                  how it's generated.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val);
+
+/**
+ *  \brief Set SPI char size
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] char_size The character size, see \ref spi_char_size.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size);
+
+/**
+ *  \brief Set SPI data order
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] dord SPI data order (LSB/MSB first).
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord);
+
+/**
+ *  \brief Transfer the whole message without interrupt
+ *  Transfer the message, it will keep waiting until the message finish or
+ *  error.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] msg Pointer to the message instance to process.
+ *  \return Error or number of characters transferred.
+ *  \retval ERR_BUSY SPI hardware is not ready to start transfer (not
+ *                   enabled, busy applying settings, ...).
+ *  \retval SPI_ERR_OVERFLOW Overflow error.
+ *  \retval >=0 Number of characters transferred.
+ */
+int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_s_async.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_s_async.h
new file mode 100644
index 0000000..5647243
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_s_async.h
@@ -0,0 +1,232 @@
+/**
+ * \file
+ *
+ * \brief SPI Slave Async related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED
+#define _HPL_SPI_S_ASYNC_H_INCLUDED
+
+#include <hpl_spi_async.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Uses common SPI async device driver. */
+#define _spi_s_async_dev _spi_async_dev
+
+#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type
+
+/** Uses common SPI async device driver complete callback type. */
+#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
+
+/** Uses common SPI async device driver transfer callback type. */
+#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  It will load default hardware configuration and software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval ERR_DENIED SPI has been enabled.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw);
+
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  Disable, reset the hardware and the software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev);
+
+/**
+ *  \brief Enable SPI for access with interrupts
+ *  Enable the SPI and enable callback generation of receive and error
+ *  interrupts.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev);
+
+/**
+ *  \brief Disable SPI for access without interrupts
+ *  Disable SPI and interrupts. Deactivate all CS pins if works as master.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev);
+
+/**
+ *  \brief Set SPI transfer mode
+ *  Set SPI transfer mode (\ref spi_transfer_mode),
+ *  which controls clock polarity and clock phase.
+ *  Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  Mode 3: leading edge is falling edge, data sample on trailing edge.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] mode The SPI transfer mode.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] char_size The character size, see \ref spi_char_size.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size);
+
+/**
+ *  \brief Set SPI data order
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] dord SPI data order (LSB/MSB first).
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord);
+
+/**
+ * \brief Enable interrupt on character output
+ *
+ * Enable interrupt when a new character can be written
+ * to the SPI device.
+ *
+ * \param[in] dev   Pointer to the SPI device instance
+ * \param[in] state true  = enable output interrupt
+ *                  false = disable output interrupt
+ *
+ * \return Status code
+ * \retval 0 Ok status
+ */
+int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state);
+
+/**
+ * \brief Enable interrupt on character input
+ *
+ * Enable interrupt when a new character is ready to be
+ * read from the SPI device.
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ * \param[in] state true  = enable input interrupts
+ *                  false = disable input interrupt
+ *
+ * \return Status code
+ * \retvat 0 OK Status
+ */
+int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state);
+
+/**
+ * \brief Enable interrupt on Slave Select (SS) rising
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ * \param[in] state true  = enable input interrupts
+ *                  false = disable input interrupt
+ *
+ * \return Status code
+ * \retvat 0 OK Status
+ */
+int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state);
+
+/**
+ *  \brief Read one character to SPI device instance
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *
+ *  \return Character read from SPI module
+ */
+uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev);
+
+/**
+ *  \brief Write one character to assigned buffer
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] data
+ *
+ *  \return Status code of write operation
+ *  \retval 0 Write operation OK
+ */
+int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data);
+
+/**
+ *  \brief Register the SPI device callback
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] cb_type The callback type.
+ *  \param[in] func The callback function to register. NULL to disable callback.
+ *  \return Always 0.
+ */
+int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type,
+                                       const FUNC_PTR func);
+
+/**
+ * \brief Enable/disable SPI slave interrupt
+ *
+ * param[in] device The pointer to SPI slave device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] state Enable or disable
+ */
+void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type,
+                                const bool state);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_s_sync.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_s_sync.h
new file mode 100644
index 0000000..ff4c811
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_s_sync.h
@@ -0,0 +1,232 @@
+/**
+ * \file
+ *
+ * \brief SPI related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_S_SYNC_H_INCLUDED
+#define _HPL_SPI_S_SYNC_H_INCLUDED
+
+#include <hpl_spi_sync.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Uses common SPI sync device driver. */
+#define _spi_s_sync_dev _spi_sync_dev
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ *  \brief Initialize SPI for access without interrupts
+ *  It will load default hardware configuration and software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval ERR_DENIED SPI has been enabled.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw);
+
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  Disable, reset the hardware and the software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev);
+
+/**
+ *  \brief Enable SPI for access without interrupts
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev);
+
+/**
+ *  \brief Disable SPI for access without interrupts
+ *  Disable SPI. Deactivate all CS pins if works as master.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev);
+
+/**
+ *  \brief Set SPI transfer mode
+ *  Set SPI transfer mode (\ref spi_transfer_mode),
+ *  which controls clock polarity and clock phase.
+ *  Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  Mode 3: leading edge is falling edge, data sample on trailing edge.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] mode The SPI transfer mode.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] char_size The character size, see \ref spi_char_size.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size);
+
+/**
+ *  \brief Set SPI data order
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] dord SPI data order (LSB/MSB first).
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord);
+
+/**
+ * \brief Enable interrupt on character output
+ *
+ * Enable interrupt when a new character can be written
+ * to the SPI device.
+ *
+ * \param[in] dev   Pointer to the SPI device instance
+ * \param[in] state true  = enable output interrupt
+ *                  false = disable output interrupt
+ *
+ * \return Status code
+ * \retval 0 Ok status
+ */
+int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state);
+
+/**
+ * \brief Enable interrupt on character input
+ *
+ * Enable interrupt when a new character is ready to be
+ * read from the SPI device.
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ * \param[in] state true  = enable input interrupts
+ *                  false = disable input interrupt
+ *
+ * \return Status code
+ * \retval 0 OK Status
+ */
+int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state);
+
+/**
+ *  \brief Read one character to SPI device instance
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *
+ *  \return Character read from SPI module
+ */
+uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev);
+
+/**
+ *  \brief Write one character to assigned buffer
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] data
+ *
+ *  \return Status code of write operation
+ *  \retval 0 Write operation OK
+ */
+int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data);
+
+/**
+ * \brief Check if TX ready
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ *
+ * \return TX ready state
+ * \retval true TX ready
+ * \retval false TX not ready
+ */
+bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev);
+
+/**
+ * \brief Check if RX character ready
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ *
+ * \return RX character ready state
+ * \retval true RX character ready
+ * \retval false RX character not ready
+ */
+bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev);
+
+/**
+ * \brief Check if SS deactiviation detected
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ *
+ * \return SS deactiviation state
+ * \retval true SS deactiviation detected
+ * \retval false SS deactiviation not detected
+ */
+bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev);
+
+/**
+ * \brief Check if error is detected
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ *
+ * \return Error detection state
+ * \retval true Error detected
+ * \retval false Error not detected
+ */
+bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_sync.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_sync.h
new file mode 100644
index 0000000..dc88648
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_spi_sync.h
@@ -0,0 +1,70 @@
+/**
+ * \file
+ *
+ * \brief Common SPI related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_SYNC_H_INCLUDED
+#define _HPL_SPI_SYNC_H_INCLUDED
+
+#include <compiler.h>
+#include <utils.h>
+
+#include <hpl_spi.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ * \section hpl_spi_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SPI driver to support sync HAL */
+struct _spi_sync_dev {
+	/** Pointer to the hardware base or private data for special device. */
+	void *prvt;
+	/** Data size, number of bytes for each character */
+	uint8_t char_size;
+	/** Dummy byte used in master mode when reading the slave */
+	uint16_t dummy_byte;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_timer.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_timer.h
new file mode 100644
index 0000000..9bdfbb7
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_timer.h
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Timer related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_TIMER_H_INCLUDED
+#define _HPL_TIMER_H_INCLUDED
+
+/**
+ * \addtogroup HPL Timer
+ *
+ * \section hpl_timer_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+#include <hpl_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Timer device structure
+ *
+ * The Timer device structure forward declaration.
+ */
+struct _timer_device;
+
+/**
+ * \brief Timer interrupt callbacks
+ */
+struct _timer_callbacks {
+	void (*period_expired)(struct _timer_device *device);
+};
+
+/**
+ * \brief Timer device structure
+ */
+struct _timer_device {
+	struct _timer_callbacks timer_cb;
+	struct _irq_descriptor  irq;
+	void *                  hw;
+};
+
+/**
+ * \brief Timer functions, pointers to low-level functions
+ */
+struct _timer_hpl_interface {
+	int32_t (*init)(struct _timer_device *const device, void *const hw);
+	void (*deinit)(struct _timer_device *const device);
+	void (*start_timer)(struct _timer_device *const device);
+	void (*stop_timer)(struct _timer_device *const device);
+	void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles);
+	uint32_t (*get_period)(const struct _timer_device *const device);
+	bool (*is_timer_started)(const struct _timer_device *const device);
+	void (*set_timer_irq)(struct _timer_device *const device);
+};
+/**
+ * \brief Initialize TCC
+ *
+ * This function does low level TCC configuration.
+ *
+ * \param[in] device The pointer to timer device instance
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status.
+ */
+int32_t _timer_init(struct _timer_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize TCC
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_deinit(struct _timer_device *const device);
+
+/**
+ * \brief Start hardware timer
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_start(struct _timer_device *const device);
+
+/**
+ * \brief Stop hardware timer
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_stop(struct _timer_device *const device);
+
+/**
+ * \brief Set timer period
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles);
+
+/**
+ * \brief Retrieve timer period
+ *
+ * \param[in] device The pointer to timer device instance
+ *
+ * \return Timer period
+ */
+uint32_t _timer_get_period(const struct _timer_device *const device);
+
+/**
+ * \brief Check if timer is running
+ *
+ * \param[in] device The pointer to timer device instance
+ *
+ * \return Check status.
+ * \retval true The given timer is running
+ * \retval false The given timer is not running
+ */
+bool _timer_is_started(const struct _timer_device *const device);
+
+/**
+ * \brief Set timer IRQ
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_set_irq(struct _timer_device *const device);
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_TIMER_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_usart.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_usart.h
new file mode 100644
index 0000000..0e09501
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_usart.h
@@ -0,0 +1,113 @@
+/**
+ * \file
+ *
+ * \brief USART related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_USART_H_INCLUDED
+#define _HPL_USART_H_INCLUDED
+
+/**
+ * \addtogroup HPL USART SYNC
+ *
+ * \section hpl_usart_sync_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief USART flow control state
+ */
+union usart_flow_control_state {
+	struct {
+		uint8_t cts : 1;
+		uint8_t rts : 1;
+		uint8_t unavailable : 1;
+		uint8_t reserved : 5;
+	} bit;
+	uint8_t value;
+};
+
+/**
+ * \brief USART baud rate mode
+ */
+enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH };
+
+/**
+ * \brief USART data order
+ */
+enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 };
+
+/**
+ * \brief USART mode
+ */
+enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 };
+
+/**
+ * \brief USART parity
+ */
+enum usart_parity {
+	USART_PARITY_EVEN  = 0,
+	USART_PARITY_ODD   = 1,
+	USART_PARITY_NONE  = 2,
+	USART_PARITY_SPACE = 3,
+	USART_PARITY_MARK  = 4
+};
+
+/**
+ * \brief USART stop bits mode
+ */
+enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 };
+
+/**
+ * \brief USART character size
+ */
+enum usart_character_size {
+	USART_CHARACTER_SIZE_8BITS = 0,
+	USART_CHARACTER_SIZE_9BITS = 1,
+	USART_CHARACTER_SIZE_5BITS = 5,
+	USART_CHARACTER_SIZE_6BITS = 6,
+	USART_CHARACTER_SIZE_7BITS = 7
+};
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_USART_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_usart_async.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_usart_async.h
new file mode 100644
index 0000000..3f833d1
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_usart_async.h
@@ -0,0 +1,270 @@
+/**
+ * \file
+ *
+ * \brief USART related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_USART_ASYNC_H_INCLUDED
+#define _HPL_USART_ASYNC_H_INCLUDED
+
+/**
+ * \addtogroup HPL USART
+ *
+ * \section hpl_usart_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include "hpl_usart.h"
+#include "hpl_irq.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief USART callback types
+ */
+enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR };
+
+/**
+ * \brief USART device structure
+ *
+ * The USART device structure forward declaration.
+ */
+struct _usart_async_device;
+
+/**
+ * \brief USART interrupt callbacks
+ */
+struct _usart_async_callbacks {
+	void (*tx_byte_sent)(struct _usart_async_device *device);
+	void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data);
+	void (*tx_done_cb)(struct _usart_async_device *device);
+	void (*error_cb)(struct _usart_async_device *device);
+};
+
+/**
+ * \brief USART descriptor device structure
+ */
+struct _usart_async_device {
+	struct _usart_async_callbacks usart_cb;
+	struct _irq_descriptor        irq;
+	void *                        hw;
+};
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize asynchronous USART
+ *
+ * This function does low level USART configuration.
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize USART
+ *
+ * This function closes the given USART by disabling its clock.
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_async_deinit(struct _usart_async_device *const device);
+
+/**
+ * \brief Enable usart module
+ *
+ * This function will enable the usart module
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_async_enable(struct _usart_async_device *const device);
+
+/**
+ * \brief Disable usart module
+ *
+ * This function will disable the usart module
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_async_disable(struct _usart_async_device *const device);
+
+/**
+ * \brief Calculate baud rate register value
+ *
+ * \param[in] baud Required baud rate
+ * \param[in] clock_rate clock frequency
+ * \param[in] samples The number of samples
+ * \param[in] mode USART mode
+ * \param[in] fraction A fraction value
+ *
+ * \return Calculated baud rate register value
+ */
+uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
+                                          const enum usart_baud_rate_mode mode, const uint8_t fraction);
+
+/**
+ * \brief Set baud rate
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] baud_rate A baud rate to set
+ */
+void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate);
+
+/**
+ * \brief Set data order
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] order A data order to set
+ */
+void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order);
+
+/**
+ * \brief Set mode
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] mode A mode to set
+ */
+void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode);
+
+/**
+ * \brief Set parity
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] parity A parity to set
+ */
+void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity);
+
+/**
+ * \brief Set stop bits mode
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] stop_bits A stop bits mode to set
+ */
+void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits);
+
+/**
+ * \brief Set character size
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] size A character size to set
+ */
+void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size);
+
+/**
+ * \brief Retrieve usart status
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+uint32_t _usart_async_get_status(const struct _usart_async_device *const device);
+
+/**
+ * \brief Write a byte to the given USART instance
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] data Data to write
+ */
+void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data);
+
+/**
+ * \brief Check if USART is ready to send next byte
+ *
+ * \param[in] device The pointer to USART device instance
+ *
+ * \return Status of the ready check.
+ * \retval true if the USART is ready to send next byte
+ * \retval false if the USART is not ready to send next byte
+ */
+bool _usart_async_is_byte_sent(const struct _usart_async_device *const device);
+
+/**
+ * \brief Set the state of flow control pins
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] state - A state of flow control pins to set
+ */
+void _usart_async_set_flow_control_state(struct _usart_async_device *const    device,
+                                         const union usart_flow_control_state state);
+
+/**
+ * \brief Retrieve the state of flow control pins
+ *
+ * This function retrieves the of flow control pins.
+ *
+ * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
+ */
+union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device);
+
+/**
+ * \brief Enable data register empty interrupt
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device);
+
+/**
+ * \brief Enable transmission complete interrupt
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device);
+
+/**
+ * \brief Retrieve ordinal number of the given USART hardware instance
+ *
+ * \param[in] device The pointer to USART device instance
+ *
+ * \return The ordinal number of the given USART hardware instance
+ */
+uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device);
+
+/**
+ * \brief Enable/disable USART interrupt
+ *
+ * param[in] device The pointer to USART device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] state Enable or disable
+ */
+void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type,
+                                const bool state);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_USART_ASYNC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_usart_sync.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_usart_sync.h
new file mode 100644
index 0000000..abc7264
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hpl_usart_sync.h
@@ -0,0 +1,254 @@
+/**
+ * \file
+ *
+ * \brief USART related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SYNC_USART_H_INCLUDED
+#define _HPL_SYNC_USART_H_INCLUDED
+
+/**
+ * \addtogroup HPL USART SYNC
+ *
+ * \section hpl_usart_sync_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <hpl_usart.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief USART descriptor device structure
+ */
+struct _usart_sync_device {
+	void *hw;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize synchronous USART
+ *
+ * This function does low level USART configuration.
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize USART
+ *
+ * This function closes the given USART by disabling its clock.
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_sync_deinit(struct _usart_sync_device *const device);
+
+/**
+ * \brief Enable usart module
+ *
+ * This function will enable the usart module
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_sync_enable(struct _usart_sync_device *const device);
+
+/**
+ * \brief Disable usart module
+ *
+ * This function will disable the usart module
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_sync_disable(struct _usart_sync_device *const device);
+
+/**
+ * \brief Calculate baud rate register value
+ *
+ * \param[in] baud Required baud rate
+ * \param[in] clock_rate clock frequency
+ * \param[in] samples The number of samples
+ * \param[in] mode USART mode
+ * \param[in] fraction A fraction value
+ *
+ * \return Calculated baud rate register value
+ */
+uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
+                                         const enum usart_baud_rate_mode mode, const uint8_t fraction);
+
+/**
+ * \brief Set baud rate
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] baud_rate A baud rate to set
+ */
+void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate);
+
+/**
+ * \brief Set data order
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] order A data order to set
+ */
+void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order);
+
+/**
+ * \brief Set mode
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] mode A mode to set
+ */
+void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode);
+
+/**
+ * \brief Set parity
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] parity A parity to set
+ */
+void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity);
+
+/**
+ * \brief Set stop bits mode
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] stop_bits A stop bits mode to set
+ */
+void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits);
+
+/**
+ * \brief Set character size
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] size A character size to set
+ */
+void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size);
+
+/**
+ * \brief Retrieve usart status
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device);
+
+/**
+ * \brief Write a byte to the given USART instance
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] data Data to write
+ */
+void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data);
+
+/**
+ * \brief Read a byte from the given USART instance
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] data Data to write
+ *
+ * \return Data received via USART interface.
+ */
+uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device);
+
+/**
+ * \brief Check if USART is ready to send next byte
+ *
+ * \param[in] device The pointer to USART device instance
+ *
+ * \return Status of the ready check.
+ * \retval true if the USART is ready to send next byte
+ * \retval false if the USART is not ready to send next byte
+ */
+bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device);
+
+/**
+ * \brief Check if USART transmitter has sent the byte
+ *
+ * \param[in] device The pointer to USART device instance
+ *
+ * \return Status of the ready check.
+ * \retval true if the USART transmitter has sent the byte
+ * \retval false if the USART transmitter has not send the byte
+ */
+bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device);
+
+/**
+ * \brief Check if there is data received by USART
+ *
+ * \param[in] device The pointer to USART device instance
+ *
+ * \return Status of the data received check.
+ * \retval true if the USART has received a byte
+ * \retval false if the USART has not received a byte
+ */
+bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device);
+
+/**
+ * \brief Set the state of flow control pins
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] state - A state of flow control pins to set
+ */
+void _usart_sync_set_flow_control_state(struct _usart_sync_device *const     device,
+                                        const union usart_flow_control_state state);
+
+/**
+ * \brief Retrieve the state of flow control pins
+ *
+ * This function retrieves the of flow control pins.
+ *
+ * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
+ */
+union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device);
+
+/**
+ * \brief Retrieve ordinal number of the given USART hardware instance
+ *
+ * \param[in] device The pointer to USART device instance
+ *
+ * \return The ordinal number of the given USART hardware instance
+ */
+uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_SYNC_USART_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_adc_sync.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_adc_sync.c
new file mode 100644
index 0000000..33e0d92
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_adc_sync.c
@@ -0,0 +1,244 @@
+/**
+ * \file
+ *
+ * \brief ADC functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \brief Indicates HAL being compiled. Must be defined before including.
+ */
+#define _COMPILING_HAL
+
+#include "hal_adc_sync.h"
+#include <utils_assert.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Maximum amount of ADC interface instances
+ */
+#define MAX_ADC_AMOUNT ADC_INST_NUM
+
+/**
+ * \brief Initialize ADC
+ */
+int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func)
+{
+	ASSERT(descr && hw);
+
+	return _adc_sync_init(&descr->device, hw);
+}
+
+/**
+ * \brief Deinitialize ADC
+ */
+int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr)
+{
+	ASSERT(descr);
+	_adc_sync_deinit(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable ADC
+ */
+int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
+{
+	ASSERT(descr);
+	_adc_sync_enable_channel(&descr->device, channel);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Disable ADC
+ */
+int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
+{
+	ASSERT(descr);
+	_adc_sync_disable_channel(&descr->device, channel);
+	return ERR_NONE;
+}
+
+/*
+ * \brief Read data from ADC
+ */
+int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
+                              const uint16_t length)
+{
+	uint8_t  data_size;
+	uint16_t offset = 0;
+
+	ASSERT(descr && buffer && length);
+	data_size = _adc_sync_get_data_size(&descr->device);
+	ASSERT(!(length % data_size));
+
+	do {
+		uint16_t result;
+		_adc_sync_convert(&descr->device);
+
+		while (!_adc_sync_is_channel_conversion_done(&descr->device, channel))
+			;
+
+		result         = _adc_sync_read_channel_data(&descr->device, channel);
+		buffer[offset] = result;
+		if (1 < data_size) {
+			buffer[offset + 1] = result >> 8;
+		}
+		offset += data_size;
+	} while (offset < length);
+
+	return offset;
+}
+
+/**
+ * \brief Set ADC reference source
+ */
+int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference)
+{
+	ASSERT(descr);
+	_adc_sync_set_reference_source(&descr->device, reference);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC resolution
+ */
+int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution)
+{
+	ASSERT(descr);
+	_adc_sync_set_resolution(&descr->device, resolution);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC input source of a channel
+ */
+int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
+                            const adc_neg_input_t neg_input, const uint8_t channel)
+{
+	ASSERT(descr);
+	_adc_sync_set_inputs(&descr->device, pos_input, neg_input, channel);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC thresholds
+ */
+int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
+                                const adc_threshold_t up_threshold)
+{
+	ASSERT(descr);
+	_adc_sync_set_thresholds(&descr->device, low_threshold, up_threshold);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC gain
+ */
+int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, const adc_gain_t gain)
+{
+	ASSERT(descr);
+	_adc_sync_set_channel_gain(&descr->device, channel, gain);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC conversion mode
+ */
+int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode)
+{
+	ASSERT(descr);
+	_adc_sync_set_conversion_mode(&descr->device, mode);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC differential mode
+ */
+int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                               const enum adc_differential_mode mode)
+{
+	ASSERT(descr);
+	_adc_sync_set_channel_differential_mode(&descr->device, channel, mode);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC window mode
+ */
+int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode)
+{
+	ASSERT(descr);
+	_adc_sync_set_window_mode(&descr->device, mode);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve threshold state
+ */
+int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, adc_threshold_status_t *const state)
+{
+	ASSERT(descr && state);
+	_adc_sync_get_threshold_state(&descr->device, state);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Check if conversion is complete
+ */
+int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel)
+{
+	ASSERT(descr);
+	return _adc_sync_is_channel_conversion_done(&descr->device, channel);
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t adc_sync_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+//@}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_atomic.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_atomic.c
new file mode 100644
index 0000000..f56418e
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_atomic.c
@@ -0,0 +1,66 @@
+/**
+ * \file
+ *
+ * \brief Critical sections related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_atomic.h"
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Disable interrupts, enter critical section
+ */
+void atomic_enter_critical(hal_atomic_t volatile *atomic)
+{
+	*atomic = __get_PRIMASK();
+	__disable_irq();
+	__DMB();
+}
+
+/**
+ * \brief Exit atomic section
+ */
+void atomic_leave_critical(hal_atomic_t volatile *atomic)
+{
+	__DMB();
+	__set_PRIMASK(*atomic);
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t atomic_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_cache.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_cache.c
new file mode 100644
index 0000000..b2e75aa
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_cache.c
@@ -0,0 +1,78 @@
+/**
+ * \file
+ *
+ * \brief HAL cache functionality implementation.
+ *
+ * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".  NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <compiler.h>
+#include <hpl_cmcc.h>
+
+/**
+ * \brief Initialize cache module
+ */
+int32_t cache_init(void)
+{
+	return _cmcc_init();
+}
+
+/**
+ * \brief Enable cache module
+ */
+int32_t cache_enable(const void *hw)
+{
+	return _cmcc_enable(hw);
+}
+
+/**
+ * \brief Disable cache module
+ */
+int32_t cache_disable(const void *hw)
+{
+	return _cmcc_disable(hw);
+}
+
+/**
+ * \brief Configure cache module
+ */
+int32_t cache_configure(const void *hw, struct _cache_cfg *cache)
+{
+	return _cmcc_configure(hw, cache);
+}
+
+/**
+ * \brief Invalidate entire cache entries
+ */
+int32_t cache_invalidate_all(const void *hw)
+{
+	return _cmcc_invalidate_all(hw);
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_delay.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_delay.c
new file mode 100644
index 0000000..6f77cc7
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_delay.c
@@ -0,0 +1,80 @@
+/**
+ * \file
+ *
+ * \brief HAL delay related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_irq.h>
+#include <hpl_reset.h>
+#include <hpl_sleep.h>
+#include "hal_delay.h"
+#include <hpl_delay.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief The pointer to a hardware instance used by the driver.
+ */
+static void *hardware;
+
+/**
+ * \brief Initialize Delay driver
+ */
+void delay_init(void *const hw)
+{
+	_delay_init(hardware = hw);
+}
+
+/**
+ * \brief Perform delay in us
+ */
+void delay_us(const uint16_t us)
+{
+	_delay_cycles(hardware, _get_cycles_for_us(us));
+}
+
+/**
+ * \brief Perform delay in ms
+ */
+void delay_ms(const uint16_t ms)
+{
+	_delay_cycles(hardware, _get_cycles_for_ms(ms));
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t delay_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_evsys.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_evsys.c
new file mode 100644
index 0000000..0ce8ce5
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_evsys.c
@@ -0,0 +1,98 @@
+/**
+ * \file
+ *
+ * \brief HAL event system related functionality implementation.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_evsys.h"
+#include <hpl_evsys.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Initialize event system.
+ */
+int32_t event_system_init(void)
+{
+	return _event_system_init();
+}
+
+/**
+ * \brief Deinitialize event system.
+ */
+int32_t event_system_deinit(void)
+{
+	return _event_system_deinit();
+}
+
+/**
+ * \brief Enable event reception by the given user from the given channel
+ */
+int32_t event_system_enable_user(const uint16_t user, const uint16_t channel)
+{
+	return _event_system_enable_user(user, channel, true);
+}
+
+/**
+ * \brief Enable event reception by the given user from the given channel
+ */
+int32_t event_system_disable_user(const uint16_t user, const uint16_t channel)
+{
+	return _event_system_enable_user(user, channel, false);
+}
+
+/**
+ * \brief Enable event generation by the given generator for the given channel
+ */
+int32_t event_system_enable_generator(const uint16_t generator, const uint16_t channel)
+{
+	return _event_system_enable_generator(generator, channel, true);
+}
+
+/**
+ * \brief Enable event generation by the given generator for the given channel
+ */
+int32_t event_system_disable_generator(const uint16_t generator, const uint16_t channel)
+{
+	return _event_system_enable_generator(generator, channel, false);
+}
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version
+ */
+uint32_t event_system_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_ext_irq.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_ext_irq.c
new file mode 100644
index 0000000..7a62a80
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_ext_irq.c
@@ -0,0 +1,188 @@
+/**
+ * \file
+ *
+ * \brief External interrupt functionality imkplementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_ext_irq.h"
+
+#define EXT_IRQ_AMOUNT 4
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief External IRQ struct
+ */
+struct ext_irq {
+	ext_irq_cb_t cb;
+	uint32_t     pin;
+};
+
+/* Remove KEIL compiling error in case no IRQ line selected */
+#if EXT_IRQ_AMOUNT == 0
+#undef EXT_IRQ_AMOUNT
+#define EXT_IRQ_AMOUNT 1
+#endif
+
+/**
+ * \brief Array of external IRQs callbacks
+ */
+static struct ext_irq ext_irqs[EXT_IRQ_AMOUNT];
+
+static void process_ext_irq(const uint32_t pin);
+
+/**
+ * \brief Initialize external irq component if any
+ */
+int32_t ext_irq_init(void)
+{
+	uint16_t i;
+
+	for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
+		ext_irqs[i].pin = 0xFFFFFFFF;
+		ext_irqs[i].cb  = NULL;
+	}
+
+	return _ext_irq_init(process_ext_irq);
+}
+
+/**
+ * \brief Deinitialize external irq if any
+ */
+int32_t ext_irq_deinit(void)
+{
+	return _ext_irq_deinit();
+}
+
+/**
+ * \brief Register callback for the given external interrupt
+ */
+int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb)
+{
+	uint8_t i = 0, j = 0;
+	bool    found = false;
+
+	for (; i < EXT_IRQ_AMOUNT; i++) {
+		if (ext_irqs[i].pin == pin) {
+			ext_irqs[i].cb = cb;
+			found          = true;
+			break;
+		}
+	}
+
+	if (NULL == cb) {
+		if (!found) {
+			return ERR_INVALID_ARG;
+		}
+		return _ext_irq_enable(pin, false);
+	}
+
+	if (!found) {
+		for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
+			if (NULL == ext_irqs[i].cb) {
+				ext_irqs[i].cb  = cb;
+				ext_irqs[i].pin = pin;
+				found           = true;
+				break;
+			}
+		}
+		for (; (j < EXT_IRQ_AMOUNT) && (i < EXT_IRQ_AMOUNT); j++) {
+			if ((ext_irqs[i].pin < ext_irqs[j].pin) && (ext_irqs[j].pin != 0xFFFFFFFF)) {
+				struct ext_irq tmp = ext_irqs[j];
+
+				ext_irqs[j] = ext_irqs[i];
+				ext_irqs[i] = tmp;
+			}
+		}
+	}
+
+	if (!found) {
+		return ERR_INVALID_ARG;
+	}
+
+	return _ext_irq_enable(pin, true);
+}
+
+/**
+ * \brief Enable external irq
+ */
+int32_t ext_irq_enable(const uint32_t pin)
+{
+	return _ext_irq_enable(pin, true);
+}
+
+/**
+ * \brief Disable external irq
+ */
+int32_t ext_irq_disable(const uint32_t pin)
+{
+	return _ext_irq_enable(pin, false);
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t ext_irq_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+/**
+ * \brief Interrupt processing routine
+ *
+ * \param[in] pin The pin which triggered the interrupt
+ */
+static void process_ext_irq(const uint32_t pin)
+{
+	uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT;
+
+	while (upper >= lower) {
+		middle = (upper + lower) >> 1;
+		if (middle >= EXT_IRQ_AMOUNT) {
+			return;
+		}
+
+		if (ext_irqs[middle].pin == pin) {
+			if (ext_irqs[middle].cb) {
+				ext_irqs[middle].cb();
+			}
+			return;
+		}
+
+		if (ext_irqs[middle].pin < pin) {
+			lower = middle + 1;
+		} else {
+			upper = middle - 1;
+		}
+	}
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_gpio.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_gpio.c
new file mode 100644
index 0000000..00dfea6
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_gpio.c
@@ -0,0 +1,44 @@
+/**
+ * \file
+ *
+ * \brief Port
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_gpio.h"
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+uint32_t gpio_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_i2c_m_async.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_i2c_m_async.c
new file mode 100644
index 0000000..898567d
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_i2c_m_async.c
@@ -0,0 +1,389 @@
+/**
+ * \file
+ *
+ * \brief I/O I2C related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <hal_i2c_m_async.h>
+#include <utils.h>
+#include <utils_assert.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Callback function for tx complete
+ */
+static void i2c_tx_complete(struct _i2c_m_async_device *const i2c_dev)
+{
+	struct i2c_m_async_desc *i2c = CONTAINER_OF(i2c_dev, struct i2c_m_async_desc, device);
+
+	if (!(i2c_dev->service.msg.flags & I2C_M_BUSY)) {
+		if (i2c->i2c_cb.tx_complete) {
+			i2c->i2c_cb.tx_complete(i2c);
+		}
+	}
+}
+
+/**
+ * \brief Callback function for rx complete
+ */
+static void i2c_rx_complete(struct _i2c_m_async_device *const i2c_dev)
+{
+	struct i2c_m_async_desc *i2c = CONTAINER_OF(i2c_dev, struct i2c_m_async_desc, device);
+
+	if (!(i2c_dev->service.msg.flags & I2C_M_BUSY)) {
+		if (i2c->i2c_cb.rx_complete) {
+			i2c->i2c_cb.rx_complete(i2c);
+		}
+	}
+}
+
+static void i2c_error(struct _i2c_m_async_device *const i2c_dev, int32_t error)
+{
+	struct i2c_m_async_desc *i2c = CONTAINER_OF(i2c_dev, struct i2c_m_async_desc, device);
+
+	if (!(i2c_dev->service.msg.flags & I2C_M_BUSY)) {
+		if (i2c->i2c_cb.error) {
+			i2c->i2c_cb.error(i2c, error);
+		}
+	}
+}
+
+/**
+ * \brief Async version of I2C I/O read
+ */
+static int32_t i2c_m_async_read(struct io_descriptor *const io, uint8_t *buf, const uint16_t n)
+{
+	struct i2c_m_async_desc *i2c = CONTAINER_OF(io, struct i2c_m_async_desc, io);
+	struct _i2c_m_msg        msg;
+	int32_t                  ret;
+
+	msg.addr   = i2c->slave_addr;
+	msg.len    = n;
+	msg.flags  = I2C_M_STOP | I2C_M_RD;
+	msg.buffer = buf;
+
+	/* start transfer then return */
+	ret = _i2c_m_async_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		return ret;
+	}
+
+	return (int32_t)n;
+}
+
+/**
+ * \brief Async version of I2C I/O write
+ */
+static int32_t i2c_m_async_write(struct io_descriptor *const io, const uint8_t *buf, const uint16_t n)
+{
+	struct i2c_m_async_desc *i2c = CONTAINER_OF(io, struct i2c_m_async_desc, io);
+	struct _i2c_m_msg        msg;
+	int32_t                  ret;
+
+	msg.addr   = i2c->slave_addr;
+	msg.len    = n;
+	msg.flags  = I2C_M_STOP;
+	msg.buffer = (uint8_t *)buf;
+
+	/* start transfer then return */
+	ret = _i2c_m_async_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		return ret;
+	}
+
+	return (int32_t)n;
+}
+
+/**
+ * \brief Async version of i2c initialize
+ */
+int32_t i2c_m_async_init(struct i2c_m_async_desc *const i2c, void *const hw)
+{
+	int32_t init_status;
+	ASSERT(i2c);
+
+	init_status = _i2c_m_async_init(&i2c->device, hw);
+	if (init_status) {
+		return init_status;
+	}
+	/* Init I/O */
+	i2c->io.read  = i2c_m_async_read;
+	i2c->io.write = i2c_m_async_write;
+
+	/* Init callbacks */
+	_i2c_m_async_register_callback(&i2c->device, I2C_M_ASYNC_DEVICE_TX_COMPLETE, (FUNC_PTR)i2c_tx_complete);
+	_i2c_m_async_register_callback(&i2c->device, I2C_M_ASYNC_DEVICE_RX_COMPLETE, (FUNC_PTR)i2c_rx_complete);
+	_i2c_m_async_register_callback(&i2c->device, I2C_M_ASYNC_DEVICE_ERROR, (FUNC_PTR)i2c_error);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinitialize
+ */
+int32_t i2c_m_async_deinit(struct i2c_m_async_desc *const i2c)
+{
+	int32_t status;
+	ASSERT(i2c);
+
+	status = _i2c_m_async_deinit(&i2c->device);
+	if (status) {
+		return status;
+	}
+
+	i2c->io.read  = NULL;
+	i2c->io.write = NULL;
+
+	_i2c_m_async_register_callback(&i2c->device, I2C_M_ASYNC_DEVICE_TX_COMPLETE, NULL);
+	_i2c_m_async_register_callback(&i2c->device, I2C_M_ASYNC_DEVICE_RX_COMPLETE, NULL);
+	_i2c_m_async_register_callback(&i2c->device, I2C_M_ASYNC_DEVICE_ERROR, NULL);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Async version of i2c enable
+ */
+int32_t i2c_m_async_enable(struct i2c_m_async_desc *const i2c)
+{
+	int32_t rc;
+
+	ASSERT(i2c);
+
+	rc = _i2c_m_async_enable(&i2c->device);
+	if (rc == ERR_NONE) {
+		_i2c_m_async_set_irq_state(&i2c->device, I2C_M_ASYNC_DEVICE_TX_COMPLETE, true);
+		_i2c_m_async_set_irq_state(&i2c->device, I2C_M_ASYNC_DEVICE_RX_COMPLETE, true);
+		_i2c_m_async_set_irq_state(&i2c->device, I2C_M_ASYNC_DEVICE_ERROR, true);
+	}
+	return rc;
+}
+
+/**
+ * \brief Async version of i2c disable
+ */
+int32_t i2c_m_async_disable(struct i2c_m_async_desc *const i2c)
+{
+	int32_t rc;
+
+	ASSERT(i2c);
+
+	rc = _i2c_m_async_disable(&i2c->device);
+	if (rc == ERR_NONE) {
+		_i2c_m_async_set_irq_state(&i2c->device, I2C_M_ASYNC_DEVICE_TX_COMPLETE, false);
+		_i2c_m_async_set_irq_state(&i2c->device, I2C_M_ASYNC_DEVICE_RX_COMPLETE, false);
+		_i2c_m_async_set_irq_state(&i2c->device, I2C_M_ASYNC_DEVICE_ERROR, false);
+	}
+	return rc;
+}
+
+/**
+ * \brief Async version of i2c set slave address
+ */
+int32_t i2c_m_async_set_slaveaddr(struct i2c_m_async_desc *const i2c, int16_t addr, int32_t addr_len)
+{
+	return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN);
+}
+
+/**
+ * \brief I2c register callback
+ */
+int32_t i2c_m_async_register_callback(struct i2c_m_async_desc *const i2c, enum i2c_m_async_callback_type type,
+                                      FUNC_PTR func)
+{
+	switch (type) {
+	case I2C_M_ASYNC_ERROR:
+		i2c->i2c_cb.error = (i2c_error_cb_t)func;
+		break;
+	case I2C_M_ASYNC_TX_COMPLETE:
+		i2c->i2c_cb.tx_complete = (i2c_complete_cb_t)func;
+		break;
+	case I2C_M_ASYNC_RX_COMPLETE:
+		i2c->i2c_cb.rx_complete = (i2c_complete_cb_t)func;
+		break;
+	default:
+		/* error */
+		return ERR_INVALID_ARG;
+	}
+	return I2C_OK;
+}
+
+/**
+ * \brief Async version of i2c set baudrate
+ */
+int32_t i2c_m_async_set_baudrate(struct i2c_m_async_desc *const i2c, uint32_t clkrate, uint32_t baudrate)
+{
+	return _i2c_m_async_set_baudrate(&i2c->device, clkrate, baudrate);
+}
+
+/**
+ * \brief Async version of i2c write command
+ */
+int32_t i2c_m_async_cmd_write(struct i2c_m_async_desc *const i2c, uint8_t reg, uint8_t value)
+{
+	struct _i2c_m_msg msg;
+	int32_t           ret;
+
+	msg.addr   = i2c->slave_addr;
+	msg.len    = 1;
+	msg.flags  = 0;
+	msg.buffer = &reg;
+
+	i2c->device.cb.tx_complete = NULL;
+
+	ret = _i2c_m_async_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		/* re-register to enable notify user callback */
+		i2c->device.cb.tx_complete = i2c_tx_complete;
+		return ret;
+	}
+
+	/* we polling busy flag wait for send finish here */
+	while (i2c->device.service.msg.flags & I2C_M_BUSY) {
+		;
+	}
+
+	i2c->device.cb.tx_complete = i2c_tx_complete;
+
+	msg.flags  = I2C_M_STOP;
+	msg.buffer = &value;
+
+	ret = _i2c_m_async_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		return ret;
+	}
+
+	return I2C_OK;
+}
+
+/**
+ * \brief Async version of i2c read command
+ */
+int32_t i2c_m_async_cmd_read(struct i2c_m_async_desc *const i2c, uint8_t reg, uint8_t *value)
+{
+	struct _i2c_m_msg msg;
+	int32_t           ret;
+
+	msg.addr   = i2c->slave_addr;
+	msg.len    = 1;
+	msg.flags  = 0;
+	msg.buffer = &reg;
+
+	i2c->device.cb.tx_complete = NULL;
+
+	ret = _i2c_m_async_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		/* re-register to enable notify user callback */
+		i2c->device.cb.tx_complete = i2c_tx_complete;
+		return ret;
+	}
+
+	/* we polling busy flag wait for send finish here */
+	while (i2c->device.service.msg.flags & I2C_M_BUSY) {
+		;
+	}
+
+	/* re-register to enable notify user callback */
+	i2c->device.cb.tx_complete = i2c_tx_complete;
+
+	msg.flags  = I2C_M_STOP | I2C_M_RD;
+	msg.buffer = value;
+
+	ret = _i2c_m_async_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		return ret;
+	}
+
+	return I2C_OK;
+}
+
+int32_t i2c_m_async_transfer(struct i2c_m_async_desc *const i2c, struct _i2c_m_msg *msg)
+{
+	return _i2c_m_async_transfer(&i2c->device, msg);
+}
+
+/**
+ * \brief Send stop condition
+ */
+int32_t i2c_m_async_send_stop(struct i2c_m_async_desc *const i2c)
+{
+	return _i2c_m_async_send_stop(&i2c->device);
+}
+
+/**
+ * \brief Get bytes left in message buffer
+ */
+int32_t i2c_m_async_get_status(struct i2c_m_async_desc *const i2c, struct i2c_m_async_status *stat)
+{
+	ASSERT(i2c && stat);
+	/* Get a copy of status to avoid critical issue */
+	volatile uint16_t *tmp_stat = &(i2c->device.service.msg.flags);
+	volatile int32_t * tmp_left = &(i2c->device.service.msg.len);
+
+	if (*tmp_stat == I2C_M_BUSY) {
+		stat->flags = *tmp_stat;
+		stat->left  = *tmp_left;
+		return ERR_BUSY;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve I/O descriptor
+ */
+int32_t i2c_m_async_get_io_descriptor(struct i2c_m_async_desc *const i2c, struct io_descriptor **io)
+{
+	*io = &i2c->io;
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t i2c_m_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_init.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_init.c
new file mode 100644
index 0000000..fb65341
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_init.c
@@ -0,0 +1,47 @@
+/**
+ * \file
+ *
+ * \brief HAL initialization related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_init.h"
+
+/**
+ * \brief Driver version
+ */
+#define HAL_INIT_VERSION 0x00000001u
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t init_get_version(void)
+{
+	return HAL_INIT_VERSION;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_io.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_io.c
new file mode 100644
index 0000000..7e8feb0
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_io.c
@@ -0,0 +1,63 @@
+/**
+ * \file
+ *
+ * \brief I/O functionality implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hal_io.h>
+#include <utils_assert.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+uint32_t io_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+/**
+ * \brief I/O write interface
+ */
+int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
+{
+	ASSERT(io_descr && buf);
+	return io_descr->write(io_descr, buf, length);
+}
+
+/**
+ * \brief I/O read interface
+ */
+int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
+{
+	ASSERT(io_descr && buf);
+	return io_descr->read(io_descr, buf, length);
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_pwm.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_pwm.c
new file mode 100644
index 0000000..b586972
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_pwm.c
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief PWM functionality implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_pwm.h"
+#include <utils_assert.h>
+#include <utils.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+static void pwm_period_expired(struct _pwm_device *device);
+static void pwm_detect_fault(struct _pwm_device *device);
+
+/**
+ * \brief Initialize pwm
+ */
+int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func)
+{
+	ASSERT(descr && hw);
+	_pwm_init(&descr->device, hw);
+	descr->device.callback.pwm_period_cb = pwm_period_expired;
+	descr->device.callback.pwm_error_cb  = pwm_detect_fault;
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinitialize pwm
+ */
+int32_t pwm_deinit(struct pwm_descriptor *const descr)
+{
+	ASSERT(descr);
+	_pwm_deinit(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Start pwm
+ */
+int32_t pwm_enable(struct pwm_descriptor *const descr)
+{
+	ASSERT(descr);
+	if (_pwm_is_enabled(&descr->device)) {
+		return ERR_DENIED;
+	}
+	_pwm_enable(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Stop pwm
+ */
+int32_t pwm_disable(struct pwm_descriptor *const descr)
+{
+	ASSERT(descr);
+	if (!_pwm_is_enabled(&descr->device)) {
+		return ERR_DENIED;
+	}
+	_pwm_disable(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Register PWM callback
+ */
+int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb)
+{
+	switch (type) {
+	case PWM_PERIOD_CB:
+		descr->pwm_cb.period = cb;
+		break;
+
+	case PWM_ERROR_CB:
+		descr->pwm_cb.error = cb;
+		break;
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+	ASSERT(descr);
+	_pwm_set_irq_state(&descr->device, (enum _pwm_callback_type)type, NULL != cb);
+	return ERR_NONE;
+}
+
+/**
+ * \brief Change PWM parameter
+ */
+int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, const pwm_period_t duty_cycle)
+{
+	ASSERT(descr);
+	_pwm_set_param(&descr->device, period, duty_cycle);
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t pwm_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+/**
+ * \internal Process interrupts caused by period experied
+ */
+static void pwm_period_expired(struct _pwm_device *device)
+{
+	struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);
+
+	if (descr->pwm_cb.period) {
+		descr->pwm_cb.period(descr);
+	}
+}
+
+/**
+ * \internal Process interrupts caused by pwm fault
+ */
+static void pwm_detect_fault(struct _pwm_device *device)
+{
+	struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);
+
+	if (descr->pwm_cb.error) {
+		descr->pwm_cb.error(descr);
+	}
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_qspi_dma.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_qspi_dma.c
new file mode 100644
index 0000000..2f35a4b
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_qspi_dma.c
@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief Quad SPI dma related functionality implementation.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_assert.h>
+#include <utils.h>
+#include "hal_qspi_dma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Driver version
+ */
+#define QSPI_DMA_DRIVER_VERSION 0x00000001u
+
+int32_t qspi_dma_init(struct qspi_dma_descriptor *qspi, void *const hw)
+{
+	ASSERT(qspi && hw);
+
+	return _qspi_dma_init(&qspi->dev, hw);
+}
+
+int32_t qspi_dma_deinit(struct qspi_dma_descriptor *qspi)
+{
+	ASSERT(qspi);
+
+	return _qspi_dma_deinit(&qspi->dev);
+}
+
+int32_t qspi_dma_enable(struct qspi_dma_descriptor *qspi)
+{
+	ASSERT(qspi);
+
+	return _qspi_dma_enable(&qspi->dev);
+}
+
+int32_t qspi_dma_disable(struct qspi_dma_descriptor *qspi)
+{
+	ASSERT(qspi);
+
+	return _qspi_dma_disable(&qspi->dev);
+}
+
+int32_t qspi_dma_serial_run_command(struct qspi_dma_descriptor *qspi, const struct _qspi_command *cmd)
+{
+	ASSERT(qspi && cmd);
+
+	return _qspi_dma_serial_run_command(&qspi->dev, cmd);
+}
+
+void qspi_dma_register_callback(struct qspi_dma_descriptor *qspi, const enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb)
+{
+	ASSERT(qspi);
+
+	_qspi_dma_register_callback(&qspi->dev, type, cb);
+}
+
+uint32_t qspi_dma_get_version(void)
+{
+	return QSPI_DMA_DRIVER_VERSION;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_sleep.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_sleep.c
new file mode 100644
index 0000000..89472f1
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_sleep.c
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Sleep related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_sleep.h"
+#include <hpl_sleep.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Set the sleep mode of the device and put the MCU to sleep
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see the data sheet.
+ *
+ * \param[in] mode Sleep mode to use
+ *
+ * \return The status of a sleep request
+ * \retval -1 The requested sleep mode was invalid or not available
+ * \retval  0 The operation completed successfully, returned after leaving the
+ *            sleep
+ */
+int sleep(const uint8_t mode)
+{
+	if (ERR_NONE != _set_sleep_mode(mode))
+		return ERR_INVALID_ARG;
+
+	_go_to_sleep();
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version
+ */
+uint32_t sleep_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_spi_m_dma.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_spi_m_dma.c
new file mode 100644
index 0000000..976d0f8
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_spi_m_dma.c
@@ -0,0 +1,183 @@
+/**
+ * \file
+ *
+ * \brief I/O SPI DMA related functionality implementation.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_atomic.h"
+#include "hal_spi_m_dma.h"
+#include <utils_assert.h>
+#include <utils.h>
+
+/**
+ * \brief Driver version
+ */
+#define SPI_DRIVER_VERSION 0x00000001u
+
+static int32_t _spi_m_dma_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length);
+static int32_t _spi_m_dma_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length);
+
+/**
+ *  \brief Initialize the SPI HAL instance function pointer for HPL APIs.
+ */
+void spi_m_dma_set_func_ptr(struct spi_m_dma_descriptor *spi, void *const func)
+{
+	ASSERT(spi);
+	spi->func = (struct _spi_m_dma_hpl_interface *)func;
+}
+
+int32_t spi_m_dma_init(struct spi_m_dma_descriptor *spi, void *const hw)
+{
+	int32_t rc = 0;
+	ASSERT(spi && hw);
+	spi->dev.prvt = (void *)hw;
+	rc            = _spi_m_dma_init(&spi->dev, hw);
+
+	if (rc) {
+		return rc;
+	}
+
+	spi->io.read  = _spi_m_dma_io_read;
+	spi->io.write = _spi_m_dma_io_write;
+
+	return ERR_NONE;
+}
+
+void spi_m_dma_deinit(struct spi_m_dma_descriptor *spi)
+{
+	ASSERT(spi);
+	_spi_m_dma_deinit(&spi->dev);
+}
+
+void spi_m_dma_enable(struct spi_m_dma_descriptor *spi)
+{
+	ASSERT(spi);
+	_spi_m_dma_enable(&spi->dev);
+}
+
+void spi_m_dma_disable(struct spi_m_dma_descriptor *spi)
+{
+	ASSERT(spi);
+	_spi_m_dma_disable(&spi->dev);
+}
+
+int32_t spi_m_dma_set_baudrate(struct spi_m_dma_descriptor *spi, const uint32_t baud_val)
+{
+	ASSERT(spi);
+	return _spi_m_dma_set_baudrate(&spi->dev, baud_val);
+}
+
+int32_t spi_m_dma_set_mode(struct spi_m_dma_descriptor *spi, const enum spi_transfer_mode mode)
+{
+	ASSERT(spi);
+	return _spi_m_dma_set_mode(&spi->dev, mode);
+}
+
+int32_t spi_m_dma_set_char_size(struct spi_m_dma_descriptor *spi, const enum spi_char_size char_size)
+{
+	ASSERT(spi);
+	return _spi_m_dma_set_char_size(&spi->dev, char_size);
+}
+
+int32_t spi_m_dma_set_data_order(struct spi_m_dma_descriptor *spi, const enum spi_data_order dord)
+{
+	ASSERT(spi);
+	return _spi_m_dma_set_data_order(&spi->dev, dord);
+}
+
+/** \brief Do SPI read in background
+ *
+ *  It never blocks and return quickly, user check status or set callback to
+ *  know when data is ready to process.
+ *
+ *  \param[in, out] spi Pointer to the HAL SPI instance.
+ *  \param[out] p_buf Pointer to the buffer to store read data.
+ *  \param[in] size Size of the data in number of characters.
+ *  \return ERR_NONE on success, or an error code on failure.
+ *  \retval ERR_NONE Success, transfer started.
+ *  \retval ERR_BUSY Busy.
+ */
+static int32_t _spi_m_dma_io_read(struct io_descriptor *io, uint8_t *const buf, const uint16_t length)
+{
+	ASSERT(io);
+
+	struct spi_m_dma_descriptor *spi = CONTAINER_OF(io, struct spi_m_dma_descriptor, io);
+	return _spi_m_dma_transfer(&spi->dev, NULL, buf, length);
+}
+
+/** \brief Do SPI data write in background
+ *
+ *  The data read back is discarded.
+ *
+ *  It never blocks and return quickly, user check status or set callback to
+ *  know when data is sent.
+ *
+ *  \param[in, out] spi Pointer to the HAL SPI instance.
+ *  \param[in] p_buf Pointer to the buffer to store data to write.
+ *  \param[in] size Size of the data in number of characters.
+ *
+ *  \return ERR_NONE on success, or an error code on failure.
+ *  \retval ERR_NONE Success, transfer started.
+ *  \retval ERR_BUSY Busy.
+ */
+static int32_t _spi_m_dma_io_write(struct io_descriptor *io, const uint8_t *const buf, const uint16_t length)
+{
+	ASSERT(io);
+
+	struct spi_m_dma_descriptor *spi = CONTAINER_OF(io, struct spi_m_dma_descriptor, io);
+	return _spi_m_dma_transfer(&spi->dev, buf, NULL, length);
+}
+
+int32_t spi_m_dma_transfer(struct spi_m_dma_descriptor *spi, uint8_t const *txbuf, uint8_t *const rxbuf,
+                           const uint16_t length)
+{
+	ASSERT(spi);
+	return _spi_m_dma_transfer(&spi->dev, txbuf, rxbuf, length);
+}
+
+void spi_m_dma_register_callback(struct spi_m_dma_descriptor *spi, const enum spi_m_dma_cb_type type,
+                                 spi_m_dma_cb_t func)
+{
+	ASSERT(spi);
+	_spi_m_dma_register_callback(&spi->dev, (enum _spi_dma_dev_cb_type)type, func);
+}
+
+int32_t spi_m_dma_get_io_descriptor(struct spi_m_dma_descriptor *const spi, struct io_descriptor **io)
+{
+	ASSERT(spi && io);
+	*io = &spi->io;
+
+	return 0;
+}
+
+uint32_t spi_m_dma_get_version(void)
+{
+	return SPI_DRIVER_VERSION;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_spi_m_sync.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_spi_m_sync.c
new file mode 100644
index 0000000..1a64296
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/src/hal_spi_m_sync.c
@@ -0,0 +1,201 @@
+/**
+ * \file
+ *
+ * \brief I/O SPI related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_spi_m_sync.h"
+#include <utils_assert.h>
+#include <utils.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Driver version
+ */
+#define SPI_M_SYNC_DRIVER_VERSION 0x00000001u
+
+#define SPI_DEACTIVATE_NEXT 0x8000
+
+static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length);
+static int32_t _spi_m_sync_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length);
+
+/**
+ *  \brief Initialize the SPI HAL instance function pointer for HPL APIs.
+ */
+void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func)
+{
+	ASSERT(spi);
+	spi->func = (struct _spi_m_sync_hpl_interface *)func;
+}
+
+int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw)
+{
+	int32_t rc = 0;
+	ASSERT(spi && hw);
+	spi->dev.prvt = (void *)hw;
+	rc            = _spi_m_sync_init(&spi->dev, hw);
+
+	if (rc < 0) {
+		return rc;
+	}
+
+	spi->flags    = SPI_DEACTIVATE_NEXT;
+	spi->io.read  = _spi_m_sync_io_read;
+	spi->io.write = _spi_m_sync_io_write;
+
+	return ERR_NONE;
+}
+
+void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi)
+{
+	ASSERT(spi);
+	_spi_m_sync_deinit(&spi->dev);
+}
+
+void spi_m_sync_enable(struct spi_m_sync_descriptor *spi)
+{
+	ASSERT(spi);
+	_spi_m_sync_enable(&spi->dev);
+}
+
+void spi_m_sync_disable(struct spi_m_sync_descriptor *spi)
+{
+	ASSERT(spi);
+	_spi_m_sync_disable(&spi->dev);
+}
+
+int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val)
+{
+	ASSERT(spi);
+	return _spi_m_sync_set_baudrate(&spi->dev, baud_val);
+}
+
+int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode)
+{
+	ASSERT(spi);
+	return _spi_m_sync_set_mode(&spi->dev, mode);
+}
+
+int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size)
+{
+	ASSERT(spi);
+	return _spi_m_sync_set_char_size(&spi->dev, char_size);
+}
+
+int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord)
+{
+	ASSERT(spi);
+	return _spi_m_sync_set_data_order(&spi->dev, dord);
+}
+
+/** \brief Do SPI read in polling way
+ *  For SPI master, activate CS, do send 0xFFs and read data, deactivate CS.
+ *
+ *  It blocks until all data read or error.
+ *
+ *  \param[in, out] spi Pointer to the HAL SPI instance.
+ *  \param[out] buf Pointer to the buffer to store read data.
+ *  \param[in] size Size of the data in number of characters.
+ *  \return Operation status.
+ *  \retval size Success.
+ *  \retval >=0 Time out, with number of characters read.
+ */
+static int32_t _spi_m_sync_io_read(struct io_descriptor *io, uint8_t *buf, const uint16_t length)
+{
+	ASSERT(io);
+
+	struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io);
+	struct spi_xfer               xfer;
+
+	xfer.rxbuf = buf;
+	xfer.txbuf = 0;
+	xfer.size  = length;
+
+	return spi_m_sync_transfer(spi, &xfer);
+}
+
+/** \brief Do SPI data write in polling way
+ *  For SPI master, activate CS, do buffer send and deactivate CS. The data back
+ *  is discarded.
+ *
+ *  The data read back is discarded.
+ *
+ *  It blocks until all data sent or error.
+ *
+ *  \param[in, out] spi Pointer to the HAL SPI instance.
+ *  \param[in] p_xfer Pointer to the transfer information (\ref spi_transfer).
+ *  \return Operation status.
+ *  \retval size Success.
+ *  \retval >=0 Timeout, with number of characters transferred.
+ */
+static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length)
+{
+	ASSERT(io);
+
+	struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io);
+	struct spi_xfer               xfer;
+
+	xfer.rxbuf = 0;
+	xfer.txbuf = (uint8_t *)buf;
+	xfer.size  = length;
+
+	return spi_m_sync_transfer(spi, &xfer);
+}
+
+int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer)
+{
+	struct spi_msg msg;
+
+	ASSERT(spi && p_xfer);
+
+	msg.txbuf = p_xfer->txbuf;
+	msg.rxbuf = p_xfer->rxbuf;
+	msg.size  = p_xfer->size;
+	return _spi_m_sync_trans(&spi->dev, &msg);
+}
+
+int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io)
+{
+	ASSERT(spi && io);
+	*io = &spi->io;
+	return 0;
+}
+
+uint32_t spi_m_sync_get_version(void)
+{
+	return SPI_M_SYNC_DRIVER_VERSION;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/compiler.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/compiler.h
new file mode 100644
index 0000000..f35db3d
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/compiler.h
@@ -0,0 +1,64 @@
+/**
+ * \file
+ *
+ * \brief Header
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+/******************************************************************************
+ * compiler.h
+ *
+ * Created: 05.05.2014
+ * Author: N. Fomin
+ ******************************************************************************/
+
+#ifndef _COMPILER_H
+#define _COMPILER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifndef _UNIT_TEST_
+#include "parts.h"
+#endif
+#include "err_codes.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _COMPILER_H */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/err_codes.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/err_codes.h
new file mode 100644
index 0000000..a7aff01
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/err_codes.h
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Error code definitions.
+ *
+ * This file defines various status codes returned by functions,
+ * indicating success or failure as well as what kind of failure.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ERROR_CODES_H_INCLUDED
+#define ERROR_CODES_H_INCLUDED
+
+#define ERR_NONE 0
+#define ERR_INVALID_DATA -1
+#define ERR_NO_CHANGE -2
+#define ERR_ABORTED -3
+#define ERR_BUSY -4
+#define ERR_SUSPEND -5
+#define ERR_IO -6
+#define ERR_REQ_FLUSHED -7
+#define ERR_TIMEOUT -8
+#define ERR_BAD_DATA -9
+#define ERR_NOT_FOUND -10
+#define ERR_UNSUPPORTED_DEV -11
+#define ERR_NO_MEMORY -12
+#define ERR_INVALID_ARG -13
+#define ERR_BAD_ADDRESS -14
+#define ERR_BAD_FORMAT -15
+#define ERR_BAD_FRQ -16
+#define ERR_DENIED -17
+#define ERR_ALREADY_INITIALIZED -18
+#define ERR_OVERFLOW -19
+#define ERR_NOT_INITIALIZED -20
+#define ERR_SAMPLERATE_UNAVAILABLE -21
+#define ERR_RESOLUTION_UNAVAILABLE -22
+#define ERR_BAUDRATE_UNAVAILABLE -23
+#define ERR_PACKET_COLLISION -24
+#define ERR_PROTOCOL -25
+#define ERR_PIN_MUX_INVALID -26
+#define ERR_UNSUPPORTED_OP -27
+#define ERR_NO_RESOURCE -28
+#define ERR_NOT_READY -29
+#define ERR_FAILURE -30
+#define ERR_WRONG_LENGTH -31
+
+#endif
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/events.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/events.h
new file mode 100644
index 0000000..3ee891a
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/events.h
@@ -0,0 +1,54 @@
+/**
+ * \file
+ *
+ * \brief Events declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _EVENTS_H_INCLUDED
+#define _EVENTS_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+
+/**
+ * \brief List of events. Must start with 0, be unique and follow numerical order.
+ */
+#define EVENT_IS_READY_TO_SLEEP_ID 0
+#define EVENT_PREPARE_TO_SLEEP_ID 1
+#define EVENT_WOKEN_UP_ID 2
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _EVENTS_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/parts.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/parts.h
new file mode 100644
index 0000000..5b469cc
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/parts.h
@@ -0,0 +1,41 @@
+/**
+ * \file
+ *
+ * \brief Atmel part identification macros
+ *
+ * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ATMEL_PARTS_H
+#define ATMEL_PARTS_H
+
+#include "samd51.h"
+
+#include "hri_d51.h"
+
+#endif /* ATMEL_PARTS_H */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils.h
new file mode 100644
index 0000000..1cf2699
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils.h
@@ -0,0 +1,368 @@
+/**
+ * \file
+ *
+ * \brief Different macros.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef UTILS_H_INCLUDED
+#define UTILS_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_utils_macro
+ *
+ * @{
+ */
+
+/**
+ * \brief Retrieve pointer to parent structure
+ */
+#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name)))
+
+/**
+ * \brief Retrieve array size
+ */
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+/**
+ * \brief Emit the compiler pragma \a arg.
+ *
+ * \param[in] arg  The pragma directive as it would appear after \e \#pragma
+ *             (i.e. not stringified).
+ */
+#define COMPILER_PRAGMA(arg) _Pragma(#arg)
+
+/**
+ * \def COMPILER_PACK_SET(alignment)
+ * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment.
+ */
+#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
+
+/**
+ * \def COMPILER_PACK_RESET()
+ * \brief Set default alignment for subsequent struct and union definitions.
+ */
+#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
+
+/**
+ * \brief Set aligned boundary.
+ */
+#if defined __GNUC__
+#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
+#elif defined __ICCARM__
+#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)
+#elif defined __CC_ARM
+#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
+#endif
+
+/**
+ * \brief Flash located data macros
+ */
+#if defined __GNUC__
+#define PROGMEM_DECLARE(type, name) const type name
+#define PROGMEM_T const
+#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x))
+#define PROGMEM_PTR_T const *
+#define PROGMEM_STRING_T const uint8_t *
+#elif defined __ICCARM__
+#define PROGMEM_DECLARE(type, name) const type name
+#define PROGMEM_T const
+#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x))
+#define PROGMEM_PTR_T const *
+#define PROGMEM_STRING_T const uint8_t *
+#elif defined __CC_ARM
+#define PROGMEM_DECLARE(type, name) const type name
+#define PROGMEM_T const
+#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x))
+#define PROGMEM_PTR_T const *
+#define PROGMEM_STRING_T const uint8_t *
+#endif
+
+/**
+ * \brief Optimization
+ */
+#if defined __GNUC__
+#define OPTIMIZE_HIGH __attribute__((optimize(s)))
+#elif defined __CC_ARM
+#define OPTIMIZE_HIGH _Pragma("O3")
+#elif defined __ICCARM__
+#define OPTIMIZE_HIGH _Pragma("optimize=high")
+#endif
+
+/**
+ * \brief RAM located function attribute
+ */
+#if defined(__CC_ARM) /* Keil ?Vision 4 */
+#define RAMFUNC __attribute__((section(".ramfunc")))
+#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */
+#define RAMFUNC __ramfunc
+#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */
+#define RAMFUNC __attribute__((section(".ramfunc")))
+#endif
+
+/**
+ * \brief No-init section.
+ * Place a data object or a function in a no-init section.
+ */
+#if defined(__CC_ARM)
+#define NO_INIT(a) __attribute__((zero_init))
+#elif defined(__ICCARM__)
+#define NO_INIT(a) __no_init
+#elif defined(__GNUC__)
+#define NO_INIT(a) __attribute__((section(".no_init")))
+#endif
+
+/**
+ * \brief Set user-defined section.
+ * Place a data object or a function in a user-defined section.
+ */
+#if defined(__CC_ARM)
+#define COMPILER_SECTION(a) __attribute__((__section__(a)))
+#elif defined(__ICCARM__)
+#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a)
+#elif defined(__GNUC__)
+#define COMPILER_SECTION(a) __attribute__((__section__(a)))
+#endif
+
+/**
+ * \brief Define WEAK attribute.
+ */
+#if defined(__CC_ARM) /* Keil ?Vision 4 */
+#define WEAK __attribute__((weak))
+#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */
+#define WEAK __weak
+#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */
+#define WEAK __attribute__((weak))
+#endif
+
+/**
+ * \brief Pointer to function
+ */
+typedef void (*FUNC_PTR)(void);
+
+#define LE_BYTE0(a) ((uint8_t)(a))
+#define LE_BYTE1(a) ((uint8_t)((a) >> 8))
+#define LE_BYTE2(a) ((uint8_t)((a) >> 16))
+#define LE_BYTE3(a) ((uint8_t)((a) >> 24))
+
+#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8))
+#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24))
+
+/** \name Zero-Bit Counting
+ *
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
+ * applied to constant expressions (values known at compile time), so they are
+ * more optimized than the use of the corresponding assembly instructions and
+ * they can be used as constant expressions e.g. to initialize objects having
+ * static storage duration, and like the corresponding assembly instructions
+ * when applied to non-constant expressions (values unknown at compile time), so
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz
+ * ensure a possible and optimized behavior for both constant and non-constant
+ * expressions.
+ *
+ * @{ */
+
+/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the leading zero bits.
+ *
+ * \return The count of leading zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#define clz(u) __builtin_clz(u)
+#else
+#define clz(u)                                                                                                                                                                                                                                                                                                                                                                                     \
+	(                                                                                                                                                                                                                                                                                                                                                                                              \
+	    ((u) == 0)                                                                                                                                                                                                                                                                                                                                                                                 \
+	        ? 32                                                                                                                                                                                                                                                                                                                                                                                   \
+	        : ((u) & (1ul << 31))                                                                                                                                                                                                                                                                                                                                                                  \
+	              ? 0                                                                                                                                                                                                                                                                                                                                                                              \
+	              : ((u) & (1ul << 30))                                                                                                                                                                                                                                                                                                                                                            \
+	                    ? 1                                                                                                                                                                                                                                                                                                                                                                        \
+	                    : ((u) & (1ul << 29))                                                                                                                                                                                                                                                                                                                                                      \
+	                          ? 2                                                                                                                                                                                                                                                                                                                                                                  \
+	                          : ((u) & (1ul << 28))                                                                                                                                                                                                                                                                                                                                                \
+	                                ? 3                                                                                                                                                                                                                                                                                                                                                            \
+	                                : ((u) & (1ul << 27))                                                                                                                                                                                                                                                                                                                                          \
+	                                      ? 4                                                                                                                                                                                                                                                                                                                                                      \
+	                                      : ((u) & (1ul << 26))                                                                                                                                                                                                                                                                                                                                    \
+	                                            ? 5                                                                                                                                                                                                                                                                                                                                                \
+	                                            : ((u) & (1ul << 25))                                                                                                                                                                                                                                                                                                                              \
+	                                                  ? 6                                                                                                                                                                                                                                                                                                                                          \
+	                                                  : ((u) & (1ul << 24))                                                                                                                                                                                                                                                                                                                        \
+	                                                        ? 7                                                                                                                                                                                                                                                                                                                                    \
+	                                                        : ((u) & (1ul << 23))                                                                                                                                                                                                                                                                                                                  \
+	                                                              ? 8                                                                                                                                                                                                                                                                                                                              \
+	                                                              : ((u) & (1ul << 22))                                                                                                                                                                                                                                                                                                            \
+	                                                                    ? 9                                                                                                                                                                                                                                                                                                                        \
+	                                                                    : ((u) & (1ul << 21))                                                                                                                                                                                                                                                                                                      \
+	                                                                          ? 10                                                                                                                                                                                                                                                                                                                 \
+	                                                                          : ((u) & (1ul << 20))                                                                                                                                                                                                                                                                                                \
+	                                                                                ? 11                                                                                                                                                                                                                                                                                                           \
+	                                                                                : ((u) & (1ul << 19))                                                                                                                                                                                                                                                                                          \
+	                                                                                      ? 12                                                                                                                                                                                                                                                                                                     \
+	                                                                                      : ((u) & (1ul << 18))                                                                                                                                                                                                                                                                                    \
+	                                                                                            ? 13                                                                                                                                                                                                                                                                                               \
+	                                                                                            : ((u) & (1ul << 17)) ? 14                                                                                                                                                                                                                                                                         \
+	                                                                                                                  : ((u) & (1ul << 16)) ? 15                                                                                                                                                                                                                                                   \
+	                                                                                                                                        : ((u) & (1ul << 15)) ? 16                                                                                                                                                                                                                             \
+	                                                                                                                                                              : ((u) & (1ul << 14)) ? 17                                                                                                                                                                                                       \
+	                                                                                                                                                                                    : ((u) & (1ul << 13)) ? 18                                                                                                                                                                                 \
+	                                                                                                                                                                                                          : ((u) & (1ul << 12)) ? 19                                                                                                                                                           \
+	                                                                                                                                                                                                                                : ((u)                                                                                                                                                         \
+	                                                                                                                                                                                                                                   & (1ul                                                                                                                                                      \
+	                                                                                                                                                                                                                                      << 11))                                                                                                                                                  \
+	                                                                                                                                                                                                                                      ? 20                                                                                                                                                     \
+	                                                                                                                                                                                                                                      : ((u)                                                                                                                                                   \
+	                                                                                                                                                                                                                                         & (1ul                                                                                                                                                \
+	                                                                                                                                                                                                                                            << 10))                                                                                                                                            \
+	                                                                                                                                                                                                                                            ? 21                                                                                                                                               \
+	                                                                                                                                                                                                                                            : ((u)                                                                                                                                             \
+	                                                                                                                                                                                                                                               & (1ul                                                                                                                                          \
+	                                                                                                                                                                                                                                                  << 9))                                                                                                                                       \
+	                                                                                                                                                                                                                                                  ? 22                                                                                                                                         \
+	                                                                                                                                                                                                                                                  : ((u)                                                                                                                                       \
+	                                                                                                                                                                                                                                                     & (1ul                                                                                                                                    \
+	                                                                                                                                                                                                                                                        << 8))                                                                                                                                 \
+	                                                                                                                                                                                                                                                        ? 23                                                                                                                                   \
+	                                                                                                                                                                                                                                                        : ((u) & (1ul << 7)) ? 24                                                                                                              \
+	                                                                                                                                                                                                                                                                             : ((u) & (1ul << 6)) ? 25                                                                                         \
+	                                                                                                                                                                                                                                                                                                  : ((u)                                                                                       \
+	                                                                                                                                                                                                                                                                                                     & (1ul                                                                                    \
+	                                                                                                                                                                                                                                                                                                        << 5))                                                                                 \
+	                                                                                                                                                                                                                                                                                                        ? 26                                                                                   \
+	                                                                                                                                                                                                                                                                                                        : ((u) & (1ul << 4)) ? 27                                                              \
+	                                                                                                                                                                                                                                                                                                                             : ((u) & (1ul << 3)) ? 28                                         \
+	                                                                                                                                                                                                                                                                                                                                                  : ((u) & (1ul << 2)) ? 29                    \
+	                                                                                                                                                                                                                                                                                                                                                                       : (                     \
+	                                                                                                                                                                                                                                                                                                                                                                             (u) & (1ul << 1)) \
+	                                                                                                                                                                                                                                                                                                                                                                             ? 30              \
+	                                                                                                                                                                                                                                                                                                                                                                             : 31)
+#endif
+
+/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the trailing zero bits.
+ *
+ * \return The count of trailing zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#define ctz(u) __builtin_ctz(u)
+#else
+#define ctz(u)                                                                                                                                                                                                                                                                                                   \
+	(                                                                                                                                                                                                                                                                                                            \
+	    (u) & (1ul << 0)                                                                                                                                                                                                                                                                                         \
+	        ? 0                                                                                                                                                                                                                                                                                                  \
+	        : (u) & (1ul << 1)                                                                                                                                                                                                                                                                                   \
+	              ? 1                                                                                                                                                                                                                                                                                            \
+	              : (u) & (1ul << 2)                                                                                                                                                                                                                                                                             \
+	                    ? 2                                                                                                                                                                                                                                                                                      \
+	                    : (u) & (1ul << 3)                                                                                                                                                                                                                                                                       \
+	                          ? 3                                                                                                                                                                                                                                                                                \
+	                          : (u) & (1ul << 4)                                                                                                                                                                                                                                                                 \
+	                                ? 4                                                                                                                                                                                                                                                                          \
+	                                : (u) & (1ul << 5)                                                                                                                                                                                                                                                           \
+	                                      ? 5                                                                                                                                                                                                                                                                    \
+	                                      : (u) & (1ul << 6)                                                                                                                                                                                                                                                     \
+	                                            ? 6                                                                                                                                                                                                                                                              \
+	                                            : (u) & (1ul << 7)                                                                                                                                                                                                                                               \
+	                                                  ? 7                                                                                                                                                                                                                                                        \
+	                                                  : (u) & (1ul << 8)                                                                                                                                                                                                                                         \
+	                                                        ? 8                                                                                                                                                                                                                                                  \
+	                                                        : (u) & (1ul << 9)                                                                                                                                                                                                                                   \
+	                                                              ? 9                                                                                                                                                                                                                                            \
+	                                                              : (u) & (1ul << 10)                                                                                                                                                                                                                            \
+	                                                                    ? 10                                                                                                                                                                                                                                     \
+	                                                                    : (u) & (1ul << 11)                                                                                                                                                                                                                      \
+	                                                                          ? 11                                                                                                                                                                                                                               \
+	                                                                          : (u) & (1ul << 12)                                                                                                                                                                                                                \
+	                                                                                ? 12                                                                                                                                                                                                                         \
+	                                                                                : (u) & (1ul << 13)                                                                                                                                                                                                          \
+	                                                                                      ? 13                                                                                                                                                                                                                   \
+	                                                                                      : (u) & (1ul << 14)                                                                                                                                                                                                    \
+	                                                                                            ? 14                                                                                                                                                                                                             \
+	                                                                                            : (u) & (1ul << 15)                                                                                                                                                                                              \
+	                                                                                                  ? 15                                                                                                                                                                                                       \
+	                                                                                                  : (u) & (1ul << 16)                                                                                                                                                                                        \
+	                                                                                                        ? 16                                                                                                                                                                                                 \
+	                                                                                                        : (u) & (1ul << 17)                                                                                                                                                                                  \
+	                                                                                                              ? 17                                                                                                                                                                                           \
+	                                                                                                              : (u) & (1ul << 18)                                                                                                                                                                            \
+	                                                                                                                    ? 18                                                                                                                                                                                     \
+	                                                                                                                    : (u) & (1ul << 19) ? 19                                                                                                                                                                 \
+	                                                                                                                                        : (u) & (1ul << 20) ? 20                                                                                                                                             \
+	                                                                                                                                                            : (u) & (1ul << 21) ? 21                                                                                                                         \
+	                                                                                                                                                                                : (u) & (1ul << 22) ? 22                                                                                                     \
+	                                                                                                                                                                                                    : (u) & (1ul << 23) ? 23                                                                                 \
+	                                                                                                                                                                                                                        : (u) & (1ul << 24) ? 24                                                             \
+	                                                                                                                                                                                                                                            : (u) & (1ul << 25) ? 25                                         \
+	                                                                                                                                                                                                                                                                : (u) & (1ul << 26) ? 26                     \
+	                                                                                                                                                                                                                                                                                    : (u) & (1ul << 27) ? 27 \
+	                                                                                                                                                                                                                                                                                                        : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32)
+#endif
+/** @} */
+
+/**
+ * \brief Counts the number of bits in a mask (no more than 32 bits)
+ * \param[in] mask Mask of which to count the bits.
+ */
+#define size_of_mask(mask) (32 - clz(mask) - ctz(mask))
+
+/**
+ * \brief Retrieve the start position of bits mask (no more than 32 bits)
+ * \param[in] mask Mask of which to retrieve the start position.
+ */
+#define pos_of_mask(mask) ctz(mask)
+
+/**
+ * \brief Return division result of a/b and round up the result to the closest
+ *        number divisible by "b"
+ */
+#define round_up(a, b) (((a)-1) / (b) + 1)
+
+/**
+ * \brief Get the minimum of x and y
+ */
+#define min(x, y) ((x) > (y) ? (y) : (x))
+
+/**
+ * \brief Get the maximum of x and y
+ */
+#define max(x, y) ((x) > (y) ? (x) : (y))
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* UTILS_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_assert.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_assert.h
new file mode 100644
index 0000000..c2328d6
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_assert.h
@@ -0,0 +1,93 @@
+/**
+ * \file
+ *
+ * \brief Asserts related functionality.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _ASSERT_H_INCLUDED
+#define _ASSERT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+
+#ifndef USE_SIMPLE_ASSERT
+//# define USE_SIMPLE_ASSERT
+#endif
+
+/**
+ * \brief Assert macro
+ *
+ * This macro is used to throw asserts. It can be mapped to different function
+ * based on debug level.
+ *
+ * \param[in] condition A condition to be checked;
+ *                      assert is thrown if the given condition is false
+ */
+#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__)
+
+#ifdef DEBUG
+
+#ifdef USE_SIMPLE_ASSERT
+#define ASSERT_IMPL(condition, file, line)                                                                             \
+	if (!(condition))                                                                                                  \
+		__asm("BKPT #0");
+#else
+#define ASSERT_IMPL(condition, file, line) assert((condition), file, line)
+#endif
+
+#else /* DEBUG */
+
+#ifdef USE_SIMPLE_ASSERT
+#define ASSERT_IMPL(condition, file, line) ((void)0)
+#else
+#define ASSERT_IMPL(condition, file, line) ((void)0)
+#endif
+
+#endif /* DEBUG */
+
+/**
+ * \brief Assert function
+ *
+ * This function is used to throw asserts.
+ *
+ * \param[in] condition A condition to be checked; assert is thrown if the given
+ *                      condition is false
+ * \param[in] file File name
+ * \param[in] line Line number
+ */
+void assert(const bool condition, const char *const file, const int line);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _ASSERT_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_event.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_event.h
new file mode 100644
index 0000000..13067c4
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_event.h
@@ -0,0 +1,115 @@
+/**
+ * \file
+ *
+ * \brief Events declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_EVENT_H_INCLUDED
+#define _UTILS_EVENT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <utils.h>
+#include <utils_list.h>
+#include <events.h>
+
+/**
+ * \brief The maximum amount of events
+ */
+#define EVENT_MAX_AMOUNT 8
+
+/**
+ * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the
+ *        closest number divisible by 8.
+ */
+#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8))
+
+/**
+ * \brief The type of event ID. IDs should start with 0 and be in numerical order.
+ */
+typedef uint8_t event_id_t;
+
+/**
+ * \brief The type of returned parameter. This type is big enough to contain
+ *        pointer to data on any platform.
+ */
+typedef uintptr_t event_data_t;
+
+/**
+ * \brief The type of returned parameter. This type is big enough to contain
+ *        pointer to data on any platform.
+ */
+typedef void (*event_cb_t)(event_id_t id, event_data_t data);
+
+/**
+ * \brief Event structure
+ */
+struct event {
+	struct list_element elem;                  /*! The pointer to next event */
+	uint8_t             mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */
+	event_cb_t          cb;                    /*! Callback to be called when an event occurs */
+};
+
+/**
+ * \brief Subscribe to event
+ *
+ * \param[in] event The pointer to event structure
+ * \param[in] id The event ID to subscribe to
+ * \param[in] cb The callback function to call when the given event occurs
+ *
+ * \return The status of subscription
+ */
+int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb);
+
+/**
+ * \brief Remove event from subscription
+ *
+ * \param[in] event The pointer to event structure
+ * \param[in] id The event ID to remove subscription from
+ *
+ * \return The status of subscription removing
+ */
+int32_t event_unsubscribe(struct event *const event, const event_id_t id);
+
+/**
+ * \brief Post event
+ *
+ * \param[in] id The event ID to post
+ * \param[in] data The event data to be passed to event subscribers
+ */
+void event_post(const event_id_t id, const event_data_t data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _UTILS_EVENT_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_increment_macro.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_increment_macro.h
new file mode 100644
index 0000000..464c6cb
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_increment_macro.h
@@ -0,0 +1,308 @@
+/**
+ * \file
+ *
+ * \brief Increment macro.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_INCREMENT_MACRO_H
+#define _UTILS_INCREMENT_MACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Compile time increment, result value is entire integer literal
+ *
+ * \param[in] val - value to be incremented (254 max)
+ */
+#define INC_VALUE(val) SP_INC_##val
+
+// Preprocessor increment implementation
+#define SP_INC_0 1
+#define SP_INC_1 2
+#define SP_INC_2 3
+#define SP_INC_3 4
+#define SP_INC_4 5
+#define SP_INC_5 6
+#define SP_INC_6 7
+#define SP_INC_7 8
+#define SP_INC_8 9
+#define SP_INC_9 10
+#define SP_INC_10 11
+#define SP_INC_11 12
+#define SP_INC_12 13
+#define SP_INC_13 14
+#define SP_INC_14 15
+#define SP_INC_15 16
+#define SP_INC_16 17
+#define SP_INC_17 18
+#define SP_INC_18 19
+#define SP_INC_19 20
+#define SP_INC_20 21
+#define SP_INC_21 22
+#define SP_INC_22 23
+#define SP_INC_23 24
+#define SP_INC_24 25
+#define SP_INC_25 26
+#define SP_INC_26 27
+#define SP_INC_27 28
+#define SP_INC_28 29
+#define SP_INC_29 30
+#define SP_INC_30 31
+#define SP_INC_31 32
+#define SP_INC_32 33
+#define SP_INC_33 34
+#define SP_INC_34 35
+#define SP_INC_35 36
+#define SP_INC_36 37
+#define SP_INC_37 38
+#define SP_INC_38 39
+#define SP_INC_39 40
+#define SP_INC_40 41
+#define SP_INC_41 42
+#define SP_INC_42 43
+#define SP_INC_43 44
+#define SP_INC_44 45
+#define SP_INC_45 46
+#define SP_INC_46 47
+#define SP_INC_47 48
+#define SP_INC_48 49
+#define SP_INC_49 50
+#define SP_INC_50 51
+#define SP_INC_51 52
+#define SP_INC_52 53
+#define SP_INC_53 54
+#define SP_INC_54 55
+#define SP_INC_55 56
+#define SP_INC_56 57
+#define SP_INC_57 58
+#define SP_INC_58 59
+#define SP_INC_59 60
+#define SP_INC_60 61
+#define SP_INC_61 62
+#define SP_INC_62 63
+#define SP_INC_63 64
+#define SP_INC_64 65
+#define SP_INC_65 66
+#define SP_INC_66 67
+#define SP_INC_67 68
+#define SP_INC_68 69
+#define SP_INC_69 70
+#define SP_INC_70 71
+#define SP_INC_71 72
+#define SP_INC_72 73
+#define SP_INC_73 74
+#define SP_INC_74 75
+#define SP_INC_75 76
+#define SP_INC_76 77
+#define SP_INC_77 78
+#define SP_INC_78 79
+#define SP_INC_79 80
+#define SP_INC_80 81
+#define SP_INC_81 82
+#define SP_INC_82 83
+#define SP_INC_83 84
+#define SP_INC_84 85
+#define SP_INC_85 86
+#define SP_INC_86 87
+#define SP_INC_87 88
+#define SP_INC_88 89
+#define SP_INC_89 90
+#define SP_INC_90 91
+#define SP_INC_91 92
+#define SP_INC_92 93
+#define SP_INC_93 94
+#define SP_INC_94 95
+#define SP_INC_95 96
+#define SP_INC_96 97
+#define SP_INC_97 98
+#define SP_INC_98 99
+#define SP_INC_99 100
+#define SP_INC_100 101
+#define SP_INC_101 102
+#define SP_INC_102 103
+#define SP_INC_103 104
+#define SP_INC_104 105
+#define SP_INC_105 106
+#define SP_INC_106 107
+#define SP_INC_107 108
+#define SP_INC_108 109
+#define SP_INC_109 110
+#define SP_INC_110 111
+#define SP_INC_111 112
+#define SP_INC_112 113
+#define SP_INC_113 114
+#define SP_INC_114 115
+#define SP_INC_115 116
+#define SP_INC_116 117
+#define SP_INC_117 118
+#define SP_INC_118 119
+#define SP_INC_119 120
+#define SP_INC_120 121
+#define SP_INC_121 122
+#define SP_INC_122 123
+#define SP_INC_123 124
+#define SP_INC_124 125
+#define SP_INC_125 126
+#define SP_INC_126 127
+#define SP_INC_127 128
+#define SP_INC_128 129
+#define SP_INC_129 130
+#define SP_INC_130 131
+#define SP_INC_131 132
+#define SP_INC_132 133
+#define SP_INC_133 134
+#define SP_INC_134 135
+#define SP_INC_135 136
+#define SP_INC_136 137
+#define SP_INC_137 138
+#define SP_INC_138 139
+#define SP_INC_139 140
+#define SP_INC_140 141
+#define SP_INC_141 142
+#define SP_INC_142 143
+#define SP_INC_143 144
+#define SP_INC_144 145
+#define SP_INC_145 146
+#define SP_INC_146 147
+#define SP_INC_147 148
+#define SP_INC_148 149
+#define SP_INC_149 150
+#define SP_INC_150 151
+#define SP_INC_151 152
+#define SP_INC_152 153
+#define SP_INC_153 154
+#define SP_INC_154 155
+#define SP_INC_155 156
+#define SP_INC_156 157
+#define SP_INC_157 158
+#define SP_INC_158 159
+#define SP_INC_159 160
+#define SP_INC_160 161
+#define SP_INC_161 162
+#define SP_INC_162 163
+#define SP_INC_163 164
+#define SP_INC_164 165
+#define SP_INC_165 166
+#define SP_INC_166 167
+#define SP_INC_167 168
+#define SP_INC_168 169
+#define SP_INC_169 170
+#define SP_INC_170 171
+#define SP_INC_171 172
+#define SP_INC_172 173
+#define SP_INC_173 174
+#define SP_INC_174 175
+#define SP_INC_175 176
+#define SP_INC_176 177
+#define SP_INC_177 178
+#define SP_INC_178 179
+#define SP_INC_179 180
+#define SP_INC_180 181
+#define SP_INC_181 182
+#define SP_INC_182 183
+#define SP_INC_183 184
+#define SP_INC_184 185
+#define SP_INC_185 186
+#define SP_INC_186 187
+#define SP_INC_187 188
+#define SP_INC_188 189
+#define SP_INC_189 190
+#define SP_INC_190 191
+#define SP_INC_191 192
+#define SP_INC_192 193
+#define SP_INC_193 194
+#define SP_INC_194 195
+#define SP_INC_195 196
+#define SP_INC_196 197
+#define SP_INC_197 198
+#define SP_INC_198 199
+#define SP_INC_199 200
+#define SP_INC_200 201
+#define SP_INC_201 202
+#define SP_INC_202 203
+#define SP_INC_203 204
+#define SP_INC_204 205
+#define SP_INC_205 206
+#define SP_INC_206 207
+#define SP_INC_207 208
+#define SP_INC_208 209
+#define SP_INC_209 210
+#define SP_INC_210 211
+#define SP_INC_211 212
+#define SP_INC_212 213
+#define SP_INC_213 214
+#define SP_INC_214 215
+#define SP_INC_215 216
+#define SP_INC_216 217
+#define SP_INC_217 218
+#define SP_INC_218 219
+#define SP_INC_219 220
+#define SP_INC_220 221
+#define SP_INC_221 222
+#define SP_INC_222 223
+#define SP_INC_223 224
+#define SP_INC_224 225
+#define SP_INC_225 226
+#define SP_INC_226 227
+#define SP_INC_227 228
+#define SP_INC_228 229
+#define SP_INC_229 230
+#define SP_INC_230 231
+#define SP_INC_231 232
+#define SP_INC_232 233
+#define SP_INC_233 234
+#define SP_INC_234 235
+#define SP_INC_235 236
+#define SP_INC_236 237
+#define SP_INC_237 238
+#define SP_INC_238 239
+#define SP_INC_239 240
+#define SP_INC_240 241
+#define SP_INC_241 242
+#define SP_INC_242 243
+#define SP_INC_243 244
+#define SP_INC_244 245
+#define SP_INC_245 246
+#define SP_INC_246 247
+#define SP_INC_247 248
+#define SP_INC_248 249
+#define SP_INC_249 250
+#define SP_INC_250 251
+#define SP_INC_251 252
+#define SP_INC_252 253
+#define SP_INC_253 254
+#define SP_INC_254 255
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _UTILS_INCREMENT_MACRO_H */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_list.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_list.h
new file mode 100644
index 0000000..977e8cc
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_list.h
@@ -0,0 +1,164 @@
+/**
+ * \file
+ *
+ * \brief List declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_LIST_H_INCLUDED
+#define _UTILS_LIST_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_utils_list
+ *
+ * @{
+ */
+
+#include <compiler.h>
+
+/**
+ * \brief List element type
+ */
+struct list_element {
+	struct list_element *next;
+};
+
+/**
+ * \brief List head type
+ */
+struct list_descriptor {
+	struct list_element *head;
+};
+
+/**
+ * \brief Reset list
+ *
+ * \param[in] list The pointer to a list descriptor
+ */
+static inline void list_reset(struct list_descriptor *const list)
+{
+	list->head = NULL;
+}
+
+/**
+ * \brief Retrieve list head
+ *
+ * \param[in] list The pointer to a list descriptor
+ *
+ * \return A pointer to the head of the given list or NULL if the list is
+ * empty
+ */
+static inline void *list_get_head(const struct list_descriptor *const list)
+{
+	return (void *)list->head;
+}
+
+/**
+ * \brief Retrieve next list head
+ *
+ * \param[in] list The pointer to a list element
+ *
+ * \return A pointer to the next list element or NULL if there is not next
+ * element
+ */
+static inline void *list_get_next_element(const void *const element)
+{
+	return element ? ((struct list_element *)element)->next : NULL;
+}
+
+/**
+ * \brief Insert an element as list head
+ *
+ * \param[in] list The pointer to a list element
+ * \param[in] element An element to insert to the given list
+ */
+void list_insert_as_head(struct list_descriptor *const list, void *const element);
+
+/**
+ * \brief Insert an element after the given list element
+ *
+ * \param[in] after An element to insert after
+ * \param[in] element Element to insert to the given list
+ */
+void list_insert_after(void *const after, void *const element);
+
+/**
+ * \brief Insert an element at list end
+ *
+ * \param[in] after An element to insert after
+ * \param[in] element Element to insert to the given list
+ */
+void list_insert_at_end(struct list_descriptor *const list, void *const element);
+
+/**
+ * \brief Check whether an element belongs to a list
+ *
+ * \param[in] list The pointer to a list
+ * \param[in] element An element to check
+ *
+ * \return The result of checking
+ * \retval true If the given element is an element of the given list
+ * \retval false Otherwise
+ */
+bool is_list_element(const struct list_descriptor *const list, const void *const element);
+
+/**
+ * \brief Removes list head
+ *
+ * This function removes the list head and sets the next element after the list
+ * head as a new list head.
+ *
+ * \param[in] list The pointer to a list
+ *
+ * \return The pointer to the new list head of NULL if the list head is NULL
+ */
+void *list_remove_head(struct list_descriptor *const list);
+
+/**
+ * \brief Removes the list element
+ *
+ * \param[in] list The pointer to a list
+ * \param[in] element An element to remove
+ *
+ * \return The result of element removing
+ * \retval true The given element is removed from the given list
+ * \retval false The given element is not an element of the given list
+ */
+bool list_delete_element(struct list_descriptor *const list, const void *const element);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _UTILS_LIST_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_repeat_macro.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_repeat_macro.h
new file mode 100644
index 0000000..89e6f52
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/include/utils_repeat_macro.h
@@ -0,0 +1,322 @@
+/**
+ * \file
+ *
+ * \brief Repeat macro.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_REPEAT_MACRO_H
+#define _UTILS_REPEAT_MACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * \brief Sequently repeates specified macro for n times (255 max).
+ *
+ * Specified macro shall have two arguments:  macro(arg, i)
+ *   arg - user defined argument, which have the same value for all iterations.
+ *   i - iteration number; numbering begins from zero and increments on each
+ *   iteration.
+ *
+ * \param[in] macro - macro to be repeated
+ * \param[in] arg - user defined argument for repeated macro
+ * \param[in] n - total number of iterations (255 max)
+ */
+#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n)
+
+/*
+ * \brief Second level is needed to get integer literal from "n" if it is
+ *        defined as macro
+ */
+#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0)
+
+#define REPEAT1(macro, arg, n) macro(arg, n)
+#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n))
+#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n))
+#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n))
+#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n))
+#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n))
+#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n))
+#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n))
+#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n))
+#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n))
+#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n))
+#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n))
+#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n))
+#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n))
+#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n))
+#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n))
+#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n))
+#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n))
+#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n))
+#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n))
+#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n))
+#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n))
+#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n))
+#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n))
+#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n))
+#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n))
+#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n))
+#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n))
+#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n))
+#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n))
+#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n))
+#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n))
+#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n))
+#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n))
+#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n))
+#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n))
+#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n))
+#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n))
+#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n))
+#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n))
+#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n))
+#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n))
+#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n))
+#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n))
+#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n))
+#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n))
+#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n))
+#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n))
+#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n))
+#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n))
+#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n))
+#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n))
+#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n))
+#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n))
+#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n))
+#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n))
+#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n))
+#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n))
+#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n))
+#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n))
+#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n))
+#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n))
+#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n))
+#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n))
+#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n))
+#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n))
+#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n))
+#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n))
+#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n))
+#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n))
+#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n))
+#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n))
+#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n))
+#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n))
+#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n))
+#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n))
+#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n))
+#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n))
+#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n))
+#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n))
+#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n))
+#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n))
+#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n))
+#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n))
+#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n))
+#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n))
+#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n))
+#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n))
+#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n))
+#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n))
+#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n))
+#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n))
+#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n))
+#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n))
+#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n))
+#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n))
+#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n))
+#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n))
+#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n))
+#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n))
+#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n))
+#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n))
+#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n))
+#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n))
+#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n))
+#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n))
+#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n))
+#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n))
+#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n))
+#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n))
+#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n))
+#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n))
+#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n))
+#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n))
+#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n))
+#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n))
+#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n))
+#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n))
+#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n))
+#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n))
+#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n))
+#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n))
+#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n))
+#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n))
+#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n))
+#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n))
+#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n))
+#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n))
+#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n))
+#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n))
+#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n))
+#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n))
+#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n))
+#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n))
+#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n))
+#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n))
+#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n))
+#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n))
+#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n))
+#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n))
+#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n))
+#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n))
+#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n))
+#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n))
+#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n))
+#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n))
+#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n))
+#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n))
+#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n))
+#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n))
+#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n))
+#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n))
+#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n))
+#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n))
+#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n))
+#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n))
+#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n))
+#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n))
+#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n))
+#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n))
+#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n))
+#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n))
+#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n))
+#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n))
+#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n))
+#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n))
+#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n))
+#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n))
+#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n))
+#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n))
+#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n))
+#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n))
+#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n))
+#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n))
+#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n))
+#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n))
+#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n))
+#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n))
+#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n))
+#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n))
+#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n))
+#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n))
+#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n))
+#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n))
+#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n))
+#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n))
+#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n))
+#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n))
+#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n))
+#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n))
+#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n))
+#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n))
+#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n))
+#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n))
+#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n))
+#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n))
+#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n))
+#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n))
+#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n))
+#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n))
+#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n))
+#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n))
+#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n))
+#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n))
+#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n))
+#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n))
+#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n))
+#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n))
+#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n))
+#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n))
+#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n))
+#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n))
+#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n))
+#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n))
+#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n))
+#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n))
+#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n))
+#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n))
+#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n))
+#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n))
+#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n))
+#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n))
+#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n))
+#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n))
+#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n))
+#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n))
+#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n))
+#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n))
+#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n))
+#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n))
+#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n))
+#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n))
+#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n))
+#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n))
+#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n))
+#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n))
+#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n))
+#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n))
+#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n))
+#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n))
+#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n))
+#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n))
+#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n))
+#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n))
+#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n))
+#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n))
+#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n))
+#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n))
+#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n))
+#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n))
+#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n))
+#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n))
+#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n))
+#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n))
+#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n))
+
+#ifdef __cplusplus
+}
+#endif
+
+#include <utils_increment_macro.h>
+#endif /* _UTILS_REPEAT_MACRO_H */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_assert.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_assert.c
new file mode 100644
index 0000000..b376c97
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_assert.c
@@ -0,0 +1,46 @@
+/**
+ * \file
+ *
+ * \brief Asserts related functionality.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_assert.h>
+
+/**
+ * \brief Assert function
+ */
+void assert(const bool condition, const char *const file, const int line)
+{
+	if (!(condition)) {
+		__asm("BKPT #0");
+	}
+	(void)file;
+	(void)line;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_event.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_event.c
new file mode 100644
index 0000000..d1af9d0
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_event.c
@@ -0,0 +1,125 @@
+/**
+ * \file
+ *
+ * \brief Events implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_event.h>
+#include <utils_assert.h>
+#include <string.h>
+
+#define EVENT_WORD_BITS (sizeof(event_word_t) * 8)
+
+static struct list_descriptor events;
+static uint8_t                subscribed[EVENT_MASK_SIZE];
+
+int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb)
+{
+	/* get byte and bit number of the given event in the event mask */
+	const uint8_t position = id >> 3;
+	const uint8_t mask     = 1 << (id & 0x7);
+
+	ASSERT(event && cb && (id < EVENT_MAX_AMOUNT));
+
+	if (event->mask[position] & mask) {
+		return ERR_NO_CHANGE; /* Already subscribed */
+	}
+
+	if (!is_list_element(&events, event)) {
+		memset(event->mask, 0, EVENT_MASK_SIZE);
+		list_insert_as_head(&events, event);
+	}
+	event->cb = cb;
+	event->mask[position] |= mask;
+
+	subscribed[position] |= mask;
+
+	return ERR_NONE;
+}
+
+int32_t event_unsubscribe(struct event *const event, const event_id_t id)
+{
+	/* get byte and bit number of the given event in the event mask */
+	const uint8_t       position = id >> 3;
+	const uint8_t       mask     = 1 << (id & 0x7);
+	const struct event *current;
+	uint8_t             i;
+
+	ASSERT(event && (id < EVENT_MAX_AMOUNT));
+
+	if (!(event->mask[position] & mask)) {
+		return ERR_NO_CHANGE; /* Already unsubscribed */
+	}
+
+	event->mask[position] &= ~mask;
+
+	/* Check if there are more subscribers */
+	for ((current = (const struct event *)list_get_head(&events)); current;
+	     current = (const struct event *)list_get_next_element(current)) {
+		if (current->mask[position] & mask) {
+			break;
+		}
+	}
+	if (!current) {
+		subscribed[position] &= ~mask;
+	}
+
+	/* Remove event from the list. Can be unsave, document it! */
+	for (i = 0; i < ARRAY_SIZE(event->mask); i++) {
+		if (event->mask[i]) {
+			return ERR_NONE;
+		}
+	}
+	list_delete_element(&events, event);
+
+	return ERR_NONE;
+}
+
+void event_post(const event_id_t id, const event_data_t data)
+{
+	/* get byte and bit number of the given event in the event mask */
+	const uint8_t       position = id >> 3;
+	const uint8_t       mask     = 1 << (id & 0x7);
+	const struct event *current;
+
+	ASSERT((id < EVENT_MAX_AMOUNT));
+
+	if (!(subscribed[position] & mask)) {
+		return; /* No subscribers */
+	}
+
+	/* Find all subscribers */
+	for ((current = (const struct event *)list_get_head(&events)); current;
+	     current = (const struct event *)list_get_next_element(current)) {
+		if (current->mask[position] & mask) {
+			current->cb(id, data);
+		}
+	}
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_list.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_list.c
new file mode 100644
index 0000000..4006a01
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_list.c
@@ -0,0 +1,136 @@
+/**
+ * \file
+ *
+ * \brief List functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_list.h>
+#include <utils_assert.h>
+
+/**
+ * \brief Check whether element belongs to list
+ */
+bool is_list_element(const struct list_descriptor *const list, const void *const element)
+{
+	struct list_element *it;
+	for (it = list->head; it; it = it->next) {
+		if (it == element) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+/**
+ * \brief Insert an element as list head
+ */
+void list_insert_as_head(struct list_descriptor *const list, void *const element)
+{
+	ASSERT(!is_list_element(list, element));
+
+	((struct list_element *)element)->next = list->head;
+	list->head                             = (struct list_element *)element;
+}
+
+/**
+ * \brief Insert an element after the given list element
+ */
+void list_insert_after(void *const after, void *const element)
+{
+	((struct list_element *)element)->next = ((struct list_element *)after)->next;
+	((struct list_element *)after)->next   = (struct list_element *)element;
+}
+
+/**
+ * \brief Insert an element at list end
+ */
+void list_insert_at_end(struct list_descriptor *const list, void *const element)
+{
+	struct list_element *it = list->head;
+
+	ASSERT(!is_list_element(list, element));
+
+	if (!list->head) {
+		list->head                             = (struct list_element *)element;
+		((struct list_element *)element)->next = NULL;
+		return;
+	}
+
+	while (it->next) {
+		it = it->next;
+	}
+	it->next                               = (struct list_element *)element;
+	((struct list_element *)element)->next = NULL;
+}
+
+/**
+ * \brief Removes list head
+ */
+void *list_remove_head(struct list_descriptor *const list)
+{
+	if (list->head) {
+		struct list_element *tmp = list->head;
+
+		list->head = list->head->next;
+		return (void *)tmp;
+	}
+
+	return NULL;
+}
+
+/**
+ * \brief Removes list element
+ */
+bool list_delete_element(struct list_descriptor *const list, const void *const element)
+{
+	if (!element) {
+		return false;
+	}
+
+	if (list->head == element) {
+		list->head = list->head->next;
+		return true;
+	} else {
+		struct list_element *it = list->head;
+
+		while (it && it->next != element) {
+			it = it->next;
+		}
+		if (it) {
+			it->next = ((struct list_element *)element)->next;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+//@}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_syscalls.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_syscalls.c
new file mode 100644
index 0000000..79e2f1f
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/utils/src/utils_syscalls.c
@@ -0,0 +1,152 @@
+/**
+ * \file
+ *
+ * \brief Syscalls for SAM0 (GCC).
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#undef errno
+extern int errno;
+extern int _end;
+
+extern caddr_t _sbrk(int incr);
+extern int     link(char *old, char *_new);
+extern int     _close(int file);
+extern int     _fstat(int file, struct stat *st);
+extern int     _isatty(int file);
+extern int     _lseek(int file, int ptr, int dir);
+extern void    _exit(int status);
+extern void    _kill(int pid, int sig);
+extern int     _getpid(void);
+
+/**
+ * \brief Replacement of C library of _sbrk
+ */
+extern caddr_t _sbrk(int incr)
+{
+	static unsigned char *heap = NULL;
+	unsigned char *       prev_heap;
+
+	if (heap == NULL) {
+		heap = (unsigned char *)&_end;
+	}
+	prev_heap = heap;
+
+	heap += incr;
+
+	return (caddr_t)prev_heap;
+}
+
+/**
+ * \brief Replacement of C library of link
+ */
+extern int link(char *old, char *_new)
+{
+	(void)old, (void)_new;
+	return -1;
+}
+
+/**
+ * \brief Replacement of C library of _close
+ */
+extern int _close(int file)
+{
+	(void)file;
+	return -1;
+}
+
+/**
+ * \brief Replacement of C library of _fstat
+ */
+extern int _fstat(int file, struct stat *st)
+{
+	(void)file;
+	st->st_mode = S_IFCHR;
+
+	return 0;
+}
+
+/**
+ * \brief Replacement of C library of _isatty
+ */
+extern int _isatty(int file)
+{
+	(void)file;
+	return 1;
+}
+
+/**
+ * \brief Replacement of C library of _lseek
+ */
+extern int _lseek(int file, int ptr, int dir)
+{
+	(void)file, (void)ptr, (void)dir;
+	return 0;
+}
+
+/**
+ * \brief Replacement of C library of _exit
+ */
+extern void _exit(int status)
+{
+	printf("Exiting with status %d.\n", status);
+
+	for (;;)
+		;
+}
+
+/**
+ * \brief Replacement of C library of _kill
+ */
+extern void _kill(int pid, int sig)
+{
+	(void)pid, (void)sig;
+	return;
+}
+
+/**
+ * \brief Replacement of C library of _getpid
+ */
+extern int _getpid(void)
+{
+	return -1;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/adc/hpl_adc.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/adc/hpl_adc.c
new file mode 100644
index 0000000..29f7da5
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/adc/hpl_adc.c
@@ -0,0 +1,769 @@
+
+/**
+ * \file
+ *
+ * \brief SAM Analog Digital Converter
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_adc_async.h>
+#include <hpl_adc_dma.h>
+#include <hpl_adc_sync.h>
+#include <utils_assert.h>
+#include <utils_repeat_macro.h>
+#include <hpl_adc_config.h>
+
+#ifndef CONF_ADC_0_ENABLE
+#define CONF_ADC_0_ENABLE 0
+#endif
+#ifndef CONF_ADC_1_ENABLE
+#define CONF_ADC_1_ENABLE 0
+#endif
+
+/**
+ * \brief Macro is used to fill ADC configuration structure based on its number
+ *
+ * \param[in] n The number of structures
+ */
+#define ADC_CONFIGURATION(n)                                                                                           \
+	{                                                                                                                  \
+		(n),                                                                                                           \
+		    (CONF_ADC_##n##_RUNSTDBY << ADC_CTRLA_RUNSTDBY_Pos) | (CONF_ADC_##n##_ONDEMAND << ADC_CTRLA_ONDEMAND_Pos)  \
+		        | ADC_CTRLA_PRESCALER(CONF_ADC_##n##_PRESCALER),                                                       \
+		    ADC_CTRLB_RESSEL(CONF_ADC_##n##_RESSEL) | (CONF_ADC_##n##_CORREN << ADC_CTRLB_CORREN_Pos)                  \
+		        | (CONF_ADC_##n##_FREERUN << ADC_CTRLB_FREERUN_Pos)                                                    \
+		        | (CONF_ADC_##n##_LEFTADJ << ADC_CTRLB_LEFTADJ_Pos) | ADC_CTRLB_WINMODE(CONF_ADC_##n##_WINMODE),       \
+		    (CONF_ADC_##n##_REFCOMP << ADC_REFCTRL_REFCOMP_Pos) | ADC_REFCTRL_REFSEL(CONF_ADC_##n##_REFSEL),           \
+		    (CONF_ADC_##n##_WINMONEO << ADC_EVCTRL_WINMONEO_Pos)                                                       \
+		        | (CONF_ADC_##n##_RESRDYEO << ADC_EVCTRL_RESRDYEO_Pos)                                                 \
+		        | (CONF_ADC_##n##_STARTINV << ADC_EVCTRL_STARTINV_Pos)                                                 \
+		        | (CONF_ADC_##n##_FLUSHINV << ADC_EVCTRL_FLUSHINV_Pos)                                                 \
+		        | (CONF_ADC_##n##_STARTEI << ADC_EVCTRL_STARTEI_Pos)                                                   \
+		        | (CONF_ADC_##n##_FLUSHEI << ADC_EVCTRL_FLUSHEI_Pos),                                                  \
+		    (CONF_ADC_##n##_DIFFMODE << ADC_INPUTCTRL_DIFFMODE_Pos) | ADC_INPUTCTRL_MUXNEG(CONF_ADC_##n##_MUXNEG)      \
+		        | ADC_INPUTCTRL_MUXPOS(CONF_ADC_##n##_MUXPOS),                                                         \
+		    ADC_AVGCTRL_ADJRES(CONF_ADC_##n##_ADJRES) | ADC_AVGCTRL_SAMPLENUM(CONF_ADC_##n##_SAMPLENUM),               \
+		    (CONF_ADC_##n##_OFFCOMP << ADC_SAMPCTRL_OFFCOMP_Pos) | ADC_SAMPCTRL_SAMPLEN(CONF_ADC_##n##_SAMPLEN),       \
+		    ADC_WINLT_WINLT(CONF_ADC_##n##_WINLT), ADC_WINUT_WINUT(CONF_ADC_##n##_WINUT),                              \
+		    ADC_GAINCORR_GAINCORR(CONF_ADC_##n##_GAINCORR), ADC_OFFSETCORR_OFFSETCORR(CONF_ADC_##n##_OFFSETCORR),      \
+		    CONF_ADC_##n##_DBGRUN << ADC_DBGCTRL_DBGRUN_Pos,                                                           \
+	}
+
+/**
+ * \brief ADC configuration
+ */
+struct adc_configuration {
+	uint8_t                  number;
+	hri_adc_ctrla_reg_t      ctrl_a;
+	hri_adc_ctrlb_reg_t      ctrl_b;
+	hri_adc_refctrl_reg_t    ref_ctrl;
+	hri_adc_evctrl_reg_t     ev_ctrl;
+	hri_adc_inputctrl_reg_t  input_ctrl;
+	hri_adc_avgctrl_reg_t    avg_ctrl;
+	hri_adc_sampctrl_reg_t   samp_ctrl;
+	hri_adc_winlt_reg_t      win_lt;
+	hri_adc_winut_reg_t      win_ut;
+	hri_adc_gaincorr_reg_t   gain_corr;
+	hri_adc_offsetcorr_reg_t offset_corr;
+	hri_adc_dbgctrl_reg_t    dbg_ctrl;
+};
+
+#define ADC_AMOUNT (CONF_ADC_0_ENABLE + CONF_ADC_1_ENABLE)
+
+/**
+ * \brief Array of ADC configurations
+ */
+static const struct adc_configuration _adcs[] = {
+#if CONF_ADC_0_ENABLE == 1
+    ADC_CONFIGURATION(0),
+#endif
+#if CONF_ADC_1_ENABLE == 1
+    ADC_CONFIGURATION(1),
+#endif
+};
+
+static void _adc_set_reference_source(void *const hw, const adc_reference_t reference);
+
+/**
+ * \brief Retrieve ordinal number of the given adc hardware instance
+ */
+static uint8_t _adc_get_hardware_index(const void *const hw)
+{
+	return ((uint32_t)hw - (uint32_t)ADC0) >> 10;
+}
+
+/** \brief Return the pointer to register settings of specific ADC
+ *  \param[in] hw_addr The hardware register base address.
+ *  \return Pointer to register settings of specific ADC.
+ */
+static uint8_t _adc_get_regs(const uint32_t hw_addr)
+{
+	uint8_t n = _adc_get_hardware_index((const void *)hw_addr);
+	uint8_t i;
+
+	for (i = 0; i < sizeof(_adcs) / sizeof(struct adc_configuration); i++) {
+		if (_adcs[i].number == n) {
+			return i;
+		}
+	}
+
+	ASSERT(false);
+	return 0;
+}
+
+/**
+ * \brief Retrieve IRQ number for the given hardware instance
+ */
+static uint8_t _adc_get_irq_num(const struct _adc_async_device *const device)
+{
+
+	return ADC0_0_IRQn + (_adc_get_hardware_index(device->hw) << 1);
+}
+
+/**
+ * \brief Init irq param with the given afec hardware instance
+ */
+static void _adc_init_irq_param(const void *const hw, struct _adc_async_device *dev)
+{
+}
+
+/**
+ * \brief Initialize ADC
+ *
+ * \param[in] hw The pointer to hardware instance
+ * \param[in] i The number of hardware instance
+ */
+static int32_t _adc_init(void *const hw, const uint8_t i)
+{
+	uint16_t calib_reg = 0;
+	if (hw == ADC0) {
+		calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC0_FUSES_BIASREFBUF_ADDR >> ADC0_FUSES_BIASREFBUF_Pos))
+		            | ADC_CALIB_BIASR2R((*(uint32_t *)ADC0_FUSES_BIASR2R_ADDR >> ADC0_FUSES_BIASR2R_Pos))
+		            | ADC_CALIB_BIASCOMP((*(uint32_t *)ADC0_FUSES_BIASCOMP_ADDR >> ADC0_FUSES_BIASCOMP_Pos));
+	} else if (hw == ADC1) {
+		calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC1_FUSES_BIASREFBUF_ADDR >> ADC1_FUSES_BIASREFBUF_Pos))
+		            | ADC_CALIB_BIASR2R((*(uint32_t *)ADC1_FUSES_BIASR2R_ADDR >> ADC1_FUSES_BIASR2R_Pos))
+		            | ADC_CALIB_BIASCOMP((*(uint32_t *)ADC1_FUSES_BIASCOMP_ADDR >> ADC1_FUSES_BIASCOMP_Pos));
+	}
+
+	if (!hri_adc_is_syncing(hw, ADC_SYNCBUSY_SWRST)) {
+		if (hri_adc_get_CTRLA_reg(hw, ADC_CTRLA_ENABLE)) {
+			hri_adc_clear_CTRLA_ENABLE_bit(hw);
+			hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_ENABLE);
+		}
+		hri_adc_write_CTRLA_reg(hw, ADC_CTRLA_SWRST);
+	}
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+
+	hri_adc_write_CALIB_reg(hw, calib_reg);
+	hri_adc_write_CTRLB_reg(hw, _adcs[i].ctrl_b);
+	hri_adc_write_REFCTRL_reg(hw, _adcs[i].ref_ctrl);
+	hri_adc_write_EVCTRL_reg(hw, _adcs[i].ev_ctrl);
+	hri_adc_write_INPUTCTRL_reg(hw, _adcs[i].input_ctrl);
+	hri_adc_write_AVGCTRL_reg(hw, _adcs[i].avg_ctrl);
+	hri_adc_write_SAMPCTRL_reg(hw, _adcs[i].samp_ctrl);
+	hri_adc_write_WINLT_reg(hw, _adcs[i].win_lt);
+	hri_adc_write_WINUT_reg(hw, _adcs[i].win_ut);
+	hri_adc_write_GAINCORR_reg(hw, _adcs[i].gain_corr);
+	hri_adc_write_OFFSETCORR_reg(hw, _adcs[i].offset_corr);
+	hri_adc_write_DBGCTRL_reg(hw, _adcs[i].dbg_ctrl);
+	hri_adc_write_CTRLA_reg(hw, _adcs[i].ctrl_a);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief De-initialize ADC
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+static inline void _adc_deinit(void *hw)
+{
+	hri_adc_clear_CTRLA_ENABLE_bit(hw);
+	hri_adc_set_CTRLA_SWRST_bit(hw);
+}
+
+/**
+ * \brief Initialize ADC
+ */
+int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw)
+{
+	ASSERT(device);
+
+	device->hw = hw;
+
+	return _adc_init(hw, _adc_get_regs((uint32_t)hw));
+}
+
+/**
+ * \brief Initialize ADC
+ */
+int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw)
+{
+	int32_t init_status;
+
+	ASSERT(device);
+
+	init_status = _adc_init(hw, _adc_get_regs((uint32_t)hw));
+	if (init_status) {
+		return init_status;
+	}
+	device->hw = hw;
+	_adc_init_irq_param(hw, device);
+	NVIC_DisableIRQ(_adc_get_irq_num(device) + 0);
+	NVIC_ClearPendingIRQ(_adc_get_irq_num(device) + 0);
+	NVIC_EnableIRQ(_adc_get_irq_num(device) + 0);
+	NVIC_DisableIRQ(_adc_get_irq_num(device) + 1);
+	NVIC_ClearPendingIRQ(_adc_get_irq_num(device) + 1);
+	NVIC_EnableIRQ(_adc_get_irq_num(device) + 1);
+	return ERR_NONE;
+}
+
+/**
+ * \brief Initialize ADC
+ */
+int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw)
+{
+	ASSERT(device);
+
+	device->hw = hw;
+
+	return _adc_init(hw, _adc_get_regs((uint32_t)hw));
+}
+
+/**
+ * \brief De-initialize ADC
+ */
+void _adc_sync_deinit(struct _adc_sync_device *const device)
+{
+	_adc_deinit(device->hw);
+}
+
+/**
+ * \brief De-initialize ADC
+ */
+void _adc_async_deinit(struct _adc_async_device *const device)
+{
+	NVIC_DisableIRQ(_adc_get_irq_num(device));
+	NVIC_ClearPendingIRQ(_adc_get_irq_num(device));
+
+	_adc_deinit(device->hw);
+}
+
+/**
+ * \brief De-initialize ADC
+ */
+void _adc_dma_deinit(struct _adc_dma_device *const device)
+{
+	_adc_deinit(device->hw);
+}
+
+/**
+ * \brief Enable ADC
+ */
+void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Enable ADC
+ */
+void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Enable ADC
+ */
+void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable ADC
+ */
+void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable ADC
+ */
+void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable ADC
+ */
+void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Return address of ADC DMA source
+ */
+uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device)
+{
+	return (uint32_t) & (((Adc *)(device->hw))->RESULT.reg);
+}
+
+/**
+ * \brief Retrieve ADC conversion data size
+ */
+uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device)
+{
+	return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2;
+}
+
+/**
+ * \brief Retrieve ADC conversion data size
+ */
+uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device)
+{
+	return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2;
+}
+
+/**
+ * \brief Retrieve ADC conversion data size
+ */
+uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device)
+{
+	return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2;
+}
+
+/**
+ * \brief Check if conversion is done
+ */
+bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	return hri_adc_get_interrupt_RESRDY_bit(device->hw);
+}
+
+/**
+ * \brief Check if conversion is done
+ */
+bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	return hri_adc_get_interrupt_RESRDY_bit(device->hw);
+}
+
+/**
+ * \brief Check if conversion is done
+ */
+bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device)
+{
+	return hri_adc_get_interrupt_RESRDY_bit(device->hw);
+}
+
+/**
+ * \brief Make conversion
+ */
+void _adc_sync_convert(struct _adc_sync_device *const device)
+{
+	hri_adc_set_SWTRIG_START_bit(device->hw);
+}
+
+/**
+ * \brief Make conversion
+ */
+void _adc_async_convert(struct _adc_async_device *const device)
+{
+	hri_adc_set_SWTRIG_START_bit(device->hw);
+}
+
+/**
+ * \brief Make conversion
+ */
+void _adc_dma_convert(struct _adc_dma_device *const device)
+{
+	hri_adc_set_SWTRIG_START_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve the conversion result
+ */
+uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	return hri_adc_read_RESULT_reg(device->hw);
+}
+
+/**
+ * \brief Retrieve the conversion result
+ */
+uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	return hri_adc_read_RESULT_reg(device->hw);
+}
+
+/**
+ * \brief Set reference source
+ */
+void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference)
+{
+	_adc_set_reference_source(device->hw, reference);
+}
+
+/**
+ * \brief Set reference source
+ */
+void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference)
+{
+	_adc_set_reference_source(device->hw, reference);
+}
+
+/**
+ * \brief Set reference source
+ */
+void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference)
+{
+	_adc_set_reference_source(device->hw, reference);
+}
+
+/**
+ * \brief Set resolution
+ */
+void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution)
+{
+	hri_adc_write_CTRLB_RESSEL_bf(device->hw, resolution);
+}
+
+/**
+ * \brief Set resolution
+ */
+void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution)
+{
+	hri_adc_write_CTRLB_RESSEL_bf(device->hw, resolution);
+}
+
+/**
+ * \brief Set resolution
+ */
+void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution)
+{
+	hri_adc_write_CTRLB_RESSEL_bf(device->hw, resolution);
+}
+
+/**
+ * \brief Set channels input sources
+ */
+void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
+                          const adc_neg_input_t neg_input, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
+	hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
+}
+
+/**
+ * \brief Set channels input sources
+ */
+void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
+                           const adc_neg_input_t neg_input, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
+	hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
+}
+
+/**
+ * \brief Set channels input source
+ */
+void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input,
+                         const adc_neg_input_t neg_input, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
+	hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
+}
+
+/**
+ * \brief Set thresholds
+ */
+void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
+                              const adc_threshold_t up_threshold)
+{
+	hri_adc_write_WINLT_reg(device->hw, low_threshold);
+	hri_adc_write_WINUT_reg(device->hw, up_threshold);
+}
+
+/**
+ * \brief Set thresholds
+ */
+void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
+                               const adc_threshold_t up_threshold)
+{
+	hri_adc_write_WINLT_reg(device->hw, low_threshold);
+	hri_adc_write_WINUT_reg(device->hw, up_threshold);
+}
+
+/**
+ * \brief Set thresholds
+ */
+void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold,
+                             const adc_threshold_t up_threshold)
+{
+	hri_adc_write_WINLT_reg(device->hw, low_threshold);
+	hri_adc_write_WINUT_reg(device->hw, up_threshold);
+}
+
+/**
+ * \brief Set gain
+ */
+void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain)
+{
+	(void)device, (void)channel, (void)gain;
+}
+
+/**
+ * \brief Set gain
+ */
+void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain)
+{
+	(void)device, (void)channel, (void)gain;
+}
+
+/**
+ * \brief Set gain
+ */
+void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain)
+{
+	(void)device, (void)channel, (void)gain;
+}
+
+/**
+ * \brief Set conversion mode
+ */
+void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode)
+{
+	if (ADC_CONVERSION_MODE_FREERUN == mode) {
+		hri_adc_set_CTRLB_FREERUN_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLB_FREERUN_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set conversion mode
+ */
+void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode)
+{
+	if (ADC_CONVERSION_MODE_FREERUN == mode) {
+		hri_adc_set_CTRLB_FREERUN_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLB_FREERUN_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set conversion mode
+ */
+void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode)
+{
+	if (ADC_CONVERSION_MODE_FREERUN == mode) {
+		hri_adc_set_CTRLB_FREERUN_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLB_FREERUN_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set differential mode
+ */
+void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
+                                             const enum adc_differential_mode mode)
+{
+	(void)channel;
+
+	if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
+		hri_adc_set_INPUTCTRL_DIFFMODE_bit(device->hw);
+	} else {
+		hri_adc_clear_INPUTCTRL_DIFFMODE_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set differential mode
+ */
+void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
+                                              const enum adc_differential_mode mode)
+{
+	(void)channel;
+
+	if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
+		hri_adc_set_INPUTCTRL_DIFFMODE_bit(device->hw);
+	} else {
+		hri_adc_clear_INPUTCTRL_DIFFMODE_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set differential mode
+ */
+void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel,
+                                            const enum adc_differential_mode mode)
+{
+	(void)channel;
+
+	if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
+		hri_adc_set_INPUTCTRL_DIFFMODE_bit(device->hw);
+	} else {
+		hri_adc_clear_INPUTCTRL_DIFFMODE_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set window mode
+ */
+void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode)
+{
+	hri_adc_write_CTRLB_WINMODE_bf(device->hw, mode);
+}
+
+/**
+ * \brief Set window mode
+ */
+void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode)
+{
+	hri_adc_write_CTRLB_WINMODE_bf(device->hw, mode);
+}
+
+/**
+ * \brief Set window mode
+ */
+void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode)
+{
+	hri_adc_write_CTRLB_WINMODE_bf(device->hw, mode);
+}
+
+/**
+ * \brief Retrieve threshold state
+ */
+void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state)
+{
+	*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve threshold state
+ */
+void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state)
+{
+	*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve threshold state
+ */
+void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state)
+{
+	*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
+}
+
+/**
+ * \brief Enable/disable ADC channel interrupt
+ */
+void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
+                              const enum _adc_async_callback_type type, const bool state)
+{
+	(void)channel;
+
+	void *const hw = device->hw;
+
+	if (ADC_ASYNC_DEVICE_MONITOR_CB == type) {
+		hri_adc_write_INTEN_WINMON_bit(hw, state);
+	} else if (ADC_ASYNC_DEVICE_ERROR_CB == type) {
+		hri_adc_write_INTEN_OVERRUN_bit(hw, state);
+	} else if (ADC_ASYNC_DEVICE_CONVERT_CB == type) {
+		hri_adc_write_INTEN_RESRDY_bit(hw, state);
+	}
+}
+
+/**
+ * \brief Retrieve ADC sync helper functions
+ */
+void *_adc_get_adc_sync(void)
+{
+	return (void *)NULL;
+}
+
+/**
+ * \brief Retrieve ADC async helper functions
+ */
+void *_adc_get_adc_async(void)
+{
+	return (void *)NULL;
+}
+
+/**
+ * \brief Set ADC reference source
+ *
+ * \param[in] hw The pointer to hardware instance
+ * \param[in] reference The reference to set
+ */
+static void _adc_set_reference_source(void *const hw, const adc_reference_t reference)
+{
+	bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw);
+
+	hri_adc_clear_CTRLA_ENABLE_bit(hw);
+	hri_adc_write_REFCTRL_REFSEL_bf(hw, reference);
+
+	if (enabled) {
+		hri_adc_set_CTRLA_ENABLE_bit(hw);
+	}
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/adc/hpl_adc_base.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/adc/hpl_adc_base.h
new file mode 100644
index 0000000..e9b9528
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/adc/hpl_adc_base.h
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief ADC related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_ADC_ADC_H_INCLUDED
+#define _HPL_ADC_ADC_H_INCLUDED
+
+#include <hpl_adc_sync.h>
+#include <hpl_adc_async.h>
+
+/**
+ * \addtogroup HPL ADC
+ *
+ * \section hpl_adc_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name HPL functions
+ */
+//@{
+
+/**
+ * \brief Retrieve ADC helper functions
+ *
+ * \return A pointer to set of ADC helper functions
+ */
+void *_adc_get_adc_sync(void);
+void *_adc_get_adc_async(void);
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_USART_UART_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/ccl/hpl_ccl.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/ccl/hpl_ccl.c
new file mode 100644
index 0000000..732ce82
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/ccl/hpl_ccl.c
@@ -0,0 +1,97 @@
+/**
+ * \file
+ *
+ * \brief Custom Control Logic functionality implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_custom_logic.h>
+#include <hpl_ccl_config.h>
+#include <utils_repeat_macro.h>
+
+/* Configuration value for CCL LUTCTRL reg */
+#define _CCL_LUTCTRL(unused, n)                                                                                        \
+	((CONF_CCL_LUTCTRL_EN_##n << 1) | ((uint32_t)CONF_CCL_TRUTH_##n << 24) | (CONF_CCL_INSEL0_##n << 8)                \
+	 | (CONF_CCL_INSEL1_##n << 12) | (CONF_CCL_INSEL2_##n << 16) | (CONF_CCL_EDGESEL_##n << 7)                         \
+	 | (CONF_CCL_FILTSEL_##n << 4) | (CONF_CCL_LUTEO_##n << 22) | (CONF_CCL_LUTEI_##n << 21)                           \
+	 | (CONF_CCL_INVEI_##n << 20)),
+
+/* Configuration value for CCL SEQCTRL reg */
+#define _CCL_SEQCTRL(unused, n) ((CONF_CCL_SEQSEL_##n)),
+
+/* Configuration value for CCL CTRL reg */
+#define _CCL_CTRL() (CONF_CCL_RUNSTDBY << CCL_CTRL_RUNSTDBY_Pos)
+
+#define REG_SEQCTRL_NUM 2
+#define REG_LUTCTRL_NUM 4
+
+struct _ccl_regs {
+	uint32_t lutctrl[REG_LUTCTRL_NUM];
+	uint8_t  seqctrl[REG_SEQCTRL_NUM];
+	uint8_t  ctrl;
+};
+
+const struct _ccl_regs _ccl_reg_cfgs = {{REPEAT_MACRO(_CCL_LUTCTRL, unused, REG_LUTCTRL_NUM)},
+                                        {REPEAT_MACRO(_CCL_SEQCTRL, unused, REG_SEQCTRL_NUM)},
+                                        _CCL_CTRL()};
+
+int32_t _custom_logic_init(void)
+{
+	uint8_t i;
+
+	hri_ccl_write_CTRL_reg(CCL, 0);
+	hri_ccl_write_CTRL_reg(CCL, CCL_CTRL_SWRST);
+
+	for (i = 0; i < REG_SEQCTRL_NUM; i++) {
+		hri_ccl_write_SEQCTRL_reg(CCL, i, _ccl_reg_cfgs.seqctrl[i]);
+	}
+	for (i = 0; i < REG_LUTCTRL_NUM; i++) {
+		hri_ccl_write_LUTCTRL_reg(CCL, i, _ccl_reg_cfgs.lutctrl[i]);
+	}
+
+	hri_ccl_write_CTRL_reg(CCL, _ccl_reg_cfgs.ctrl);
+	return ERR_NONE;
+}
+
+void _custom_logic_deinit(void)
+{
+	hri_ccl_clear_CTRL_ENABLE_bit(CCL);
+	hri_ccl_write_CTRL_reg(CCL, CCL_CTRL_SWRST);
+}
+
+int32_t _custom_logic_enable(void)
+{
+	hri_ccl_set_CTRL_ENABLE_bit(CCL);
+	return ERR_NONE;
+}
+
+void _custom_logic_disable(void)
+{
+	hri_ccl_clear_CTRL_ENABLE_bit(CCL);
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/cmcc/hpl_cmcc.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/cmcc/hpl_cmcc.c
new file mode 100644
index 0000000..bddf0e1
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/cmcc/hpl_cmcc.c
@@ -0,0 +1,354 @@
+/**
+ * \file
+ *
+ * \brief Generic CMCC(Cortex M Cache Controller) related functionality.
+ *
+ * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".  NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <compiler.h>
+#include <hpl_cmcc.h>
+#include <hpl_cmcc_config.h>
+
+/**
+ * \brief Initialize Cache Module
+ *
+ * This function does low level cache configuration.
+ *
+ * \return initialize status
+ */
+int32_t _cmcc_init(void)
+{
+	int32_t return_value;
+
+	_cmcc_disable(CMCC);
+
+	if (_is_cache_disabled(CMCC)) {
+		hri_cmcc_write_CFG_reg(
+		    CMCC,
+		    (CMCC_CFG_CSIZESW(CONF_CMCC_CACHE_SIZE) | (CONF_CMCC_DATA_CACHE_DISABLE << CMCC_CFG_DCDIS_Pos)
+		     | (CONF_CMCC_INST_CACHE_DISABLE << CMCC_CFG_ICDIS_Pos) | (CONF_CMCC_CLK_GATING_DISABLE)));
+
+		_cmcc_enable(CMCC);
+		return_value = _is_cache_enabled(CMCC) == true ? ERR_NONE : ERR_FAILURE;
+	} else {
+		return_value = ERR_NOT_INITIALIZED;
+	}
+
+	return return_value;
+}
+
+/**
+ * \brief Configure CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] cache configuration structure pointer
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl)
+{
+	int32_t return_value;
+
+	_cmcc_disable(hw);
+
+	if (_is_cache_disabled(hw)) {
+		hri_cmcc_write_CFG_reg(
+		    hw,
+		    (CMCC_CFG_CSIZESW(cache_ctrl->cache_size) | (cache_ctrl->data_cache_disable << CMCC_CFG_DCDIS_Pos)
+		     | (cache_ctrl->inst_cache_disable << CMCC_CFG_ICDIS_Pos) | (cache_ctrl->gclk_gate_disable)));
+
+		return_value = ERR_NONE;
+	} else {
+		return_value = ERR_NOT_INITIALIZED;
+	}
+
+	return return_value;
+}
+
+/**
+ * \brief Enable data cache in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_enable_data_cache(const void *hw, bool value)
+{
+	uint32_t tmp;
+	int32_t  ret;
+
+	tmp = hri_cmcc_read_CFG_reg(hw);
+	tmp &= ~CMCC_CFG_DCDIS;
+	tmp |= ((!value) << CMCC_CFG_DCDIS_Pos);
+
+	ret = _cmcc_disable(hw);
+	hri_cmcc_write_CFG_reg(hw, tmp);
+	ret = _cmcc_enable(hw);
+
+	return ret;
+}
+
+/**
+ * \brief Enable instruction cache in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_enable_inst_cache(const void *hw, bool value)
+{
+	uint32_t tmp;
+	int32_t  ret;
+
+	tmp = hri_cmcc_read_CFG_reg(hw);
+	tmp &= ~CMCC_CFG_ICDIS;
+	tmp |= ((!value) << CMCC_CFG_ICDIS_Pos);
+
+	ret = _cmcc_disable(hw);
+	hri_cmcc_write_CFG_reg(hw, tmp);
+	ret = _cmcc_enable(hw);
+
+	return ret;
+}
+
+/**
+ * \brief Enable clock gating in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_enable_clock_gating(const void *hw, bool value)
+{
+	uint32_t tmp;
+	int32_t  ret;
+
+	tmp = hri_cmcc_read_CFG_reg(hw);
+	tmp |= value;
+
+	ret = _cmcc_disable(hw);
+	hri_cmcc_write_CFG_reg(hw, tmp);
+	ret = _cmcc_enable(hw);
+
+	return ret;
+}
+
+/**
+ * \brief Configure the cache size in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from cache size configuration enumerator
+ *				0->1K, 1->2K, 2->4K(default)
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size)
+{
+	uint32_t tmp;
+	int32_t  ret;
+
+	tmp = hri_cmcc_read_CFG_reg(hw);
+	tmp &= (~CMCC_CFG_CSIZESW_Msk);
+	tmp |= (size << CMCC_CFG_CSIZESW_Pos);
+
+	ret = _cmcc_disable(hw);
+	hri_cmcc_write_CFG_reg(hw, tmp);
+	ret = _cmcc_enable(hw);
+
+	return ret;
+}
+
+/**
+ * \brief Lock the mentioned WAY in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from "way_num_index" enumerator
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_lock_way(const void *hw, enum way_num_index num)
+{
+	uint32_t tmp;
+	int32_t  ret;
+
+	tmp = hri_cmcc_read_LCKWAY_reg(hw);
+	tmp |= CMCC_LCKWAY_LCKWAY(num);
+
+	ret = _cmcc_disable(hw);
+	hri_cmcc_write_LCKWAY_reg(hw, tmp);
+	ret = _cmcc_enable(hw);
+
+	return ret;
+}
+
+/**
+ * \brief Unlock the mentioned WAY in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from "way_num_index" enumerator
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_unlock_way(const void *hw, enum way_num_index num)
+{
+	uint32_t tmp;
+	int32_t  ret;
+
+	tmp = hri_cmcc_read_LCKWAY_reg(hw);
+	tmp &= (~CMCC_LCKWAY_LCKWAY(num));
+
+	ret = _cmcc_disable(hw);
+	hri_cmcc_write_LCKWAY_reg(hw, tmp);
+	ret = _cmcc_enable(hw);
+
+	return ret;
+}
+
+/**
+ * \brief Invalidate the mentioned cache line in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from "way_num" enumerator (valid arg is 0-3)
+ * \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num)
+{
+	int32_t return_value;
+
+	if ((way_num < CMCC_WAY_NOS) && (line_num < CMCC_LINE_NOS)) {
+		_cmcc_disable(hw);
+		while (!(_is_cache_disabled(hw)))
+			;
+		hri_cmcc_write_MAINT1_reg(hw, (CMCC_MAINT1_INDEX(line_num) | CMCC_MAINT1_WAY(way_num)));
+		return_value = ERR_NONE;
+	} else {
+		return_value = ERR_INVALID_ARG;
+	}
+
+	return return_value;
+}
+
+/**
+ * \brief Invalidate entire cache entries in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_invalidate_all(const void *hw)
+{
+	int32_t return_value;
+
+	_cmcc_disable(hw);
+	if (_is_cache_disabled(hw)) {
+		hri_cmcc_write_MAINT0_reg(hw, CMCC_MAINT0_INVALL);
+		return_value = ERR_NONE;
+	} else {
+		return_value = ERR_FAILURE;
+	}
+
+	return return_value;
+}
+
+/**
+ * \brief Configure cache monitor in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from cache monitor configurations enumerator
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg)
+{
+	hri_cmcc_write_MCFG_reg(hw, CMCC_MCFG_MODE(monitor_cfg));
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable cache monitor in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_enable_monitor(const void *hw)
+{
+	hri_cmcc_write_MEN_reg(hw, CMCC_MEN_MENABLE);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Disable cache monitor in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_disable_monitor(const void *hw)
+{
+	hri_cmcc_write_MEN_reg(hw, (CMCC_MONITOR_DISABLE << CMCC_MEN_MENABLE_Pos));
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Reset cache monitor in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_reset_monitor(const void *hw)
+{
+	hri_cmcc_write_MCTRL_reg(hw, CMCC_MCTRL_SWRST);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Get cache monitor event counter value from CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return event counter value
+ */
+uint32_t _cmcc_get_monitor_event_count(const void *hw)
+{
+	return hri_cmcc_read_MSR_reg(hw);
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/core/hpl_core_m4.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/core/hpl_core_m4.c
new file mode 100644
index 0000000..4680ec3
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/core/hpl_core_m4.c
@@ -0,0 +1,241 @@
+/**
+ * \file
+ *
+ * \brief Core related functionality implementation.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_core.h>
+#include <hpl_irq.h>
+#ifndef _UNIT_TEST_
+#include <utils.h>
+#endif
+#include <utils_assert.h>
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 1000000
+#endif
+
+#if CONF_CPU_FREQUENCY < 1000
+#define CPU_FREQ_POWER 3
+#elif CONF_CPU_FREQUENCY < 10000
+#define CPU_FREQ_POWER 4
+#elif CONF_CPU_FREQUENCY < 100000
+#define CPU_FREQ_POWER 5
+#elif CONF_CPU_FREQUENCY < 1000000
+#define CPU_FREQ_POWER 6
+#elif CONF_CPU_FREQUENCY < 10000000
+#define CPU_FREQ_POWER 7
+#elif CONF_CPU_FREQUENCY < 100000000
+#define CPU_FREQ_POWER 8
+#elif CONF_CPU_FREQUENCY < 1000000000
+#define CPU_FREQ_POWER 9
+#endif
+
+/**
+ * \brief The array of interrupt handlers
+ */
+struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn];
+
+/**
+ * \brief Reset MCU
+ */
+void _reset_mcu(void)
+{
+	NVIC_SystemReset();
+}
+
+/**
+ * \brief Put MCU to sleep
+ */
+void _go_to_sleep(void)
+{
+	__DSB();
+	__WFI();
+}
+
+/**
+ * \brief Retrieve current IRQ number
+ */
+uint8_t _irq_get_current(void)
+{
+	return (uint8_t)__get_IPSR() - 16;
+}
+
+/**
+ * \brief Disable the given IRQ
+ */
+void _irq_disable(uint8_t n)
+{
+	NVIC_DisableIRQ((IRQn_Type)n);
+}
+
+/**
+ * \brief Set the given IRQ
+ */
+void _irq_set(uint8_t n)
+{
+	NVIC_SetPendingIRQ((IRQn_Type)n);
+}
+
+/**
+ * \brief Clear the given IRQ
+ */
+void _irq_clear(uint8_t n)
+{
+	NVIC_ClearPendingIRQ((IRQn_Type)n);
+}
+
+/**
+ * \brief Enable the given IRQ
+ */
+void _irq_enable(uint8_t n)
+{
+	NVIC_EnableIRQ((IRQn_Type)n);
+}
+
+/**
+ * \brief Register IRQ handler
+ */
+void _irq_register(const uint8_t n, struct _irq_descriptor *const irq)
+{
+	ASSERT(n < PERIPH_COUNT_IRQn);
+
+	_irq_table[n] = irq;
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Default_Handler(void)
+{
+	while (1) {
+	}
+}
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of us
+ */
+static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power)
+{
+	switch (power) {
+	case 9:
+		return (us * (freq / 1000000) + 2) / 3;
+	case 8:
+		return (us * (freq / 100000) + 29) / 30;
+	case 7:
+		return (us * (freq / 10000) + 299) / 300;
+	case 6:
+		return (us * (freq / 1000) + 2999) / 3000;
+	case 5:
+		return (us * (freq / 100) + 29999) / 30000;
+	case 4:
+		return (us * (freq / 10) + 299999) / 300000;
+	default:
+		return (us * freq + 2999999) / 3000000;
+	}
+}
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of us
+ */
+uint32_t _get_cycles_for_us(const uint16_t us)
+{
+	return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER);
+}
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of ms
+ */
+static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power)
+{
+	switch (power) {
+	case 9:
+		return (ms * (freq / 1000000) + 2) / 3 * 1000;
+	case 8:
+		return (ms * (freq / 100000) + 2) / 3 * 100;
+	case 7:
+		return (ms * (freq / 10000) + 2) / 3 * 10;
+	case 6:
+		return (ms * (freq / 1000) + 2) / 3;
+	case 5:
+		return (ms * (freq / 100) + 29) / 30;
+	case 4:
+		return (ms * (freq / 10) + 299) / 300;
+	default:
+		return (ms * (freq / 1) + 2999) / 3000;
+	}
+}
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of ms
+ */
+uint32_t _get_cycles_for_ms(const uint16_t ms)
+{
+	return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER);
+}
+/**
+ * \brief Initialize delay functionality
+ */
+void _delay_init(void *const hw)
+{
+	(void)hw;
+}
+/**
+ * \brief Delay loop to delay n number of cycles
+ */
+void _delay_cycles(void *const hw, uint32_t cycles)
+{
+#ifndef _UNIT_TEST_
+	(void)hw;
+	(void)cycles;
+#if defined(__GNUC__) && (__ARMCOMPILER_VERSION > 6000000) /*  Keil MDK with ARM Compiler 6 */
+	__asm(".align 3 \n"
+	      "__delay:\n"
+	      "subs r1, r1, #1\n"
+	      "bhi __delay\n");
+#elif defined __GNUC__
+	__asm(".syntax unified\n"
+	      ".align 3 \n"
+	      "__delay:\n"
+	      "subs r1, r1, #1\n"
+	      "bhi __delay\n"
+	      ".syntax divided");
+#elif defined __CC_ARM
+	__asm("__delay:\n"
+	      "subs cycles, cycles, #1\n"
+	      "bhi __delay\n");
+#elif defined __ICCARM__
+	__asm("__delay:\n"
+	      "subs r1, r1, #1\n"
+	      "bhi.n __delay\n");
+#endif
+#endif
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/core/hpl_core_port.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/core/hpl_core_port.h
new file mode 100644
index 0000000..3f3e8f2
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/core/hpl_core_port.h
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Core related functionality implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_CORE_PORT_H_INCLUDED
+#define _HPL_CORE_PORT_H_INCLUDED
+
+#include <peripheral_clk_config.h>
+
+/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR
+ * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h),
+ * there will be assembling errors.
+ * So the following things are not included for assembling.
+ */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+
+#ifndef _UNIT_TEST_
+#include <compiler.h>
+#endif
+
+/**
+ * \brief Check if it's in ISR handling
+ * \return \c true if it's in ISR
+ */
+static inline bool _is_in_isr(void)
+{
+	return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk);
+}
+
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _HPL_CORE_PORT_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/core/hpl_init.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/core/hpl_init.c
new file mode 100644
index 0000000..3ba6bf3
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/core/hpl_init.c
@@ -0,0 +1,80 @@
+/**
+ * \file
+ *
+ * \brief HPL initialization related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_gpio.h>
+#include <hpl_init.h>
+#include <hpl_gclk_base.h>
+#include <hpl_mclk_config.h>
+
+#include <hpl_dma.h>
+#include <hpl_dmac_config.h>
+#include <hpl_cmcc_config.h>
+#include <hal_cache.h>
+
+/* Referenced GCLKs (out of 0~11), should be initialized firstly
+ * - GCLK 2 for DFLL
+ * - GCLK 1 for FDPLL1
+ */
+#define _GCLK_INIT_1ST 0x00000006
+/* Not referenced GCLKs, initialized last */
+#define _GCLK_INIT_LAST 0x00000FF9
+
+/**
+ * \brief Initialize the hardware abstraction layer
+ */
+void _init_chip(void)
+{
+	hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
+
+	_osc32kctrl_init_sources();
+	_oscctrl_init_sources();
+	_mclk_init();
+#if _GCLK_INIT_1ST
+	_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
+#endif
+	_oscctrl_init_referenced_generators();
+	_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
+
+#if CONF_DMAC_ENABLE
+	hri_mclk_set_AHBMASK_DMAC_bit(MCLK);
+	_dma_init();
+#endif
+
+#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3)
+	_port_event_init();
+#endif
+
+#if CONF_CMCC_ENABLE
+	cache_init();
+#endif
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/dmac/hpl_dmac.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/dmac/hpl_dmac.c
new file mode 100644
index 0000000..7dddc9d
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/dmac/hpl_dmac.c
@@ -0,0 +1,260 @@
+
+/**
+ * \file
+ *
+ * \brief Generic DMAC related functionality.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <hpl_dma.h>
+#include <utils_assert.h>
+#include <utils.h>
+#include <hpl_dmac_config.h>
+#include <utils_repeat_macro.h>
+
+/* Section containing first descriptors for all DMAC channels */
+COMPILER_ALIGNED(16)
+DmacDescriptor _descriptor_section[DMAC_CH_NUM];
+
+/* Section containing current descriptors for all DMAC channels */
+COMPILER_ALIGNED(16)
+DmacDescriptor _write_back_section[DMAC_CH_NUM];
+
+/* Array containing callbacks for DMAC channels */
+static struct _dma_resource _resources[DMAC_CH_NUM];
+
+/* DMAC interrupt handler */
+static void _dmac_handler(void);
+
+/* This macro DMAC configuration */
+#define DMAC_CHANNEL_CFG(i, n)                                                                                         \
+	{(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | DMAC_CHCTRLA_TRIGACT(CONF_DMAC_TRIGACT_##n)               \
+	     | DMAC_CHCTRLA_TRIGSRC(CONF_DMAC_TRIGSRC_##n),                                                                \
+	 DMAC_CHPRILVL_PRILVL(CONF_DMAC_LVL_##n),                                                                          \
+	 (CONF_DMAC_EVIE_##n << DMAC_CHEVCTRL_EVIE_Pos) | (CONF_DMAC_EVOE_##n << DMAC_CHEVCTRL_EVOE_Pos)                   \
+	     | (CONF_DMAC_EVACT_##n << DMAC_CHEVCTRL_EVACT_Pos),                                                           \
+	 DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos)                 \
+	     | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos)         \
+	     | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n)                 \
+	     | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)},
+
+/* DMAC channel configuration */
+struct dmac_channel_cfg {
+	uint32_t ctrla;
+	uint8_t  prilvl;
+	uint8_t  evctrl;
+	uint16_t btctrl;
+};
+
+/* DMAC channel configurations */
+const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)};
+
+/**
+ * \brief Initialize DMAC
+ */
+int32_t _dma_init(void)
+{
+	uint8_t i;
+
+	hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC);
+	hri_dmac_clear_CRCCTRL_reg(DMAC, DMAC_CRCCTRL_CRCSRC_Msk);
+	hri_dmac_set_CTRL_SWRST_bit(DMAC);
+	while (hri_dmac_get_CTRL_SWRST_bit(DMAC))
+		;
+
+	hri_dmac_write_CTRL_reg(DMAC,
+	                        (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos)
+	                            | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos)
+	                            | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos));
+	hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN);
+
+	hri_dmac_write_PRICTRL0_reg(
+	    DMAC,
+	    DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1)
+	        | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3)
+	        | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos)
+	        | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos));
+	hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section);
+	hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section);
+
+	for (i = 0; i < DMAC_CH_NUM; i++) {
+		hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla);
+		hri_dmac_write_CHPRILVL_reg(DMAC, i, _cfgs[i].prilvl);
+		hri_dmac_write_CHEVCTRL_reg(DMAC, i, _cfgs[i].evctrl);
+		hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl);
+		hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0);
+	}
+
+	for (i = 0; i < 5; i++) {
+		NVIC_DisableIRQ(DMAC_0_IRQn + i);
+		NVIC_ClearPendingIRQ(DMAC_0_IRQn + i);
+		NVIC_EnableIRQ(DMAC_0_IRQn + i);
+	}
+
+	hri_dmac_set_CTRL_DMAENABLE_bit(DMAC);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable/disable DMA interrupt
+ */
+void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state)
+{
+	if (DMA_TRANSFER_COMPLETE_CB == type) {
+		hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, channel, state);
+	} else if (DMA_TRANSFER_ERROR_CB == type) {
+		hri_dmac_write_CHINTEN_TERR_bit(DMAC, channel, state);
+	}
+}
+
+int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst)
+{
+	hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst);
+
+	return ERR_NONE;
+}
+
+int32_t _dma_set_source_address(const uint8_t channel, const void *const src)
+{
+	hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src);
+
+	return ERR_NONE;
+}
+
+int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel)
+{
+	hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel],
+	                                      (uint32_t)&_descriptor_section[next_channel]);
+
+	return ERR_NONE;
+}
+
+int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable)
+{
+	hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable);
+
+	return ERR_NONE;
+}
+
+int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount)
+{
+	uint32_t address   = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]);
+	uint8_t  beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]);
+
+	if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) {
+		hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size));
+	}
+
+	address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]);
+
+	if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) {
+		hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size));
+	}
+
+	hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount);
+
+	return ERR_NONE;
+}
+
+int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger)
+{
+	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]);
+	hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel);
+
+	if (software_trigger) {
+		hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel);
+	}
+
+	return ERR_NONE;
+}
+
+int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel)
+{
+	*resource = &_resources[channel];
+
+	return ERR_NONE;
+}
+
+int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable)
+{
+	hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable);
+
+	return ERR_NONE;
+}
+/**
+ * \internal DMAC interrupt handler
+ */
+static void _dmac_handler(void)
+{
+	uint8_t               channel      = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk);
+	struct _dma_resource *tmp_resource = &_resources[channel];
+
+	if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) {
+		hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel);
+		tmp_resource->dma_cb.error(tmp_resource);
+	} else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)) {
+		hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel);
+		tmp_resource->dma_cb.transfer_done(tmp_resource);
+	}
+}
+/**
+ * \brief DMAC interrupt handler
+ */
+void DMAC_0_Handler(void)
+{
+	_dmac_handler();
+}
+/**
+ * \brief DMAC interrupt handler
+ */
+void DMAC_1_Handler(void)
+{
+	_dmac_handler();
+}
+/**
+ * \brief DMAC interrupt handler
+ */
+void DMAC_2_Handler(void)
+{
+	_dmac_handler();
+}
+/**
+ * \brief DMAC interrupt handler
+ */
+void DMAC_3_Handler(void)
+{
+	_dmac_handler();
+}
+/**
+ * \brief DMAC interrupt handler
+ */
+void DMAC_4_Handler(void)
+{
+	_dmac_handler();
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/doc_lite/tc.rst b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/doc_lite/tc.rst
new file mode 100644
index 0000000..833bb67
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/doc_lite/tc.rst
@@ -0,0 +1,39 @@
+=========
+TC driver
+=========
+The TC consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events, or it can be configured to count clock pulses. The counter, together with the compare/capture channels, can be configured to timestamp input events, allowing capture of frequency and pulse width. It can also perform waveform generation, such as frequency generation and pulse-width modulation (PWM) 
+
+The timer/counter is clocked by the peripheral clock with optional prescaling or from the event system.
+
+Features
+--------
+* Initialization
+
+Applications
+------------
+* Frequency Generation
+* Single-slope PWM (pulse width modulation)
+* Dual-slope PWM
+* Count on event
+* Quadrature decoding
+
+Dependencies
+------------
+* CLK for clock
+* CPUINT/PMIC for Interrupt
+* EVSYS for events
+* UPDI/PDI/JTAG for debug
+* PORT for Waveform Generation
+
+Concurrency
+-----------
+N/A
+
+Limitations
+-----------
+N/A
+
+Knows issues and workarounds
+----------------------------
+N/A
+
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/eic/hpl_eic.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/eic/hpl_eic.c
new file mode 100644
index 0000000..459bf16
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/eic/hpl_eic.c
@@ -0,0 +1,299 @@
+
+/**
+ * \file
+ *
+ * \brief EIC related functionality implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <compiler.h>
+#include <hpl_eic_config.h>
+#include <hpl_ext_irq.h>
+#include <string.h>
+#include <utils.h>
+#include <utils_assert.h>
+
+#ifdef __MINGW32__
+#define ffs __builtin_ffs
+#endif
+#if defined(__CC_ARM) || defined(__ICCARM__)
+/* Find the first bit set */
+static int ffs(int v)
+{
+	int i, bit = 1;
+	for (i = 0; i < sizeof(int) * 8; i++) {
+		if (v & bit) {
+			return i + 1;
+		}
+		bit <<= 1;
+	}
+	return 0;
+}
+#endif
+
+/**
+ * \brief Invalid external interrupt and pin numbers
+ */
+#define INVALID_EXTINT_NUMBER 0xFF
+#define INVALID_PIN_NUMBER 0xFFFFFFFF
+
+#ifndef CONFIG_EIC_EXTINT_MAP
+/** Dummy mapping to pass compiling. */
+#define CONFIG_EIC_EXTINT_MAP                                                                                          \
+	{                                                                                                                  \
+		INVALID_EXTINT_NUMBER, INVALID_PIN_NUMBER                                                                      \
+	}
+#endif
+
+#define EXT_IRQ_AMOUNT 4
+
+/**
+ * \brief EXTINTx and pin number map
+ */
+struct _eic_map {
+	uint8_t  extint;
+	uint32_t pin;
+};
+
+/**
+ * \brief PIN and EXTINT map for enabled external interrupts
+ */
+static const struct _eic_map _map[] = {CONFIG_EIC_EXTINT_MAP};
+
+/**
+ * \brief The callback to upper layer's interrupt processing routine
+ */
+static void (*callback)(const uint32_t pin);
+
+static void _ext_irq_handler(void);
+
+/**
+ * \brief Initialize external interrupt module
+ */
+int32_t _ext_irq_init(void (*cb)(const uint32_t pin))
+{
+	if (!hri_eic_is_syncing(EIC, EIC_SYNCBUSY_SWRST)) {
+		if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) {
+			hri_eic_clear_CTRLA_ENABLE_bit(EIC);
+			hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_ENABLE);
+		}
+		hri_eic_write_CTRLA_reg(EIC, EIC_CTRLA_SWRST);
+	}
+	hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_SWRST);
+
+	hri_eic_write_CTRLA_CKSEL_bit(EIC, CONF_EIC_CKSEL);
+
+	hri_eic_write_NMICTRL_reg(EIC,
+	                          (CONF_EIC_NMIFILTEN << EIC_NMICTRL_NMIFILTEN_Pos)
+	                              | EIC_NMICTRL_NMISENSE(CONF_EIC_NMISENSE) | EIC_ASYNCH_ASYNCH(CONF_EIC_NMIASYNCH)
+	                              | 0);
+
+	hri_eic_write_EVCTRL_reg(EIC,
+	                         (CONF_EIC_EXTINTEO0 << 0) | (CONF_EIC_EXTINTEO1 << 1) | (CONF_EIC_EXTINTEO2 << 2)
+	                             | (CONF_EIC_EXTINTEO3 << 3) | (CONF_EIC_EXTINTEO4 << 4) | (CONF_EIC_EXTINTEO5 << 5)
+	                             | (CONF_EIC_EXTINTEO6 << 6) | (CONF_EIC_EXTINTEO7 << 7) | (CONF_EIC_EXTINTEO8 << 8)
+	                             | (CONF_EIC_EXTINTEO9 << 9) | (CONF_EIC_EXTINTEO10 << 10) | (CONF_EIC_EXTINTEO11 << 11)
+	                             | (CONF_EIC_EXTINTEO12 << 12) | (CONF_EIC_EXTINTEO13 << 13)
+	                             | (CONF_EIC_EXTINTEO14 << 14) | (CONF_EIC_EXTINTEO15 << 15) | 0);
+	hri_eic_write_ASYNCH_reg(EIC,
+	                         (CONF_EIC_ASYNCH0 << 0) | (CONF_EIC_ASYNCH1 << 1) | (CONF_EIC_ASYNCH2 << 2)
+	                             | (CONF_EIC_ASYNCH3 << 3) | (CONF_EIC_ASYNCH4 << 4) | (CONF_EIC_ASYNCH5 << 5)
+	                             | (CONF_EIC_ASYNCH6 << 6) | (CONF_EIC_ASYNCH7 << 7) | (CONF_EIC_ASYNCH8 << 8)
+	                             | (CONF_EIC_ASYNCH9 << 9) | (CONF_EIC_ASYNCH10 << 10) | (CONF_EIC_ASYNCH11 << 11)
+	                             | (CONF_EIC_ASYNCH12 << 12) | (CONF_EIC_ASYNCH13 << 13) | (CONF_EIC_ASYNCH14 << 14)
+	                             | (CONF_EIC_ASYNCH15 << 15) | 0);
+	hri_eic_write_DEBOUNCEN_reg(
+	    EIC,
+	    (CONF_EIC_DEBOUNCE_ENABLE0 << 0) | (CONF_EIC_DEBOUNCE_ENABLE1 << 1) | (CONF_EIC_DEBOUNCE_ENABLE2 << 2)
+	        | (CONF_EIC_DEBOUNCE_ENABLE3 << 3) | (CONF_EIC_DEBOUNCE_ENABLE4 << 4) | (CONF_EIC_DEBOUNCE_ENABLE5 << 5)
+	        | (CONF_EIC_DEBOUNCE_ENABLE6 << 6) | (CONF_EIC_DEBOUNCE_ENABLE7 << 7) | (CONF_EIC_DEBOUNCE_ENABLE8 << 8)
+	        | (CONF_EIC_DEBOUNCE_ENABLE9 << 9) | (CONF_EIC_DEBOUNCE_ENABLE10 << 10) | (CONF_EIC_DEBOUNCE_ENABLE11 << 11)
+	        | (CONF_EIC_DEBOUNCE_ENABLE12 << 12) | (CONF_EIC_DEBOUNCE_ENABLE13 << 13)
+	        | (CONF_EIC_DEBOUNCE_ENABLE14 << 14) | (CONF_EIC_DEBOUNCE_ENABLE15 << 15) | 0);
+
+	hri_eic_write_DPRESCALER_reg(
+	    EIC,
+	    (EIC_DPRESCALER_PRESCALER0(CONF_EIC_DPRESCALER0)) | (CONF_EIC_STATES0 << EIC_DPRESCALER_STATES0_Pos)
+	        | (EIC_DPRESCALER_PRESCALER1(CONF_EIC_DPRESCALER1)) | (CONF_EIC_STATES1 << EIC_DPRESCALER_STATES1_Pos)
+	        | CONF_EIC_TICKON << EIC_DPRESCALER_TICKON_Pos | 0);
+
+	hri_eic_write_CONFIG_reg(EIC,
+	                         0,
+	                         (CONF_EIC_FILTEN0 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE0)
+	                             | (CONF_EIC_FILTEN1 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE1)
+	                             | (CONF_EIC_FILTEN2 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE2)
+	                             | (CONF_EIC_FILTEN3 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE3)
+	                             | (CONF_EIC_FILTEN4 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE4)
+	                             | (CONF_EIC_FILTEN5 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE5)
+	                             | (CONF_EIC_FILTEN6 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE6)
+	                             | (CONF_EIC_FILTEN7 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE7)
+	                             | 0);
+
+	hri_eic_write_CONFIG_reg(EIC,
+	                         1,
+	                         (CONF_EIC_FILTEN8 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE8)
+	                             | (CONF_EIC_FILTEN9 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE9)
+	                             | (CONF_EIC_FILTEN10 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE10)
+	                             | (CONF_EIC_FILTEN11 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE11)
+	                             | (CONF_EIC_FILTEN12 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE12)
+	                             | (CONF_EIC_FILTEN13 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE13)
+	                             | (CONF_EIC_FILTEN14 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE14)
+	                             | (CONF_EIC_FILTEN15 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE15)
+	                             | 0);
+
+	hri_eic_set_CTRLA_ENABLE_bit(EIC);
+	NVIC_DisableIRQ(EIC_2_IRQn);
+	NVIC_ClearPendingIRQ(EIC_2_IRQn);
+	NVIC_EnableIRQ(EIC_2_IRQn);
+	NVIC_DisableIRQ(EIC_7_IRQn);
+	NVIC_ClearPendingIRQ(EIC_7_IRQn);
+	NVIC_EnableIRQ(EIC_7_IRQn);
+	NVIC_DisableIRQ(EIC_14_IRQn);
+	NVIC_ClearPendingIRQ(EIC_14_IRQn);
+	NVIC_EnableIRQ(EIC_14_IRQn);
+	NVIC_DisableIRQ(EIC_15_IRQn);
+	NVIC_ClearPendingIRQ(EIC_15_IRQn);
+	NVIC_EnableIRQ(EIC_15_IRQn);
+
+	callback = cb;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief De-initialize external interrupt module
+ */
+int32_t _ext_irq_deinit(void)
+{
+	NVIC_DisableIRQ(EIC_2_IRQn);
+	NVIC_DisableIRQ(EIC_7_IRQn);
+	NVIC_DisableIRQ(EIC_14_IRQn);
+	NVIC_DisableIRQ(EIC_15_IRQn);
+	callback = NULL;
+
+	hri_eic_clear_CTRLA_ENABLE_bit(EIC);
+	hri_eic_set_CTRLA_SWRST_bit(EIC);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable / disable external irq
+ */
+int32_t _ext_irq_enable(const uint32_t pin, const bool enable)
+{
+	uint8_t extint = INVALID_EXTINT_NUMBER;
+	uint8_t i      = 0;
+
+	for (; i < ARRAY_SIZE(_map); i++) {
+		if (_map[i].pin == pin) {
+			extint = _map[i].extint;
+			break;
+		}
+	}
+	if (INVALID_EXTINT_NUMBER == extint) {
+		return -1;
+	}
+
+	if (enable) {
+		hri_eic_set_INTEN_reg(EIC, 1ul << extint);
+	} else {
+		hri_eic_clear_INTEN_reg(EIC, 1ul << extint);
+		hri_eic_clear_INTFLAG_reg(EIC, 1ul << extint);
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Inter EIC interrupt handler
+ */
+static void _ext_irq_handler(void)
+{
+	volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC);
+	int8_t            pos;
+	uint32_t          pin = INVALID_PIN_NUMBER;
+
+	hri_eic_clear_INTFLAG_reg(EIC, flags);
+
+	ASSERT(callback);
+
+	while (flags) {
+		pos = ffs(flags) - 1;
+		while (-1 != pos) {
+			uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT;
+
+			while (upper >= lower) {
+				middle = (upper + lower) >> 1;
+				if (_map[middle].extint == pos) {
+					pin = _map[middle].pin;
+					break;
+				}
+				if (_map[middle].extint < pos) {
+					lower = middle + 1;
+				} else {
+					upper = middle - 1;
+				}
+			}
+
+			if (INVALID_PIN_NUMBER != pin) {
+				callback(pin);
+			}
+			flags &= ~(1ul << pos);
+			pos = ffs(flags) - 1;
+		}
+		flags = hri_eic_read_INTFLAG_reg(EIC);
+		hri_eic_clear_INTFLAG_reg(EIC, flags);
+	}
+}
+
+/**
+ * \brief EIC interrupt handler
+ */
+void EIC_2_Handler(void)
+{
+	_ext_irq_handler();
+} /**
+   * \brief EIC interrupt handler
+   */
+void EIC_7_Handler(void)
+{
+	_ext_irq_handler();
+} /**
+   * \brief EIC interrupt handler
+   */
+void EIC_14_Handler(void)
+{
+	_ext_irq_handler();
+} /**
+   * \brief EIC interrupt handler
+   */
+void EIC_15_Handler(void)
+{
+	_ext_irq_handler();
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/evsys/hpl_evsys.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/evsys/hpl_evsys.c
new file mode 100644
index 0000000..da0847a
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/evsys/hpl_evsys.c
@@ -0,0 +1,140 @@
+
+/**
+ * \file
+ *
+ * \brief EVSYS related functionality implementation.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_evsys_config.h>
+#include <hpl_init.h>
+#include <utils_repeat_macro.h>
+#include <err_codes.h>
+
+/* Stub macros for reserved channel */
+#define CONF_CHANNEL_38 0
+#define CONF_ONDEMAND_38 0
+#define CONF_RUNSTDBY_38 0
+#define CONF_EDGSEL_38 0
+#define CONF_PATH_38 0
+#define CONF_EVGEN_38 0
+
+#define CONF_CHANNEL_39 0
+#define CONF_ONDEMAND_39 0
+#define CONF_RUNSTDBY_39 0
+#define CONF_EDGSEL_39 0
+#define CONF_PATH_39 0
+#define CONF_EVGEN_39 0
+
+#define CONF_CHANNEL_113 0
+#define CONF_ONDEMAND_113 0
+#define CONF_RUNSTDBY_113 0
+#define CONF_EDGSEL_113 0
+#define CONF_PATH_113 0
+#define CONF_EVGEN_113 0
+
+/* Event user configuration */
+#define USER_MUX_CONF(i, n) EVSYS_USER_CHANNEL(CONF_CHANNEL_##n),
+
+/* This macro is used for repeat macro: i - unused, n - amount of channels.
+ * It contains channel configuration. */
+#define CHANNEL_CONF(i, n)                                                                                             \
+	(CONF_ONDEMAND_##n << EVSYS_CHANNEL_ONDEMAND_Pos) | (CONF_RUNSTDBY_##n << EVSYS_CHANNEL_RUNSTDBY_Pos)              \
+	    | EVSYS_CHANNEL_EDGSEL(CONF_EDGSEL_##n) | EVSYS_CHANNEL_PATH(CONF_PATH_##n)                                    \
+	    | EVSYS_CHANNEL_EVGEN(CONF_EVGEN_##n),
+
+/* This macro is used for repeat macro: i - unused, n - amount of channels
+ * It contains interrupts configuration. */
+#define INT_CFG(i, n) (CONF_OVR_##n << EVSYS_CHINTFLAG_OVR_Pos) | (CONF_EVD_##n << EVSYS_CHINTFLAG_EVD_Pos),
+
+static const uint8_t user_mux_confs[] = {REPEAT_MACRO(USER_MUX_CONF, i, EVSYS_USERS)};
+
+static const uint16_t channel_confs[] = {REPEAT_MACRO(CHANNEL_CONF, i, EVSYS_CHANNELS)};
+
+static const uint32_t interrupt_cfg[] = {REPEAT_MACRO(INT_CFG, i, EVSYS_CHANNELS)};
+
+/**
+ * \brief Initialize event system
+ */
+int32_t _event_system_init(void)
+{
+	uint8_t i;
+	/* configure user multiplexers */
+	for (i = 0; i < EVSYS_USERS; i++) {
+		hri_evsys_write_USER_reg(EVSYS, i, user_mux_confs[i]);
+	}
+
+	/* configure channels */
+	for (i = 0; i < EVSYS_CHANNELS; i++) {
+		hri_evsys_write_CHANNEL_reg(EVSYS, i, channel_confs[i]);
+		hri_evsys_write_CHINTEN_reg(EVSYS, i, interrupt_cfg[i]);
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief De-initialize event system.
+ */
+int32_t _event_system_deinit()
+{
+	hri_evsys_write_CTRLA_reg(EVSYS, EVSYS_CTRLA_SWRST);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable/disable event reception by the given user from the given
+ *        channel
+ */
+int32_t _event_system_enable_user(const uint16_t user, const uint16_t channel, const bool on)
+{
+	if (on) {
+		hri_evsys_write_USER_reg(EVSYS, user, channel);
+	} else {
+		hri_evsys_write_USER_reg(EVSYS, user, 0);
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable/disable event generation by the given generator for the given
+ *        channel
+ */
+int32_t _event_system_enable_generator(const uint16_t generator, const uint16_t channel, const bool on)
+{
+	if (on) {
+		hri_evsys_write_CHANNEL_EVGEN_bf(EVSYS, channel, generator);
+	} else {
+		hri_evsys_write_CHANNEL_EVGEN_bf(EVSYS, channel, 0);
+	}
+
+	return ERR_NONE;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/gclk/hpl_gclk.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/gclk/hpl_gclk.c
new file mode 100644
index 0000000..211ccc3
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/gclk/hpl_gclk.c
@@ -0,0 +1,312 @@
+
+/**
+ * \file
+ *
+ * \brief Generic Clock Controller related functionality.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_gclk_config.h>
+#include <hpl_init.h>
+#include <utils_assert.h>
+
+/**
+ * \brief Initializes generators
+ */
+void _gclk_init_generators(void)
+{
+
+#if CONF_GCLK_GENERATOR_0_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    0,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_1_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    1,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_2_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    2,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_3_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    3,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_4_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    4,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_5_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    5,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_6_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    6,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_7_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    7,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_8_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    8,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_9_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    9,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_10_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    10,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_11_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    11,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE);
+#endif
+}
+
+void _gclk_init_generators_by_fref(uint32_t bm)
+{
+
+#if CONF_GCLK_GENERATOR_0_CONFIG == 1
+	if (bm & (1ul << 0)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    0,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_1_CONFIG == 1
+	if (bm & (1ul << 1)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    1,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_2_CONFIG == 1
+	if (bm & (1ul << 2)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    2,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_3_CONFIG == 1
+	if (bm & (1ul << 3)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    3,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_4_CONFIG == 1
+	if (bm & (1ul << 4)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    4,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_5_CONFIG == 1
+	if (bm & (1ul << 5)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    5,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_6_CONFIG == 1
+	if (bm & (1ul << 6)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    6,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_7_CONFIG == 1
+	if (bm & (1ul << 7)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    7,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_8_CONFIG == 1
+	if (bm & (1ul << 8)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    8,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_9_CONFIG == 1
+	if (bm & (1ul << 9)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    9,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_10_CONFIG == 1
+	if (bm & (1ul << 10)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    10,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_11_CONFIG == 1
+	if (bm & (1ul << 11)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    11,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE);
+	}
+#endif
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/gclk/hpl_gclk_base.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/gclk/hpl_gclk_base.h
new file mode 100644
index 0000000..3e7d282
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/gclk/hpl_gclk_base.h
@@ -0,0 +1,87 @@
+/**
+ * \file
+ *
+ * \brief Generic Clock Controller.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_GCLK_H_INCLUDED
+#define _HPL_GCLK_H_INCLUDED
+
+#include <compiler.h>
+#ifdef _UNIT_TEST_
+#include <hri_gclk1_v210_mock.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup gclk_group GCLK Hardware Proxy Layer
+ *
+ * \section gclk_hpl_rev Revision History
+ * - v0.0.0.1 Initial Commit
+ *
+ *@{
+ */
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Enable clock on the given channel with the given clock source
+ *
+ * This function maps the given clock source to the given clock channel
+ * and enables channel.
+ *
+ * \param[in] channel The channel to enable clock for
+ * \param[in] source The clock source for the given channel
+ */
+static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source)
+{
+
+	hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN);
+}
+
+/**
+ * \brief Initialize GCLK generators by function references
+ * \param[in] bm Bit mapping for referenced generators,
+ *               a bit 1 in position triggers generator initialization.
+ */
+void _gclk_init_generators_by_fref(uint32_t bm);
+
+//@}
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_GCLK_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/mclk/hpl_mclk.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/mclk/hpl_mclk.c
new file mode 100644
index 0000000..6684320
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/mclk/hpl_mclk.c
@@ -0,0 +1,44 @@
+/**
+ * \file
+ *
+ * \brief SAM Main Clock.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <compiler.h>
+#include <hpl_mclk_config.h>
+
+/**
+ * \brief Initialize master clock generator
+ */
+void _mclk_init(void)
+{
+	void *hw = (void *)MCLK;
+	hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV));
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/osc32kctrl/hpl_osc32kctrl.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/osc32kctrl/hpl_osc32kctrl.c
new file mode 100644
index 0000000..8859b42
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/osc32kctrl/hpl_osc32kctrl.c
@@ -0,0 +1,82 @@
+
+/**
+ * \file
+ *
+ * \brief SAM 32k Oscillators Controller.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <hpl_init.h>
+#include <hpl_osc32kctrl_config.h>
+
+/**
+ * \brief Initialize 32 kHz clock sources
+ */
+void _osc32kctrl_init_sources(void)
+{
+	void *   hw    = (void *)OSC32KCTRL;
+	uint16_t calib = 0;
+
+#if CONF_XOSC32K_CONFIG == 1
+	hri_osc32kctrl_write_XOSC32K_reg(
+	    hw,
+	    OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
+	        | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
+	        | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos)
+	        | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) |
+#ifdef CONF_XOSC32K_CGM
+	        OSC32KCTRL_XOSC32K_CGM(CONF_XOSC32K_CGM) |
+#endif
+	        (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos));
+
+	hri_osc32kctrl_write_CFDCTRL_reg(hw, (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos));
+
+	hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos));
+#endif
+
+#if CONF_OSCULP32K_CONFIG == 1
+	calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
+	hri_osc32kctrl_write_OSCULP32K_reg(hw,
+#if CONF_OSCULP32K_CALIB_ENABLE == 1
+	                                   OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB)
+#else
+	                                   OSC32KCTRL_OSCULP32K_CALIB(calib)
+#endif
+	);
+#endif
+
+#if CONF_XOSC32K_CONFIG
+#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0
+	while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw))
+		;
+#endif
+#endif
+
+	hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
+	(void)calib;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/oscctrl/hpl_oscctrl.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/oscctrl/hpl_oscctrl.c
new file mode 100644
index 0000000..9f55076
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/oscctrl/hpl_oscctrl.c
@@ -0,0 +1,230 @@
+
+/**
+ * \file
+ *
+ * \brief SAM Oscillators Controller.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_init.h>
+#include <hpl_oscctrl_config.h>
+#include <hpl_gclk_config.h>
+
+/**
+ * \brief Initialize clock sources
+ */
+void _oscctrl_init_sources(void)
+{
+	void *hw = (void *)OSCCTRL;
+
+#if CONF_XOSC0_CONFIG == 1
+	hri_oscctrl_write_XOSCCTRL_reg(
+	    hw,
+	    0,
+	    OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC0_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC0_STARTUP)
+	        | (CONF_XOSC0_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC0_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos)
+	        | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC0_IMULT)
+	        | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC0_IPTAT) | (CONF_XOSC0_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)
+	        | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC0_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
+	        | (CONF_XOSC0_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC0_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos));
+#endif
+
+#if CONF_XOSC0_CONFIG == 1
+#if CONF_XOSC0_ENABLE == 1
+	while (!hri_oscctrl_get_STATUS_XOSCRDY0_bit(hw))
+		;
+#endif
+#if CONF_XOSC0_ENALC == 1
+	hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 0);
+#endif
+#if CONF_XOSC0_ONDEMAND == 1
+	hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 0);
+#endif
+#endif
+
+#if CONF_XOSC1_CONFIG == 1
+	hri_oscctrl_write_XOSCCTRL_reg(
+	    hw,
+	    1,
+	    OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC1_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC1_STARTUP)
+	        | (CONF_XOSC1_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC1_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos)
+	        | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC1_IMULT)
+	        | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC1_IPTAT) | (CONF_XOSC1_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)
+	        | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC1_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
+	        | (CONF_XOSC1_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC1_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos));
+#endif
+
+#if CONF_XOSC1_CONFIG == 1
+#if CONF_XOSC1_ENABLE == 1
+	while (!hri_oscctrl_get_STATUS_XOSCRDY1_bit(hw))
+		;
+#endif
+#if CONF_XOSC1_ENALC == 1
+	hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 1);
+#endif
+#if CONF_XOSC1_ONDEMAND == 1
+	hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1);
+#endif
+#endif
+
+	(void)hw;
+}
+
+void _oscctrl_init_referenced_generators(void)
+{
+	void *hw = (void *)OSCCTRL;
+
+#if CONF_DFLL_CONFIG == 1
+	hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K);
+	while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK))
+		;
+	uint8_t tmp;
+	hri_oscctrl_write_DFLLCTRLA_reg(hw, 0);
+#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0
+	hri_gclk_write_PCHCTRL_reg(
+	    GCLK, OSCCTRL_GCLK_ID_DFLL48, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK));
+#endif
+
+	hri_oscctrl_write_DFLLMUL_reg(hw,
+	                              OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP)
+	                                  | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL));
+	while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw))
+		;
+
+	hri_oscctrl_write_DFLLCTRLB_reg(hw, 0);
+	while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw))
+		;
+
+	tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE;
+	hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp);
+	while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw))
+		;
+
+#if CONF_DFLL_OVERWRITE_CALIBRATION == 1
+	hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE));
+#endif
+	hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw));
+	while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw))
+		;
+
+	tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)
+	      | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos)
+	      | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos)
+	      | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0;
+	hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp);
+	while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw))
+		;
+#endif
+
+#if CONF_FDPLL0_CONFIG == 1
+#if CONF_FDPLL0_REFCLK == 0
+	hri_gclk_write_PCHCTRL_reg(
+	    GCLK, OSCCTRL_GCLK_ID_FDPLL0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL0_GCLK));
+#endif
+	hri_oscctrl_write_DPLLRATIO_reg(
+	    hw, 0, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL0_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL0_LDR));
+	hri_oscctrl_write_DPLLCTRLB_reg(
+	    hw,
+	    0,
+	    OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL0_DIV) | (CONF_FDPLL0_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos)
+	        | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL0_DCOFILTER)
+	        | (CONF_FDPLL0_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL0_LTIME)
+	        | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL0_REFCLK) | (CONF_FDPLL0_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos)
+	        | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL0_FILTER));
+	hri_oscctrl_write_DPLLCTRLA_reg(hw,
+	                                0,
+	                                (CONF_FDPLL0_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+	                                    | (CONF_FDPLL0_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos));
+#endif
+
+#if CONF_FDPLL1_CONFIG == 1
+#if CONF_FDPLL1_REFCLK == 0
+	hri_gclk_write_PCHCTRL_reg(
+	    GCLK, OSCCTRL_GCLK_ID_FDPLL1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL1_GCLK));
+#endif
+	hri_oscctrl_write_DPLLRATIO_reg(
+	    hw, 1, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL1_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL1_LDR));
+	hri_oscctrl_write_DPLLCTRLB_reg(
+	    hw,
+	    1,
+	    OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL1_DIV) | (CONF_FDPLL1_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos)
+	        | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL1_DCOFILTER)
+	        | (CONF_FDPLL1_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL1_LTIME)
+	        | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL1_REFCLK) | (CONF_FDPLL1_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos)
+	        | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL1_FILTER));
+	hri_oscctrl_write_DPLLCTRLA_reg(hw,
+	                                1,
+	                                (CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+	                                    | (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos));
+#endif
+
+#if CONF_DFLL_CONFIG == 1
+	if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) {
+		hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC;
+
+		while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask)
+			;
+	} else {
+		while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw))
+			;
+	}
+#if CONF_DFLL_ONDEMAND == 1
+	hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(hw);
+#endif
+#endif
+
+#if CONF_FDPLL0_CONFIG == 1
+#if CONF_FDPLL0_ENABLE == 1
+	while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0)))
+		;
+#endif
+#if CONF_FDPLL0_ONDEMAND == 1
+	hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 0);
+#endif
+#endif
+
+#if CONF_FDPLL1_CONFIG == 1
+#if CONF_FDPLL1_ENABLE == 1
+	while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 1) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 1)))
+		;
+#endif
+#if CONF_FDPLL1_ONDEMAND == 1
+	hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1);
+#endif
+#endif
+
+#if CONF_DFLL_CONFIG == 1
+	while (hri_gclk_read_SYNCBUSY_reg(GCLK))
+		;
+	hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE);
+	while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK))
+		;
+#endif
+	(void)hw;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/pm/hpl_pm.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/pm/hpl_pm.c
new file mode 100644
index 0000000..55dc4db
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/pm/hpl_pm.c
@@ -0,0 +1,68 @@
+
+/**
+ * \file
+ *
+ * \brief SAM Power manager
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_sleep.h>
+#include <hpl_init.h>
+
+/**
+ * \brief Set the sleep mode for the device
+ */
+int32_t _set_sleep_mode(const uint8_t mode)
+{
+	uint8_t delay = 10;
+
+	switch (mode) {
+	case 2:
+	case 4:
+	case 5:
+	case 6:
+	case 7:
+		hri_pm_write_SLEEPCFG_reg(PM, mode);
+		/* A small latency happens between the store instruction and actual
+		 * writing of the SLEEPCFG register due to bridges. Software has to make
+		 * sure the SLEEPCFG register reads the wanted value before issuing WFI
+		 * instruction.
+		 */
+		do {
+			if (hri_pm_read_SLEEPCFG_reg(PM) == mode) {
+				break;
+			}
+		} while (--delay);
+		break;
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return ERR_NONE;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/pm/hpl_pm_base.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/pm/hpl_pm_base.h
new file mode 100644
index 0000000..5a50a91
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/pm/hpl_pm_base.h
@@ -0,0 +1,45 @@
+/**
+ * \file
+ *
+ * \brief SAM Power manager
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _HPL_PM_BASE_H_INCLUDED
+#define _HPL_PM_BASE_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <utils_assert.h>
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HPL_PM_BASE_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/port/hpl_gpio_base.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/port/hpl_gpio_base.h
new file mode 100644
index 0000000..b4fa78b
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/port/hpl_gpio_base.h
@@ -0,0 +1,170 @@
+
+/**
+ * \file
+ *
+ * \brief SAM PORT.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <compiler.h>
+#include <hpl_gpio.h>
+#include <utils_assert.h>
+#include <hpl_port_config.h>
+
+/**
+ * \brief Set direction on port with mask
+ */
+static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
+                                       const enum gpio_direction direction)
+{
+	switch (direction) {
+	case GPIO_DIRECTION_OFF:
+		hri_port_clear_DIR_reg(PORT, port, mask);
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
+		hri_port_write_WRCONFIG_reg(
+		    PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16));
+		break;
+
+	case GPIO_DIRECTION_IN:
+		hri_port_clear_DIR_reg(PORT, port, mask);
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff));
+		hri_port_write_WRCONFIG_reg(PORT,
+		                            port,
+		                            PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN
+		                                | ((mask & 0xffff0000) >> 16));
+		break;
+
+	case GPIO_DIRECTION_OUT:
+		hri_port_set_DIR_reg(PORT, port, mask);
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
+		hri_port_write_WRCONFIG_reg(
+		    PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16));
+		break;
+
+	default:
+		ASSERT(false);
+	}
+}
+
+/**
+ * \brief Set output level on port with mask
+ */
+static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level)
+{
+	if (level) {
+		hri_port_set_OUT_reg(PORT, port, mask);
+	} else {
+		hri_port_clear_OUT_reg(PORT, port, mask);
+	}
+}
+
+/**
+ * \brief Change output level to the opposite with mask
+ */
+static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask)
+{
+	hri_port_toggle_OUT_reg(PORT, port, mask);
+}
+
+/**
+ * \brief Get input levels on all port pins
+ */
+static inline uint32_t _gpio_get_level(const enum gpio_port port)
+{
+	uint32_t tmp;
+
+	CRITICAL_SECTION_ENTER();
+
+	uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port);
+
+	tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp;
+	tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp;
+
+	CRITICAL_SECTION_LEAVE();
+
+	return tmp;
+}
+
+/**
+ * \brief Set pin pull mode
+ */
+static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
+                                           const enum gpio_pull_mode pull_mode)
+{
+	switch (pull_mode) {
+	case GPIO_PULL_OFF:
+		hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin);
+		break;
+
+	case GPIO_PULL_UP:
+		hri_port_clear_DIR_reg(PORT, port, 1U << pin);
+		hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin);
+		hri_port_set_OUT_reg(PORT, port, 1U << pin);
+		break;
+
+	case GPIO_PULL_DOWN:
+		hri_port_clear_DIR_reg(PORT, port, 1U << pin);
+		hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin);
+		hri_port_clear_OUT_reg(PORT, port, 1U << pin);
+		break;
+
+	default:
+		ASSERT(false);
+		break;
+	}
+}
+
+/**
+ * \brief Set gpio pin function
+ */
+static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function)
+{
+	uint8_t port = GPIO_PORT(gpio);
+	uint8_t pin  = GPIO_PIN(gpio);
+
+	if (function == GPIO_PIN_FUNCTION_OFF) {
+		hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false);
+
+	} else {
+		hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true);
+
+		if (pin & 1) {
+			// Odd numbered pin
+			hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff);
+		} else {
+			// Even numbered pin
+			hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff);
+		}
+	}
+}
+
+static inline void _port_event_init()
+{
+	hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL);
+	hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL);
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/qspi/hpl_qspi.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/qspi/hpl_qspi.c
new file mode 100644
index 0000000..af00ba9
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/qspi/hpl_qspi.c
@@ -0,0 +1,331 @@
+/**
+ * \file
+ *
+ * \brief QSPI Driver
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_assert.h>
+#include <hpl_qspi_sync.h>
+#include <hpl_qspi_dma.h>
+#include <hpl_qspi_config.h>
+
+/**
+ * \brief Memory copy function.
+ *
+ * \param dst  Pointer to destination buffer.
+ * \param src  Pointer to source buffer.
+ * \param count  Bytes to be copied.
+ */
+static void _qspi_memcpy(uint8_t *dst, uint8_t *src, uint32_t count)
+{
+	while (count--) {
+		*dst++ = *src++;
+	}
+}
+
+/**
+ * \brief Ends ongoing transfer by releasing CS of QSPI peripheral.
+ *
+ * \param qspi  Pointer to an Qspi instance.
+ */
+static inline void _qspi_end_transfer(void *hw)
+{
+	hri_qspi_write_CTRLA_reg(hw, QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER);
+}
+
+int32_t _qspi_sync_init(struct _qspi_sync_dev *dev, void *const hw)
+{
+	ASSERT(dev && hw);
+	dev->prvt = hw;
+	hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_SWRST);
+
+	hri_qspi_write_CTRLB_reg(hw,
+	                         QSPI_CTRLB_MODE_MEMORY | QSPI_CTRLB_CSMODE_LASTXFER | QSPI_CTRLB_DATALEN(0)
+	                             | QSPI_CTRLB_DLYBCT(0) | QSPI_CTRLB_DLYCS(CONF_QSPI_DLYCS));
+
+	hri_qspi_write_BAUD_reg(hw,
+	                        CONF_QSPI_CPOL << QSPI_BAUD_CPOL_Pos | CONF_QSPI_CPHA << QSPI_BAUD_CPHA_Pos
+	                            | QSPI_BAUD_BAUD(CONF_QSPI_BAUD_RATE) | QSPI_BAUD_DLYBS(CONF_QSPI_DLYBS));
+	return ERR_NONE;
+}
+
+int32_t _qspi_sync_deinit(struct _qspi_sync_dev *dev)
+{
+	hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_SWRST);
+	return ERR_NONE;
+}
+
+int32_t _qspi_sync_enable(struct _qspi_sync_dev *dev)
+{
+	hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_ENABLE);
+	return ERR_NONE;
+}
+
+int32_t _qspi_sync_disable(struct _qspi_sync_dev *dev)
+{
+	hri_qspi_write_CTRLA_reg(dev->prvt, 0);
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set instruction frame param.
+ */
+static void _qspi_sync_command_set_ifr(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd)
+{
+	void *hw = dev->prvt;
+	if (cmd->inst_frame.bits.addr_en) {
+		hri_qspi_write_INSTRADDR_reg(hw, cmd->address);
+	}
+
+	if (cmd->inst_frame.bits.inst_en) {
+		hri_qspi_write_INSTRCTRL_INSTR_bf(hw, cmd->instruction);
+	}
+
+	if (cmd->inst_frame.bits.opt_en) {
+		hri_qspi_write_INSTRCTRL_OPTCODE_bf(hw, cmd->option);
+	}
+
+	hri_qspi_write_INSTRFRAME_reg(hw, cmd->inst_frame.word);
+}
+
+/**
+ * \brief Access QSPI mapping memory via AHB.
+ */
+static void _qspi_sync_run_transfer(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd)
+{
+	void *   hw       = dev->prvt;
+	uint8_t *qspi_mem = (uint8_t *)QSPI_AHB;
+	if (cmd->inst_frame.bits.addr_en)
+		qspi_mem += cmd->address;
+
+	/* To synchronize system bus accesses */
+	hri_qspi_read_INSTRFRAME_reg(hw);
+
+	ASSERT(cmd->tx_buf || cmd->rx_buf);
+
+	if (cmd->tx_buf) {
+		_qspi_memcpy((uint8_t *)qspi_mem, (uint8_t *)cmd->tx_buf, cmd->buf_len);
+	} else {
+		_qspi_memcpy((uint8_t *)cmd->rx_buf, (uint8_t *)qspi_mem, cmd->buf_len);
+	}
+
+	__DSB();
+	__ISB();
+}
+
+int32_t _qspi_sync_serial_run_command(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd)
+{
+	_qspi_sync_command_set_ifr(dev, cmd);
+
+	if (cmd->inst_frame.bits.data_en) {
+		_qspi_sync_run_transfer(dev, cmd);
+	}
+
+	_qspi_end_transfer(dev->prvt);
+
+	while (!hri_qspi_get_INTFLAG_INSTREND_bit(dev->prvt))
+		;
+	hri_qspi_clear_INTFLAG_INSTREND_bit(dev->prvt);
+	return ERR_NONE;
+}
+/**
+ *  \brief Callback for RX
+ *  \param[in, out] dev Pointer to the DMA resource.
+ */
+static void _qspi_dma_rx_complete(struct _dma_resource *resource)
+{
+	struct _qspi_dma_dev *dev = (struct _qspi_dma_dev *)resource->back;
+
+	_qspi_end_transfer(dev->prvt);
+
+	if (dev->cb.xfer_done) {
+		dev->cb.xfer_done(resource);
+	}
+}
+
+/**
+ *  \brief Callback for TX
+ *  \param[in, out] dev Pointer to the DMA resource.
+ */
+static void _qspi_dma_tx_complete(struct _dma_resource *resource)
+{
+	struct _qspi_dma_dev *dev = (struct _qspi_dma_dev *)resource->back;
+
+	_qspi_end_transfer(dev->prvt);
+
+	if (dev->cb.xfer_done) {
+		dev->cb.xfer_done(resource);
+	}
+}
+
+/**
+ *  \brief Callback for ERROR
+ *  \param[in, out] dev Pointer to the DMA resource.
+ */
+static void _qspi_dma_error_occured(struct _dma_resource *resource)
+{
+	struct _qspi_dma_dev *dev = (struct _qspi_dma_dev *)resource->back;
+
+	if (dev->cb.error) {
+		dev->cb.error(resource);
+	}
+}
+
+int32_t _qspi_dma_init(struct _qspi_dma_dev *dev, void *const hw)
+{
+	ASSERT(dev && hw);
+	dev->prvt = hw;
+	hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_SWRST);
+
+	hri_qspi_write_CTRLB_reg(hw,
+	                         QSPI_CTRLB_MODE_MEMORY | QSPI_CTRLB_CSMODE_LASTXFER | QSPI_CTRLB_DATALEN(0)
+	                             | QSPI_CTRLB_DLYBCT(0) | QSPI_CTRLB_DLYCS(CONF_QSPI_DLYCS));
+
+	hri_qspi_write_BAUD_reg(hw,
+	                        CONF_QSPI_CPOL << QSPI_BAUD_CPOL_Pos | CONF_QSPI_CPHA << QSPI_BAUD_CPHA_Pos
+	                            | QSPI_BAUD_BAUD(CONF_QSPI_BAUD_RATE) | QSPI_BAUD_DLYBS(CONF_QSPI_DLYBS));
+
+	/* Initialize DMA rx channel */
+	_dma_get_channel_resource(&dev->resource, CONF_QSPI_DMA_RX_CHANNEL);
+	dev->resource->back                 = dev;
+	dev->resource->dma_cb.transfer_done = _qspi_dma_rx_complete;
+	dev->resource->dma_cb.error         = _qspi_dma_error_occured;
+	/* Initialize DMA tx channel */
+	_dma_get_channel_resource(&dev->resource, CONF_QSPI_DMA_TX_CHANNEL);
+	dev->resource->back                 = dev;
+	dev->resource->dma_cb.transfer_done = _qspi_dma_tx_complete;
+	dev->resource->dma_cb.error         = _qspi_dma_error_occured;
+
+	return ERR_NONE;
+}
+
+int32_t _qspi_dma_deinit(struct _qspi_dma_dev *dev)
+{
+	hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_SWRST);
+	return ERR_NONE;
+}
+
+int32_t _qspi_dma_enable(struct _qspi_dma_dev *dev)
+{
+	hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_ENABLE);
+	return ERR_NONE;
+}
+
+int32_t _qspi_dma_disable(struct _qspi_dma_dev *dev)
+{
+	hri_qspi_write_CTRLA_reg(dev->prvt, 0);
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set instruction frame param.
+ */
+static void _qspi_dma_command_set_ifr(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd)
+{
+	void *hw = dev->prvt;
+
+	if (cmd->inst_frame.bits.addr_en) {
+		hri_qspi_write_INSTRADDR_reg(hw, cmd->address);
+	}
+
+	if (cmd->inst_frame.bits.inst_en) {
+		hri_qspi_write_INSTRCTRL_INSTR_bf(hw, cmd->instruction);
+	}
+
+	if (cmd->inst_frame.bits.opt_en) {
+		hri_qspi_write_INSTRCTRL_OPTCODE_bf(hw, cmd->option);
+	}
+
+	hri_qspi_write_INSTRFRAME_reg(hw, cmd->inst_frame.word);
+}
+
+/**
+ * \brief Access QSPI mapping memory via AHB.
+ */
+static void _qspi_dma_run_transfer(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd)
+{
+	void *   hw       = dev->prvt;
+	uint8_t *qspi_mem = (uint8_t *)QSPI_AHB;
+
+	if (cmd->inst_frame.bits.addr_en) {
+		qspi_mem += cmd->address;
+	}
+
+	/* To synchronize system bus accesses */
+	hri_qspi_read_INSTRFRAME_reg(hw);
+
+	ASSERT(cmd->tx_buf || cmd->rx_buf);
+
+	if (cmd->tx_buf) {
+		_dma_set_source_address(CONF_QSPI_DMA_TX_CHANNEL, cmd->tx_buf);
+		_dma_set_destination_address(CONF_QSPI_DMA_TX_CHANNEL, (uint8_t *)qspi_mem);
+		_dma_set_data_amount(CONF_QSPI_DMA_TX_CHANNEL, cmd->buf_len);
+		_dma_enable_transaction(CONF_QSPI_DMA_TX_CHANNEL, false);
+	} else {
+		_dma_set_source_address(CONF_QSPI_DMA_RX_CHANNEL, (uint8_t *)qspi_mem);
+		_dma_set_destination_address(CONF_QSPI_DMA_RX_CHANNEL, cmd->rx_buf);
+		_dma_set_data_amount(CONF_QSPI_DMA_RX_CHANNEL, cmd->buf_len);
+		_dma_enable_transaction(CONF_QSPI_DMA_RX_CHANNEL, false);
+		/* first read and then trig DMA */
+		*(uint8_t *)(cmd->rx_buf) = qspi_mem[0];
+	}
+
+	__DSB();
+	__ISB();
+}
+
+int32_t _qspi_dma_serial_run_command(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd)
+{
+	_qspi_dma_command_set_ifr(dev, cmd);
+
+	if (cmd->inst_frame.bits.data_en) {
+		_qspi_dma_run_transfer(dev, cmd);
+	}
+
+	return ERR_NONE;
+}
+
+void _qspi_dma_register_callback(struct _qspi_dma_dev *dev, enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb)
+{
+	switch (type) {
+	case QSPI_DMA_CB_XFER_DONE:
+		dev->cb.xfer_done = cb;
+		_dma_set_irq_state(CONF_QSPI_DMA_TX_CHANNEL, DMA_TRANSFER_COMPLETE_CB, cb != NULL);
+		_dma_set_irq_state(CONF_QSPI_DMA_RX_CHANNEL, DMA_TRANSFER_COMPLETE_CB, cb != NULL);
+		break;
+	case QSPI_DMA_CB_ERROR:
+		dev->cb.error = cb;
+		_dma_set_irq_state(CONF_QSPI_DMA_TX_CHANNEL, DMA_TRANSFER_ERROR_CB, cb != NULL);
+		_dma_set_irq_state(CONF_QSPI_DMA_RX_CHANNEL, DMA_TRANSFER_ERROR_CB, cb != NULL);
+		break;
+	default:
+		break;
+	}
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/ramecc/hpl_ramecc.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/ramecc/hpl_ramecc.c
new file mode 100644
index 0000000..4c158b2
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/ramecc/hpl_ramecc.c
@@ -0,0 +1,83 @@
+/**
+ * \file
+ *
+ * \brief Generic RAMECC related functionality.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils.h>
+#include <utils_assert.h>
+#include <hpl_ramecc.h>
+
+/* RAMECC device descriptor */
+struct _ramecc_device device;
+
+/**
+ * \brief Initialize RAMECC
+ */
+int32_t _ramecc_init(void)
+{
+	if (hri_ramecc_get_STATUS_ECCDIS_bit(RAMECC)) {
+		return ERR_ABORTED;
+	}
+
+	NVIC_DisableIRQ(RAMECC_IRQn);
+	NVIC_ClearPendingIRQ(RAMECC_IRQn);
+	NVIC_EnableIRQ(RAMECC_IRQn);
+
+	return ERR_NONE;
+}
+
+void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb)
+{
+	if (RAMECC_DUAL_ERROR_CB == type) {
+		device.ramecc_cb.dual_bit_err = cb;
+		hri_ramecc_write_INTEN_DUALE_bit(RAMECC, NULL != cb);
+	} else if (RAMECC_SINGLE_ERROR_CB == type) {
+		device.ramecc_cb.single_bit_err = cb;
+		hri_ramecc_write_INTEN_SINGLEE_bit(RAMECC, NULL != cb);
+	}
+}
+
+/**
+ * \internal RAMECC interrupt handler
+ */
+void RAMECC_Handler(void)
+{
+	struct _ramecc_device *dev      = (struct _ramecc_device *)&device;
+	volatile uint32_t      int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC);
+
+	if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) {
+		dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
+	} else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) {
+		dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
+	} else {
+		return;
+	}
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/sercom/hpl_sercom.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/sercom/hpl_sercom.c
new file mode 100644
index 0000000..957e259
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/sercom/hpl_sercom.c
@@ -0,0 +1,3462 @@
+
+/**
+ * \file
+ *
+ * \brief SAM Serial Communication Interface
+ *
+ * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <hpl_spi_m_dma.h>
+#include <hpl_dma.h>
+#include <hpl_i2c_m_async.h>
+#include <hpl_i2c_m_sync.h>
+#include <hpl_i2c_s_async.h>
+#include <hpl_sercom_config.h>
+#include <hpl_spi_m_async.h>
+#include <hpl_spi_m_sync.h>
+#include <hpl_spi_s_async.h>
+#include <hpl_spi_s_sync.h>
+#include <hpl_usart_async.h>
+#include <hpl_usart_sync.h>
+#include <utils.h>
+#include <utils_assert.h>
+
+#ifndef CONF_SERCOM_0_USART_ENABLE
+#define CONF_SERCOM_0_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_1_USART_ENABLE
+#define CONF_SERCOM_1_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_2_USART_ENABLE
+#define CONF_SERCOM_2_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_3_USART_ENABLE
+#define CONF_SERCOM_3_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_4_USART_ENABLE
+#define CONF_SERCOM_4_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_5_USART_ENABLE
+#define CONF_SERCOM_5_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_6_USART_ENABLE
+#define CONF_SERCOM_6_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_7_USART_ENABLE
+#define CONF_SERCOM_7_USART_ENABLE 0
+#endif
+
+/** Amount of SERCOM that is used as USART. */
+#define SERCOM_USART_AMOUNT                                                                                            \
+	(CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \
+	 + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE                            \
+	 + CONF_SERCOM_7_USART_ENABLE)
+
+/**
+ * \brief Macro is used to fill usart configuration structure based on
+ * its number
+ *
+ * \param[in] n The number of structures
+ */
+#define SERCOM_CONFIGURATION(n)                                                                                        \
+	{                                                                                                                  \
+		n,                                                                                                             \
+		    SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE)                                                      \
+		        | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos)                                \
+		        | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos)                                        \
+		        | (CONF_SERCOM_##n##_USART_TXINV << SERCOM_USART_CTRLA_TXINV_Pos)                                      \
+		        | (CONF_SERCOM_##n##_USART_RXINV << SERCOM_USART_CTRLA_RXINV_Pos)                                      \
+		        | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR)                                              \
+		        | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO)                                                \
+		        | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO)                                                \
+		        | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA)                                              \
+		        | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM)                                                \
+		        | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos)                                      \
+		        | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos)                                        \
+		        | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos),                                       \
+		    SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE)                                                  \
+		        | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos)                                    \
+		        | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos)                                    \
+		        | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos)                                        \
+		        | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos)                                          \
+		        | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos)                                      \
+		        | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos)                                        \
+		        | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos),                                       \
+		    SERCOM_USART_CTRLC_GTIME(CONF_SERCOM_##n##_USART_GTIME)                                                    \
+		        | (CONF_SERCOM_##n##_USART_DSNACK << SERCOM_USART_CTRLC_DSNACK_Pos)                                    \
+		        | (CONF_SERCOM_##n##_USART_INACK << SERCOM_USART_CTRLC_INACK_Pos)                                      \
+		        | SERCOM_USART_CTRLC_MAXITER(CONF_SERCOM_##n##_USART_MAXITER),                                         \
+		    (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL,                         \
+		    CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE,                     \
+	}
+
+/**
+ * \brief SERCOM USART configuration type
+ */
+struct usart_configuration {
+	uint8_t                       number;
+	hri_sercomusart_ctrla_reg_t   ctrl_a;
+	hri_sercomusart_ctrlb_reg_t   ctrl_b;
+	hri_sercomusart_ctrlc_reg_t   ctrl_c;
+	hri_sercomusart_baud_reg_t    baud;
+	uint8_t                       fractional;
+	hri_sercomusart_rxpl_reg_t    rxpl;
+	hri_sercomusart_dbgctrl_reg_t debug_ctrl;
+};
+
+#if SERCOM_USART_AMOUNT < 1
+/** Dummy array to pass compiling. */
+static struct usart_configuration _usarts[1] = {{0}};
+#else
+/**
+ * \brief Array of SERCOM USART configurations
+ */
+static struct usart_configuration _usarts[] = {
+#if CONF_SERCOM_0_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(0),
+#endif
+#if CONF_SERCOM_1_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(1),
+#endif
+#if CONF_SERCOM_2_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(2),
+#endif
+#if CONF_SERCOM_3_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(3),
+#endif
+#if CONF_SERCOM_4_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(4),
+#endif
+#if CONF_SERCOM_5_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(5),
+#endif
+#if CONF_SERCOM_6_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(6),
+#endif
+#if CONF_SERCOM_7_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(7),
+#endif
+};
+#endif
+
+static struct _i2c_m_async_device *_sercom0_dev = NULL;
+
+static uint8_t _get_sercom_index(const void *const hw);
+static uint8_t _sercom_get_irq_num(const void *const hw);
+static void    _sercom_init_irq_param(const void *const hw, void *dev);
+static uint8_t _sercom_get_hardware_index(const void *const hw);
+
+static int32_t     _usart_init(void *const hw);
+static inline void _usart_deinit(void *const hw);
+static uint16_t    _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
+                                              const enum usart_baud_rate_mode mode, const uint8_t fraction);
+static void        _usart_set_baud_rate(void *const hw, const uint32_t baud_rate);
+static void        _usart_set_data_order(void *const hw, const enum usart_data_order order);
+static void        _usart_set_mode(void *const hw, const enum usart_mode mode);
+static void        _usart_set_parity(void *const hw, const enum usart_parity parity);
+static void        _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits);
+static void        _usart_set_character_size(void *const hw, const enum usart_character_size size);
+
+/**
+ * \brief Initialize synchronous SERCOM USART
+ */
+int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw)
+{
+	ASSERT(device);
+
+	device->hw = hw;
+
+	return _usart_init(hw);
+}
+
+/**
+ * \brief Initialize asynchronous SERCOM USART
+ */
+int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw)
+{
+	int32_t init_status;
+
+	ASSERT(device);
+
+	init_status = _usart_init(hw);
+	if (init_status) {
+		return init_status;
+	}
+	device->hw = hw;
+	_sercom_init_irq_param(hw, (void *)device);
+	uint8_t irq = _sercom_get_irq_num(hw);
+	for (uint32_t i = 0; i < 4; i++) {
+		NVIC_DisableIRQ((IRQn_Type)irq);
+		NVIC_ClearPendingIRQ((IRQn_Type)irq);
+		NVIC_EnableIRQ((IRQn_Type)irq);
+		irq++;
+	}
+	return ERR_NONE;
+}
+
+/**
+ * \brief De-initialize SERCOM USART
+ */
+void _usart_sync_deinit(struct _usart_sync_device *const device)
+{
+	_usart_deinit(device->hw);
+}
+
+/**
+ * \brief De-initialize SERCOM USART
+ */
+void _usart_async_deinit(struct _usart_async_device *const device)
+{
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw));
+	_usart_deinit(device->hw);
+}
+
+/**
+ * \brief Calculate baud rate register value
+ */
+uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
+                                         const enum usart_baud_rate_mode mode, const uint8_t fraction)
+{
+	return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction);
+}
+
+/**
+ * \brief Calculate baud rate register value
+ */
+uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
+                                          const enum usart_baud_rate_mode mode, const uint8_t fraction)
+{
+	return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction);
+}
+
+/**
+ * \brief Enable SERCOM module
+ */
+void _usart_sync_enable(struct _usart_sync_device *const device)
+{
+	hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Enable SERCOM module
+ */
+void _usart_async_enable(struct _usart_async_device *const device)
+{
+	hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable SERCOM module
+ */
+void _usart_sync_disable(struct _usart_sync_device *const device)
+{
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable SERCOM module
+ */
+void _usart_async_disable(struct _usart_async_device *const device)
+{
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Set baud rate
+ */
+void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate)
+{
+	_usart_set_baud_rate(device->hw, baud_rate);
+}
+
+/**
+ * \brief Set baud rate
+ */
+void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate)
+{
+	_usart_set_baud_rate(device->hw, baud_rate);
+}
+
+/**
+ * \brief Set data order
+ */
+void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order)
+{
+	_usart_set_data_order(device->hw, order);
+}
+
+/**
+ * \brief Set data order
+ */
+void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order)
+{
+	_usart_set_data_order(device->hw, order);
+}
+
+/**
+ * \brief Set mode
+ */
+void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode)
+{
+	_usart_set_mode(device->hw, mode);
+}
+
+/**
+ * \brief Set mode
+ */
+void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode)
+{
+	_usart_set_mode(device->hw, mode);
+}
+
+/**
+ * \brief Set parity
+ */
+void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity)
+{
+	_usart_set_parity(device->hw, parity);
+}
+
+/**
+ * \brief Set parity
+ */
+void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity)
+{
+	_usart_set_parity(device->hw, parity);
+}
+
+/**
+ * \brief Set stop bits mode
+ */
+void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits)
+{
+	_usart_set_stop_bits(device->hw, stop_bits);
+}
+
+/**
+ * \brief Set stop bits mode
+ */
+void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits)
+{
+	_usart_set_stop_bits(device->hw, stop_bits);
+}
+
+/**
+ * \brief Set character size
+ */
+void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size)
+{
+	_usart_set_character_size(device->hw, size);
+}
+
+/**
+ * \brief Set character size
+ */
+void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size)
+{
+	_usart_set_character_size(device->hw, size);
+}
+
+/**
+ * \brief Retrieve SERCOM usart status
+ */
+uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device)
+{
+	return hri_sercomusart_read_STATUS_reg(device->hw);
+}
+
+/**
+ * \brief Retrieve SERCOM usart status
+ */
+uint32_t _usart_async_get_status(const struct _usart_async_device *const device)
+{
+	return hri_sercomusart_read_STATUS_reg(device->hw);
+}
+
+/**
+ * \brief Write a byte to the given SERCOM USART instance
+ */
+void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data)
+{
+	hri_sercomusart_write_DATA_reg(device->hw, data);
+}
+
+/**
+ * \brief Write a byte to the given SERCOM USART instance
+ */
+void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data)
+{
+	hri_sercomusart_write_DATA_reg(device->hw, data);
+}
+
+/**
+ * \brief Read a byte from the given SERCOM USART instance
+ */
+uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device)
+{
+	return hri_sercomusart_read_DATA_reg(device->hw);
+}
+
+/**
+ * \brief Check if USART is ready to send next byte
+ */
+bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device)
+{
+	return hri_sercomusart_get_interrupt_DRE_bit(device->hw);
+}
+
+/**
+ * \brief Check if USART transmission complete
+ */
+bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device)
+{
+	return hri_sercomusart_get_interrupt_TXC_bit(device->hw);
+}
+
+/**
+ * \brief Check if USART is ready to send next byte
+ */
+bool _usart_async_is_byte_sent(const struct _usart_async_device *const device)
+{
+	return hri_sercomusart_get_interrupt_DRE_bit(device->hw);
+}
+
+/**
+ * \brief Check if there is data received by USART
+ */
+bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device)
+{
+	return hri_sercomusart_get_interrupt_RXC_bit(device->hw);
+}
+
+/**
+ * \brief Set the state of flow control pins
+ */
+void _usart_sync_set_flow_control_state(struct _usart_sync_device *const     device,
+                                        const union usart_flow_control_state state)
+{
+	(void)device;
+	(void)state;
+}
+
+/**
+ * \brief Set the state of flow control pins
+ */
+void _usart_async_set_flow_control_state(struct _usart_async_device *const    device,
+                                         const union usart_flow_control_state state)
+{
+	(void)device;
+	(void)state;
+}
+
+/**
+ * \brief Retrieve the state of flow control pins
+ */
+union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device)
+{
+	(void)device;
+	union usart_flow_control_state state;
+
+	state.value           = 0;
+	state.bit.unavailable = 1;
+	return state;
+}
+
+/**
+ * \brief Retrieve the state of flow control pins
+ */
+union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device)
+{
+	(void)device;
+	union usart_flow_control_state state;
+
+	state.value           = 0;
+	state.bit.unavailable = 1;
+	return state;
+}
+
+/**
+ * \brief Enable data register empty interrupt
+ */
+void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device)
+{
+	hri_sercomusart_set_INTEN_DRE_bit(device->hw);
+}
+
+/**
+ * \brief Enable transmission complete interrupt
+ */
+void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device)
+{
+	hri_sercomusart_set_INTEN_TXC_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve ordinal number of the given sercom hardware instance
+ */
+static uint8_t _sercom_get_hardware_index(const void *const hw)
+{
+	Sercom *const sercom_modules[] = SERCOM_INSTS;
+	/* Find index for SERCOM instance. */
+	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+		if ((uint32_t)hw == (uint32_t)sercom_modules[i]) {
+			return i;
+		}
+	}
+	return 0;
+}
+
+/**
+ * \brief Retrieve ordinal number of the given SERCOM USART hardware instance
+ */
+uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device)
+{
+	return _sercom_get_hardware_index(device->hw);
+}
+
+/**
+ * \brief Retrieve ordinal number of the given SERCOM USART hardware instance
+ */
+uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device)
+{
+	return _sercom_get_hardware_index(device->hw);
+}
+
+/**
+ * \brief Enable/disable USART interrupt
+ */
+void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type,
+                                const bool state)
+{
+	ASSERT(device);
+
+	if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) {
+		hri_sercomusart_write_INTEN_DRE_bit(device->hw, state);
+		hri_sercomusart_write_INTEN_TXC_bit(device->hw, state);
+	} else if (USART_ASYNC_RX_DONE == type) {
+		hri_sercomusart_write_INTEN_RXC_bit(device->hw, state);
+	} else if (USART_ASYNC_ERROR == type) {
+		hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state);
+	}
+}
+
+/**
+ * \internal Retrieve ordinal number of the given sercom hardware instance
+ *
+ * \param[in] hw The pointer to hardware instance
+
+ * \return The ordinal number of the given sercom hardware instance
+ */
+static uint8_t _get_sercom_index(const void *const hw)
+{
+	uint8_t sercom_offset = _sercom_get_hardware_index(hw);
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_usarts); i++) {
+		if (_usarts[i].number == sercom_offset) {
+			return i;
+		}
+	}
+
+	ASSERT(false);
+	return 0;
+}
+
+/**
+ * \brief Init irq param with the given sercom hardware instance
+ */
+static void _sercom_init_irq_param(const void *const hw, void *dev)
+{
+
+	if (hw == SERCOM0) {
+		_sercom0_dev = (struct _i2c_m_async_device *)dev;
+	}
+}
+
+/**
+ * \internal Initialize SERCOM USART
+ *
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return The status of initialization
+ */
+static int32_t _usart_init(void *const hw)
+{
+	uint8_t i = _get_sercom_index(hw);
+
+	if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) {
+		uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk;
+		if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) {
+			hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+			hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+		}
+		hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode);
+	}
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+
+	hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a);
+	hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b);
+	hri_sercomusart_write_CTRLC_reg(hw, _usarts[i].ctrl_c);
+	if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) {
+		((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud;
+		((Sercom *)hw)->USART.BAUD.FRAC.FP   = _usarts[i].fractional;
+	} else {
+		hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud);
+	}
+
+	hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl);
+	hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl);
+
+	return ERR_NONE;
+}
+
+/**
+ * \internal De-initialize SERCOM USART
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+static inline void _usart_deinit(void *const hw)
+{
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+	hri_sercomusart_set_CTRLA_SWRST_bit(hw);
+}
+
+/**
+ * \internal Calculate baud rate register value
+ *
+ * \param[in] baud Required baud rate
+ * \param[in] clock_rate SERCOM clock frequency
+ * \param[in] samples The number of samples
+ * \param[in] mode USART mode
+ * \param[in] fraction A fraction value
+ *
+ * \return Calculated baud rate register value
+ */
+static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
+                                           const enum usart_baud_rate_mode mode, const uint8_t fraction)
+{
+	if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) {
+		return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate;
+	}
+
+	if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) {
+		return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction);
+	}
+
+	if (USART_BAUDRATE_SYNCH == mode) {
+		return clock_rate / baud / 2 - 1;
+	}
+
+	return 0;
+}
+
+/**
+ * \internal Set baud rate
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] baud_rate A baud rate to set
+ */
+static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate)
+{
+	bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw);
+
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+	hri_sercomusart_write_BAUD_reg(hw, baud_rate);
+	CRITICAL_SECTION_LEAVE()
+
+	hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled);
+}
+
+/**
+ * \internal Set data order
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] order A data order to set
+ */
+static void _usart_set_data_order(void *const hw, const enum usart_data_order order)
+{
+	bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw);
+
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+	hri_sercomusart_write_CTRLA_DORD_bit(hw, order);
+	CRITICAL_SECTION_LEAVE()
+
+	hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled);
+}
+
+/**
+ * \internal Set mode
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] mode A mode to set
+ */
+static void _usart_set_mode(void *const hw, const enum usart_mode mode)
+{
+	bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw);
+
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+	hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode);
+	CRITICAL_SECTION_LEAVE()
+
+	hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled);
+}
+
+/**
+ * \internal Set parity
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] parity A parity to set
+ */
+static void _usart_set_parity(void *const hw, const enum usart_parity parity)
+{
+	bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw);
+
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+
+	if (USART_PARITY_NONE != parity) {
+		hri_sercomusart_set_CTRLA_FORM_bf(hw, 1);
+	} else {
+		hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1);
+	}
+
+	hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity);
+	CRITICAL_SECTION_LEAVE()
+
+	hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled);
+}
+
+/**
+ * \internal Set stop bits mode
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] stop_bits A stop bits mode to set
+ */
+static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits)
+{
+	bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw);
+
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+	hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits);
+	CRITICAL_SECTION_LEAVE()
+
+	hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled);
+}
+
+/**
+ * \internal Set character size
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] size A character size to set
+ */
+static void _usart_set_character_size(void *const hw, const enum usart_character_size size)
+{
+	bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw);
+
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+	hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size);
+	CRITICAL_SECTION_LEAVE()
+
+	if (enabled) {
+		hri_sercomusart_set_CTRLA_ENABLE_bit(hw);
+	}
+}
+
+	/* Sercom I2C implementation */
+
+#ifndef CONF_SERCOM_0_I2CM_ENABLE
+#define CONF_SERCOM_0_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_1_I2CM_ENABLE
+#define CONF_SERCOM_1_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_2_I2CM_ENABLE
+#define CONF_SERCOM_2_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_3_I2CM_ENABLE
+#define CONF_SERCOM_3_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_4_I2CM_ENABLE
+#define CONF_SERCOM_4_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_5_I2CM_ENABLE
+#define CONF_SERCOM_5_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_6_I2CM_ENABLE
+#define CONF_SERCOM_6_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_7_I2CM_ENABLE
+#define CONF_SERCOM_7_I2CM_ENABLE 0
+#endif
+
+/** Amount of SERCOM that is used as I2C Master. */
+#define SERCOM_I2CM_AMOUNT                                                                                             \
+	(CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE     \
+	 + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE)
+
+/**
+ * \brief Macro is used to fill i2cm configuration structure based on
+ * its number
+ *
+ * \param[in] n The number of structures
+ */
+#define I2CM_CONFIGURATION(n)                                                                                          \
+	{                                                                                                                  \
+		(n),                                                                                                           \
+		    (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)  \
+		        | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos)                                        \
+		        | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)                                  \
+		        | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)                                  \
+		        | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos)                                  \
+		        | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)                                  \
+		        | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos),                                   \
+		    SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE),                                      \
+		    CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \
+	}
+
+#define ERROR_FLAG (1 << 7)
+#define SB_FLAG (1 << 1)
+#define MB_FLAG (1 << 0)
+
+#define CMD_STOP 0x3
+#define I2C_IDLE 0x1
+#define I2C_SM 0x0
+#define I2C_FM 0x1
+#define I2C_HS 0x2
+#define TEN_ADDR_FRAME 0x78
+#define TEN_ADDR_MASK 0x3ff
+#define SEVEN_ADDR_MASK 0x7f
+
+/**
+ * \brief SERCOM I2CM configuration type
+ */
+struct i2cm_configuration {
+	uint8_t                      number;
+	hri_sercomi2cm_ctrla_reg_t   ctrl_a;
+	hri_sercomi2cm_ctrlb_reg_t   ctrl_b;
+	hri_sercomi2cm_baud_reg_t    baud;
+	hri_sercomi2cm_dbgctrl_reg_t dbgctrl;
+	uint16_t                     trise;
+	uint32_t                     clk; /* SERCOM peripheral clock frequency */
+};
+
+static inline int32_t _i2c_m_enable_implementation(void *hw);
+static int32_t        _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw);
+
+#if SERCOM_I2CM_AMOUNT < 1
+/** Dummy array to pass compiling. */
+static struct i2cm_configuration _i2cms[1] = {{0}};
+#else
+/**
+ * \brief Array of SERCOM I2CM configurations
+ */
+static struct i2cm_configuration _i2cms[] = {
+#if CONF_SERCOM_0_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(0),
+#endif
+#if CONF_SERCOM_1_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(1),
+#endif
+#if CONF_SERCOM_2_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(2),
+#endif
+#if CONF_SERCOM_3_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(3),
+#endif
+#if CONF_SERCOM_4_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(4),
+#endif
+#if CONF_SERCOM_5_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(5),
+#endif
+#if CONF_SERCOM_6_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(6),
+#endif
+#if CONF_SERCOM_7_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(7),
+#endif
+};
+#endif
+
+/**
+ * \internal Retrieve ordinal number of the given sercom hardware instance
+ *
+ * \param[in] hw The pointer to hardware instance
+
+ * \return The ordinal number of the given sercom hardware instance
+ */
+static int8_t _get_i2cm_index(const void *const hw)
+{
+	uint8_t sercom_offset = _sercom_get_hardware_index(hw);
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_i2cms); i++) {
+		if (_i2cms[i].number == sercom_offset) {
+			return i;
+		}
+	}
+
+	ASSERT(false);
+	return -1;
+}
+
+static inline void _sercom_i2c_send_stop(void *const hw)
+{
+	hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP);
+}
+
+/**
+ * \brief SERCOM I2CM analyze hardware status and transfer next byte
+ */
+static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg)
+{
+	int      sclsm  = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw);
+	uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw);
+
+	if (flags & MB_FLAG) {
+		/* tx error */
+		if (status & SERCOM_I2CM_STATUS_ARBLOST) {
+			hri_sercomi2cm_clear_interrupt_MB_bit(hw);
+			msg->flags |= I2C_M_FAIL;
+			msg->flags &= ~I2C_M_BUSY;
+
+			if (status & SERCOM_I2CM_STATUS_BUSERR) {
+				return I2C_ERR_BUS;
+			}
+
+			return I2C_ERR_BAD_ADDRESS;
+		} else {
+			if (status & SERCOM_I2CM_STATUS_RXNACK) {
+
+				/* Slave rejects to receive more data */
+				if (msg->len > 0) {
+					msg->flags |= I2C_M_FAIL;
+				}
+
+				if (msg->flags & I2C_M_STOP) {
+					_sercom_i2c_send_stop(hw);
+				}
+
+				msg->flags &= ~I2C_M_BUSY;
+
+				return I2C_NACK;
+			}
+
+			if (msg->flags & I2C_M_TEN) {
+				hri_sercomi2cm_write_ADDR_reg(hw,
+				                              ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD
+				                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+				msg->flags &= ~I2C_M_TEN;
+
+				return I2C_OK;
+			}
+
+			if (msg->len == 0) {
+				if (msg->flags & I2C_M_STOP) {
+					_sercom_i2c_send_stop(hw);
+				}
+
+				msg->flags &= ~I2C_M_BUSY;
+			} else {
+				hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer);
+				msg->buffer++;
+				msg->len--;
+			}
+
+			return I2C_OK;
+		}
+	} else if (flags & SB_FLAG) {
+		if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) {
+			msg->len--;
+
+			/* last byte, send nack */
+			if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) {
+				hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw);
+			}
+
+			if (msg->len == 0) {
+				if (msg->flags & I2C_M_STOP) {
+					hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw);
+					_sercom_i2c_send_stop(hw);
+				}
+
+				msg->flags &= ~I2C_M_BUSY;
+			}
+
+			/* Accessing DATA.DATA auto-triggers I2C bus operations.
+			 * The operation performed depends on the state of
+			 * CTRLB.ACKACT, CTRLB.SMEN
+			 **/
+			*msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw);
+		} else {
+			hri_sercomi2cm_clear_interrupt_SB_bit(hw);
+			return I2C_NACK;
+		}
+
+		hri_sercomi2cm_clear_interrupt_SB_bit(hw);
+	}
+
+	return I2C_OK;
+}
+
+/**
+ * \internal Sercom i2c master interrupt handler
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+static void _sercom_i2c_m_irq_handler(struct _i2c_m_async_device *i2c_dev)
+{
+	void *   hw    = i2c_dev->hw;
+	uint32_t flags = hri_sercomi2cm_read_INTFLAG_reg(hw);
+	int32_t  ret   = I2C_OK;
+
+	ASSERT(i2c_dev);
+	ASSERT(i2c_dev->hw);
+
+	while (!(flags & ERROR_FLAG)) {
+		ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg);
+
+		if (ret != 0) {
+			break;
+		}
+
+		/* app callback */
+		if ((flags & MB_FLAG) && i2c_dev->cb.tx_complete) {
+			i2c_dev->cb.tx_complete(i2c_dev);
+		} else if ((flags & SB_FLAG) && i2c_dev->cb.rx_complete) {
+			i2c_dev->cb.rx_complete(i2c_dev);
+		}
+
+		return;
+	}
+
+	i2c_dev->service.msg.flags &= ~I2C_M_BUSY;
+	if (i2c_dev->cb.error) {
+		if (ret != I2C_OK) {
+			i2c_dev->cb.error(i2c_dev, ret);
+		} else {
+			i2c_dev->cb.error(i2c_dev, I2C_ERR_BUS);
+		}
+		hri_sercomi2cm_clear_INTFLAG_reg(hw, SERCOM_I2CM_INTFLAG_ERROR);
+	}
+}
+
+/**
+ * \brief Enable the i2c master module
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev)
+{
+	ASSERT(i2c_dev);
+
+	return _i2c_m_enable_implementation(i2c_dev->hw);
+}
+
+/**
+ * \brief Disable the i2c master module
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev)
+{
+	void *hw = i2c_dev->hw;
+
+	ASSERT(i2c_dev);
+	ASSERT(i2c_dev->hw);
+
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+	hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set baudrate of master
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ * \param[in] clkrate The clock rate of i2c master, in KHz
+ * \param[in] baudrate The baud rate desired for i2c master, in KHz
+ */
+int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate)
+{
+	uint32_t tmp;
+	void *   hw = i2c_dev->hw;
+
+	if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) {
+		return ERR_DENIED;
+	}
+
+	tmp     = _get_i2cm_index(hw);
+	clkrate = _i2cms[tmp].clk / 1000;
+
+	if (i2c_dev->service.mode == I2C_STANDARD_MODE) {
+		tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001))
+		                 / (2 * baudrate));
+		hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp);
+	} else if (i2c_dev->service.mode == I2C_FASTMODE) {
+		tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001))
+		                 / (2 * baudrate));
+		hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp);
+	} else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) {
+		tmp = (clkrate - 2 * baudrate) / (2 * baudrate);
+		hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp);
+	} else {
+		/* error baudrate */
+		return ERR_INVALID_ARG;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve IRQ number for the given hardware instance
+ */
+static uint8_t _sercom_get_irq_num(const void *const hw)
+{
+	return SERCOM0_0_IRQn + (_sercom_get_hardware_index(hw) << 2);
+}
+
+/**
+ * \brief Initialize sercom i2c module to use in async mode
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw)
+{
+	int32_t init_status;
+
+	ASSERT(i2c_dev);
+
+	i2c_dev->hw = hw;
+
+	init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw);
+	if (init_status) {
+		return init_status;
+	}
+
+	_sercom_init_irq_param(hw, (void *)i2c_dev);
+	uint8_t irq = _sercom_get_irq_num(hw);
+	for (uint32_t i = 0; i < 4; i++) {
+		NVIC_DisableIRQ((IRQn_Type)irq);
+		NVIC_ClearPendingIRQ((IRQn_Type)irq);
+		NVIC_EnableIRQ((IRQn_Type)irq);
+		irq++;
+	}
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinitialize sercom i2c module
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev)
+{
+	ASSERT(i2c_dev);
+
+	hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw);
+	hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Transfer the slave address to bus, which will start the transfer
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev)
+{
+	void *             hw    = i2c_dev->hw;
+	struct _i2c_m_msg *msg   = &i2c_dev->service.msg;
+	int                sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw);
+
+	ASSERT(i2c_dev);
+
+	if (msg->len == 1 && sclsm) {
+		hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw);
+	} else {
+		hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw);
+	}
+
+	/* ten bit address */
+	if (msg->addr & I2C_M_TEN) {
+		if (msg->flags & I2C_M_RD) {
+			msg->flags |= I2C_M_TEN;
+		}
+
+		hri_sercomi2cm_write_ADDR_reg(hw,
+		                              ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN
+		                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+	} else {
+		hri_sercomi2cm_write_ADDR_reg(hw,
+		                              ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0)
+		                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Transfer data specified by msg
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ * \param[in] msg The pointer to i2c message
+ *
+ * \return Transfer status.
+ * \retval 0 Transfer success
+ * \retval <0 Transfer fail, return the error code
+ */
+int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg)
+{
+	int ret;
+
+	ASSERT(i2c_dev);
+	ASSERT(i2c_dev->hw);
+	ASSERT(msg);
+
+	if (msg->len == 0) {
+		return ERR_NONE;
+	}
+
+	if (i2c_dev->service.msg.flags & I2C_M_BUSY) {
+		return ERR_BUSY;
+	}
+
+	msg->flags |= I2C_M_BUSY;
+	i2c_dev->service.msg = *msg;
+	hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw);
+
+	ret = _sercom_i2c_send_address(i2c_dev);
+
+	if (ret) {
+		i2c_dev->service.msg.flags &= ~I2C_M_BUSY;
+
+		return ret;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set callback to be called in interrupt handler
+ *
+ * \param[in] i2c_dev The pointer to master i2c device
+ * \param[in] type The callback type
+ * \param[in] func The callback function pointer
+ */
+int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type,
+                                       FUNC_PTR func)
+{
+	switch (type) {
+	case I2C_M_ASYNC_DEVICE_ERROR:
+		i2c_dev->cb.error = (_i2c_error_cb_t)func;
+		break;
+	case I2C_M_ASYNC_DEVICE_TX_COMPLETE:
+		i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func;
+		break;
+	case I2C_M_ASYNC_DEVICE_RX_COMPLETE:
+		i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func;
+		break;
+	default:
+		/* error */
+		break;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set stop condition on I2C
+ *
+ * \param i2c_dev Pointer to master i2c device
+ *
+ * \return Operation status
+ * \retval I2C_OK Operation was successfull
+ */
+int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev)
+{
+	void *hw = i2c_dev->hw;
+
+	_sercom_i2c_send_stop(hw);
+
+	return I2C_OK;
+}
+
+/**
+ * \brief Get number of bytes left in transfer buffer
+ *
+ * \param i2c_dev Pointer to i2c master device
+ *
+ * \return Bytes left in buffer
+ * \retval =>0 Bytes left in buffer
+ */
+int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev)
+{
+	if (i2c_dev->service.msg.flags & I2C_M_BUSY) {
+		return i2c_dev->service.msg.len;
+	}
+
+	return 0;
+}
+
+/**
+ * \brief Initialize sercom i2c module to use in sync mode
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw)
+{
+	ASSERT(i2c_dev);
+
+	i2c_dev->hw = hw;
+
+	return _i2c_m_sync_init_impl(&i2c_dev->service, hw);
+}
+
+/**
+ * \brief Deinitialize sercom i2c module
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev)
+{
+	ASSERT(i2c_dev);
+
+	hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw);
+	hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable the i2c master module
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev)
+{
+	ASSERT(i2c_dev);
+
+	return _i2c_m_enable_implementation(i2c_dev->hw);
+}
+
+/**
+ * \brief Disable the i2c master module
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev)
+{
+	void *hw = i2c_dev->hw;
+
+	ASSERT(i2c_dev);
+	ASSERT(i2c_dev->hw);
+
+	hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set baudrate of master
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ * \param[in] clkrate The clock rate of i2c master, in KHz
+ * \param[in] baudrate The baud rate desired for i2c master, in KHz
+ */
+int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate)
+{
+	uint32_t tmp;
+	void *   hw = i2c_dev->hw;
+
+	if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) {
+		return ERR_DENIED;
+	}
+
+	tmp     = _get_i2cm_index(hw);
+	clkrate = _i2cms[tmp].clk / 1000;
+
+	if (i2c_dev->service.mode == I2C_STANDARD_MODE) {
+		tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001))
+		                 / (2 * baudrate));
+		hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp);
+	} else if (i2c_dev->service.mode == I2C_FASTMODE) {
+		tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001))
+		                 / (2 * baudrate));
+		hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp);
+	} else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) {
+		tmp = (clkrate - 2 * baudrate) / (2 * baudrate);
+		hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp);
+	} else {
+		/* error baudrate */
+		return ERR_INVALID_ARG;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable/disable I2C master interrupt
+ */
+void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type,
+                                const bool state)
+{
+	if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) {
+		hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state);
+		hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state);
+	} else if (I2C_M_ASYNC_DEVICE_ERROR == type) {
+		hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state);
+	}
+}
+
+/**
+ * \brief Wait for bus response
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ * \param[in] flags Store the hardware response
+ *
+ * \return Bus response status.
+ * \retval 0 Bus response status OK
+ * \retval <0 Bus response fail
+ */
+inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags)
+{
+	uint32_t timeout = 65535;
+	void *   hw      = i2c_dev->hw;
+
+	do {
+		*flags = hri_sercomi2cm_read_INTFLAG_reg(hw);
+
+		if (timeout-- == 0) {
+			return I2C_ERR_BUS;
+		}
+	} while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG));
+
+	return I2C_OK;
+}
+
+/**
+ * \brief Send the slave address to bus, which will start the transfer
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev)
+{
+	void *             hw    = i2c_dev->hw;
+	struct _i2c_m_msg *msg   = &i2c_dev->service.msg;
+	int                sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw);
+	uint32_t           flags;
+
+	ASSERT(i2c_dev);
+
+	if (msg->len == 1 && sclsm) {
+		hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw);
+	} else {
+		hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw);
+	}
+
+	/* ten bit address */
+	if (msg->addr & I2C_M_TEN) {
+		if (msg->flags & I2C_M_RD) {
+			msg->flags |= I2C_M_TEN;
+		}
+
+		hri_sercomi2cm_write_ADDR_reg(hw,
+		                              ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN
+		                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+	} else {
+		hri_sercomi2cm_write_ADDR_reg(hw,
+		                              ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0)
+		                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+	}
+
+	_sercom_i2c_sync_wait_bus(i2c_dev, &flags);
+	return _sercom_i2c_sync_analyse_flags(hw, flags, msg);
+}
+
+/**
+ * \brief Transfer data specified by msg
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ * \param[in] msg The pointer to i2c message
+ *
+ * \return Transfer status.
+ * \retval 0 Transfer success
+ * \retval <0 Transfer fail or partial fail, return the error code
+ */
+int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg)
+{
+	uint32_t flags;
+	int      ret;
+	void *   hw = i2c_dev->hw;
+
+	ASSERT(i2c_dev);
+	ASSERT(i2c_dev->hw);
+	ASSERT(msg);
+
+	if (i2c_dev->service.msg.flags & I2C_M_BUSY) {
+		return I2C_ERR_BUSY;
+	}
+
+	msg->flags |= I2C_M_BUSY;
+	i2c_dev->service.msg = *msg;
+	hri_sercomi2cm_set_CTRLB_SMEN_bit(hw);
+
+	ret = _sercom_i2c_sync_send_address(i2c_dev);
+
+	if (ret) {
+		i2c_dev->service.msg.flags &= ~I2C_M_BUSY;
+
+		return ret;
+	}
+
+	while (i2c_dev->service.msg.flags & I2C_M_BUSY) {
+		ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags);
+
+		if (ret) {
+			if (msg->flags & I2C_M_STOP) {
+				_sercom_i2c_send_stop(hw);
+			}
+
+			i2c_dev->service.msg.flags &= ~I2C_M_BUSY;
+
+			return ret;
+		}
+
+		ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg);
+	}
+
+	return ret;
+}
+
+int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev)
+{
+	void *hw = i2c_dev->hw;
+
+	_sercom_i2c_send_stop(hw);
+
+	return I2C_OK;
+}
+
+static inline int32_t _i2c_m_enable_implementation(void *const hw)
+{
+	int timeout         = 65535;
+	int timeout_attempt = 4;
+
+	ASSERT(hw);
+
+	/* Enable interrupts */
+	hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw);
+
+	while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) {
+		timeout--;
+
+		if (timeout <= 0) {
+			if (--timeout_attempt)
+				timeout = 65535;
+			else
+				return I2C_ERR_BUSY;
+			hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE));
+		}
+	}
+	return ERR_NONE;
+}
+
+static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw)
+{
+	uint8_t i = _get_i2cm_index(hw);
+
+	if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) {
+		uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk;
+		if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) {
+			hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw);
+			hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE);
+		}
+		hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode);
+	}
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+
+	hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a);
+	hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b);
+	hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud);
+
+	service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1);
+
+	service->trise = _i2cms[i].trise;
+
+	return ERR_NONE;
+}
+
+	/* SERCOM I2C slave */
+
+#ifndef CONF_SERCOM_0_I2CS_ENABLE
+#define CONF_SERCOM_0_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_1_I2CS_ENABLE
+#define CONF_SERCOM_1_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_2_I2CS_ENABLE
+#define CONF_SERCOM_2_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_3_I2CS_ENABLE
+#define CONF_SERCOM_3_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_4_I2CS_ENABLE
+#define CONF_SERCOM_4_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_5_I2CS_ENABLE
+#define CONF_SERCOM_5_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_6_I2CS_ENABLE
+#define CONF_SERCOM_6_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_7_I2CS_ENABLE
+#define CONF_SERCOM_7_I2CS_ENABLE 0
+#endif
+
+/** Amount of SERCOM that is used as I2C Slave. */
+#define SERCOM_I2CS_AMOUNT                                                                                             \
+	(CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE     \
+	 + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE)
+
+/**
+ * \brief Macro is used to fill I2C slave configuration structure based on
+ * its number
+ *
+ * \param[in] n The number of structures
+ */
+#define I2CS_CONFIGURATION(n)                                                                                          \
+	{                                                                                                                  \
+		n,                                                                                                             \
+		    SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)     \
+		        | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD)                                            \
+		        | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)                                  \
+		        | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos)                                        \
+		        | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos)                                        \
+		        | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos),                                 \
+		    SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \
+		    (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos)                                             \
+		        | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS)                                                \
+		        | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos)                                   \
+		        | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK)                                       \
+	}
+
+/**
+ * \brief Macro to check 10-bit addressing
+ */
+#define I2CS_7BIT_ADDRESSING_MASK 0x7F
+
+static int32_t     _i2c_s_init(void *const hw);
+static int8_t      _get_i2c_s_index(const void *const hw);
+static inline void _i2c_s_deinit(void *const hw);
+static int32_t     _i2c_s_set_address(void *const hw, const uint16_t address);
+
+/**
+ * \brief SERCOM I2C slave configuration type
+ */
+struct i2cs_configuration {
+	uint8_t                    number;
+	hri_sercomi2cs_ctrla_reg_t ctrl_a;
+	hri_sercomi2cs_ctrlb_reg_t ctrl_b;
+	hri_sercomi2cs_addr_reg_t  address;
+};
+
+#if SERCOM_I2CS_AMOUNT < 1
+/** Dummy array for compiling. */
+static struct i2cs_configuration _i2css[1] = {{0}};
+#else
+/**
+ * \brief Array of SERCOM I2C slave configurations
+ */
+static struct i2cs_configuration _i2css[] = {
+#if CONF_SERCOM_0_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(0),
+#endif
+#if CONF_SERCOM_1_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(1),
+#endif
+#if CONF_SERCOM_2_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(2),
+#endif
+#if CONF_SERCOM_3_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(3),
+#endif
+#if CONF_SERCOM_4_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(4),
+#endif
+#if CONF_SERCOM_5_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(5),
+#endif
+#if CONF_SERCOM_6_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(6),
+#endif
+#if CONF_SERCOM_7_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(7),
+#endif
+};
+#endif
+
+/**
+ * \brief Initialize synchronous I2C slave
+ */
+int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw)
+{
+	int32_t status;
+
+	ASSERT(device);
+
+	status = _i2c_s_init(hw);
+	if (status) {
+		return status;
+	}
+	device->hw = hw;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Initialize asynchronous I2C slave
+ */
+int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw)
+{
+	int32_t init_status;
+
+	ASSERT(device);
+
+	init_status = _i2c_s_init(hw);
+	if (init_status) {
+		return init_status;
+	}
+
+	device->hw = hw;
+	_sercom_init_irq_param(hw, (void *)device);
+	uint8_t irq = _sercom_get_irq_num(hw);
+	for (uint32_t i = 0; i < 4; i++) {
+		NVIC_DisableIRQ((IRQn_Type)irq);
+		NVIC_ClearPendingIRQ((IRQn_Type)irq);
+		NVIC_EnableIRQ((IRQn_Type)irq);
+		irq++;
+	}
+	// Enable Address Match and PREC interrupt by default.
+	hri_sercomi2cs_set_INTEN_AMATCH_bit(hw);
+	hri_sercomi2cs_set_INTEN_PREC_bit(hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinitialize synchronous I2C
+ */
+int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device)
+{
+	_i2c_s_deinit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinitialize asynchronous I2C
+ */
+int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device)
+{
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw));
+	_i2c_s_deinit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable I2C module
+ */
+int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device)
+{
+	hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable I2C module
+ */
+int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device)
+{
+	hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Disable I2C module
+ */
+int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device)
+{
+	hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Disable I2C module
+ */
+int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device)
+{
+	hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Check if 10-bit addressing mode is on
+ */
+int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device)
+{
+	return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw);
+}
+
+/**
+ * \brief Check if 10-bit addressing mode is on
+ */
+int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device)
+{
+	return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw);
+}
+
+/**
+ * \brief Set I2C slave address
+ */
+int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address)
+{
+	return _i2c_s_set_address(device->hw, address);
+}
+
+/**
+ * \brief Set I2C slave address
+ */
+int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address)
+{
+	return _i2c_s_set_address(device->hw, address);
+}
+
+/**
+ * \brief Write a byte to the given I2C instance
+ */
+void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data)
+{
+	hri_sercomi2cs_write_DATA_reg(device->hw, data);
+}
+
+/**
+ * \brief Write a byte to the given I2C instance
+ */
+void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data)
+{
+	hri_sercomi2cs_write_DATA_reg(device->hw, data);
+}
+
+/**
+ * \brief Read a byte from the given I2C instance
+ */
+uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device)
+{
+	return hri_sercomi2cs_read_DATA_reg(device->hw);
+}
+
+/**
+ * \brief Check if I2C is ready to send next byt
+ */
+bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device)
+{
+	return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw);
+}
+
+/**
+ * \brief Check if there is data received by I2C
+ */
+bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device)
+{
+	return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve I2C slave status
+ */
+i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device)
+{
+	return hri_sercomi2cs_read_STATUS_reg(device->hw);
+}
+
+/**
+ * \brief Clear the Data Ready interrupt flag
+ */
+int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device)
+{
+	hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve I2C slave status
+ */
+i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device)
+{
+	return hri_sercomi2cs_read_STATUS_reg(device->hw);
+}
+
+/**
+ * \brief Abort data transmission
+ */
+int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device)
+{
+	hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable/disable I2C slave interrupt
+ */
+int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type,
+                                   const bool state)
+{
+	ASSERT(device);
+
+	if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) {
+		hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state);
+	} else if (I2C_S_DEVICE_ERROR == type) {
+		hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state);
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \internal Initalize i2c slave hardware
+ *
+ * \param[in] p The pointer to hardware instance
+ *
+ *\ return status of initialization
+ */
+static int32_t _i2c_s_init(void *const hw)
+{
+	int8_t i = _get_i2c_s_index(hw);
+	if (i == -1) {
+		return ERR_INVALID_ARG;
+	}
+
+	if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) {
+		uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk;
+		if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) {
+			hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw);
+			hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE);
+		}
+		hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode);
+	}
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+
+	hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a);
+	hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b);
+	hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address);
+
+	return ERR_NONE;
+}
+
+/**
+ * \internal Retrieve ordinal number of the given sercom hardware instance
+ *
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return The ordinal number of the given sercom hardware instance
+ */
+static int8_t _get_i2c_s_index(const void *const hw)
+{
+	uint8_t sercom_offset = _sercom_get_hardware_index(hw);
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_i2css); i++) {
+		if (_i2css[i].number == sercom_offset) {
+			return i;
+		}
+	}
+
+	ASSERT(false);
+	return -1;
+}
+
+/**
+ * \internal De-initialize i2c slave
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+static inline void _i2c_s_deinit(void *const hw)
+{
+	hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw);
+	hri_sercomi2cs_set_CTRLA_SWRST_bit(hw);
+}
+
+/**
+ * \internal De-initialize i2c slave
+ *
+ * \param[in] hw The pointer to hardware instance
+ * \param[in] address Address to set
+ */
+static int32_t _i2c_s_set_address(void *const hw, const uint16_t address)
+{
+	bool enabled;
+
+	enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw);
+	hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address);
+	CRITICAL_SECTION_LEAVE()
+
+	if (enabled) {
+		hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw);
+	}
+
+	return ERR_NONE;
+}
+
+	/* Sercom SPI implementation */
+
+#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2)
+#endif
+
+#define SPI_DEV_IRQ_MODE 0x8000
+
+#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF)
+#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF)
+
+COMPILER_PACK_SET(1)
+/** Initialization configuration of registers. */
+struct sercomspi_regs_cfg {
+	uint32_t ctrla;
+	uint32_t ctrlb;
+	uint32_t addr;
+	uint8_t  baud;
+	uint8_t  dbgctrl;
+	uint16_t dummy_byte;
+	uint8_t  n;
+};
+COMPILER_PACK_RESET()
+
+/** Build configuration from header macros. */
+#define SERCOMSPI_REGS(n)                                                                                              \
+	{                                                                                                                  \
+		(((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos)                                                   \
+		 | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos)                                                   \
+		 | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos)                                                   \
+		 | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0))                      \
+		 | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO)       \
+		 | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos)                                                   \
+		 | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)                                           \
+		 | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */                                             \
+		    ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos)                                                 \
+		     | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos)                                             \
+		     | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos)                                               \
+		     | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos)                                         \
+		     | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE)                                                     \
+		     | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */                                     \
+		    (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR)                                                          \
+		     | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)),      /* addr */                              \
+		    ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE),                        /* baud */                              \
+		    (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */                           \
+		    CONF_SERCOM_##n##_SPI_DUMMYBYTE,                                   /* Dummy byte for SPI master mode */    \
+		    n                                                                  /* sercom number */                     \
+	}
+
+#ifndef CONF_SERCOM_0_SPI_ENABLE
+#define CONF_SERCOM_0_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_1_SPI_ENABLE
+#define CONF_SERCOM_1_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_2_SPI_ENABLE
+#define CONF_SERCOM_2_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_3_SPI_ENABLE
+#define CONF_SERCOM_3_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_4_SPI_ENABLE
+#define CONF_SERCOM_4_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_5_SPI_ENABLE
+#define CONF_SERCOM_5_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_6_SPI_ENABLE
+#define CONF_SERCOM_6_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_7_SPI_ENABLE
+#define CONF_SERCOM_7_SPI_ENABLE 0
+#endif
+
+/** Amount of SERCOM that is used as SPI */
+#define SERCOM_SPI_AMOUNT                                                                                              \
+	(CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE         \
+	 + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE)
+
+#if SERCOM_SPI_AMOUNT < 1
+/** Dummy array for compiling. */
+static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}};
+#else
+/** The SERCOM SPI configurations of SERCOM that is used as SPI. */
+static const struct sercomspi_regs_cfg sercomspi_regs[] = {
+#if CONF_SERCOM_0_SPI_ENABLE
+    SERCOMSPI_REGS(0),
+#endif
+#if CONF_SERCOM_1_SPI_ENABLE
+    SERCOMSPI_REGS(1),
+#endif
+#if CONF_SERCOM_2_SPI_ENABLE
+    SERCOMSPI_REGS(2),
+#endif
+#if CONF_SERCOM_3_SPI_ENABLE
+    SERCOMSPI_REGS(3),
+#endif
+#if CONF_SERCOM_4_SPI_ENABLE
+    SERCOMSPI_REGS(4),
+#endif
+#if CONF_SERCOM_5_SPI_ENABLE
+    SERCOMSPI_REGS(5),
+#endif
+#if CONF_SERCOM_6_SPI_ENABLE
+    SERCOMSPI_REGS(6),
+#endif
+#if CONF_SERCOM_7_SPI_ENABLE
+    SERCOMSPI_REGS(7),
+#endif
+};
+#endif
+
+/** \internal De-initialize SERCOM SPI
+ *
+ *  \param[in] hw Pointer to the hardware register base.
+ *
+ * \return De-initialization status
+ */
+static int32_t _spi_deinit(void *const hw)
+{
+	hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
+	hri_sercomspi_set_CTRLA_SWRST_bit(hw);
+
+	return ERR_NONE;
+}
+
+/** \internal Enable SERCOM SPI
+ *
+ *  \param[in] hw Pointer to the hardware register base.
+ *
+ * \return Enabling status
+ */
+static int32_t _spi_sync_enable(void *const hw)
+{
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
+		return ERR_BUSY;
+	}
+
+	hri_sercomspi_set_CTRLA_ENABLE_bit(hw);
+
+	return ERR_NONE;
+}
+
+/** \internal Enable SERCOM SPI
+ *
+ *  \param[in] hw Pointer to the hardware register base.
+ *
+ * \return Enabling status
+ */
+static int32_t _spi_async_enable(void *const hw)
+{
+	_spi_sync_enable(hw);
+	uint8_t irq = _sercom_get_irq_num(hw);
+	for (uint32_t i = 0; i < 4; i++) {
+		NVIC_EnableIRQ((IRQn_Type)irq++);
+	}
+
+	return ERR_NONE;
+}
+
+/** \internal Disable SERCOM SPI
+ *
+ *  \param[in] hw Pointer to the hardware register base.
+ *
+ * \return Disabling status
+ */
+static int32_t _spi_sync_disable(void *const hw)
+{
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
+		return ERR_BUSY;
+	}
+	hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
+
+	return ERR_NONE;
+}
+
+/** \internal Disable SERCOM SPI
+ *
+ *  \param[in] hw Pointer to the hardware register base.
+ *
+ * \return Disabling status
+ */
+static int32_t _spi_async_disable(void *const hw)
+{
+	_spi_sync_disable(hw);
+	hri_sercomspi_clear_INTEN_reg(
+	    hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE);
+	uint8_t irq = _sercom_get_irq_num(hw);
+	for (uint32_t i = 0; i < 4; i++) {
+		NVIC_DisableIRQ((IRQn_Type)irq++);
+	}
+
+	return ERR_NONE;
+}
+
+/** \internal Set SERCOM SPI mode
+ *
+ * \param[in] hw Pointer to the hardware register base.
+ * \param[in] mode The mode to set
+ *
+ * \return Setting mode status
+ */
+static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode)
+{
+	uint32_t ctrla;
+
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) {
+		return ERR_BUSY;
+	}
+
+	ctrla = hri_sercomspi_read_CTRLA_reg(hw);
+	ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA);
+	ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos;
+	hri_sercomspi_write_CTRLA_reg(hw, ctrla);
+
+	return ERR_NONE;
+}
+
+/** \internal Set SERCOM SPI baudrate
+ *
+ * \param[in] hw Pointer to the hardware register base.
+ * \param[in] baud_val The baudrate to set
+ *
+ * \return Setting baudrate status
+ */
+static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val)
+{
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
+		return ERR_BUSY;
+	}
+
+	hri_sercomspi_write_BAUD_reg(hw, baud_val);
+
+	return ERR_NONE;
+}
+
+/** \internal Set SERCOM SPI char size
+ *
+ * \param[in] hw Pointer to the hardware register base.
+ * \param[in] baud_val The baudrate to set
+ * \param[out] size Stored char size
+ *
+ * \return Setting char size status
+ */
+static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size)
+{
+	/* Only 8-bit or 9-bit accepted */
+	if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) {
+		return ERR_INVALID_ARG;
+	}
+
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) {
+		return ERR_BUSY;
+	}
+
+	hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size);
+	*size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2;
+
+	return ERR_NONE;
+}
+
+/** \internal Set SERCOM SPI data order
+ *
+ * \param[in] hw Pointer to the hardware register base.
+ * \param[in] baud_val The baudrate to set
+ *
+ * \return Setting data order status
+ */
+static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord)
+{
+	uint32_t ctrla;
+
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
+		return ERR_BUSY;
+	}
+
+	ctrla = hri_sercomspi_read_CTRLA_reg(hw);
+
+	if (dord == SPI_DATA_ORDER_LSB_1ST) {
+		ctrla |= SERCOM_SPI_CTRLA_DORD;
+	} else {
+		ctrla &= ~SERCOM_SPI_CTRLA_DORD;
+	}
+	hri_sercomspi_write_CTRLA_reg(hw, ctrla);
+
+	return ERR_NONE;
+}
+
+/** \brief Load SERCOM registers to init for SPI master mode
+ *  The settings will be applied with default master mode, unsupported things
+ *  are ignored.
+ *  \param[in, out] hw Pointer to the hardware register base.
+ *  \param[in] regs Pointer to register configuration values.
+ */
+static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs)
+{
+	ASSERT(hw && regs);
+	hri_sercomspi_write_CTRLA_reg(
+	    hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
+	hri_sercomspi_write_CTRLB_reg(
+	    hw,
+	    (regs->ctrlb
+	     & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN))
+	        | (SERCOM_SPI_CTRLB_RXEN));
+	hri_sercomspi_write_BAUD_reg(hw, regs->baud);
+	hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
+}
+
+/** \brief Load SERCOM registers to init for SPI slave mode
+ *  The settings will be applied with default slave mode, unsupported things
+ *  are ignored.
+ *  \param[in, out] hw Pointer to the hardware register base.
+ *  \param[in] regs Pointer to register configuration values.
+ */
+static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs)
+{
+	ASSERT(hw && regs);
+	hri_sercomspi_write_CTRLA_reg(
+	    hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
+	hri_sercomspi_write_CTRLB_reg(hw,
+	                              (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN))
+	                                  | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN));
+	hri_sercomspi_write_ADDR_reg(hw, regs->addr);
+	hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
+	while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF))
+		;
+}
+
+/** \brief Return the pointer to register settings of specific SERCOM
+ *  \param[in] hw_addr The hardware register base address.
+ *  \return Pointer to register settings of specific SERCOM.
+ */
+static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr)
+{
+	uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
+	uint8_t i;
+
+	for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) {
+		if (sercomspi_regs[i].n == n) {
+			return &sercomspi_regs[i];
+		}
+	}
+
+	return NULL;
+}
+
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM0_0_Handler(void)
+{
+	_sercom_i2c_m_irq_handler(_sercom0_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM0_1_Handler(void)
+{
+	_sercom_i2c_m_irq_handler(_sercom0_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM0_2_Handler(void)
+{
+	_sercom_i2c_m_irq_handler(_sercom0_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM0_3_Handler(void)
+{
+	_sercom_i2c_m_irq_handler(_sercom0_dev);
+}
+
+int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw)
+{
+	const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw);
+
+	ASSERT(dev && hw);
+
+	if (regs == NULL) {
+		return ERR_INVALID_ARG;
+	}
+
+	if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
+		uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
+		if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
+			hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
+			hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE);
+		}
+		hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode);
+	}
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+
+	dev->prvt = hw;
+
+	if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) {
+		_spi_load_regs_slave(hw, regs);
+	} else {
+		_spi_load_regs_master(hw, regs);
+	}
+
+	/* Load character size from default hardware configuration */
+	dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2;
+
+	dev->dummy_byte = regs->dummy_byte;
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw)
+{
+	return _spi_m_sync_init(dev, hw);
+}
+
+int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw)
+{
+	struct _spi_async_dev *spid = dev;
+	/* Do hardware initialize. */
+	int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw);
+
+	if (rc < 0) {
+		return rc;
+	}
+
+	_sercom_init_irq_param(hw, (void *)dev);
+	/* Initialize callbacks: must use them */
+	spid->callbacks.complete = NULL;
+	spid->callbacks.rx       = NULL;
+	spid->callbacks.tx       = NULL;
+	uint8_t irq              = _sercom_get_irq_num(hw);
+	for (uint32_t i = 0; i < 4; i++) {
+		NVIC_DisableIRQ((IRQn_Type)irq);
+		NVIC_ClearPendingIRQ((IRQn_Type)irq);
+		irq++;
+	}
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw)
+{
+	return _spi_m_async_init(dev, hw);
+}
+
+int32_t _spi_m_async_deinit(struct _spi_async_dev *dev)
+{
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt));
+	NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt));
+
+	return _spi_deinit(dev->prvt);
+}
+
+int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev)
+{
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt));
+	NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt));
+
+	return _spi_deinit(dev->prvt);
+}
+
+int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev)
+{
+	return _spi_deinit(dev->prvt);
+}
+
+int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev)
+{
+	return _spi_deinit(dev->prvt);
+}
+
+int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_sync_enable(dev->prvt);
+}
+
+int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_sync_enable(dev->prvt);
+}
+
+int32_t _spi_m_async_enable(struct _spi_async_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_async_enable(dev->prvt);
+}
+
+int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_async_enable(dev->prvt);
+}
+
+int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_sync_disable(dev->prvt);
+}
+
+int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_sync_disable(dev->prvt);
+}
+
+int32_t _spi_m_async_disable(struct _spi_async_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_async_disable(dev->prvt);
+}
+
+int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_async_disable(dev->prvt);
+}
+
+int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_mode(dev->prvt, mode);
+}
+
+int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_mode(dev->prvt, mode);
+}
+
+int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_mode(dev->prvt, mode);
+}
+
+int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_mode(dev->prvt, mode);
+}
+
+int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud)
+{
+	int32_t rc;
+	ASSERT(dev);
+
+	/* Not accept 0es */
+	if (clk == 0 || baud == 0) {
+		return ERR_INVALID_ARG;
+	}
+
+	/* Check baudrate range of current assigned clock */
+	if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) {
+		return ERR_INVALID_ARG;
+	}
+
+	rc = ((clk >> 1) / baud) - 1;
+	return rc;
+}
+
+int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_baudrate(dev->prvt, baud_val);
+}
+
+int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_baudrate(dev->prvt, baud_val);
+}
+
+int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_char_size(dev->prvt, char_size, &dev->char_size);
+}
+
+int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_char_size(dev->prvt, char_size, &dev->char_size);
+}
+
+int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_char_size(dev->prvt, char_size, &dev->char_size);
+}
+
+int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_char_size(dev->prvt, char_size, &dev->char_size);
+}
+
+int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_data_order(dev->prvt, dord);
+}
+
+int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_data_order(dev->prvt, dord);
+}
+
+int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_data_order(dev->prvt, dord);
+}
+
+int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_data_order(dev->prvt, dord);
+}
+
+/** Wait until SPI bus idle. */
+static inline void _spi_wait_bus_idle(void *const hw)
+{
+	while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) {
+		;
+	}
+	hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE);
+}
+
+/** Holds run time information for message sync transaction. */
+struct _spi_trans_ctrl {
+	/** Pointer to transmitting data buffer. */
+	uint8_t *txbuf;
+	/** Pointer to receiving data buffer. */
+	uint8_t *rxbuf;
+	/** Count number of data transmitted. */
+	uint32_t txcnt;
+	/** Count number of data received. */
+	uint32_t rxcnt;
+	/** Data character size. */
+	uint8_t char_size;
+};
+
+/** Check interrupt flag of RXC and update transaction runtime information. */
+static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl)
+{
+	uint32_t data;
+
+	if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) {
+		return false;
+	}
+
+	data = hri_sercomspi_read_DATA_reg(hw);
+
+	if (ctrl->rxbuf) {
+		*ctrl->rxbuf++ = (uint8_t)data;
+
+		if (ctrl->char_size > 1) {
+			*ctrl->rxbuf++ = (uint8_t)(data >> 8);
+		}
+	}
+
+	ctrl->rxcnt++;
+
+	return true;
+}
+
+/** Check interrupt flag of DRE and update transaction runtime information. */
+static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl,
+                                          uint16_t dummy)
+{
+	uint32_t data;
+
+	if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) {
+		return;
+	}
+
+	if (ctrl->txbuf) {
+		data = *ctrl->txbuf++;
+
+		if (ctrl->char_size > 1) {
+			data |= (*ctrl->txbuf) << 8;
+			ctrl->txbuf++;
+		}
+	} else {
+		data = dummy;
+	}
+
+	ctrl->txcnt++;
+	hri_sercomspi_write_DATA_reg(hw, data);
+}
+
+/** Check interrupt flag of ERROR and update transaction runtime information. */
+static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw)
+{
+	if (SERCOM_SPI_INTFLAG_ERROR & iflag) {
+		hri_sercomspi_clear_STATUS_reg(hw, ~0);
+		hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR);
+		return ERR_OVERFLOW;
+	}
+
+	return ERR_NONE;
+}
+
+int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg)
+{
+	void *                 hw   = dev->prvt;
+	int32_t                rc   = 0;
+	struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
+
+	ASSERT(dev && hw);
+
+	/* If settings are not applied (pending), we can not go on */
+	if (hri_sercomspi_is_syncing(
+	        hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) {
+		return ERR_BUSY;
+	}
+
+	/* SPI must be enabled to start synchronous transfer */
+	if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) {
+		return ERR_NOT_INITIALIZED;
+	}
+
+	for (;;) {
+		uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw);
+
+		if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) {
+			/* In master mode, do not start next byte before previous byte received
+			 * to make better output waveform */
+			if (ctrl.rxcnt >= ctrl.txcnt) {
+				_spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte);
+			}
+		}
+
+		rc = _spi_err_check(iflag, hw);
+
+		if (rc < 0) {
+			break;
+		}
+		if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) {
+			rc = ctrl.txcnt;
+			break;
+		}
+	}
+	/* Wait until SPI bus idle */
+	_spi_wait_bus_idle(hw);
+
+	return rc;
+}
+
+int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state)
+{
+	void *hw = dev->prvt;
+
+	ASSERT(dev && hw);
+
+	if (state) {
+		hri_sercomspi_set_INTEN_DRE_bit(hw);
+	} else {
+		hri_sercomspi_clear_INTEN_DRE_bit(hw);
+	}
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state)
+{
+	return _spi_m_async_enable_tx(dev, state);
+}
+
+int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state)
+{
+	void *hw = dev->prvt;
+
+	ASSERT(dev);
+	ASSERT(hw);
+
+	if (state) {
+		hri_sercomspi_set_INTEN_RXC_bit(hw);
+	} else {
+		hri_sercomspi_clear_INTEN_RXC_bit(hw);
+	}
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state)
+{
+	return _spi_m_async_enable_rx(dev, state);
+}
+
+int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state)
+{
+	ASSERT(dev && dev->prvt);
+
+	if (state) {
+		hri_sercomspi_set_INTEN_TXC_bit(dev->prvt);
+	} else {
+		hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt);
+	}
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state)
+{
+	return _spi_m_async_enable_tx_complete(dev, state);
+}
+
+int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data)
+{
+	ASSERT(dev && dev->prvt);
+
+	hri_sercomspi_write_DATA_reg(dev->prvt, data);
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data)
+{
+	ASSERT(dev && dev->prvt);
+
+	hri_sercomspi_write_DATA_reg(dev->prvt, data);
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data)
+{
+	ASSERT(dev && dev->prvt);
+
+	hri_sercomspi_write_DATA_reg(dev->prvt, data);
+
+	return ERR_NONE;
+}
+
+uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return hri_sercomspi_read_DATA_reg(dev->prvt);
+}
+
+uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return hri_sercomspi_read_DATA_reg(dev->prvt);
+}
+
+uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return hri_sercomspi_read_DATA_reg(dev->prvt);
+}
+
+int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type,
+                                       const FUNC_PTR func)
+{
+	typedef void (*func_t)(void);
+	struct _spi_async_dev *spid = dev;
+
+	ASSERT(dev && (cb_type < SPI_DEV_CB_N));
+
+	func_t *p_ls  = (func_t *)&spid->callbacks;
+	p_ls[cb_type] = (func_t)func;
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type,
+                                       const FUNC_PTR func)
+{
+	return _spi_m_async_register_callback(dev, cb_type, func);
+}
+
+bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE);
+}
+
+bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC);
+}
+
+bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev)
+{
+	void *hw = dev->prvt;
+
+	ASSERT(dev && hw);
+
+	if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) {
+		hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC);
+		return true;
+	}
+	return false;
+}
+
+bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev)
+{
+	void *hw = dev->prvt;
+
+	ASSERT(dev && hw);
+
+	if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) {
+		hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF);
+		hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR);
+		return true;
+	}
+	return false;
+}
+
+/**
+ * \brief Enable/disable SPI master interrupt
+ *
+ * param[in] device The pointer to SPI master device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] state Enable or disable
+ */
+void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type,
+                                const bool state)
+{
+	ASSERT(device);
+
+	if (SPI_DEV_CB_ERROR == type) {
+		hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state);
+	}
+}
+
+/**
+ * \brief Enable/disable SPI slave interrupt
+ *
+ * param[in] device The pointer to SPI slave device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] state Enable or disable
+ */
+void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type,
+                                const bool state)
+{
+	_spi_m_async_set_irq_state(device, type, state);
+}
+#ifndef CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_0_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_0_SPI_M_DMA_RX_CHANNEL 1
+#endif
+#ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 1
+#endif
+#ifndef CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL 1
+#endif
+#ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1
+#endif
+#ifndef CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL 1
+#endif
+#ifndef CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL 1
+#endif
+#ifndef CONF_SERCOM_6_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_6_SPI_M_DMA_TX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_6_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_6_SPI_M_DMA_RX_CHANNEL 1
+#endif
+#ifndef CONF_SERCOM_7_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_7_SPI_M_DMA_TX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_7_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_7_SPI_M_DMA_RX_CHANNEL 1
+#endif
+
+#ifndef CONF_SERCOM_0_SPI_RX_CHANNEL
+#define CONF_SERCOM_0_SPI_RX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_1_SPI_RX_CHANNEL
+#define CONF_SERCOM_1_SPI_RX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_2_SPI_RX_CHANNEL
+#define CONF_SERCOM_2_SPI_RX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_3_SPI_RX_CHANNEL
+#define CONF_SERCOM_3_SPI_RX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_4_SPI_RX_CHANNEL
+#define CONF_SERCOM_4_SPI_RX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_5_SPI_RX_CHANNEL
+#define CONF_SERCOM_5_SPI_RX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_6_SPI_RX_CHANNEL
+#define CONF_SERCOM_6_SPI_RX_CHANNEL 0
+#endif
+#ifndef CONF_SERCOM_7_SPI_RX_CHANNEL
+#define CONF_SERCOM_7_SPI_RX_CHANNEL 0
+#endif
+
+/** \internal Enable SERCOM SPI RX
+ *
+ *  \param[in] hw Pointer to the hardware register base.
+ *
+ * \return Enabling status
+ */
+static int32_t _spi_sync_rx_enable(void *const hw)
+{
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_CTRLB)) {
+		return ERR_BUSY;
+	}
+
+	hri_sercomspi_set_CTRLB_RXEN_bit(hw);
+
+	return ERR_NONE;
+}
+
+/** \internal Disable SERCOM SPI RX
+ *
+ *  \param[in] hw Pointer to the hardware register base.
+ *
+ * \return Disabling status
+ */
+static int32_t _spi_sync_rx_disable(void *const hw)
+{
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_CTRLB)) {
+		return ERR_BUSY;
+	}
+	hri_sercomspi_clear_CTRLB_RXEN_bit(hw);
+
+	return ERR_NONE;
+}
+
+static int32_t _spi_m_dma_rx_enable(struct _spi_m_dma_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_sync_rx_enable(dev->prvt);
+}
+
+static int32_t _spi_m_dma_rx_disable(struct _spi_m_dma_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_sync_rx_disable(dev->prvt);
+}
+
+/**
+ *  \brief Get the spi source address for DMA
+ *  \param[in] dev Pointer to the SPI device instance
+ *
+ *  \return The spi source address
+ */
+static uint32_t _spi_m_get_source_for_dma(void *const hw)
+{
+	return (uint32_t) & (((Sercom *)hw)->SPI.DATA);
+}
+
+/**
+ *  \brief Get the spi destination address for DMA
+ *  \param[in] dev Pointer to the SPI device instance
+ *
+ *  \return The spi destination address
+ */
+static uint32_t _spi_m_get_destination_for_dma(void *const hw)
+{
+	return (uint32_t) & (((Sercom *)hw)->SPI.DATA);
+}
+
+/**
+ *  \brief Return the SPI TX DMA channel index
+ *  \param[in] hw_addr The hardware register base address
+ *
+ *  \return SPI TX DMA channel index.
+ */
+static uint8_t _spi_get_tx_dma_channel(const void *const hw)
+{
+	uint8_t index = _sercom_get_hardware_index(hw);
+
+	switch (index) {
+	case 0:
+		return CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL;
+	case 1:
+		return CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL;
+	case 2:
+		return CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL;
+	case 3:
+		return CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL;
+	case 4:
+		return CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL;
+	case 5:
+		return CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL;
+	case 6:
+		return CONF_SERCOM_6_SPI_M_DMA_TX_CHANNEL;
+	case 7:
+		return CONF_SERCOM_7_SPI_M_DMA_TX_CHANNEL;
+	default:
+		return CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL;
+	}
+}
+
+/**
+ *  \brief Return whether SPI RX DMA channel is enabled or not
+ *  \param[in] hw_addr The hardware register base address
+ *
+ *  \return one if enabled.
+ */
+static uint8_t _spi_is_rx_dma_channel_enabled(const void *const hw)
+{
+	uint8_t index = _sercom_get_hardware_index(hw);
+
+	switch (index) {
+	case 0:
+		return CONF_SERCOM_0_SPI_RX_CHANNEL;
+	case 1:
+		return CONF_SERCOM_1_SPI_RX_CHANNEL;
+	case 2:
+		return CONF_SERCOM_2_SPI_RX_CHANNEL;
+	case 3:
+		return CONF_SERCOM_3_SPI_RX_CHANNEL;
+	case 4:
+		return CONF_SERCOM_4_SPI_RX_CHANNEL;
+	case 5:
+		return CONF_SERCOM_5_SPI_RX_CHANNEL;
+	case 6:
+		return CONF_SERCOM_6_SPI_RX_CHANNEL;
+	case 7:
+		return CONF_SERCOM_7_SPI_RX_CHANNEL;
+	default:
+		return false;
+	}
+}
+
+/**
+ *  \brief Return the SPI RX DMA channel index
+ *  \param[in] hw_addr The hardware register base address
+ *
+ *  \return SPI RX DMA channel index.
+ */
+static uint8_t _spi_get_rx_dma_channel(const void *const hw)
+{
+	uint8_t index = _sercom_get_hardware_index(hw);
+
+	switch (index) {
+	case 0:
+		return CONF_SERCOM_0_SPI_M_DMA_RX_CHANNEL;
+	case 1:
+		return CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL;
+	case 2:
+		return CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL;
+	case 3:
+		return CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL;
+	case 4:
+		return CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL;
+	case 5:
+		return CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL;
+	case 6:
+		return CONF_SERCOM_6_SPI_M_DMA_RX_CHANNEL;
+	case 7:
+		return CONF_SERCOM_7_SPI_M_DMA_RX_CHANNEL;
+	default:
+		return CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL;
+	}
+}
+
+/**
+ *  \brief Callback for RX
+ *  \param[in, out] dev Pointer to the DMA resource.
+ */
+static void _spi_dma_rx_complete(struct _dma_resource *resource)
+{
+	struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back;
+
+	if (dev->callbacks.rx) {
+		dev->callbacks.rx(resource);
+	}
+}
+
+/**
+ *  \brief Callback for TX
+ *  \param[in, out] dev Pointer to the DMA resource.
+ */
+static void _spi_dma_tx_complete(struct _dma_resource *resource)
+{
+	struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back;
+
+	if (dev->callbacks.tx) {
+		dev->callbacks.tx(resource);
+	}
+}
+
+/**
+ *  \brief Callback for ERROR
+ *  \param[in, out] dev Pointer to the DMA resource.
+ */
+static void _spi_dma_error_occured(struct _dma_resource *resource)
+{
+	struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back;
+
+	if (dev->callbacks.error) {
+		dev->callbacks.error(resource);
+	}
+}
+
+int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw)
+{
+	const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw);
+
+	ASSERT(dev && hw);
+
+	if (regs == NULL) {
+		return ERR_INVALID_ARG;
+	}
+
+	if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
+		uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
+		if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
+			hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
+			hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE);
+		}
+		hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode);
+	}
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+
+	dev->prvt = hw;
+
+	_spi_load_regs_master(hw, regs);
+
+	/* If enabled, initialize DMA rx channel */
+	if (_spi_is_rx_dma_channel_enabled(hw)) {
+		_dma_get_channel_resource(&dev->resource, _spi_get_rx_dma_channel(hw));
+		dev->resource->back                 = dev;
+		dev->resource->dma_cb.transfer_done = _spi_dma_rx_complete;
+		dev->resource->dma_cb.error         = _spi_dma_error_occured;
+	}
+	/* Initialize DMA tx channel */
+	_dma_get_channel_resource(&dev->resource, _spi_get_tx_dma_channel(hw));
+	dev->resource->back                 = dev;
+	dev->resource->dma_cb.transfer_done = _spi_dma_tx_complete;
+	dev->resource->dma_cb.error         = _spi_dma_error_occured;
+
+	return ERR_NONE;
+}
+
+int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev)
+{
+	return _spi_deinit(dev->prvt);
+}
+
+int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_sync_enable(dev->prvt);
+}
+
+int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_sync_disable(dev->prvt);
+}
+
+int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_mode(dev->prvt, mode);
+}
+
+int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_baudrate(dev->prvt, baud_val);
+}
+
+int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_data_order(dev->prvt, dord);
+}
+
+int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size)
+{
+	uint8_t size;
+
+	ASSERT(dev && dev->prvt);
+
+	_spi_set_char_size(dev->prvt, char_size, &size);
+
+	return size;
+}
+
+void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type type, _spi_dma_cb_t func)
+{
+	switch (type) {
+	case SPI_DEV_CB_DMA_TX:
+		dev->callbacks.tx = func;
+		_dma_set_irq_state(_spi_get_tx_dma_channel(dev->prvt), DMA_TRANSFER_COMPLETE_CB, func != NULL);
+		break;
+	case SPI_DEV_CB_DMA_RX:
+		dev->callbacks.rx = func;
+		_dma_set_irq_state(_spi_get_rx_dma_channel(dev->prvt), DMA_TRANSFER_COMPLETE_CB, func != NULL);
+		break;
+	case SPI_DEV_CB_DMA_ERROR:
+		dev->callbacks.error = func;
+		_dma_set_irq_state(_spi_get_rx_dma_channel(dev->prvt), DMA_TRANSFER_ERROR_CB, func != NULL);
+		_dma_set_irq_state(_spi_get_tx_dma_channel(dev->prvt), DMA_TRANSFER_ERROR_CB, func != NULL);
+		break;
+	case SPI_DEV_CB_DMA_N:
+		break;
+	}
+}
+
+int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf,
+                            const uint16_t length)
+{
+	const struct sercomspi_regs_cfg *regs  = _spi_get_regs((uint32_t)dev->prvt);
+	uint8_t                          rx_ch = _spi_get_rx_dma_channel(dev->prvt);
+	uint8_t                          tx_ch = _spi_get_tx_dma_channel(dev->prvt);
+
+	if (rxbuf) {
+		/* Enable spi rx */
+		_spi_m_dma_rx_enable(dev);
+		_dma_set_source_address(rx_ch, (void *)_spi_m_get_source_for_dma(dev->prvt));
+		_dma_set_destination_address(rx_ch, rxbuf);
+		_dma_set_data_amount(rx_ch, length);
+		_dma_enable_transaction(rx_ch, false);
+	} else {
+		/* Disable spi rx */
+		_spi_m_dma_rx_disable(dev);
+	}
+
+	if (txbuf) {
+		/* Enable spi tx */
+		_dma_set_source_address(tx_ch, txbuf);
+		_dma_set_destination_address(tx_ch, (void *)_spi_m_get_destination_for_dma(dev->prvt));
+		_dma_srcinc_enable(tx_ch, true);
+		_dma_set_data_amount(tx_ch, length);
+	} else {
+		_dma_set_source_address(tx_ch, &regs->dummy_byte);
+		_dma_set_destination_address(tx_ch, (void *)_spi_m_get_destination_for_dma(dev->prvt));
+		_dma_srcinc_enable(tx_ch, false);
+		_dma_set_data_amount(tx_ch, length);
+	}
+	_dma_enable_transaction(tx_ch, false);
+
+	return ERR_NONE;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tc/tc_lite.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tc/tc_lite.c
new file mode 100644
index 0000000..736464a
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tc/tc_lite.c
@@ -0,0 +1,309 @@
+
+/**
+ * \file
+ *
+ * \brief TC related functionality implementation.
+ *
+ * Copyright (c) 2017 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "tc_lite.h"
+
+/**
+ * \brief Initialize TC interface
+ */
+int8_t TIMER_0_init()
+{
+
+	if (!hri_tc_is_syncing(TC0, TC_SYNCBUSY_SWRST)) {
+		if (hri_tc_get_CTRLA_reg(TC0, TC_CTRLA_ENABLE)) {
+			hri_tc_clear_CTRLA_ENABLE_bit(TC0);
+			hri_tc_wait_for_sync(TC0, TC_SYNCBUSY_ENABLE);
+		}
+		hri_tc_write_CTRLA_reg(TC0, TC_CTRLA_SWRST);
+	}
+	hri_tc_wait_for_sync(TC0, TC_SYNCBUSY_SWRST);
+
+	hri_tc_write_CTRLA_reg(TC0,
+	                       0 << TC_CTRLA_CAPTMODE0_Pos       /* Capture mode Channel 0: 0 */
+	                           | 0 << TC_CTRLA_CAPTMODE1_Pos /* Capture mode Channel 1: 0 */
+	                           | 0 << TC_CTRLA_COPEN0_Pos    /* Capture Pin 0 Enable: disabled */
+	                           | 0 << TC_CTRLA_COPEN1_Pos    /* Capture Pin 1 Enable: disabled */
+	                           | 0 << TC_CTRLA_CAPTEN0_Pos   /* Capture Channel 0 Enable: disabled */
+	                           | 0 << TC_CTRLA_CAPTEN1_Pos   /* Capture Channel 1 Enable: disabled */
+	                           | 0 << TC_CTRLA_ALOCK_Pos     /* Auto Lock: disabled */
+	                           | 0 << TC_CTRLA_PRESCSYNC_Pos /* Prescaler and Counter Synchronization: 0 */
+	                           | 0 << TC_CTRLA_ONDEMAND_Pos  /* Clock On Demand: disabled */
+	                           | 0 << TC_CTRLA_RUNSTDBY_Pos  /* Run in Standby: disabled */
+	                           | 3 << TC_CTRLA_PRESCALER_Pos /* Setting: 3 */
+	                           | 0x1 << TC_CTRLA_MODE_Pos);  /* Operating Mode: 0x1 */
+
+	hri_tc_write_CTRLB_reg(TC0,
+	                       0 << TC_CTRLBSET_CMD_Pos           /* Command: 0 */
+	                           | 0 << TC_CTRLBSET_ONESHOT_Pos /* One-Shot: disabled */
+	                           | 0 << TC_CTRLBCLR_LUPD_Pos    /* Setting: disabled */
+	                           | 0 << TC_CTRLBSET_DIR_Pos);   /* Counter Direction: disabled */
+
+	// hri_tc_write_WAVE_reg(TC0,0); /* Waveform Generation Mode: 0 */
+
+	// hri_tc_write_DRVCTRL_reg(TC0,0 << TC_DRVCTRL_INVEN1_Pos /* Output Waveform 1 Invert Enable: disabled */
+	//		 | 0 << TC_DRVCTRL_INVEN0_Pos); /* Output Waveform 0 Invert Enable: disabled */
+
+	// hri_tc_write_DBGCTRL_reg(TC0,0); /* Run in debug: 0 */
+
+	hri_tccount8_write_CC_reg(TC0, 0, 0xa); /* Compare/Capture Value: 0xa */
+
+	hri_tccount8_write_CC_reg(TC0, 1, 0x80); /* Compare/Capture Value: 0x3c */
+
+	// hri_tccount8_write_COUNT_reg(TC0,0x0); /* Counter Value: 0x0 */
+
+	hri_tc_write_PER_reg(TC0, 0xfa); /* Period Value: 0xfa */
+
+	hri_tc_write_EVCTRL_reg(TC0,
+	                        1 << TC_EVCTRL_MCEO0_Pos       /* Match or Capture Channel 0 Event Output Enable: enabled */
+	                            | 1 << TC_EVCTRL_MCEO1_Pos /* Match or Capture Channel 1 Event Output Enable: enabled */
+	                            | 0 << TC_EVCTRL_OVFEO_Pos /* Overflow/Underflow Event Output Enable: disabled */
+	                            | 0 << TC_EVCTRL_TCEI_Pos  /* TC Event Input: disabled */
+	                            | 0 << TC_EVCTRL_TCINV_Pos /* TC Inverted Event Input: disabled */
+	                            | 0);                      /* Event Action: 0 */
+
+	hri_tc_write_INTEN_reg(TC0,
+	                       0 << TC_INTENSET_MC0_Pos         /* Match or Capture Channel 0 Interrupt Enable: disabled */
+	                           | 0 << TC_INTENSET_MC1_Pos   /* Match or Capture Channel 1 Interrupt Enable: disabled */
+	                           | 0 << TC_INTENSET_ERR_Pos   /* Error Interrupt Enable: disabled */
+	                           | 1 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: enabled */
+
+	hri_tc_write_CTRLA_ENABLE_bit(TC0, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */
+
+	return 0;
+}
+
+/**
+ * \brief Initialize TC interface
+ */
+int8_t TIMER_SPARE_init()
+{
+
+	if (!hri_tc_is_syncing(TC1, TC_SYNCBUSY_SWRST)) {
+		if (hri_tc_get_CTRLA_reg(TC1, TC_CTRLA_ENABLE)) {
+			hri_tc_clear_CTRLA_ENABLE_bit(TC1);
+			hri_tc_wait_for_sync(TC1, TC_SYNCBUSY_ENABLE);
+		}
+		hri_tc_write_CTRLA_reg(TC1, TC_CTRLA_SWRST);
+	}
+	hri_tc_wait_for_sync(TC1, TC_SYNCBUSY_SWRST);
+
+	hri_tc_write_CTRLA_reg(TC1,
+	                       0 << TC_CTRLA_CAPTMODE0_Pos       /* Capture mode Channel 0: 0 */
+	                           | 0 << TC_CTRLA_CAPTMODE1_Pos /* Capture mode Channel 1: 0 */
+	                           | 0 << TC_CTRLA_COPEN0_Pos    /* Capture Pin 0 Enable: disabled */
+	                           | 0 << TC_CTRLA_COPEN1_Pos    /* Capture Pin 1 Enable: disabled */
+	                           | 0 << TC_CTRLA_CAPTEN0_Pos   /* Capture Channel 0 Enable: disabled */
+	                           | 0 << TC_CTRLA_CAPTEN1_Pos   /* Capture Channel 1 Enable: disabled */
+	                           | 0 << TC_CTRLA_ALOCK_Pos     /* Auto Lock: disabled */
+	                           | 0 << TC_CTRLA_PRESCSYNC_Pos /* Prescaler and Counter Synchronization: 0 */
+	                           | 0 << TC_CTRLA_ONDEMAND_Pos  /* Clock On Demand: disabled */
+	                           | 0 << TC_CTRLA_RUNSTDBY_Pos  /* Run in Standby: disabled */
+	                           | 2 << TC_CTRLA_PRESCALER_Pos /* Setting: 2 */
+	                           | 0x1 << TC_CTRLA_MODE_Pos);  /* Operating Mode: 0x1 */
+
+	hri_tc_write_CTRLB_reg(TC1,
+	                       0 << TC_CTRLBSET_CMD_Pos           /* Command: 0 */
+	                           | 0 << TC_CTRLBSET_ONESHOT_Pos /* One-Shot: disabled */
+	                           | 0 << TC_CTRLBCLR_LUPD_Pos    /* Setting: disabled */
+	                           | 0 << TC_CTRLBSET_DIR_Pos);   /* Counter Direction: disabled */
+
+	// hri_tc_write_WAVE_reg(TC1,0); /* Waveform Generation Mode: 0 */
+
+	// hri_tc_write_DRVCTRL_reg(TC1,0 << TC_DRVCTRL_INVEN1_Pos /* Output Waveform 1 Invert Enable: disabled */
+	//		 | 0 << TC_DRVCTRL_INVEN0_Pos); /* Output Waveform 0 Invert Enable: disabled */
+
+	// hri_tc_write_DBGCTRL_reg(TC1,0); /* Run in debug: 0 */
+
+	hri_tccount8_write_CC_reg(TC1, 0, 0xa); /* Compare/Capture Value: 0xa */
+
+	hri_tccount8_write_CC_reg(TC1, 1, 0x3c); /* Compare/Capture Value: 0x3c */
+
+	// hri_tccount8_write_COUNT_reg(TC1,0x0); /* Counter Value: 0x0 */
+
+	hri_tc_write_PER_reg(TC1, 0xfa); /* Period Value: 0xfa */
+
+	hri_tc_write_EVCTRL_reg(TC1,
+	                        1 << TC_EVCTRL_MCEO0_Pos       /* Match or Capture Channel 0 Event Output Enable: enabled */
+	                            | 1 << TC_EVCTRL_MCEO1_Pos /* Match or Capture Channel 1 Event Output Enable: enabled */
+	                            | 1 << TC_EVCTRL_OVFEO_Pos /* Overflow/Underflow Event Output Enable: enabled */
+	                            | 0 << TC_EVCTRL_TCEI_Pos  /* TC Event Input: disabled */
+	                            | 0 << TC_EVCTRL_TCINV_Pos /* TC Inverted Event Input: disabled */
+	                            | 0);                      /* Event Action: 0 */
+
+	hri_tc_write_INTEN_reg(TC1,
+	                       0 << TC_INTENSET_MC0_Pos         /* Match or Capture Channel 0 Interrupt Enable: disabled */
+	                           | 1 << TC_INTENSET_MC1_Pos   /* Match or Capture Channel 1 Interrupt Enable: enabled */
+	                           | 0 << TC_INTENSET_ERR_Pos   /* Error Interrupt Enable: disabled */
+	                           | 1 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: enabled */
+
+	// hri_tc_write_CTRLA_ENABLE_bit(TC1,0 << TC_CTRLA_ENABLE_Pos); /* Enable: disabled */
+
+	return 0;
+}
+
+/**
+ * \brief Initialize TC interface
+ */
+int8_t TC_SPEED_M1_init()
+{
+
+	if (!hri_tc_is_syncing(TC2, TC_SYNCBUSY_SWRST)) {
+		if (hri_tc_get_CTRLA_reg(TC2, TC_CTRLA_ENABLE)) {
+			hri_tc_clear_CTRLA_ENABLE_bit(TC2);
+			hri_tc_wait_for_sync(TC2, TC_SYNCBUSY_ENABLE);
+		}
+		hri_tc_write_CTRLA_reg(TC2, TC_CTRLA_SWRST);
+	}
+	hri_tc_wait_for_sync(TC2, TC_SYNCBUSY_SWRST);
+
+	hri_tc_write_CTRLA_reg(TC2,
+	                       0 << TC_CTRLA_CAPTMODE0_Pos       /* Capture mode Channel 0: 0 */
+	                           | 0 << TC_CTRLA_CAPTMODE1_Pos /* Capture mode Channel 1: 0 */
+	                           | 0 << TC_CTRLA_COPEN0_Pos    /* Capture Pin 0 Enable: disabled */
+	                           | 0 << TC_CTRLA_COPEN1_Pos    /* Capture Pin 1 Enable: disabled */
+	                           | 1 << TC_CTRLA_CAPTEN0_Pos   /* Capture Channel 0 Enable: enabled */
+	                           | 1 << TC_CTRLA_CAPTEN1_Pos   /* Capture Channel 1 Enable: enabled */
+	                           | 0 << TC_CTRLA_ALOCK_Pos     /* Auto Lock: disabled */
+	                           | 0 << TC_CTRLA_PRESCSYNC_Pos /* Prescaler and Counter Synchronization: 0 */
+	                           | 0 << TC_CTRLA_ONDEMAND_Pos  /* Clock On Demand: disabled */
+	                           | 0 << TC_CTRLA_RUNSTDBY_Pos  /* Run in Standby: disabled */
+	                           | 2 << TC_CTRLA_PRESCALER_Pos /* Setting: 2 */
+	                           | 0x2 << TC_CTRLA_MODE_Pos);  /* Operating Mode: 0x2 */
+
+	hri_tc_write_CTRLB_reg(TC2,
+	                       0 << TC_CTRLBSET_CMD_Pos           /* Command: 0 */
+	                           | 0 << TC_CTRLBSET_ONESHOT_Pos /* One-Shot: disabled */
+	                           | 0 << TC_CTRLBCLR_LUPD_Pos    /* Setting: disabled */
+	                           | 0 << TC_CTRLBSET_DIR_Pos);   /* Counter Direction: disabled */
+
+	// hri_tc_write_WAVE_reg(TC2,0); /* Waveform Generation Mode: 0 */
+
+	// hri_tc_write_DRVCTRL_reg(TC2,0 << TC_DRVCTRL_INVEN1_Pos /* Output Waveform 1 Invert Enable: disabled */
+	//		 | 0 << TC_DRVCTRL_INVEN0_Pos); /* Output Waveform 0 Invert Enable: disabled */
+
+	// hri_tc_write_DBGCTRL_reg(TC2,0); /* Run in debug: 0 */
+
+	// hri_tccount32_write_CC_reg(TC2, 0 ,0x0); /* Compare/Capture Value: 0x0 */
+
+	// hri_tccount32_write_CC_reg(TC2, 1 ,0x0); /* Compare/Capture Value: 0x0 */
+
+	// hri_tccount32_write_COUNT_reg(TC2,0x0); /* Counter Value: 0x0 */
+
+	hri_tc_write_EVCTRL_reg(
+	    TC2,
+	    0 << TC_EVCTRL_MCEO0_Pos       /* Match or Capture Channel 0 Event Output Enable: disabled */
+	        | 0 << TC_EVCTRL_MCEO1_Pos /* Match or Capture Channel 1 Event Output Enable: disabled */
+	        | 1 << TC_EVCTRL_OVFEO_Pos /* Overflow/Underflow Event Output Enable: enabled */
+	        | 1 << TC_EVCTRL_TCEI_Pos  /* TC Event Input: enabled */
+	        | 0 << TC_EVCTRL_TCINV_Pos /* TC Inverted Event Input: disabled */
+	        | 5);                      /* Event Action: 5 */
+
+	hri_tc_write_INTEN_reg(TC2,
+	                       0 << TC_INTENSET_MC0_Pos         /* Match or Capture Channel 0 Interrupt Enable: disabled */
+	                           | 0 << TC_INTENSET_MC1_Pos   /* Match or Capture Channel 1 Interrupt Enable: disabled */
+	                           | 0 << TC_INTENSET_ERR_Pos   /* Error Interrupt Enable: disabled */
+	                           | 1 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: enabled */
+
+	hri_tc_write_CTRLA_ENABLE_bit(TC2, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */
+
+	return 0;
+}
+
+/**
+ * \brief Initialize TC interface
+ */
+int8_t TC_SPEED_M2_init()
+{
+
+	if (!hri_tc_is_syncing(TC4, TC_SYNCBUSY_SWRST)) {
+		if (hri_tc_get_CTRLA_reg(TC4, TC_CTRLA_ENABLE)) {
+			hri_tc_clear_CTRLA_ENABLE_bit(TC4);
+			hri_tc_wait_for_sync(TC4, TC_SYNCBUSY_ENABLE);
+		}
+		hri_tc_write_CTRLA_reg(TC4, TC_CTRLA_SWRST);
+	}
+	hri_tc_wait_for_sync(TC4, TC_SYNCBUSY_SWRST);
+
+	hri_tc_write_CTRLA_reg(TC4,
+	                       0 << TC_CTRLA_CAPTMODE0_Pos       /* Capture mode Channel 0: 0 */
+	                           | 0 << TC_CTRLA_CAPTMODE1_Pos /* Capture mode Channel 1: 0 */
+	                           | 0 << TC_CTRLA_COPEN0_Pos    /* Capture Pin 0 Enable: disabled */
+	                           | 0 << TC_CTRLA_COPEN1_Pos    /* Capture Pin 1 Enable: disabled */
+	                           | 1 << TC_CTRLA_CAPTEN0_Pos   /* Capture Channel 0 Enable: enabled */
+	                           | 1 << TC_CTRLA_CAPTEN1_Pos   /* Capture Channel 1 Enable: enabled */
+	                           | 0 << TC_CTRLA_ALOCK_Pos     /* Auto Lock: disabled */
+	                           | 0 << TC_CTRLA_PRESCSYNC_Pos /* Prescaler and Counter Synchronization: 0 */
+	                           | 0 << TC_CTRLA_ONDEMAND_Pos  /* Clock On Demand: disabled */
+	                           | 0 << TC_CTRLA_RUNSTDBY_Pos  /* Run in Standby: disabled */
+	                           | 2 << TC_CTRLA_PRESCALER_Pos /* Setting: 2 */
+	                           | 0x2 << TC_CTRLA_MODE_Pos);  /* Operating Mode: 0x2 */
+
+	hri_tc_write_CTRLB_reg(TC4,
+	                       0 << TC_CTRLBSET_CMD_Pos           /* Command: 0 */
+	                           | 0 << TC_CTRLBSET_ONESHOT_Pos /* One-Shot: disabled */
+	                           | 0 << TC_CTRLBCLR_LUPD_Pos    /* Setting: disabled */
+	                           | 0 << TC_CTRLBSET_DIR_Pos);   /* Counter Direction: disabled */
+
+	// hri_tc_write_WAVE_reg(TC4,0); /* Waveform Generation Mode: 0 */
+
+	// hri_tc_write_DRVCTRL_reg(TC4,0 << TC_DRVCTRL_INVEN1_Pos /* Output Waveform 1 Invert Enable: disabled */
+	//		 | 0 << TC_DRVCTRL_INVEN0_Pos); /* Output Waveform 0 Invert Enable: disabled */
+
+	// hri_tc_write_DBGCTRL_reg(TC4,0); /* Run in debug: 0 */
+
+	// hri_tccount32_write_CC_reg(TC4, 0 ,0x0); /* Compare/Capture Value: 0x0 */
+
+	// hri_tccount32_write_CC_reg(TC4, 1 ,0x0); /* Compare/Capture Value: 0x0 */
+
+	// hri_tccount32_write_COUNT_reg(TC4,0x0); /* Counter Value: 0x0 */
+
+	hri_tc_write_EVCTRL_reg(
+	    TC4,
+	    0 << TC_EVCTRL_MCEO0_Pos       /* Match or Capture Channel 0 Event Output Enable: disabled */
+	        | 0 << TC_EVCTRL_MCEO1_Pos /* Match or Capture Channel 1 Event Output Enable: disabled */
+	        | 1 << TC_EVCTRL_OVFEO_Pos /* Overflow/Underflow Event Output Enable: enabled */
+	        | 1 << TC_EVCTRL_TCEI_Pos  /* TC Event Input: enabled */
+	        | 0 << TC_EVCTRL_TCINV_Pos /* TC Inverted Event Input: disabled */
+	        | 5);                      /* Event Action: 5 */
+
+	hri_tc_write_INTEN_reg(TC4,
+	                       0 << TC_INTENSET_MC0_Pos         /* Match or Capture Channel 0 Interrupt Enable: disabled */
+	                           | 0 << TC_INTENSET_MC1_Pos   /* Match or Capture Channel 1 Interrupt Enable: disabled */
+	                           | 0 << TC_INTENSET_ERR_Pos   /* Error Interrupt Enable: disabled */
+	                           | 1 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: enabled */
+
+	hri_tc_write_CTRLA_ENABLE_bit(TC4, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */
+
+	return 0;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tc/tc_lite.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tc/tc_lite.h
new file mode 100644
index 0000000..582cc4e
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tc/tc_lite.h
@@ -0,0 +1,82 @@
+
+/**
+ * \file
+ *
+ * \brief TC related functionality declaration.
+ *
+ * Copyright (c) 2017 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _TC_H_INCLUDED
+#define _TC_H_INCLUDED
+
+#include <compiler.h>
+#include <utils_assert.h>
+
+/**
+ * \addtogroup tc driver
+ *
+ * \section tc Revision History
+ * - v0.0.0.1 Initial Commit
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Initialize tc interface
+ * \return Initialization status.
+ */
+int8_t TIMER_0_init();
+
+/**
+ * \brief Initialize tc interface
+ * \return Initialization status.
+ */
+int8_t TIMER_SPARE_init();
+
+/**
+ * \brief Initialize tc interface
+ * \return Initialization status.
+ */
+int8_t TC_SPEED_M1_init();
+
+/**
+ * \brief Initialize tc interface
+ * \return Initialization status.
+ */
+int8_t TC_SPEED_M2_init();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TC_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tcc/hpl_tcc.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tcc/hpl_tcc.c
new file mode 100644
index 0000000..eafcced
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tcc/hpl_tcc.c
@@ -0,0 +1,394 @@
+/**
+ * \file
+ *
+ * \brief SAM TCC
+ *
+ * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <compiler.h>
+#include <hpl_pwm.h>
+#include <hpl_tcc.h>
+#include <hpl_tcc_config.h>
+#include <hpl_timer.h>
+#include <utils.h>
+#include <utils_assert.h>
+
+/**
+ * \brief TCC configuration type
+ */
+struct tcc_cfg {
+	void *                 hw; /*!< instance of TCC */
+	IRQn_Type              irq;
+	hri_tcc_ctrla_reg_t    ctrl_a;
+	hri_tcc_ctrlbset_reg_t ctrl_b;
+	hri_tcc_dbgctrl_reg_t  dbg_ctrl;
+	hri_tcc_evctrl_reg_t   event_ctrl;
+	hri_tcc_cc_reg_t       cc0;
+	hri_tcc_cc_reg_t       cc1;
+	hri_tcc_cc_reg_t       cc2;
+	hri_tcc_cc_reg_t       cc3;
+	hri_tcc_cc_reg_t       cc4;
+	hri_tcc_cc_reg_t       cc5;
+	hri_tcc_per_reg_t      per;
+};
+/**
+ * \brief pwm configuration type
+ */
+struct tcc_pwm_cfg {
+	void *    hw; /*!< instance of TCC */
+	IRQn_Type irq;
+	uint8_t   sel_ch;
+	uint32_t  period;
+	uint32_t  duty_cycle;
+	uint32_t  wave;
+};
+
+/**
+ * \internal Retrieve configuration
+ *
+ * \param[in] hw The pointer of TCC base address
+ *
+ * \return The configuration
+ */
+static struct tcc_cfg *_get_tcc_cfg(void *hw);
+
+/**
+ * \brief Array of TCC configurations
+ */
+static struct tcc_cfg _cfgs[2] = {
+    {(void *)TCC0,
+     TCC0_0_IRQn,
+     CONF_TCC0_CTRLA,
+     CONF_TCC0_CTRLB,
+     CONF_TCC0_DBGCTRL,
+     CONF_TCC0_EVCTRL,
+     CONF_TCC0_CC0,
+     CONF_TCC0_CC1,
+     CONF_TCC0_CC2,
+     CONF_TCC0_CC3,
+     CONF_TCC0_CC4,
+     CONF_TCC0_CC5,
+     CONF_TCC0_PER},
+
+    {(void *)TCC1,
+     TCC1_0_IRQn,
+     CONF_TCC1_CTRLA,
+     CONF_TCC1_CTRLB,
+     CONF_TCC1_DBGCTRL,
+     CONF_TCC1_EVCTRL,
+     CONF_TCC1_CC0,
+     CONF_TCC1_CC1,
+     CONF_TCC1_CC2,
+     CONF_TCC1_CC3,
+     0,
+     0,
+     CONF_TCC1_PER},
+};
+
+/**
+ * \internal Retrieve configuration
+ *
+ * \param[in] hw The pointer of TCC base address
+ *
+ * \return The configuration
+ */
+static struct tcc_pwm_cfg *_get_tcc_pwm_cfg(void *hw);
+
+/**
+ * \brief Array of PWM configurations
+ */
+static struct tcc_pwm_cfg _cfgs_pwm[2] = {
+    {(void *)TCC0,
+     TCC0_0_IRQn,
+     CONF_TCC0_SEL_CH,
+     CONF_TCC0_PER_REG,
+     CONF_TCC0_CCX_REG,
+     (CONF_TCC0_WAVEGEN << TCC_WAVE_WAVEGEN_Pos)},
+    {(void *)TCC1,
+     TCC1_0_IRQn,
+     CONF_TCC1_SEL_CH,
+     CONF_TCC1_PER_REG,
+     CONF_TCC1_CCX_REG,
+     (CONF_TCC1_WAVEGEN << TCC_WAVE_WAVEGEN_Pos)},
+};
+/* Renamed access REG name PERB -> PERBUF */
+#define hri_tcc_write_PERB_reg hri_tcc_write_PERBUF_reg
+#define hri_tcc_read_PERB_reg hri_tcc_read_PERBUF_reg
+
+/** Renamed access REG name CCB -> CCBUF */
+#define hri_tcc_write_CCB_reg hri_tcc_write_CCBUF_reg
+#define hri_tcc_read_CCB_reg hri_tcc_read_CCBUF_reg
+
+static struct _pwm_device *_tcc0_dev = NULL;
+
+static struct _pwm_device *_tcc1_dev = NULL;
+
+/**
+ * \brief Init irq param with the given tcc hardware instance
+ */
+static void _tcc_init_irq_param(const void *const hw, void *dev)
+{
+	if (hw == TCC0) {
+		_tcc0_dev = (struct _pwm_device *)dev;
+	}
+	if (hw == TCC1) {
+		_tcc1_dev = (struct _pwm_device *)dev;
+	}
+}
+/**
+ * \brief Initialize TCC for PWM mode
+ */
+int32_t _pwm_init(struct _pwm_device *const device, void *const hw)
+{
+	struct tcc_cfg *cfg = _get_tcc_cfg(hw);
+	if (cfg == NULL) {
+		return ERR_NOT_FOUND;
+	}
+	struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
+	if (cfg_pwm == NULL) {
+		return ERR_NOT_FOUND;
+	}
+
+	device->hw = hw;
+
+	if (!hri_tcc_is_syncing(hw, TCC_SYNCBUSY_SWRST)) {
+		if (hri_tcc_get_CTRLA_reg(hw, TCC_CTRLA_ENABLE)) {
+			hri_tcc_clear_CTRLA_ENABLE_bit(hw);
+			hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_ENABLE);
+		}
+		hri_tcc_write_CTRLA_reg(hw, TCC_CTRLA_SWRST);
+	}
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+
+	hri_tcc_write_CTRLA_reg(hw, cfg->ctrl_a);
+	hri_tcc_set_CTRLB_reg(hw, cfg->ctrl_b);
+	hri_tcc_write_DBGCTRL_reg(hw, cfg->dbg_ctrl);
+	hri_tcc_write_EVCTRL_reg(hw, cfg->event_ctrl);
+
+	hri_tcc_write_WAVE_reg(hw, cfg_pwm->wave);
+	hri_tcc_write_PER_reg(hw, cfg_pwm->period);
+	cfg->per = cfg_pwm->period;
+	switch (cfg_pwm->sel_ch) {
+	case 0:
+		cfg->cc0 = cfg_pwm->duty_cycle;
+		hri_tcc_write_CC_reg(hw, 0, cfg->cc0);
+		break;
+	case 1:
+		cfg->cc1 = cfg_pwm->duty_cycle;
+		hri_tcc_write_CC_reg(hw, 1, cfg->cc1);
+		break;
+	case 2:
+		cfg->cc2 = cfg_pwm->duty_cycle;
+		hri_tcc_write_CC_reg(hw, 2, cfg->cc2);
+		break;
+	case 3:
+		cfg->cc3 = cfg_pwm->duty_cycle;
+		hri_tcc_write_CC_reg(hw, 3, cfg->cc3);
+		break;
+	case 4:
+		cfg->cc4 = cfg_pwm->duty_cycle;
+		hri_tcc_write_CC_reg(hw, 4, cfg->cc4);
+		break;
+	case 5:
+		cfg->cc5 = cfg_pwm->duty_cycle;
+		hri_tcc_write_CC_reg(hw, 5, cfg->cc5);
+		break;
+	default:
+		return ERR_NO_RESOURCE;
+		break;
+	}
+	hri_tcc_clear_CTRLB_LUPD_bit(hw);
+
+	_tcc_init_irq_param(hw, (void *)device);
+	NVIC_DisableIRQ((IRQn_Type)cfg_pwm->irq);
+	NVIC_ClearPendingIRQ((IRQn_Type)cfg_pwm->irq);
+	NVIC_EnableIRQ((IRQn_Type)cfg_pwm->irq);
+
+	return ERR_NONE;
+}
+/**
+ * \brief De-initialize TCC for PWM mode
+ */
+void _pwm_deinit(struct _pwm_device *const device)
+{
+	void *const         hw      = device->hw;
+	struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
+	if (cfg_pwm != NULL) {
+		NVIC_DisableIRQ((IRQn_Type)cfg_pwm->irq);
+		hri_tcc_clear_CTRLA_ENABLE_bit(hw);
+		hri_tcc_set_CTRLA_SWRST_bit(hw);
+	}
+}
+/**
+ * \brief Start PWM
+ */
+void _pwm_enable(struct _pwm_device *const device)
+{
+	hri_tcc_set_CTRLA_ENABLE_bit(device->hw);
+}
+/**
+ * \brief Stop PWM
+ */
+void _pwm_disable(struct _pwm_device *const device)
+{
+	hri_tcc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+/**
+ * \brief Set PWM parameter
+ */
+void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle)
+{
+	void *const         hw      = device->hw;
+	struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
+	if (cfg_pwm != NULL) {
+		hri_tcc_write_PERB_reg(hw, period);
+		hri_tcc_write_CCB_reg(hw, cfg_pwm->sel_ch, duty_cycle);
+		;
+	}
+}
+/**
+ * \brief Get pwm waveform period value
+ */
+pwm_period_t _pwm_get_period(const struct _pwm_device *const device)
+{
+	return (pwm_period_t)(hri_tcc_read_PERB_reg(device->hw));
+}
+/**
+ * \brief Get pwm waveform duty cycle
+ */
+uint32_t _pwm_get_duty(const struct _pwm_device *const device)
+{
+	void *const         hw      = device->hw;
+	struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
+	if (cfg_pwm == NULL) {
+		return ERR_NOT_FOUND;
+	}
+	uint32_t per        = hri_tcc_read_PERB_reg(hw);
+	uint32_t duty_cycle = hri_tcc_read_CCB_reg(hw, cfg_pwm->sel_ch);
+
+	return ((duty_cycle * 1000) / per);
+}
+/**
+ * \brief Check if PWM is running
+ */
+bool _pwm_is_enabled(const struct _pwm_device *const device)
+{
+	return hri_tcc_get_CTRLA_ENABLE_bit(device->hw);
+}
+/**
+ * \brief Enable/disable PWM interrupt
+ */
+void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable)
+{
+	ASSERT(device);
+
+	if (PWM_DEVICE_PERIOD_CB == type) {
+		hri_tcc_write_INTEN_OVF_bit(device->hw, disable);
+	} else if (PWM_DEVICE_ERROR_CB == type) {
+		hri_tcc_write_INTEN_ERR_bit(device->hw, disable);
+	}
+}
+
+/**
+ * \brief Retrieve timer helper functions
+ */
+struct _timer_hpl_interface *_tcc_get_timer(void)
+{
+	return NULL;
+}
+
+/**
+ * \brief Retrieve pwm helper functions
+ */
+struct _pwm_hpl_interface *_tcc_get_pwm(void)
+{
+	return NULL;
+}
+/**
+ * \internal TC interrupt handler for PWM
+ *
+ * \param[in] instance TC instance number
+ */
+static void tcc_pwm_interrupt_handler(struct _pwm_device *device)
+{
+	void *const hw = device->hw;
+
+	if (hri_tcc_get_interrupt_OVF_bit(hw)) {
+		hri_tcc_clear_interrupt_OVF_bit(hw);
+		if (NULL != device->callback.pwm_period_cb) {
+			device->callback.pwm_period_cb(device);
+		}
+	}
+	if (hri_tcc_get_INTEN_ERR_bit(hw)) {
+		hri_tcc_clear_interrupt_ERR_bit(hw);
+		if (NULL != device->callback.pwm_error_cb) {
+			device->callback.pwm_error_cb(device);
+		}
+	}
+}
+
+/**
+ * \brief TCC interrupt handler
+ */
+void TCC0_0_Handler(void)
+{
+	tcc_pwm_interrupt_handler(_tcc0_dev);
+}
+
+/**
+ * \brief TCC interrupt handler
+ */
+void TCC1_0_Handler(void)
+{
+	tcc_pwm_interrupt_handler(_tcc1_dev);
+}
+
+static struct tcc_cfg *_get_tcc_cfg(void *hw)
+{
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_cfgs); i++) {
+		if (_cfgs[i].hw == hw) {
+			return &(_cfgs[i]);
+		}
+	}
+	return NULL;
+}
+
+static struct tcc_pwm_cfg *_get_tcc_pwm_cfg(void *hw)
+{
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_cfgs_pwm); i++) {
+		if (_cfgs_pwm[i].hw == hw) {
+			return &(_cfgs_pwm[i]);
+		}
+	}
+	return NULL;
+}
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tcc/hpl_tcc.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tcc/hpl_tcc.h
new file mode 100644
index 0000000..4ccac85
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hpl/tcc/hpl_tcc.h
@@ -0,0 +1,77 @@
+/**
+ * \file
+ *
+ * \brief SAM Timer/Counter for Control Applications
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _HPL_TCC_V101_BASE_H_INCLUDED
+#define _HPL_TCC_V101_BASE_H_INCLUDED
+
+#include <hpl_timer.h>
+#include <hpl_pwm.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup tcc_group TCC Low Level Driver Helpers
+ *
+ * \section tcc_helpers_rev Revision History
+ * - v0.0.0.1 Initial Commit
+ *
+ *@{
+ */
+
+/**
+ * \name HPL functions
+ */
+//@{
+
+/**
+ * \brief Retrieve timer helper functions
+ *
+ * \return A pointer to set of timer helper functions
+ */
+struct _timer_hpl_interface *_tcc_get_timer(void);
+
+/**
+ * \brief Retrieve pwm helper functions
+ *
+ * \return A pointer to set of pwm helper functions
+ */
+struct _pwm_hpl_interface *_tcc_get_pwm(void);
+
+//@}
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HPL_TCC_V101_BASE_H_INCLUDED */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_ac_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_ac_d51.h
new file mode 100644
index 0000000..f5f4931
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_ac_d51.h
@@ -0,0 +1,1836 @@
+/**
+ * \file
+ *
+ * \brief SAM AC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_AC_COMPONENT_
+#ifndef _HRI_AC_D51_H_INCLUDED_
+#define _HRI_AC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_AC_CRITICAL_SECTIONS)
+#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define AC_CRITICAL_SECTION_ENTER()
+#define AC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_ac_calib_reg_t;
+typedef uint16_t hri_ac_evctrl_reg_t;
+typedef uint32_t hri_ac_compctrl_reg_t;
+typedef uint32_t hri_ac_syncbusy_reg_t;
+typedef uint8_t  hri_ac_ctrla_reg_t;
+typedef uint8_t  hri_ac_ctrlb_reg_t;
+typedef uint8_t  hri_ac_dbgctrl_reg_t;
+typedef uint8_t  hri_ac_intenset_reg_t;
+typedef uint8_t  hri_ac_intflag_reg_t;
+typedef uint8_t  hri_ac_scaler_reg_t;
+typedef uint8_t  hri_ac_statusa_reg_t;
+typedef uint8_t  hri_ac_statusb_reg_t;
+typedef uint8_t  hri_ac_winctrl_reg_t;
+
+static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg)
+{
+	while (((Ac *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg)
+{
+	return ((Ac *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
+}
+
+static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
+}
+
+static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
+}
+
+static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
+}
+
+static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
+}
+
+static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
+}
+
+static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Ac *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
+{
+	((Ac *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
+}
+
+static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos;
+}
+
+static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
+}
+
+static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
+}
+
+static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos;
+}
+
+static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
+}
+
+static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
+}
+
+static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos;
+}
+
+static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
+}
+
+static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	((Ac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw)
+{
+	return ((Ac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data)
+{
+	((Ac *)hw)->INTENSET.reg = data;
+	((Ac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	((Ac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSA.reg;
+}
+
+static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos;
+}
+
+static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSB.reg;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos;
+}
+
+static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Ac *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= ~AC_CTRLA_ENABLE;
+	tmp |= value << AC_CTRLA_ENABLE_Pos;
+	((Ac *)hw)->CTRLA.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	return ((Ac *)hw)->CTRLA.reg;
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEO0;
+	tmp |= value << AC_EVCTRL_COMPEO0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEO1;
+	tmp |= value << AC_EVCTRL_COMPEO1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_WINEO0;
+	tmp |= value << AC_EVCTRL_WINEO0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEI0;
+	tmp |= value << AC_EVCTRL_COMPEI0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEI1;
+	tmp |= value << AC_EVCTRL_COMPEI1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_INVEI0;
+	tmp |= value << AC_EVCTRL_INVEI0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_INVEI1;
+	tmp |= value << AC_EVCTRL_INVEI1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Ac *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp &= ~AC_DBGCTRL_DBGRUN;
+	tmp |= value << AC_DBGCTRL_DBGRUN_Pos;
+	((Ac *)hw)->DBGCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Ac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= ~AC_WINCTRL_WEN0;
+	tmp |= value << AC_WINCTRL_WEN0_Pos;
+	((Ac *)hw)->WINCTRL.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= ~AC_WINCTRL_WINTSEL0_Msk;
+	tmp |= AC_WINCTRL_WINTSEL0(data);
+	((Ac *)hw)->WINCTRL.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	return ((Ac *)hw)->WINCTRL.reg;
+}
+
+static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index,
+                                                             hri_ac_scaler_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp &= ~AC_SCALER_VALUE_Msk;
+	tmp |= AC_SCALER_VALUE(data);
+	((Ac *)hw)->SCALER[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index)
+{
+	return ((Ac *)hw)->SCALER[index].reg;
+}
+
+static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_ENABLE;
+	tmp |= value << AC_COMPCTRL_ENABLE_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SINGLE;
+	tmp |= value << AC_COMPCTRL_SINGLE_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_RUNSTDBY;
+	tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SWAP;
+	tmp |= value << AC_COMPCTRL_SWAP_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_HYSTEN;
+	tmp |= value << AC_COMPCTRL_HYSTEN_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_INTSEL_Msk;
+	tmp |= AC_COMPCTRL_INTSEL(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_MUXNEG_Msk;
+	tmp |= AC_COMPCTRL_MUXNEG(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_MUXPOS_Msk;
+	tmp |= AC_COMPCTRL_MUXPOS(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index,
+                                                                 hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SPEED_Msk;
+	tmp |= AC_COMPCTRL_SPEED(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index,
+                                                                hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_HYST_Msk;
+	tmp |= AC_COMPCTRL_HYST(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index,
+                                                                hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_FLEN_Msk;
+	tmp |= AC_COMPCTRL_FLEN(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index,
+                                                               hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_OUT_Msk;
+	tmp |= AC_COMPCTRL_OUT(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	return ((Ac *)hw)->COMPCTRL[index].reg;
+}
+
+static inline void hri_ac_set_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg |= AC_CALIB_BIAS0(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_calib_reg_t hri_ac_get_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->CALIB.reg;
+	tmp = (tmp & AC_CALIB_BIAS0(mask)) >> AC_CALIB_BIAS0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t data)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->CALIB.reg;
+	tmp &= ~AC_CALIB_BIAS0_Msk;
+	tmp |= AC_CALIB_BIAS0(data);
+	((Ac *)hw)->CALIB.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg &= ~AC_CALIB_BIAS0(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg ^= AC_CALIB_BIAS0(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_calib_reg_t hri_ac_read_CALIB_BIAS0_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->CALIB.reg;
+	tmp = (tmp & AC_CALIB_BIAS0_Msk) >> AC_CALIB_BIAS0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_calib_reg_t hri_ac_get_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_CALIB_reg(const void *const hw, hri_ac_calib_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_calib_reg_t hri_ac_read_CALIB_reg(const void *const hw)
+{
+	return ((Ac *)hw)->CALIB.reg;
+}
+
+static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLB.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_AC_D51_H_INCLUDED */
+#endif /* _SAMD51_AC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_adc_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_adc_d51.h
new file mode 100644
index 0000000..a140f32
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_adc_d51.h
@@ -0,0 +1,3663 @@
+/**
+ * \file
+ *
+ * \brief SAM ADC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_ADC_COMPONENT_
+#ifndef _HRI_ADC_D51_H_INCLUDED_
+#define _HRI_ADC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_ADC_CRITICAL_SECTIONS)
+#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define ADC_CRITICAL_SECTION_ENTER()
+#define ADC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_adc_calib_reg_t;
+typedef uint16_t hri_adc_ctrla_reg_t;
+typedef uint16_t hri_adc_ctrlb_reg_t;
+typedef uint16_t hri_adc_gaincorr_reg_t;
+typedef uint16_t hri_adc_inputctrl_reg_t;
+typedef uint16_t hri_adc_offsetcorr_reg_t;
+typedef uint16_t hri_adc_ress_reg_t;
+typedef uint16_t hri_adc_result_reg_t;
+typedef uint16_t hri_adc_winlt_reg_t;
+typedef uint16_t hri_adc_winut_reg_t;
+typedef uint32_t hri_adc_dseqctrl_reg_t;
+typedef uint32_t hri_adc_dseqdata_reg_t;
+typedef uint32_t hri_adc_dseqstat_reg_t;
+typedef uint32_t hri_adc_syncbusy_reg_t;
+typedef uint8_t  hri_adc_avgctrl_reg_t;
+typedef uint8_t  hri_adc_dbgctrl_reg_t;
+typedef uint8_t  hri_adc_evctrl_reg_t;
+typedef uint8_t  hri_adc_intenset_reg_t;
+typedef uint8_t  hri_adc_intflag_reg_t;
+typedef uint8_t  hri_adc_refctrl_reg_t;
+typedef uint8_t  hri_adc_sampctrl_reg_t;
+typedef uint8_t  hri_adc_status_reg_t;
+typedef uint8_t  hri_adc_swtrig_reg_t;
+
+static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg)
+{
+	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg)
+{
+	return ((Adc *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+}
+
+static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+}
+
+static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
+}
+
+static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+}
+
+static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+}
+
+static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
+}
+
+static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask)
+{
+	((Adc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
+}
+
+static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos;
+}
+
+static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
+}
+
+static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
+}
+
+static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos;
+}
+
+static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
+}
+
+static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
+}
+
+static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos;
+}
+
+static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
+}
+
+static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	((Adc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data)
+{
+	((Adc *)hw)->INTENSET.reg = data;
+	((Adc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	((Adc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_adc_get_STATUS_ADCBUSY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->STATUS.reg & ADC_STATUS_ADCBUSY) >> ADC_STATUS_ADCBUSY_Pos;
+}
+
+static inline hri_adc_status_reg_t hri_adc_get_STATUS_WCC_bf(const void *const hw, hri_adc_status_reg_t mask)
+{
+	return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC(mask)) >> ADC_STATUS_WCC_Pos;
+}
+
+static inline hri_adc_status_reg_t hri_adc_read_STATUS_WCC_bf(const void *const hw)
+{
+	return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC_Msk) >> ADC_STATUS_WCC_Pos;
+}
+
+static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw)
+{
+	return ((Adc *)hw)->STATUS.reg;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB) >> ADC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_REFCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL) >> ADC_SYNCBUSY_REFCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos;
+}
+
+static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Adc *)hw)->SYNCBUSY.reg;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_INPUTCTRL_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_INPUTCTRL) >> ADC_DSEQSTAT_INPUTCTRL_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_CTRLB_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_CTRLB) >> ADC_DSEQSTAT_CTRLB_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_REFCTRL_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_REFCTRL) >> ADC_DSEQSTAT_REFCTRL_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_AVGCTRL_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_AVGCTRL) >> ADC_DSEQSTAT_AVGCTRL_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_SAMPCTRL_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_SAMPCTRL) >> ADC_DSEQSTAT_SAMPCTRL_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_WINLT_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINLT) >> ADC_DSEQSTAT_WINLT_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_WINUT_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINUT) >> ADC_DSEQSTAT_WINUT_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_GAINCORR_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_GAINCORR) >> ADC_DSEQSTAT_GAINCORR_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_OFFSETCORR_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_OFFSETCORR) >> ADC_DSEQSTAT_OFFSETCORR_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_BUSY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_BUSY) >> ADC_DSEQSTAT_BUSY_Pos;
+}
+
+static inline hri_adc_dseqstat_reg_t hri_adc_get_DSEQSTAT_reg(const void *const hw, hri_adc_dseqstat_reg_t mask)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQSTAT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_dseqstat_reg_t hri_adc_read_DSEQSTAT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return ((Adc *)hw)->DSEQSTAT.reg;
+}
+
+static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask)
+{
+	return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos;
+}
+
+static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw)
+{
+	return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos;
+}
+
+static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->RESULT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw)
+{
+	return ((Adc *)hw)->RESULT.reg;
+}
+
+static inline hri_adc_ress_reg_t hri_adc_get_RESS_RESS_bf(const void *const hw, hri_adc_ress_reg_t mask)
+{
+	return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS(mask)) >> ADC_RESS_RESS_Pos;
+}
+
+static inline hri_adc_ress_reg_t hri_adc_read_RESS_RESS_bf(const void *const hw)
+{
+	return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS_Msk) >> ADC_RESS_RESS_Pos;
+}
+
+static inline hri_adc_ress_reg_t hri_adc_get_RESS_reg(const void *const hw, hri_adc_ress_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->RESS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_ress_reg_t hri_adc_read_RESS_reg(const void *const hw)
+{
+	return ((Adc *)hw)->RESS.reg;
+}
+
+static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_ENABLE;
+	tmp |= value << ADC_CTRLA_ENABLE_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_SLAVEEN;
+	tmp |= value << ADC_CTRLA_SLAVEEN_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_RUNSTDBY;
+	tmp |= value << ADC_CTRLA_RUNSTDBY_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_ONDEMAND;
+	tmp |= value << ADC_CTRLA_ONDEMAND_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_R2R_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_R2R) >> ADC_CTRLA_R2R_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_R2R_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_R2R;
+	tmp |= value << ADC_CTRLA_R2R_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_DUALSEL(mask)) >> ADC_CTRLA_DUALSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_DUALSEL_Msk;
+	tmp |= ADC_CTRLA_DUALSEL(data);
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_DUALSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_DUALSEL_Msk) >> ADC_CTRLA_DUALSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_PRESCALER(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_PRESCALER(mask)) >> ADC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_PRESCALER_Msk;
+	tmp |= ADC_CTRLA_PRESCALER(data);
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_PRESCALER(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_PRESCALER(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_PRESCALER_Msk) >> ADC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	return ((Adc *)hw)->CTRLA.reg;
+}
+
+static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_FLUSHEI;
+	tmp |= value << ADC_EVCTRL_FLUSHEI_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_STARTEI;
+	tmp |= value << ADC_EVCTRL_STARTEI_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_FLUSHINV;
+	tmp |= value << ADC_EVCTRL_FLUSHINV_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_STARTINV;
+	tmp |= value << ADC_EVCTRL_STARTINV_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_RESRDYEO;
+	tmp |= value << ADC_EVCTRL_RESRDYEO_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_WINMONEO;
+	tmp |= value << ADC_EVCTRL_WINMONEO_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp &= ~ADC_DBGCTRL_DBGRUN;
+	tmp |= value << ADC_DBGCTRL_DBGRUN_Pos;
+	((Adc *)hw)->DBGCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_adc_set_INPUTCTRL_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_INPUTCTRL_DIFFMODE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_DIFFMODE) >> ADC_INPUTCTRL_DIFFMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_DIFFMODE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_DIFFMODE;
+	tmp |= value << ADC_INPUTCTRL_DIFFMODE_Pos;
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_INPUTCTRL_DSEQSTOP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DSEQSTOP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_INPUTCTRL_DSEQSTOP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_DSEQSTOP) >> ADC_INPUTCTRL_DSEQSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_DSEQSTOP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_DSEQSTOP;
+	tmp |= value << ADC_INPUTCTRL_DSEQSTOP_Pos;
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_DSEQSTOP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_DSEQSTOP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DSEQSTOP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const       hw,
+                                                                      hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk;
+	tmp |= ADC_INPUTCTRL_MUXPOS(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const       hw,
+                                                                      hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk;
+	tmp |= ADC_INPUTCTRL_MUXNEG(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->INPUTCTRL.reg;
+}
+
+static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_LEFTADJ;
+	tmp |= value << ADC_CTRLB_LEFTADJ_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_FREERUN;
+	tmp |= value << ADC_CTRLB_FREERUN_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_CORREN;
+	tmp |= value << ADC_CTRLB_CORREN_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_WINSS_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINSS;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_WINSS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_WINSS) >> ADC_CTRLB_WINSS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_WINSS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_WINSS;
+	tmp |= value << ADC_CTRLB_WINSS_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_WINSS_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINSS;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_WINSS_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINSS;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_RESSEL_Msk;
+	tmp |= ADC_CTRLB_RESSEL(data);
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_WINMODE(mask)) >> ADC_CTRLB_WINMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_WINMODE_Msk;
+	tmp |= ADC_CTRLB_WINMODE(data);
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_WINMODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_WINMODE_Msk) >> ADC_CTRLB_WINMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->CTRLB.reg;
+}
+
+static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= ~ADC_REFCTRL_REFCOMP;
+	tmp |= value << ADC_REFCTRL_REFCOMP_Pos;
+	((Adc *)hw)->REFCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= ~ADC_REFCTRL_REFSEL_Msk;
+	tmp |= ADC_REFCTRL_REFSEL(data);
+	((Adc *)hw)->REFCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->REFCTRL.reg;
+}
+
+static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk;
+	tmp |= ADC_AVGCTRL_SAMPLENUM(data);
+	((Adc *)hw)->AVGCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= ~ADC_AVGCTRL_ADJRES_Msk;
+	tmp |= ADC_AVGCTRL_ADJRES(data);
+	((Adc *)hw)->AVGCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->AVGCTRL.reg;
+}
+
+static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= ~ADC_SAMPCTRL_OFFCOMP;
+	tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos;
+	((Adc *)hw)->SAMPCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk;
+	tmp |= ADC_SAMPCTRL_SAMPLEN(data);
+	((Adc *)hw)->SAMPCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->SAMPCTRL.reg;
+}
+
+static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp &= ~ADC_WINLT_WINLT_Msk;
+	tmp |= ADC_WINLT_WINLT(data);
+	((Adc *)hw)->WINLT.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	return ((Adc *)hw)->WINLT.reg;
+}
+
+static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp &= ~ADC_WINUT_WINUT_Msk;
+	tmp |= ADC_WINUT_WINUT(data);
+	((Adc *)hw)->WINUT.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	return ((Adc *)hw)->WINUT.reg;
+}
+
+static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp &= ~ADC_GAINCORR_GAINCORR_Msk;
+	tmp |= ADC_GAINCORR_GAINCORR(data);
+	((Adc *)hw)->GAINCORR.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	return ((Adc *)hw)->GAINCORR.reg;
+}
+
+static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const        hw,
+                                                                            hri_adc_offsetcorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk;
+	tmp |= ADC_OFFSETCORR_OFFSETCORR(data);
+	((Adc *)hw)->OFFSETCORR.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	return ((Adc *)hw)->OFFSETCORR.reg;
+}
+
+static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= ~ADC_SWTRIG_FLUSH;
+	tmp |= value << ADC_SWTRIG_FLUSH_Pos;
+	((Adc *)hw)->SWTRIG.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= ~ADC_SWTRIG_START;
+	tmp |= value << ADC_SWTRIG_START_Pos;
+	((Adc *)hw)->SWTRIG.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->SWTRIG.reg;
+}
+
+static inline void hri_adc_set_DSEQCTRL_INPUTCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_INPUTCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_INPUTCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_INPUTCTRL) >> ADC_DSEQCTRL_INPUTCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_INPUTCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_INPUTCTRL;
+	tmp |= value << ADC_DSEQCTRL_INPUTCTRL_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_INPUTCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_INPUTCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_INPUTCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_INPUTCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_CTRLB_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_CTRLB;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_CTRLB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_CTRLB) >> ADC_DSEQCTRL_CTRLB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_CTRLB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_CTRLB;
+	tmp |= value << ADC_DSEQCTRL_CTRLB_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_CTRLB_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_CTRLB;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_CTRLB_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_CTRLB;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_REFCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_REFCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_REFCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_REFCTRL) >> ADC_DSEQCTRL_REFCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_REFCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_REFCTRL;
+	tmp |= value << ADC_DSEQCTRL_REFCTRL_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_REFCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_REFCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_REFCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_REFCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_AVGCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AVGCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_AVGCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_AVGCTRL) >> ADC_DSEQCTRL_AVGCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_AVGCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_AVGCTRL;
+	tmp |= value << ADC_DSEQCTRL_AVGCTRL_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_AVGCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AVGCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_AVGCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AVGCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_SAMPCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_SAMPCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_SAMPCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_SAMPCTRL) >> ADC_DSEQCTRL_SAMPCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_SAMPCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_SAMPCTRL;
+	tmp |= value << ADC_DSEQCTRL_SAMPCTRL_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_SAMPCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_SAMPCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_SAMPCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_SAMPCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_WINLT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINLT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_WINLT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_WINLT) >> ADC_DSEQCTRL_WINLT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_WINLT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_WINLT;
+	tmp |= value << ADC_DSEQCTRL_WINLT_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_WINLT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINLT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_WINLT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINLT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_WINUT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINUT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_WINUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_WINUT) >> ADC_DSEQCTRL_WINUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_WINUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_WINUT;
+	tmp |= value << ADC_DSEQCTRL_WINUT_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_WINUT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINUT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_WINUT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINUT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_GAINCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_GAINCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_GAINCORR_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_GAINCORR) >> ADC_DSEQCTRL_GAINCORR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_GAINCORR_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_GAINCORR;
+	tmp |= value << ADC_DSEQCTRL_GAINCORR_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_GAINCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_GAINCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_GAINCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_GAINCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_OFFSETCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_OFFSETCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_OFFSETCORR_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_OFFSETCORR) >> ADC_DSEQCTRL_OFFSETCORR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_OFFSETCORR_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_OFFSETCORR;
+	tmp |= value << ADC_DSEQCTRL_OFFSETCORR_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_OFFSETCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_OFFSETCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_OFFSETCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_OFFSETCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_AUTOSTART_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AUTOSTART;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_AUTOSTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_AUTOSTART) >> ADC_DSEQCTRL_AUTOSTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_AUTOSTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_AUTOSTART;
+	tmp |= value << ADC_DSEQCTRL_AUTOSTART_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_AUTOSTART_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AUTOSTART;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_AUTOSTART_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AUTOSTART;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dseqctrl_reg_t hri_adc_get_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg = data;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dseqctrl_reg_t hri_adc_read_DSEQCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return ((Adc *)hw)->DSEQCTRL.reg;
+}
+
+static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASCOMP_Msk;
+	tmp |= ADC_CALIB_BIASCOMP(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASR2R(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASR2R(mask)) >> ADC_CALIB_BIASR2R_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASR2R_Msk;
+	tmp |= ADC_CALIB_BIASR2R(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASR2R(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASR2R(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASR2R_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASR2R_Msk) >> ADC_CALIB_BIASR2R_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASREFBUF_Msk;
+	tmp |= ADC_CALIB_BIASREFBUF(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw)
+{
+	return ((Adc *)hw)->CALIB.reg;
+}
+
+static inline void hri_adc_write_DSEQDATA_reg(const void *const hw, hri_adc_dseqdata_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQDATA.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_ADC_D51_H_INCLUDED */
+#endif /* _SAMD51_ADC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_aes_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_aes_d51.h
new file mode 100644
index 0000000..97981db
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_aes_d51.h
@@ -0,0 +1,1287 @@
+/**
+ * \file
+ *
+ * \brief SAM AES
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_AES_COMPONENT_
+#ifndef _HRI_AES_D51_H_INCLUDED_
+#define _HRI_AES_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_AES_CRITICAL_SECTIONS)
+#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define AES_CRITICAL_SECTION_ENTER()
+#define AES_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_aes_ciplen_reg_t;
+typedef uint32_t hri_aes_ctrla_reg_t;
+typedef uint32_t hri_aes_ghash_reg_t;
+typedef uint32_t hri_aes_hashkey_reg_t;
+typedef uint32_t hri_aes_indata_reg_t;
+typedef uint32_t hri_aes_intvectv_reg_t;
+typedef uint32_t hri_aes_keyword_reg_t;
+typedef uint32_t hri_aes_randseed_reg_t;
+typedef uint8_t  hri_aes_ctrlb_reg_t;
+typedef uint8_t  hri_aes_databufptr_reg_t;
+typedef uint8_t  hri_aes_dbgctrl_reg_t;
+typedef uint8_t  hri_aes_intenset_reg_t;
+typedef uint8_t  hri_aes_intflag_reg_t;
+
+static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos;
+}
+
+static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP;
+}
+
+static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos;
+}
+
+static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP;
+}
+
+static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos;
+}
+
+static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP;
+}
+
+static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos;
+}
+
+static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP;
+}
+
+static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask)
+{
+	((Aes *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP;
+}
+
+static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos;
+}
+
+static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP;
+	} else {
+		((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP;
+	}
+}
+
+static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP;
+}
+
+static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP;
+}
+
+static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos;
+}
+
+static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP;
+	} else {
+		((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP;
+	}
+}
+
+static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP;
+}
+
+static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	((Aes *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INTENSET.reg;
+}
+
+static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data)
+{
+	((Aes *)hw)->INTENSET.reg = data;
+	((Aes *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	((Aes *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_ENABLE;
+	tmp |= value << AES_CTRLA_ENABLE_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CIPHER;
+	tmp |= value << AES_CTRLA_CIPHER_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_STARTMODE;
+	tmp |= value << AES_CTRLA_STARTMODE_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_LOD;
+	tmp |= value << AES_CTRLA_LOD_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_KEYGEN;
+	tmp |= value << AES_CTRLA_KEYGEN_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_XORKEY;
+	tmp |= value << AES_CTRLA_XORKEY_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_AESMODE_Msk;
+	tmp |= AES_CTRLA_AESMODE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CFBS_Msk;
+	tmp |= AES_CTRLA_CFBS(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_KEYSIZE_Msk;
+	tmp |= AES_CTRLA_KEYSIZE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CTYPE_Msk;
+	tmp |= AES_CTRLA_CTYPE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CTRLA.reg;
+}
+
+static inline void hri_aes_set_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_START;
+	tmp |= value << AES_CTRLB_START_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_NEWMSG;
+	tmp |= value << AES_CTRLB_NEWMSG_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_EOM;
+	tmp |= value << AES_CTRLB_EOM_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_GFMUL;
+	tmp |= value << AES_CTRLB_GFMUL_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CTRLB.reg;
+}
+
+static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const        hw,
+                                                                           hri_aes_databufptr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk;
+	tmp |= AES_DATABUFPTR_INDATAPTR(data);
+	((Aes *)hw)->DATABUFPTR.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw)
+{
+	return ((Aes *)hw)->DATABUFPTR.reg;
+}
+
+static inline void hri_aes_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg |= AES_DBGCTRL_DBGRUN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DBGCTRL.reg;
+	tmp = (tmp & AES_DBGCTRL_DBGRUN) >> AES_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->DBGCTRL.reg;
+	tmp &= ~AES_DBGCTRL_DBGRUN;
+	tmp |= value << AES_DBGCTRL_DBGRUN_Pos;
+	((Aes *)hw)->DBGCTRL.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg &= ~AES_DBGCTRL_DBGRUN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg ^= AES_DBGCTRL_DBGRUN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_dbgctrl_reg_t hri_aes_get_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_dbgctrl_reg_t hri_aes_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Aes *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->INDATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INDATA.reg;
+}
+
+static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index,
+                                                            hri_aes_hashkey_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->HASHKEY[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index)
+{
+	return ((Aes *)hw)->HASHKEY[index].reg;
+}
+
+static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->GHASH[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index)
+{
+	return ((Aes *)hw)->GHASH[index].reg;
+}
+
+static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CIPLEN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CIPLEN.reg;
+}
+
+static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->RANDSEED.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw)
+{
+	return ((Aes *)hw)->RANDSEED.reg;
+}
+
+static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->KEYWORD[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INTVECTV[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_AES_D51_H_INCLUDED */
+#endif /* _SAMD51_AES_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_ccl_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_ccl_d51.h
new file mode 100644
index 0000000..105b186
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_ccl_d51.h
@@ -0,0 +1,776 @@
+/**
+ * \file
+ *
+ * \brief SAM CCL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_CCL_COMPONENT_
+#ifndef _HRI_CCL_D51_H_INCLUDED_
+#define _HRI_CCL_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_CCL_CRITICAL_SECTIONS)
+#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define CCL_CRITICAL_SECTION_ENTER()
+#define CCL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_ccl_lutctrl_reg_t;
+typedef uint8_t  hri_ccl_ctrl_reg_t;
+typedef uint8_t  hri_ccl_seqctrl_reg_t;
+
+static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= ~CCL_CTRL_ENABLE;
+	tmp |= value << CCL_CTRL_ENABLE_Pos;
+	((Ccl *)hw)->CTRL.reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= ~CCL_CTRL_RUNSTDBY;
+	tmp |= value << CCL_CTRL_RUNSTDBY_Pos;
+	((Ccl *)hw)->CTRL.reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw)
+{
+	return ((Ccl *)hw)->CTRL.reg;
+}
+
+static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_seqctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp &= ~CCL_SEQCTRL_SEQSEL_Msk;
+	tmp |= CCL_SEQCTRL_SEQSEL(data);
+	((Ccl *)hw)->SEQCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ccl_seqctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Ccl *)hw)->SEQCTRL[index].reg;
+}
+
+static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_ENABLE;
+	tmp |= value << CCL_LUTCTRL_ENABLE_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_EDGESEL;
+	tmp |= value << CCL_LUTCTRL_EDGESEL_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INVEI;
+	tmp |= value << CCL_LUTCTRL_INVEI_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_LUTEI;
+	tmp |= value << CCL_LUTCTRL_LUTEI_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_LUTEO;
+	tmp |= value << CCL_LUTCTRL_LUTEO_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index,
+                                                                   hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_FILTSEL_Msk;
+	tmp |= CCL_LUTCTRL_FILTSEL(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL0_Msk;
+	tmp |= CCL_LUTCTRL_INSEL0(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL1_Msk;
+	tmp |= CCL_LUTCTRL_INSEL1(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL2_Msk;
+	tmp |= CCL_LUTCTRL_INSEL2(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index,
+                                                                 hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_TRUTH_Msk;
+	tmp |= CCL_LUTCTRL_TRUTH(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Ccl *)hw)->LUTCTRL[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_CCL_D51_H_INCLUDED */
+#endif /* _SAMD51_CCL_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_cmcc_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_cmcc_d51.h
new file mode 100644
index 0000000..6b87c38
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_cmcc_d51.h
@@ -0,0 +1,361 @@
+/**
+ * \file
+ *
+ * \brief SAM CMCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_CMCC_COMPONENT_
+#ifndef _HRI_CMCC_D51_H_INCLUDED_
+#define _HRI_CMCC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_CMCC_CRITICAL_SECTIONS)
+#define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define CMCC_CRITICAL_SECTION_ENTER()
+#define CMCC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_cmcc_cfg_reg_t;
+typedef uint32_t hri_cmcc_ctrl_reg_t;
+typedef uint32_t hri_cmcc_lckway_reg_t;
+typedef uint32_t hri_cmcc_maint0_reg_t;
+typedef uint32_t hri_cmcc_maint1_reg_t;
+typedef uint32_t hri_cmcc_mcfg_reg_t;
+typedef uint32_t hri_cmcc_mctrl_reg_t;
+typedef uint32_t hri_cmcc_men_reg_t;
+typedef uint32_t hri_cmcc_msr_reg_t;
+typedef uint32_t hri_cmcc_sr_reg_t;
+typedef uint32_t hri_cmcc_type_reg_t;
+
+static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos;
+}
+
+static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos;
+}
+
+static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->TYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->TYPE.reg;
+}
+
+static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw)
+{
+	return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos;
+}
+
+static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->SR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->SR.reg;
+}
+
+static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask)
+{
+	return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos;
+}
+
+static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw)
+{
+	return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos;
+}
+
+static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->MSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->MSR.reg;
+}
+
+static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CFG.reg |= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->CFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CFG.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CFG.reg &= ~mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CFG.reg ^= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->CFG.reg;
+}
+
+static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->LCKWAY.reg |= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->LCKWAY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->LCKWAY.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->LCKWAY.reg &= ~mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->LCKWAY.reg ^= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->LCKWAY.reg;
+}
+
+static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCFG.reg |= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->MCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCFG.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCFG.reg &= ~mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCFG.reg ^= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->MCFG.reg;
+}
+
+static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MEN.reg |= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->MEN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MEN.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MEN.reg &= ~mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MEN.reg ^= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->MEN.reg;
+}
+
+static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CTRL.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MAINT0.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MAINT1.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCTRL.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_CMCC_D51_H_INCLUDED */
+#endif /* _SAMD51_CMCC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_d51.h
new file mode 100644
index 0000000..389edb5
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_d51.h
@@ -0,0 +1,75 @@
+/**
+ * \file
+ *
+ * \brief SAM D51 HRI top-level header file
+ *
+ * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HRI_D51_H_INCLUDED_
+#define _HRI_D51_H_INCLUDED_
+
+#include <sam.h>
+#include <hri_ac_d51.h>
+#include <hri_adc_d51.h>
+#include <hri_aes_d51.h>
+#include <hri_ccl_d51.h>
+#include <hri_cmcc_d51.h>
+#include <hri_dac_d51.h>
+#include <hri_dmac_d51.h>
+#include <hri_dsu_d51.h>
+#include <hri_eic_d51.h>
+#include <hri_evsys_d51.h>
+#include <hri_freqm_d51.h>
+#include <hri_gclk_d51.h>
+#include <hri_hmatrixb_d51.h>
+#include <hri_i2s_d51.h>
+#include <hri_icm_d51.h>
+#include <hri_mclk_d51.h>
+#include <hri_nvmctrl_d51.h>
+#include <hri_osc32kctrl_d51.h>
+#include <hri_oscctrl_d51.h>
+#include <hri_pac_d51.h>
+#include <hri_pcc_d51.h>
+#include <hri_pdec_d51.h>
+#include <hri_pm_d51.h>
+#include <hri_port_d51.h>
+#include <hri_qspi_d51.h>
+#include <hri_ramecc_d51.h>
+#include <hri_rstc_d51.h>
+#include <hri_rtc_d51.h>
+#include <hri_sdhc_d51.h>
+#include <hri_sercom_d51.h>
+#include <hri_supc_d51.h>
+#include <hri_tc_d51.h>
+#include <hri_tcc_d51.h>
+#include <hri_trng_d51.h>
+#include <hri_usb_d51.h>
+#include <hri_wdt_d51.h>
+
+#endif /* _HRI_D51_H_INCLUDED_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_dac_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_dac_d51.h
new file mode 100644
index 0000000..dd7e9c5
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_dac_d51.h
@@ -0,0 +1,1706 @@
+/**
+ * \file
+ *
+ * \brief SAM DAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_DAC_COMPONENT_
+#ifndef _HRI_DAC_D51_H_INCLUDED_
+#define _HRI_DAC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DAC_CRITICAL_SECTIONS)
+#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DAC_CRITICAL_SECTION_ENTER()
+#define DAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_dac_dacctrl_reg_t;
+typedef uint16_t hri_dac_data_reg_t;
+typedef uint16_t hri_dac_databuf_reg_t;
+typedef uint16_t hri_dac_result_reg_t;
+typedef uint32_t hri_dac_syncbusy_reg_t;
+typedef uint8_t  hri_dac_ctrla_reg_t;
+typedef uint8_t  hri_dac_ctrlb_reg_t;
+typedef uint8_t  hri_dac_dbgctrl_reg_t;
+typedef uint8_t  hri_dac_evctrl_reg_t;
+typedef uint8_t  hri_dac_intenset_reg_t;
+typedef uint8_t  hri_dac_intflag_reg_t;
+typedef uint8_t  hri_dac_status_reg_t;
+
+static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg)
+{
+	while (((Dac *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg)
+{
+	return ((Dac *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0;
+}
+
+static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1;
+}
+
+static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0;
+}
+
+static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1;
+}
+
+static inline bool hri_dac_get_INTFLAG_RESRDY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_RESRDY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0;
+}
+
+static inline bool hri_dac_get_INTFLAG_RESRDY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_RESRDY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1;
+}
+
+static inline bool hri_dac_get_INTFLAG_OVERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_OVERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0;
+}
+
+static inline bool hri_dac_get_INTFLAG_OVERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_OVERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1;
+}
+
+static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0;
+}
+
+static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1;
+}
+
+static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0;
+}
+
+static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1;
+}
+
+static inline bool hri_dac_get_interrupt_RESRDY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_RESRDY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0;
+}
+
+static inline bool hri_dac_get_interrupt_RESRDY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_RESRDY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1;
+}
+
+static inline bool hri_dac_get_interrupt_OVERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_OVERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0;
+}
+
+static inline bool hri_dac_get_interrupt_OVERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_OVERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1;
+}
+
+static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Dac *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask)
+{
+	((Dac *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0;
+}
+
+static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos;
+}
+
+static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0;
+}
+
+static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1;
+}
+
+static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos;
+}
+
+static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1;
+}
+
+static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0;
+}
+
+static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos;
+}
+
+static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0;
+}
+
+static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1;
+}
+
+static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos;
+}
+
+static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1;
+}
+
+static inline void hri_dac_set_INTEN_RESRDY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0;
+}
+
+static inline bool hri_dac_get_INTEN_RESRDY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY0) >> DAC_INTENSET_RESRDY0_Pos;
+}
+
+static inline void hri_dac_write_INTEN_RESRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_RESRDY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0;
+}
+
+static inline void hri_dac_set_INTEN_RESRDY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1;
+}
+
+static inline bool hri_dac_get_INTEN_RESRDY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY1) >> DAC_INTENSET_RESRDY1_Pos;
+}
+
+static inline void hri_dac_write_INTEN_RESRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_RESRDY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1;
+}
+
+static inline void hri_dac_set_INTEN_OVERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0;
+}
+
+static inline bool hri_dac_get_INTEN_OVERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN0) >> DAC_INTENSET_OVERRUN0_Pos;
+}
+
+static inline void hri_dac_write_INTEN_OVERRUN0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_OVERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0;
+}
+
+static inline void hri_dac_set_INTEN_OVERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1;
+}
+
+static inline bool hri_dac_get_INTEN_OVERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN1) >> DAC_INTENSET_OVERRUN1_Pos;
+}
+
+static inline void hri_dac_write_INTEN_OVERRUN1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_OVERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1;
+}
+
+static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask)
+{
+	((Dac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw)
+{
+	return ((Dac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data)
+{
+	((Dac *)hw)->INTENSET.reg = data;
+	((Dac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask)
+{
+	((Dac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos;
+}
+
+static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos;
+}
+
+static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos;
+}
+
+static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos;
+}
+
+static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw)
+{
+	return ((Dac *)hw)->STATUS.reg;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos;
+}
+
+static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dac *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Dac *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_dac_result_reg_t hri_dac_get_RESULT_RESULT_bf(const void *const hw, uint8_t index,
+                                                                hri_dac_result_reg_t mask)
+{
+	return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT(mask)) >> DAC_RESULT_RESULT_Pos;
+}
+
+static inline hri_dac_result_reg_t hri_dac_read_RESULT_RESULT_bf(const void *const hw, uint8_t index)
+{
+	return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT_Msk) >> DAC_RESULT_RESULT_Pos;
+}
+
+static inline hri_dac_result_reg_t hri_dac_get_RESULT_reg(const void *const hw, uint8_t index,
+                                                          hri_dac_result_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->RESULT[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_result_reg_t hri_dac_read_RESULT_reg(const void *const hw, uint8_t index)
+{
+	return ((Dac *)hw)->RESULT[index].reg;
+}
+
+static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp &= ~DAC_CTRLA_ENABLE;
+	tmp |= value << DAC_CTRLA_ENABLE_Pos;
+	((Dac *)hw)->CTRLA.reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg |= mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg = data;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg &= ~mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg ^= mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw)
+{
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	return ((Dac *)hw)->CTRLA.reg;
+}
+
+static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= ~DAC_CTRLB_DIFF;
+	tmp |= value << DAC_CTRLB_DIFF_Pos;
+	((Dac *)hw)->CTRLB.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= ~DAC_CTRLB_REFSEL_Msk;
+	tmp |= DAC_CTRLB_REFSEL(data);
+	((Dac *)hw)->CTRLB.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw)
+{
+	return ((Dac *)hw)->CTRLB.reg;
+}
+
+static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_STARTEI0;
+	tmp |= value << DAC_EVCTRL_STARTEI0_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_STARTEI1;
+	tmp |= value << DAC_EVCTRL_STARTEI1_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_EMPTYEO0;
+	tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_EMPTYEO1;
+	tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_INVEI0;
+	tmp |= value << DAC_EVCTRL_INVEI0_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_INVEI1;
+	tmp |= value << DAC_EVCTRL_INVEI1_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_RESRDYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_RESRDYEO0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_RESRDYEO0) >> DAC_EVCTRL_RESRDYEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_RESRDYEO0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_RESRDYEO0;
+	tmp |= value << DAC_EVCTRL_RESRDYEO0_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_RESRDYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_RESRDYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_RESRDYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_RESRDYEO1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_RESRDYEO1) >> DAC_EVCTRL_RESRDYEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_RESRDYEO1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_RESRDYEO1;
+	tmp |= value << DAC_EVCTRL_RESRDYEO1_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_RESRDYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_RESRDYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Dac *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_LEFTADJ;
+	tmp |= value << DAC_DACCTRL_LEFTADJ_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_ENABLE;
+	tmp |= value << DAC_DACCTRL_ENABLE_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_FEXT_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_FEXT;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_FEXT_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_FEXT) >> DAC_DACCTRL_FEXT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_FEXT_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_FEXT;
+	tmp |= value << DAC_DACCTRL_FEXT_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_FEXT_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_FEXT;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_FEXT_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_FEXT;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_RUNSTDBY;
+	tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_DITHER;
+	tmp |= value << DAC_DACCTRL_DITHER_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index,
+                                                                 hri_dac_dacctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_CCTRL_Msk;
+	tmp |= DAC_DACCTRL_CCTRL(data);
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index,
+                                                                   hri_dac_dacctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_REFRESH_Msk;
+	tmp |= DAC_DACCTRL_REFRESH(data);
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_OSR(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_OSR_bf(const void *const hw, uint8_t index,
+                                                               hri_dac_dacctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_OSR(mask)) >> DAC_DACCTRL_OSR_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_OSR_Msk;
+	tmp |= DAC_DACCTRL_OSR(data);
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_OSR(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_OSR(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_OSR_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_OSR_Msk) >> DAC_DACCTRL_OSR_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_dac_dacctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg = data;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	return ((Dac *)hw)->DACCTRL[index].reg;
+}
+
+static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DBGCTRL.reg;
+	tmp &= ~DAC_DBGCTRL_DBGRUN;
+	tmp |= value << DAC_DBGCTRL_DBGRUN_Pos;
+	((Dac *)hw)->DBGCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Dac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATA[index].reg = data;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA0 | DAC_SYNCBUSY_DATA1);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATABUF[index].reg = data;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF0 | DAC_SYNCBUSY_DATABUF1);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DAC_D51_H_INCLUDED */
+#endif /* _SAMD51_DAC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_dmac_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_dmac_d51.h
new file mode 100644
index 0000000..7747eda
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_dmac_d51.h
@@ -0,0 +1,6800 @@
+/**
+ * \file
+ *
+ * \brief SAM DMAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_DMAC_COMPONENT_
+#ifndef _HRI_DMAC_D51_H_INCLUDED_
+#define _HRI_DMAC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DMAC_CRITICAL_SECTIONS)
+#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DMAC_CRITICAL_SECTION_ENTER()
+#define DMAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_dmac_crcctrl_reg_t;
+typedef uint16_t hri_dmac_ctrl_reg_t;
+typedef uint16_t hri_dmac_intpend_reg_t;
+typedef uint16_t hri_dmacdescriptor_btcnt_reg_t;
+typedef uint16_t hri_dmacdescriptor_btctrl_reg_t;
+typedef uint32_t hri_dmac_active_reg_t;
+typedef uint32_t hri_dmac_baseaddr_reg_t;
+typedef uint32_t hri_dmac_busych_reg_t;
+typedef uint32_t hri_dmac_chctrla_reg_t;
+typedef uint32_t hri_dmac_crcchksum_reg_t;
+typedef uint32_t hri_dmac_crcdatain_reg_t;
+typedef uint32_t hri_dmac_intstatus_reg_t;
+typedef uint32_t hri_dmac_pendch_reg_t;
+typedef uint32_t hri_dmac_prictrl0_reg_t;
+typedef uint32_t hri_dmac_swtrigctrl_reg_t;
+typedef uint32_t hri_dmac_wrbaddr_reg_t;
+typedef uint32_t hri_dmacchannel_chctrla_reg_t;
+typedef uint32_t hri_dmacdescriptor_descaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t;
+typedef uint8_t  hri_dmac_chctrlb_reg_t;
+typedef uint8_t  hri_dmac_chevctrl_reg_t;
+typedef uint8_t  hri_dmac_chintenset_reg_t;
+typedef uint8_t  hri_dmac_chintflag_reg_t;
+typedef uint8_t  hri_dmac_chprilvl_reg_t;
+typedef uint8_t  hri_dmac_chstatus_reg_t;
+typedef uint8_t  hri_dmac_crcstatus_reg_t;
+typedef uint8_t  hri_dmac_dbgctrl_reg_t;
+typedef uint8_t  hri_dmacchannel_chctrlb_reg_t;
+typedef uint8_t  hri_dmacchannel_chevctrl_reg_t;
+typedef uint8_t  hri_dmacchannel_chintenset_reg_t;
+typedef uint8_t  hri_dmacchannel_chintflag_reg_t;
+typedef uint8_t  hri_dmacchannel_chprilvl_reg_t;
+typedef uint8_t  hri_dmacchannel_chstatus_reg_t;
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT16_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT16) >> DMAC_INTSTATUS_CHINT16_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT17_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT17) >> DMAC_INTSTATUS_CHINT17_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT18_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT18) >> DMAC_INTSTATUS_CHINT18_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT19_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT19) >> DMAC_INTSTATUS_CHINT19_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT20_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT20) >> DMAC_INTSTATUS_CHINT20_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT21_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT21) >> DMAC_INTSTATUS_CHINT21_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT22_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT22) >> DMAC_INTSTATUS_CHINT22_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT23_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT23) >> DMAC_INTSTATUS_CHINT23_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT24_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT24) >> DMAC_INTSTATUS_CHINT24_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT25_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT25) >> DMAC_INTSTATUS_CHINT25_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT26_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT26) >> DMAC_INTSTATUS_CHINT26_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT27_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT27) >> DMAC_INTSTATUS_CHINT27_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT28_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT28) >> DMAC_INTSTATUS_CHINT28_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT29_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT29) >> DMAC_INTSTATUS_CHINT29_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT30_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT30) >> DMAC_INTSTATUS_CHINT30_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT31_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT31) >> DMAC_INTSTATUS_CHINT31_Pos;
+}
+
+static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->INTSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->INTSTATUS.reg;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH16_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH16) >> DMAC_BUSYCH_BUSYCH16_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH17_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH17) >> DMAC_BUSYCH_BUSYCH17_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH18_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH18) >> DMAC_BUSYCH_BUSYCH18_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH19_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH19) >> DMAC_BUSYCH_BUSYCH19_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH20_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH20) >> DMAC_BUSYCH_BUSYCH20_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH21_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH21) >> DMAC_BUSYCH_BUSYCH21_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH22_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH22) >> DMAC_BUSYCH_BUSYCH22_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH23_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH23) >> DMAC_BUSYCH_BUSYCH23_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH24_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH24) >> DMAC_BUSYCH_BUSYCH24_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH25_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH25) >> DMAC_BUSYCH_BUSYCH25_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH26_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH26) >> DMAC_BUSYCH_BUSYCH26_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH27_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH27) >> DMAC_BUSYCH_BUSYCH27_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH28_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH28) >> DMAC_BUSYCH_BUSYCH28_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH29_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH29) >> DMAC_BUSYCH_BUSYCH29_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH30_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH30) >> DMAC_BUSYCH_BUSYCH30_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH31_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH31) >> DMAC_BUSYCH_BUSYCH31_Pos;
+}
+
+static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BUSYCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->BUSYCH.reg;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH16_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH16) >> DMAC_PENDCH_PENDCH16_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH17_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH17) >> DMAC_PENDCH_PENDCH17_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH18_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH18) >> DMAC_PENDCH_PENDCH18_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH19_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH19) >> DMAC_PENDCH_PENDCH19_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH20_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH20) >> DMAC_PENDCH_PENDCH20_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH21_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH21) >> DMAC_PENDCH_PENDCH21_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH22_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH22) >> DMAC_PENDCH_PENDCH22_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH23_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH23) >> DMAC_PENDCH_PENDCH23_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH24_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH24) >> DMAC_PENDCH_PENDCH24_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH25_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH25) >> DMAC_PENDCH_PENDCH25_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH26_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH26) >> DMAC_PENDCH_PENDCH26_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH27_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH27) >> DMAC_PENDCH_PENDCH27_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH28_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH28) >> DMAC_PENDCH_PENDCH28_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH29_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH29) >> DMAC_PENDCH_PENDCH29_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH30_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH30) >> DMAC_PENDCH_PENDCH30_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH31_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH31) >> DMAC_PENDCH_PENDCH31_Pos;
+}
+
+static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PENDCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->PENDCH.reg;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->ACTIVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->ACTIVE.reg;
+}
+
+static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_DMAENABLE;
+	tmp |= value << DMAC_CTRL_DMAENABLE_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN0;
+	tmp |= value << DMAC_CTRL_LVLEN0_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN1;
+	tmp |= value << DMAC_CTRL_LVLEN1_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN2;
+	tmp |= value << DMAC_CTRL_LVLEN2_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN3;
+	tmp |= value << DMAC_CTRL_LVLEN3_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CTRL.reg;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const      hw,
+                                                                         hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk;
+	tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk;
+	tmp |= DMAC_CRCCTRL_CRCPOLY(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk;
+	tmp |= DMAC_CRCCTRL_CRCSRC(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCMODE(mask)) >> DMAC_CRCCTRL_CRCMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCMODE_Msk;
+	tmp |= DMAC_CRCCTRL_CRCMODE(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCMODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCMODE_Msk) >> DMAC_CRCCTRL_CRCMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCCTRL.reg;
+}
+
+static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const        hw,
+                                                                           hri_dmac_crcdatain_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk;
+	tmp |= DMAC_CRCDATAIN_CRCDATAIN(data);
+	((Dmac *)hw)->CRCDATAIN.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCDATAIN.reg;
+}
+
+static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const        hw,
+                                                                           hri_dmac_crcchksum_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk;
+	tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data);
+	((Dmac *)hw)->CRCCHKSUM.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCCHKSUM.reg;
+}
+
+static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp &= ~DMAC_DBGCTRL_DBGRUN;
+	tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos;
+	((Dmac *)hw)->DBGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG16_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG16;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG16_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG16) >> DMAC_SWTRIGCTRL_SWTRIG16_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG16_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG16;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG16_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG16_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG16;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG16_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG16;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG17_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG17;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG17_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG17) >> DMAC_SWTRIGCTRL_SWTRIG17_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG17_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG17;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG17_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG17_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG17;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG17_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG17;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG18_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG18;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG18_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG18) >> DMAC_SWTRIGCTRL_SWTRIG18_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG18_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG18;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG18_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG18_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG18;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG18_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG18;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG19_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG19;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG19_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG19) >> DMAC_SWTRIGCTRL_SWTRIG19_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG19_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG19;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG19_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG19_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG19;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG19_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG19;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG20_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG20;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG20_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG20) >> DMAC_SWTRIGCTRL_SWTRIG20_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG20_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG20;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG20_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG20_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG20;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG20_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG20;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG21_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG21;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG21_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG21) >> DMAC_SWTRIGCTRL_SWTRIG21_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG21_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG21;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG21_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG21_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG21;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG21_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG21;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG22_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG22;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG22_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG22) >> DMAC_SWTRIGCTRL_SWTRIG22_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG22_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG22;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG22_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG22_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG22;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG22_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG22;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG23_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG23;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG23_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG23) >> DMAC_SWTRIGCTRL_SWTRIG23_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG23_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG23;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG23_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG23_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG23;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG23_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG23;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG24_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG24;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG24_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG24) >> DMAC_SWTRIGCTRL_SWTRIG24_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG24_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG24;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG24_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG24_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG24;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG24_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG24;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG25_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG25;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG25_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG25) >> DMAC_SWTRIGCTRL_SWTRIG25_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG25_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG25;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG25_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG25_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG25;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG25_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG25;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG26_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG26;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG26_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG26) >> DMAC_SWTRIGCTRL_SWTRIG26_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG26_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG26;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG26_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG26_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG26;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG26_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG26;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG27_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG27;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG27_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG27) >> DMAC_SWTRIGCTRL_SWTRIG27_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG27_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG27;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG27_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG27_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG27;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG27_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG27;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG28_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG28;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG28_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG28) >> DMAC_SWTRIGCTRL_SWTRIG28_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG28_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG28;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG28_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG28_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG28;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG28_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG28;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG29_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG29;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG29_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG29) >> DMAC_SWTRIGCTRL_SWTRIG29_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG29_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG29;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG29_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG29_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG29;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG29_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG29;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG30_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG30;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG30_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG30) >> DMAC_SWTRIGCTRL_SWTRIG30_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG30_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG30;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG30_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG30_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG30;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG30_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG30;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG31_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG31;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG31_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG31) >> DMAC_SWTRIGCTRL_SWTRIG31_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG31_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG31;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG31_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG31_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG31;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG31_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG31;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const         hw,
+                                                                    hri_dmac_swtrigctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->SWTRIGCTRL.reg;
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN0;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN1;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN2;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN3;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI0(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS0(mask)) >> DMAC_PRICTRL0_QOS0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_QOS0_Msk;
+	tmp |= DMAC_PRICTRL0_QOS0(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS0_Msk) >> DMAC_PRICTRL0_QOS0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI1(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS1(mask)) >> DMAC_PRICTRL0_QOS1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_QOS1_Msk;
+	tmp |= DMAC_PRICTRL0_QOS1(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS1_Msk) >> DMAC_PRICTRL0_QOS1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI2(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS2(mask)) >> DMAC_PRICTRL0_QOS2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_QOS2_Msk;
+	tmp |= DMAC_PRICTRL0_QOS2(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS2_Msk) >> DMAC_PRICTRL0_QOS2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI3(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS3(mask)) >> DMAC_PRICTRL0_QOS3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_QOS3_Msk;
+	tmp |= DMAC_PRICTRL0_QOS3(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS3_Msk) >> DMAC_PRICTRL0_QOS3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->PRICTRL0.reg;
+}
+
+static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_TERR;
+	tmp |= value << DMAC_INTPEND_TERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_TCMPL;
+	tmp |= value << DMAC_INTPEND_TCMPL_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_SUSP;
+	tmp |= value << DMAC_INTPEND_SUSP_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_CRCERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_CRCERR) >> DMAC_INTPEND_CRCERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_CRCERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_CRCERR;
+	tmp |= value << DMAC_INTPEND_CRCERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_FERR;
+	tmp |= value << DMAC_INTPEND_FERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_BUSY;
+	tmp |= value << DMAC_INTPEND_BUSY_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_PEND;
+	tmp |= value << DMAC_INTPEND_PEND_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_ID_Msk;
+	tmp |= DMAC_INTPEND_ID(data);
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->INTPEND.reg;
+}
+
+static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const       hw,
+                                                                        hri_dmac_baseaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp &= ~DMAC_BASEADDR_BASEADDR_Msk;
+	tmp |= DMAC_BASEADDR_BASEADDR(data);
+	((Dmac *)hw)->BASEADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->BASEADDR.reg;
+}
+
+static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp &= ~DMAC_WRBADDR_WRBADDR_Msk;
+	tmp |= DMAC_WRBADDR_WRBADDR(data);
+	((Dmac *)hw)->WRBADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->WRBADDR.reg;
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCERR) >> DMAC_CRCSTATUS_CRCERR_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CRCSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCSTATUS.reg;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_VALID;
+	tmp |= value << DMAC_BTCTRL_VALID_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_SRCINC;
+	tmp |= value << DMAC_BTCTRL_SRCINC_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_DSTINC;
+	tmp |= value << DMAC_BTCTRL_DSTINC_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_STEPSEL;
+	tmp |= value << DMAC_BTCTRL_STEPSEL_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_EVOSEL_Msk;
+	tmp |= DMAC_BTCTRL_EVOSEL(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const               hw,
+                                                              hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk;
+	tmp |= DMAC_BTCTRL_BLOCKACT(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk;
+	tmp |= DMAC_BTCTRL_BEATSIZE(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk;
+	tmp |= DMAC_BTCTRL_STEPSIZE(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const               hw,
+                                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->BTCTRL.reg;
+}
+
+static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const              hw,
+                                                                                   hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp &= ~DMAC_BTCNT_BTCNT_Msk;
+	tmp |= DMAC_BTCNT_BTCNT(data);
+	((DmacDescriptor *)hw)->BTCNT.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const              hw,
+                                                                              hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->BTCNT.reg;
+}
+
+static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                             hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t
+hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_srcaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp &= ~DMAC_SRCADDR_SRCADDR_Msk;
+	tmp |= DMAC_SRCADDR_SRCADDR(data);
+	((DmacDescriptor *)hw)->SRCADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                                hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const                hw,
+                                                                                  hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->SRCADDR.reg;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_CRC_CHKINIT_bf(const void *const                hw,
+                                                                 hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_CRC_CHKINIT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t
+hri_dmacdescriptor_get_DSTADDR_CRC_CHKINIT_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT(mask)) >> DMAC_DSTADDR_CRC_CHKINIT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_CRC_CHKINIT_bf(const void *const                hw,
+                                                                   hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= ~DMAC_DSTADDR_CRC_CHKINIT_Msk;
+	tmp |= DMAC_DSTADDR_CRC_CHKINIT(data);
+	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_CHKINIT_bf(const void *const                hw,
+                                                                   hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_CRC_CHKINIT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_CHKINIT_bf(const void *const                hw,
+                                                                    hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_CRC_CHKINIT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_CHKINIT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT_Msk) >> DMAC_DSTADDR_CRC_CHKINIT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                             hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t
+hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= ~DMAC_DSTADDR_DSTADDR_Msk;
+	tmp |= DMAC_DSTADDR_DSTADDR(data);
+	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                                hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const                hw,
+                                                                                  hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->DSTADDR.reg;
+}
+
+static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                               hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t
+hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                 hri_dmacdescriptor_descaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp &= ~DMAC_DESCADDR_DESCADDR_Msk;
+	tmp |= DMAC_DESCADDR_DESCADDR(data);
+	((DmacDescriptor *)hw)->DESCADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                 hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                  hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t
+hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->DESCADDR.reg;
+}
+
+static inline bool hri_dmacchannel_get_CHINTFLAG_TERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHINTFLAG_TERR_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmacchannel_get_CHINTFLAG_TCMPL_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHINTFLAG_TCMPL_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmacchannel_get_CHINTFLAG_SUSP_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHINTFLAG_SUSP_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline bool hri_dmacchannel_get_interrupt_TERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmacchannel_clear_interrupt_TERR_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmacchannel_get_interrupt_TCMPL_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmacchannel_clear_interrupt_TCMPL_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmacchannel_get_interrupt_SUSP_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmacchannel_clear_interrupt_SUSP_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmacchannel_get_CHINTFLAG_reg(const void *const        hw,
+                                                                         hri_dmac_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmacchannel_read_CHINTFLAG_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHINTFLAG.reg;
+}
+
+static inline void hri_dmacchannel_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = mask;
+}
+
+static inline void hri_dmacchannel_set_CHINTEN_TERR_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline bool hri_dmacchannel_get_CHINTEN_TERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos;
+}
+
+static inline void hri_dmacchannel_write_CHINTEN_TERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+	} else {
+		((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+	}
+}
+
+static inline void hri_dmacchannel_clear_CHINTEN_TERR_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline void hri_dmacchannel_set_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline bool hri_dmacchannel_get_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos;
+}
+
+static inline void hri_dmacchannel_write_CHINTEN_TCMPL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+	} else {
+		((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+	}
+}
+
+static inline void hri_dmacchannel_clear_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline void hri_dmacchannel_set_CHINTEN_SUSP_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline bool hri_dmacchannel_get_CHINTEN_SUSP_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos;
+}
+
+static inline void hri_dmacchannel_write_CHINTEN_SUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+	} else {
+		((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+	}
+}
+
+static inline void hri_dmacchannel_clear_CHINTEN_SUSP_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline void hri_dmacchannel_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = mask;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmacchannel_get_CHINTEN_reg(const void *const         hw,
+                                                                        hri_dmac_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmacchannel_read_CHINTEN_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHINTENSET.reg;
+}
+
+static inline void hri_dmacchannel_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = data;
+	((DmacChannel *)hw)->CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_dmacchannel_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	((DmacChannel *)hw)->CHINTENCLR.reg = mask;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_SWRST_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHCTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_ENABLE;
+	tmp |= value << DMAC_CHCTRLA_ENABLE_Pos;
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_RUNSTDBY;
+	tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos;
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGSRC_bf(const void *const      hw,
+                                                                            hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk;
+	tmp |= DMAC_CHCTRLA_TRIGSRC(data);
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGSRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGACT_bf(const void *const      hw,
+                                                                            hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk;
+	tmp |= DMAC_CHCTRLA_TRIGACT(data);
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_BURSTLEN_bf(const void *const      hw,
+                                                                             hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk;
+	tmp |= DMAC_CHCTRLA_BURSTLEN(data);
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_BURSTLEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_THRESHOLD_bf(const void *const      hw,
+                                                                              hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk;
+	tmp |= DMAC_CHCTRLA_THRESHOLD(data);
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_THRESHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHCTRLA.reg;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_CMD_bf(const void *const      hw,
+                                                                        hri_dmac_chctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_CMD_Msk;
+	tmp |= DMAC_CHCTRLB_CMD(data);
+	((DmacChannel *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHCTRLB.reg;
+}
+
+static inline void hri_dmacchannel_set_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_PRILVL_bf(const void *const       hw,
+                                                                             hri_dmac_chprilvl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHPRILVL.reg;
+	tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHPRILVL.reg;
+	tmp &= ~DMAC_CHPRILVL_PRILVL_Msk;
+	tmp |= DMAC_CHPRILVL_PRILVL(data);
+	((DmacChannel *)hw)->CHPRILVL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_PRILVL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHPRILVL.reg;
+	tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_reg(const void *const       hw,
+                                                                       hri_dmac_chprilvl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHPRILVL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHPRILVL.reg;
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHEVCTRL_EVIE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_EVIE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVIE;
+	tmp |= value << DMAC_CHEVCTRL_EVIE_Pos;
+	((DmacChannel *)hw)->CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHEVCTRL_EVOE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_EVOE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVOE;
+	tmp |= value << DMAC_CHEVCTRL_EVOE_Pos;
+	((DmacChannel *)hw)->CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVACT_bf(const void *const       hw,
+                                                                            hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVACT_Msk;
+	tmp |= DMAC_CHEVCTRL_EVACT(data);
+	((DmacChannel *)hw)->CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVACT_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVOMODE_bf(const void *const       hw,
+                                                                              hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk;
+	tmp |= DMAC_CHEVCTRL_EVOMODE(data);
+	((DmacChannel *)hw)->CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVOMODE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_reg(const void *const       hw,
+                                                                       hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHEVCTRL.reg;
+}
+
+static inline bool hri_dmacchannel_get_CHSTATUS_PEND_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHSTATUS_BUSY_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHSTATUS_FERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHSTATUS_CRCERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmacchannel_get_CHSTATUS_reg(const void *const       hw,
+                                                                       hri_dmac_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmacchannel_read_CHSTATUS_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHSTATUS.reg;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_dmac_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_dmac_chintflag_reg_t mask)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask;
+}
+
+static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+	} else {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+	} else {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+	} else {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                            hri_dmac_chintenset_reg_t mask)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = mask;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                 hri_dmac_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg;
+}
+
+static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chintenset_reg_t data)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = data;
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chintenset_reg_t mask)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask;
+}
+
+static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_ENABLE;
+	tmp |= value << DMAC_CHCTRLA_ENABLE_Pos;
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_RUNSTDBY;
+	tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos;
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk;
+	tmp |= DMAC_CHCTRLA_TRIGSRC(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk;
+	tmp |= DMAC_CHCTRLA_TRIGACT(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk;
+	tmp |= DMAC_CHCTRLA_BURSTLEN(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk;
+	tmp |= DMAC_CHCTRLA_THRESHOLD(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chctrla_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+}
+
+static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_dmac_chctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_dmac_chctrlb_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_CMD_Msk;
+	tmp |= DMAC_CHCTRLB_CMD(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_dmac_chctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chctrlb_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+}
+
+static inline void hri_dmac_set_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_dmac_chprilvl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+	tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chprilvl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+	tmp &= ~DMAC_CHPRILVL_PRILVL_Msk;
+	tmp |= DMAC_CHPRILVL_PRILVL(data);
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+	tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_dmac_chprilvl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chprilvl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+}
+
+static inline void hri_dmac_set_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVIE;
+	tmp |= value << DMAC_CHEVCTRL_EVIE_Pos;
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVOE;
+	tmp |= value << DMAC_CHEVCTRL_EVOE_Pos;
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_dmac_chevctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVACT_Msk;
+	tmp |= DMAC_CHEVCTRL_EVACT(data);
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chevctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk;
+	tmp |= DMAC_CHEVCTRL_EVOMODE(data);
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chevctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+}
+
+static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_dmac_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chstatus_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_dmacdescriptor_set_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_set_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_get_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_get_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_write_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_write_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_clear_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_clear_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_toggle_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_toggle_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_read_DSTADDR_CRC_reg(a) hri_dmacdescriptor_read_DSTADDR_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DMAC_D51_H_INCLUDED */
+#endif /* _SAMD51_DMAC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_dsu_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_dsu_d51.h
new file mode 100644
index 0000000..3cf56cc
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_dsu_d51.h
@@ -0,0 +1,1256 @@
+/**
+ * \file
+ *
+ * \brief SAM DSU
+ *
+ * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_DSU_COMPONENT_
+#ifndef _HRI_DSU_D51_H_INCLUDED_
+#define _HRI_DSU_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DSU_CRITICAL_SECTIONS)
+#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DSU_CRITICAL_SECTION_ENTER()
+#define DSU_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_dsu_addr_reg_t;
+typedef uint32_t hri_dsu_cfg_reg_t;
+typedef uint32_t hri_dsu_cid0_reg_t;
+typedef uint32_t hri_dsu_cid1_reg_t;
+typedef uint32_t hri_dsu_cid2_reg_t;
+typedef uint32_t hri_dsu_cid3_reg_t;
+typedef uint32_t hri_dsu_data_reg_t;
+typedef uint32_t hri_dsu_dcc_reg_t;
+typedef uint32_t hri_dsu_did_reg_t;
+typedef uint32_t hri_dsu_end_reg_t;
+typedef uint32_t hri_dsu_entry0_reg_t;
+typedef uint32_t hri_dsu_entry1_reg_t;
+typedef uint32_t hri_dsu_length_reg_t;
+typedef uint32_t hri_dsu_memtype_reg_t;
+typedef uint32_t hri_dsu_pid0_reg_t;
+typedef uint32_t hri_dsu_pid1_reg_t;
+typedef uint32_t hri_dsu_pid2_reg_t;
+typedef uint32_t hri_dsu_pid3_reg_t;
+typedef uint32_t hri_dsu_pid4_reg_t;
+typedef uint32_t hri_dsu_pid5_reg_t;
+typedef uint32_t hri_dsu_pid6_reg_t;
+typedef uint32_t hri_dsu_pid7_reg_t;
+typedef uint8_t  hri_dsu_ctrl_reg_t;
+typedef uint8_t  hri_dsu_statusa_reg_t;
+typedef uint8_t  hri_dsu_statusb_reg_t;
+
+static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos;
+}
+
+static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dsu *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->STATUSB.reg;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->DID.reg;
+}
+
+static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos;
+}
+
+static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ENTRY0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ENTRY0.reg;
+}
+
+static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ENTRY1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ENTRY1.reg;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask)
+{
+	return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->END.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->END.reg;
+}
+
+static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos;
+}
+
+static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->MEMTYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->MEMTYPE.reg;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID4.reg;
+}
+
+static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID5.reg;
+}
+
+static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID6.reg;
+}
+
+static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID7.reg;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask)
+{
+	return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID0.reg;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID1.reg;
+}
+
+static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID2.reg;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID3.reg;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask)
+{
+	return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID0.reg;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID1.reg;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask)
+{
+	return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID2.reg;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask)
+{
+	return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID3.reg;
+}
+
+static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= ~DSU_ADDR_AMOD_Msk;
+	tmp |= DSU_ADDR_AMOD(data);
+	((Dsu *)hw)->ADDR.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= ~DSU_ADDR_ADDR_Msk;
+	tmp |= DSU_ADDR_ADDR(data);
+	((Dsu *)hw)->ADDR.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ADDR.reg;
+}
+
+static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp &= ~DSU_LENGTH_LENGTH_Msk;
+	tmp |= DSU_LENGTH_LENGTH(data);
+	((Dsu *)hw)->LENGTH.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->LENGTH.reg;
+}
+
+static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp &= ~DSU_DATA_DATA_Msk;
+	tmp |= DSU_DATA_DATA(data);
+	((Dsu *)hw)->DATA.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->DATA.reg;
+}
+
+static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp &= ~DSU_DCC_DATA_Msk;
+	tmp |= DSU_DCC_DATA(data);
+	((Dsu *)hw)->DCC[index].reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index)
+{
+	return ((Dsu *)hw)->DCC[index].reg;
+}
+
+static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp &= ~DSU_CFG_ETBRAMEN;
+	tmp |= value << DSU_CFG_ETBRAMEN_Pos;
+	((Dsu *)hw)->CFG.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp &= ~DSU_CFG_LQOS_Msk;
+	tmp |= DSU_CFG_LQOS(data);
+	((Dsu *)hw)->CFG.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp &= ~DSU_CFG_DCCDMALEVEL_Msk;
+	tmp |= DSU_CFG_DCCDMALEVEL(data);
+	((Dsu *)hw)->CFG.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CFG.reg;
+}
+
+static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dsu *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->STATUSA.reg;
+}
+
+static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CTRL.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DSU_D51_H_INCLUDED */
+#endif /* _SAMD51_DSU_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_eic_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_eic_d51.h
new file mode 100644
index 0000000..8f20ba9
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_eic_d51.h
@@ -0,0 +1,1838 @@
+/**
+ * \file
+ *
+ * \brief SAM EIC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_EIC_COMPONENT_
+#ifndef _HRI_EIC_D51_H_INCLUDED_
+#define _HRI_EIC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_EIC_CRITICAL_SECTIONS)
+#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define EIC_CRITICAL_SECTION_ENTER()
+#define EIC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_eic_nmiflag_reg_t;
+typedef uint32_t hri_eic_asynch_reg_t;
+typedef uint32_t hri_eic_config_reg_t;
+typedef uint32_t hri_eic_debouncen_reg_t;
+typedef uint32_t hri_eic_dprescaler_reg_t;
+typedef uint32_t hri_eic_evctrl_reg_t;
+typedef uint32_t hri_eic_intenset_reg_t;
+typedef uint32_t hri_eic_intflag_reg_t;
+typedef uint32_t hri_eic_pinstate_reg_t;
+typedef uint32_t hri_eic_syncbusy_reg_t;
+typedef uint8_t  hri_eic_ctrla_reg_t;
+typedef uint8_t  hri_eic_nmictrl_reg_t;
+
+static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg)
+{
+	while (((Eic *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg)
+{
+	return ((Eic *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw)
+{
+	return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos;
+}
+
+static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw)
+{
+	((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI;
+}
+
+static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Eic *)hw)->NMIFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->NMIFLAG.reg;
+}
+
+static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
+{
+	((Eic *)hw)->NMIFLAG.reg = mask;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	((Eic *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask);
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos;
+	return tmp;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data);
+	((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data);
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask);
+}
+
+static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTENSET.reg;
+}
+
+static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data)
+{
+	((Eic *)hw)->INTENSET.reg = data;
+	((Eic *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Eic *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_PINSTATE_bf(const void *const hw, hri_eic_pinstate_reg_t mask)
+{
+	return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE(mask)) >> EIC_PINSTATE_PINSTATE_Pos;
+}
+
+static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_PINSTATE_bf(const void *const hw)
+{
+	return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE_Msk) >> EIC_PINSTATE_PINSTATE_Pos;
+}
+
+static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_reg(const void *const hw, hri_eic_pinstate_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->PINSTATE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_reg(const void *const hw)
+{
+	return ((Eic *)hw)->PINSTATE.reg;
+}
+
+static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= ~EIC_CTRLA_ENABLE;
+	tmp |= value << EIC_CTRLA_ENABLE_Pos;
+	((Eic *)hw)->CTRLA.reg = tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= ~EIC_CTRLA_CKSEL;
+	tmp |= value << EIC_CTRLA_CKSEL_Pos;
+	((Eic *)hw)->CTRLA.reg = tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg = data;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw)
+{
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	return ((Eic *)hw)->CTRLA.reg;
+}
+
+static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMIFILTEN;
+	tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos;
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMIASYNCH;
+	tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos;
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMISENSE_Msk;
+	tmp |= EIC_NMICTRL_NMISENSE(data);
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->NMICTRL.reg;
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO_Msk;
+	tmp |= EIC_EVCTRL_EXTINTEO(data);
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp &= ~EIC_ASYNCH_ASYNCH_Msk;
+	tmp |= EIC_ASYNCH_ASYNCH(data);
+	((Eic *)hw)->ASYNCH.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw)
+{
+	return ((Eic *)hw)->ASYNCH.reg;
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN0;
+	tmp |= value << EIC_CONFIG_FILTEN0_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN1;
+	tmp |= value << EIC_CONFIG_FILTEN1_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN2;
+	tmp |= value << EIC_CONFIG_FILTEN2_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN3;
+	tmp |= value << EIC_CONFIG_FILTEN3_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN4;
+	tmp |= value << EIC_CONFIG_FILTEN4_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN5;
+	tmp |= value << EIC_CONFIG_FILTEN5_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN6;
+	tmp |= value << EIC_CONFIG_FILTEN6_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN7;
+	tmp |= value << EIC_CONFIG_FILTEN7_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE0_Msk;
+	tmp |= EIC_CONFIG_SENSE0(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE1_Msk;
+	tmp |= EIC_CONFIG_SENSE1(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE2_Msk;
+	tmp |= EIC_CONFIG_SENSE2(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE3_Msk;
+	tmp |= EIC_CONFIG_SENSE3(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE4_Msk;
+	tmp |= EIC_CONFIG_SENSE4(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE5_Msk;
+	tmp |= EIC_CONFIG_SENSE5(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE6_Msk;
+	tmp |= EIC_CONFIG_SENSE6(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE7_Msk;
+	tmp |= EIC_CONFIG_SENSE7(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index,
+                                                          hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index)
+{
+	return ((Eic *)hw)->CONFIG[index].reg;
+}
+
+static inline void hri_eic_set_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg |= EIC_DEBOUNCEN_DEBOUNCEN(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_DEBOUNCEN_bf(const void *const       hw,
+                                                                         hri_eic_debouncen_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DEBOUNCEN.reg;
+	tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN(mask)) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DEBOUNCEN.reg;
+	tmp &= ~EIC_DEBOUNCEN_DEBOUNCEN_Msk;
+	tmp |= EIC_DEBOUNCEN_DEBOUNCEN(data);
+	((Eic *)hw)->DEBOUNCEN.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg &= ~EIC_DEBOUNCEN_DEBOUNCEN(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg ^= EIC_DEBOUNCEN_DEBOUNCEN(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DEBOUNCEN.reg;
+	tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN_Msk) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DEBOUNCEN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_reg(const void *const hw)
+{
+	return ((Eic *)hw)->DEBOUNCEN.reg;
+}
+
+static inline void hri_eic_set_DPRESCALER_STATES0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_DPRESCALER_STATES0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_STATES0) >> EIC_DPRESCALER_STATES0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_STATES0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_STATES0;
+	tmp |= value << EIC_DPRESCALER_STATES0_Pos;
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_STATES0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_STATES0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_DPRESCALER_STATES1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_DPRESCALER_STATES1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_STATES1) >> EIC_DPRESCALER_STATES1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_STATES1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_STATES1;
+	tmp |= value << EIC_DPRESCALER_STATES1_Pos;
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_STATES1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_STATES1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_DPRESCALER_TICKON_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_TICKON;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_DPRESCALER_TICKON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_TICKON) >> EIC_DPRESCALER_TICKON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_TICKON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_TICKON;
+	tmp |= value << EIC_DPRESCALER_TICKON_Pos;
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_TICKON_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_TICKON;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_TICKON_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_TICKON;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER0_bf(const void *const        hw,
+                                                                            hri_eic_dprescaler_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_PRESCALER0(mask)) >> EIC_DPRESCALER_PRESCALER0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_PRESCALER0_Msk;
+	tmp |= EIC_DPRESCALER_PRESCALER0(data);
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_PRESCALER0_Msk) >> EIC_DPRESCALER_PRESCALER0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER1_bf(const void *const        hw,
+                                                                            hri_eic_dprescaler_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_PRESCALER1(mask)) >> EIC_DPRESCALER_PRESCALER1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_PRESCALER1_Msk;
+	tmp |= EIC_DPRESCALER_PRESCALER1(data);
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_PRESCALER1_Msk) >> EIC_DPRESCALER_PRESCALER1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_reg(const void *const hw)
+{
+	return ((Eic *)hw)->DPRESCALER.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_EIC_D51_H_INCLUDED */
+#endif /* _SAMD51_EIC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_evsys_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_evsys_d51.h
new file mode 100644
index 0000000..f35dceb
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_evsys_d51.h
@@ -0,0 +1,1707 @@
+/**
+ * \file
+ *
+ * \brief SAM EVSYS
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_EVSYS_COMPONENT_
+#ifndef _HRI_EVSYS_D51_H_INCLUDED_
+#define _HRI_EVSYS_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS)
+#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define EVSYS_CRITICAL_SECTION_ENTER()
+#define EVSYS_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_evsys_intpend_reg_t;
+typedef uint32_t hri_evsys_busych_reg_t;
+typedef uint32_t hri_evsys_channel_reg_t;
+typedef uint32_t hri_evsys_intstatus_reg_t;
+typedef uint32_t hri_evsys_readyusr_reg_t;
+typedef uint32_t hri_evsys_swevt_reg_t;
+typedef uint32_t hri_evsys_user_reg_t;
+typedef uint32_t hri_evsyschannel_channel_reg_t;
+typedef uint8_t  hri_evsys_chintenset_reg_t;
+typedef uint8_t  hri_evsys_chintflag_reg_t;
+typedef uint8_t  hri_evsys_chstatus_reg_t;
+typedef uint8_t  hri_evsys_ctrla_reg_t;
+typedef uint8_t  hri_evsys_prictrl_reg_t;
+typedef uint8_t  hri_evsyschannel_chintenset_reg_t;
+typedef uint8_t  hri_evsyschannel_chintflag_reg_t;
+typedef uint8_t  hri_evsyschannel_chstatus_reg_t;
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT9) >> EVSYS_INTSTATUS_CHINT9_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT10) >> EVSYS_INTSTATUS_CHINT10_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT11) >> EVSYS_INTSTATUS_CHINT11_Pos;
+}
+
+static inline hri_evsys_intstatus_reg_t hri_evsys_get_INTSTATUS_reg(const void *const         hw,
+                                                                    hri_evsys_intstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->INTSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_intstatus_reg_t hri_evsys_read_INTSTATUS_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->INTSTATUS.reg;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH0) >> EVSYS_BUSYCH_BUSYCH0_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH1) >> EVSYS_BUSYCH_BUSYCH1_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH2) >> EVSYS_BUSYCH_BUSYCH2_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH3) >> EVSYS_BUSYCH_BUSYCH3_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH4) >> EVSYS_BUSYCH_BUSYCH4_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH5) >> EVSYS_BUSYCH_BUSYCH5_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH6) >> EVSYS_BUSYCH_BUSYCH6_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH7) >> EVSYS_BUSYCH_BUSYCH7_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH8) >> EVSYS_BUSYCH_BUSYCH8_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH9) >> EVSYS_BUSYCH_BUSYCH9_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH10) >> EVSYS_BUSYCH_BUSYCH10_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH11) >> EVSYS_BUSYCH_BUSYCH11_Pos;
+}
+
+static inline hri_evsys_busych_reg_t hri_evsys_get_BUSYCH_reg(const void *const hw, hri_evsys_busych_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->BUSYCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_busych_reg_t hri_evsys_read_BUSYCH_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->BUSYCH.reg;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR0) >> EVSYS_READYUSR_READYUSR0_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR1) >> EVSYS_READYUSR_READYUSR1_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR2) >> EVSYS_READYUSR_READYUSR2_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR3) >> EVSYS_READYUSR_READYUSR3_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR4) >> EVSYS_READYUSR_READYUSR4_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR5) >> EVSYS_READYUSR_READYUSR5_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR6) >> EVSYS_READYUSR_READYUSR6_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR7) >> EVSYS_READYUSR_READYUSR7_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR8) >> EVSYS_READYUSR_READYUSR8_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR9) >> EVSYS_READYUSR_READYUSR9_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR10) >> EVSYS_READYUSR_READYUSR10_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR11) >> EVSYS_READYUSR_READYUSR11_Pos;
+}
+
+static inline hri_evsys_readyusr_reg_t hri_evsys_get_READYUSR_reg(const void *const hw, hri_evsys_readyusr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->READYUSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_readyusr_reg_t hri_evsys_read_READYUSR_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->READYUSR.reg;
+}
+
+static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->CTRLA.reg;
+	tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->CTRLA.reg;
+}
+
+static inline void hri_evsys_set_PRICTRL_RREN_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_RREN;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_PRICTRL_RREN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp = (tmp & EVSYS_PRICTRL_RREN) >> EVSYS_PRICTRL_RREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_PRICTRL_RREN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp &= ~EVSYS_PRICTRL_RREN;
+	tmp |= value << EVSYS_PRICTRL_RREN_Pos;
+	((Evsys *)hw)->PRICTRL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_PRICTRL_RREN_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_RREN;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_PRICTRL_RREN_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_RREN;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_PRI(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp = (tmp & EVSYS_PRICTRL_PRI(mask)) >> EVSYS_PRICTRL_PRI_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t data)
+{
+	uint8_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp &= ~EVSYS_PRICTRL_PRI_Msk;
+	tmp |= EVSYS_PRICTRL_PRI(data);
+	((Evsys *)hw)->PRICTRL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_PRI(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_PRI(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_PRI_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp = (tmp & EVSYS_PRICTRL_PRI_Msk) >> EVSYS_PRICTRL_PRI_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->PRICTRL.reg;
+}
+
+static inline void hri_evsys_set_INTPEND_OVR_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_OVR;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_INTPEND_OVR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_OVR) >> EVSYS_INTPEND_OVR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_OVR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_OVR;
+	tmp |= value << EVSYS_INTPEND_OVR_Pos;
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_OVR_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_OVR;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_OVR_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_OVR;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_INTPEND_EVD_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_EVD;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_INTPEND_EVD_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_EVD) >> EVSYS_INTPEND_EVD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_EVD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_EVD;
+	tmp |= value << EVSYS_INTPEND_EVD_Pos;
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_EVD_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_EVD;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_EVD_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_EVD;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_INTPEND_READY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_READY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_INTPEND_READY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_READY) >> EVSYS_INTPEND_READY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_READY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_READY;
+	tmp |= value << EVSYS_INTPEND_READY_Pos;
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_READY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_READY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_READY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_READY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_INTPEND_BUSY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_BUSY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_INTPEND_BUSY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_BUSY) >> EVSYS_INTPEND_BUSY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_BUSY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_BUSY;
+	tmp |= value << EVSYS_INTPEND_BUSY_Pos;
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_BUSY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_BUSY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_BUSY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_BUSY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_ID(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_ID(mask)) >> EVSYS_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t data)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_ID_Msk;
+	tmp |= EVSYS_INTPEND_ID(data);
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_ID(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_ID(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_ID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_ID_Msk) >> EVSYS_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->INTPEND.reg;
+}
+
+static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index,
+                                                                 hri_evsys_user_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp &= ~EVSYS_USER_CHANNEL_Msk;
+	tmp |= EVSYS_USER_CHANNEL(data);
+	((Evsys *)hw)->USER[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index,
+                                                          hri_evsys_user_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index)
+{
+	return ((Evsys *)hw)->USER[index].reg;
+}
+
+static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->SWEVT.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsyschannel_get_CHINTFLAG_OVR_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos;
+}
+
+static inline void hri_evsyschannel_clear_CHINTFLAG_OVR_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR;
+}
+
+static inline bool hri_evsyschannel_get_CHINTFLAG_EVD_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos;
+}
+
+static inline void hri_evsyschannel_clear_CHINTFLAG_EVD_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD;
+}
+
+static inline bool hri_evsyschannel_get_interrupt_OVR_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos;
+}
+
+static inline void hri_evsyschannel_clear_interrupt_OVR_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR;
+}
+
+static inline bool hri_evsyschannel_get_interrupt_EVD_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos;
+}
+
+static inline void hri_evsyschannel_clear_interrupt_EVD_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD;
+}
+
+static inline hri_evsys_chintflag_reg_t hri_evsyschannel_get_CHINTFLAG_reg(const void *const         hw,
+                                                                           hri_evsys_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chintflag_reg_t hri_evsyschannel_read_CHINTFLAG_reg(const void *const hw)
+{
+	return ((EvsysChannel *)hw)->CHINTFLAG.reg;
+}
+
+static inline void hri_evsyschannel_clear_CHINTFLAG_reg(const void *const hw, hri_evsys_chintflag_reg_t mask)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = mask;
+}
+
+static inline void hri_evsyschannel_set_CHINTEN_OVR_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR;
+}
+
+static inline bool hri_evsyschannel_get_CHINTEN_OVR_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos;
+}
+
+static inline void hri_evsyschannel_write_CHINTEN_OVR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR;
+	} else {
+		((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR;
+	}
+}
+
+static inline void hri_evsyschannel_clear_CHINTEN_OVR_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR;
+}
+
+static inline void hri_evsyschannel_set_CHINTEN_EVD_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD;
+}
+
+static inline bool hri_evsyschannel_get_CHINTEN_EVD_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos;
+}
+
+static inline void hri_evsyschannel_write_CHINTEN_EVD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD;
+	} else {
+		((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD;
+	}
+}
+
+static inline void hri_evsyschannel_clear_CHINTEN_EVD_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD;
+}
+
+static inline void hri_evsyschannel_set_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask)
+{
+	((EvsysChannel *)hw)->CHINTENSET.reg = mask;
+}
+
+static inline hri_evsys_chintenset_reg_t hri_evsyschannel_get_CHINTEN_reg(const void *const          hw,
+                                                                          hri_evsys_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chintenset_reg_t hri_evsyschannel_read_CHINTEN_reg(const void *const hw)
+{
+	return ((EvsysChannel *)hw)->CHINTENSET.reg;
+}
+
+static inline void hri_evsyschannel_write_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t data)
+{
+	((EvsysChannel *)hw)->CHINTENSET.reg = data;
+	((EvsysChannel *)hw)->CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_evsyschannel_clear_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask)
+{
+	((EvsysChannel *)hw)->CHINTENCLR.reg = mask;
+}
+
+static inline bool hri_evsyschannel_get_CHSTATUS_RDYUSR_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos;
+}
+
+static inline bool hri_evsyschannel_get_CHSTATUS_BUSYCH_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsyschannel_get_CHSTATUS_reg(const void *const        hw,
+                                                                         hri_evsys_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsyschannel_read_CHSTATUS_reg(const void *const hw)
+{
+	return ((EvsysChannel *)hw)->CHSTATUS.reg;
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_RUNSTDBY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_RUNSTDBY;
+	tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos;
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_RUNSTDBY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_ONDEMAND_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsyschannel_get_CHANNEL_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_ONDEMAND;
+	tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos;
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_ONDEMAND_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_ONDEMAND_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EVGEN_bf(const void *const       hw,
+                                                                            hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EVGEN_Msk;
+	tmp |= EVSYS_CHANNEL_EVGEN(data);
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EVGEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_PATH_bf(const void *const       hw,
+                                                                           hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_PATH_Msk;
+	tmp |= EVSYS_CHANNEL_PATH(data);
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_PATH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EDGSEL_bf(const void *const       hw,
+                                                                             hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk;
+	tmp |= EVSYS_CHANNEL_EDGSEL(data);
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EDGSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_reg(const void *const       hw,
+                                                                       hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_reg(const void *const hw)
+{
+	return ((EvsysChannel *)hw)->CHANNEL.reg;
+}
+
+static inline bool hri_evsys_get_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos;
+}
+
+static inline void hri_evsys_clear_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR;
+}
+
+static inline bool hri_evsys_get_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos;
+}
+
+static inline void hri_evsys_clear_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD;
+}
+
+static inline hri_evsys_chintflag_reg_t hri_evsys_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_evsys_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chintflag_reg_t hri_evsys_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg;
+}
+
+static inline void hri_evsys_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_evsys_chintflag_reg_t mask)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask;
+}
+
+static inline void hri_evsys_set_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR;
+}
+
+static inline bool hri_evsys_get_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos;
+}
+
+static inline void hri_evsys_write_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR;
+	} else {
+		((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR;
+	}
+}
+
+static inline void hri_evsys_clear_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR;
+}
+
+static inline void hri_evsys_set_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD;
+}
+
+static inline bool hri_evsys_get_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos;
+}
+
+static inline void hri_evsys_write_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD;
+	} else {
+		((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD;
+	}
+}
+
+static inline void hri_evsys_clear_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD;
+}
+
+static inline void hri_evsys_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_evsys_chintenset_reg_t mask)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = mask;
+}
+
+static inline hri_evsys_chintenset_reg_t hri_evsys_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                   hri_evsys_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chintenset_reg_t hri_evsys_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg;
+}
+
+static inline void hri_evsys_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_evsys_chintenset_reg_t data)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data;
+	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_evsys_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_evsys_chintenset_reg_t mask)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_RDYUSR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_BUSYCH_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_evsys_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg;
+}
+
+static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_RUNSTDBY;
+	tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos;
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_ONDEMAND;
+	tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos;
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EVGEN_Msk;
+	tmp |= EVSYS_CHANNEL_EVGEN(data);
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_PATH_Msk;
+	tmp |= EVSYS_CHANNEL_PATH(data);
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk;
+	tmp |= EVSYS_CHANNEL_EDGSEL(data);
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_evsys_channel_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_EVSYS_D51_H_INCLUDED */
+#endif /* _SAMD51_EVSYS_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_freqm_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_freqm_d51.h
new file mode 100644
index 0000000..c6fc15d
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_freqm_d51.h
@@ -0,0 +1,464 @@
+/**
+ * \file
+ *
+ * \brief SAM FREQM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_FREQM_COMPONENT_
+#ifndef _HRI_FREQM_D51_H_INCLUDED_
+#define _HRI_FREQM_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_FREQM_CRITICAL_SECTIONS)
+#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define FREQM_CRITICAL_SECTION_ENTER()
+#define FREQM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_freqm_cfga_reg_t;
+typedef uint32_t hri_freqm_syncbusy_reg_t;
+typedef uint32_t hri_freqm_value_reg_t;
+typedef uint8_t  hri_freqm_ctrla_reg_t;
+typedef uint8_t  hri_freqm_ctrlb_reg_t;
+typedef uint8_t  hri_freqm_intenset_reg_t;
+typedef uint8_t  hri_freqm_intflag_reg_t;
+typedef uint8_t  hri_freqm_status_reg_t;
+
+static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg)
+{
+	while (((Freqm *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg)
+{
+	return ((Freqm *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
+}
+
+static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
+}
+
+static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
+{
+	((Freqm *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
+}
+
+static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos;
+}
+
+static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
+	} else {
+		((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
+	}
+}
+
+static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
+}
+
+static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	((Freqm *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->INTENSET.reg;
+}
+
+static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data)
+{
+	((Freqm *)hw)->INTENSET.reg = data;
+	((Freqm *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	((Freqm *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Freqm *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask)
+{
+	return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw)
+{
+	return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Freqm *)hw)->VALUE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->VALUE.reg;
+}
+
+static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	FREQM_CRITICAL_SECTION_ENTER();
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp &= ~FREQM_CTRLA_ENABLE;
+	tmp |= value << FREQM_CTRLA_ENABLE_Pos;
+	((Freqm *)hw)->CTRLA.reg = tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg = data;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg &= ~mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg ^= mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw)
+{
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	return ((Freqm *)hw)->CTRLA.reg;
+}
+
+static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data)
+{
+	uint16_t tmp;
+	FREQM_CRITICAL_SECTION_ENTER();
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp &= ~FREQM_CFGA_REFNUM_Msk;
+	tmp |= FREQM_CFGA_REFNUM(data);
+	((Freqm *)hw)->CFGA.reg = tmp;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg |= mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg = data;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg &= ~mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg ^= mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->CFGA.reg;
+}
+
+static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos;
+}
+
+static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos;
+}
+
+static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->STATUS.reg;
+}
+
+static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLB.reg = data;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_FREQM_D51_H_INCLUDED */
+#endif /* _SAMD51_FREQM_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_gclk_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_gclk_d51.h
new file mode 100644
index 0000000..48a5354
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_gclk_d51.h
@@ -0,0 +1,805 @@
+/**
+ * \file
+ *
+ * \brief SAM GCLK
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_GCLK_COMPONENT_
+#ifndef _HRI_GCLK_D51_H_INCLUDED_
+#define _HRI_GCLK_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_GCLK_CRITICAL_SECTIONS)
+#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define GCLK_CRITICAL_SECTION_ENTER()
+#define GCLK_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_gclk_genctrl_reg_t;
+typedef uint32_t hri_gclk_pchctrl_reg_t;
+typedef uint32_t hri_gclk_syncbusy_reg_t;
+typedef uint8_t  hri_gclk_ctrla_reg_t;
+
+static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg)
+{
+	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg)
+{
+	return ((Gclk *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL9_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL9) >> GCLK_SYNCBUSY_GENCTRL9_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL10_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL10) >> GCLK_SYNCBUSY_GENCTRL10_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL11_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL11) >> GCLK_SYNCBUSY_GENCTRL11_Pos;
+}
+
+static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Gclk *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	tmp = ((Gclk *)hw)->CTRLA.reg;
+	tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg |= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	tmp = ((Gclk *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg = data;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg &= ~mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg ^= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw)
+{
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	return ((Gclk *)hw)->CTRLA.reg;
+}
+
+static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_GENEN;
+	tmp |= value << GCLK_GENCTRL_GENEN_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_IDC;
+	tmp |= value << GCLK_GENCTRL_IDC_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_OOV;
+	tmp |= value << GCLK_GENCTRL_OOV_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_OE;
+	tmp |= value << GCLK_GENCTRL_OE_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_DIVSEL;
+	tmp |= value << GCLK_GENCTRL_DIVSEL_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_RUNSTDBY;
+	tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_SRC_Msk;
+	tmp |= GCLK_GENCTRL_SRC(data);
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_DIV_Msk;
+	tmp |= GCLK_GENCTRL_DIV(data);
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index,
+                                                              hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg = data;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	return ((Gclk *)hw)->GENCTRL[index].reg;
+}
+
+static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_CHEN;
+	tmp |= value << GCLK_PCHCTRL_CHEN_Pos;
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_WRTLOCK;
+	tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos;
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_pchctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_GEN_Msk;
+	tmp |= GCLK_PCHCTRL_GEN(data);
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index,
+                                                              hri_gclk_pchctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg = data;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Gclk *)hw)->PCHCTRL[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_GCLK_D51_H_INCLUDED */
+#endif /* _SAMD51_GCLK_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_hmatrixb_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_hmatrixb_d51.h
new file mode 100644
index 0000000..6567771
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_hmatrixb_d51.h
@@ -0,0 +1,237 @@
+/**
+ * \file
+ *
+ * \brief SAM HMATRIXB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_HMATRIXB_COMPONENT_
+#ifndef _HRI_HMATRIXB_D51_H_INCLUDED_
+#define _HRI_HMATRIXB_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS)
+#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define HMATRIXB_CRITICAL_SECTION_ENTER()
+#define HMATRIXB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_hmatrixb_pras_reg_t;
+typedef uint32_t hri_hmatrixb_prbs_reg_t;
+typedef uint32_t hri_hmatrixbprs_pras_reg_t;
+typedef uint32_t hri_hmatrixbprs_prbs_reg_t;
+
+static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((HmatrixbPrs *)hw)->PRAS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw)
+{
+	return ((HmatrixbPrs *)hw)->PRAS.reg;
+}
+
+static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((HmatrixbPrs *)hw)->PRBS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw)
+{
+	return ((HmatrixbPrs *)hw)->PRBS.reg;
+}
+
+static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_hmatrixb_pras_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_pras_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg;
+}
+
+static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_hmatrixb_prbs_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_prbs_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_HMATRIXB_D51_H_INCLUDED */
+#endif /* _SAMD51_HMATRIXB_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_i2s_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_i2s_d51.h
new file mode 100644
index 0000000..547ba15
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_i2s_d51.h
@@ -0,0 +1,3032 @@
+/**
+ * \file
+ *
+ * \brief SAM I2S
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_I2S_COMPONENT_
+#ifndef _HRI_I2S_D51_H_INCLUDED_
+#define _HRI_I2S_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_I2S_CRITICAL_SECTIONS)
+#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define I2S_CRITICAL_SECTION_ENTER()
+#define I2S_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_i2s_intenset_reg_t;
+typedef uint16_t hri_i2s_intflag_reg_t;
+typedef uint16_t hri_i2s_syncbusy_reg_t;
+typedef uint32_t hri_i2s_clkctrl_reg_t;
+typedef uint32_t hri_i2s_rxctrl_reg_t;
+typedef uint32_t hri_i2s_rxdata_reg_t;
+typedef uint32_t hri_i2s_txctrl_reg_t;
+typedef uint32_t hri_i2s_txdata_reg_t;
+typedef uint8_t  hri_i2s_ctrla_reg_t;
+
+static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg)
+{
+	while (((I2s *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg)
+{
+	return ((I2s *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1;
+}
+
+static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0;
+}
+
+static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1;
+}
+
+static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0;
+}
+
+static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1;
+}
+
+static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0;
+}
+
+static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1;
+}
+
+static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0;
+}
+
+static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1;
+}
+
+static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((I2s *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw)
+{
+	return ((I2s *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask)
+{
+	((I2s *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0;
+}
+
+static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0;
+}
+
+static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1;
+}
+
+static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1;
+}
+
+static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0;
+}
+
+static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0;
+}
+
+static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1;
+}
+
+static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1;
+}
+
+static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0;
+}
+
+static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0;
+}
+
+static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1;
+}
+
+static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1;
+}
+
+static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0;
+}
+
+static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0;
+}
+
+static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1;
+}
+
+static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1;
+}
+
+static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
+{
+	((I2s *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((I2s *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw)
+{
+	return ((I2s *)hw)->INTENSET.reg;
+}
+
+static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data)
+{
+	((I2s *)hw)->INTENSET.reg = data;
+	((I2s *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
+{
+	((I2s *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_TXEN_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXEN) >> I2S_SYNCBUSY_TXEN_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_RXEN_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXEN) >> I2S_SYNCBUSY_RXEN_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_TXDATA_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXDATA) >> I2S_SYNCBUSY_TXDATA_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_RXDATA_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXDATA) >> I2S_SYNCBUSY_RXDATA_Pos;
+}
+
+static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((I2s *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((I2s *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_DATA_bf(const void *const hw, hri_i2s_rxdata_reg_t mask)
+{
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA(mask)) >> I2S_RXDATA_DATA_Pos;
+}
+
+static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_DATA_bf(const void *const hw)
+{
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA_Msk) >> I2S_RXDATA_DATA_Pos;
+}
+
+static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_reg(const void *const hw, hri_i2s_rxdata_reg_t mask)
+{
+	uint32_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	tmp = ((I2s *)hw)->RXDATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_reg(const void *const hw)
+{
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	return ((I2s *)hw)->RXDATA.reg;
+}
+
+static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_ENABLE;
+	tmp |= value << I2S_CTRLA_ENABLE_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_CKEN0;
+	tmp |= value << I2S_CTRLA_CKEN0_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_CKEN1;
+	tmp |= value << I2S_CTRLA_CKEN1_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_TXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_TXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_TXEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_TXEN) >> I2S_CTRLA_TXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_TXEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_TXEN;
+	tmp |= value << I2S_CTRLA_TXEN_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_TXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_TXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_TXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_TXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_RXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_RXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_RXEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_RXEN) >> I2S_CTRLA_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_RXEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_RXEN;
+	tmp |= value << I2S_CTRLA_RXEN_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_RXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_RXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_RXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_RXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= mask;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg = data;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~mask;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= mask;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw)
+{
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	return ((I2s *)hw)->CTRLA.reg;
+}
+
+static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_BITDELAY;
+	tmp |= value << I2S_CLKCTRL_BITDELAY_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSSEL;
+	tmp |= value << I2S_CLKCTRL_FSSEL_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSINV;
+	tmp |= value << I2S_CLKCTRL_FSINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSOUTINV;
+	tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_SCKSEL;
+	tmp |= value << I2S_CLKCTRL_SCKSEL_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_SCKOUTINV;
+	tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKSEL;
+	tmp |= value << I2S_CLKCTRL_MCKSEL_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKEN;
+	tmp |= value << I2S_CLKCTRL_MCKEN_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKOUTINV;
+	tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index,
+                                                                    hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk;
+	tmp |= I2S_CLKCTRL_SLOTSIZE(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index,
+                                                                   hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk;
+	tmp |= I2S_CLKCTRL_NBSLOTS(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index,
+                                                                   hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk;
+	tmp |= I2S_CLKCTRL_FSWIDTH(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index,
+                                                                  hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKDIV_Msk;
+	tmp |= I2S_CLKCTRL_MCKDIV(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index,
+                                                                     hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk;
+	tmp |= I2S_CLKCTRL_MCKOUTDIV(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((I2s *)hw)->CLKCTRL[index].reg;
+}
+
+static inline void hri_i2s_set_TXCTRL_TXSAME_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXSAME;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_TXSAME_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_TXSAME) >> I2S_TXCTRL_TXSAME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_TXSAME_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_TXSAME;
+	tmp |= value << I2S_TXCTRL_TXSAME_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_TXSAME_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXSAME;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_TXSAME_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXSAME;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTADJ) >> I2S_TXCTRL_SLOTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTADJ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTADJ;
+	tmp |= value << I2S_TXCTRL_SLOTADJ_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_WORDADJ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_WORDADJ) >> I2S_TXCTRL_WORDADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_WORDADJ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_WORDADJ;
+	tmp |= value << I2S_TXCTRL_WORDADJ_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_BITREV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_BITREV) >> I2S_TXCTRL_BITREV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_BITREV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_BITREV;
+	tmp |= value << I2S_TXCTRL_BITREV_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS0) >> I2S_TXCTRL_SLOTDIS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS0;
+	tmp |= value << I2S_TXCTRL_SLOTDIS0_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS1) >> I2S_TXCTRL_SLOTDIS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS1;
+	tmp |= value << I2S_TXCTRL_SLOTDIS1_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS2) >> I2S_TXCTRL_SLOTDIS2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS2;
+	tmp |= value << I2S_TXCTRL_SLOTDIS2_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS3) >> I2S_TXCTRL_SLOTDIS3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS3;
+	tmp |= value << I2S_TXCTRL_SLOTDIS3_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS4) >> I2S_TXCTRL_SLOTDIS4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS4;
+	tmp |= value << I2S_TXCTRL_SLOTDIS4_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS5) >> I2S_TXCTRL_SLOTDIS5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS5;
+	tmp |= value << I2S_TXCTRL_SLOTDIS5_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS6) >> I2S_TXCTRL_SLOTDIS6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS6;
+	tmp |= value << I2S_TXCTRL_SLOTDIS6_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS7) >> I2S_TXCTRL_SLOTDIS7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS7;
+	tmp |= value << I2S_TXCTRL_SLOTDIS7_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_MONO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_MONO) >> I2S_TXCTRL_MONO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_MONO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_MONO;
+	tmp |= value << I2S_TXCTRL_MONO_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_DMA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_DMA) >> I2S_TXCTRL_DMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_DMA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_DMA;
+	tmp |= value << I2S_TXCTRL_DMA_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXDEFAULT(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_TXDEFAULT(mask)) >> I2S_TXCTRL_TXDEFAULT_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_TXDEFAULT_Msk;
+	tmp |= I2S_TXCTRL_TXDEFAULT(data);
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXDEFAULT(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXDEFAULT(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_TXDEFAULT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_TXDEFAULT_Msk) >> I2S_TXCTRL_TXDEFAULT_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_DATASIZE(mask)) >> I2S_TXCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_DATASIZE_Msk;
+	tmp |= I2S_TXCTRL_DATASIZE(data);
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_DATASIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_DATASIZE_Msk) >> I2S_TXCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_EXTEND(mask)) >> I2S_TXCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_EXTEND_Msk;
+	tmp |= I2S_TXCTRL_EXTEND(data);
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_EXTEND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_EXTEND_Msk) >> I2S_TXCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_reg(const void *const hw)
+{
+	return ((I2s *)hw)->TXCTRL.reg;
+}
+
+static inline void hri_i2s_set_RXCTRL_CLKSEL_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_CLKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_CLKSEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_CLKSEL) >> I2S_RXCTRL_CLKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_CLKSEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_CLKSEL;
+	tmp |= value << I2S_RXCTRL_CLKSEL_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_CLKSEL_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_CLKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_CLKSEL_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_CLKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTADJ) >> I2S_RXCTRL_SLOTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTADJ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTADJ;
+	tmp |= value << I2S_RXCTRL_SLOTADJ_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_WORDADJ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_WORDADJ) >> I2S_RXCTRL_WORDADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_WORDADJ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_WORDADJ;
+	tmp |= value << I2S_RXCTRL_WORDADJ_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_BITREV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_BITREV) >> I2S_RXCTRL_BITREV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_BITREV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_BITREV;
+	tmp |= value << I2S_RXCTRL_BITREV_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS0) >> I2S_RXCTRL_SLOTDIS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS0;
+	tmp |= value << I2S_RXCTRL_SLOTDIS0_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS1) >> I2S_RXCTRL_SLOTDIS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS1;
+	tmp |= value << I2S_RXCTRL_SLOTDIS1_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS2) >> I2S_RXCTRL_SLOTDIS2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS2;
+	tmp |= value << I2S_RXCTRL_SLOTDIS2_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS3) >> I2S_RXCTRL_SLOTDIS3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS3;
+	tmp |= value << I2S_RXCTRL_SLOTDIS3_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS4) >> I2S_RXCTRL_SLOTDIS4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS4;
+	tmp |= value << I2S_RXCTRL_SLOTDIS4_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS5) >> I2S_RXCTRL_SLOTDIS5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS5;
+	tmp |= value << I2S_RXCTRL_SLOTDIS5_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS6) >> I2S_RXCTRL_SLOTDIS6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS6;
+	tmp |= value << I2S_RXCTRL_SLOTDIS6_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS7) >> I2S_RXCTRL_SLOTDIS7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS7;
+	tmp |= value << I2S_RXCTRL_SLOTDIS7_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_MONO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_MONO) >> I2S_RXCTRL_MONO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_MONO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_MONO;
+	tmp |= value << I2S_RXCTRL_MONO_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_DMA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_DMA) >> I2S_RXCTRL_DMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_DMA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_DMA;
+	tmp |= value << I2S_RXCTRL_DMA_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_RXLOOP_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_RXLOOP;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_RXLOOP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_RXLOOP) >> I2S_RXCTRL_RXLOOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_RXLOOP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_RXLOOP;
+	tmp |= value << I2S_RXCTRL_RXLOOP_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_RXLOOP_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_RXLOOP;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_RXLOOP_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_RXLOOP;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SERMODE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SERMODE(mask)) >> I2S_RXCTRL_SERMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SERMODE_Msk;
+	tmp |= I2S_RXCTRL_SERMODE(data);
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SERMODE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SERMODE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_SERMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SERMODE_Msk) >> I2S_RXCTRL_SERMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_DATASIZE(mask)) >> I2S_RXCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_DATASIZE_Msk;
+	tmp |= I2S_RXCTRL_DATASIZE(data);
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_DATASIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_DATASIZE_Msk) >> I2S_RXCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_EXTEND(mask)) >> I2S_RXCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_EXTEND_Msk;
+	tmp |= I2S_RXCTRL_EXTEND(data);
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_EXTEND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_EXTEND_Msk) >> I2S_RXCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_reg(const void *const hw)
+{
+	return ((I2s *)hw)->RXCTRL.reg;
+}
+
+static inline void hri_i2s_write_TXDATA_reg(const void *const hw, hri_i2s_txdata_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXDATA.reg = data;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_I2S_D51_H_INCLUDED */
+#endif /* _SAMD51_I2S_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_icm_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_icm_d51.h
new file mode 100644
index 0000000..9069ea3
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_icm_d51.h
@@ -0,0 +1,761 @@
+/**
+ * \file
+ *
+ * \brief SAM ICM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_ICM_COMPONENT_
+#ifndef _HRI_ICM_D51_H_INCLUDED_
+#define _HRI_ICM_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_ICM_CRITICAL_SECTIONS)
+#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define ICM_CRITICAL_SECTION_ENTER()
+#define ICM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_icm_cfg_reg_t;
+typedef uint32_t hri_icm_ctrl_reg_t;
+typedef uint32_t hri_icm_dscr_reg_t;
+typedef uint32_t hri_icm_hash_reg_t;
+typedef uint32_t hri_icm_imr_reg_t;
+typedef uint32_t hri_icm_isr_reg_t;
+typedef uint32_t hri_icm_sr_reg_t;
+typedef uint32_t hri_icm_uasr_reg_t;
+typedef uint32_t hri_icm_uihval_reg_t;
+typedef uint32_t hri_icmdescriptor_raddr_reg_t;
+typedef uint32_t hri_icmdescriptor_rcfg_reg_t;
+typedef uint32_t hri_icmdescriptor_rctrl_reg_t;
+typedef uint32_t hri_icmdescriptor_rnext_reg_t;
+
+static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RADDR.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const             hw,
+                                                                            hri_icmdescriptor_raddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((IcmDescriptor *)hw)->RADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RADDR.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RADDR.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RADDR.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw)
+{
+	return ((IcmDescriptor *)hw)->RADDR.reg;
+}
+
+static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCFG.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const            hw,
+                                                                          hri_icmdescriptor_rcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((IcmDescriptor *)hw)->RCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCFG.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCFG.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCFG.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw)
+{
+	return ((IcmDescriptor *)hw)->RCFG.reg;
+}
+
+static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCTRL.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const             hw,
+                                                                            hri_icmdescriptor_rctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((IcmDescriptor *)hw)->RCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCTRL.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCTRL.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCTRL.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw)
+{
+	return ((IcmDescriptor *)hw)->RCTRL.reg;
+}
+
+static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RNEXT.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const             hw,
+                                                                            hri_icmdescriptor_rnext_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((IcmDescriptor *)hw)->RNEXT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RNEXT.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RNEXT.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RNEXT.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw)
+{
+	return ((IcmDescriptor *)hw)->RNEXT.reg;
+}
+
+static inline void hri_icm_set_IMR_URAD_bit(const void *const hw)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_URAD;
+}
+
+static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw)
+{
+	return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos;
+}
+
+static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Icm *)hw)->IDR.reg = ICM_IMR_URAD;
+	} else {
+		((Icm *)hw)->IER.reg = ICM_IMR_URAD;
+	}
+}
+
+static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_URAD;
+}
+
+static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RHC(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data);
+}
+
+static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask);
+}
+
+static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RDM(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data);
+}
+
+static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask);
+}
+
+static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RBE(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data);
+}
+
+static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask);
+}
+
+static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RWC(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data);
+}
+
+static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask);
+}
+
+static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_REC(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_REC(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data);
+}
+
+static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask);
+}
+
+static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RSU(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data);
+}
+
+static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask);
+}
+
+static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = mask;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->IMR.reg;
+}
+
+static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = data;
+	((Icm *)hw)->IDR.reg = ~data;
+}
+
+static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = mask;
+}
+
+static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->SR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->SR.reg;
+}
+
+static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->ISR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->ISR.reg;
+}
+
+static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask)
+{
+	return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos;
+}
+
+static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw)
+{
+	return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos;
+}
+
+static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->UASR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->UASR.reg;
+}
+
+static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CFG.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->CFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CFG.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CFG.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CFG.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw)
+{
+	return ((Icm *)hw)->CFG.reg;
+}
+
+static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->DSCR.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->DSCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->DSCR.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->DSCR.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->DSCR.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->DSCR.reg;
+}
+
+static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->HASH.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->HASH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->HASH.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->HASH.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->HASH.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw)
+{
+	return ((Icm *)hw)->HASH.reg;
+}
+
+static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CTRL.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->UIHVAL[index].reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_ICM_D51_H_INCLUDED */
+#endif /* _SAMD51_ICM_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_mclk_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_mclk_d51.h
new file mode 100644
index 0000000..ff53c97
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_mclk_d51.h
@@ -0,0 +1,3396 @@
+/**
+ * \file
+ *
+ * \brief SAM MCLK
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_MCLK_COMPONENT_
+#ifndef _HRI_MCLK_D51_H_INCLUDED_
+#define _HRI_MCLK_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_MCLK_CRITICAL_SECTIONS)
+#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define MCLK_CRITICAL_SECTION_ENTER()
+#define MCLK_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_mclk_ahbmask_reg_t;
+typedef uint32_t hri_mclk_apbamask_reg_t;
+typedef uint32_t hri_mclk_apbbmask_reg_t;
+typedef uint32_t hri_mclk_apbcmask_reg_t;
+typedef uint32_t hri_mclk_apbdmask_reg_t;
+typedef uint8_t  hri_mclk_cpudiv_reg_t;
+typedef uint8_t  hri_mclk_hsdiv_reg_t;
+typedef uint8_t  hri_mclk_intenset_reg_t;
+typedef uint8_t  hri_mclk_intflag_reg_t;
+
+static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
+}
+
+static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
+}
+
+static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
+}
+
+static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
+}
+
+static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
+{
+	((Mclk *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
+}
+
+static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos;
+}
+
+static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
+	} else {
+		((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
+	}
+}
+
+static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
+}
+
+static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	((Mclk *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->INTENSET.reg;
+}
+
+static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data)
+{
+	((Mclk *)hw)->INTENSET.reg = data;
+	((Mclk *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	((Mclk *)hw)->INTENCLR.reg = mask;
+}
+
+static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_DIV_bf(const void *const hw, hri_mclk_hsdiv_reg_t mask)
+{
+	return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV(mask)) >> MCLK_HSDIV_DIV_Pos;
+}
+
+static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_DIV_bf(const void *const hw)
+{
+	return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV_Msk) >> MCLK_HSDIV_DIV_Pos;
+}
+
+static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_reg(const void *const hw, hri_mclk_hsdiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->HSDIV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->HSDIV.reg;
+}
+
+static inline void hri_mclk_set_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp = (tmp & MCLK_CPUDIV_DIV(mask)) >> MCLK_CPUDIV_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_write_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data)
+{
+	uint8_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp &= ~MCLK_CPUDIV_DIV_Msk;
+	tmp |= MCLK_CPUDIV_DIV(data);
+	((Mclk *)hw)->CPUDIV.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_DIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_DIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_DIV_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp = (tmp & MCLK_CPUDIV_DIV_Msk) >> MCLK_CPUDIV_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->CPUDIV.reg;
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB0;
+	tmp |= value << MCLK_AHBMASK_HPB0_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB1;
+	tmp |= value << MCLK_AHBMASK_HPB1_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB2;
+	tmp |= value << MCLK_AHBMASK_HPB2_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB3;
+	tmp |= value << MCLK_AHBMASK_HPB3_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_DSU;
+	tmp |= value << MCLK_AHBMASK_DSU_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HMATRIX_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HMATRIX) >> MCLK_AHBMASK_HMATRIX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HMATRIX_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HMATRIX;
+	tmp |= value << MCLK_AHBMASK_HMATRIX_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HSRAM;
+	tmp |= value << MCLK_AHBMASK_HSRAM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_CMCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CMCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_CMCC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_CMCC) >> MCLK_AHBMASK_CMCC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_CMCC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_CMCC;
+	tmp |= value << MCLK_AHBMASK_CMCC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_CMCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CMCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_CMCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CMCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_DMAC;
+	tmp |= value << MCLK_AHBMASK_DMAC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_USB;
+	tmp |= value << MCLK_AHBMASK_USB_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_BKUPRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_BKUPRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_BKUPRAM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_BKUPRAM) >> MCLK_AHBMASK_BKUPRAM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_BKUPRAM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_BKUPRAM;
+	tmp |= value << MCLK_AHBMASK_BKUPRAM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_BKUPRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_BKUPRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_BKUPRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_BKUPRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_PAC;
+	tmp |= value << MCLK_AHBMASK_PAC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_QSPI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_QSPI) >> MCLK_AHBMASK_QSPI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_QSPI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_QSPI;
+	tmp |= value << MCLK_AHBMASK_QSPI_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_SDHC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_SDHC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_SDHC0) >> MCLK_AHBMASK_SDHC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_SDHC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_SDHC0;
+	tmp |= value << MCLK_AHBMASK_SDHC0_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_SDHC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_SDHC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_SDHC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_SDHC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_SDHC1) >> MCLK_AHBMASK_SDHC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_SDHC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_SDHC1;
+	tmp |= value << MCLK_AHBMASK_SDHC1_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_SDHC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_SDHC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_ICM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_ICM) >> MCLK_AHBMASK_ICM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_ICM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_ICM;
+	tmp |= value << MCLK_AHBMASK_ICM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_PUKCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PUKCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_PUKCC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_PUKCC) >> MCLK_AHBMASK_PUKCC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_PUKCC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_PUKCC;
+	tmp |= value << MCLK_AHBMASK_PUKCC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_PUKCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PUKCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_PUKCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PUKCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_QSPI_2X_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI_2X;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_QSPI_2X_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_QSPI_2X) >> MCLK_AHBMASK_QSPI_2X_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_QSPI_2X_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_QSPI_2X;
+	tmp |= value << MCLK_AHBMASK_QSPI_2X_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_QSPI_2X_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI_2X;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_QSPI_2X_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI_2X;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_SMEEPROM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL_SMEEPROM) >> MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_SMEEPROM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_CACHE;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL_CACHE) >> MCLK_AHBMASK_NVMCTRL_CACHE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL_CACHE;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_CACHE_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_CACHE;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_CACHE;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->AHBMASK.reg;
+}
+
+static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_PAC;
+	tmp |= value << MCLK_APBAMASK_PAC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_PM;
+	tmp |= value << MCLK_APBAMASK_PM_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_MCLK;
+	tmp |= value << MCLK_APBAMASK_MCLK_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_RSTC;
+	tmp |= value << MCLK_APBAMASK_RSTC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_OSCCTRL;
+	tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_OSC32KCTRL;
+	tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_SUPC;
+	tmp |= value << MCLK_APBAMASK_SUPC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_GCLK;
+	tmp |= value << MCLK_APBAMASK_GCLK_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_WDT;
+	tmp |= value << MCLK_APBAMASK_WDT_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_RTC;
+	tmp |= value << MCLK_APBAMASK_RTC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_EIC;
+	tmp |= value << MCLK_APBAMASK_EIC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_FREQM;
+	tmp |= value << MCLK_APBAMASK_FREQM_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_SERCOM0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_SERCOM0) >> MCLK_APBAMASK_SERCOM0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_SERCOM0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_SERCOM0;
+	tmp |= value << MCLK_APBAMASK_SERCOM0_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_SERCOM1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_SERCOM1) >> MCLK_APBAMASK_SERCOM1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_SERCOM1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_SERCOM1;
+	tmp |= value << MCLK_APBAMASK_SERCOM1_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_TC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_TC0) >> MCLK_APBAMASK_TC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_TC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_TC0;
+	tmp |= value << MCLK_APBAMASK_TC0_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_TC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_TC1) >> MCLK_APBAMASK_TC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_TC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_TC1;
+	tmp |= value << MCLK_APBAMASK_TC1_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBAMASK.reg;
+}
+
+static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_USB;
+	tmp |= value << MCLK_APBBMASK_USB_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_DSU;
+	tmp |= value << MCLK_APBBMASK_DSU_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_NVMCTRL;
+	tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_PORT;
+	tmp |= value << MCLK_APBBMASK_PORT_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_HMATRIX) >> MCLK_APBBMASK_HMATRIX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_HMATRIX;
+	tmp |= value << MCLK_APBBMASK_HMATRIX_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_EVSYS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_EVSYS) >> MCLK_APBBMASK_EVSYS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_EVSYS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_EVSYS;
+	tmp |= value << MCLK_APBBMASK_EVSYS_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_SERCOM2) >> MCLK_APBBMASK_SERCOM2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_SERCOM2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_SERCOM2;
+	tmp |= value << MCLK_APBBMASK_SERCOM2_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_SERCOM3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_SERCOM3) >> MCLK_APBBMASK_SERCOM3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_SERCOM3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_SERCOM3;
+	tmp |= value << MCLK_APBBMASK_SERCOM3_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_TCC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_TCC0) >> MCLK_APBBMASK_TCC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_TCC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_TCC0;
+	tmp |= value << MCLK_APBBMASK_TCC0_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_TCC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_TCC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_TCC1) >> MCLK_APBBMASK_TCC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_TCC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_TCC1;
+	tmp |= value << MCLK_APBBMASK_TCC1_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_TCC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_TCC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_TC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_TC2) >> MCLK_APBBMASK_TC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_TC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_TC2;
+	tmp |= value << MCLK_APBBMASK_TC2_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_TC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_TC3) >> MCLK_APBBMASK_TC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_TC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_TC3;
+	tmp |= value << MCLK_APBBMASK_TC3_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_RAMECC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_RAMECC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_RAMECC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_RAMECC) >> MCLK_APBBMASK_RAMECC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_RAMECC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_RAMECC;
+	tmp |= value << MCLK_APBBMASK_RAMECC_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_RAMECC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_RAMECC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_RAMECC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_RAMECC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBBMASK.reg;
+}
+
+static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TCC2;
+	tmp |= value << MCLK_APBCMASK_TCC2_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TCC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TCC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TCC3) >> MCLK_APBCMASK_TCC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TCC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TCC3;
+	tmp |= value << MCLK_APBCMASK_TCC3_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TCC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TCC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC4;
+	tmp |= value << MCLK_APBCMASK_TC4_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC5) >> MCLK_APBCMASK_TC5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC5;
+	tmp |= value << MCLK_APBCMASK_TC5_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_PDEC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_PDEC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_PDEC) >> MCLK_APBCMASK_PDEC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_PDEC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_PDEC;
+	tmp |= value << MCLK_APBCMASK_PDEC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_PDEC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PDEC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_PDEC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PDEC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_AC;
+	tmp |= value << MCLK_APBCMASK_AC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_AES;
+	tmp |= value << MCLK_APBCMASK_AES_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TRNG;
+	tmp |= value << MCLK_APBCMASK_TRNG_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_ICM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_ICM) >> MCLK_APBCMASK_ICM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_ICM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_ICM;
+	tmp |= value << MCLK_APBCMASK_ICM_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_QSPI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_QSPI) >> MCLK_APBCMASK_QSPI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_QSPI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_QSPI;
+	tmp |= value << MCLK_APBCMASK_QSPI_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_CCL;
+	tmp |= value << MCLK_APBCMASK_CCL_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBCMASK.reg;
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_SERCOM4) >> MCLK_APBDMASK_SERCOM4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_SERCOM4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_SERCOM4;
+	tmp |= value << MCLK_APBDMASK_SERCOM4_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_SERCOM5;
+	tmp |= value << MCLK_APBDMASK_SERCOM5_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_SERCOM6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_SERCOM6) >> MCLK_APBDMASK_SERCOM6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_SERCOM6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_SERCOM6;
+	tmp |= value << MCLK_APBDMASK_SERCOM6_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_SERCOM6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_SERCOM6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_SERCOM7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_SERCOM7) >> MCLK_APBDMASK_SERCOM7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_SERCOM7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_SERCOM7;
+	tmp |= value << MCLK_APBDMASK_SERCOM7_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_SERCOM7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_SERCOM7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_TCC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TCC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_TCC4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_TCC4) >> MCLK_APBDMASK_TCC4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_TCC4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_TCC4;
+	tmp |= value << MCLK_APBDMASK_TCC4_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_TCC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TCC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_TCC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TCC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_TC6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_TC6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_TC6) >> MCLK_APBDMASK_TC6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_TC6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_TC6;
+	tmp |= value << MCLK_APBDMASK_TC6_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_TC6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_TC6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_TC7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_TC7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_TC7) >> MCLK_APBDMASK_TC7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_TC7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_TC7;
+	tmp |= value << MCLK_APBDMASK_TC7_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_TC7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_TC7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_ADC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_ADC0) >> MCLK_APBDMASK_ADC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_ADC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_ADC0;
+	tmp |= value << MCLK_APBDMASK_ADC0_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_ADC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_ADC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_ADC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_ADC1) >> MCLK_APBDMASK_ADC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_ADC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_ADC1;
+	tmp |= value << MCLK_APBDMASK_ADC1_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_ADC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_ADC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_DAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_DAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_DAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_DAC) >> MCLK_APBDMASK_DAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_DAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_DAC;
+	tmp |= value << MCLK_APBDMASK_DAC_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_DAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_DAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_DAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_DAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_I2S_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_I2S;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_I2S_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_I2S) >> MCLK_APBDMASK_I2S_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_I2S_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_I2S;
+	tmp |= value << MCLK_APBDMASK_I2S_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_I2S_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_I2S;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_I2S_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_I2S;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_PCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_PCC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_PCC) >> MCLK_APBDMASK_PCC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_PCC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_PCC;
+	tmp |= value << MCLK_APBDMASK_PCC_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_PCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_PCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBDMASK.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_MCLK_D51_H_INCLUDED */
+#endif /* _SAMD51_MCLK_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_nvmctrl_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_nvmctrl_d51.h
new file mode 100644
index 0000000..e9190ee
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_nvmctrl_d51.h
@@ -0,0 +1,1618 @@
+/**
+ * \file
+ *
+ * \brief SAM NVMCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_NVMCTRL_COMPONENT_
+#ifndef _HRI_NVMCTRL_D51_H_INCLUDED_
+#define _HRI_NVMCTRL_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS)
+#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define NVMCTRL_CRITICAL_SECTION_ENTER()
+#define NVMCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_nvmctrl_ctrla_reg_t;
+typedef uint16_t hri_nvmctrl_ctrlb_reg_t;
+typedef uint16_t hri_nvmctrl_intenset_reg_t;
+typedef uint16_t hri_nvmctrl_intflag_reg_t;
+typedef uint16_t hri_nvmctrl_status_reg_t;
+typedef uint32_t hri_nvmctrl_addr_reg_t;
+typedef uint32_t hri_nvmctrl_eccerr_reg_t;
+typedef uint32_t hri_nvmctrl_param_reg_t;
+typedef uint32_t hri_nvmctrl_pbldata_reg_t;
+typedef uint32_t hri_nvmctrl_runlock_reg_t;
+typedef uint32_t hri_nvmctrl_seestat_reg_t;
+typedef uint8_t  hri_nvmctrl_dbgctrl_reg_t;
+typedef uint8_t  hri_nvmctrl_seecfg_reg_t;
+
+static inline bool hri_nvmctrl_get_INTFLAG_DONE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_DONE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_ADDRE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_ADDRE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_PROGE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_PROGE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_LOCKE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_LOCKE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_ECCSE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_ECCSE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_ECCDE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_ECCDE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_NVME_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_NVME_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_SUSP_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_SUSP_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_SEESFULL_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_SEESFULL_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_SEESOVF_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_SEESOVF_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_SEEWRC_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_SEEWRC_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_DONE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_DONE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_ADDRE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_ADDRE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_PROGE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_PROGE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_LOCKE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_LOCKE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_ECCSE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_ECCSE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_ECCDE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_ECCDE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_NVME_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_NVME_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_SUSP_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_SUSP_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_SEESFULL_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_SEESFULL_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_SEESOVF_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_SEESOVF_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_SEEWRC_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_SEEWRC_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC;
+}
+
+static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_nvmctrl_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_nvmctrl_set_INTEN_DONE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_DONE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_DONE) >> NVMCTRL_INTENSET_DONE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_DONE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_DONE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_ADDRE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_ADDRE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ADDRE) >> NVMCTRL_INTENSET_ADDRE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_ADDRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_ADDRE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_PROGE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_PROGE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_PROGE) >> NVMCTRL_INTENSET_PROGE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_PROGE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_PROGE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_LOCKE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_LOCKE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_LOCKE) >> NVMCTRL_INTENSET_LOCKE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_LOCKE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_LOCKE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_ECCSE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_ECCSE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCSE) >> NVMCTRL_INTENSET_ECCSE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_ECCSE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_ECCSE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_ECCDE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_ECCDE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCDE) >> NVMCTRL_INTENSET_ECCDE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_ECCDE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_ECCDE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_NVME_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_NVME_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_NVME) >> NVMCTRL_INTENSET_NVME_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_NVME_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_NVME_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME;
+}
+
+static inline void hri_nvmctrl_set_INTEN_SUSP_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_SUSP_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SUSP) >> NVMCTRL_INTENSET_SUSP_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_SUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_SUSP_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP;
+}
+
+static inline void hri_nvmctrl_set_INTEN_SEESFULL_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_SEESFULL_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESFULL) >> NVMCTRL_INTENSET_SEESFULL_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_SEESFULL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_SEESFULL_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL;
+}
+
+static inline void hri_nvmctrl_set_INTEN_SEESOVF_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_SEESOVF_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESOVF) >> NVMCTRL_INTENSET_SEESOVF_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_SEESOVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_SEESOVF_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF;
+}
+
+static inline void hri_nvmctrl_set_INTEN_SEEWRC_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_SEEWRC_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEEWRC) >> NVMCTRL_INTENSET_SEEWRC_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_SEEWRC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_SEEWRC_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC;
+}
+
+static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const          hw,
+                                                                   hri_nvmctrl_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = data;
+	((Nvmctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_nvmctrl_get_PARAM_SEE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->PARAM.reg;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_READY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_READY) >> NVMCTRL_STATUS_READY_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_SUSP_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SUSP) >> NVMCTRL_STATUS_SUSP_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_AFIRST_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_AFIRST) >> NVMCTRL_STATUS_AFIRST_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_BPDIS_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BPDIS) >> NVMCTRL_STATUS_BPDIS_Pos;
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_BOOTPROT_bf(const void *const        hw,
+                                                                          hri_nvmctrl_status_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT(mask)) >> NVMCTRL_STATUS_BOOTPROT_Pos;
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_BOOTPROT_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT_Msk) >> NVMCTRL_STATUS_BOOTPROT_Pos;
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->STATUS.reg;
+}
+
+static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_RUNLOCK_bf(const void *const         hw,
+                                                                           hri_nvmctrl_runlock_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK(mask)) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos;
+}
+
+static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_RUNLOCK_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK_Msk) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos;
+}
+
+static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_reg(const void *const         hw,
+                                                                    hri_nvmctrl_runlock_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->RUNLOCK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->RUNLOCK.reg;
+}
+
+static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_DATA_bf(const void *const hw, uint8_t index,
+                                                                        hri_nvmctrl_pbldata_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA(mask)) >> NVMCTRL_PBLDATA_DATA_Pos;
+}
+
+static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_DATA_bf(const void *const hw, uint8_t index)
+{
+	return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA_Msk) >> NVMCTRL_PBLDATA_DATA_Pos;
+}
+
+static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_reg(const void *const hw, uint8_t index,
+                                                                    hri_nvmctrl_pbldata_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PBLDATA[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_reg(const void *const hw, uint8_t index)
+{
+	return ((Nvmctrl *)hw)->PBLDATA[index].reg;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_ADDR_bf(const void *const        hw,
+                                                                      hri_nvmctrl_eccerr_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR(mask)) >> NVMCTRL_ECCERR_ADDR_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_ADDR_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR_Msk) >> NVMCTRL_ECCERR_ADDR_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEL_bf(const void *const        hw,
+                                                                       hri_nvmctrl_eccerr_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL(mask)) >> NVMCTRL_ECCERR_TYPEL_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEL_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL_Msk) >> NVMCTRL_ECCERR_TYPEL_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEH_bf(const void *const        hw,
+                                                                       hri_nvmctrl_eccerr_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH(mask)) >> NVMCTRL_ECCERR_TYPEH_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEH_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH_Msk) >> NVMCTRL_ECCERR_TYPEH_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_reg(const void *const hw, hri_nvmctrl_eccerr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ECCERR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->ECCERR.reg;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_ASEES_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_ASEES) >> NVMCTRL_SEESTAT_ASEES_Pos;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_LOAD_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOAD) >> NVMCTRL_SEESTAT_LOAD_Pos;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_BUSY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_BUSY) >> NVMCTRL_SEESTAT_BUSY_Pos;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_LOCK_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOCK) >> NVMCTRL_SEESTAT_LOCK_Pos;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_RLOCK_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_RLOCK) >> NVMCTRL_SEESTAT_RLOCK_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_SBLK_bf(const void *const         hw,
+                                                                        hri_nvmctrl_seestat_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK(mask)) >> NVMCTRL_SEESTAT_SBLK_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_SBLK_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK_Msk) >> NVMCTRL_SEESTAT_SBLK_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_PSZ_bf(const void *const         hw,
+                                                                       hri_nvmctrl_seestat_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ(mask)) >> NVMCTRL_SEESTAT_PSZ_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_PSZ_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ_Msk) >> NVMCTRL_SEESTAT_PSZ_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_reg(const void *const         hw,
+                                                                    hri_nvmctrl_seestat_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->SEESTAT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->SEESTAT.reg;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_AUTOWS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AUTOWS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_AUTOWS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_AUTOWS) >> NVMCTRL_CTRLA_AUTOWS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_AUTOWS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_AUTOWS;
+	tmp |= value << NVMCTRL_CTRLA_AUTOWS_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_AUTOWS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AUTOWS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_AUTOWS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AUTOWS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_SUSPEN_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_SUSPEN;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_SUSPEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_SUSPEN) >> NVMCTRL_CTRLA_SUSPEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_SUSPEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_SUSPEN;
+	tmp |= value << NVMCTRL_CTRLA_SUSPEN_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_SUSPEN_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_SUSPEN;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_SUSPEN_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_SUSPEN;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_AHBNS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_AHBNS0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_AHBNS0) >> NVMCTRL_CTRLA_AHBNS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_AHBNS0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_AHBNS0;
+	tmp |= value << NVMCTRL_CTRLA_AHBNS0_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_AHBNS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_AHBNS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_AHBNS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_AHBNS1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_AHBNS1) >> NVMCTRL_CTRLA_AHBNS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_AHBNS1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_AHBNS1;
+	tmp |= value << NVMCTRL_CTRLA_AHBNS1_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_AHBNS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_AHBNS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS0) >> NVMCTRL_CTRLA_CACHEDIS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_CACHEDIS0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_CACHEDIS0;
+	tmp |= value << NVMCTRL_CTRLA_CACHEDIS0_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS1) >> NVMCTRL_CTRLA_CACHEDIS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_CACHEDIS1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_CACHEDIS1;
+	tmp |= value << NVMCTRL_CTRLA_CACHEDIS1_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_WMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_WMODE(mask)) >> NVMCTRL_CTRLA_WMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_WMODE_Msk;
+	tmp |= NVMCTRL_CTRLA_WMODE(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_WMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_WMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_WMODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_WMODE_Msk) >> NVMCTRL_CTRLA_WMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_PRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_PRM(mask)) >> NVMCTRL_CTRLA_PRM_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_PRM_Msk;
+	tmp |= NVMCTRL_CTRLA_PRM(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_PRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_PRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_PRM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_PRM_Msk) >> NVMCTRL_CTRLA_PRM_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_RWS(mask)) >> NVMCTRL_CTRLA_RWS_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_RWS_Msk;
+	tmp |= NVMCTRL_CTRLA_RWS(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_RWS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_RWS_Msk) >> NVMCTRL_CTRLA_RWS_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->CTRLA.reg;
+}
+
+static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp &= ~NVMCTRL_ADDR_ADDR_Msk;
+	tmp |= NVMCTRL_ADDR_ADDR(data);
+	((Nvmctrl *)hw)->ADDR.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->ADDR.reg;
+}
+
+static inline void hri_nvmctrl_set_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp = (tmp & NVMCTRL_DBGCTRL_ECCDIS) >> NVMCTRL_DBGCTRL_ECCDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp &= ~NVMCTRL_DBGCTRL_ECCDIS;
+	tmp |= value << NVMCTRL_DBGCTRL_ECCDIS_Pos;
+	((Nvmctrl *)hw)->DBGCTRL.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCELOG;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp = (tmp & NVMCTRL_DBGCTRL_ECCELOG) >> NVMCTRL_DBGCTRL_ECCELOG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp &= ~NVMCTRL_DBGCTRL_ECCELOG;
+	tmp |= value << NVMCTRL_DBGCTRL_ECCELOG_Pos;
+	((Nvmctrl *)hw)->DBGCTRL.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCELOG;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCELOG;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_get_DBGCTRL_reg(const void *const         hw,
+                                                                    hri_nvmctrl_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_nvmctrl_set_SEECFG_WMODE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_WMODE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_SEECFG_WMODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp = (tmp & NVMCTRL_SEECFG_WMODE) >> NVMCTRL_SEECFG_WMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_SEECFG_WMODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp &= ~NVMCTRL_SEECFG_WMODE;
+	tmp |= value << NVMCTRL_SEECFG_WMODE_Pos;
+	((Nvmctrl *)hw)->SEECFG.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_SEECFG_WMODE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_WMODE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_SEECFG_WMODE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_WMODE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_SEECFG_APRDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_APRDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_SEECFG_APRDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp = (tmp & NVMCTRL_SEECFG_APRDIS) >> NVMCTRL_SEECFG_APRDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_SEECFG_APRDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp &= ~NVMCTRL_SEECFG_APRDIS;
+	tmp |= value << NVMCTRL_SEECFG_APRDIS_Pos;
+	((Nvmctrl *)hw)->SEECFG.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_SEECFG_APRDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_APRDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_SEECFG_APRDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_APRDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_get_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_read_SEECFG_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->SEECFG.reg;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_NVMCTRL_D51_H_INCLUDED */
+#endif /* _SAMD51_NVMCTRL_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_osc32kctrl_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_osc32kctrl_d51.h
new file mode 100644
index 0000000..f0dbeb8
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_osc32kctrl_d51.h
@@ -0,0 +1,1199 @@
+/**
+ * \file
+ *
+ * \brief SAM OSC32KCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_OSC32KCTRL_COMPONENT_
+#ifndef _HRI_OSC32KCTRL_D51_H_INCLUDED_
+#define _HRI_OSC32KCTRL_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS)
+#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define OSC32KCTRL_CRITICAL_SECTION_ENTER()
+#define OSC32KCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_osc32kctrl_xosc32k_reg_t;
+typedef uint32_t hri_osc32kctrl_intenset_reg_t;
+typedef uint32_t hri_osc32kctrl_intflag_reg_t;
+typedef uint32_t hri_osc32kctrl_osculp32k_reg_t;
+typedef uint32_t hri_osc32kctrl_status_reg_t;
+typedef uint8_t  hri_osc32kctrl_cfdctrl_reg_t;
+typedef uint8_t  hri_osc32kctrl_evctrl_reg_t;
+typedef uint8_t  hri_osc32kctrl_rtcctrl_reg_t;
+
+static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL;
+}
+
+static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_interrupt_XOSC32KFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_interrupt_XOSC32KFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL;
+}
+
+static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+	} else {
+		((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+	}
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_XOSC32KFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL;
+}
+
+static inline bool hri_osc32kctrl_get_INTEN_XOSC32KFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KFAIL) >> OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_XOSC32KFAIL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL;
+	} else {
+		((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL;
+	}
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_XOSC32KFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const             hw,
+                                                                         hri_osc32kctrl_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = data;
+	((Osc32kctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_XOSC32KFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KFAIL) >> OSC32KCTRL_STATUS_XOSC32KFAIL_Pos;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_XOSC32KSW_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KSW) >> OSC32KCTRL_STATUS_XOSC32KSW_Pos;
+}
+
+static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const           hw,
+                                                                        hri_osc32kctrl_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->STATUS.reg;
+}
+
+static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const            hw,
+                                                                                hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk;
+	tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data);
+	((Osc32kctrl *)hw)->RTCCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->RTCCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_ENABLE;
+	tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_XTALEN;
+	tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_EN32K;
+	tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_EN1K;
+	tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY;
+	tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND;
+	tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK;
+	tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const            hw,
+                                                                                 hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk;
+	tmp |= OSC32KCTRL_XOSC32K_STARTUP(data);
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_CGM(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_CGM_bf(const void *const            hw,
+                                                                             hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_CGM(mask)) >> OSC32KCTRL_XOSC32K_CGM_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_CGM_Msk;
+	tmp |= OSC32KCTRL_XOSC32K_CGM(data);
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_CGM(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_CGM(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_CGM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_CGM_Msk) >> OSC32KCTRL_XOSC32K_CGM_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->XOSC32K.reg;
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN;
+	tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK;
+	tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC;
+	tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->CFDCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSC32KCTRL_EVCTRL_CFDEO;
+	tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos;
+	((Osc32kctrl *)hw)->EVCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const           hw,
+                                                                        hri_osc32kctrl_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_EN32K;
+	tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_EN1K;
+	tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK;
+	tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const              hw,
+                                                                                   hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk;
+	tmp |= OSC32KCTRL_OSCULP32K_CALIB(data);
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const              hw,
+                                                                              hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->OSCULP32K.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_OSC32KCTRL_D51_H_INCLUDED */
+#endif /* _SAMD51_OSC32KCTRL_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_oscctrl_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_oscctrl_d51.h
new file mode 100644
index 0000000..7a6b7f3
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_oscctrl_d51.h
@@ -0,0 +1,4441 @@
+/**
+ * \file
+ *
+ * \brief SAM OSCCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_OSCCTRL_COMPONENT_
+#ifndef _HRI_OSCCTRL_D51_H_INCLUDED_
+#define _HRI_OSCCTRL_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS)
+#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define OSCCTRL_CRITICAL_SECTION_ENTER()
+#define OSCCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_oscctrl_dfllmul_reg_t;
+typedef uint32_t hri_oscctrl_dfllval_reg_t;
+typedef uint32_t hri_oscctrl_dpllctrlb_reg_t;
+typedef uint32_t hri_oscctrl_dpllratio_reg_t;
+typedef uint32_t hri_oscctrl_dpllstatus_reg_t;
+typedef uint32_t hri_oscctrl_dpllsyncbusy_reg_t;
+typedef uint32_t hri_oscctrl_intenset_reg_t;
+typedef uint32_t hri_oscctrl_intflag_reg_t;
+typedef uint32_t hri_oscctrl_status_reg_t;
+typedef uint32_t hri_oscctrl_xoscctrl_reg_t;
+typedef uint32_t hri_oscctrldpll_dpllctrlb_reg_t;
+typedef uint32_t hri_oscctrldpll_dpllratio_reg_t;
+typedef uint32_t hri_oscctrldpll_dpllstatus_reg_t;
+typedef uint32_t hri_oscctrldpll_dpllsyncbusy_reg_t;
+typedef uint8_t  hri_oscctrl_dfllctrla_reg_t;
+typedef uint8_t  hri_oscctrl_dfllctrlb_reg_t;
+typedef uint8_t  hri_oscctrl_dfllsync_reg_t;
+typedef uint8_t  hri_oscctrl_dpllctrla_reg_t;
+typedef uint8_t  hri_oscctrl_evctrl_reg_t;
+typedef uint8_t  hri_oscctrldpll_dpllctrla_reg_t;
+
+static inline void hri_oscctrldpll_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	while (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_oscctrldpll_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg;
+}
+
+static inline void hri_oscctrl_wait_for_sync(const void *const hw, uint8_t submodule_index,
+                                             hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_oscctrl_is_syncing(const void *const hw, uint8_t submodule_index,
+                                          hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg;
+}
+
+static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw)
+{
+	return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO)
+	       >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_get_DPLLSYNCBUSY_reg(const void *const              hw,
+                                                                                  hri_oscctrl_dpllsyncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_read_DPLLSYNCBUSY_reg(const void *const hw)
+{
+	return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg;
+}
+
+static inline bool hri_oscctrldpll_get_DPLLSTATUS_LOCK_bit(const void *const hw)
+{
+	return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos;
+}
+
+static inline bool hri_oscctrldpll_get_DPLLSTATUS_CLKRDY_bit(const void *const hw)
+{
+	return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_get_DPLLSTATUS_reg(const void *const            hw,
+                                                                              hri_oscctrl_dpllstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_read_DPLLSTATUS_reg(const void *const hw)
+{
+	return ((OscctrlDpll *)hw)->DPLLSTATUS.reg;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg |= mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_get_DPLLCTRLA_reg(const void *const           hw,
+                                                                            hri_oscctrl_dpllctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg = data;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_read_DPLLCTRLA_reg(const void *const hw)
+{
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+}
+
+static inline void hri_oscctrldpll_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDR_bf(const void *const           hw,
+                                                                               hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDR(data);
+	((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDRFRAC_bf(const void *const           hw,
+                                                                                   hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data);
+	((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDRFRAC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg |= mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_reg(const void *const           hw,
+                                                                            hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg = data;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg ^= mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_reg(const void *const hw)
+{
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	return ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_WUF;
+	tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLB_DCOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN;
+	tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_FILTER_bf(const void *const           hw,
+                                                                                  hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_FILTER(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_FILTER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_REFCLK_bf(const void *const           hw,
+                                                                                  hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_REFCLK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_LTIME_bf(const void *const           hw,
+                                                                                 hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_LTIME(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_LTIME_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DCOFILTER_bf(const void *const           hw,
+                                                                                     hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DIV_bf(const void *const           hw,
+                                                                               hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DIV(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DIV_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_reg(const void *const           hw,
+                                                                            hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_reg(const void *const hw)
+{
+	return ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+}
+
+static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE)
+	       >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO)
+	       >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t
+hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllsyncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg;
+}
+
+static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK)
+	       >> OSCCTRL_DPLLSTATUS_LOCK_Pos;
+}
+
+static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY)
+	       >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                          hri_oscctrl_dpllstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw,
+                                                                           uint8_t           submodule_index)
+{
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_oscctrl_dpllctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrla_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index)
+{
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t
+hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDR(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t
+hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllratio_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index)
+{
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_WUF;
+	tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN;
+	tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_FILTER(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_LTIME(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw,
+                                                                              uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                             hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw,
+                                                                                  uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DIV(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrlb_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL0LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL0LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL0LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL0LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL1LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL1LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL1LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL1LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCRDY0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCRDY0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCRDY1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCRDY1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCFAIL0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCFAIL0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCFAIL1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCFAIL1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL0LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL0LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL0LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL0LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL0LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL0LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL0LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL0LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL1LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL1LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL1LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL1LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL1LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL1LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL1LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL1LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO;
+}
+
+static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_oscctrl_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCRDY0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCRDY0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY0) >> OSCCTRL_INTENSET_XOSCRDY0_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCRDY0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCRDY1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCRDY1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY1) >> OSCCTRL_INTENSET_XOSCRDY1_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCRDY1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCFAIL0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCFAIL0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL0) >> OSCCTRL_INTENSET_XOSCFAIL0_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCFAIL0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCFAIL0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCFAIL1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCFAIL1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL1) >> OSCCTRL_INTENSET_XOSCFAIL1_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCFAIL1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCFAIL1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL0LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL0LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKR) >> OSCCTRL_INTENSET_DPLL0LCKR_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL0LCKR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL0LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL0LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL0LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKF) >> OSCCTRL_INTENSET_DPLL0LCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL0LCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL0LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL0LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL0LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LTO) >> OSCCTRL_INTENSET_DPLL0LTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL0LTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL0LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL0LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL0LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LDRTO) >> OSCCTRL_INTENSET_DPLL0LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL0LDRTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL0LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL1LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL1LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKR) >> OSCCTRL_INTENSET_DPLL1LCKR_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL1LCKR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL1LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL1LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL1LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKF) >> OSCCTRL_INTENSET_DPLL1LCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL1LCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL1LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL1LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL1LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LTO) >> OSCCTRL_INTENSET_DPLL1LTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL1LTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL1LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL1LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL1LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LDRTO) >> OSCCTRL_INTENSET_DPLL1LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL1LDRTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL1LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask)
+{
+	((Oscctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const          hw,
+                                                                   hri_oscctrl_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data)
+{
+	((Oscctrl *)hw)->INTENSET.reg = data;
+	((Oscctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCRDY0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY0) >> OSCCTRL_STATUS_XOSCRDY0_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCRDY1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCFAIL0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL0) >> OSCCTRL_STATUS_XOSCFAIL0_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCFAIL1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL1) >> OSCCTRL_STATUS_XOSCFAIL1_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCCKSW0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW0) >> OSCCTRL_STATUS_XOSCCKSW0_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCCKSW1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW1) >> OSCCTRL_STATUS_XOSCCKSW1_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL0LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKR) >> OSCCTRL_STATUS_DPLL0LCKR_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL0LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKF) >> OSCCTRL_STATUS_DPLL0LCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL0TO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0TO) >> OSCCTRL_STATUS_DPLL0TO_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL0LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LDRTO) >> OSCCTRL_STATUS_DPLL0LDRTO_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL1LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKR) >> OSCCTRL_STATUS_DPLL1LCKR_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL1LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKF) >> OSCCTRL_STATUS_DPLL1LCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL1TO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1TO) >> OSCCTRL_STATUS_DPLL1TO_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL1LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LDRTO) >> OSCCTRL_STATUS_DPLL1LDRTO_Pos;
+}
+
+static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->STATUS.reg;
+}
+
+static inline void hri_oscctrl_set_EVCTRL_CFDEO0_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO0;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_EVCTRL_CFDEO0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSCCTRL_EVCTRL_CFDEO0) >> OSCCTRL_EVCTRL_CFDEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_CFDEO0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSCCTRL_EVCTRL_CFDEO0;
+	tmp |= value << OSCCTRL_EVCTRL_CFDEO0_Pos;
+	((Oscctrl *)hw)->EVCTRL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_CFDEO0_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO0;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_CFDEO0_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO0;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_EVCTRL_CFDEO1_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO1;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_EVCTRL_CFDEO1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSCCTRL_EVCTRL_CFDEO1) >> OSCCTRL_EVCTRL_CFDEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_CFDEO1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSCCTRL_EVCTRL_CFDEO1;
+	tmp |= value << OSCCTRL_EVCTRL_CFDEO1_Pos;
+	((Oscctrl *)hw)->EVCTRL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_CFDEO1_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO1;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_CFDEO1_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO1;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ENABLE;
+	tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_XTALEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_XTALEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_XTALEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_XTALEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY;
+	tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND;
+	tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_LOWBUFGAIN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_LOWBUFGAIN) >> OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN;
+	tmp |= value << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_LOWBUFGAIN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENALC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ENALC) >> OSCCTRL_XOSCCTRL_ENALC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ENALC;
+	tmp |= value << OSCCTRL_XOSCCTRL_ENALC_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENALC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENALC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_CFDEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_SWBEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_SWBEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_SWBEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_SWBEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                     hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IPTAT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                                           hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT(mask)) >> OSCCTRL_XOSCCTRL_IPTAT_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_IPTAT_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_IPTAT(data);
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IPTAT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                        hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IPTAT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT_Msk) >> OSCCTRL_XOSCCTRL_IPTAT_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                     hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IMULT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                                           hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT(mask)) >> OSCCTRL_XOSCCTRL_IMULT_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_IMULT_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_IMULT(data);
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IMULT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                        hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IMULT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT_Msk) >> OSCCTRL_XOSCCTRL_IMULT_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_STARTUP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                                             hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                         hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_STARTUP(data);
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                         hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                          hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                        hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                                              hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC(mask)) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                          hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_CFDPRESC_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_CFDPRESC(data);
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                          hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                           hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC_Msk) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, uint8_t index,
+                                                                      hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLA_ENABLE) >> OSCCTRL_DFLLCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLA_ENABLE;
+	tmp |= value << OSCCTRL_DFLLCTRLA_ENABLE_Pos;
+	((Oscctrl *)hw)->DFLLCTRLA.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLA_RUNSTDBY) >> OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	tmp |= value << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->DFLLCTRLA.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLA_ONDEMAND) >> OSCCTRL_DFLLCTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLA_ONDEMAND;
+	tmp |= value << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos;
+	((Oscctrl *)hw)->DFLLCTRLA.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_get_DFLLCTRLA_reg(const void *const           hw,
+                                                                        hri_oscctrl_dfllctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_read_DFLLCTRLA_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLCTRLA.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_MODE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_MODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_MODE) >> OSCCTRL_DFLLCTRLB_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_MODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_MODE;
+	tmp |= value << OSCCTRL_DFLLCTRLB_MODE_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_MODE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_MODE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_STABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_STABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_STABLE) >> OSCCTRL_DFLLCTRLB_STABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_STABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_STABLE;
+	tmp |= value << OSCCTRL_DFLLCTRLB_STABLE_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_STABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_STABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_LLAW;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_LLAW_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_LLAW) >> OSCCTRL_DFLLCTRLB_LLAW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_LLAW_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_LLAW;
+	tmp |= value << OSCCTRL_DFLLCTRLB_LLAW_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_LLAW;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_LLAW;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_USBCRM;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_USBCRM_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_USBCRM) >> OSCCTRL_DFLLCTRLB_USBCRM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_USBCRM_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_USBCRM;
+	tmp |= value << OSCCTRL_DFLLCTRLB_USBCRM_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_USBCRM;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_USBCRM;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_CCDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_CCDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_CCDIS) >> OSCCTRL_DFLLCTRLB_CCDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_CCDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_CCDIS;
+	tmp |= value << OSCCTRL_DFLLCTRLB_CCDIS_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_CCDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_CCDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_QLDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_QLDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_QLDIS) >> OSCCTRL_DFLLCTRLB_QLDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_QLDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_QLDIS;
+	tmp |= value << OSCCTRL_DFLLCTRLB_QLDIS_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_QLDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_QLDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_BPLCKC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_BPLCKC_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_BPLCKC) >> OSCCTRL_DFLLCTRLB_BPLCKC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_BPLCKC_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_BPLCKC;
+	tmp |= value << OSCCTRL_DFLLCTRLB_BPLCKC_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_BPLCKC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_BPLCKC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_WAITLOCK;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_WAITLOCK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_WAITLOCK) >> OSCCTRL_DFLLCTRLB_WAITLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_WAITLOCK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_WAITLOCK;
+	tmp |= value << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_WAITLOCK;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_WAITLOCK;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_get_DFLLCTRLB_reg(const void *const           hw,
+                                                                        hri_oscctrl_dfllctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_read_DFLLCTRLB_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLCTRLB.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const         hw,
+                                                                        hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk;
+	tmp |= OSCCTRL_DFLLVAL_FINE(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const         hw,
+                                                                          hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk;
+	tmp |= OSCCTRL_DFLLVAL_COARSE(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const         hw,
+                                                                        hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk;
+	tmp |= OSCCTRL_DFLLVAL_DIFF(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const         hw,
+                                                                    hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLVAL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const         hw,
+                                                                       hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk;
+	tmp |= OSCCTRL_DFLLMUL_MUL(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const         hw,
+                                                                         hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk;
+	tmp |= OSCCTRL_DFLLMUL_FSTEP(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const         hw,
+                                                                         hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk;
+	tmp |= OSCCTRL_DFLLMUL_CSTEP(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const         hw,
+                                                                    hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLMUL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_ENABLE) >> OSCCTRL_DFLLSYNC_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_ENABLE;
+	tmp |= value << OSCCTRL_DFLLSYNC_ENABLE_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_DFLLCTRLB_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLCTRLB;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLCTRLB) >> OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_DFLLCTRLB_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB;
+	tmp |= value << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_DFLLCTRLB_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLCTRLB_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLCTRLB;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_DFLLVAL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLVAL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLVAL) >> OSCCTRL_DFLLSYNC_DFLLVAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_DFLLVAL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_DFLLVAL;
+	tmp |= value << OSCCTRL_DFLLSYNC_DFLLVAL_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_DFLLVAL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLVAL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLVAL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLVAL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_DFLLMUL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLMUL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLMUL) >> OSCCTRL_DFLLSYNC_DFLLMUL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_DFLLMUL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_DFLLMUL;
+	tmp |= value << OSCCTRL_DFLLSYNC_DFLLMUL_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_DFLLMUL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLMUL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLMUL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLMUL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const          hw,
+                                                                      hri_oscctrl_dfllsync_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLSYNC.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_OSCCTRL_D51_H_INCLUDED */
+#endif /* _SAMD51_OSCCTRL_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pac_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pac_d51.h
new file mode 100644
index 0000000..48a1aa4
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pac_d51.h
@@ -0,0 +1,1469 @@
+/**
+ * \file
+ *
+ * \brief SAM PAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_PAC_COMPONENT_
+#ifndef _HRI_PAC_D51_H_INCLUDED_
+#define _HRI_PAC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PAC_CRITICAL_SECTIONS)
+#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PAC_CRITICAL_SECTION_ENTER()
+#define PAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_pac_intflaga_reg_t;
+typedef uint32_t hri_pac_intflagahb_reg_t;
+typedef uint32_t hri_pac_intflagb_reg_t;
+typedef uint32_t hri_pac_intflagc_reg_t;
+typedef uint32_t hri_pac_intflagd_reg_t;
+typedef uint32_t hri_pac_statusa_reg_t;
+typedef uint32_t hri_pac_statusb_reg_t;
+typedef uint32_t hri_pac_statusc_reg_t;
+typedef uint32_t hri_pac_statusd_reg_t;
+typedef uint32_t hri_pac_wrctrl_reg_t;
+typedef uint8_t  hri_pac_evctrl_reg_t;
+typedef uint8_t  hri_pac_intenset_reg_t;
+
+static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_FLASH_ALT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH_ALT) >> PAC_INTFLAGAHB_FLASH_ALT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_FLASH_ALT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH_ALT;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_SEEPROM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SEEPROM) >> PAC_INTFLAGAHB_SEEPROM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_SEEPROM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SEEPROM;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_RAMCM4S_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMCM4S) >> PAC_INTFLAGAHB_RAMCM4S_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_RAMCM4S_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMCM4S;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMPPPDSU) >> PAC_INTFLAGAHB_RAMPPPDSU_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMPPPDSU;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_RAMDMAWR_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMAWR) >> PAC_INTFLAGAHB_RAMDMAWR_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_RAMDMAWR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMAWR;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_RAMDMACICM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMACICM) >> PAC_INTFLAGAHB_RAMDMACICM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_RAMDMACICM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMACICM;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_PUKCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_PUKCC) >> PAC_INTFLAGAHB_PUKCC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_PUKCC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_PUKCC;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_SDHC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC0) >> PAC_INTFLAGAHB_SDHC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_SDHC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC0;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_SDHC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC1) >> PAC_INTFLAGAHB_SDHC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_SDHC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC1;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_QSPI_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_QSPI) >> PAC_INTFLAGAHB_QSPI_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_QSPI_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_QSPI;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_BKUPRAM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_BKUPRAM) >> PAC_INTFLAGAHB_BKUPRAM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_BKUPRAM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_BKUPRAM;
+}
+
+static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGAHB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGAHB.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM;
+}
+
+static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK;
+}
+
+static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK;
+}
+
+static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT;
+}
+
+static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM;
+}
+
+static inline bool hri_pac_get_INTFLAGA_SERCOM0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM0) >> PAC_INTFLAGA_SERCOM0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_SERCOM0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM0;
+}
+
+static inline bool hri_pac_get_INTFLAGA_SERCOM1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM1) >> PAC_INTFLAGA_SERCOM1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_SERCOM1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM1;
+}
+
+static inline bool hri_pac_get_INTFLAGA_TC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC0) >> PAC_INTFLAGA_TC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_TC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC0;
+}
+
+static inline bool hri_pac_get_INTFLAGA_TC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC1) >> PAC_INTFLAGA_TC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_TC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC1;
+}
+
+static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGA.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGA.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB;
+}
+
+static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU;
+}
+
+static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGB_CMCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_CMCC) >> PAC_INTFLAGB_CMCC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_CMCC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_CMCC;
+}
+
+static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT;
+}
+
+static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC;
+}
+
+static inline bool hri_pac_get_INTFLAGB_HMATRIX_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIX) >> PAC_INTFLAGB_HMATRIX_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_HMATRIX_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIX;
+}
+
+static inline bool hri_pac_get_INTFLAGB_EVSYS_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_EVSYS) >> PAC_INTFLAGB_EVSYS_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_EVSYS_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_EVSYS;
+}
+
+static inline bool hri_pac_get_INTFLAGB_SERCOM2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM2) >> PAC_INTFLAGB_SERCOM2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_SERCOM2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM2;
+}
+
+static inline bool hri_pac_get_INTFLAGB_SERCOM3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM3) >> PAC_INTFLAGB_SERCOM3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_SERCOM3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM3;
+}
+
+static inline bool hri_pac_get_INTFLAGB_TCC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC0) >> PAC_INTFLAGB_TCC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_TCC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC0;
+}
+
+static inline bool hri_pac_get_INTFLAGB_TCC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC1) >> PAC_INTFLAGB_TCC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_TCC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC1;
+}
+
+static inline bool hri_pac_get_INTFLAGB_TC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC2) >> PAC_INTFLAGB_TC2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_TC2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC2;
+}
+
+static inline bool hri_pac_get_INTFLAGB_TC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC3) >> PAC_INTFLAGB_TC3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_TC3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC3;
+}
+
+static inline bool hri_pac_get_INTFLAGB_RAMECC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_RAMECC) >> PAC_INTFLAGB_RAMECC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_RAMECC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_RAMECC;
+}
+
+static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGB.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGB.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TCC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC3) >> PAC_INTFLAGC_TCC3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TCC3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC3;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC5) >> PAC_INTFLAGC_TC5_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC5_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC5;
+}
+
+static inline bool hri_pac_get_INTFLAGC_PDEC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PDEC) >> PAC_INTFLAGC_PDEC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_PDEC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PDEC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG;
+}
+
+static inline bool hri_pac_get_INTFLAGC_ICM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ICM) >> PAC_INTFLAGC_ICM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_ICM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ICM;
+}
+
+static inline bool hri_pac_get_INTFLAGC_PUKCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PUKCC) >> PAC_INTFLAGC_PUKCC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_PUKCC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PUKCC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_QSPI_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_QSPI) >> PAC_INTFLAGC_QSPI_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_QSPI_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_QSPI;
+}
+
+static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL;
+}
+
+static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGC.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGC.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGD_SERCOM4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM4) >> PAC_INTFLAGD_SERCOM4_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_SERCOM4_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM4;
+}
+
+static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5;
+}
+
+static inline bool hri_pac_get_INTFLAGD_SERCOM6_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM6) >> PAC_INTFLAGD_SERCOM6_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_SERCOM6_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM6;
+}
+
+static inline bool hri_pac_get_INTFLAGD_SERCOM7_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM7) >> PAC_INTFLAGD_SERCOM7_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_SERCOM7_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM7;
+}
+
+static inline bool hri_pac_get_INTFLAGD_TCC4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TCC4) >> PAC_INTFLAGD_TCC4_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_TCC4_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TCC4;
+}
+
+static inline bool hri_pac_get_INTFLAGD_TC6_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC6) >> PAC_INTFLAGD_TC6_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_TC6_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC6;
+}
+
+static inline bool hri_pac_get_INTFLAGD_TC7_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC7) >> PAC_INTFLAGD_TC7_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_TC7_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC7;
+}
+
+static inline bool hri_pac_get_INTFLAGD_ADC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC0) >> PAC_INTFLAGD_ADC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_ADC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC0;
+}
+
+static inline bool hri_pac_get_INTFLAGD_ADC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC1) >> PAC_INTFLAGD_ADC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_ADC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC1;
+}
+
+static inline bool hri_pac_get_INTFLAGD_DAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_DAC) >> PAC_INTFLAGD_DAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_DAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_DAC;
+}
+
+static inline bool hri_pac_get_INTFLAGD_I2S_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_I2S) >> PAC_INTFLAGD_I2S_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_I2S_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_I2S;
+}
+
+static inline bool hri_pac_get_INTFLAGD_PCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PCC) >> PAC_INTFLAGD_PCC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_PCC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PCC;
+}
+
+static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGD.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGD.reg = mask;
+}
+
+static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR;
+}
+
+static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR;
+	} else {
+		((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR;
+}
+
+static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	((Pac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data)
+{
+	((Pac *)hw)->INTENSET.reg = data;
+	((Pac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	((Pac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_SERCOM0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM0) >> PAC_STATUSA_SERCOM0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_SERCOM1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM1) >> PAC_STATUSA_SERCOM1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_TC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC0) >> PAC_STATUSA_TC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_TC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC1) >> PAC_STATUSA_TC1_Pos;
+}
+
+static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSA.reg;
+}
+
+static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_CMCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_CMCC) >> PAC_STATUSB_CMCC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_HMATRIX_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIX) >> PAC_STATUSB_HMATRIX_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_EVSYS_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_EVSYS) >> PAC_STATUSB_EVSYS_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_SERCOM2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM2) >> PAC_STATUSB_SERCOM2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_SERCOM3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM3) >> PAC_STATUSB_SERCOM3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_TCC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC0) >> PAC_STATUSB_TCC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_TCC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC1) >> PAC_STATUSB_TCC1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_TC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC2) >> PAC_STATUSB_TC2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_TC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC3) >> PAC_STATUSB_TC3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_RAMECC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_RAMECC) >> PAC_STATUSB_RAMECC_Pos;
+}
+
+static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSB.reg;
+}
+
+static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TCC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC3) >> PAC_STATUSC_TCC3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC5) >> PAC_STATUSC_TC5_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_PDEC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PDEC) >> PAC_STATUSC_PDEC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_ICM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ICM) >> PAC_STATUSC_ICM_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_PUKCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PUKCC) >> PAC_STATUSC_PUKCC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_QSPI_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_QSPI) >> PAC_STATUSC_QSPI_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos;
+}
+
+static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSC.reg;
+}
+
+static inline bool hri_pac_get_STATUSD_SERCOM4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM4) >> PAC_STATUSD_SERCOM4_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_SERCOM6_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM6) >> PAC_STATUSD_SERCOM6_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_SERCOM7_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM7) >> PAC_STATUSD_SERCOM7_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_TCC4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TCC4) >> PAC_STATUSD_TCC4_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_TC6_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC6) >> PAC_STATUSD_TC6_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_TC7_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC7) >> PAC_STATUSD_TC7_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_ADC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC0) >> PAC_STATUSD_ADC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_ADC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC1) >> PAC_STATUSD_ADC1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_DAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_DAC) >> PAC_STATUSD_DAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_I2S_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_I2S) >> PAC_STATUSD_I2S_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_PCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PCC) >> PAC_STATUSD_PCC_Pos;
+}
+
+static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSD.reg;
+}
+
+static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	uint32_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= ~PAC_WRCTRL_PERID_Msk;
+	tmp |= PAC_WRCTRL_PERID(data);
+	((Pac *)hw)->WRCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	uint32_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= ~PAC_WRCTRL_KEY_Msk;
+	tmp |= PAC_WRCTRL_KEY(data);
+	((Pac *)hw)->WRCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg = data;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw)
+{
+	return ((Pac *)hw)->WRCTRL.reg;
+}
+
+static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp &= ~PAC_EVCTRL_ERREO;
+	tmp |= value << PAC_EVCTRL_ERREO_Pos;
+	((Pac *)hw)->EVCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg |= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg = data;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg &= ~mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg ^= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Pac *)hw)->EVCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PAC_D51_H_INCLUDED */
+#endif /* _SAMD51_PAC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pcc_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pcc_d51.h
new file mode 100644
index 0000000..d3d8a3f
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pcc_d51.h
@@ -0,0 +1,298 @@
+/**
+ * \file
+ *
+ * \brief SAM PCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_PCC_COMPONENT_
+#ifndef _HRI_PCC_D51_H_INCLUDED_
+#define _HRI_PCC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PCC_CRITICAL_SECTIONS)
+#define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PCC_CRITICAL_SECTION_ENTER()
+#define PCC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_pcc_imr_reg_t;
+typedef uint32_t hri_pcc_isr_reg_t;
+typedef uint32_t hri_pcc_mr_reg_t;
+typedef uint32_t hri_pcc_rhr_reg_t;
+typedef uint32_t hri_pcc_wpmr_reg_t;
+typedef uint32_t hri_pcc_wpsr_reg_t;
+
+static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw)
+{
+	((Pcc *)hw)->IER.reg = PCC_IMR_DRDY;
+}
+
+static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos;
+}
+
+static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY;
+	} else {
+		((Pcc *)hw)->IER.reg = PCC_IMR_DRDY;
+	}
+}
+
+static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw)
+{
+	((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY;
+}
+
+static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw)
+{
+	((Pcc *)hw)->IER.reg = PCC_IMR_OVRE;
+}
+
+static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos;
+}
+
+static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE;
+	} else {
+		((Pcc *)hw)->IER.reg = PCC_IMR_OVRE;
+	}
+}
+
+static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw)
+{
+	((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE;
+}
+
+static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask)
+{
+	((Pcc *)hw)->IER.reg = mask;
+}
+
+static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->IMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->IMR.reg;
+}
+
+static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data)
+{
+	((Pcc *)hw)->IER.reg = data;
+	((Pcc *)hw)->IDR.reg = ~data;
+}
+
+static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask)
+{
+	((Pcc *)hw)->IDR.reg = mask;
+}
+
+static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos;
+}
+
+static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos;
+}
+
+static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->ISR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->ISR.reg;
+}
+
+static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask)
+{
+	return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos;
+}
+
+static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw)
+{
+	return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos;
+}
+
+static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->RHR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->RHR.reg;
+}
+
+static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos;
+}
+
+static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask)
+{
+	return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos;
+}
+
+static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw)
+{
+	return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos;
+}
+
+static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->WPSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->WPSR.reg;
+}
+
+static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->MR.reg |= mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->MR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->MR.reg = data;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->MR.reg &= ~mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->MR.reg ^= mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->MR.reg;
+}
+
+static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->WPMR.reg |= mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->WPMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->WPMR.reg = data;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->WPMR.reg &= ~mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->WPMR.reg ^= mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->WPMR.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PCC_D51_H_INCLUDED */
+#endif /* _SAMD51_PCC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pdec_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pdec_d51.h
new file mode 100644
index 0000000..a60ed70
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pdec_d51.h
@@ -0,0 +1,2684 @@
+/**
+ * \file
+ *
+ * \brief SAM PDEC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_PDEC_COMPONENT_
+#ifndef _HRI_PDEC_D51_H_INCLUDED_
+#define _HRI_PDEC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PDEC_CRITICAL_SECTIONS)
+#define PDEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PDEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PDEC_CRITICAL_SECTION_ENTER()
+#define PDEC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_pdec_evctrl_reg_t;
+typedef uint16_t hri_pdec_status_reg_t;
+typedef uint32_t hri_pdec_cc_reg_t;
+typedef uint32_t hri_pdec_ccbuf_reg_t;
+typedef uint32_t hri_pdec_count_reg_t;
+typedef uint32_t hri_pdec_ctrla_reg_t;
+typedef uint32_t hri_pdec_syncbusy_reg_t;
+typedef uint8_t  hri_pdec_ctrlbset_reg_t;
+typedef uint8_t  hri_pdec_dbgctrl_reg_t;
+typedef uint8_t  hri_pdec_filter_reg_t;
+typedef uint8_t  hri_pdec_filterbuf_reg_t;
+typedef uint8_t  hri_pdec_intenset_reg_t;
+typedef uint8_t  hri_pdec_intflag_reg_t;
+typedef uint8_t  hri_pdec_presc_reg_t;
+typedef uint8_t  hri_pdec_prescbuf_reg_t;
+
+static inline void hri_pdec_wait_for_sync(const void *const hw, hri_pdec_syncbusy_reg_t reg)
+{
+	while (((Pdec *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg)
+{
+	return ((Pdec *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_pdec_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF;
+}
+
+static inline bool hri_pdec_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR;
+}
+
+static inline bool hri_pdec_get_INTFLAG_DIR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_DIR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR;
+}
+
+static inline bool hri_pdec_get_INTFLAG_VLC_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_VLC_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC;
+}
+
+static inline bool hri_pdec_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0;
+}
+
+static inline bool hri_pdec_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1;
+}
+
+static inline bool hri_pdec_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF;
+}
+
+static inline bool hri_pdec_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR;
+}
+
+static inline bool hri_pdec_get_interrupt_DIR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_DIR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR;
+}
+
+static inline bool hri_pdec_get_interrupt_VLC_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_VLC_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC;
+}
+
+static inline bool hri_pdec_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0;
+}
+
+static inline bool hri_pdec_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1;
+}
+
+static inline hri_pdec_intflag_reg_t hri_pdec_get_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pdec_intflag_reg_t hri_pdec_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_pdec_clear_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask)
+{
+	((Pdec *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_pdec_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_pdec_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->CTRLBSET.reg & PDEC_CTRLBSET_LUPD) >> PDEC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_pdec_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD;
+	} else {
+		((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_pdec_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD;
+}
+
+static inline void hri_pdec_set_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->CTRLBSET.reg;
+	tmp = (tmp & PDEC_CTRLBSET_CMD(mask)) >> PDEC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->CTRLBSET.reg;
+	tmp = (tmp & PDEC_CTRLBSET_CMD_Msk) >> PDEC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t data)
+{
+	((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(data);
+	((Pdec *)hw)->CTRLBCLR.reg = ~PDEC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_pdec_clear_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_pdec_set_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	((Pdec *)hw)->CTRLBSET.reg = mask;
+}
+
+static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->CTRLBSET.reg;
+}
+
+static inline void hri_pdec_write_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t data)
+{
+	((Pdec *)hw)->CTRLBSET.reg = data;
+	((Pdec *)hw)->CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_pdec_clear_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	((Pdec *)hw)->CTRLBCLR.reg = mask;
+}
+
+static inline void hri_pdec_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF;
+}
+
+static inline bool hri_pdec_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_OVF) >> PDEC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF;
+}
+
+static inline void hri_pdec_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR;
+}
+
+static inline bool hri_pdec_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_ERR) >> PDEC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR;
+}
+
+static inline void hri_pdec_set_INTEN_DIR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR;
+}
+
+static inline bool hri_pdec_get_INTEN_DIR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_DIR) >> PDEC_INTENSET_DIR_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_DIR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR;
+}
+
+static inline void hri_pdec_set_INTEN_VLC_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC;
+}
+
+static inline bool hri_pdec_get_INTEN_VLC_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_VLC) >> PDEC_INTENSET_VLC_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_VLC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_VLC_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC;
+}
+
+static inline void hri_pdec_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0;
+}
+
+static inline bool hri_pdec_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC0) >> PDEC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0;
+}
+
+static inline void hri_pdec_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1;
+}
+
+static inline bool hri_pdec_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC1) >> PDEC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1;
+}
+
+static inline void hri_pdec_set_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask)
+{
+	((Pdec *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pdec_intenset_reg_t hri_pdec_get_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pdec_intenset_reg_t hri_pdec_read_INTEN_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pdec_write_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t data)
+{
+	((Pdec *)hw)->INTENSET.reg = data;
+	((Pdec *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pdec_clear_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask)
+{
+	((Pdec *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_SWRST) >> PDEC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_ENABLE) >> PDEC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CTRLB) >> PDEC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_STATUS) >> PDEC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_PRESC_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_PRESC) >> PDEC_SYNCBUSY_PRESC_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_FILTER_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_FILTER) >> PDEC_SYNCBUSY_FILTER_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_COUNT) >> PDEC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC0) >> PDEC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC1) >> PDEC_SYNCBUSY_CC1_Pos;
+}
+
+static inline hri_pdec_syncbusy_reg_t hri_pdec_get_SYNCBUSY_reg(const void *const hw, hri_pdec_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pdec_syncbusy_reg_t hri_pdec_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_pdec_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWRST;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST);
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_SWRST) >> PDEC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ENABLE;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_ENABLE) >> PDEC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_ENABLE;
+	tmp |= value << PDEC_CTRLA_ENABLE_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ENABLE;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_RUNSTDBY;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_RUNSTDBY) >> PDEC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_RUNSTDBY;
+	tmp |= value << PDEC_CTRLA_RUNSTDBY_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_RUNSTDBY;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_RUNSTDBY;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ALOCK;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_ALOCK) >> PDEC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_ALOCK;
+	tmp |= value << PDEC_CTRLA_ALOCK_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ALOCK;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ALOCK;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_SWAP_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWAP;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_SWAP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_SWAP) >> PDEC_CTRLA_SWAP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_SWAP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_SWAP;
+	tmp |= value << PDEC_CTRLA_SWAP_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_SWAP_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_SWAP;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_SWAP_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_SWAP;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PEREN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PEREN;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PEREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PEREN) >> PDEC_CTRLA_PEREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PEREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PEREN;
+	tmp |= value << PDEC_CTRLA_PEREN_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PEREN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PEREN;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PEREN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PEREN;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINEN0) >> PDEC_CTRLA_PINEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINEN0;
+	tmp |= value << PDEC_CTRLA_PINEN0_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINEN1) >> PDEC_CTRLA_PINEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINEN1;
+	tmp |= value << PDEC_CTRLA_PINEN1_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINEN2) >> PDEC_CTRLA_PINEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINEN2;
+	tmp |= value << PDEC_CTRLA_PINEN2_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINVEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINVEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINVEN0) >> PDEC_CTRLA_PINVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINVEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINVEN0;
+	tmp |= value << PDEC_CTRLA_PINVEN0_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINVEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINVEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINVEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINVEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINVEN1) >> PDEC_CTRLA_PINVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINVEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINVEN1;
+	tmp |= value << PDEC_CTRLA_PINVEN1_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINVEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINVEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINVEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINVEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINVEN2) >> PDEC_CTRLA_PINVEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINVEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINVEN2;
+	tmp |= value << PDEC_CTRLA_PINVEN2_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINVEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINVEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MODE(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_MODE(mask)) >> PDEC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_MODE_Msk;
+	tmp |= PDEC_CTRLA_MODE(data);
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MODE(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MODE(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_MODE_Msk) >> PDEC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_CONF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_CONF(mask)) >> PDEC_CTRLA_CONF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_CONF_Msk;
+	tmp |= PDEC_CTRLA_CONF(data);
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_CONF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_CONF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_CONF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_CONF_Msk) >> PDEC_CTRLA_CONF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ANGULAR(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_ANGULAR(mask)) >> PDEC_CTRLA_ANGULAR_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_ANGULAR_Msk;
+	tmp |= PDEC_CTRLA_ANGULAR(data);
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ANGULAR(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ANGULAR(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_ANGULAR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_ANGULAR_Msk) >> PDEC_CTRLA_ANGULAR_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MAXCMP(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_MAXCMP(mask)) >> PDEC_CTRLA_MAXCMP_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_MAXCMP_Msk;
+	tmp |= PDEC_CTRLA_MAXCMP(data);
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MAXCMP(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MAXCMP(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MAXCMP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_MAXCMP_Msk) >> PDEC_CTRLA_MAXCMP_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	return ((Pdec *)hw)->CTRLA.reg;
+}
+
+static inline void hri_pdec_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_OVFEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_OVFEO) >> PDEC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_OVFEO;
+	tmp |= value << PDEC_EVCTRL_OVFEO_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_OVFEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_OVFEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_ERREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_ERREO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_ERREO) >> PDEC_EVCTRL_ERREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_ERREO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_ERREO;
+	tmp |= value << PDEC_EVCTRL_ERREO_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_ERREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_ERREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_DIREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_DIREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_DIREO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_DIREO) >> PDEC_EVCTRL_DIREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_DIREO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_DIREO;
+	tmp |= value << PDEC_EVCTRL_DIREO_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_DIREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_DIREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_DIREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_DIREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_VLCEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_VLCEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_VLCEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_VLCEO) >> PDEC_EVCTRL_VLCEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_VLCEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_VLCEO;
+	tmp |= value << PDEC_EVCTRL_VLCEO_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_VLCEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_VLCEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_VLCEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_VLCEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO0;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_MCEO0) >> PDEC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_MCEO0;
+	tmp |= value << PDEC_EVCTRL_MCEO0_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO0;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO0;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO1;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_MCEO1) >> PDEC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_MCEO1;
+	tmp |= value << PDEC_EVCTRL_MCEO1_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO1;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO1;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVACT(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVACT(mask)) >> PDEC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_EVACT_Msk;
+	tmp |= PDEC_EVCTRL_EVACT(data);
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVACT(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVACT(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVACT_Msk) >> PDEC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVINV(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVINV(mask)) >> PDEC_EVCTRL_EVINV_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_EVINV_Msk;
+	tmp |= PDEC_EVCTRL_EVINV(data);
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVINV(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVINV(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVINV_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVINV_Msk) >> PDEC_EVCTRL_EVINV_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVEI(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVEI(mask)) >> PDEC_EVCTRL_EVEI_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_EVEI_Msk;
+	tmp |= PDEC_EVCTRL_EVEI(data);
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVEI(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVEI(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVEI_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVEI_Msk) >> PDEC_EVCTRL_EVEI_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg = data;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_pdec_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg |= PDEC_DBGCTRL_DBGRUN;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->DBGCTRL.reg;
+	tmp = (tmp & PDEC_DBGCTRL_DBGRUN) >> PDEC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->DBGCTRL.reg;
+	tmp &= ~PDEC_DBGCTRL_DBGRUN;
+	tmp |= value << PDEC_DBGCTRL_DBGRUN_Pos;
+	((Pdec *)hw)->DBGCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg &= ~PDEC_DBGCTRL_DBGRUN;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg ^= PDEC_DBGCTRL_DBGRUN;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg |= mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_dbgctrl_reg_t hri_pdec_get_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg = data;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg &= ~mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg ^= mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_dbgctrl_reg_t hri_pdec_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_pdec_set_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg |= PDEC_PRESC_PRESC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	tmp = ((Pdec *)hw)->PRESC.reg;
+	tmp = (tmp & PDEC_PRESC_PRESC(mask)) >> PDEC_PRESC_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t data)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->PRESC.reg;
+	tmp &= ~PDEC_PRESC_PRESC_Msk;
+	tmp |= PDEC_PRESC_PRESC(data);
+	((Pdec *)hw)->PRESC.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg &= ~PDEC_PRESC_PRESC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg ^= PDEC_PRESC_PRESC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_PRESC_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	tmp = ((Pdec *)hw)->PRESC.reg;
+	tmp = (tmp & PDEC_PRESC_PRESC_Msk) >> PDEC_PRESC_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	tmp = ((Pdec *)hw)->PRESC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	return ((Pdec *)hw)->PRESC.reg;
+}
+
+static inline void hri_pdec_set_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg |= PDEC_FILTER_FILTER(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	tmp = ((Pdec *)hw)->FILTER.reg;
+	tmp = (tmp & PDEC_FILTER_FILTER(mask)) >> PDEC_FILTER_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t data)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->FILTER.reg;
+	tmp &= ~PDEC_FILTER_FILTER_Msk;
+	tmp |= PDEC_FILTER_FILTER(data);
+	((Pdec *)hw)->FILTER.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg &= ~PDEC_FILTER_FILTER(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg ^= PDEC_FILTER_FILTER(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_FILTER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	tmp = ((Pdec *)hw)->FILTER.reg;
+	tmp = (tmp & PDEC_FILTER_FILTER_Msk) >> PDEC_FILTER_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	tmp = ((Pdec *)hw)->FILTER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	return ((Pdec *)hw)->FILTER.reg;
+}
+
+static inline void hri_pdec_set_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg |= PDEC_PRESCBUF_PRESCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_PRESCBUF_bf(const void *const       hw,
+                                                                        hri_pdec_prescbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->PRESCBUF.reg;
+	tmp = (tmp & PDEC_PRESCBUF_PRESCBUF(mask)) >> PDEC_PRESCBUF_PRESCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t data)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->PRESCBUF.reg;
+	tmp &= ~PDEC_PRESCBUF_PRESCBUF_Msk;
+	tmp |= PDEC_PRESCBUF_PRESCBUF(data);
+	((Pdec *)hw)->PRESCBUF.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg &= ~PDEC_PRESCBUF_PRESCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg ^= PDEC_PRESCBUF_PRESCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_PRESCBUF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->PRESCBUF.reg;
+	tmp = (tmp & PDEC_PRESCBUF_PRESCBUF_Msk) >> PDEC_PRESCBUF_PRESCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	tmp = ((Pdec *)hw)->PRESCBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return ((Pdec *)hw)->PRESCBUF.reg;
+}
+
+static inline void hri_pdec_set_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg |= PDEC_FILTERBUF_FILTERBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_FILTERBUF_bf(const void *const        hw,
+                                                                           hri_pdec_filterbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->FILTERBUF.reg;
+	tmp = (tmp & PDEC_FILTERBUF_FILTERBUF(mask)) >> PDEC_FILTERBUF_FILTERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t data)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->FILTERBUF.reg;
+	tmp &= ~PDEC_FILTERBUF_FILTERBUF_Msk;
+	tmp |= PDEC_FILTERBUF_FILTERBUF(data);
+	((Pdec *)hw)->FILTERBUF.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg &= ~PDEC_FILTERBUF_FILTERBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg ^= PDEC_FILTERBUF_FILTERBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_FILTERBUF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->FILTERBUF.reg;
+	tmp = (tmp & PDEC_FILTERBUF_FILTERBUF_Msk) >> PDEC_FILTERBUF_FILTERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	tmp = ((Pdec *)hw)->FILTERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return ((Pdec *)hw)->FILTERBUF.reg;
+}
+
+static inline void hri_pdec_set_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg |= PDEC_COUNT_COUNT(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	tmp = ((Pdec *)hw)->COUNT.reg;
+	tmp = (tmp & PDEC_COUNT_COUNT(mask)) >> PDEC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->COUNT.reg;
+	tmp &= ~PDEC_COUNT_COUNT_Msk;
+	tmp |= PDEC_COUNT_COUNT(data);
+	((Pdec *)hw)->COUNT.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg &= ~PDEC_COUNT_COUNT(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg ^= PDEC_COUNT_COUNT(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	tmp = ((Pdec *)hw)->COUNT.reg;
+	tmp = (tmp & PDEC_COUNT_COUNT_Msk) >> PDEC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	tmp = ((Pdec *)hw)->COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_COUNT_reg(const void *const hw, hri_pdec_count_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	return ((Pdec *)hw)->COUNT.reg;
+}
+
+static inline void hri_pdec_set_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg |= PDEC_CC_CC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_cc_reg_t hri_pdec_get_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	tmp = ((Pdec *)hw)->CC[index].reg;
+	tmp = (tmp & PDEC_CC_CC(mask)) >> PDEC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CC[index].reg;
+	tmp &= ~PDEC_CC_CC_Msk;
+	tmp |= PDEC_CC_CC(data);
+	((Pdec *)hw)->CC[index].reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg &= ~PDEC_CC_CC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg ^= PDEC_CC_CC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_cc_reg_t hri_pdec_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	tmp = ((Pdec *)hw)->CC[index].reg;
+	tmp = (tmp & PDEC_CC_CC_Msk) >> PDEC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_cc_reg_t hri_pdec_get_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	tmp = ((Pdec *)hw)->CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_cc_reg_t hri_pdec_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	return ((Pdec *)hw)->CC[index].reg;
+}
+
+static inline void hri_pdec_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg |= PDEC_CCBUF_CCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                               hri_pdec_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CCBUF[index].reg;
+	tmp = (tmp & PDEC_CCBUF_CCBUF(mask)) >> PDEC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CCBUF[index].reg;
+	tmp &= ~PDEC_CCBUF_CCBUF_Msk;
+	tmp |= PDEC_CCBUF_CCBUF(data);
+	((Pdec *)hw)->CCBUF[index].reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg &= ~PDEC_CCBUF_CCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg ^= PDEC_CCBUF_CCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CCBUF[index].reg;
+	tmp = (tmp & PDEC_CCBUF_CCBUF_Msk) >> PDEC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                          hri_pdec_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	tmp = ((Pdec *)hw)->CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return ((Pdec *)hw)->CCBUF[index].reg;
+}
+
+static inline bool hri_pdec_get_STATUS_QERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_QERR) >> PDEC_STATUS_QERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_QERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_QERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_IDXERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_IDXERR) >> PDEC_STATUS_IDXERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_IDXERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_IDXERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_MPERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_MPERR) >> PDEC_STATUS_MPERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_MPERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_MPERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_WINERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_WINERR) >> PDEC_STATUS_WINERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_WINERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_WINERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_HERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_HERR) >> PDEC_STATUS_HERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_HERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_HERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_STOP_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_STOP) >> PDEC_STATUS_STOP_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_STOP_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_STOP;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_DIR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_DIR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_PRESCBUFV_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_PRESCBUFV) >> PDEC_STATUS_PRESCBUFV_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_PRESCBUFV_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_PRESCBUFV;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_FILTERBUFV_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_FILTERBUFV) >> PDEC_STATUS_FILTERBUFV_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_FILTERBUFV_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_FILTERBUFV;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV0) >> PDEC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV1) >> PDEC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_status_reg_t hri_pdec_get_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask)
+{
+	uint16_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	tmp = ((Pdec *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_clear_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_status_reg_t hri_pdec_read_STATUS_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return ((Pdec *)hw)->STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PDEC_D51_H_INCLUDED */
+#endif /* _SAMD51_PDEC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pm_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pm_d51.h
new file mode 100644
index 0000000..730acdc
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_pm_d51.h
@@ -0,0 +1,820 @@
+/**
+ * \file
+ *
+ * \brief SAM PM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_PM_COMPONENT_
+#ifndef _HRI_PM_D51_H_INCLUDED_
+#define _HRI_PM_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PM_CRITICAL_SECTIONS)
+#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PM_CRITICAL_SECTION_ENTER()
+#define PM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint8_t hri_pm_bkupcfg_reg_t;
+typedef uint8_t hri_pm_ctrla_reg_t;
+typedef uint8_t hri_pm_hibcfg_reg_t;
+typedef uint8_t hri_pm_intenset_reg_t;
+typedef uint8_t hri_pm_intflag_reg_t;
+typedef uint8_t hri_pm_pwsakdly_reg_t;
+typedef uint8_t hri_pm_sleepcfg_reg_t;
+typedef uint8_t hri_pm_stdbycfg_reg_t;
+
+static inline bool hri_pm_get_INTFLAG_SLEEPRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos;
+}
+
+static inline void hri_pm_clear_INTFLAG_SLEEPRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY;
+}
+
+static inline bool hri_pm_get_interrupt_SLEEPRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos;
+}
+
+static inline void hri_pm_clear_interrupt_SLEEPRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY;
+}
+
+static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
+{
+	((Pm *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_pm_set_INTEN_SLEEPRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY;
+}
+
+static inline bool hri_pm_get_INTEN_SLEEPRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_SLEEPRDY) >> PM_INTENSET_SLEEPRDY_Pos;
+}
+
+static inline void hri_pm_write_INTEN_SLEEPRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY;
+	} else {
+		((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY;
+	}
+}
+
+static inline void hri_pm_clear_INTEN_SLEEPRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY;
+}
+
+static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	((Pm *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw)
+{
+	return ((Pm *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data)
+{
+	((Pm *)hw)->INTENSET.reg = data;
+	((Pm *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	((Pm *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp &= ~PM_CTRLA_IORET;
+	tmp |= value << PM_CTRLA_IORET_Pos;
+	((Pm *)hw)->CTRLA.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw)
+{
+	return ((Pm *)hw)->CTRLA.reg;
+}
+
+static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk;
+	tmp |= PM_SLEEPCFG_SLEEPMODE(data);
+	((Pm *)hw)->SLEEPCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->SLEEPCFG.reg;
+}
+
+static inline void hri_pm_set_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_RAMCFG(mask)) >> PM_STDBYCFG_RAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= ~PM_STDBYCFG_RAMCFG_Msk;
+	tmp |= PM_STDBYCFG_RAMCFG(data);
+	((Pm *)hw)->STDBYCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_RAMCFG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_RAMCFG_Msk) >> PM_STDBYCFG_RAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_FASTWKUP(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_FASTWKUP(mask)) >> PM_STDBYCFG_FASTWKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= ~PM_STDBYCFG_FASTWKUP_Msk;
+	tmp |= PM_STDBYCFG_FASTWKUP(data);
+	((Pm *)hw)->STDBYCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_FASTWKUP(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_FASTWKUP(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_FASTWKUP_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_FASTWKUP_Msk) >> PM_STDBYCFG_FASTWKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->STDBYCFG.reg;
+}
+
+static inline void hri_pm_set_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp = (tmp & PM_HIBCFG_RAMCFG(mask)) >> PM_HIBCFG_RAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp &= ~PM_HIBCFG_RAMCFG_Msk;
+	tmp |= PM_HIBCFG_RAMCFG(data);
+	((Pm *)hw)->HIBCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_RAMCFG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp = (tmp & PM_HIBCFG_RAMCFG_Msk) >> PM_HIBCFG_RAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp = (tmp & PM_HIBCFG_BRAMCFG(mask)) >> PM_HIBCFG_BRAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp &= ~PM_HIBCFG_BRAMCFG_Msk;
+	tmp |= PM_HIBCFG_BRAMCFG(data);
+	((Pm *)hw)->HIBCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_BRAMCFG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp = (tmp & PM_HIBCFG_BRAMCFG_Msk) >> PM_HIBCFG_BRAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->HIBCFG.reg;
+}
+
+static inline void hri_pm_set_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg |= PM_BKUPCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->BKUPCFG.reg;
+	tmp = (tmp & PM_BKUPCFG_BRAMCFG(mask)) >> PM_BKUPCFG_BRAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->BKUPCFG.reg;
+	tmp &= ~PM_BKUPCFG_BRAMCFG_Msk;
+	tmp |= PM_BKUPCFG_BRAMCFG(data);
+	((Pm *)hw)->BKUPCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg &= ~PM_BKUPCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg ^= PM_BKUPCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_BRAMCFG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->BKUPCFG.reg;
+	tmp = (tmp & PM_BKUPCFG_BRAMCFG_Msk) >> PM_BKUPCFG_BRAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->BKUPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->BKUPCFG.reg;
+}
+
+static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp &= ~PM_PWSAKDLY_IGNACK;
+	tmp |= value << PM_PWSAKDLY_IGNACK_Pos;
+	((Pm *)hw)->PWSAKDLY.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp &= ~PM_PWSAKDLY_DLYVAL_Msk;
+	tmp |= PM_PWSAKDLY_DLYVAL(data);
+	((Pm *)hw)->PWSAKDLY.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw)
+{
+	return ((Pm *)hw)->PWSAKDLY.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PM_D51_H_INCLUDED */
+#endif /* _SAMD51_PM_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_port_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_port_d51.h
new file mode 100644
index 0000000..947701a
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_port_d51.h
@@ -0,0 +1,2528 @@
+/**
+ * \file
+ *
+ * \brief SAM PORT
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_PORT_COMPONENT_
+#ifndef _HRI_PORT_D51_H_INCLUDED_
+#define _HRI_PORT_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PORT_CRITICAL_SECTIONS)
+#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PORT_CRITICAL_SECTION_ENTER()
+#define PORT_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_port_ctrl_reg_t;
+typedef uint32_t hri_port_dir_reg_t;
+typedef uint32_t hri_port_evctrl_reg_t;
+typedef uint32_t hri_port_in_reg_t;
+typedef uint32_t hri_port_out_reg_t;
+typedef uint32_t hri_port_wrconfig_reg_t;
+typedef uint32_t hri_portgroup_ctrl_reg_t;
+typedef uint32_t hri_portgroup_dir_reg_t;
+typedef uint32_t hri_portgroup_evctrl_reg_t;
+typedef uint32_t hri_portgroup_in_reg_t;
+typedef uint32_t hri_portgroup_out_reg_t;
+typedef uint32_t hri_portgroup_wrconfig_reg_t;
+typedef uint8_t  hri_port_pincfg_reg_t;
+typedef uint8_t  hri_port_pmux_reg_t;
+typedef uint8_t  hri_portgroup_pincfg_reg_t;
+typedef uint8_t  hri_portgroup_pmux_reg_t;
+
+static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask);
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data)
+{
+	((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data);
+	((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data);
+}
+
+static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRSET.reg = mask;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->DIR.reg;
+}
+
+static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data)
+{
+	((PortGroup *)hw)->DIRSET.reg = data;
+	((PortGroup *)hw)->DIRCLR.reg = ~data;
+}
+
+static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRCLR.reg = mask;
+}
+
+static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRTGL.reg = mask;
+}
+
+static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask);
+}
+
+static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data)
+{
+	((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data);
+	((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data);
+}
+
+static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTSET.reg = mask;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->OUT.reg;
+}
+
+static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data)
+{
+	((PortGroup *)hw)->OUTSET.reg = data;
+	((PortGroup *)hw)->OUTCLR.reg = ~data;
+}
+
+static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTCLR.reg = mask;
+}
+
+static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTTGL.reg = mask;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask)
+{
+	return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw)
+{
+	return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->IN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->IN.reg;
+}
+
+static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp &= ~PORT_CTRL_SAMPLING_Msk;
+	tmp |= PORT_CTRL_SAMPLING(data);
+	((PortGroup *)hw)->CTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->CTRL.reg;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI0;
+	tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI1;
+	tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI2;
+	tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI3;
+	tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID0_Msk;
+	tmp |= PORT_EVCTRL_PID0(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT0_Msk;
+	tmp |= PORT_EVCTRL_EVACT0(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID1_Msk;
+	tmp |= PORT_EVCTRL_PID1(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT1_Msk;
+	tmp |= PORT_EVCTRL_EVACT1(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID2_Msk;
+	tmp |= PORT_EVCTRL_PID2(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT2_Msk;
+	tmp |= PORT_EVCTRL_EVACT2(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID3_Msk;
+	tmp |= PORT_EVCTRL_PID3(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT3_Msk;
+	tmp |= PORT_EVCTRL_EVACT3(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index,
+                                                                  hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+	tmp |= PORT_PMUX_PMUXE(data);
+	((PortGroup *)hw)->PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index,
+                                                                  hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+	tmp |= PORT_PMUX_PMUXO(data);
+	((PortGroup *)hw)->PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index,
+                                                             hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index)
+{
+	return ((PortGroup *)hw)->PMUX[index].reg;
+}
+
+static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_INEN;
+	tmp |= value << PORT_PINCFG_INEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PULLEN;
+	tmp |= value << PORT_PINCFG_PULLEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_DRVSTR;
+	tmp |= value << PORT_PINCFG_DRVSTR_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index,
+                                                                 hri_port_pincfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index)
+{
+	return ((PortGroup *)hw)->PINCFG[index].reg;
+}
+
+static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->WRCONFIG.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask);
+}
+
+static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data);
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data);
+}
+
+static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+}
+
+static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].DIR.reg;
+}
+
+static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = data;
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data;
+}
+
+static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+}
+
+static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask;
+}
+
+static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask);
+}
+
+static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data);
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data);
+}
+
+static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
+}
+
+static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].OUT.reg;
+}
+
+static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = data;
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data;
+}
+
+static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+}
+
+static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask;
+}
+
+static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_in_reg_t mask)
+{
+	return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index)
+{
+	return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_in_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].IN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].IN.reg;
+}
+
+static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_ctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp &= ~PORT_CTRL_SAMPLING_Msk;
+	tmp |= PORT_CTRL_SAMPLING(data);
+	((Port *)hw)->Group[submodule_index].CTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].CTRL.reg;
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI0;
+	tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI1;
+	tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI2;
+	tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI3;
+	tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID0_Msk;
+	tmp |= PORT_EVCTRL_PID0(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT0_Msk;
+	tmp |= PORT_EVCTRL_EVACT0(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID1_Msk;
+	tmp |= PORT_EVCTRL_PID1(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT1_Msk;
+	tmp |= PORT_EVCTRL_EVACT1(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID2_Msk;
+	tmp |= PORT_EVCTRL_PID2(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT2_Msk;
+	tmp |= PORT_EVCTRL_EVACT2(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID3_Msk;
+	tmp |= PORT_EVCTRL_PID3(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT3_Msk;
+	tmp |= PORT_EVCTRL_EVACT3(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+}
+
+static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index, hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+	tmp |= PORT_PMUX_PMUXE(data);
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                 hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
+                                                              uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index, hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+	tmp |= PORT_PMUX_PMUXO(data);
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                 hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
+                                                              uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                         hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                        hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pmux_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                            hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	return ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+}
+
+static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                  bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_INEN;
+	tmp |= value << PORT_PINCFG_INEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PULLEN;
+	tmp |= value << PORT_PINCFG_PULLEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_DRVSTR;
+	tmp |= value << PORT_PINCFG_DRVSTR_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                            uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                             hri_port_pincfg_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                             hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index)
+{
+	return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+}
+
+static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PORT_D51_H_INCLUDED */
+#endif /* _SAMD51_PORT_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_qspi_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_qspi_d51.h
new file mode 100644
index 0000000..1d2fc5e
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_qspi_d51.h
@@ -0,0 +1,2058 @@
+/**
+ * \file
+ *
+ * \brief SAM QSPI
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_QSPI_COMPONENT_
+#ifndef _HRI_QSPI_D51_H_INCLUDED_
+#define _HRI_QSPI_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_QSPI_CRITICAL_SECTIONS)
+#define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define QSPI_CRITICAL_SECTION_ENTER()
+#define QSPI_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_qspi_baud_reg_t;
+typedef uint32_t hri_qspi_ctrla_reg_t;
+typedef uint32_t hri_qspi_ctrlb_reg_t;
+typedef uint32_t hri_qspi_instraddr_reg_t;
+typedef uint32_t hri_qspi_instrctrl_reg_t;
+typedef uint32_t hri_qspi_instrframe_reg_t;
+typedef uint32_t hri_qspi_intenset_reg_t;
+typedef uint32_t hri_qspi_intflag_reg_t;
+typedef uint32_t hri_qspi_rxdata_reg_t;
+typedef uint32_t hri_qspi_scrambctrl_reg_t;
+typedef uint32_t hri_qspi_scrambkey_reg_t;
+typedef uint32_t hri_qspi_status_reg_t;
+typedef uint32_t hri_qspi_txdata_reg_t;
+
+static inline bool hri_qspi_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC;
+}
+
+static inline bool hri_qspi_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE;
+}
+
+static inline bool hri_qspi_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC;
+}
+
+static inline bool hri_qspi_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR;
+}
+
+static inline bool hri_qspi_get_INTFLAG_CSRISE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_CSRISE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE;
+}
+
+static inline bool hri_qspi_get_INTFLAG_INSTREND_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_INSTREND_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
+}
+
+static inline bool hri_qspi_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC;
+}
+
+static inline bool hri_qspi_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE;
+}
+
+static inline bool hri_qspi_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC;
+}
+
+static inline bool hri_qspi_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR;
+}
+
+static inline bool hri_qspi_get_interrupt_CSRISE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_CSRISE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE;
+}
+
+static inline bool hri_qspi_get_interrupt_INSTREND_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_INSTREND_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
+}
+
+static inline hri_qspi_intflag_reg_t hri_qspi_get_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_qspi_intflag_reg_t hri_qspi_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_qspi_clear_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask)
+{
+	((Qspi *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_qspi_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC;
+}
+
+static inline bool hri_qspi_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_RXC) >> QSPI_INTENSET_RXC_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC;
+}
+
+static inline void hri_qspi_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE;
+}
+
+static inline bool hri_qspi_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_DRE) >> QSPI_INTENSET_DRE_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE;
+}
+
+static inline void hri_qspi_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC;
+}
+
+static inline bool hri_qspi_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_TXC) >> QSPI_INTENSET_TXC_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC;
+}
+
+static inline void hri_qspi_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR;
+}
+
+static inline bool hri_qspi_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_ERROR) >> QSPI_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR;
+}
+
+static inline void hri_qspi_set_INTEN_CSRISE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE;
+}
+
+static inline bool hri_qspi_get_INTEN_CSRISE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_CSRISE) >> QSPI_INTENSET_CSRISE_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_CSRISE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_CSRISE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE;
+}
+
+static inline void hri_qspi_set_INTEN_INSTREND_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND;
+}
+
+static inline bool hri_qspi_get_INTEN_INSTREND_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_INSTREND) >> QSPI_INTENSET_INSTREND_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_INSTREND_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_INSTREND_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND;
+}
+
+static inline void hri_qspi_set_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask)
+{
+	((Qspi *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_qspi_intenset_reg_t hri_qspi_get_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_qspi_intenset_reg_t hri_qspi_read_INTEN_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INTENSET.reg;
+}
+
+static inline void hri_qspi_write_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t data)
+{
+	((Qspi *)hw)->INTENSET.reg = data;
+	((Qspi *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_qspi_clear_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask)
+{
+	((Qspi *)hw)->INTENCLR.reg = mask;
+}
+
+static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_DATA_bf(const void *const hw, hri_qspi_rxdata_reg_t mask)
+{
+	return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA(mask)) >> QSPI_RXDATA_DATA_Pos;
+}
+
+static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_DATA_bf(const void *const hw)
+{
+	return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos;
+}
+
+static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_reg(const void *const hw, hri_qspi_rxdata_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->RXDATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->RXDATA.reg;
+}
+
+static inline bool hri_qspi_get_STATUS_ENABLE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_ENABLE) >> QSPI_STATUS_ENABLE_Pos;
+}
+
+static inline bool hri_qspi_get_STATUS_CSSTATUS_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_CSSTATUS) >> QSPI_STATUS_CSSTATUS_Pos;
+}
+
+static inline hri_qspi_status_reg_t hri_qspi_get_STATUS_reg(const void *const hw, hri_qspi_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_qspi_status_reg_t hri_qspi_read_STATUS_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->STATUS.reg;
+}
+
+static inline void hri_qspi_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_SWRST;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp = (tmp & QSPI_CTRLA_SWRST) >> QSPI_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp = (tmp & QSPI_CTRLA_ENABLE) >> QSPI_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp &= ~QSPI_CTRLA_ENABLE;
+	tmp |= value << QSPI_CTRLA_ENABLE_Pos;
+	((Qspi *)hw)->CTRLA.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLA_LASTXFER_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_LASTXFER;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLA_LASTXFER_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp = (tmp & QSPI_CTRLA_LASTXFER) >> QSPI_CTRLA_LASTXFER_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLA_LASTXFER_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp &= ~QSPI_CTRLA_LASTXFER;
+	tmp |= value << QSPI_CTRLA_LASTXFER_Pos;
+	((Qspi *)hw)->CTRLA.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLA_LASTXFER_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_LASTXFER;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLA_LASTXFER_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_LASTXFER;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrla_reg_t hri_qspi_get_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrla_reg_t hri_qspi_read_CTRLA_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->CTRLA.reg;
+}
+
+static inline void hri_qspi_set_CTRLB_MODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_MODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLB_MODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_MODE) >> QSPI_CTRLB_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_MODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_MODE;
+	tmp |= value << QSPI_CTRLB_MODE_Pos;
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_MODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_MODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_MODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_MODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLB_LOOPEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_LOOPEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLB_LOOPEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_LOOPEN) >> QSPI_CTRLB_LOOPEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_LOOPEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_LOOPEN;
+	tmp |= value << QSPI_CTRLB_LOOPEN_Pos;
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_LOOPEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_LOOPEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_LOOPEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_LOOPEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLB_WDRBT_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_WDRBT;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLB_WDRBT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_WDRBT) >> QSPI_CTRLB_WDRBT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_WDRBT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_WDRBT;
+	tmp |= value << QSPI_CTRLB_WDRBT_Pos;
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_WDRBT_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_WDRBT;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_WDRBT_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_WDRBT;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLB_SMEMREG_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_SMEMREG;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLB_SMEMREG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_SMEMREG) >> QSPI_CTRLB_SMEMREG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_SMEMREG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_SMEMREG;
+	tmp |= value << QSPI_CTRLB_SMEMREG_Pos;
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_SMEMREG_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_SMEMREG;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_SMEMREG_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_SMEMREG;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_CSMODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_CSMODE(mask)) >> QSPI_CTRLB_CSMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_CSMODE_Msk;
+	tmp |= QSPI_CTRLB_CSMODE(data);
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_CSMODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_CSMODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_CSMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_CSMODE_Msk) >> QSPI_CTRLB_CSMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DATALEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DATALEN(mask)) >> QSPI_CTRLB_DATALEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_DATALEN_Msk;
+	tmp |= QSPI_CTRLB_DATALEN(data);
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DATALEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DATALEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DATALEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DATALEN_Msk) >> QSPI_CTRLB_DATALEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYBCT(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DLYBCT(mask)) >> QSPI_CTRLB_DLYBCT_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_DLYBCT_Msk;
+	tmp |= QSPI_CTRLB_DLYBCT(data);
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYBCT(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYBCT(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYBCT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DLYBCT_Msk) >> QSPI_CTRLB_DLYBCT_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYCS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DLYCS(mask)) >> QSPI_CTRLB_DLYCS_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_DLYCS_Msk;
+	tmp |= QSPI_CTRLB_DLYCS(data);
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYCS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYCS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYCS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DLYCS_Msk) >> QSPI_CTRLB_DLYCS_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->CTRLB.reg;
+}
+
+static inline void hri_qspi_set_BAUD_CPOL_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPOL;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_BAUD_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_CPOL) >> QSPI_BAUD_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_BAUD_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= ~QSPI_BAUD_CPOL;
+	tmp |= value << QSPI_BAUD_CPOL_Pos;
+	((Qspi *)hw)->BAUD.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_CPOL_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPOL;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_CPOL_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPOL;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_BAUD_CPHA_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPHA;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_BAUD_CPHA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_CPHA) >> QSPI_BAUD_CPHA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_BAUD_CPHA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= ~QSPI_BAUD_CPHA;
+	tmp |= value << QSPI_BAUD_CPHA_Pos;
+	((Qspi *)hw)->BAUD.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_CPHA_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPHA;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_CPHA_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPHA;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_BAUD(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_BAUD(mask)) >> QSPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= ~QSPI_BAUD_BAUD_Msk;
+	tmp |= QSPI_BAUD_BAUD(data);
+	((Qspi *)hw)->BAUD.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_BAUD(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_BAUD(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_BAUD_Msk) >> QSPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_DLYBS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_DLYBS(mask)) >> QSPI_BAUD_DLYBS_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= ~QSPI_BAUD_DLYBS_Msk;
+	tmp |= QSPI_BAUD_DLYBS(data);
+	((Qspi *)hw)->BAUD.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_DLYBS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_DLYBS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_DLYBS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_DLYBS_Msk) >> QSPI_BAUD_DLYBS_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->BAUD.reg;
+}
+
+static inline void hri_qspi_set_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg |= QSPI_INSTRADDR_ADDR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_ADDR_bf(const void *const        hw,
+                                                                      hri_qspi_instraddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRADDR.reg;
+	tmp = (tmp & QSPI_INSTRADDR_ADDR(mask)) >> QSPI_INSTRADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRADDR.reg;
+	tmp &= ~QSPI_INSTRADDR_ADDR_Msk;
+	tmp |= QSPI_INSTRADDR_ADDR(data);
+	((Qspi *)hw)->INSTRADDR.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg &= ~QSPI_INSTRADDR_ADDR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg ^= QSPI_INSTRADDR_ADDR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRADDR.reg;
+	tmp = (tmp & QSPI_INSTRADDR_ADDR_Msk) >> QSPI_INSTRADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INSTRADDR.reg;
+}
+
+static inline void hri_qspi_set_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_INSTR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_INSTR_bf(const void *const        hw,
+                                                                       hri_qspi_instrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp = (tmp & QSPI_INSTRCTRL_INSTR(mask)) >> QSPI_INSTRCTRL_INSTR_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp &= ~QSPI_INSTRCTRL_INSTR_Msk;
+	tmp |= QSPI_INSTRCTRL_INSTR(data);
+	((Qspi *)hw)->INSTRCTRL.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_INSTR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_INSTR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_INSTR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp = (tmp & QSPI_INSTRCTRL_INSTR_Msk) >> QSPI_INSTRCTRL_INSTR_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_OPTCODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_OPTCODE_bf(const void *const        hw,
+                                                                         hri_qspi_instrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp = (tmp & QSPI_INSTRCTRL_OPTCODE(mask)) >> QSPI_INSTRCTRL_OPTCODE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp &= ~QSPI_INSTRCTRL_OPTCODE_Msk;
+	tmp |= QSPI_INSTRCTRL_OPTCODE(data);
+	((Qspi *)hw)->INSTRCTRL.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_OPTCODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_OPTCODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_OPTCODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp = (tmp & QSPI_INSTRCTRL_OPTCODE_Msk) >> QSPI_INSTRCTRL_OPTCODE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INSTRCTRL.reg;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_INSTREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_INSTREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_INSTREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_INSTREN) >> QSPI_INSTRFRAME_INSTREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_INSTREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_INSTREN;
+	tmp |= value << QSPI_INSTRFRAME_INSTREN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_INSTREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_INSTREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_INSTREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_INSTREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_ADDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_ADDREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_ADDREN) >> QSPI_INSTRFRAME_ADDREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_ADDREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_ADDREN;
+	tmp |= value << QSPI_INSTRFRAME_ADDREN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_ADDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_ADDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_OPTCODEEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODEEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_OPTCODEEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_OPTCODEEN) >> QSPI_INSTRFRAME_OPTCODEEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_OPTCODEEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_OPTCODEEN;
+	tmp |= value << QSPI_INSTRFRAME_OPTCODEEN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_OPTCODEEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODEEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_OPTCODEEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODEEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_DATAEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DATAEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_DATAEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_DATAEN) >> QSPI_INSTRFRAME_DATAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_DATAEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_DATAEN;
+	tmp |= value << QSPI_INSTRFRAME_DATAEN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_DATAEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DATAEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_DATAEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DATAEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_ADDRLEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDRLEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_ADDRLEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_ADDRLEN) >> QSPI_INSTRFRAME_ADDRLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_ADDRLEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_ADDRLEN;
+	tmp |= value << QSPI_INSTRFRAME_ADDRLEN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_ADDRLEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDRLEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_ADDRLEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDRLEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_CRMODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_CRMODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_CRMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_CRMODE) >> QSPI_INSTRFRAME_CRMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_CRMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_CRMODE;
+	tmp |= value << QSPI_INSTRFRAME_CRMODE_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_CRMODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_CRMODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_CRMODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_CRMODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_DDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_DDREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_DDREN) >> QSPI_INSTRFRAME_DDREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_DDREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_DDREN;
+	tmp |= value << QSPI_INSTRFRAME_DDREN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_DDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_DDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_WIDTH(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_WIDTH_bf(const void *const         hw,
+                                                                         hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_WIDTH(mask)) >> QSPI_INSTRFRAME_WIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_WIDTH_Msk;
+	tmp |= QSPI_INSTRFRAME_WIDTH(data);
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_WIDTH(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_WIDTH(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_WIDTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_WIDTH_Msk) >> QSPI_INSTRFRAME_WIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODELEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_OPTCODELEN_bf(const void *const         hw,
+                                                                              hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN(mask)) >> QSPI_INSTRFRAME_OPTCODELEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_OPTCODELEN_Msk;
+	tmp |= QSPI_INSTRFRAME_OPTCODELEN(data);
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODELEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODELEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_OPTCODELEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN_Msk) >> QSPI_INSTRFRAME_OPTCODELEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_TFRTYPE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_TFRTYPE_bf(const void *const         hw,
+                                                                           hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE(mask)) >> QSPI_INSTRFRAME_TFRTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_TFRTYPE_Msk;
+	tmp |= QSPI_INSTRFRAME_TFRTYPE(data);
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_TFRTYPE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_TFRTYPE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_TFRTYPE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE_Msk) >> QSPI_INSTRFRAME_TFRTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DUMMYLEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_DUMMYLEN_bf(const void *const         hw,
+                                                                            hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN(mask)) >> QSPI_INSTRFRAME_DUMMYLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_DUMMYLEN_Msk;
+	tmp |= QSPI_INSTRFRAME_DUMMYLEN(data);
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DUMMYLEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DUMMYLEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_DUMMYLEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN_Msk) >> QSPI_INSTRFRAME_DUMMYLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_reg(const void *const         hw,
+                                                                    hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INSTRFRAME.reg;
+}
+
+static inline void hri_qspi_set_SCRAMBCTRL_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_SCRAMBCTRL_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp = (tmp & QSPI_SCRAMBCTRL_ENABLE) >> QSPI_SCRAMBCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_SCRAMBCTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp &= ~QSPI_SCRAMBCTRL_ENABLE;
+	tmp |= value << QSPI_SCRAMBCTRL_ENABLE_Pos;
+	((Qspi *)hw)->SCRAMBCTRL.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_SCRAMBCTRL_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_SCRAMBCTRL_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_RANDOMDIS;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp = (tmp & QSPI_SCRAMBCTRL_RANDOMDIS) >> QSPI_SCRAMBCTRL_RANDOMDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp &= ~QSPI_SCRAMBCTRL_RANDOMDIS;
+	tmp |= value << QSPI_SCRAMBCTRL_RANDOMDIS_Pos;
+	((Qspi *)hw)->SCRAMBCTRL.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_RANDOMDIS;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_RANDOMDIS;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_scrambctrl_reg_t hri_qspi_get_SCRAMBCTRL_reg(const void *const         hw,
+                                                                    hri_qspi_scrambctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_scrambctrl_reg_t hri_qspi_read_SCRAMBCTRL_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->SCRAMBCTRL.reg;
+}
+
+static inline void hri_qspi_write_TXDATA_reg(const void *const hw, hri_qspi_txdata_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->TXDATA.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_write_SCRAMBKEY_reg(const void *const hw, hri_qspi_scrambkey_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBKEY.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_QSPI_D51_H_INCLUDED */
+#endif /* _SAMD51_QSPI_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_ramecc_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_ramecc_d51.h
new file mode 100644
index 0000000..072c9e2
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_ramecc_d51.h
@@ -0,0 +1,362 @@
+/**
+ * \file
+ *
+ * \brief SAM RAMECC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_RAMECC_COMPONENT_
+#ifndef _HRI_RAMECC_D51_H_INCLUDED_
+#define _HRI_RAMECC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RAMECC_CRITICAL_SECTIONS)
+#define RAMECC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RAMECC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RAMECC_CRITICAL_SECTION_ENTER()
+#define RAMECC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_ramecc_erraddr_reg_t;
+typedef uint8_t  hri_ramecc_dbgctrl_reg_t;
+typedef uint8_t  hri_ramecc_intenset_reg_t;
+typedef uint8_t  hri_ramecc_intflag_reg_t;
+typedef uint8_t  hri_ramecc_status_reg_t;
+
+static inline bool hri_ramecc_get_INTFLAG_SINGLEE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos;
+}
+
+static inline void hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE;
+}
+
+static inline bool hri_ramecc_get_INTFLAG_DUALE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos;
+}
+
+static inline void hri_ramecc_clear_INTFLAG_DUALE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE;
+}
+
+static inline bool hri_ramecc_get_interrupt_SINGLEE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos;
+}
+
+static inline void hri_ramecc_clear_interrupt_SINGLEE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE;
+}
+
+static inline bool hri_ramecc_get_interrupt_DUALE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos;
+}
+
+static inline void hri_ramecc_clear_interrupt_DUALE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE;
+}
+
+static inline hri_ramecc_intflag_reg_t hri_ramecc_get_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_ramecc_clear_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask)
+{
+	((Ramecc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_ramecc_set_INTEN_SINGLEE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE;
+}
+
+static inline bool hri_ramecc_get_INTEN_SINGLEE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_SINGLEE) >> RAMECC_INTENSET_SINGLEE_Pos;
+}
+
+static inline void hri_ramecc_write_INTEN_SINGLEE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE;
+	} else {
+		((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE;
+	}
+}
+
+static inline void hri_ramecc_clear_INTEN_SINGLEE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE;
+}
+
+static inline void hri_ramecc_set_INTEN_DUALE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE;
+}
+
+static inline bool hri_ramecc_get_INTEN_DUALE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_DUALE) >> RAMECC_INTENSET_DUALE_Pos;
+}
+
+static inline void hri_ramecc_write_INTEN_DUALE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE;
+	} else {
+		((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE;
+	}
+}
+
+static inline void hri_ramecc_clear_INTEN_DUALE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE;
+}
+
+static inline void hri_ramecc_set_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask)
+{
+	((Ramecc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_ramecc_intenset_reg_t hri_ramecc_get_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ramecc_intenset_reg_t hri_ramecc_read_INTEN_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_ramecc_write_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t data)
+{
+	((Ramecc *)hw)->INTENSET.reg = data;
+	((Ramecc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_ramecc_clear_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask)
+{
+	((Ramecc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_ramecc_get_STATUS_ECCDIS_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->STATUS.reg & RAMECC_STATUS_ECCDIS) >> RAMECC_STATUS_ECCDIS_Pos;
+}
+
+static inline hri_ramecc_status_reg_t hri_ramecc_get_STATUS_reg(const void *const hw, hri_ramecc_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ramecc_status_reg_t hri_ramecc_read_STATUS_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->STATUS.reg;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_ERRADDR_bf(const void *const        hw,
+                                                                         hri_ramecc_erraddr_reg_t mask)
+{
+	return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR(mask)) >> RAMECC_ERRADDR_ERRADDR_Pos;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_ERRADDR_bf(const void *const hw)
+{
+	return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR_Msk) >> RAMECC_ERRADDR_ERRADDR_Pos;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_reg(const void *const hw, hri_ramecc_erraddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ramecc *)hw)->ERRADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->ERRADDR.reg;
+}
+
+static inline void hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCDIS;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & RAMECC_DBGCTRL_ECCDIS) >> RAMECC_DBGCTRL_ECCDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RAMECC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp &= ~RAMECC_DBGCTRL_ECCDIS;
+	tmp |= value << RAMECC_DBGCTRL_ECCDIS_Pos;
+	((Ramecc *)hw)->DBGCTRL.reg = tmp;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCDIS;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCDIS;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCELOG;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & RAMECC_DBGCTRL_ECCELOG) >> RAMECC_DBGCTRL_ECCELOG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RAMECC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp &= ~RAMECC_DBGCTRL_ECCELOG;
+	tmp |= value << RAMECC_DBGCTRL_ECCELOG_Pos;
+	((Ramecc *)hw)->DBGCTRL.reg = tmp;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCELOG;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCELOG;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_set_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg |= mask;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_get_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ramecc_write_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t data)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg = data;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_clear_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg &= ~mask;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_toggle_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg ^= mask;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->DBGCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RAMECC_D51_H_INCLUDED */
+#endif /* _SAMD51_RAMECC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_rstc_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_rstc_d51.h
new file mode 100644
index 0000000..7e6b6ee
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_rstc_d51.h
@@ -0,0 +1,142 @@
+/**
+ * \file
+ *
+ * \brief SAM RSTC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_RSTC_COMPONENT_
+#ifndef _HRI_RSTC_D51_H_INCLUDED_
+#define _HRI_RSTC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RSTC_CRITICAL_SECTIONS)
+#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RSTC_CRITICAL_SECTION_ENTER()
+#define RSTC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint8_t hri_rstc_bkupexit_reg_t;
+typedef uint8_t hri_rstc_rcause_reg_t;
+
+static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_NVM_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_NVM) >> RSTC_RCAUSE_NVM_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos;
+}
+
+static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rstc *)hw)->RCAUSE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw)
+{
+	return ((Rstc *)hw)->RCAUSE.reg;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_HIB_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_HIB) >> RSTC_BKUPEXIT_HIB_Pos;
+}
+
+static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rstc *)hw)->BKUPEXIT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw)
+{
+	return ((Rstc *)hw)->BKUPEXIT.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RSTC_D51_H_INCLUDED */
+#endif /* _SAMD51_RSTC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_rtc_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_rtc_d51.h
new file mode 100644
index 0000000..4947029
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_rtc_d51.h
@@ -0,0 +1,10139 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_RTC_COMPONENT_
+#ifndef _HRI_RTC_D51_H_INCLUDED_
+#define _HRI_RTC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RTC_CRITICAL_SECTIONS)
+#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RTC_CRITICAL_SECTION_ENTER()
+#define RTC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_rtcmode0_ctrla_reg_t;
+typedef uint16_t hri_rtcmode0_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode0_intenset_reg_t;
+typedef uint16_t hri_rtcmode0_intflag_reg_t;
+typedef uint16_t hri_rtcmode1_comp_reg_t;
+typedef uint16_t hri_rtcmode1_count_reg_t;
+typedef uint16_t hri_rtcmode1_ctrla_reg_t;
+typedef uint16_t hri_rtcmode1_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode1_intenset_reg_t;
+typedef uint16_t hri_rtcmode1_intflag_reg_t;
+typedef uint16_t hri_rtcmode1_per_reg_t;
+typedef uint16_t hri_rtcmode2_ctrla_reg_t;
+typedef uint16_t hri_rtcmode2_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode2_intenset_reg_t;
+typedef uint16_t hri_rtcmode2_intflag_reg_t;
+typedef uint32_t hri_rtc_bkup_reg_t;
+typedef uint32_t hri_rtc_gp_reg_t;
+typedef uint32_t hri_rtc_tampctrl_reg_t;
+typedef uint32_t hri_rtc_tampid_reg_t;
+typedef uint32_t hri_rtcalarm_alarm_reg_t;
+typedef uint32_t hri_rtcmode0_comp_reg_t;
+typedef uint32_t hri_rtcmode0_count_reg_t;
+typedef uint32_t hri_rtcmode0_evctrl_reg_t;
+typedef uint32_t hri_rtcmode0_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode0_timestamp_reg_t;
+typedef uint32_t hri_rtcmode1_evctrl_reg_t;
+typedef uint32_t hri_rtcmode1_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode1_timestamp_reg_t;
+typedef uint32_t hri_rtcmode2_alarm_reg_t;
+typedef uint32_t hri_rtcmode2_clock_reg_t;
+typedef uint32_t hri_rtcmode2_evctrl_reg_t;
+typedef uint32_t hri_rtcmode2_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode2_timestamp_reg_t;
+typedef uint8_t  hri_rtc_dbgctrl_reg_t;
+typedef uint8_t  hri_rtc_freqcorr_reg_t;
+typedef uint8_t  hri_rtcalarm_mask_reg_t;
+typedef uint8_t  hri_rtcmode2_mask_reg_t;
+
+static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
+	tmp |= RTC_MODE2_ALARM_SECOND(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
+	tmp |= RTC_MODE2_ALARM_MINUTE(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
+	tmp |= RTC_MODE2_ALARM_HOUR(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
+	tmp |= RTC_MODE2_ALARM_DAY(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
+	tmp |= RTC_MODE2_ALARM_MONTH(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
+	tmp |= RTC_MODE2_ALARM_YEAR(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+}
+
+static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= ~RTC_MODE2_MASK_SEL_Msk;
+	tmp |= RTC_MODE2_MASK_SEL(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+}
+
+static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
+	tmp |= RTC_MODE2_ALARM_SECOND(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
+	tmp |= RTC_MODE2_ALARM_MINUTE(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
+	tmp |= RTC_MODE2_ALARM_HOUR(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
+	tmp |= RTC_MODE2_ALARM_DAY(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
+	tmp |= RTC_MODE2_ALARM_MONTH(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
+	tmp |= RTC_MODE2_ALARM_YEAR(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+}
+
+static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= ~RTC_MODE2_MASK_SEL_Msk;
+	tmp |= RTC_MODE2_MASK_SEL(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode0_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = mask;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode1_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = mask;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_ALARM1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_ALARM1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_ALARM1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_ALARM1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode2_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = mask;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
+static inline void hri_rtcmode0_set_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP1) >> RTC_MODE0_INTENSET_CMP1_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_CMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1;
+}
+
+static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode0_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTENSET.reg;
+}
+
+static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = data;
+	((Rtc *)hw)->MODE0.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = mask;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP2) >> RTC_MODE1_INTENSET_CMP2_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP3) >> RTC_MODE1_INTENSET_CMP3_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3;
+}
+
+static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode1_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.INTENSET.reg;
+}
+
+static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = data;
+	((Rtc *)hw)->MODE1.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = mask;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
+}
+
+static inline void hri_rtcmode2_set_INTEN_ALARM1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_ALARM1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM1) >> RTC_MODE2_INTENSET_ALARM1_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_ALARM1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_ALARM1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1;
+}
+
+static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode2_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.INTENSET.reg;
+}
+
+static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = data;
+	((Rtc *)hw)->MODE2.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = mask;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP1) >> RTC_MODE0_SYNCBUSY_COMP1_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP2) >> RTC_MODE0_SYNCBUSY_GP2_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP3) >> RTC_MODE0_SYNCBUSY_GP3_Pos;
+}
+
+static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode0_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.SYNCBUSY.reg;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP2) >> RTC_MODE1_SYNCBUSY_COMP2_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP3) >> RTC_MODE1_SYNCBUSY_COMP3_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP2) >> RTC_MODE1_SYNCBUSY_GP2_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP3) >> RTC_MODE1_SYNCBUSY_GP3_Pos;
+}
+
+static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode1_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.SYNCBUSY.reg;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM1) >> RTC_MODE2_SYNCBUSY_ALARM1_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_MASK1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK1) >> RTC_MODE2_SYNCBUSY_MASK1_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP2) >> RTC_MODE2_SYNCBUSY_GP2_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP3) >> RTC_MODE2_SYNCBUSY_GP3_Pos;
+}
+
+static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode2_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.SYNCBUSY.reg;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const            hw,
+                                                                               hri_rtcmode0_timestamp_reg_t mask)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode0_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE0.TIMESTAMP.reg;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const            hw,
+                                                                               hri_rtcmode1_timestamp_reg_t mask)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode1_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE1.TIMESTAMP.reg;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const            hw,
+                                                                                hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const            hw,
+                                                                                hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const            hw,
+                                                                              hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const            hw,
+                                                                             hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const            hw,
+                                                                               hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const            hw,
+                                                                              hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode2_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return ((Rtc *)hw)->MODE2.TIMESTAMP.reg;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_MATCHCLR;
+	tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC;
+	tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE0_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE0_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	return ((Rtc *)hw)->MODE0.CTRLA.reg;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC;
+	tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE1_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE1_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	return ((Rtc *)hw)->MODE1.CTRLA.reg;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_CLKREP;
+	tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_MATCHCLR;
+	tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC;
+	tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE2_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE2_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg = data;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	return ((Rtc *)hw)->MODE2.CTRLA.reg;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_GP2EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_GP2EN) >> RTC_MODE0_CTRLB_GP2EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_GP2EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_GP2EN;
+	tmp |= value << RTC_MODE0_CTRLB_GP2EN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE0_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE0_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.CTRLB.reg;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_GP2EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_GP2EN) >> RTC_MODE1_CTRLB_GP2EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_GP2EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_GP2EN;
+	tmp |= value << RTC_MODE1_CTRLB_GP2EN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE1_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE1_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.CTRLB.reg;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_GP2EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_GP2EN) >> RTC_MODE2_CTRLB_GP2EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_GP2EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_GP2EN;
+	tmp |= value << RTC_MODE2_CTRLB_GP2EN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE2_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE2_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.CTRLB.reg;
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_CMPEO0;
+	tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO1) >> RTC_MODE0_EVCTRL_CMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_CMPEO1;
+	tmp |= value << RTC_MODE0_EVCTRL_CMPEO1_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode0_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO0;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO1;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO2) >> RTC_MODE1_EVCTRL_CMPEO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO2;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO2_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO3) >> RTC_MODE1_EVCTRL_CMPEO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO3;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO3_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode1_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0;
+	tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_ALARMEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO1) >> RTC_MODE2_EVCTRL_ALARMEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_ALARMEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_ALARMEO1;
+	tmp |= value << RTC_MODE2_EVCTRL_ALARMEO1_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode2_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.EVCTRL.reg;
+}
+
+static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp &= ~RTC_DBGCTRL_DBGRUN;
+	tmp |= value << RTC_DBGCTRL_DBGRUN_Pos;
+	((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+}
+
+static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_SIGN;
+	tmp |= value << RTC_FREQCORR_SIGN_Pos;
+	((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_VALUE_Msk;
+	tmp |= RTC_FREQCORR_VALUE(data);
+	((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	return ((Rtc *)hw)->MODE0.FREQCORR.reg;
+}
+
+static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_rtcmode0_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp &= ~RTC_MODE0_COUNT_COUNT_Msk;
+	tmp |= RTC_MODE0_COUNT_COUNT(data);
+	((Rtc *)hw)->MODE0.COUNT.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE0.COUNT.reg;
+}
+
+static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_rtcmode1_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp &= ~RTC_MODE1_COUNT_COUNT_Msk;
+	tmp |= RTC_MODE1_COUNT_COUNT(data);
+	((Rtc *)hw)->MODE1.COUNT.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE1.COUNT.reg;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const        hw,
+                                                                        hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk;
+	tmp |= RTC_MODE2_CLOCK_SECOND(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const        hw,
+                                                                        hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk;
+	tmp |= RTC_MODE2_CLOCK_MINUTE(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const        hw,
+                                                                      hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk;
+	tmp |= RTC_MODE2_CLOCK_HOUR(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const        hw,
+                                                                     hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_DAY_Msk;
+	tmp |= RTC_MODE2_CLOCK_DAY(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const        hw,
+                                                                       hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk;
+	tmp |= RTC_MODE2_CLOCK_MONTH(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const        hw,
+                                                                      hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk;
+	tmp |= RTC_MODE2_CLOCK_YEAR(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg = data;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return ((Rtc *)hw)->MODE2.CLOCK.reg;
+}
+
+static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp &= ~RTC_MODE1_PER_PER_Msk;
+	tmp |= RTC_MODE1_PER_PER(data);
+	((Rtc *)hw)->MODE1.PER.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	return ((Rtc *)hw)->MODE1.PER.reg;
+}
+
+static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index,
+                                                                    hri_rtcmode0_comp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp &= ~RTC_MODE0_COMP_COMP_Msk;
+	tmp |= RTC_MODE0_COMP_COMP(data);
+	((Rtc *)hw)->MODE0.COMP[index].reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index,
+                                                                hri_rtcmode0_comp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	return ((Rtc *)hw)->MODE0.COMP[index].reg;
+}
+
+static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index,
+                                                                    hri_rtcmode1_comp_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp &= ~RTC_MODE1_COMP_COMP_Msk;
+	tmp |= RTC_MODE1_COMP_COMP(data);
+	((Rtc *)hw)->MODE1.COMP[index].reg = tmp;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg |= mask;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index,
+                                                                hri_rtcmode1_comp_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg = data;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg ^= mask;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	return ((Rtc *)hw)->MODE1.COMP[index].reg;
+}
+
+static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp &= ~RTC_GP_GP_Msk;
+	tmp |= RTC_GP_GP(data);
+	((Rtc *)hw)->MODE0.GP[index].reg = tmp;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg |= mask;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg = data;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg ^= mask;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	return ((Rtc *)hw)->MODE0.GP[index].reg;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL0;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL1;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL2;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL3;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL4;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC0;
+	tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC1;
+	tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC2;
+	tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC3;
+	tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC4;
+	tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN0ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN1ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN2ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN3ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN4ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID0;
+	tmp |= value << RTC_TAMPID_TAMPID0_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID1;
+	tmp |= value << RTC_TAMPID_TAMPID1_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID2;
+	tmp |= value << RTC_TAMPID_TAMPID2_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID3;
+	tmp |= value << RTC_TAMPID_TAMPID3_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID4;
+	tmp |= value << RTC_TAMPID_TAMPID4_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPEVT;
+	tmp |= value << RTC_TAMPID_TAMPEVT_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.TAMPID.reg;
+}
+
+static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp &= ~RTC_BKUP_BKUP_Msk;
+	tmp |= RTC_BKUP_BKUP(data);
+	((Rtc *)hw)->MODE0.BKUP[index].reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index)
+{
+	return ((Rtc *)hw)->MODE0.BKUP[index].reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b)
+#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a)
+#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b)
+#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a)
+#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b)
+#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b)
+#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b)
+#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b)
+#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b)
+#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a)
+#define hri_rtcmode2_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b)
+#define hri_rtcmode2_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c)
+#define hri_rtcmode2_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c)
+#define hri_rtcmode2_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c)
+#define hri_rtcmode2_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c)
+#define hri_rtcmode2_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c)
+#define hri_rtcmode2_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode2_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b)
+#define hri_rtcmode2_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b)
+#define hri_rtcmode2_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b)
+#define hri_rtcmode2_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b)
+#define hri_rtcmode2_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b)
+#define hri_rtcmode2_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a)
+#define hri_rtcmode2_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b)
+#define hri_rtcmode2_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c)
+#define hri_rtcmode2_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c)
+#define hri_rtcmode2_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c)
+#define hri_rtcmode2_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c)
+#define hri_rtcmode2_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c)
+#define hri_rtcmode2_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b)
+#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b)
+#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a)
+#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b)
+#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a)
+#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b)
+#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b)
+#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b)
+#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b)
+#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b)
+#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a)
+#define hri_rtcmode0_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b)
+#define hri_rtcmode0_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c)
+#define hri_rtcmode0_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c)
+#define hri_rtcmode0_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c)
+#define hri_rtcmode0_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c)
+#define hri_rtcmode0_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c)
+#define hri_rtcmode0_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode0_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b)
+#define hri_rtcmode0_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b)
+#define hri_rtcmode0_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b)
+#define hri_rtcmode0_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b)
+#define hri_rtcmode0_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b)
+#define hri_rtcmode0_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a)
+#define hri_rtcmode0_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b)
+#define hri_rtcmode0_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c)
+#define hri_rtcmode0_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c)
+#define hri_rtcmode0_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c)
+#define hri_rtcmode0_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c)
+#define hri_rtcmode0_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c)
+#define hri_rtcmode0_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b)
+#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b)
+#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a)
+#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b)
+#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a)
+#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b)
+#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b)
+#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b)
+#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b)
+#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b)
+#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a)
+#define hri_rtcmode1_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b)
+#define hri_rtcmode1_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c)
+#define hri_rtcmode1_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c)
+#define hri_rtcmode1_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c)
+#define hri_rtcmode1_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c)
+#define hri_rtcmode1_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c)
+#define hri_rtcmode1_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode1_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b)
+#define hri_rtcmode1_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b)
+#define hri_rtcmode1_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b)
+#define hri_rtcmode1_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b)
+#define hri_rtcmode1_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b)
+#define hri_rtcmode1_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a)
+#define hri_rtcmode1_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b)
+#define hri_rtcmode1_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c)
+#define hri_rtcmode1_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c)
+#define hri_rtcmode1_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c)
+#define hri_rtcmode1_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c)
+#define hri_rtcmode1_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c)
+#define hri_rtcmode1_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RTC_D51_H_INCLUDED */
+#endif /* _SAMD51_RTC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_sdhc_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_sdhc_d51.h
new file mode 100644
index 0000000..54f592c
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_sdhc_d51.h
@@ -0,0 +1,7477 @@
+/**
+ * \file
+ *
+ * \brief SAM SDHC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_SDHC_COMPONENT_
+#ifndef _HRI_SDHC_D51_H_INCLUDED_
+#define _HRI_SDHC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SDHC_CRITICAL_SECTIONS)
+#define SDHC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SDHC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SDHC_CRITICAL_SECTION_ENTER()
+#define SDHC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_sdhc_acesr_reg_t;
+typedef uint16_t hri_sdhc_bcr_reg_t;
+typedef uint16_t hri_sdhc_bsr_reg_t;
+typedef uint16_t hri_sdhc_ccr_reg_t;
+typedef uint16_t hri_sdhc_cr_reg_t;
+typedef uint16_t hri_sdhc_eisier_reg_t;
+typedef uint16_t hri_sdhc_eister_reg_t;
+typedef uint16_t hri_sdhc_eistr_reg_t;
+typedef uint16_t hri_sdhc_feraces_reg_t;
+typedef uint16_t hri_sdhc_fereis_reg_t;
+typedef uint16_t hri_sdhc_hc2r_reg_t;
+typedef uint16_t hri_sdhc_hcvr_reg_t;
+typedef uint16_t hri_sdhc_nisier_reg_t;
+typedef uint16_t hri_sdhc_nister_reg_t;
+typedef uint16_t hri_sdhc_nistr_reg_t;
+typedef uint16_t hri_sdhc_pvr_reg_t;
+typedef uint16_t hri_sdhc_sisr_reg_t;
+typedef uint16_t hri_sdhc_tmr_reg_t;
+typedef uint32_t hri_sdhc_acr_reg_t;
+typedef uint32_t hri_sdhc_arg1r_reg_t;
+typedef uint32_t hri_sdhc_asar_reg_t;
+typedef uint32_t hri_sdhc_bdpr_reg_t;
+typedef uint32_t hri_sdhc_ca0r_reg_t;
+typedef uint32_t hri_sdhc_ca1r_reg_t;
+typedef uint32_t hri_sdhc_cacr_reg_t;
+typedef uint32_t hri_sdhc_cc2r_reg_t;
+typedef uint32_t hri_sdhc_mccar_reg_t;
+typedef uint32_t hri_sdhc_psr_reg_t;
+typedef uint32_t hri_sdhc_rr_reg_t;
+typedef uint32_t hri_sdhc_ssar_reg_t;
+typedef uint8_t  hri_sdhc_aesr_reg_t;
+typedef uint8_t  hri_sdhc_bgcr_reg_t;
+typedef uint8_t  hri_sdhc_dbgr_reg_t;
+typedef uint8_t  hri_sdhc_hc1r_reg_t;
+typedef uint8_t  hri_sdhc_mc1r_reg_t;
+typedef uint8_t  hri_sdhc_mc2r_reg_t;
+typedef uint8_t  hri_sdhc_pcr_reg_t;
+typedef uint8_t  hri_sdhc_srr_reg_t;
+typedef uint8_t  hri_sdhc_tcr_reg_t;
+typedef uint8_t  hri_sdhc_wcr_reg_t;
+
+static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_CMDRESP_bf(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask)
+{
+	return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP(mask)) >> SDHC_RR_CMDRESP_Pos;
+}
+
+static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_CMDRESP_bf(const void *const hw, uint8_t index)
+{
+	return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP_Msk) >> SDHC_RR_CMDRESP_Pos;
+}
+
+static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_reg(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->RR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_reg(const void *const hw, uint8_t index)
+{
+	return ((Sdhc *)hw)->RR[index].reg;
+}
+
+static inline bool hri_sdhc_get_PSR_CMDINHC_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHC) >> SDHC_PSR_CMDINHC_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CMDINHD_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHD) >> SDHC_PSR_CMDINHD_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_DLACT_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DLACT) >> SDHC_PSR_DLACT_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_RTREQ_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTREQ) >> SDHC_PSR_RTREQ_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_WTACT_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WTACT) >> SDHC_PSR_WTACT_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_RTACT_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTACT) >> SDHC_PSR_RTACT_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_BUFWREN_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFWREN) >> SDHC_PSR_BUFWREN_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_BUFRDEN_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFRDEN) >> SDHC_PSR_BUFRDEN_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CARDINS_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDINS) >> SDHC_PSR_CARDINS_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CARDSS_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDSS) >> SDHC_PSR_CARDSS_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CARDDPL_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDDPL) >> SDHC_PSR_CARDDPL_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_WRPPL_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WRPPL) >> SDHC_PSR_WRPPL_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CMDLL_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDLL) >> SDHC_PSR_CMDLL_Pos;
+}
+
+static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_DATLL_bf(const void *const hw, hri_sdhc_psr_reg_t mask)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL(mask)) >> SDHC_PSR_DATLL_Pos;
+}
+
+static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_DATLL_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL_Msk) >> SDHC_PSR_DATLL_Pos;
+}
+
+static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_reg(const void *const hw, hri_sdhc_psr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->PSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->PSR.reg;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMD12NE_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMD12NE) >> SDHC_ACESR_ACMD12NE_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMDTEO_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDTEO) >> SDHC_ACESR_ACMDTEO_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMDCRC_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDCRC) >> SDHC_ACESR_ACMDCRC_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMDEND_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDEND) >> SDHC_ACESR_ACMDEND_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMDIDX_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDIDX) >> SDHC_ACESR_ACMDIDX_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_CMDNI_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_CMDNI) >> SDHC_ACESR_CMDNI_Pos;
+}
+
+static inline hri_sdhc_acesr_reg_t hri_sdhc_get_ACESR_reg(const void *const hw, hri_sdhc_acesr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->ACESR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_acesr_reg_t hri_sdhc_read_ACESR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->ACESR.reg;
+}
+
+static inline bool hri_sdhc_get_CA0R_TEOCLKU_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKU) >> SDHC_CA0R_TEOCLKU_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_ED8SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ED8SUP) >> SDHC_CA0R_ED8SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_ADMA2SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ADMA2SUP) >> SDHC_CA0R_ADMA2SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_HSSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_HSSUP) >> SDHC_CA0R_HSSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_SDMASUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SDMASUP) >> SDHC_CA0R_SDMASUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_SRSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SRSUP) >> SDHC_CA0R_SRSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_V33VSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V33VSUP) >> SDHC_CA0R_V33VSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_V30VSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V30VSUP) >> SDHC_CA0R_V30VSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_V18VSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V18VSUP) >> SDHC_CA0R_V18VSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_SB64SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SB64SUP) >> SDHC_CA0R_SB64SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_ASINTSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ASINTSUP) >> SDHC_CA0R_ASINTSUP_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_TEOCLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF(mask)) >> SDHC_CA0R_TEOCLKF_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_TEOCLKF_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF_Msk) >> SDHC_CA0R_TEOCLKF_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_BASECLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF(mask)) >> SDHC_CA0R_BASECLKF_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_BASECLKF_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF_Msk) >> SDHC_CA0R_BASECLKF_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_MAXBLKL_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL(mask)) >> SDHC_CA0R_MAXBLKL_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_MAXBLKL_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL_Msk) >> SDHC_CA0R_MAXBLKL_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_SLTYPE_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE(mask)) >> SDHC_CA0R_SLTYPE_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_SLTYPE_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE_Msk) >> SDHC_CA0R_SLTYPE_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_reg(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CA0R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CA0R.reg;
+}
+
+static inline bool hri_sdhc_get_CA1R_SDR50SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR50SUP) >> SDHC_CA1R_SDR50SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_SDR104SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR104SUP) >> SDHC_CA1R_SDR104SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_DDR50SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DDR50SUP) >> SDHC_CA1R_DDR50SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_DRVASUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVASUP) >> SDHC_CA1R_DRVASUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_DRVCSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVCSUP) >> SDHC_CA1R_DRVCSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_DRVDSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVDSUP) >> SDHC_CA1R_DRVDSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_TSDR50_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TSDR50) >> SDHC_CA1R_TSDR50_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_TCNTRT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT(mask)) >> SDHC_CA1R_TCNTRT_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_TCNTRT_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT_Msk) >> SDHC_CA1R_TCNTRT_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_CLKMULT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT(mask)) >> SDHC_CA1R_CLKMULT_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_CLKMULT_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT_Msk) >> SDHC_CA1R_CLKMULT_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_reg(const void *const hw, hri_sdhc_ca1r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CA1R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CA1R.reg;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR33V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V(mask)) >> SDHC_MCCAR_MAXCUR33V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR33V_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V_Msk) >> SDHC_MCCAR_MAXCUR33V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR30V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V(mask)) >> SDHC_MCCAR_MAXCUR30V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR30V_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V_Msk) >> SDHC_MCCAR_MAXCUR30V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR18V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V(mask)) >> SDHC_MCCAR_MAXCUR18V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR18V_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V_Msk) >> SDHC_MCCAR_MAXCUR18V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_reg(const void *const hw, hri_sdhc_mccar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->MCCAR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->MCCAR.reg;
+}
+
+static inline bool hri_sdhc_get_AESR_LMIS_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_LMIS) >> SDHC_AESR_LMIS_Pos;
+}
+
+static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_ERRST_bf(const void *const hw, hri_sdhc_aesr_reg_t mask)
+{
+	return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST(mask)) >> SDHC_AESR_ERRST_Pos;
+}
+
+static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_ERRST_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST_Msk) >> SDHC_AESR_ERRST_Pos;
+}
+
+static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_reg(const void *const hw, hri_sdhc_aesr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->AESR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->AESR.reg;
+}
+
+static inline bool hri_sdhc_get_SISR_INTSSL_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->SISR.reg & SDHC_SISR_INTSSL_Msk) >> SDHC_SISR_INTSSL_Pos;
+}
+
+static inline hri_sdhc_sisr_reg_t hri_sdhc_get_SISR_reg(const void *const hw, hri_sdhc_sisr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->SISR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_sisr_reg_t hri_sdhc_read_SISR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->SISR.reg;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_SVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask)
+{
+	return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER(mask)) >> SDHC_HCVR_SVER_Pos;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_SVER_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER_Msk) >> SDHC_HCVR_SVER_Pos;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_VVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask)
+{
+	return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER(mask)) >> SDHC_HCVR_VVER_Pos;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_VVER_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER_Msk) >> SDHC_HCVR_VVER_Pos;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_reg(const void *const hw, hri_sdhc_hcvr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HCVR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->HCVR.reg;
+}
+
+static inline void hri_sdhc_set_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_ADDR(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp = (tmp & SDHC_SSAR_ADDR(mask)) >> SDHC_SSAR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp &= ~SDHC_SSAR_ADDR_Msk;
+	tmp |= SDHC_SSAR_ADDR(data);
+	((Sdhc *)hw)->SSAR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_ADDR(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_ADDR(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp = (tmp & SDHC_SSAR_ADDR_Msk) >> SDHC_SSAR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_CMD23_ARG2(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp = (tmp & SDHC_SSAR_CMD23_ARG2(mask)) >> SDHC_SSAR_CMD23_ARG2_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp &= ~SDHC_SSAR_CMD23_ARG2_Msk;
+	tmp |= SDHC_SSAR_CMD23_ARG2(data);
+	((Sdhc *)hw)->SSAR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_CMD23_ARG2(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_CMD23_ARG2(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_ARG2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp = (tmp & SDHC_SSAR_CMD23_ARG2_Msk) >> SDHC_SSAR_CMD23_ARG2_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->SSAR.reg;
+}
+
+static inline void hri_sdhc_set_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BLOCKSIZE(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp = (tmp & SDHC_BSR_BLOCKSIZE(mask)) >> SDHC_BSR_BLOCKSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp &= ~SDHC_BSR_BLOCKSIZE_Msk;
+	tmp |= SDHC_BSR_BLOCKSIZE(data);
+	((Sdhc *)hw)->BSR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BLOCKSIZE(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BLOCKSIZE(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BLOCKSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp = (tmp & SDHC_BSR_BLOCKSIZE_Msk) >> SDHC_BSR_BLOCKSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BOUNDARY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp = (tmp & SDHC_BSR_BOUNDARY(mask)) >> SDHC_BSR_BOUNDARY_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp &= ~SDHC_BSR_BOUNDARY_Msk;
+	tmp |= SDHC_BSR_BOUNDARY(data);
+	((Sdhc *)hw)->BSR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BOUNDARY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BOUNDARY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BOUNDARY_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp = (tmp & SDHC_BSR_BOUNDARY_Msk) >> SDHC_BSR_BOUNDARY_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->BSR.reg;
+}
+
+static inline void hri_sdhc_set_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg |= SDHC_BCR_BCNT(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BCR.reg;
+	tmp = (tmp & SDHC_BCR_BCNT(mask)) >> SDHC_BCR_BCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BCR.reg;
+	tmp &= ~SDHC_BCR_BCNT_Msk;
+	tmp |= SDHC_BCR_BCNT(data);
+	((Sdhc *)hw)->BCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg &= ~SDHC_BCR_BCNT(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg ^= SDHC_BCR_BCNT(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_BCNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BCR.reg;
+	tmp = (tmp & SDHC_BCR_BCNT_Msk) >> SDHC_BCR_BCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->BCR.reg;
+}
+
+static inline void hri_sdhc_set_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg |= SDHC_ARG1R_ARG(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ARG1R.reg;
+	tmp = (tmp & SDHC_ARG1R_ARG(mask)) >> SDHC_ARG1R_ARG_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->ARG1R.reg;
+	tmp &= ~SDHC_ARG1R_ARG_Msk;
+	tmp |= SDHC_ARG1R_ARG(data);
+	((Sdhc *)hw)->ARG1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg &= ~SDHC_ARG1R_ARG(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg ^= SDHC_ARG1R_ARG(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_ARG_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ARG1R.reg;
+	tmp = (tmp & SDHC_ARG1R_ARG_Msk) >> SDHC_ARG1R_ARG_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ARG1R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->ARG1R.reg;
+}
+
+static inline void hri_sdhc_set_TMR_DMAEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DMAEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_TMR_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_DMAEN) >> SDHC_TMR_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_TMR_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_DMAEN;
+	tmp |= value << SDHC_TMR_DMAEN_Pos;
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_DMAEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DMAEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_DMAEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DMAEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_TMR_BCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_BCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_TMR_BCEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_BCEN) >> SDHC_TMR_BCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_TMR_BCEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_BCEN;
+	tmp |= value << SDHC_TMR_BCEN_Pos;
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_BCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_BCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_BCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_BCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_TMR_DTDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DTDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_TMR_DTDSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_DTDSEL) >> SDHC_TMR_DTDSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_TMR_DTDSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_DTDSEL;
+	tmp |= value << SDHC_TMR_DTDSEL_Pos;
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_DTDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DTDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_DTDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DTDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_TMR_MSBSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_MSBSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_TMR_MSBSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_MSBSEL) >> SDHC_TMR_MSBSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_TMR_MSBSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_MSBSEL;
+	tmp |= value << SDHC_TMR_MSBSEL_Pos;
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_MSBSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_MSBSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_MSBSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_MSBSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_ACMDEN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_ACMDEN(mask)) >> SDHC_TMR_ACMDEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_ACMDEN_Msk;
+	tmp |= SDHC_TMR_ACMDEN(data);
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_ACMDEN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_ACMDEN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_ACMDEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_ACMDEN_Msk) >> SDHC_TMR_ACMDEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->TMR.reg;
+}
+
+static inline void hri_sdhc_set_CR_CMDCCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDCCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CR_CMDCCEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDCCEN) >> SDHC_CR_CMDCCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CR_CMDCCEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_CMDCCEN;
+	tmp |= value << SDHC_CR_CMDCCEN_Pos;
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_CMDCCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDCCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_CMDCCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDCCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CR_CMDICEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDICEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CR_CMDICEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDICEN) >> SDHC_CR_CMDICEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CR_CMDICEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_CMDICEN;
+	tmp |= value << SDHC_CR_CMDICEN_Pos;
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_CMDICEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDICEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_CMDICEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDICEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CR_DPSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_DPSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CR_DPSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_DPSEL) >> SDHC_CR_DPSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CR_DPSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_DPSEL;
+	tmp |= value << SDHC_CR_DPSEL_Pos;
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_DPSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_DPSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_DPSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_DPSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_RESPTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_RESPTYP(mask)) >> SDHC_CR_RESPTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_RESPTYP_Msk;
+	tmp |= SDHC_CR_RESPTYP(data);
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_RESPTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_RESPTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_RESPTYP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_RESPTYP_Msk) >> SDHC_CR_RESPTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDTYP(mask)) >> SDHC_CR_CMDTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_CMDTYP_Msk;
+	tmp |= SDHC_CR_CMDTYP(data);
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDTYP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDTYP_Msk) >> SDHC_CR_CMDTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDIDX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDIDX(mask)) >> SDHC_CR_CMDIDX_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_CMDIDX_Msk;
+	tmp |= SDHC_CR_CMDIDX(data);
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDIDX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDIDX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDIDX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDIDX_Msk) >> SDHC_CR_CMDIDX_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CR_reg(const void *const hw, hri_sdhc_cr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CR.reg;
+}
+
+static inline void hri_sdhc_set_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg |= SDHC_BDPR_BUFDATA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->BDPR.reg;
+	tmp = (tmp & SDHC_BDPR_BUFDATA(mask)) >> SDHC_BDPR_BUFDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BDPR.reg;
+	tmp &= ~SDHC_BDPR_BUFDATA_Msk;
+	tmp |= SDHC_BDPR_BUFDATA(data);
+	((Sdhc *)hw)->BDPR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg &= ~SDHC_BDPR_BUFDATA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg ^= SDHC_BDPR_BUFDATA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_BUFDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->BDPR.reg;
+	tmp = (tmp & SDHC_BDPR_BUFDATA_Msk) >> SDHC_BDPR_BUFDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->BDPR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->BDPR.reg;
+}
+
+static inline void hri_sdhc_set_HC1R_LEDCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_LEDCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_LEDCTRL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_LEDCTRL) >> SDHC_HC1R_LEDCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_LEDCTRL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_LEDCTRL;
+	tmp |= value << SDHC_HC1R_LEDCTRL_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_LEDCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_LEDCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_LEDCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_LEDCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_DW_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DW;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_DW_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_DW) >> SDHC_HC1R_DW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_DW_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_DW;
+	tmp |= value << SDHC_HC1R_DW_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_DW_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DW;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_DW_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DW;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_HSEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_HSEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_HSEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_HSEN) >> SDHC_HC1R_HSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_HSEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_HSEN;
+	tmp |= value << SDHC_HC1R_HSEN_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_HSEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_HSEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_HSEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_HSEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_CARDDTL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDTL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_CARDDTL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_CARDDTL) >> SDHC_HC1R_CARDDTL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_CARDDTL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_CARDDTL;
+	tmp |= value << SDHC_HC1R_CARDDTL_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_CARDDTL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDTL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_CARDDTL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDTL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_CARDDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_CARDDSEL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_CARDDSEL) >> SDHC_HC1R_CARDDSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_CARDDSEL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_CARDDSEL;
+	tmp |= value << SDHC_HC1R_CARDDSEL_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_CARDDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_CARDDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DMASEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_DMASEL(mask)) >> SDHC_HC1R_DMASEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_DMASEL_Msk;
+	tmp |= SDHC_HC1R_DMASEL(data);
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DMASEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DMASEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_DMASEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_DMASEL_Msk) >> SDHC_HC1R_DMASEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->HC1R.reg;
+}
+
+static inline void hri_sdhc_set_PCR_SDBPWR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBPWR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_PCR_SDBPWR_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp = (tmp & SDHC_PCR_SDBPWR) >> SDHC_PCR_SDBPWR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_PCR_SDBPWR_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp &= ~SDHC_PCR_SDBPWR;
+	tmp |= value << SDHC_PCR_SDBPWR_Pos;
+	((Sdhc *)hw)->PCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PCR_SDBPWR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBPWR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PCR_SDBPWR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBPWR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp = (tmp & SDHC_PCR_SDBVSEL(mask)) >> SDHC_PCR_SDBVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t data)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp &= ~SDHC_PCR_SDBVSEL_Msk;
+	tmp |= SDHC_PCR_SDBVSEL(data);
+	((Sdhc *)hw)->PCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_SDBVSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp = (tmp & SDHC_PCR_SDBVSEL_Msk) >> SDHC_PCR_SDBVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->PCR.reg;
+}
+
+static inline void hri_sdhc_set_BGCR_STPBGR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_STPBGR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_BGCR_STPBGR_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp = (tmp & SDHC_BGCR_STPBGR) >> SDHC_BGCR_STPBGR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_STPBGR_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= ~SDHC_BGCR_STPBGR;
+	tmp |= value << SDHC_BGCR_STPBGR_Pos;
+	((Sdhc *)hw)->BGCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_STPBGR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_STPBGR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_STPBGR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_STPBGR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_BGCR_CONTR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_CONTR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_BGCR_CONTR_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp = (tmp & SDHC_BGCR_CONTR) >> SDHC_BGCR_CONTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_CONTR_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= ~SDHC_BGCR_CONTR;
+	tmp |= value << SDHC_BGCR_CONTR_Pos;
+	((Sdhc *)hw)->BGCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_CONTR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_CONTR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_CONTR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_CONTR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_BGCR_RWCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_RWCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_BGCR_RWCTRL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp = (tmp & SDHC_BGCR_RWCTRL) >> SDHC_BGCR_RWCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_RWCTRL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= ~SDHC_BGCR_RWCTRL;
+	tmp |= value << SDHC_BGCR_RWCTRL_Pos;
+	((Sdhc *)hw)->BGCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_RWCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_RWCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_RWCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_RWCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_BGCR_INTBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_INTBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_BGCR_INTBG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp = (tmp & SDHC_BGCR_INTBG) >> SDHC_BGCR_INTBG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_INTBG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= ~SDHC_BGCR_INTBG;
+	tmp |= value << SDHC_BGCR_INTBG_Pos;
+	((Sdhc *)hw)->BGCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_INTBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_INTBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_INTBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_INTBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->BGCR.reg;
+}
+
+static inline void hri_sdhc_set_WCR_WKENCINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_WCR_WKENCINT_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp = (tmp & SDHC_WCR_WKENCINT) >> SDHC_WCR_WKENCINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_WCR_WKENCINT_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp &= ~SDHC_WCR_WKENCINT;
+	tmp |= value << SDHC_WCR_WKENCINT_Pos;
+	((Sdhc *)hw)->WCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_WCR_WKENCINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_WCR_WKENCINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_WCR_WKENCINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_WCR_WKENCINS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp = (tmp & SDHC_WCR_WKENCINS) >> SDHC_WCR_WKENCINS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_WCR_WKENCINS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp &= ~SDHC_WCR_WKENCINS;
+	tmp |= value << SDHC_WCR_WKENCINS_Pos;
+	((Sdhc *)hw)->WCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_WCR_WKENCINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_WCR_WKENCINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_WCR_WKENCREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_WCR_WKENCREM_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp = (tmp & SDHC_WCR_WKENCREM) >> SDHC_WCR_WKENCREM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_WCR_WKENCREM_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp &= ~SDHC_WCR_WKENCREM;
+	tmp |= value << SDHC_WCR_WKENCREM_Pos;
+	((Sdhc *)hw)->WCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_WCR_WKENCREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_WCR_WKENCREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_wcr_reg_t hri_sdhc_get_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_wcr_reg_t hri_sdhc_read_WCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->WCR.reg;
+}
+
+static inline void hri_sdhc_set_CCR_INTCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CCR_INTCLKEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_INTCLKEN) >> SDHC_CCR_INTCLKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CCR_INTCLKEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_INTCLKEN;
+	tmp |= value << SDHC_CCR_INTCLKEN_Pos;
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_INTCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_INTCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CCR_INTCLKS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CCR_INTCLKS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_INTCLKS) >> SDHC_CCR_INTCLKS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CCR_INTCLKS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_INTCLKS;
+	tmp |= value << SDHC_CCR_INTCLKS_Pos;
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_INTCLKS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_INTCLKS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CCR_SDCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CCR_SDCLKEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_SDCLKEN) >> SDHC_CCR_SDCLKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CCR_SDCLKEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_SDCLKEN;
+	tmp |= value << SDHC_CCR_SDCLKEN_Pos;
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_SDCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_SDCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CCR_CLKGSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CCR_CLKGSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_CLKGSEL) >> SDHC_CCR_CLKGSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CCR_CLKGSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_CLKGSEL;
+	tmp |= value << SDHC_CCR_CLKGSEL_Pos;
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_CLKGSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_CLKGSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_USDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_USDCLKFSEL(mask)) >> SDHC_CCR_USDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_USDCLKFSEL_Msk;
+	tmp |= SDHC_CCR_USDCLKFSEL(data);
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_USDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_USDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_USDCLKFSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_USDCLKFSEL_Msk) >> SDHC_CCR_USDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_SDCLKFSEL(mask)) >> SDHC_CCR_SDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_SDCLKFSEL_Msk;
+	tmp |= SDHC_CCR_SDCLKFSEL(data);
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_SDCLKFSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_SDCLKFSEL_Msk) >> SDHC_CCR_SDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CCR.reg;
+}
+
+static inline void hri_sdhc_set_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg |= SDHC_TCR_DTCVAL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->TCR.reg;
+	tmp = (tmp & SDHC_TCR_DTCVAL(mask)) >> SDHC_TCR_DTCVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t data)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TCR.reg;
+	tmp &= ~SDHC_TCR_DTCVAL_Msk;
+	tmp |= SDHC_TCR_DTCVAL(data);
+	((Sdhc *)hw)->TCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg &= ~SDHC_TCR_DTCVAL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg ^= SDHC_TCR_DTCVAL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_DTCVAL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->TCR.reg;
+	tmp = (tmp & SDHC_TCR_DTCVAL_Msk) >> SDHC_TCR_DTCVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->TCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->TCR.reg;
+}
+
+static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp = (tmp & SDHC_SRR_SWRSTALL) >> SDHC_SRR_SWRSTALL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_SRR_SWRSTALL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp &= ~SDHC_SRR_SWRSTALL;
+	tmp |= value << SDHC_SRR_SWRSTALL_Pos;
+	((Sdhc *)hw)->SRR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SRR_SWRSTALL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTALL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SRR_SWRSTALL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTALL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_SRR_SWRSTCMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTCMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_SRR_SWRSTCMD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp = (tmp & SDHC_SRR_SWRSTCMD) >> SDHC_SRR_SWRSTCMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_SRR_SWRSTCMD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp &= ~SDHC_SRR_SWRSTCMD;
+	tmp |= value << SDHC_SRR_SWRSTCMD_Pos;
+	((Sdhc *)hw)->SRR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SRR_SWRSTCMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTCMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SRR_SWRSTCMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTCMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_SRR_SWRSTDAT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTDAT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_SRR_SWRSTDAT_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp = (tmp & SDHC_SRR_SWRSTDAT) >> SDHC_SRR_SWRSTDAT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_SRR_SWRSTDAT_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp &= ~SDHC_SRR_SWRSTDAT;
+	tmp |= value << SDHC_SRR_SWRSTDAT_Pos;
+	((Sdhc *)hw)->SRR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SRR_SWRSTDAT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTDAT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SRR_SWRSTDAT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTDAT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_srr_reg_t hri_sdhc_get_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_srr_reg_t hri_sdhc_read_SRR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->SRR.reg;
+}
+
+static inline void hri_sdhc_set_NISTR_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_CMDC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_CMDC) >> SDHC_NISTR_CMDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_CMDC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_CMDC;
+	tmp |= value << SDHC_NISTR_CMDC_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_TRFC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_TRFC) >> SDHC_NISTR_TRFC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_TRFC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_TRFC;
+	tmp |= value << SDHC_NISTR_TRFC_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_BLKGE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_BLKGE) >> SDHC_NISTR_BLKGE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_BLKGE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_BLKGE;
+	tmp |= value << SDHC_NISTR_BLKGE_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_DMAINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_DMAINT) >> SDHC_NISTR_DMAINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_DMAINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_DMAINT;
+	tmp |= value << SDHC_NISTR_DMAINT_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_BWRRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_BWRRDY) >> SDHC_NISTR_BWRRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_BWRRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_BWRRDY;
+	tmp |= value << SDHC_NISTR_BWRRDY_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_BRDRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_BRDRDY) >> SDHC_NISTR_BRDRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_BRDRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_BRDRDY;
+	tmp |= value << SDHC_NISTR_BRDRDY_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_CINS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_CINS) >> SDHC_NISTR_CINS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_CINS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_CINS;
+	tmp |= value << SDHC_NISTR_CINS_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_CREM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_CREM) >> SDHC_NISTR_CREM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_CREM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_CREM;
+	tmp |= value << SDHC_NISTR_CREM_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_CINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_CINT) >> SDHC_NISTR_CINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_CINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_CINT;
+	tmp |= value << SDHC_NISTR_CINT_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_EMMC_BOOTAR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_EMMC_BOOTAR) >> SDHC_NISTR_EMMC_BOOTAR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_EMMC_BOOTAR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_EMMC_BOOTAR;
+	tmp |= value << SDHC_NISTR_EMMC_BOOTAR_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_ERRINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_ERRINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_ERRINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_ERRINT) >> SDHC_NISTR_ERRINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_ERRINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_ERRINT;
+	tmp |= value << SDHC_NISTR_ERRINT_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_ERRINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_ERRINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_ERRINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_ERRINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->NISTR.reg;
+}
+
+static inline void hri_sdhc_set_EISTR_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CMDTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CMDTEO) >> SDHC_EISTR_CMDTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CMDTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CMDTEO;
+	tmp |= value << SDHC_EISTR_CMDTEO_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CMDCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CMDCRC) >> SDHC_EISTR_CMDCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CMDCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CMDCRC;
+	tmp |= value << SDHC_EISTR_CMDCRC_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CMDEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CMDEND) >> SDHC_EISTR_CMDEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CMDEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CMDEND;
+	tmp |= value << SDHC_EISTR_CMDEND_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CMDIDX_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CMDIDX) >> SDHC_EISTR_CMDIDX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CMDIDX_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CMDIDX;
+	tmp |= value << SDHC_EISTR_CMDIDX_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_DATTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_DATTEO) >> SDHC_EISTR_DATTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_DATTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_DATTEO;
+	tmp |= value << SDHC_EISTR_DATTEO_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_DATCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_DATCRC) >> SDHC_EISTR_DATCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_DATCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_DATCRC;
+	tmp |= value << SDHC_EISTR_DATCRC_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_DATEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_DATEND) >> SDHC_EISTR_DATEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_DATEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_DATEND;
+	tmp |= value << SDHC_EISTR_DATEND_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CURLIM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CURLIM) >> SDHC_EISTR_CURLIM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CURLIM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CURLIM;
+	tmp |= value << SDHC_EISTR_CURLIM_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_ACMD_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_ACMD) >> SDHC_EISTR_ACMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_ACMD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_ACMD;
+	tmp |= value << SDHC_EISTR_ACMD_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_ADMA_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_ADMA) >> SDHC_EISTR_ADMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_ADMA_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_ADMA;
+	tmp |= value << SDHC_EISTR_ADMA_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_EMMC_BOOTAE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_EMMC_BOOTAE) >> SDHC_EISTR_EMMC_BOOTAE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_EMMC_BOOTAE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_EMMC_BOOTAE;
+	tmp |= value << SDHC_EISTR_EMMC_BOOTAE_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->EISTR.reg;
+}
+
+static inline void hri_sdhc_set_NISTER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_CMDC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_CMDC) >> SDHC_NISTER_CMDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_CMDC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_CMDC;
+	tmp |= value << SDHC_NISTER_CMDC_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_TRFC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_TRFC) >> SDHC_NISTER_TRFC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_TRFC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_TRFC;
+	tmp |= value << SDHC_NISTER_TRFC_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_BLKGE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_BLKGE) >> SDHC_NISTER_BLKGE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_BLKGE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_BLKGE;
+	tmp |= value << SDHC_NISTER_BLKGE_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_DMAINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_DMAINT) >> SDHC_NISTER_DMAINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_DMAINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_DMAINT;
+	tmp |= value << SDHC_NISTER_DMAINT_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_BWRRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_BWRRDY) >> SDHC_NISTER_BWRRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_BWRRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_BWRRDY;
+	tmp |= value << SDHC_NISTER_BWRRDY_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_BRDRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_BRDRDY) >> SDHC_NISTER_BRDRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_BRDRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_BRDRDY;
+	tmp |= value << SDHC_NISTER_BRDRDY_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_CINS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_CINS) >> SDHC_NISTER_CINS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_CINS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_CINS;
+	tmp |= value << SDHC_NISTER_CINS_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_CREM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_CREM) >> SDHC_NISTER_CREM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_CREM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_CREM;
+	tmp |= value << SDHC_NISTER_CREM_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_CINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_CINT) >> SDHC_NISTER_CINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_CINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_CINT;
+	tmp |= value << SDHC_NISTER_CINT_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_EMMC_BOOTAR) >> SDHC_NISTER_EMMC_BOOTAR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_EMMC_BOOTAR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_EMMC_BOOTAR;
+	tmp |= value << SDHC_NISTER_EMMC_BOOTAR_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->NISTER.reg;
+}
+
+static inline void hri_sdhc_set_EISTER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CMDTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CMDTEO) >> SDHC_EISTER_CMDTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CMDTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CMDTEO;
+	tmp |= value << SDHC_EISTER_CMDTEO_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CMDCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CMDCRC) >> SDHC_EISTER_CMDCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CMDCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CMDCRC;
+	tmp |= value << SDHC_EISTER_CMDCRC_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CMDEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CMDEND) >> SDHC_EISTER_CMDEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CMDEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CMDEND;
+	tmp |= value << SDHC_EISTER_CMDEND_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CMDIDX_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CMDIDX) >> SDHC_EISTER_CMDIDX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CMDIDX_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CMDIDX;
+	tmp |= value << SDHC_EISTER_CMDIDX_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_DATTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_DATTEO) >> SDHC_EISTER_DATTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_DATTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_DATTEO;
+	tmp |= value << SDHC_EISTER_DATTEO_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_DATCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_DATCRC) >> SDHC_EISTER_DATCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_DATCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_DATCRC;
+	tmp |= value << SDHC_EISTER_DATCRC_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_DATEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_DATEND) >> SDHC_EISTER_DATEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_DATEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_DATEND;
+	tmp |= value << SDHC_EISTER_DATEND_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CURLIM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CURLIM) >> SDHC_EISTER_CURLIM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CURLIM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CURLIM;
+	tmp |= value << SDHC_EISTER_CURLIM_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_ACMD_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_ACMD) >> SDHC_EISTER_ACMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_ACMD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_ACMD;
+	tmp |= value << SDHC_EISTER_ACMD_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_ADMA_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_ADMA) >> SDHC_EISTER_ADMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_ADMA_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_ADMA;
+	tmp |= value << SDHC_EISTER_ADMA_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_EMMC_BOOTAE) >> SDHC_EISTER_EMMC_BOOTAE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_EMMC_BOOTAE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_EMMC_BOOTAE;
+	tmp |= value << SDHC_EISTER_EMMC_BOOTAE_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->EISTER.reg;
+}
+
+static inline void hri_sdhc_set_NISIER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_CMDC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_CMDC) >> SDHC_NISIER_CMDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_CMDC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_CMDC;
+	tmp |= value << SDHC_NISIER_CMDC_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_TRFC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_TRFC) >> SDHC_NISIER_TRFC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_TRFC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_TRFC;
+	tmp |= value << SDHC_NISIER_TRFC_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_BLKGE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_BLKGE) >> SDHC_NISIER_BLKGE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_BLKGE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_BLKGE;
+	tmp |= value << SDHC_NISIER_BLKGE_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_DMAINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_DMAINT) >> SDHC_NISIER_DMAINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_DMAINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_DMAINT;
+	tmp |= value << SDHC_NISIER_DMAINT_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_BWRRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_BWRRDY) >> SDHC_NISIER_BWRRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_BWRRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_BWRRDY;
+	tmp |= value << SDHC_NISIER_BWRRDY_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_BRDRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_BRDRDY) >> SDHC_NISIER_BRDRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_BRDRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_BRDRDY;
+	tmp |= value << SDHC_NISIER_BRDRDY_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_CINS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_CINS) >> SDHC_NISIER_CINS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_CINS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_CINS;
+	tmp |= value << SDHC_NISIER_CINS_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_CREM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_CREM) >> SDHC_NISIER_CREM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_CREM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_CREM;
+	tmp |= value << SDHC_NISIER_CREM_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_CINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_CINT) >> SDHC_NISIER_CINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_CINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_CINT;
+	tmp |= value << SDHC_NISIER_CINT_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_EMMC_BOOTAR) >> SDHC_NISIER_EMMC_BOOTAR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_EMMC_BOOTAR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_EMMC_BOOTAR;
+	tmp |= value << SDHC_NISIER_EMMC_BOOTAR_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->NISIER.reg;
+}
+
+static inline void hri_sdhc_set_EISIER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CMDTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CMDTEO) >> SDHC_EISIER_CMDTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CMDTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CMDTEO;
+	tmp |= value << SDHC_EISIER_CMDTEO_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CMDCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CMDCRC) >> SDHC_EISIER_CMDCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CMDCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CMDCRC;
+	tmp |= value << SDHC_EISIER_CMDCRC_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CMDEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CMDEND) >> SDHC_EISIER_CMDEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CMDEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CMDEND;
+	tmp |= value << SDHC_EISIER_CMDEND_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CMDIDX_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CMDIDX) >> SDHC_EISIER_CMDIDX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CMDIDX_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CMDIDX;
+	tmp |= value << SDHC_EISIER_CMDIDX_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_DATTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_DATTEO) >> SDHC_EISIER_DATTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_DATTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_DATTEO;
+	tmp |= value << SDHC_EISIER_DATTEO_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_DATCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_DATCRC) >> SDHC_EISIER_DATCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_DATCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_DATCRC;
+	tmp |= value << SDHC_EISIER_DATCRC_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_DATEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_DATEND) >> SDHC_EISIER_DATEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_DATEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_DATEND;
+	tmp |= value << SDHC_EISIER_DATEND_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CURLIM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CURLIM) >> SDHC_EISIER_CURLIM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CURLIM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CURLIM;
+	tmp |= value << SDHC_EISIER_CURLIM_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_ACMD_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_ACMD) >> SDHC_EISIER_ACMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_ACMD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_ACMD;
+	tmp |= value << SDHC_EISIER_ACMD_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_ADMA_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_ADMA) >> SDHC_EISIER_ADMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_ADMA_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_ADMA;
+	tmp |= value << SDHC_EISIER_ADMA_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_EMMC_BOOTAE) >> SDHC_EISIER_EMMC_BOOTAE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_EMMC_BOOTAE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_EMMC_BOOTAE;
+	tmp |= value << SDHC_EISIER_EMMC_BOOTAE_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->EISIER.reg;
+}
+
+static inline void hri_sdhc_set_HC2R_VS18EN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_VS18EN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_VS18EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_VS18EN) >> SDHC_HC2R_VS18EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_VS18EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_VS18EN;
+	tmp |= value << SDHC_HC2R_VS18EN_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_VS18EN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_VS18EN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_VS18EN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_VS18EN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_EXTUN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EXTUN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_EXTUN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_EXTUN) >> SDHC_HC2R_EXTUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_EXTUN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_EXTUN;
+	tmp |= value << SDHC_HC2R_EXTUN_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_EXTUN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EXTUN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_EXTUN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EXTUN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_SLCKSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_SLCKSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_SLCKSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_SLCKSEL) >> SDHC_HC2R_SLCKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_SLCKSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_SLCKSEL;
+	tmp |= value << SDHC_HC2R_SLCKSEL_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_SLCKSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_SLCKSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_SLCKSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_SLCKSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_ASINTEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_ASINTEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_ASINTEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_ASINTEN) >> SDHC_HC2R_ASINTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_ASINTEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_ASINTEN;
+	tmp |= value << SDHC_HC2R_ASINTEN_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_ASINTEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_ASINTEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_ASINTEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_ASINTEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_PVALEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_PVALEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_PVALEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_PVALEN) >> SDHC_HC2R_PVALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_PVALEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_PVALEN;
+	tmp |= value << SDHC_HC2R_PVALEN_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_PVALEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_PVALEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_PVALEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_PVALEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_UHSMS(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_UHSMS(mask)) >> SDHC_HC2R_UHSMS_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_UHSMS_Msk;
+	tmp |= SDHC_HC2R_UHSMS(data);
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_UHSMS(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_UHSMS(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_UHSMS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_UHSMS_Msk) >> SDHC_HC2R_UHSMS_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_HS200EN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_EMMC_HS200EN(mask)) >> SDHC_HC2R_EMMC_HS200EN_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_EMMC_HS200EN_Msk;
+	tmp |= SDHC_HC2R_EMMC_HS200EN(data);
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_HS200EN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_HS200EN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_HS200EN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_EMMC_HS200EN_Msk) >> SDHC_HC2R_EMMC_HS200EN_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_DRVSEL(mask)) >> SDHC_HC2R_DRVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_DRVSEL_Msk;
+	tmp |= SDHC_HC2R_DRVSEL(data);
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_DRVSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_DRVSEL_Msk) >> SDHC_HC2R_DRVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->HC2R.reg;
+}
+
+static inline void hri_sdhc_set_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg |= SDHC_ASAR_ADMASA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_ADMASA_bf(const void *const hw, uint8_t index,
+                                                              hri_sdhc_asar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ASAR[index].reg;
+	tmp = (tmp & SDHC_ASAR_ADMASA(mask)) >> SDHC_ASAR_ADMASA_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->ASAR[index].reg;
+	tmp &= ~SDHC_ASAR_ADMASA_Msk;
+	tmp |= SDHC_ASAR_ADMASA(data);
+	((Sdhc *)hw)->ASAR[index].reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg &= ~SDHC_ASAR_ADMASA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg ^= SDHC_ASAR_ADMASA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_ADMASA_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ASAR[index].reg;
+	tmp = (tmp & SDHC_ASAR_ADMASA_Msk) >> SDHC_ASAR_ADMASA_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ASAR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_reg(const void *const hw, uint8_t index)
+{
+	return ((Sdhc *)hw)->ASAR[index].reg;
+}
+
+static inline void hri_sdhc_set_PVR_CLKGSEL_bit(const void *const hw, uint8_t index)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_PVR_CLKGSEL_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_CLKGSEL) >> SDHC_PVR_CLKGSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_PVR_CLKGSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp &= ~SDHC_PVR_CLKGSEL;
+	tmp |= value << SDHC_PVR_CLKGSEL_Pos;
+	((Sdhc *)hw)->PVR[index].reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PVR_CLKGSEL_bit(const void *const hw, uint8_t index)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PVR_CLKGSEL_bit(const void *const hw, uint8_t index)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index,
+                                                               hri_sdhc_pvr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_SDCLKFSEL(mask)) >> SDHC_PVR_SDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp &= ~SDHC_PVR_SDCLKFSEL_Msk;
+	tmp |= SDHC_PVR_SDCLKFSEL(data);
+	((Sdhc *)hw)->PVR[index].reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_SDCLKFSEL_Msk) >> SDHC_PVR_SDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_DRVSEL_bf(const void *const hw, uint8_t index,
+                                                            hri_sdhc_pvr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_DRVSEL(mask)) >> SDHC_PVR_DRVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp &= ~SDHC_PVR_DRVSEL_Msk;
+	tmp |= SDHC_PVR_DRVSEL(data);
+	((Sdhc *)hw)->PVR[index].reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_DRVSEL_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_DRVSEL_Msk) >> SDHC_PVR_DRVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_reg(const void *const hw, uint8_t index)
+{
+	return ((Sdhc *)hw)->PVR[index].reg;
+}
+
+static inline void hri_sdhc_set_MC1R_DDR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_DDR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_DDR_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_DDR) >> SDHC_MC1R_DDR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_DDR_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_DDR;
+	tmp |= value << SDHC_MC1R_DDR_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_DDR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_DDR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_DDR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_DDR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_OPD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_OPD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_OPD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_OPD) >> SDHC_MC1R_OPD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_OPD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_OPD;
+	tmp |= value << SDHC_MC1R_OPD_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_OPD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_OPD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_OPD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_OPD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_BOOTA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_BOOTA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_BOOTA_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_BOOTA) >> SDHC_MC1R_BOOTA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_BOOTA_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_BOOTA;
+	tmp |= value << SDHC_MC1R_BOOTA_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_BOOTA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_BOOTA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_BOOTA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_BOOTA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_RSTN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_RSTN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_RSTN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_RSTN) >> SDHC_MC1R_RSTN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_RSTN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_RSTN;
+	tmp |= value << SDHC_MC1R_RSTN_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_RSTN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_RSTN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_RSTN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_RSTN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_FCD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_FCD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_FCD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_FCD) >> SDHC_MC1R_FCD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_FCD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_FCD;
+	tmp |= value << SDHC_MC1R_FCD_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_FCD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_FCD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_FCD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_FCD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_CMDTYP(mask)) >> SDHC_MC1R_CMDTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t data)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_CMDTYP_Msk;
+	tmp |= SDHC_MC1R_CMDTYP(data);
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_CMDTYP_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_CMDTYP_Msk) >> SDHC_MC1R_CMDTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->MC1R.reg;
+}
+
+static inline void hri_sdhc_set_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg |= SDHC_ACR_BMAX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ACR.reg;
+	tmp = (tmp & SDHC_ACR_BMAX(mask)) >> SDHC_ACR_BMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->ACR.reg;
+	tmp &= ~SDHC_ACR_BMAX_Msk;
+	tmp |= SDHC_ACR_BMAX(data);
+	((Sdhc *)hw)->ACR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg &= ~SDHC_ACR_BMAX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg ^= SDHC_ACR_BMAX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_BMAX_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ACR.reg;
+	tmp = (tmp & SDHC_ACR_BMAX_Msk) >> SDHC_ACR_BMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ACR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->ACR.reg;
+}
+
+static inline void hri_sdhc_set_CC2R_FSDCLKD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg |= SDHC_CC2R_FSDCLKD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CC2R_FSDCLKD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CC2R.reg;
+	tmp = (tmp & SDHC_CC2R_FSDCLKD) >> SDHC_CC2R_FSDCLKD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CC2R_FSDCLKD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CC2R.reg;
+	tmp &= ~SDHC_CC2R_FSDCLKD;
+	tmp |= value << SDHC_CC2R_FSDCLKD_Pos;
+	((Sdhc *)hw)->CC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CC2R_FSDCLKD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg &= ~SDHC_CC2R_FSDCLKD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CC2R_FSDCLKD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg ^= SDHC_CC2R_FSDCLKD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cc2r_reg_t hri_sdhc_get_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CC2R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cc2r_reg_t hri_sdhc_read_CC2R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CC2R.reg;
+}
+
+static inline void hri_sdhc_set_CACR_CAPWREN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg |= SDHC_CACR_CAPWREN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CACR_CAPWREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp = (tmp & SDHC_CACR_CAPWREN) >> SDHC_CACR_CAPWREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CACR_CAPWREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp &= ~SDHC_CACR_CAPWREN;
+	tmp |= value << SDHC_CACR_CAPWREN_Pos;
+	((Sdhc *)hw)->CACR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CACR_CAPWREN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_CAPWREN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CACR_CAPWREN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_CAPWREN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg |= SDHC_CACR_KEY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp = (tmp & SDHC_CACR_KEY(mask)) >> SDHC_CACR_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp &= ~SDHC_CACR_KEY_Msk;
+	tmp |= SDHC_CACR_KEY(data);
+	((Sdhc *)hw)->CACR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_KEY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_KEY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_KEY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp = (tmp & SDHC_CACR_KEY_Msk) >> SDHC_CACR_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CACR.reg;
+}
+
+static inline void hri_sdhc_set_DBGR_NIDBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg |= SDHC_DBGR_NIDBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_DBGR_NIDBG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->DBGR.reg;
+	tmp = (tmp & SDHC_DBGR_NIDBG) >> SDHC_DBGR_NIDBG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_DBGR_NIDBG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->DBGR.reg;
+	tmp &= ~SDHC_DBGR_NIDBG;
+	tmp |= value << SDHC_DBGR_NIDBG_Pos;
+	((Sdhc *)hw)->DBGR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_DBGR_NIDBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg &= ~SDHC_DBGR_NIDBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_DBGR_NIDBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg ^= SDHC_DBGR_NIDBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_dbgr_reg_t hri_sdhc_get_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->DBGR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_dbgr_reg_t hri_sdhc_read_DBGR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->DBGR.reg;
+}
+
+static inline void hri_sdhc_write_FERACES_reg(const void *const hw, hri_sdhc_feraces_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->FERACES.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_write_FEREIS_reg(const void *const hw, hri_sdhc_fereis_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->FEREIS.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_write_MC2R_reg(const void *const hw, hri_sdhc_mc2r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC2R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_sdhc_set_SSAR_CMD23_reg(a, b) hri_sdhc_set_SSAR_reg(a, b)
+#define hri_sdhc_get_SSAR_CMD23_reg(a, b) hri_sdhc_get_SSAR_reg(a, b)
+#define hri_sdhc_write_SSAR_CMD23_reg(a, b) hri_sdhc_write_SSAR_reg(a, b)
+#define hri_sdhc_clear_SSAR_CMD23_reg(a, b) hri_sdhc_clear_SSAR_reg(a, b)
+#define hri_sdhc_toggle_SSAR_CMD23_reg(a, b) hri_sdhc_toggle_SSAR_reg(a, b)
+#define hri_sdhc_read_SSAR_CMD23_reg(a) hri_sdhc_read_SSAR_reg(a)
+#define hri_sdhc_set_HC1R_EMMC_DW_bit(a) hri_sdhc_set_HC1R_DW_bit(a)
+#define hri_sdhc_get_HC1R_EMMC_DW_bit(a) hri_sdhc_get_HC1R_DW_bit(a)
+#define hri_sdhc_write_HC1R_EMMC_DW_bit(a, b) hri_sdhc_write_HC1R_DW_bit(a, b)
+#define hri_sdhc_clear_HC1R_EMMC_DW_bit(a) hri_sdhc_clear_HC1R_DW_bit(a)
+#define hri_sdhc_toggle_HC1R_EMMC_DW_bit(a) hri_sdhc_toggle_HC1R_DW_bit(a)
+#define hri_sdhc_set_HC1R_EMMC_HSEN_bit(a) hri_sdhc_set_HC1R_HSEN_bit(a)
+#define hri_sdhc_get_HC1R_EMMC_HSEN_bit(a) hri_sdhc_get_HC1R_HSEN_bit(a)
+#define hri_sdhc_write_HC1R_EMMC_HSEN_bit(a, b) hri_sdhc_write_HC1R_HSEN_bit(a, b)
+#define hri_sdhc_clear_HC1R_EMMC_HSEN_bit(a) hri_sdhc_clear_HC1R_HSEN_bit(a)
+#define hri_sdhc_toggle_HC1R_EMMC_HSEN_bit(a) hri_sdhc_toggle_HC1R_HSEN_bit(a)
+#define hri_sdhc_set_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_set_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_get_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_get_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_write_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_write_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_clear_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_clear_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_toggle_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_toggle_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_read_HC1R_EMMC_DMASEL_bf(a) hri_sdhc_read_HC1R_DMASEL_bf(a)
+#define hri_sdhc_set_HC1R_EMMC_reg(a, b) hri_sdhc_set_HC1R_reg(a, b)
+#define hri_sdhc_get_HC1R_EMMC_reg(a, b) hri_sdhc_get_HC1R_reg(a, b)
+#define hri_sdhc_write_HC1R_EMMC_reg(a, b) hri_sdhc_write_HC1R_reg(a, b)
+#define hri_sdhc_clear_HC1R_EMMC_reg(a, b) hri_sdhc_clear_HC1R_reg(a, b)
+#define hri_sdhc_toggle_HC1R_EMMC_reg(a, b) hri_sdhc_toggle_HC1R_reg(a, b)
+#define hri_sdhc_read_HC1R_EMMC_reg(a) hri_sdhc_read_HC1R_reg(a)
+#define hri_sdhc_set_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_set_BGCR_STPBGR_bit(a)
+#define hri_sdhc_get_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_get_BGCR_STPBGR_bit(a)
+#define hri_sdhc_write_BGCR_EMMC_STPBGR_bit(a, b) hri_sdhc_write_BGCR_STPBGR_bit(a, b)
+#define hri_sdhc_clear_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_clear_BGCR_STPBGR_bit(a)
+#define hri_sdhc_toggle_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_toggle_BGCR_STPBGR_bit(a)
+#define hri_sdhc_set_BGCR_EMMC_CONTR_bit(a) hri_sdhc_set_BGCR_CONTR_bit(a)
+#define hri_sdhc_get_BGCR_EMMC_CONTR_bit(a) hri_sdhc_get_BGCR_CONTR_bit(a)
+#define hri_sdhc_write_BGCR_EMMC_CONTR_bit(a, b) hri_sdhc_write_BGCR_CONTR_bit(a, b)
+#define hri_sdhc_clear_BGCR_EMMC_CONTR_bit(a) hri_sdhc_clear_BGCR_CONTR_bit(a)
+#define hri_sdhc_toggle_BGCR_EMMC_CONTR_bit(a) hri_sdhc_toggle_BGCR_CONTR_bit(a)
+#define hri_sdhc_set_BGCR_EMMC_reg(a, b) hri_sdhc_set_BGCR_reg(a, b)
+#define hri_sdhc_get_BGCR_EMMC_reg(a, b) hri_sdhc_get_BGCR_reg(a, b)
+#define hri_sdhc_write_BGCR_EMMC_reg(a, b) hri_sdhc_write_BGCR_reg(a, b)
+#define hri_sdhc_clear_BGCR_EMMC_reg(a, b) hri_sdhc_clear_BGCR_reg(a, b)
+#define hri_sdhc_toggle_BGCR_EMMC_reg(a, b) hri_sdhc_toggle_BGCR_reg(a, b)
+#define hri_sdhc_read_BGCR_EMMC_reg(a) hri_sdhc_read_BGCR_reg(a)
+#define hri_sdhc_set_NISTR_EMMC_CMDC_bit(a) hri_sdhc_set_NISTR_CMDC_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_CMDC_bit(a) hri_sdhc_get_NISTR_CMDC_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTR_CMDC_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTR_CMDC_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTR_CMDC_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_TRFC_bit(a) hri_sdhc_set_NISTR_TRFC_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_TRFC_bit(a) hri_sdhc_get_NISTR_TRFC_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTR_TRFC_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTR_TRFC_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTR_TRFC_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTR_BLKGE_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTR_BLKGE_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTR_BLKGE_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTR_BLKGE_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTR_BLKGE_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTR_DMAINT_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTR_DMAINT_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTR_DMAINT_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTR_DMAINT_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTR_DMAINT_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTR_BWRRDY_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTR_BWRRDY_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTR_BWRRDY_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTR_BWRRDY_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTR_BWRRDY_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTR_BRDRDY_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTR_BRDRDY_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTR_BRDRDY_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTR_BRDRDY_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTR_BRDRDY_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_set_NISTR_ERRINT_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_get_NISTR_ERRINT_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_ERRINT_bit(a, b) hri_sdhc_write_NISTR_ERRINT_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_clear_NISTR_ERRINT_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_toggle_NISTR_ERRINT_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_reg(a, b) hri_sdhc_set_NISTR_reg(a, b)
+#define hri_sdhc_get_NISTR_EMMC_reg(a, b) hri_sdhc_get_NISTR_reg(a, b)
+#define hri_sdhc_write_NISTR_EMMC_reg(a, b) hri_sdhc_write_NISTR_reg(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_reg(a, b) hri_sdhc_clear_NISTR_reg(a, b)
+#define hri_sdhc_toggle_NISTR_EMMC_reg(a, b) hri_sdhc_toggle_NISTR_reg(a, b)
+#define hri_sdhc_read_NISTR_EMMC_reg(a) hri_sdhc_read_NISTR_reg(a)
+#define hri_sdhc_set_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTR_CMDTEO_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTR_CMDTEO_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTR_CMDTEO_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTR_CMDTEO_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTR_CMDTEO_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTR_CMDCRC_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTR_CMDCRC_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTR_CMDCRC_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTR_CMDCRC_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTR_CMDCRC_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTR_CMDEND_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTR_CMDEND_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTR_CMDEND_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTR_CMDEND_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTR_CMDEND_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTR_CMDIDX_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTR_CMDIDX_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTR_CMDIDX_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTR_CMDIDX_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTR_CMDIDX_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTR_DATTEO_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTR_DATTEO_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTR_DATTEO_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTR_DATTEO_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTR_DATTEO_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTR_DATCRC_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTR_DATCRC_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTR_DATCRC_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTR_DATCRC_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTR_DATCRC_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_DATEND_bit(a) hri_sdhc_set_EISTR_DATEND_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_DATEND_bit(a) hri_sdhc_get_EISTR_DATEND_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTR_DATEND_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTR_DATEND_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTR_DATEND_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTR_CURLIM_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTR_CURLIM_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTR_CURLIM_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTR_CURLIM_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTR_CURLIM_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_ACMD_bit(a) hri_sdhc_set_EISTR_ACMD_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_ACMD_bit(a) hri_sdhc_get_EISTR_ACMD_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTR_ACMD_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTR_ACMD_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTR_ACMD_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_ADMA_bit(a) hri_sdhc_set_EISTR_ADMA_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_ADMA_bit(a) hri_sdhc_get_EISTR_ADMA_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTR_ADMA_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTR_ADMA_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTR_ADMA_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_reg(a, b) hri_sdhc_set_EISTR_reg(a, b)
+#define hri_sdhc_get_EISTR_EMMC_reg(a, b) hri_sdhc_get_EISTR_reg(a, b)
+#define hri_sdhc_write_EISTR_EMMC_reg(a, b) hri_sdhc_write_EISTR_reg(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_reg(a, b) hri_sdhc_clear_EISTR_reg(a, b)
+#define hri_sdhc_toggle_EISTR_EMMC_reg(a, b) hri_sdhc_toggle_EISTR_reg(a, b)
+#define hri_sdhc_read_EISTR_EMMC_reg(a) hri_sdhc_read_EISTR_reg(a)
+#define hri_sdhc_set_NISTER_EMMC_CMDC_bit(a) hri_sdhc_set_NISTER_CMDC_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_CMDC_bit(a) hri_sdhc_get_NISTER_CMDC_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTER_CMDC_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTER_CMDC_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTER_CMDC_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_TRFC_bit(a) hri_sdhc_set_NISTER_TRFC_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_TRFC_bit(a) hri_sdhc_get_NISTER_TRFC_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTER_TRFC_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTER_TRFC_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTER_TRFC_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTER_BLKGE_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTER_BLKGE_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTER_BLKGE_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTER_BLKGE_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTER_BLKGE_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTER_DMAINT_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTER_DMAINT_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTER_DMAINT_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTER_DMAINT_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTER_DMAINT_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTER_BWRRDY_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTER_BWRRDY_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTER_BWRRDY_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTER_BWRRDY_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTER_BWRRDY_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTER_BRDRDY_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTER_BRDRDY_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTER_BRDRDY_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTER_BRDRDY_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTER_BRDRDY_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_reg(a, b) hri_sdhc_set_NISTER_reg(a, b)
+#define hri_sdhc_get_NISTER_EMMC_reg(a, b) hri_sdhc_get_NISTER_reg(a, b)
+#define hri_sdhc_write_NISTER_EMMC_reg(a, b) hri_sdhc_write_NISTER_reg(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_reg(a, b) hri_sdhc_clear_NISTER_reg(a, b)
+#define hri_sdhc_toggle_NISTER_EMMC_reg(a, b) hri_sdhc_toggle_NISTER_reg(a, b)
+#define hri_sdhc_read_NISTER_EMMC_reg(a) hri_sdhc_read_NISTER_reg(a)
+#define hri_sdhc_set_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTER_CMDTEO_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTER_CMDTEO_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTER_CMDTEO_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTER_CMDTEO_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTER_CMDTEO_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTER_CMDCRC_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTER_CMDCRC_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTER_CMDCRC_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTER_CMDCRC_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTER_CMDCRC_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTER_CMDEND_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTER_CMDEND_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTER_CMDEND_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTER_CMDEND_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTER_CMDEND_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTER_CMDIDX_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTER_CMDIDX_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTER_CMDIDX_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTER_CMDIDX_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTER_CMDIDX_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTER_DATTEO_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTER_DATTEO_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTER_DATTEO_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTER_DATTEO_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTER_DATTEO_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTER_DATCRC_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTER_DATCRC_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTER_DATCRC_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTER_DATCRC_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTER_DATCRC_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_DATEND_bit(a) hri_sdhc_set_EISTER_DATEND_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_DATEND_bit(a) hri_sdhc_get_EISTER_DATEND_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTER_DATEND_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTER_DATEND_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTER_DATEND_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTER_CURLIM_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTER_CURLIM_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTER_CURLIM_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTER_CURLIM_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTER_CURLIM_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_ACMD_bit(a) hri_sdhc_set_EISTER_ACMD_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_ACMD_bit(a) hri_sdhc_get_EISTER_ACMD_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTER_ACMD_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTER_ACMD_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTER_ACMD_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_ADMA_bit(a) hri_sdhc_set_EISTER_ADMA_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_ADMA_bit(a) hri_sdhc_get_EISTER_ADMA_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTER_ADMA_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTER_ADMA_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTER_ADMA_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_reg(a, b) hri_sdhc_set_EISTER_reg(a, b)
+#define hri_sdhc_get_EISTER_EMMC_reg(a, b) hri_sdhc_get_EISTER_reg(a, b)
+#define hri_sdhc_write_EISTER_EMMC_reg(a, b) hri_sdhc_write_EISTER_reg(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_reg(a, b) hri_sdhc_clear_EISTER_reg(a, b)
+#define hri_sdhc_toggle_EISTER_EMMC_reg(a, b) hri_sdhc_toggle_EISTER_reg(a, b)
+#define hri_sdhc_read_EISTER_EMMC_reg(a) hri_sdhc_read_EISTER_reg(a)
+#define hri_sdhc_set_NISIER_EMMC_CMDC_bit(a) hri_sdhc_set_NISIER_CMDC_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_CMDC_bit(a) hri_sdhc_get_NISIER_CMDC_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISIER_CMDC_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISIER_CMDC_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISIER_CMDC_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_TRFC_bit(a) hri_sdhc_set_NISIER_TRFC_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_TRFC_bit(a) hri_sdhc_get_NISIER_TRFC_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISIER_TRFC_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISIER_TRFC_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISIER_TRFC_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISIER_BLKGE_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISIER_BLKGE_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISIER_BLKGE_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISIER_BLKGE_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISIER_BLKGE_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISIER_DMAINT_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISIER_DMAINT_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISIER_DMAINT_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISIER_DMAINT_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISIER_DMAINT_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISIER_BWRRDY_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISIER_BWRRDY_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISIER_BWRRDY_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISIER_BWRRDY_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISIER_BWRRDY_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISIER_BRDRDY_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISIER_BRDRDY_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISIER_BRDRDY_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISIER_BRDRDY_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISIER_BRDRDY_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_reg(a, b) hri_sdhc_set_NISIER_reg(a, b)
+#define hri_sdhc_get_NISIER_EMMC_reg(a, b) hri_sdhc_get_NISIER_reg(a, b)
+#define hri_sdhc_write_NISIER_EMMC_reg(a, b) hri_sdhc_write_NISIER_reg(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_reg(a, b) hri_sdhc_clear_NISIER_reg(a, b)
+#define hri_sdhc_toggle_NISIER_EMMC_reg(a, b) hri_sdhc_toggle_NISIER_reg(a, b)
+#define hri_sdhc_read_NISIER_EMMC_reg(a) hri_sdhc_read_NISIER_reg(a)
+#define hri_sdhc_set_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISIER_CMDTEO_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISIER_CMDTEO_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISIER_CMDTEO_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISIER_CMDTEO_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISIER_CMDTEO_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISIER_CMDCRC_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISIER_CMDCRC_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISIER_CMDCRC_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISIER_CMDCRC_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISIER_CMDCRC_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISIER_CMDEND_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISIER_CMDEND_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISIER_CMDEND_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISIER_CMDEND_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISIER_CMDEND_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISIER_CMDIDX_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISIER_CMDIDX_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISIER_CMDIDX_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISIER_CMDIDX_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISIER_CMDIDX_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISIER_DATTEO_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISIER_DATTEO_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISIER_DATTEO_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISIER_DATTEO_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISIER_DATTEO_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISIER_DATCRC_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISIER_DATCRC_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISIER_DATCRC_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISIER_DATCRC_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISIER_DATCRC_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_DATEND_bit(a) hri_sdhc_set_EISIER_DATEND_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_DATEND_bit(a) hri_sdhc_get_EISIER_DATEND_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISIER_DATEND_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISIER_DATEND_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISIER_DATEND_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISIER_CURLIM_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISIER_CURLIM_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISIER_CURLIM_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISIER_CURLIM_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISIER_CURLIM_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_ACMD_bit(a) hri_sdhc_set_EISIER_ACMD_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_ACMD_bit(a) hri_sdhc_get_EISIER_ACMD_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISIER_ACMD_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISIER_ACMD_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISIER_ACMD_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_ADMA_bit(a) hri_sdhc_set_EISIER_ADMA_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_ADMA_bit(a) hri_sdhc_get_EISIER_ADMA_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISIER_ADMA_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISIER_ADMA_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISIER_ADMA_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_reg(a, b) hri_sdhc_set_EISIER_reg(a, b)
+#define hri_sdhc_get_EISIER_EMMC_reg(a, b) hri_sdhc_get_EISIER_reg(a, b)
+#define hri_sdhc_write_EISIER_EMMC_reg(a, b) hri_sdhc_write_EISIER_reg(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_reg(a, b) hri_sdhc_clear_EISIER_reg(a, b)
+#define hri_sdhc_toggle_EISIER_EMMC_reg(a, b) hri_sdhc_toggle_EISIER_reg(a, b)
+#define hri_sdhc_read_EISIER_EMMC_reg(a) hri_sdhc_read_EISIER_reg(a)
+#define hri_sdhc_set_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_set_HC2R_EXTUN_bit(a)
+#define hri_sdhc_get_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_get_HC2R_EXTUN_bit(a)
+#define hri_sdhc_write_HC2R_EMMC_EXTUN_bit(a, b) hri_sdhc_write_HC2R_EXTUN_bit(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_clear_HC2R_EXTUN_bit(a)
+#define hri_sdhc_toggle_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_toggle_HC2R_EXTUN_bit(a)
+#define hri_sdhc_set_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_set_HC2R_SLCKSEL_bit(a)
+#define hri_sdhc_get_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_get_HC2R_SLCKSEL_bit(a)
+#define hri_sdhc_write_HC2R_EMMC_SLCKSEL_bit(a, b) hri_sdhc_write_HC2R_SLCKSEL_bit(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_clear_HC2R_SLCKSEL_bit(a)
+#define hri_sdhc_toggle_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_toggle_HC2R_SLCKSEL_bit(a)
+#define hri_sdhc_set_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_set_HC2R_PVALEN_bit(a)
+#define hri_sdhc_get_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_get_HC2R_PVALEN_bit(a)
+#define hri_sdhc_write_HC2R_EMMC_PVALEN_bit(a, b) hri_sdhc_write_HC2R_PVALEN_bit(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_clear_HC2R_PVALEN_bit(a)
+#define hri_sdhc_toggle_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_toggle_HC2R_PVALEN_bit(a)
+#define hri_sdhc_set_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_set_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_get_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_get_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_write_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_write_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_clear_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_toggle_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_toggle_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_read_HC2R_EMMC_DRVSEL_bf(a) hri_sdhc_read_HC2R_DRVSEL_bf(a)
+#define hri_sdhc_set_HC2R_EMMC_reg(a, b) hri_sdhc_set_HC2R_reg(a, b)
+#define hri_sdhc_get_HC2R_EMMC_reg(a, b) hri_sdhc_get_HC2R_reg(a, b)
+#define hri_sdhc_write_HC2R_EMMC_reg(a, b) hri_sdhc_write_HC2R_reg(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_reg(a, b) hri_sdhc_clear_HC2R_reg(a, b)
+#define hri_sdhc_toggle_HC2R_EMMC_reg(a, b) hri_sdhc_toggle_HC2R_reg(a, b)
+#define hri_sdhc_read_HC2R_EMMC_reg(a) hri_sdhc_read_HC2R_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SDHC_D51_H_INCLUDED */
+#endif /* _SAMD51_SDHC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_sercom_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_sercom_d51.h
new file mode 100644
index 0000000..761830e
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_sercom_d51.h
@@ -0,0 +1,8892 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM
+ *
+ * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_SERCOM_COMPONENT_
+#ifndef _HRI_SERCOM_D51_H_INCLUDED_
+#define _HRI_SERCOM_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS)
+#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SERCOM_CRITICAL_SECTION_ENTER()
+#define SERCOM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_sercomi2cm_status_reg_t;
+typedef uint16_t hri_sercomi2cs_length_reg_t;
+typedef uint16_t hri_sercomi2cs_status_reg_t;
+typedef uint16_t hri_sercomspi_length_reg_t;
+typedef uint16_t hri_sercomspi_status_reg_t;
+typedef uint16_t hri_sercomusart_baud_reg_t;
+typedef uint16_t hri_sercomusart_length_reg_t;
+typedef uint16_t hri_sercomusart_status_reg_t;
+typedef uint32_t hri_sercomi2cm_addr_reg_t;
+typedef uint32_t hri_sercomi2cm_baud_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrla_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrlb_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrlc_reg_t;
+typedef uint32_t hri_sercomi2cm_data_reg_t;
+typedef uint32_t hri_sercomi2cm_syncbusy_reg_t;
+typedef uint32_t hri_sercomi2cs_addr_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrla_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrlb_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrlc_reg_t;
+typedef uint32_t hri_sercomi2cs_data_reg_t;
+typedef uint32_t hri_sercomi2cs_syncbusy_reg_t;
+typedef uint32_t hri_sercomspi_addr_reg_t;
+typedef uint32_t hri_sercomspi_ctrla_reg_t;
+typedef uint32_t hri_sercomspi_ctrlb_reg_t;
+typedef uint32_t hri_sercomspi_ctrlc_reg_t;
+typedef uint32_t hri_sercomspi_data_reg_t;
+typedef uint32_t hri_sercomspi_syncbusy_reg_t;
+typedef uint32_t hri_sercomusart_ctrla_reg_t;
+typedef uint32_t hri_sercomusart_ctrlb_reg_t;
+typedef uint32_t hri_sercomusart_ctrlc_reg_t;
+typedef uint32_t hri_sercomusart_data_reg_t;
+typedef uint32_t hri_sercomusart_syncbusy_reg_t;
+typedef uint8_t  hri_sercomi2cm_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomi2cm_intenset_reg_t;
+typedef uint8_t  hri_sercomi2cm_intflag_reg_t;
+typedef uint8_t  hri_sercomi2cs_intenset_reg_t;
+typedef uint8_t  hri_sercomi2cs_intflag_reg_t;
+typedef uint8_t  hri_sercomspi_baud_reg_t;
+typedef uint8_t  hri_sercomspi_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomspi_intenset_reg_t;
+typedef uint8_t  hri_sercomspi_intflag_reg_t;
+typedef uint8_t  hri_sercomusart_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomusart_intenset_reg_t;
+typedef uint8_t  hri_sercomusart_intflag_reg_t;
+typedef uint8_t  hri_sercomusart_rxerrcnt_reg_t;
+typedef uint8_t  hri_sercomusart_rxpl_reg_t;
+
+static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
+}
+
+static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_sercomi2cm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.INTFLAG.reg;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
+}
+
+static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_sercomi2cs_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.INTFLAG.reg;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
+}
+
+static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
+}
+
+static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const           hw,
+                                                                        hri_sercomspi_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.INTFLAG.reg;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+}
+
+static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+}
+
+static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const             hw,
+                                                                            hri_sercomusart_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.INTFLAG.reg;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = mask;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = mask;
+}
+
+static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const             hw,
+                                                                         hri_sercomi2cm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.INTENSET.reg;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = data;
+	((Sercom *)hw)->I2CM.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = mask;
+}
+
+static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const             hw,
+                                                                         hri_sercomi2cs_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.INTENSET.reg;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = data;
+	((Sercom *)hw)->I2CS.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
+}
+
+static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
+}
+
+static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
+}
+
+static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
+}
+
+static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
+}
+
+static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
+}
+
+static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
+}
+
+static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
+}
+
+static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
+}
+
+static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = mask;
+}
+
+static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const            hw,
+                                                                       hri_sercomspi_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.INTENSET.reg;
+}
+
+static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = data;
+	((Sercom *)hw)->SPI.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
+}
+
+static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
+}
+
+static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
+}
+
+static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = mask;
+}
+
+static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const              hw,
+                                                                           hri_sercomusart_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.INTENSET.reg;
+}
+
+static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = data;
+	((Sercom *)hw)->USART.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = mask;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_LENGTH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_LENGTH) >> SERCOM_I2CM_SYNCBUSY_LENGTH_Pos;
+}
+
+static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const             hw,
+                                                                            hri_sercomi2cm_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_LENGTH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_LENGTH) >> SERCOM_I2CS_SYNCBUSY_LENGTH_Pos;
+}
+
+static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const             hw,
+                                                                            hri_sercomi2cs_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_LENGTH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_LENGTH) >> SERCOM_SPI_SYNCBUSY_LENGTH_Pos;
+}
+
+static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const            hw,
+                                                                          hri_sercomspi_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_RXERRCNT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_RXERRCNT) >> SERCOM_USART_SYNCBUSY_RXERRCNT_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_LENGTH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_LENGTH) >> SERCOM_USART_SYNCBUSY_LENGTH_Pos;
+}
+
+static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const              hw,
+                                                                              hri_sercomusart_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg;
+}
+
+static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const              hw,
+                                                                              hri_sercomusart_rxerrcnt_reg_t mask)
+{
+	uint8_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.RXERRCNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->USART.RXERRCNT.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_ENABLE;
+	tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_PINOUT;
+	tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SCLSM;
+	tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const          hw,
+                                                                          hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_MODE(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const          hw,
+                                                                             hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const          hw,
+                                                                           hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_SPEED(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const          hw,
+                                                                              hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->I2CM.CTRLA.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_ENABLE;
+	tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_PINOUT;
+	tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
+	tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SCLSM;
+	tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const          hw,
+                                                                          hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_MODE(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const          hw,
+                                                                             hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const          hw,
+                                                                           hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_SPEED(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg = data;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->I2CS.CTRLA.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_ENABLE;
+	tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_IBON;
+	tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_CPHA;
+	tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_CPOL;
+	tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DORD;
+	tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk;
+	tmp |= SERCOM_SPI_CTRLA_MODE(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk;
+	tmp |= SERCOM_SPI_CTRLA_DOPO(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk;
+	tmp |= SERCOM_SPI_CTRLA_DIPO(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk;
+	tmp |= SERCOM_SPI_CTRLA_FORM(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->SPI.CTRLA.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_ENABLE;
+	tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_IBON;
+	tmp |= value << SERCOM_USART_CTRLA_IBON_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_TXINV;
+	tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RXINV;
+	tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_CMODE;
+	tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_CPOL;
+	tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_DORD;
+	tmp |= value << SERCOM_USART_CTRLA_DORD_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_MODE_Msk;
+	tmp |= SERCOM_USART_CTRLA_MODE(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk;
+	tmp |= SERCOM_USART_CTRLA_SAMPR(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk;
+	tmp |= SERCOM_USART_CTRLA_TXPO(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk;
+	tmp |= SERCOM_USART_CTRLA_RXPO(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk;
+	tmp |= SERCOM_USART_CTRLA_SAMPA(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_FORM_Msk;
+	tmp |= SERCOM_USART_CTRLA_FORM(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->USART.CTRLA.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_SMEN;
+	tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_QCEN;
+	tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const          hw,
+                                                                         hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk;
+	tmp |= SERCOM_I2CM_CTRLB_CMD(data);
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.CTRLB.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_SMEN;
+	tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_GCMD;
+	tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_AACKEN;
+	tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const          hw,
+                                                                           hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk;
+	tmp |= SERCOM_I2CS_CTRLB_AMODE(data);
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const          hw,
+                                                                         hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk;
+	tmp |= SERCOM_I2CS_CTRLB_CMD(data);
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.CTRLB.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_PLOADEN;
+	tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_SSDE;
+	tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_MSSEN;
+	tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_RXEN;
+	tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const         hw,
+                                                                          hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk;
+	tmp |= SERCOM_SPI_CTRLB_CHSIZE(data);
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const         hw,
+                                                                         hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk;
+	tmp |= SERCOM_SPI_CTRLB_AMODE(data);
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->SPI.CTRLB.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_SBMODE;
+	tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_COLDEN;
+	tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_SFDE;
+	tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_ENC;
+	tmp |= value << SERCOM_USART_CTRLB_ENC_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_PMODE;
+	tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_TXEN;
+	tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_RXEN;
+	tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk;
+	tmp |= SERCOM_USART_CTRLB_CHSIZE(data);
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk;
+	tmp |= SERCOM_USART_CTRLB_LINCMD(data);
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->USART.CTRLB.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg |= SERCOM_I2CM_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLC_DATA32B_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLC.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLC_DATA32B) >> SERCOM_I2CM_CTRLC_DATA32B_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLC_DATA32B_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLC.reg;
+	tmp &= ~SERCOM_I2CM_CTRLC_DATA32B;
+	tmp |= value << SERCOM_I2CM_CTRLC_DATA32B_Pos;
+	((Sercom *)hw)->I2CM.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg &= ~SERCOM_I2CM_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg ^= SERCOM_I2CM_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_get_CTRLC_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.CTRLC.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLC_DATA32B_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLC_DATA32B) >> SERCOM_I2CS_CTRLC_DATA32B_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLC_DATA32B_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp &= ~SERCOM_I2CS_CTRLC_DATA32B;
+	tmp |= value << SERCOM_I2CS_CTRLC_DATA32B_Pos;
+	((Sercom *)hw)->I2CS.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_SDASETUP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_SDASETUP_bf(const void *const          hw,
+                                                                              hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP(mask)) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp &= ~SERCOM_I2CS_CTRLC_SDASETUP_Msk;
+	tmp |= SERCOM_I2CS_CTRLC_SDASETUP(data);
+	((Sercom *)hw)->I2CS.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_SDASETUP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_SDASETUP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_SDASETUP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP_Msk) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.CTRLC.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLC_DATA32B_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLC_DATA32B) >> SERCOM_SPI_CTRLC_DATA32B_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLC_DATA32B_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp &= ~SERCOM_SPI_CTRLC_DATA32B;
+	tmp |= value << SERCOM_SPI_CTRLC_DATA32B_Pos;
+	((Sercom *)hw)->SPI.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_ICSPACE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_ICSPACE_bf(const void *const         hw,
+                                                                           hri_sercomspi_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE(mask)) >> SERCOM_SPI_CTRLC_ICSPACE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp &= ~SERCOM_SPI_CTRLC_ICSPACE_Msk;
+	tmp |= SERCOM_SPI_CTRLC_ICSPACE(data);
+	((Sercom *)hw)->SPI.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_ICSPACE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_ICSPACE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_ICSPACE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE_Msk) >> SERCOM_SPI_CTRLC_ICSPACE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.CTRLC.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_INACK;
+	tmp |= value << SERCOM_USART_CTRLC_INACK_Pos;
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_DSNACK;
+	tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos;
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk;
+	tmp |= SERCOM_USART_CTRLC_GTIME(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk;
+	tmp |= SERCOM_USART_CTRLC_BRKLEN(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk;
+	tmp |= SERCOM_USART_CTRLC_HDRDLY(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const           hw,
+                                                                               hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk;
+	tmp |= SERCOM_USART_CTRLC_MAXITER(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DATA32B(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_DATA32B_bf(const void *const           hw,
+                                                                               hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_DATA32B(mask)) >> SERCOM_USART_CTRLC_DATA32B_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_DATA32B_Msk;
+	tmp |= SERCOM_USART_CTRLC_DATA32B(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DATA32B(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DATA32B(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_DATA32B_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_DATA32B_Msk) >> SERCOM_USART_CTRLC_DATA32B_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.CTRLC.reg;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk;
+	tmp |= SERCOM_I2CM_BAUD_BAUD(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const         hw,
+                                                                           hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk;
+	tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const         hw,
+                                                                          hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk;
+	tmp |= SERCOM_I2CM_BAUD_HSBAUD(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const         hw,
+                                                                             hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk;
+	tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.BAUD.reg;
+}
+
+static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const        hw,
+                                                                      hri_sercomspi_baud_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk;
+	tmp |= SERCOM_SPI_BAUD_BAUD(data);
+	((Sercom *)hw)->SPI.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const          hw,
+                                                                               hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const          hw,
+                                                                                 hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const          hw,
+                                                                             hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const          hw,
+                                                                               hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk;
+	tmp |= SERCOM_USART_BAUD_FRAC_FP(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk;
+	tmp |= SERCOM_USART_BAUD_FRACFP_FP(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const          hw,
+                                                                          hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const          hw,
+                                                                                  hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const          hw,
+                                                                      hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const          hw,
+                                                                          hri_sercomusart_rxpl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp &= ~SERCOM_USART_RXPL_RXPL_Msk;
+	tmp |= SERCOM_USART_RXPL_RXPL(data);
+	((Sercom *)hw)->USART.RXPL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const          hw,
+                                                                      hri_sercomusart_rxpl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.RXPL.reg;
+}
+
+static inline void hri_sercomi2cs_set_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LENEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_LENGTH_LENEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp = (tmp & SERCOM_I2CS_LENGTH_LENEN) >> SERCOM_I2CS_LENGTH_LENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_LENGTH_LENEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp &= ~SERCOM_I2CS_LENGTH_LENEN;
+	tmp |= value << SERCOM_I2CS_LENGTH_LENEN_Pos;
+	((Sercom *)hw)->I2CS.LENGTH.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LENEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LENEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LEN(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_LEN_bf(const void *const           hw,
+                                                                           hri_sercomi2cs_length_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp = (tmp & SERCOM_I2CS_LENGTH_LEN(mask)) >> SERCOM_I2CS_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp &= ~SERCOM_I2CS_LENGTH_LEN_Msk;
+	tmp |= SERCOM_I2CS_LENGTH_LEN(data);
+	((Sercom *)hw)->I2CS.LENGTH.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LEN(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LEN(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_LEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp = (tmp & SERCOM_I2CS_LENGTH_LEN_Msk) >> SERCOM_I2CS_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg |= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_reg(const void *const           hw,
+                                                                        hri_sercomi2cs_length_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg = data;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg &= ~mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg ^= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_reg(const void *const hw)
+{
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->I2CS.LENGTH.reg;
+}
+
+static inline void hri_sercomspi_set_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LENEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_LENGTH_LENEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp = (tmp & SERCOM_SPI_LENGTH_LENEN) >> SERCOM_SPI_LENGTH_LENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_LENGTH_LENEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp &= ~SERCOM_SPI_LENGTH_LENEN;
+	tmp |= value << SERCOM_SPI_LENGTH_LENEN_Pos;
+	((Sercom *)hw)->SPI.LENGTH.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LENEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LENEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LEN(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_LEN_bf(const void *const          hw,
+                                                                         hri_sercomspi_length_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp = (tmp & SERCOM_SPI_LENGTH_LEN(mask)) >> SERCOM_SPI_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp &= ~SERCOM_SPI_LENGTH_LEN_Msk;
+	tmp |= SERCOM_SPI_LENGTH_LEN(data);
+	((Sercom *)hw)->SPI.LENGTH.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LEN(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LEN(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_LEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp = (tmp & SERCOM_SPI_LENGTH_LEN_Msk) >> SERCOM_SPI_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_reg(const void *const          hw,
+                                                                      hri_sercomspi_length_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->SPI.LENGTH.reg;
+}
+
+static inline void hri_sercomusart_set_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LEN_bf(const void *const            hw,
+                                                                             hri_sercomusart_length_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp = (tmp & SERCOM_USART_LENGTH_LEN(mask)) >> SERCOM_USART_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp &= ~SERCOM_USART_LENGTH_LEN_Msk;
+	tmp |= SERCOM_USART_LENGTH_LEN(data);
+	((Sercom *)hw)->USART.LENGTH.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp = (tmp & SERCOM_USART_LENGTH_LEN_Msk) >> SERCOM_USART_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LENEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LENEN_bf(const void *const            hw,
+                                                                               hri_sercomusart_length_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp = (tmp & SERCOM_USART_LENGTH_LENEN(mask)) >> SERCOM_USART_LENGTH_LENEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp &= ~SERCOM_USART_LENGTH_LENEN_Msk;
+	tmp |= SERCOM_USART_LENGTH_LENEN(data);
+	((Sercom *)hw)->USART.LENGTH.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LENEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LENEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LENEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp = (tmp & SERCOM_USART_LENGTH_LENEN_Msk) >> SERCOM_USART_LENGTH_LENEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_reg(const void *const            hw,
+                                                                          hri_sercomusart_length_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->USART.LENGTH.reg;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_LENEN;
+	tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_HS;
+	tmp |= value << SERCOM_I2CM_ADDR_HS_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_TENBITEN;
+	tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk;
+	tmp |= SERCOM_I2CM_ADDR_ADDR(data);
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const         hw,
+                                                                       hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk;
+	tmp |= SERCOM_I2CM_ADDR_LEN(data);
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.ADDR.reg;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_GENCEN;
+	tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos;
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_TENBITEN;
+	tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos;
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const         hw,
+                                                                        hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk;
+	tmp |= SERCOM_I2CS_ADDR_ADDR(data);
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const         hw,
+                                                                            hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk;
+	tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data);
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const         hw,
+                                                                    hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.ADDR.reg;
+}
+
+static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const        hw,
+                                                                      hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk;
+	tmp |= SERCOM_SPI_ADDR_ADDR(data);
+	((Sercom *)hw)->SPI.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const        hw,
+                                                                          hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk;
+	tmp |= SERCOM_SPI_ADDR_ADDRMASK(data);
+	((Sercom *)hw)->SPI.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.ADDR.reg;
+}
+
+static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp &= ~SERCOM_I2CM_DATA_DATA_Msk;
+	tmp |= SERCOM_I2CM_DATA_DATA(data);
+	((Sercom *)hw)->I2CM.DATA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_data_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.DATA.reg;
+}
+
+static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const         hw,
+                                                                        hri_sercomi2cs_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp &= ~SERCOM_I2CS_DATA_DATA_Msk;
+	tmp |= SERCOM_I2CS_DATA_DATA(data);
+	((Sercom *)hw)->I2CS.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const         hw,
+                                                                    hri_sercomi2cs_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.DATA.reg;
+}
+
+static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const        hw,
+                                                                      hri_sercomspi_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp &= ~SERCOM_SPI_DATA_DATA_Msk;
+	tmp |= SERCOM_SPI_DATA_DATA(data);
+	((Sercom *)hw)->SPI.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.DATA.reg;
+}
+
+static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const          hw,
+                                                                          hri_sercomusart_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp &= ~SERCOM_USART_DATA_DATA_Msk;
+	tmp |= SERCOM_USART_DATA_DATA(data);
+	((Sercom *)hw)->USART.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const          hw,
+                                                                      hri_sercomusart_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.DATA.reg;
+}
+
+static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const            hw,
+                                                                          hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+}
+
+static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->SPI.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const           hw,
+                                                                        hri_sercomspi_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.DBGCTRL.reg;
+}
+
+static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->USART.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const             hw,
+                                                                            hri_sercomusart_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.DBGCTRL.reg;
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_LENERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LENERR) >> SERCOM_I2CS_STATUS_LENERR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const           hw,
+                                                                        hri_sercomi2cs_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.STATUS.reg;
+}
+
+static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos;
+}
+
+static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_STATUS_LENERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_LENERR) >> SERCOM_SPI_STATUS_LENERR_Pos;
+}
+
+static inline void hri_sercomspi_clear_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const          hw,
+                                                                      hri_sercomspi_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.STATUS.reg;
+}
+
+static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const            hw,
+                                                                          hri_sercomusart_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.STATUS.reg;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_BUSERR;
+	tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_ARBLOST;
+	tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_RXNACK;
+	tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD;
+	tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_LENERR;
+	tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const           hw,
+                                                                                hri_sercomi2cm_status_reg_t mask)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk;
+	tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data);
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const           hw,
+                                                                        hri_sercomi2cm_status_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg |= mask;
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.STATUS.reg;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg = data;
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg ^= mask;
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b)
+#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b)
+#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b)
+#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b)
+#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b)
+#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a)
+#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b)
+#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b)
+#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b)
+#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b)
+#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b)
+#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a)
+#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b)
+#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b)
+#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b)
+#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b)
+#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b)
+#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SERCOM_D51_H_INCLUDED */
+#endif /* _SAMD51_SERCOM_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_supc_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_supc_d51.h
new file mode 100644
index 0000000..3a78970
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_supc_d51.h
@@ -0,0 +1,1769 @@
+/**
+ * \file
+ *
+ * \brief SAM SUPC
+ *
+ * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_SUPC_COMPONENT_
+#ifndef _HRI_SUPC_D51_H_INCLUDED_
+#define _HRI_SUPC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SUPC_CRITICAL_SECTIONS)
+#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SUPC_CRITICAL_SECTION_ENTER()
+#define SUPC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_supc_bbps_reg_t;
+typedef uint32_t hri_supc_bkin_reg_t;
+typedef uint32_t hri_supc_bkout_reg_t;
+typedef uint32_t hri_supc_bod33_reg_t;
+typedef uint32_t hri_supc_intenset_reg_t;
+typedef uint32_t hri_supc_intflag_reg_t;
+typedef uint32_t hri_supc_status_reg_t;
+typedef uint32_t hri_supc_vref_reg_t;
+typedef uint32_t hri_supc_vreg_reg_t;
+
+static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
+}
+
+static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
+}
+
+static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY;
+}
+
+static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY;
+}
+
+static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY;
+}
+
+static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Supc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask)
+{
+	((Supc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY;
+}
+
+static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY;
+}
+
+static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET;
+}
+
+static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET;
+}
+
+static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY;
+}
+
+static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY;
+}
+
+static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY;
+}
+
+static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY;
+}
+
+static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY;
+}
+
+static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY;
+}
+
+static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	((Supc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw)
+{
+	return ((Supc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data)
+{
+	((Supc *)hw)->INTENSET.reg = data;
+	((Supc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	((Supc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos;
+}
+
+static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw)
+{
+	return ((Supc *)hw)->STATUS.reg;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask)
+{
+	return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw)
+{
+	return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKIN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BKIN.reg;
+}
+
+static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_ENABLE;
+	tmp |= value << SUPC_BOD33_ENABLE_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_STDBYCFG;
+	tmp |= value << SUPC_BOD33_STDBYCFG_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNSTDBY;
+	tmp |= value << SUPC_BOD33_RUNSTDBY_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNHIB;
+	tmp |= value << SUPC_BOD33_RUNHIB_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNBKUP;
+	tmp |= value << SUPC_BOD33_RUNBKUP_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_ACTION_Msk;
+	tmp |= SUPC_BOD33_ACTION(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_HYST_Msk;
+	tmp |= SUPC_BOD33_HYST(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_PSEL_Msk;
+	tmp |= SUPC_BOD33_PSEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_LEVEL_Msk;
+	tmp |= SUPC_BOD33_LEVEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_VBATLEVEL_Msk;
+	tmp |= SUPC_BOD33_VBATLEVEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BOD33.reg;
+}
+
+static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_ENABLE;
+	tmp |= value << SUPC_VREG_ENABLE_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_SEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_SEL;
+	tmp |= value << SUPC_VREG_SEL_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_RUNBKUP;
+	tmp |= value << SUPC_VREG_RUNBKUP_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_VSEN;
+	tmp |= value << SUPC_VREG_VSEN_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_VSPER_Msk;
+	tmp |= SUPC_VREG_VSPER(data);
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw)
+{
+	return ((Supc *)hw)->VREG.reg;
+}
+
+static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_TSEN;
+	tmp |= value << SUPC_VREF_TSEN_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_VREFOE;
+	tmp |= value << SUPC_VREF_VREFOE_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_TSSEL;
+	tmp |= value << SUPC_VREF_TSSEL_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_RUNSTDBY;
+	tmp |= value << SUPC_VREF_RUNSTDBY_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_ONDEMAND;
+	tmp |= value << SUPC_VREF_ONDEMAND_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_SEL_Msk;
+	tmp |= SUPC_VREF_SEL(data);
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw)
+{
+	return ((Supc *)hw)->VREF.reg;
+}
+
+static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= ~SUPC_BBPS_CONF;
+	tmp |= value << SUPC_BBPS_CONF_Pos;
+	((Supc *)hw)->BBPS.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= ~SUPC_BBPS_WAKEEN;
+	tmp |= value << SUPC_BBPS_WAKEEN_Pos;
+	((Supc *)hw)->BBPS.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BBPS.reg;
+}
+
+static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_EN_Msk;
+	tmp |= SUPC_BKOUT_EN(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_CLR_Msk;
+	tmp |= SUPC_BKOUT_CLR(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_SET_Msk;
+	tmp |= SUPC_BKOUT_SET(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_RTCTGL_Msk;
+	tmp |= SUPC_BKOUT_RTCTGL(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BKOUT.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SUPC_D51_H_INCLUDED */
+#endif /* _SAMD51_SUPC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_tc_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_tc_d51.h
new file mode 100644
index 0000000..59f3788
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_tc_d51.h
@@ -0,0 +1,3003 @@
+/**
+ * \file
+ *
+ * \brief SAM TC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_TC_COMPONENT_
+#ifndef _HRI_TC_D51_H_INCLUDED_
+#define _HRI_TC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TC_CRITICAL_SECTIONS)
+#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TC_CRITICAL_SECTION_ENTER()
+#define TC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_tc_evctrl_reg_t;
+typedef uint16_t hri_tccount16_cc_reg_t;
+typedef uint16_t hri_tccount16_ccbuf_reg_t;
+typedef uint16_t hri_tccount16_count_reg_t;
+typedef uint32_t hri_tc_ctrla_reg_t;
+typedef uint32_t hri_tc_syncbusy_reg_t;
+typedef uint32_t hri_tccount32_cc_reg_t;
+typedef uint32_t hri_tccount32_ccbuf_reg_t;
+typedef uint32_t hri_tccount32_count_reg_t;
+typedef uint8_t  hri_tc_ctrlbset_reg_t;
+typedef uint8_t  hri_tc_dbgctrl_reg_t;
+typedef uint8_t  hri_tc_drvctrl_reg_t;
+typedef uint8_t  hri_tc_intenset_reg_t;
+typedef uint8_t  hri_tc_intflag_reg_t;
+typedef uint8_t  hri_tc_status_reg_t;
+typedef uint8_t  hri_tc_wave_reg_t;
+typedef uint8_t  hri_tccount8_cc_reg_t;
+typedef uint8_t  hri_tccount8_ccbuf_reg_t;
+typedef uint8_t  hri_tccount8_count_reg_t;
+typedef uint8_t  hri_tccount8_per_reg_t;
+typedef uint8_t  hri_tccount8_perbuf_reg_t;
+
+static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg)
+{
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg)
+{
+	return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF;
+}
+
+static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR;
+}
+
+static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0;
+}
+
+static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1;
+}
+
+static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF;
+}
+
+static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR;
+}
+
+static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0;
+}
+
+static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1;
+}
+
+static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.INTFLAG.reg;
+}
+
+static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = mask;
+}
+
+static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR;
+}
+
+static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR;
+}
+
+static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD;
+}
+
+static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
+}
+
+static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
+}
+
+static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data);
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = mask;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+}
+
+static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = data;
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask;
+}
+
+static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF;
+}
+
+static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF;
+}
+
+static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR;
+}
+
+static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR;
+}
+
+static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0;
+}
+
+static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0;
+}
+
+static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1;
+}
+
+static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1;
+}
+
+static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = mask;
+}
+
+static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.INTENSET.reg;
+}
+
+static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = data;
+	((Tc *)hw)->COUNT16.INTENCLR.reg = ~data;
+}
+
+static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = mask;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos;
+}
+
+static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.SYNCBUSY.reg;
+}
+
+static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ENABLE;
+	tmp |= value << TC_CTRLA_ENABLE_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_RUNSTDBY;
+	tmp |= value << TC_CTRLA_RUNSTDBY_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ONDEMAND;
+	tmp |= value << TC_CTRLA_ONDEMAND_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ALOCK;
+	tmp |= value << TC_CTRLA_ALOCK_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTEN0;
+	tmp |= value << TC_CTRLA_CAPTEN0_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTEN1;
+	tmp |= value << TC_CTRLA_CAPTEN1_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_COPEN0;
+	tmp |= value << TC_CTRLA_COPEN0_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_COPEN1;
+	tmp |= value << TC_CTRLA_COPEN1_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_MODE_Msk;
+	tmp |= TC_CTRLA_MODE(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_PRESCSYNC_Msk;
+	tmp |= TC_CTRLA_PRESCSYNC(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_PRESCALER_Msk;
+	tmp |= TC_CTRLA_PRESCALER(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE0(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTMODE0(mask)) >> TC_CTRLA_CAPTMODE0_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTMODE0_Msk;
+	tmp |= TC_CTRLA_CAPTMODE0(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE0(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE0(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTMODE0_Msk) >> TC_CTRLA_CAPTMODE0_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE1(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTMODE1(mask)) >> TC_CTRLA_CAPTMODE1_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTMODE1_Msk;
+	tmp |= TC_CTRLA_CAPTMODE1(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE1(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE1(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTMODE1_Msk) >> TC_CTRLA_CAPTMODE1_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	return ((Tc *)hw)->COUNT16.CTRLA.reg;
+}
+
+static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_TCINV;
+	tmp |= value << TC_EVCTRL_TCINV_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_TCEI;
+	tmp |= value << TC_EVCTRL_TCEI_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_OVFEO;
+	tmp |= value << TC_EVCTRL_OVFEO_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_MCEO0;
+	tmp |= value << TC_EVCTRL_MCEO0_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_MCEO1;
+	tmp |= value << TC_EVCTRL_MCEO1_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_EVACT_Msk;
+	tmp |= TC_EVCTRL_EVACT(data);
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.EVCTRL.reg;
+}
+
+static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp &= ~TC_WAVE_WAVEGEN_Msk;
+	tmp |= TC_WAVE_WAVEGEN(data);
+	((Tc *)hw)->COUNT16.WAVE.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.WAVE.reg;
+}
+
+static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= ~TC_DRVCTRL_INVEN0;
+	tmp |= value << TC_DRVCTRL_INVEN0_Pos;
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= ~TC_DRVCTRL_INVEN1;
+	tmp |= value << TC_DRVCTRL_INVEN1_Pos;
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+}
+
+static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp &= ~TC_DBGCTRL_DBGRUN;
+	tmp |= value << TC_DBGCTRL_DBGRUN_Pos;
+	((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+}
+
+static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_tccount8_count_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp &= ~TC_COUNT8_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT8_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT8.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT8.COUNT.reg;
+}
+
+static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const         hw,
+                                                                         hri_tccount16_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp &= ~TC_COUNT16_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT16_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT16.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const         hw,
+                                                                    hri_tccount16_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT16.COUNT.reg;
+}
+
+static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const         hw,
+                                                                         hri_tccount32_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp &= ~TC_COUNT32_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT32_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT32.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const         hw,
+                                                                    hri_tccount32_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT32.COUNT.reg;
+}
+
+static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp &= ~TC_COUNT8_PER_PER_Msk;
+	tmp |= TC_COUNT8_PER_PER(data);
+	((Tc *)hw)->COUNT8.PER.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	return ((Tc *)hw)->COUNT8.PER.reg;
+}
+
+static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                              hri_tccount8_cc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp &= ~TC_COUNT8_CC_CC_Msk;
+	tmp |= TC_COUNT8_CC_CC(data);
+	((Tc *)hw)->COUNT8.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index,
+                                                            hri_tccount8_cc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT8.CC[index].reg;
+}
+
+static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                                hri_tccount16_cc_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp &= ~TC_COUNT16_CC_CC_Msk;
+	tmp |= TC_COUNT16_CC_CC(data);
+	((Tc *)hw)->COUNT16.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index,
+                                                              hri_tccount16_cc_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT16.CC[index].reg;
+}
+
+static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                                hri_tccount32_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp &= ~TC_COUNT32_CC_CC_Msk;
+	tmp |= TC_COUNT32_CC_CC(data);
+	((Tc *)hw)->COUNT32.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index,
+                                                              hri_tccount32_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT32.CC[index].reg;
+}
+
+static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const         hw,
+                                                                          hri_tccount8_perbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk;
+	tmp |= TC_COUNT8_PERBUF_PERBUF(data);
+	((Tc *)hw)->COUNT8.PERBUF.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const         hw,
+                                                                    hri_tccount8_perbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT8.PERBUF.reg;
+}
+
+static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tccount8_ccbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT8_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                  hri_tccount8_ccbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+}
+
+static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                         hri_tccount16_ccbuf_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount16_ccbuf_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT16_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                       hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                    hri_tccount16_ccbuf_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+}
+
+static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                         hri_tccount32_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount32_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT32_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                       hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                    hri_tccount32_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+}
+
+static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT16.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT16.STATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b)
+#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b)
+#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b)
+#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b)
+#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b)
+#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a)
+#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b)
+#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b)
+#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b)
+#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b)
+#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b)
+#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a)
+#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a)
+#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b)
+#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b)
+#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b)
+#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b)
+#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b)
+#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TC_D51_H_INCLUDED */
+#endif /* _SAMD51_TC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_tcc_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_tcc_d51.h
new file mode 100644
index 0000000..b9356a8
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_tcc_d51.h
@@ -0,0 +1,9992 @@
+/**
+ * \file
+ *
+ * \brief SAM TCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_TCC_COMPONENT_
+#ifndef _HRI_TCC_D51_H_INCLUDED_
+#define _HRI_TCC_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TCC_CRITICAL_SECTIONS)
+#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TCC_CRITICAL_SECTION_ENTER()
+#define TCC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_tcc_patt_reg_t;
+typedef uint16_t hri_tcc_pattbuf_reg_t;
+typedef uint32_t hri_tcc_cc_reg_t;
+typedef uint32_t hri_tcc_ccbuf_reg_t;
+typedef uint32_t hri_tcc_count_reg_t;
+typedef uint32_t hri_tcc_ctrla_reg_t;
+typedef uint32_t hri_tcc_drvctrl_reg_t;
+typedef uint32_t hri_tcc_evctrl_reg_t;
+typedef uint32_t hri_tcc_fctrla_reg_t;
+typedef uint32_t hri_tcc_fctrlb_reg_t;
+typedef uint32_t hri_tcc_intenset_reg_t;
+typedef uint32_t hri_tcc_intflag_reg_t;
+typedef uint32_t hri_tcc_per_reg_t;
+typedef uint32_t hri_tcc_perbuf_reg_t;
+typedef uint32_t hri_tcc_status_reg_t;
+typedef uint32_t hri_tcc_syncbusy_reg_t;
+typedef uint32_t hri_tcc_wave_reg_t;
+typedef uint32_t hri_tcc_wexctrl_reg_t;
+typedef uint8_t  hri_tcc_ctrlbset_reg_t;
+typedef uint8_t  hri_tcc_dbgctrl_reg_t;
+
+static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg)
+{
+	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg)
+{
+	return ((Tcc *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+}
+
+static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
+}
+
+static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
+}
+
+static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+}
+
+static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS;
+}
+
+static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC4_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC5_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5;
+}
+
+static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+}
+
+static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
+}
+
+static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
+}
+
+static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+}
+
+static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS;
+}
+
+static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
+}
+
+static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
+}
+
+static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
+}
+
+static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
+}
+
+static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline bool hri_tcc_get_interrupt_MC4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC4_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4;
+}
+
+static inline bool hri_tcc_get_interrupt_MC5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC5_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5;
+}
+
+static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
+{
+	((Tcc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+}
+
+static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
+}
+
+static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
+}
+
+static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
+}
+
+static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
+}
+
+static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask);
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data);
+	((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data);
+}
+
+static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask);
+}
+
+static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data);
+	((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = mask;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->CTRLBSET.reg;
+}
+
+static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = data;
+	((Tcc *)hw)->CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = mask;
+}
+
+static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
+}
+
+static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
+}
+
+static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
+}
+
+static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
+}
+
+static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
+}
+
+static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
+}
+
+static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+}
+
+static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
+}
+
+static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS;
+}
+
+static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS;
+}
+
+static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
+}
+
+static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
+}
+
+static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
+}
+
+static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
+}
+
+static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
+}
+
+static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
+}
+
+static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
+}
+
+static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
+}
+
+static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
+}
+
+static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
+}
+
+static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
+}
+
+static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
+}
+
+static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
+}
+
+static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
+}
+
+static inline void hri_tcc_set_INTEN_MC4_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4;
+}
+
+static inline bool hri_tcc_get_INTEN_MC4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC4) >> TCC_INTENSET_MC4_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC4_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4;
+}
+
+static inline void hri_tcc_set_INTEN_MC5_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5;
+}
+
+static inline bool hri_tcc_get_INTEN_MC5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC5) >> TCC_INTENSET_MC5_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC5_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5;
+}
+
+static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	((Tcc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data)
+{
+	((Tcc *)hw)->INTENSET.reg = data;
+	((Tcc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	((Tcc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC4) >> TCC_SYNCBUSY_CC4_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC5) >> TCC_SYNCBUSY_CC5_Pos;
+}
+
+static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_ENABLE;
+	tmp |= value << TCC_CTRLA_ENABLE_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_RUNSTDBY;
+	tmp |= value << TCC_CTRLA_RUNSTDBY_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_ALOCK;
+	tmp |= value << TCC_CTRLA_ALOCK_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_MSYNC;
+	tmp |= value << TCC_CTRLA_MSYNC_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_DMAOS;
+	tmp |= value << TCC_CTRLA_DMAOS_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN0;
+	tmp |= value << TCC_CTRLA_CPTEN0_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN1;
+	tmp |= value << TCC_CTRLA_CPTEN1_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN2;
+	tmp |= value << TCC_CTRLA_CPTEN2_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN3;
+	tmp |= value << TCC_CTRLA_CPTEN3_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN4) >> TCC_CTRLA_CPTEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN4;
+	tmp |= value << TCC_CTRLA_CPTEN4_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN5) >> TCC_CTRLA_CPTEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN5;
+	tmp |= value << TCC_CTRLA_CPTEN5_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_RESOLUTION_Msk;
+	tmp |= TCC_CTRLA_RESOLUTION(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_PRESCALER_Msk;
+	tmp |= TCC_CTRLA_PRESCALER(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_PRESCSYNC_Msk;
+	tmp |= TCC_CTRLA_PRESCSYNC(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	return ((Tcc *)hw)->CTRLA.reg;
+}
+
+static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_KEEP;
+	tmp |= value << TCC_FCTRLA_KEEP_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_QUAL;
+	tmp |= value << TCC_FCTRLA_QUAL_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_RESTART;
+	tmp |= value << TCC_FCTRLA_RESTART_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANKPRESC;
+	tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_SRC_Msk;
+	tmp |= TCC_FCTRLA_SRC(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANK_Msk;
+	tmp |= TCC_FCTRLA_BLANK(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_HALT_Msk;
+	tmp |= TCC_FCTRLA_HALT(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_CHSEL_Msk;
+	tmp |= TCC_FCTRLA_CHSEL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_CAPTURE_Msk;
+	tmp |= TCC_FCTRLA_CAPTURE(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANKVAL_Msk;
+	tmp |= TCC_FCTRLA_BLANKVAL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_FILTERVAL_Msk;
+	tmp |= TCC_FCTRLA_FILTERVAL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->FCTRLA.reg;
+}
+
+static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_KEEP;
+	tmp |= value << TCC_FCTRLB_KEEP_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_QUAL;
+	tmp |= value << TCC_FCTRLB_QUAL_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_RESTART;
+	tmp |= value << TCC_FCTRLB_RESTART_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANKPRESC;
+	tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_SRC_Msk;
+	tmp |= TCC_FCTRLB_SRC(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANK_Msk;
+	tmp |= TCC_FCTRLB_BLANK(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_HALT_Msk;
+	tmp |= TCC_FCTRLB_HALT(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_CHSEL_Msk;
+	tmp |= TCC_FCTRLB_CHSEL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_CAPTURE_Msk;
+	tmp |= TCC_FCTRLB_CAPTURE(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANKVAL_Msk;
+	tmp |= TCC_FCTRLB_BLANKVAL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_FILTERVAL_Msk;
+	tmp |= TCC_FCTRLB_FILTERVAL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->FCTRLB.reg;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN0;
+	tmp |= value << TCC_WEXCTRL_DTIEN0_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN1;
+	tmp |= value << TCC_WEXCTRL_DTIEN1_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN2;
+	tmp |= value << TCC_WEXCTRL_DTIEN2_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN3;
+	tmp |= value << TCC_WEXCTRL_DTIEN3_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_OTMX_Msk;
+	tmp |= TCC_WEXCTRL_OTMX(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTLS_Msk;
+	tmp |= TCC_WEXCTRL_DTLS(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTHS_Msk;
+	tmp |= TCC_WEXCTRL_DTHS(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->WEXCTRL.reg;
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE0;
+	tmp |= value << TCC_DRVCTRL_NRE0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE1;
+	tmp |= value << TCC_DRVCTRL_NRE1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE2;
+	tmp |= value << TCC_DRVCTRL_NRE2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE3;
+	tmp |= value << TCC_DRVCTRL_NRE3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE4;
+	tmp |= value << TCC_DRVCTRL_NRE4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE5;
+	tmp |= value << TCC_DRVCTRL_NRE5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE6;
+	tmp |= value << TCC_DRVCTRL_NRE6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE7;
+	tmp |= value << TCC_DRVCTRL_NRE7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV0;
+	tmp |= value << TCC_DRVCTRL_NRV0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV1;
+	tmp |= value << TCC_DRVCTRL_NRV1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV2;
+	tmp |= value << TCC_DRVCTRL_NRV2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV3;
+	tmp |= value << TCC_DRVCTRL_NRV3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV4;
+	tmp |= value << TCC_DRVCTRL_NRV4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV5;
+	tmp |= value << TCC_DRVCTRL_NRV5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV6;
+	tmp |= value << TCC_DRVCTRL_NRV6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV7;
+	tmp |= value << TCC_DRVCTRL_NRV7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN0;
+	tmp |= value << TCC_DRVCTRL_INVEN0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN1;
+	tmp |= value << TCC_DRVCTRL_INVEN1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN2;
+	tmp |= value << TCC_DRVCTRL_INVEN2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN3;
+	tmp |= value << TCC_DRVCTRL_INVEN3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN4;
+	tmp |= value << TCC_DRVCTRL_INVEN4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN5;
+	tmp |= value << TCC_DRVCTRL_INVEN5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN6;
+	tmp |= value << TCC_DRVCTRL_INVEN6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN7;
+	tmp |= value << TCC_DRVCTRL_INVEN7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk;
+	tmp |= TCC_DRVCTRL_FILTERVAL0(data);
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk;
+	tmp |= TCC_DRVCTRL_FILTERVAL1(data);
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->DRVCTRL.reg;
+}
+
+static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= ~TCC_DBGCTRL_DBGRUN;
+	tmp |= value << TCC_DBGCTRL_DBGRUN_Pos;
+	((Tcc *)hw)->DBGCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= ~TCC_DBGCTRL_FDDBD;
+	tmp |= value << TCC_DBGCTRL_FDDBD_Pos;
+	((Tcc *)hw)->DBGCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_OVFEO;
+	tmp |= value << TCC_EVCTRL_OVFEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TRGEO;
+	tmp |= value << TCC_EVCTRL_TRGEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_CNTEO;
+	tmp |= value << TCC_EVCTRL_CNTEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCINV0;
+	tmp |= value << TCC_EVCTRL_TCINV0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCINV1;
+	tmp |= value << TCC_EVCTRL_TCINV1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCEI0;
+	tmp |= value << TCC_EVCTRL_TCEI0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCEI1;
+	tmp |= value << TCC_EVCTRL_TCEI1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI0;
+	tmp |= value << TCC_EVCTRL_MCEI0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI1;
+	tmp |= value << TCC_EVCTRL_MCEI1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI2;
+	tmp |= value << TCC_EVCTRL_MCEI2_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI3;
+	tmp |= value << TCC_EVCTRL_MCEI3_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI4) >> TCC_EVCTRL_MCEI4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI4;
+	tmp |= value << TCC_EVCTRL_MCEI4_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI5) >> TCC_EVCTRL_MCEI5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI5;
+	tmp |= value << TCC_EVCTRL_MCEI5_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO0;
+	tmp |= value << TCC_EVCTRL_MCEO0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO1;
+	tmp |= value << TCC_EVCTRL_MCEO1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO2;
+	tmp |= value << TCC_EVCTRL_MCEO2_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO3;
+	tmp |= value << TCC_EVCTRL_MCEO3_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO4) >> TCC_EVCTRL_MCEO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO4;
+	tmp |= value << TCC_EVCTRL_MCEO4_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO5) >> TCC_EVCTRL_MCEO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO5;
+	tmp |= value << TCC_EVCTRL_MCEO5_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_EVACT0_Msk;
+	tmp |= TCC_EVCTRL_EVACT0(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_EVACT1_Msk;
+	tmp |= TCC_EVCTRL_EVACT1(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_CNTSEL_Msk;
+	tmp |= TCC_EVCTRL_CNTSEL(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	return ((Tcc *)hw)->COUNT.reg;
+}
+
+static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE0;
+	tmp |= value << TCC_PATT_PGE0_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE1;
+	tmp |= value << TCC_PATT_PGE1_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE2;
+	tmp |= value << TCC_PATT_PGE2_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE3;
+	tmp |= value << TCC_PATT_PGE3_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE4;
+	tmp |= value << TCC_PATT_PGE4_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE5;
+	tmp |= value << TCC_PATT_PGE5_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE6;
+	tmp |= value << TCC_PATT_PGE6_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE7;
+	tmp |= value << TCC_PATT_PGE7_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV0;
+	tmp |= value << TCC_PATT_PGV0_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV1;
+	tmp |= value << TCC_PATT_PGV1_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV2;
+	tmp |= value << TCC_PATT_PGV2_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV3;
+	tmp |= value << TCC_PATT_PGV3_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV4;
+	tmp |= value << TCC_PATT_PGV4_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV5;
+	tmp |= value << TCC_PATT_PGV5_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV6;
+	tmp |= value << TCC_PATT_PGV6_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV7;
+	tmp |= value << TCC_PATT_PGV7_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->PATT.reg;
+}
+
+static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CIPEREN;
+	tmp |= value << TCC_WAVE_CIPEREN_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN0;
+	tmp |= value << TCC_WAVE_CICCEN0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN1;
+	tmp |= value << TCC_WAVE_CICCEN1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN2;
+	tmp |= value << TCC_WAVE_CICCEN2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN3;
+	tmp |= value << TCC_WAVE_CICCEN3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL0;
+	tmp |= value << TCC_WAVE_POL0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL1;
+	tmp |= value << TCC_WAVE_POL1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL2;
+	tmp |= value << TCC_WAVE_POL2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL3;
+	tmp |= value << TCC_WAVE_POL3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL4) >> TCC_WAVE_POL4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL4;
+	tmp |= value << TCC_WAVE_POL4_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL5) >> TCC_WAVE_POL5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL5;
+	tmp |= value << TCC_WAVE_POL5_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP0;
+	tmp |= value << TCC_WAVE_SWAP0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP1;
+	tmp |= value << TCC_WAVE_SWAP1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP2;
+	tmp |= value << TCC_WAVE_SWAP2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP3;
+	tmp |= value << TCC_WAVE_SWAP3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_WAVEGEN_Msk;
+	tmp |= TCC_WAVE_WAVEGEN(data);
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_RAMP_Msk;
+	tmp |= TCC_WAVE_RAMP(data);
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->WAVE.reg;
+}
+
+static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH4_DITHER_Msk;
+	tmp |= TCC_PER_DITH4_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH5_DITHER_Msk;
+	tmp |= TCC_PER_DITH5_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH6_DITHER_Msk;
+	tmp |= TCC_PER_DITH6_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	return ((Tcc *)hw)->PER.reg;
+}
+
+static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH4_DITHER_Msk;
+	tmp |= TCC_CC_DITH4_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH5_DITHER_Msk;
+	tmp |= TCC_CC_DITH5_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH6_DITHER_Msk;
+	tmp |= TCC_CC_DITH6_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= mask;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg = data;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~mask;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= mask;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	return ((Tcc *)hw)->CC[index].reg;
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB0;
+	tmp |= value << TCC_PATTBUF_PGEB0_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB1;
+	tmp |= value << TCC_PATTBUF_PGEB1_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB2;
+	tmp |= value << TCC_PATTBUF_PGEB2_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB3;
+	tmp |= value << TCC_PATTBUF_PGEB3_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB4;
+	tmp |= value << TCC_PATTBUF_PGEB4_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB5;
+	tmp |= value << TCC_PATTBUF_PGEB5_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB6;
+	tmp |= value << TCC_PATTBUF_PGEB6_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB7;
+	tmp |= value << TCC_PATTBUF_PGEB7_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB0;
+	tmp |= value << TCC_PATTBUF_PGVB0_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB1;
+	tmp |= value << TCC_PATTBUF_PGVB1_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB2;
+	tmp |= value << TCC_PATTBUF_PGVB2_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB3;
+	tmp |= value << TCC_PATTBUF_PGVB3_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB4;
+	tmp |= value << TCC_PATTBUF_PGVB4_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB5;
+	tmp |= value << TCC_PATTBUF_PGVB5_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB6;
+	tmp |= value << TCC_PATTBUF_PGVB6_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB7;
+	tmp |= value << TCC_PATTBUF_PGVB7_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PATTBUF.reg;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH4_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH5_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH6_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PERBUF.reg;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH5_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH6_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH4_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                             hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CCBUF[index].reg;
+}
+
+static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV4) >> TCC_STATUS_CCBUFV4_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV5) >> TCC_STATUS_CCBUFV5_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP4) >> TCC_STATUS_CMP4_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP5) >> TCC_STATUS_CMP5_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->STATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TCC_D51_H_INCLUDED */
+#endif /* _SAMD51_TCC_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_trng_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_trng_d51.h
new file mode 100644
index 0000000..0643419
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_trng_d51.h
@@ -0,0 +1,380 @@
+/**
+ * \file
+ *
+ * \brief SAM TRNG
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_TRNG_COMPONENT_
+#ifndef _HRI_TRNG_D51_H_INCLUDED_
+#define _HRI_TRNG_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TRNG_CRITICAL_SECTIONS)
+#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TRNG_CRITICAL_SECTION_ENTER()
+#define TRNG_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_trng_data_reg_t;
+typedef uint8_t  hri_trng_ctrla_reg_t;
+typedef uint8_t  hri_trng_evctrl_reg_t;
+typedef uint8_t  hri_trng_intenset_reg_t;
+typedef uint8_t  hri_trng_intflag_reg_t;
+
+static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos;
+}
+
+static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
+}
+
+static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos;
+}
+
+static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
+}
+
+static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Trng *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask)
+{
+	((Trng *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY;
+}
+
+static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos;
+}
+
+static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY;
+	} else {
+		((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY;
+	}
+}
+
+static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY;
+}
+
+static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	((Trng *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw)
+{
+	return ((Trng *)hw)->INTENSET.reg;
+}
+
+static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data)
+{
+	((Trng *)hw)->INTENSET.reg = data;
+	((Trng *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	((Trng *)hw)->INTENCLR.reg = mask;
+}
+
+static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask)
+{
+	return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos;
+}
+
+static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw)
+{
+	return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos;
+}
+
+static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Trng *)hw)->DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw)
+{
+	return ((Trng *)hw)->DATA.reg;
+}
+
+static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= ~TRNG_CTRLA_ENABLE;
+	tmp |= value << TRNG_CTRLA_ENABLE_Pos;
+	((Trng *)hw)->CTRLA.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= ~TRNG_CTRLA_RUNSTDBY;
+	tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos;
+	((Trng *)hw)->CTRLA.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg = data;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw)
+{
+	return ((Trng *)hw)->CTRLA.reg;
+}
+
+static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp &= ~TRNG_EVCTRL_DATARDYEO;
+	tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos;
+	((Trng *)hw)->EVCTRL.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg |= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg = data;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg &= ~mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg ^= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Trng *)hw)->EVCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TRNG_D51_H_INCLUDED */
+#endif /* _SAMD51_TRNG_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_usb_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_usb_d51.h
new file mode 100644
index 0000000..47739ce
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_usb_d51.h
@@ -0,0 +1,9335 @@
+/**
+ * \file
+ *
+ * \brief SAM USB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_USB_COMPONENT_
+#ifndef _HRI_USB_D51_H_INCLUDED_
+#define _HRI_USB_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_USB_CRITICAL_SECTIONS)
+#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define USB_CRITICAL_SECTION_ENTER()
+#define USB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_usb_padcal_reg_t;
+typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t;
+typedef uint16_t hri_usbdesc_bank_extreg_reg_t;
+typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t;
+typedef uint16_t hri_usbdescriptordevice_extreg_reg_t;
+typedef uint16_t hri_usbdescriptorhost_ctrl_pipe_reg_t;
+typedef uint16_t hri_usbdescriptorhost_extreg_reg_t;
+typedef uint16_t hri_usbdescriptorhost_status_pipe_reg_t;
+typedef uint16_t hri_usbdevice_ctrlb_reg_t;
+typedef uint16_t hri_usbdevice_epintsmry_reg_t;
+typedef uint16_t hri_usbdevice_fnum_reg_t;
+typedef uint16_t hri_usbdevice_intenset_reg_t;
+typedef uint16_t hri_usbdevice_intflag_reg_t;
+typedef uint16_t hri_usbhost_ctrlb_reg_t;
+typedef uint16_t hri_usbhost_fnum_reg_t;
+typedef uint16_t hri_usbhost_intenset_reg_t;
+typedef uint16_t hri_usbhost_intflag_reg_t;
+typedef uint16_t hri_usbhost_pintsmry_reg_t;
+typedef uint32_t hri_usb_descadd_reg_t;
+typedef uint32_t hri_usbdesc_bank_addr_reg_t;
+typedef uint32_t hri_usbdesc_bank_pcksize_reg_t;
+typedef uint32_t hri_usbdescriptordevice_addr_reg_t;
+typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t;
+typedef uint32_t hri_usbdescriptorhost_addr_reg_t;
+typedef uint32_t hri_usbdescriptorhost_pcksize_reg_t;
+typedef uint8_t  hri_usb_ctrla_reg_t;
+typedef uint8_t  hri_usb_fsmstatus_reg_t;
+typedef uint8_t  hri_usb_qosctrl_reg_t;
+typedef uint8_t  hri_usb_syncbusy_reg_t;
+typedef uint8_t  hri_usbdesc_bank_status_bk_reg_t;
+typedef uint8_t  hri_usbdescriptordevice_status_bk_reg_t;
+typedef uint8_t  hri_usbdescriptorhost_status_bk_reg_t;
+typedef uint8_t  hri_usbdevice_dadd_reg_t;
+typedef uint8_t  hri_usbdevice_epcfg_reg_t;
+typedef uint8_t  hri_usbdevice_epintenset_reg_t;
+typedef uint8_t  hri_usbdevice_epintflag_reg_t;
+typedef uint8_t  hri_usbdevice_epstatus_reg_t;
+typedef uint8_t  hri_usbdevice_status_reg_t;
+typedef uint8_t  hri_usbendpoint_epcfg_reg_t;
+typedef uint8_t  hri_usbendpoint_epintenset_reg_t;
+typedef uint8_t  hri_usbendpoint_epintflag_reg_t;
+typedef uint8_t  hri_usbendpoint_epstatus_reg_t;
+typedef uint8_t  hri_usbhost_binterval_reg_t;
+typedef uint8_t  hri_usbhost_flenhigh_reg_t;
+typedef uint8_t  hri_usbhost_hsofc_reg_t;
+typedef uint8_t  hri_usbhost_pcfg_reg_t;
+typedef uint8_t  hri_usbhost_pintenset_reg_t;
+typedef uint8_t  hri_usbhost_pintflag_reg_t;
+typedef uint8_t  hri_usbhost_pstatus_reg_t;
+typedef uint8_t  hri_usbhost_status_reg_t;
+typedef uint8_t  hri_usbpipe_binterval_reg_t;
+typedef uint8_t  hri_usbpipe_pcfg_reg_t;
+typedef uint8_t  hri_usbpipe_pintenset_reg_t;
+typedef uint8_t  hri_usbpipe_pintflag_reg_t;
+typedef uint8_t  hri_usbpipe_pstatus_reg_t;
+
+static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg)
+{
+	while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg)
+{
+	return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                      hri_usbpipe_pintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbpipe_pintflag_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL)
+	       >> USB_HOST_PSTATUS_DTGL_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK)
+	       >> USB_HOST_PSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE)
+	       >> USB_HOST_PSTATUS_PFREEZE_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY)
+	       >> USB_HOST_PSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY)
+	       >> USB_HOST_PSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbpipe_pstatus_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask;
+}
+
+static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbpipe_pstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_pstatus_reg_t data)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data;
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_pstatus_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0)
+	       >> USB_HOST_PINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1)
+	       >> USB_HOST_PINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL)
+	       >> USB_HOST_PINTENSET_TRFAIL_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR)
+	       >> USB_HOST_PINTENSET_PERR_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP)
+	       >> USB_HOST_PINTENSET_TXSTP_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL)
+	       >> USB_HOST_PINTENSET_STALL_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbpipe_pintenset_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask;
+}
+
+static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbpipe_pintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg;
+}
+
+static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbpipe_pintenset_reg_t data)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data;
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbpipe_pintenset_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask;
+}
+
+static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_BK;
+	tmp |= value << USB_HOST_PCFG_BK_Pos;
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbpipe_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTOKEN_Msk;
+	tmp |= USB_HOST_PCFG_PTOKEN(data);
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbpipe_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTYPE_Msk;
+	tmp |= USB_HOST_PCFG_PTYPE(data);
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbpipe_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbpipe_pcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+}
+
+static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                   uint8_t           submodule_index,
+                                                                                   hri_usbpipe_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbpipe_binterval_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk;
+	tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data);
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                    uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbpipe_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_binterval_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                      hri_usbhost_pintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbhost_pintflag_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask;
+}
+
+static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL)
+	       >> USB_HOST_PSTATUS_DTGL_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK)
+	       >> USB_HOST_PSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE)
+	       >> USB_HOST_PSTATUS_PFREEZE_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY)
+	       >> USB_HOST_PSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY)
+	       >> USB_HOST_PSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbhost_pstatus_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask;
+}
+
+static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbhost_pstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg;
+}
+
+static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_pstatus_reg_t data)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data;
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_pstatus_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0)
+	       >> USB_HOST_PINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1)
+	       >> USB_HOST_PINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL)
+	       >> USB_HOST_PINTENSET_TRFAIL_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR)
+	       >> USB_HOST_PINTENSET_PERR_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP)
+	       >> USB_HOST_PINTENSET_TXSTP_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL)
+	       >> USB_HOST_PINTENSET_STALL_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_pintenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask;
+}
+
+static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbhost_pintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg;
+}
+
+static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbhost_pintenset_reg_t data)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data;
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbhost_pintenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask;
+}
+
+static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_BK;
+	tmp |= value << USB_HOST_PCFG_BK_Pos;
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbhost_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTOKEN_Msk;
+	tmp |= USB_HOST_PCFG_PTOKEN(data);
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbhost_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTYPE_Msk;
+	tmp |= USB_HOST_PCFG_PTYPE(data);
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_pcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+}
+
+static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                   uint8_t           submodule_index,
+                                                                                   hri_usbhost_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_binterval_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk;
+	tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data);
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                    uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbhost_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_binterval_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+}
+
+static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const           hw,
+                                                                               hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp &= ~USB_HOST_ADDR_ADDR_Msk;
+	tmp |= USB_HOST_ADDR_ADDR(data);
+	((UsbHostDescBank *)hw)->ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const           hw,
+                                                                           hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->ADDR.reg;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                 hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                   hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data);
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                   hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                    hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                        hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                          hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                          hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                           hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_SIZE(data);
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const              hw,
+                                                                                 hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+}
+
+static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                                     hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_SUBPID_Msk;
+	tmp |= USB_HOST_EXTREG_SUBPID(data);
+	((UsbHostDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t
+hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk;
+	tmp |= USB_HOST_EXTREG_VARIABLE(data);
+	((UsbHostDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const             hw,
+                                                                               hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->EXTREG.reg;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                               hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PDADDR(data);
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                                  hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                               hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data);
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                                  hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                               hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PERMAX(data);
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                                  hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t
+hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->STATUS_BK.reg;
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER)
+	       >> USB_HOST_STATUS_PIPE_DAPIDER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER)
+	       >> USB_HOST_STATUS_PIPE_CRC16ER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t
+hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask))
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const                  hw,
+                                                                  hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk)
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t
+hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const                  hw,
+                                                             hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_addr_reg_t
+hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                       hri_usbdescriptorhost_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptorhost_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp &= ~USB_HOST_ADDR_ADDR_Msk;
+	tmp |= USB_HOST_ADDR_ADDR(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw,
+                                                                                       uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_addr_reg_t
+hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, hri_usbdescriptorhost_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptorhost_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw,
+                                                                                   uint8_t           submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index,
+                                                                    bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptorhost_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                          hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbdescriptorhost_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                             uint8_t           submodule_index,
+                                                                             hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                          hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptorhost_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_SIZE(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                      hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptorhost_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw,
+                                                                                         uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t
+hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                           hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptorhost_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_SUBPID_Msk;
+	tmp |= USB_HOST_EXTREG_SUBPID(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t
+hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                             hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptorhost_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk;
+	tmp |= USB_HOST_EXTREG_VARIABLE(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw,
+                                                                                               uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t
+hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                     hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptorhost_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw,
+                                                                                       uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                              hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PDADDR(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                              hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                              hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PERMAX(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_ctrl_pipe_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR)
+	       >> USB_HOST_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW)
+	       >> USB_HOST_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_bk_reg_t
+hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbdescriptorhost_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg;
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER)
+	       >> USB_HOST_STATUS_PIPE_DTGLER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER)
+	       >> USB_HOST_STATUS_PIPE_DAPIDER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER)
+	       >> USB_HOST_STATUS_PIPE_PIDER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER)
+	       >> USB_HOST_STATUS_PIPE_TOUTER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER)
+	       >> USB_HOST_STATUS_PIPE_CRC16ER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_pipe_reg_t
+hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdescriptorhost_status_pipe_reg_t mask)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask))
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptorhost_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_pipe_reg_t
+hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk)
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline hri_usbdescriptorhost_status_pipe_reg_t
+hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                          hri_usbdescriptorhost_status_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptorhost_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_pipe_reg_t
+hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline hri_usbendpoint_epintflag_reg_t
+hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw,
+                                                                                 uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                       hri_usbendpoint_epintflag_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT)
+	       >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN)
+	       >> USB_DEVICE_EPSTATUS_DTGLIN_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK)
+	       >> USB_DEVICE_EPSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index,
+                                                               bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index,
+                                                               bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY)
+	       >> USB_DEVICE_EPSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY)
+	       >> USB_DEVICE_EPSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbendpoint_epstatus_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask;
+}
+
+static inline hri_usbendpoint_epstatus_reg_t
+hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbendpoint_epstatus_reg_t data)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbendpoint_epstatus_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0)
+	       >> USB_DEVICE_EPINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1)
+	       >> USB_DEVICE_EPINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP)
+	       >> USB_DEVICE_EPINTENSET_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0)
+	       >> USB_DEVICE_EPINTENSET_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1)
+	       >> USB_DEVICE_EPINTENSET_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epintenset_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask;
+}
+
+static inline hri_usbendpoint_epintenset_reg_t
+hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbendpoint_epintenset_reg_t data)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbendpoint_epintenset_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_NYETDIS;
+	tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t
+hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE0(data);
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t
+hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE1(data);
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline hri_usbdevice_epintflag_reg_t
+hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw,
+                                                                             uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbdevice_epintflag_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT)
+	       >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN)
+	       >> USB_DEVICE_EPSTATUS_DTGLIN_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK)
+	       >> USB_DEVICE_EPSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY)
+	       >> USB_DEVICE_EPSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY)
+	       >> USB_DEVICE_EPSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_epstatus_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask;
+}
+
+static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                          hri_usbdevice_epstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw,
+                                                                           uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbdevice_epstatus_reg_t data)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbdevice_epstatus_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0)
+	       >> USB_DEVICE_EPINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1)
+	       >> USB_DEVICE_EPINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP)
+	       >> USB_DEVICE_EPINTENSET_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0)
+	       >> USB_DEVICE_EPINTENSET_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1)
+	       >> USB_DEVICE_EPINTENSET_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epintenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask;
+}
+
+static inline hri_usbdevice_epintenset_reg_t
+hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbdevice_epintenset_reg_t data)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbdevice_epintenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_NYETDIS;
+	tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t
+hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE0(data);
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t
+hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE1(data);
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF;
+}
+
+static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+}
+
+static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+}
+
+static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM;
+}
+
+static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP;
+}
+
+static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const           hw,
+                                                                        hri_usbdevice_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.INTFLAG.reg;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = mask;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+}
+
+static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+}
+
+static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+}
+
+static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+}
+
+static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+}
+
+static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+}
+
+static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_usbhost_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.INTFLAG.reg;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = mask;
+}
+
+static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND;
+}
+
+static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF;
+}
+
+static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF;
+}
+
+static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF;
+}
+
+static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF;
+}
+
+static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST;
+}
+
+static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST;
+}
+
+static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP;
+}
+
+static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM;
+}
+
+static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM;
+}
+
+static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM;
+}
+
+static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER;
+}
+
+static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET;
+}
+
+static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP;
+}
+
+static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP;
+}
+
+static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = mask;
+}
+
+static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const            hw,
+                                                                       hri_usbdevice_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.INTENSET.reg;
+}
+
+static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = data;
+	((Usb *)hw)->DEVICE.INTENCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = mask;
+}
+
+static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+}
+
+static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF;
+}
+
+static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+}
+
+static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST;
+}
+
+static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+}
+
+static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP;
+}
+
+static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+}
+
+static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM;
+}
+
+static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+}
+
+static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM;
+}
+
+static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+}
+
+static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER;
+}
+
+static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+}
+
+static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN;
+}
+
+static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+}
+
+static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC;
+}
+
+static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = mask;
+}
+
+static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const          hw,
+                                                                   hri_usbhost_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.INTENSET.reg;
+}
+
+static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = data;
+	((Usb *)hw)->HOST.INTENCLR.reg = ~data;
+}
+
+static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = mask;
+}
+
+static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.SYNCBUSY.reg;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const          hw,
+                                                                           hri_usbdevice_status_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const          hw,
+                                                                               hri_usbdevice_status_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const          hw,
+                                                                      hri_usbdevice_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.STATUS.reg;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const       hw,
+                                                                        hri_usb_fsmstatus_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.FSMSTATUS.reg;
+}
+
+static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const        hw,
+                                                                       hri_usbdevice_fnum_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const        hw,
+                                                                      hri_usbdevice_fnum_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.FNUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.FNUM.reg;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const          hw,
+                                                                              hri_usbhost_flenhigh_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const          hw,
+                                                                      hri_usbhost_flenhigh_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.FLENHIGH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.FLENHIGH.reg;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos;
+}
+
+static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const             hw,
+                                                                            hri_usbdevice_epintsmry_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.EPINTSMRY.reg;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos;
+}
+
+static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const          hw,
+                                                                      hri_usbhost_pintsmry_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PINTSMRY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.PINTSMRY.reg;
+}
+
+static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= ~USB_CTRLA_ENABLE;
+	tmp |= value << USB_CTRLA_ENABLE_Pos;
+	((Usb *)hw)->HOST.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= ~USB_CTRLA_RUNSTDBY;
+	tmp |= value << USB_CTRLA_RUNSTDBY_Pos;
+	((Usb *)hw)->HOST.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= ~USB_CTRLA_MODE;
+	tmp |= value << USB_CTRLA_MODE_Pos;
+	((Usb *)hw)->HOST.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg = data;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw)
+{
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	return ((Usb *)hw)->HOST.CTRLA.reg;
+}
+
+static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_CQOS_Msk;
+	tmp |= USB_QOSCTRL_CQOS(data);
+	((Usb *)hw)->HOST.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_DQOS_Msk;
+	tmp |= USB_QOSCTRL_DQOS(data);
+	((Usb *)hw)->HOST.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.QOSCTRL.reg;
+}
+
+static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_DETACH;
+	tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_UPRSM;
+	tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_NREPLY;
+	tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTJ;
+	tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTK;
+	tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTPCKT;
+	tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_OPMODE2;
+	tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_GNAK;
+	tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const         hw,
+                                                                           hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk;
+	tmp |= USB_DEVICE_CTRLB_SPDCONF(data);
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const         hw,
+                                                                           hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk;
+	tmp |= USB_DEVICE_CTRLB_LPMHDSK(data);
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const         hw,
+                                                                    hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.CTRLB.reg;
+}
+
+static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_RESUME;
+	tmp |= value << USB_HOST_CTRLB_RESUME_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_AUTORESUME;
+	tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_TSTJ;
+	tmp |= value << USB_HOST_CTRLB_TSTJ_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_TSTK;
+	tmp |= value << USB_HOST_CTRLB_TSTK_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_SOFE;
+	tmp |= value << USB_HOST_CTRLB_SOFE_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_BUSRESET;
+	tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_VBUSOK;
+	tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_L1RESUME;
+	tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const       hw,
+                                                                       hri_usbhost_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk;
+	tmp |= USB_HOST_CTRLB_SPDCONF(data);
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.CTRLB.reg;
+}
+
+static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= ~USB_DEVICE_DADD_ADDEN;
+	tmp |= value << USB_DEVICE_DADD_ADDEN_Pos;
+	((Usb *)hw)->DEVICE.DADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const        hw,
+                                                                      hri_usbdevice_dadd_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= ~USB_DEVICE_DADD_DADD_Msk;
+	tmp |= USB_DEVICE_DADD_DADD(data);
+	((Usb *)hw)->DEVICE.DADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.DADD.reg;
+}
+
+static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp &= ~USB_HOST_HSOFC_FLENCE;
+	tmp |= value << USB_HOST_HSOFC_FLENCE_Pos;
+	((Usb *)hw)->HOST.HSOFC.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp &= ~USB_HOST_HSOFC_FLENC_Msk;
+	tmp |= USB_HOST_HSOFC_FLENC(data);
+	((Usb *)hw)->HOST.HSOFC.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.HSOFC.reg;
+}
+
+static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp &= ~USB_HOST_FNUM_MFNUM_Msk;
+	tmp |= USB_HOST_FNUM_MFNUM(data);
+	((Usb *)hw)->HOST.FNUM.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp &= ~USB_HOST_FNUM_FNUM_Msk;
+	tmp |= USB_HOST_FNUM_FNUM(data);
+	((Usb *)hw)->HOST.FNUM.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.FNUM.reg;
+}
+
+static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp &= ~USB_DESCADD_DESCADD_Msk;
+	tmp |= USB_DESCADD_DESCADD(data);
+	((Usb *)hw)->HOST.DESCADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.DESCADD.reg;
+}
+
+static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSP_Msk;
+	tmp |= USB_PADCAL_TRANSP(data);
+	((Usb *)hw)->HOST.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSN_Msk;
+	tmp |= USB_PADCAL_TRANSN(data);
+	((Usb *)hw)->HOST.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRIM_Msk;
+	tmp |= USB_PADCAL_TRIM(data);
+	((Usb *)hw)->HOST.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.PADCAL.reg;
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const        hw,
+                                                                       hri_usbhost_status_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos;
+}
+
+static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const        hw,
+                                                                           hri_usbhost_status_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos;
+}
+
+static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.STATUS.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.STATUS.reg;
+}
+
+static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const           hw,
+                                                                                 hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp &= ~USB_DEVICE_ADDR_ADDR_Msk;
+	tmp |= USB_DEVICE_ADDR_ADDR(data);
+	((UsbDeviceDescBank *)hw)->ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const           hw,
+                                                                             hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->ADDR.reg;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                   hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                     hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                     hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                      hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                          hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                            hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                            hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                             hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                               hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_SIZE(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                               hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                                hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const              hw,
+                                                                                   hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+}
+
+static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t
+hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk;
+	tmp |= USB_DEVICE_EXTREG_SUBPID(data);
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t
+hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                  hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk;
+	tmp |= USB_DEVICE_EXTREG_VARIABLE(data);
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                  hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                   hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const             hw,
+                                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+}
+
+static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+	       >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t
+hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const                hw,
+                                                             hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t
+hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                         hri_usbdescriptordevice_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp &= ~USB_DEVICE_ADDR_ADDR_Msk;
+	tmp |= USB_DEVICE_ADDR_ADDR(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw,
+                                                                                           uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t
+hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                     hri_usbdescriptordevice_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw,
+                                                                                       uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index,
+                                                                      bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void
+hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void
+hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void
+hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_SIZE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                             hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk;
+	tmp |= USB_DEVICE_EXTREG_SUBPID(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptordevice_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk;
+	tmp |= USB_DEVICE_EXTREG_VARIABLE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                       hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw,
+                                                                                           uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+}
+
+static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR)
+	       >> USB_DEVICE_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+	       >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_status_bk_reg_t
+hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                          hri_usbdescriptordevice_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_status_bk_reg_t
+hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b)
+#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b)
+#define hri_usbhost_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b)
+#define hri_usbhost_is_syncing(a, b) hri_usb_is_syncing(a, b)
+#define hri_usbhost_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a)
+#define hri_usbhost_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a)
+#define hri_usbhost_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a)
+#define hri_usbhost_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a)
+#define hri_usbhost_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b)
+#define hri_usbhost_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a)
+#define hri_usbhost_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a)
+#define hri_usbhost_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbhost_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbhost_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b)
+#define hri_usbhost_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbhost_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a)
+#define hri_usbhost_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a)
+#define hri_usbhost_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b)
+#define hri_usbhost_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a)
+#define hri_usbhost_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a)
+#define hri_usbhost_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b)
+#define hri_usbhost_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b)
+#define hri_usbhost_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b)
+#define hri_usbhost_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b)
+#define hri_usbhost_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b)
+#define hri_usbhost_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a)
+#define hri_usbhost_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a)
+#define hri_usbhost_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a)
+#define hri_usbhost_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b)
+#define hri_usbhost_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b)
+#define hri_usbhost_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b)
+#define hri_usbhost_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b)
+#define hri_usbhost_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b)
+#define hri_usbhost_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a)
+#define hri_usbhost_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a)
+#define hri_usbhost_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b)
+#define hri_usbhost_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b)
+#define hri_usbhost_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b)
+#define hri_usbhost_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b)
+#define hri_usbhost_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b)
+#define hri_usbhost_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a)
+#define hri_usbhost_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a)
+#define hri_usbhost_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a)
+#define hri_usbhost_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a)
+#define hri_usbhost_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b)
+#define hri_usbhost_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b)
+#define hri_usbhost_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b)
+#define hri_usbhost_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b)
+#define hri_usbhost_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b)
+#define hri_usbhost_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a)
+#define hri_usbhost_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a)
+#define hri_usbhost_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a)
+#define hri_usbhost_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b)
+#define hri_usbhost_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a)
+#define hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b)
+#define hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a)
+#define hri_usbhost_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b)
+#define hri_usbhost_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a)
+#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a)
+#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a)
+#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a)
+#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a)
+#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a)
+#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a)
+#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b)
+#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b)
+#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b)
+#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b)
+#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b)
+#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a)
+#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a)
+#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a)
+#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b)
+#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b)
+#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b)
+#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b)
+#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a)
+#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a)
+#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b)
+#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b)
+#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b)
+#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b)
+#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b)
+#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a)
+#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a)
+#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a)
+#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a)
+#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b)
+#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b)
+#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b)
+#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b)
+#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b)
+#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a)
+#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a)
+#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a)
+#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b)
+#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a)
+#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b)
+#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a)
+#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b)
+#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_USB_D51_H_INCLUDED */
+#endif /* _SAMD51_USB_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_wdt_d51.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_wdt_d51.h
new file mode 100644
index 0000000..647acef
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hri/hri_wdt_d51.h
@@ -0,0 +1,617 @@
+/**
+ * \file
+ *
+ * \brief SAM WDT
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAMD51_WDT_COMPONENT_
+#ifndef _HRI_WDT_D51_H_INCLUDED_
+#define _HRI_WDT_D51_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_WDT_CRITICAL_SECTIONS)
+#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define WDT_CRITICAL_SECTION_ENTER()
+#define WDT_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_wdt_syncbusy_reg_t;
+typedef uint8_t  hri_wdt_clear_reg_t;
+typedef uint8_t  hri_wdt_config_reg_t;
+typedef uint8_t  hri_wdt_ctrla_reg_t;
+typedef uint8_t  hri_wdt_ewctrl_reg_t;
+typedef uint8_t  hri_wdt_intenset_reg_t;
+typedef uint8_t  hri_wdt_intflag_reg_t;
+
+static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg)
+{
+	while (((Wdt *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg)
+{
+	return ((Wdt *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
+}
+
+static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
+}
+
+static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
+{
+	((Wdt *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
+}
+
+static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos;
+}
+
+static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
+	} else {
+		((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
+	}
+}
+
+static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
+}
+
+static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	((Wdt *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->INTENSET.reg;
+}
+
+static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data)
+{
+	((Wdt *)hw)->INTENSET.reg = data;
+	((Wdt *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	((Wdt *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos;
+}
+
+static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Wdt *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_ENABLE;
+	tmp |= value << WDT_CTRLA_ENABLE_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_WEN;
+	tmp |= value << WDT_CTRLA_WEN_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_ALWAYSON;
+	tmp |= value << WDT_CTRLA_ALWAYSON_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg = data;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw)
+{
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	return ((Wdt *)hw)->CTRLA.reg;
+}
+
+static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= ~WDT_CONFIG_PER_Msk;
+	tmp |= WDT_CONFIG_PER(data);
+	((Wdt *)hw)->CONFIG.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= ~WDT_CONFIG_WINDOW_Msk;
+	tmp |= WDT_CONFIG_WINDOW(data);
+	((Wdt *)hw)->CONFIG.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->CONFIG.reg;
+}
+
+static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp &= ~WDT_EWCTRL_EWOFFSET_Msk;
+	tmp |= WDT_EWCTRL_EWOFFSET(data);
+	((Wdt *)hw)->EWCTRL.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->EWCTRL.reg;
+}
+
+static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CLEAR.reg = data;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_WDT_D51_H_INCLUDED */
+#endif /* _SAMD51_WDT_COMPONENT_ */
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/interrupts.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/interrupts.h
new file mode 100644
index 0000000..4bdcbc8
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/interrupts.h
@@ -0,0 +1,156 @@
+/*
+ * interrupts.h
+ *
+ * Created: 02/08/2021 21:54:14
+ *  Author: Nick-XMG
+ */ 
+
+
+#ifndef INTERRUPTS_H_
+#define INTERRUPTS_H_
+
+#include "configuration.h"
+#include "ADS1299.h"
+
+/* TC0 - Interrupt Handler 
+* Configured to trigger @ 1ms
+*/
+void TC0_Handler( void ){
+	if (TC0->COUNT8.INTFLAG.bit.OVF && TC0->COUNT8.INTENSET.bit.OVF)             
+	{
+		TC0->COUNT8.INTFLAG.bit.OVF = 0x01;
+		if ((ecat_state == wait2)|(ecat_state == wait))
+		{
+			ecat_state= write_fifo;
+			run_ECAT =true;
+		}
+		Motor1.timerflags.motor_telemetry_flag = true;
+	}	
+	if (TC0->COUNT8.INTFLAG.bit.MC0 && TC0->COUNT8.INTENSET.bit.MC0)
+	{
+		TC0->COUNT8.INTFLAG.bit.MC0 = 0x01;
+	}
+	if (TC0->COUNT8.INTFLAG.bit.MC1 && TC0->COUNT8.INTENSET.bit.MC1)
+	{
+		TC0->COUNT8.INTFLAG.bit.MC1 = 0x01;
+		//DMAC->Channel[7].CHCTRLB.bit.CMD = 0x02;
+		
+	}
+}
+
+//static void One_ms_cycle_callback(const struct timer_task *const timer_task)
+//{
+	//if ((ecat_state == wait2)|(ecat_state == wait)) 
+	//{
+		//ecat_state= write_fifo;
+		//run_ECAT =true;
+	//}
+	//Motor1.timerflags.motor_telemetry_flag = true;
+	//Motor2.timerflags.motor_telemetry_flag = true;
+	//
+	//
+	///*Master Slave Transfer */
+	////tx_buffer[0] += 1;
+	////tx_buffer[31] += 1;
+	////gpio_set_pin_level(SPI1_CS, false);
+	////spi_m_dma_transfer(&SPI_1_MSIF, (uint8_t*)Slave_1.tx_buffer, (uint8_t*)Slave_1.rx_buffer, MASTER_BUFFER_SIZE);
+	//
+	////run_ECAT = true;
+//}
+
+
+// ----------------------------------------------------------------------
+// 	Master/Slave IF Callback
+// ----------------------------------------------------------------------
+static void	b2bTransferComplete_cb(struct _dma_resource *resource)
+{
+	
+	//PORT->Group[1].OUTSET.reg = (1<<GPIO_PIN(SPI1_CS));
+	//volatile int x = 0;
+	//PORT->Group[GPIO_PORTB].OUTCLR.reg = (1<<Slave_1->SS_pin);
+	//gpio_set_pin_level(SPI1_CS, true);
+	volatile int x = 0;
+}
+
+
+
+// ----------------------------------------------------------------------
+// 	ADC Callback for Motor Phase Current Measurement.
+// Phase A & B Sampled and converted from LSB to Process Unit PU(Amps)
+// ----------------------------------------------------------------------
+static void pwm_cb(const struct pwm_descriptor *const descr)
+{
+	volatile int x = 0;
+}
+
+static void adc_sram_dma_callback(struct _dma_resource *adc_dma_res)
+{
+	Motor1.timerflags.adc_readings_ready_tic = true;
+	Motor2.timerflags.adc_readings_ready_tic = true;
+}
+
+// ----------------------------------------------------------------------
+// 	Speed Counter TC2 Overflow handler
+// ----------------------------------------------------------------------
+void TC2_Handler(void)
+{
+	if (TC2->COUNT32.INTFLAG.bit.OVF == 0x01) {
+		TC2->COUNT32.INTFLAG.bit.OVF = 0x01;
+		Motor1.motor_status.calc_rpm = 0;
+	}
+}
+
+// ----------------------------------------------------------------------
+//	Speed Counter TC2 Overflow handler
+// ----------------------------------------------------------------------
+void TC4_Handler(void)
+{
+	if (TC4->COUNT32.INTFLAG.bit.OVF == 0x01) {
+		TC4->COUNT32.INTFLAG.bit.OVF = 0x01;
+		Motor2.motor_status.calc_rpm = 0;	
+	}
+}
+
+// ----------------------------------------------------------------------
+//	BLDC Driver External Interrupt Handlers
+// ----------------------------------------------------------------------
+static void M1_RESET_BAR(void)
+{
+	volatile int x = 0;
+	Motor1.motor_state.currentstate = MOTOR_FAULT;
+	Motor1.motor_state.fault = MOTOR_DRIVER_OVER_CURRENT;
+}
+
+static void M2_RESET_BAR(void)
+{
+	volatile int x = 0;
+	Motor2.motor_state.currentstate = MOTOR_FAULT;
+	Motor2.motor_state.fault = MOTOR_DRIVER_OVER_CURRENT;
+}
+
+// ----------------------------------------------------------------------
+//	ADS Data Ready Interrupt
+// ----------------------------------------------------------------------
+void ADS1299_dataReadyISR(void)
+{
+	
+	ADS1299.data_ReadyFlag = true;
+	//int32_t* temp =  ADS1299_UPDATECHANNELDATA();
+	volatile int x = 1;
+}
+
+void ADS1299_Transfer_Complete_cb(void)
+{
+	//PORT->Group[0].OUTSET.reg = (1<<GPIO_PIN(SPI2_SS));
+	volatile int x = 1;
+}
+
+void ADS1299_Transfer_error_cb(void)
+{
+	//SERCOM2->SPI.STATUS.bit.BUFOVF = 1;
+	//PORT->Group[0].OUTSET.reg = (1<<GPIO_PIN(SPI2_SS));
+	volatile int x = 1;
+}
+
+
+#endif /* INTERRUPTS_H_ */
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/main.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/main.c
new file mode 100644
index 0000000..442b0b3
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/main.c
@@ -0,0 +1,291 @@
+#include <atmel_start.h>
+
+// ----------------------------------------------------------------------
+// Header Files
+// ----------------------------------------------------------------------
+
+
+#include "EtherCAT_QSPI.h"
+
+//#include "MSIF_master.h"
+
+#include "configuration.h"
+#include "interrupts.h"
+#include "bldc.h"
+#include "bldc_types.h"
+#include "EtherCAT_SlaveDef.h"
+#include "statemachine.h"
+
+
+#include "angle_sensors.h"
+#include "ADS1299.h"
+
+
+
+void process_currents()
+{
+	Motor1.timerflags.adc_readings_ready_tic = false;
+	Motor2.timerflags.adc_readings_ready_tic = false;
+		
+	//////tic_port(DEBUG_2_PORT);
+	volatile int16_t phase_A_current_raw, phase_B_current_raw;
+	
+	/* Motor 1 */
+	phase_A_current_raw = (adc1_res[0] - Motor1.Voffset_lsb.A);
+	phase_B_current_raw = (adc1_res[1] - Motor1.Voffset_lsb.B)*-1;
+	// Covert from LSB to PU (A) and filter out small readings
+	Motor1.Iphase_pu.A = phase_A_current_raw * LSB_TO_PU;
+	Motor1.Iphase_pu.B = phase_B_current_raw * LSB_TO_PU;
+	// i_c = -i_a - i_b because i_a + i_b + i_c = 0
+	Motor1.Iphase_pu.C = -Motor1.Iphase_pu.A - Motor1.Iphase_pu.B;
+	
+	/* Motor 2 negative is A instead of B*/ 
+	phase_A_current_raw = (adc1_res[2] - Motor2.Voffset_lsb.A);
+	phase_B_current_raw = (adc1_res[3] - Motor2.Voffset_lsb.B)*-1;
+	// Covert from LSB to PU (A) and filter out small readings
+	Motor2.Iphase_pu.A = phase_A_current_raw * LSB_TO_PU;
+	Motor2.Iphase_pu.B = phase_B_current_raw * LSB_TO_PU;
+	// i_c = -i_a - i_b because i_a + i_b + i_c = 0
+	Motor2.Iphase_pu.C = -Motor2.Iphase_pu.A - Motor2.Iphase_pu.B;
+	
+	// Set Current Loop Flag
+	Motor1.timerflags.current_loop_tic = true;
+	Motor2.timerflags.current_loop_tic = true;
+}
+
+
+
+void enable_NVIC_IRQ(void)
+{
+	
+	//ext_irq_register(M1_RST_Bar, M1_RESET_BAR);
+	//ext_irq_register(M2_RST_Bar, M2_RESET_BAR);
+	//NVIC_EnableIRQ(TC2_IRQn);	 // TC2: M1_Speed_Timer
+	//NVIC_EnableIRQ(TC4_IRQn);	 // TC4: M2_Speed_Timer
+	NVIC_EnableIRQ(DMAC_0_IRQn);
+	NVIC_EnableIRQ(DMAC_1_IRQn);
+	NVIC_EnableIRQ(DMAC_2_IRQn);
+	NVIC_EnableIRQ(DMAC_3_IRQn);
+	NVIC_EnableIRQ(DMAC_4_IRQn);
+	NVIC_SetPriority(DMAC_0_IRQn, 2);
+	NVIC_SetPriority(ADC1_0_IRQn, 3);
+	NVIC_EnableIRQ(TCC0_0_IRQn);
+	//NVIC_EnableIRQ(TCC1_0_IRQn);
+	NVIC_EnableIRQ(EIC_2_IRQn);
+	         
+	NVIC_EnableIRQ(SERCOM1_1_IRQn);
+	NVIC_EnableIRQ(SERCOM2_1_IRQn);
+	//NVIC_SetPriority(SERCOM1_1_IRQn, 1);
+	NVIC_EnableIRQ(TC0_IRQn);
+	//NVIC_EnableIRQ(TC0_IRQn);
+	//NVIC_SetPriority(EIC_2_IRQn, 3);
+	//NVIC_SetPriority(TCC0_0_IRQn, 3);
+	//NVIC_EnableIRQ(EIC_5_IRQn);
+	
+	
+	
+	/* Reset Latch Interrupt */
+	ext_irq_register(PIN_PB30, M1_RESET_BAR);
+	ext_irq_register(PIN_PB31, M2_RESET_BAR);
+	NVIC_EnableIRQ(EIC_14_IRQn);
+	NVIC_EnableIRQ(EIC_15_IRQn);
+}
+
+void APPLICATION_StateMachine(void)
+{
+	//Motor1.timerflags.current_loop_tic = false;
+	
+	if (applicationStatus.fault)
+	{
+		applicationStatus.previousstate = applicationStatus.currentstate;
+		applicationStatus.currentstate = APP_FAULT;
+	}
+	
+	switch(applicationStatus.currentstate)            /* process current motor state*/
+	{
+		case SYSTEM_INIT:
+			/* Toggle driver reset Latch */
+			gpio_set_pin_level(M1_RST, true);
+			gpio_set_pin_level(M1_RST, false);
+			gpio_set_pin_level(M2_RST, true);
+			gpio_set_pin_level(M2_RST, false);
+			/* Update State Variables */
+			applicationStatus.previousstate = applicationStatus.currentstate;
+			applicationStatus.currentstate = SYSTEM_IDLE;
+		break;
+		case SYSTEM_IDLE:
+			applicationStatus.previousstate = applicationStatus.currentstate;
+			applicationStatus.currentstate = MOTORS_ON;
+		break;
+		case MOTORS_ON:
+			applicationStatus.previousstate = applicationStatus.currentstate;
+			//applicationStatus.currentstate ;
+			motor_StateMachine(&Motor1);
+			motor_StateMachine(&Motor2);
+		break;
+		case APP_FAULT:
+			//DisableGateDrivers(&Motor1);
+			switch(applicationStatus.fault)
+			{
+				case APP_NOFAULT:
+				break;
+				case ECAT_FAULT:
+				break;
+				case MASTER_SLAVE_IF_FAULT:
+				break;
+				case SPI_POS_SENSOR_FAULT:
+				break;
+				case EMG_INTERFACE_FAULT:
+				break;
+				default: break;
+			}// End switch(switch(applicationStatus.fault))
+		case COMMSTEST:
+			comms_check();
+		break;
+		default: break;
+	} // End switch(applicationStatus.currentstate)
+} // inline void CONTROLLER_StateMachine(void)
+
+int main(void)
+{
+	/* Initializes MCU, drivers and middleware */
+	atmel_start_init();
+	__disable_irq();
+		
+	/* BLDC INIT */
+	BldcInitStruct(&Motor1, &FH_22mm24BXTR);
+	BldcInitStruct(&Motor2, &FH_32mm12BXTR);
+	//Motor2.VdcBus_pu = 12.0;
+	//Motor2.VoneByDcBus_pu = 1.0/Motor2.VdcBus_pu;
+	Motor1.readHall = &readHallSensorM1;
+	Motor2.readHall = &readHallSensorM2;
+	
+	/* Current Offeset Calibration */
+	read_zero_current_offset_value(&Motor1, &Motor2);
+	
+	/* Configure Hardware */
+	config_qspi();
+	configure_tcc_pwm();
+	adc_sync_enable_channel(&ADC_1, 6);
+	
+	/* SPI Config */ 
+	boardToBoardTransferInit();
+	/* DMA Configs */
+	init_dma();
+	
+	/* ECAT State Machine First run */
+	ECAT_STATE_MACHINE();
+		
+	//angle_sensor_init();
+	initialize_ads();
+	/* External IRQ Config */
+	custom_logic_enable();
+	
+	__enable_irq();
+	ADS1299_START();
+	delay_us(20);
+	/* ADS Result Ready Interrupt, active low */
+	
+	/* Enable Reception 
+	* Enable RX channels at startup,  Linked to itself so never ends
+	*/
+	_dma_enable_transaction(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, false);
+	_dma_enable_transaction(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, false);
+	
+	/* Clear Exint Flag */
+	EIC->INTFLAG.bit.EXTINT = (1<<2);
+	
+	//ext_irq_register(GPIO_PIN(ADS_DATA_RDY), ADS1299_dataReadyISR);
+	enable_NVIC_IRQ();
+	
+	
+	/* Replace with your application code */
+	while (1) {
+		if (Motor1.timerflags.adc_readings_ready_tic) {process_currents();}
+			
+		if (Motor1.timerflags.motor_telemetry_flag) {
+			
+			Motor1.timerflags.motor_telemetry_flag = false;	
+
+			//DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+			if (DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLA.bit.ENABLE)
+				{
+				/* Resume */
+					//DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLB.bit.CMD = 0x02;
+					volatile int x = 0;
+				}
+			else {
+			/* Enable */
+					DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;	
+			}			
+					
+			update_telemetry();
+			update_setpoints();
+				
+			//PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
+
+			//_dma_enable_transaction(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, false);
+			//_dma_enable_transaction(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, false);
+			
+			volatile int16_t* angles = 0;
+			//angles = read_angle();
+			//Motor1.motor_status.abs_position = degrees(angles[0]);
+			//Motor2.motor_status.abs_position = degrees(angles[1]);		
+			
+			////field = ang_sense_read(AS_CMD_MAGNITUDE);
+			//*Spare1_tx = (field[0] & AS_MASK);
+			//*Spare2_tx = (field[1] & AS_MASK);
+			//temp =  ang_sense_read(AS_CMD_TEMP);
+			//*Spare3_tx = (int16_t)(((float)(temp[0] & AS_MASK) / 8.0) -  273.15);
+			//*Spare4_tx = (int16_t)(((float)(temp[1] & AS_MASK) / 8.0) -  273.15);
+
+		}
+		
+		if (Motor1.timerflags.current_loop_tic) {
+				Motor1.timerflags.current_loop_tic = false;
+				APPLICATION_StateMachine();
+				exec_commutation(&Motor1);
+				exec_commutation(&Motor2);
+		}
+		
+		if (DMAC->Channel[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL].CHCTRLA.bit.ENABLE)
+			{
+			/* Resume */
+				//DMAC->Channel[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL].CHCTRLB.bit.CMD = 0x02;
+				volatile int x = 0;
+			} else {
+				DMAC->Channel[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+			/* Enable */
+			//DMAC->Channel[8].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+				
+		}		
+		
+		if (ADS1299.data_ReadyFlag){
+			ADS1299.data_ReadyFlag = false;
+			//PORT->Group[0].OUTCLR.reg = (1<<GPIO_PIN(SPI2_SS));
+			
+			if (DMAC->Channel[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL].CHCTRLA.bit.ENABLE)
+			{
+			/* Resume */
+				//DMAC->Channel[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL].CHCTRLB.bit.CMD = 0x02;
+				volatile int x = 0;
+			} else {
+				DMAC->Channel[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+			/* Enable */
+			//DMAC->Channel[8].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+				
+			}		
+			
+			//_dma_enable_transaction(2, false);
+			//_dma_enable_transaction(8, false);
+					
+			
+			//ADS1299_UPDATECHANNELDATA();
+		}
+
+		if (run_ECAT) {ECAT_STATE_MACHINE();}	
+		
+	}
+}
+
+
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/motorparameters.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/motorparameters.h
new file mode 100644
index 0000000..9fe285d
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/motorparameters.h
@@ -0,0 +1,211 @@
+/*
+ * motorparameters.h
+ *
+ * Created: 04/08/2021 21:23:43
+ *  Author: Nick-XMG
+ */ 
+
+
+#ifndef MOTORPARAMETERS_H_
+#define MOTORPARAMETERS_H_
+#include "atmel_start.h"
+#include "control.h"
+
+// ----------------------------------------------------------------------
+// 	M1 Hall Parameters
+// ----------------------------------------------------------------------
+
+#define M1_HALL_A_PIN					GPIO(GPIO_PORTA, 4)
+#define M1_HALL_A_PORT					PORT_PA04
+#define M1_HALL_A_MASK					~(1<<2)
+#define M1_HALL_A_LSR					M1_HALL_A_PIN	- M1_HALL_A_GROUP*32 -2
+#define M1_HALL_A_GROUP					M1_HALL_A_PIN/32
+
+#define M1_HALL_B_PIN					GPIO(GPIO_PORTA, 5)
+#define M1_HALL_B_PORT					PORT_PA05
+#define M1_HALL_B_MASK					~(1<<1)
+#define M1_HALL_B_LSR					M1_HALL_B_PIN	- M1_HALL_B_GROUP*32 -1
+#define M1_HALL_B_GROUP					M1_HALL_B_PIN/32
+
+#define M1_HALL_C_PIN					GPIO(GPIO_PORTA, 6)
+#define M1_HALL_C_PORT					PORT_PA06
+#define M1_HALL_C_MASK					~(1<<0)
+#define M1_HALL_C_LSR					M1_HALL_C_PIN	- M1_HALL_C_GROUP*32 -0
+#define M1_HALL_C_GROUP					M1_HALL_C_PIN/32
+
+// ----------------------------------------------------------------------
+// 	M2 Hall Parameters
+// ----------------------------------------------------------------------
+
+#define M2_HALL_A_PIN					GPIO(GPIO_PORTA, 22)
+#define M2_HALL_A_PORT					PORT_PA22
+#define M2_HALL_A_MASK					~(1<<2)
+#define M2_HALL_A_LSR					M2_HALL_A_PIN	- M2_HALL_A_GROUP*32 -2
+#define M2_HALL_A_GROUP					M2_HALL_A_PIN/32
+
+#define M2_HALL_B_PIN					GPIO(GPIO_PORTA, 23)
+#define M2_HALL_B_PORT					PORT_PA23
+#define M2_HALL_B_MASK					~(1<<1)
+#define M2_HALL_B_LSR					M2_HALL_B_PIN	- M2_HALL_B_GROUP*32 -1
+#define M2_HALL_B_GROUP					M2_HALL_B_PIN/32
+
+#define M2_HALL_C_PIN					GPIO(GPIO_PORTA, 24)
+#define M2_HALL_C_PORT					PORT_PA24
+#define M2_HALL_C_MASK					~(1<<0)
+#define M2_HALL_C_LSR					M2_HALL_C_PIN	- M2_HALL_C_GROUP*32 -0
+#define M2_HALL_C_GROUP					M2_HALL_C_PIN/32
+
+
+
+/* ----------------------------------------------------------------------
+// Commutation Patterns
+// ----------------------------------------------------------------------
+/**
+**	____|___TCC0_____OTMX ||____TCC1____ OTMX|
+**	W0	|	M1_0	| CC0 ||    M2_0   | CC0 |
+**	W1	|	M1_0	| CC0 ||	M2_0   | CC0 |
+**	W2	|	M1_0	| CC0 ||	M2_0   | CC0 |
+**	W3	|	M1_0	| CC0 ||	M2_0   | CC0 |
+**	W4	|   M1_0	| CC0 ||	M2_0   | CC0 |
+**	W5	|   M1_0	| CC0 ||	M2_0   | CC0 |
+**	W6	|	M1_0	| CC0 ||	M2_0   | CC0 |
+**	W7  |	M1_0	| CC0 ||	M2_0   | CC0 |
+*/
+
+#define DISABLE_PATTERN		0x003F
+
+//////* A&C phase swapped */
+//static const uint16_t COMMUTATION_PATTERN[16] = {
+	//0x003F,		// (0) invalid state
+	//0x1437,					// (1)
+	//0x053D,					// (2)
+	//0x113D,					// (3)
+	//0x111F,					// (4)
+	//0x0537,					// (5)
+	//0x141F,					// (6)
+	//0x003F,		// (7) invalid state
+	//0x003F,		// (8) invalid state
+	//0x141F,					// (9)
+	//0x0537,					// (10)
+	//0x111F,					// (11)
+	//0x113D,					// (12)
+	//0x053D,					// (13)
+	//0x1437,					// (14)
+	//0x003F,			// (15) invalid state
+//};
+
+////* A&C phase swapped and modified to match currents */
+static const uint16_t COMMUTATION_PATTERN[16] = {
+	0x003F,		// (0) invalid state
+	0x141F,		// (1)
+	0x0537,		// (2)
+	0x111F,		// (3)
+	0x113D,		// (4)
+	0x053D,		// (5)
+	0x1437,		// (6)
+	0x003F,		// (7) invalid state
+	0x003F,		// (8) invalid state
+	0x1437,		// (9)
+	0x053D,		// (10)
+	0x113D,		// (11)
+	0x111F,		// (12)
+	0x0537,		// (13)
+	0x141F,		// (14)
+	0x003F		// (15) invalid state
+};
+
+// ----------------------------------------------------------------------
+// 	Motor Physical Parameters
+// ----------------------------------------------------------------------
+typedef struct
+{
+	const uint16_t motor_Poles;          
+	const uint16_t motor_polePairs;
+	const uint16_t motor_commutationStates;
+	const float32_t motor_RS_Ohm;
+	const float32_t motor_LD_H;
+	const float32_t motor_LQ_H;
+	const float32_t motor_Flux_WB;
+	const float32_t motor_Max_Spd_RPM;
+	const float32_t motor_MeasureRange_RPM;	// give 20% headroom
+	const float32_t motor_Max_Spd_ELEC;
+	const float32_t motor_Max_Current_IDC_A;
+	MOTOR_Control_Structs controller_param;
+	float32_t motor_MaxPWM;
+} BLDCMotor_param_t;
+
+//static BLDCMotor_param_t FH_22mm24BXTR;
+//static BLDCMotor_param_t FH_32mm24BXTR;
+
+/* Small Motor - 2214S024BXTR*/
+const static BLDCMotor_param_t FH_22mm24BXTR = {
+	.motor_Poles			       = 14,
+	.motor_polePairs		       = 7,
+	.motor_commutationStates       = 42,			 //polePairs * 6
+	.motor_RS_Ohm			       = 25.9,
+	.motor_LD_H				       = 0.003150,
+	.motor_LQ_H				       = 0.003150,
+	.motor_Flux_WB			       = 0.001575,
+	.motor_Max_Spd_RPM		       = 2000,
+	.motor_MeasureRange_RPM	       = 3000 * 1.2,	//(1.2f * MOTOR_MAX_SPD_RPM)f   // give 20% headroom
+	.motor_Max_Spd_ELEC			   = (3000/60)*7.0,		//(MOTOR_MAX_SPD_RPM/60)*MOTOR_POLEPAIRS
+	//.motor_Max_Current_IDC_A	   = 0.368,
+	.motor_Max_Current_IDC_A	   = 0.180,
+	.controller_param.Pid_Speed.Kp = 0.00004f,
+	.controller_param.Pid_Speed.Ki = 0.0000001f,
+	//.controller_param.Pid_Speed.Ki = 0.0000001f,
+	.controller_param.Pi_Pos.Kp	   = 30.0f,
+	.controller_param.Pi_Pos.Ki	   = 0.0f,
+	.motor_MaxPWM = 600.0,
+};
+
+
+/* Big Motor - 3216W012BXTR */
+const static BLDCMotor_param_t FH_32mm12BXTR = {
+	.motor_Poles				   = 14,
+	.motor_polePairs			   = 7,
+	.motor_commutationStates	   = 42,			 //polePairs * 6
+	.motor_RS_Ohm				   = 0.88,
+	.motor_LD_H					   = 0.000331,
+	.motor_LQ_H					   = 0.000331,
+	.motor_Flux_WB				   = 0.0063879968,
+	.motor_Max_Spd_RPM			   = 2000,
+	.motor_MeasureRange_RPM		   = 3200,		//(1.2f * MOTOR_MAX_SPD_RPM)f   // give 20% headroom
+	.motor_Max_Spd_ELEC			   = 12000,		//(MOTOR_MAX_SPD_RPM/60)*MOTOR_POLEPAIRS
+	.motor_Max_Current_IDC_A	   = (1.2),
+	.controller_param.Pid_Speed.Kp = 0.0003f,
+	.controller_param.Pid_Speed.Ki = 0.0000001f,
+	.controller_param.Pi_Pos.Kp	   = 30.0f,
+	.controller_param.Pi_Pos.Ki	   = 0.000f,
+	//.controller_param.Pid_Speed.Kp = 0.00002f,
+	//.controller_param.Pid_Speed.Ki = 0.0f,
+	//.controller_param.Pi_Pos.Kp	   = 4.0f,
+	//.controller_param.Pi_Pos.Ki	   = 0.0f,
+	.motor_MaxPWM = 250.0,
+};
+
+/* Big Motor - 3216W024BXTR */
+const static BLDCMotor_param_t FH_32mm24BXTR = {
+	.motor_Poles				   = 14,
+	.motor_polePairs			   = 7,
+	.motor_commutationStates	   = 42,			 //polePairs * 6
+	.motor_RS_Ohm				   = 3.37,
+	.motor_LD_H					   = 0.001290,
+	.motor_LQ_H					   = 0.001290,
+	.motor_Flux_WB				   = 0.0063879968,
+	.motor_Max_Spd_RPM			   = 3000,
+	.motor_MeasureRange_RPM		   = 3200,		//(1.2f * MOTOR_MAX_SPD_RPM)f   // give 20% headroom
+	.motor_Max_Spd_ELEC			   = 12000,		//(MOTOR_MAX_SPD_RPM/60)*MOTOR_POLEPAIRS
+	.motor_Max_Current_IDC_A	   = 1.0,
+	.controller_param.Pid_Speed.Kp = 0.0002f,
+	.controller_param.Pid_Speed.Ki = 0.0000001f,
+	.controller_param.Pi_Pos.Kp	   = 40.0f,
+	.controller_param.Pi_Pos.Ki	   = 0.0f,
+	.motor_MaxPWM = 800.0,
+	//.controller_param.Pid_Speed.Kp = 0.00002f,
+	//.controller_param.Pid_Speed.Ki = 0.0f,
+	//.controller_param.Pi_Pos.Kp	   = 4.0f,
+	//.controller_param.Pi_Pos.Ki	   = 0.0f,
+};
+
+#endif /* MOTORPARAMETERS_H_ */
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/statemachine.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/statemachine.h
new file mode 100644
index 0000000..7cfc98d
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/statemachine.h
@@ -0,0 +1,76 @@
+/*
+ * statemachine.h
+ *
+ * Created: 05/04/2021 13:23:24
+ *  Author: Nick-XMG
+ */ 
+
+
+#ifndef STATEMACHINE_H_
+#define STATEMACHINE_H_
+
+// ----------------------------------------------------------------------
+// 	Application States
+// ----------------------------------------------------------------------
+typedef enum
+{
+	SYSTEM_INIT			  = 0,
+	SYSTEM_IDLE			  = 1,
+	MOTORS_ON			  = 2,
+	APP_FAULT			  = 3,
+	COMMSTEST			  = 4,
+} APPLICATION_FSM_t;
+
+typedef enum
+{
+	APP_NOFAULT			  = 0,
+	ECAT_FAULT			  = 1,
+	MASTER_SLAVE_IF_FAULT = 2,
+	SPI_POS_SENSOR_FAULT  = 3,
+	EMG_INTERFACE_FAULT   = 4,
+	APP_MOTORFAULT	      = 5,
+} APP_FAULTS_t;
+
+typedef struct APPLICATION_STATE
+{
+	volatile APPLICATION_FSM_t currentstate;
+	volatile APPLICATION_FSM_t previousstate;
+	volatile APP_FAULTS_t fault;
+} APPLICATION_STATE_t;
+
+volatile APPLICATION_STATE_t applicationStatus;
+
+// ----------------------------------------------------------------------
+// Motor States
+// ----------------------------------------------------------------------
+typedef enum
+{
+	MOTOR_INIT			  = 0,
+	MOTOR_IDLE			  = 1,
+	MOTOR_OPEN_LOOP_STATE = 2,
+	MOTOR_I_CTRL_STATE    = 3,
+	MOTOR_V_CTRL_STATE    = 4,
+	MOTOR_P_CTRL_STATE    = 5,
+	MOTOR_VI_CTRL_STATE   = 6,
+	MOTOR_PVI_CTRL_STATE  = 7,
+	MOTOR_STOP			  = 8,
+	MOTOR_FAULT			  = 9,	
+} MOTOR_FSM_t;
+
+typedef enum
+{
+	MOTOR_NOFAULT			  = 0x0E,
+	MOTOR_HALLSENSORINVALID	  = 0xE1,
+	MOTOR_DRIVER_OVER_CURRENT = 0xE2,
+	MOTOR_CURRENTS_SENSOR	  = 0xE3,
+} MOTOR_FAULTS_t;
+
+typedef struct MOTOR_STATE
+{
+	volatile MOTOR_FSM_t currentstate;
+	volatile MOTOR_FSM_t previousstate;
+	volatile MOTOR_FAULTS_t fault;
+} MOTOR_STATE_t;
+
+
+#endif /* STATEMACHINE_H_ */
\ No newline at end of file
diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/utilities.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/utilities.h
new file mode 100644
index 0000000..aac75bf
--- /dev/null
+++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/utilities.h
@@ -0,0 +1,181 @@
+/*
+ * utilities.h
+ *
+ * Created: 20/04/2021 19:59:00
+ *  Author: Nick-XMG
+ */ 
+
+
+#ifndef UTILITIES_H_
+#define UTILITIES_H_
+
+
+#define ENABLED(V...)       DO(ENA,&&,V)
+#define DISABLED(V...)      DO(DIS,&&,V)
+#include "arm_math.h"
+
+#define DEBUG_1_PORT PORT_PC01
+#define DEBUG_2_PORT PORT_PC03
+#define DEBUG_3_PORT PORT_PC02
+#define DEBUG_4_PORT PORT_PC30
+
+static inline void tic(const uint8_t pin)
+{
+	gpio_set_pin_level(pin, true);
+}
+
+static inline void toc(const uint8_t pin)
+{
+	gpio_set_pin_level(pin, false);
+}
+
+static inline void tic_port(const uint32_t port)
+{
+	REG_PORT_OUTSET2 = port;
+}
+
+static inline void toc_port(const uint32_t port)
+{
+	REG_PORT_OUTCLR2 = port;
+}
+
+//! \brief     Saturates the input value between the minimum and maximum values
+//! \param[in] in   The input value
+//! \param[in] max  The maximum value allowed
+//! \param[in] min  The minimum value allowed
+//! \return    The saturated value
+static inline uint16_t u_clamp(const int16_t in, const uint16_t min, const uint16_t max)
+{
+	uint16_t out = abs(in);
+
+	if(in < min)
+	{
+		out = min;
+	}
+	else if(in > max)
+	{
+		out = max;
+	}
+	else
+	{
+		// do nothing as of now
+		;
+	}
+
+	return(out);
+}
+
+//! \brief     Saturates the input value between the minimum and maximum values
+//! \param[in] in   The input value
+//! \param[in] max  The maximum value allowed
+//! \param[in] min  The minimum value allowed
+//! \return    The saturated value
+static inline float32_t f_clamp(const float32_t in, const float32_t min, const float32_t max)
+{
+	float32_t out = in;
+
+
+	if(in < min)
+	{
+		out = min;
+	}
+	else if(in > max)
+	{
+		out = max;
+	}
+	else
+	{
+		// do nothing as of now
+		;
+	}
+
+	return(out);
+}
+
+//! \brief     Finds the absolute value
+//! \param[in] in   The input value
+//! \return    The absolute value
+static inline float32_t f_abs(const float32_t in)
+{
+	float32_t out = in;
+	if(in < (float32_t)0.0)
+	{
+		out = -in;
+	}
+
+	return(out);
+} 
+
+// the typedefs
+
+//! \brief Defines the first-order filter (FILTER_FO) object
+//!
+typedef struct _FILTER_FO_Obj_
+{
+	float32_t  a1;  //the denominator filter coefficient value for z^(-1)
+
+	float32_t  b0;  //the numerator filter coefficient value for z^0
+	float32_t  b1;  //the numerator filter coefficient value for z^(-1)
+
+	float32_t  x1;  //the input value at time sample n=-1
+
+	float32_t  y1;  //the output value at time sample n=-1
+} FILTER_FO_Obj;
+
+
+//! \brief     Runs a first-order filter of the form
+//!            y[n] = b0*x[n] + b1*x[n-1] - a1*y[n-1]
+//!
+//! \param[in] handle      The filter handle
+//! \param[in] inputValue  The input value to filter
+//! \return    The output value from the filter
+
+static inline float32_t FILTER_FO_run(volatile FILTER_FO_Obj *handle, const float32_t inputValue)
+{
+	FILTER_FO_Obj *obj = (FILTER_FO_Obj *)handle;
+
+	float32_t a1 = obj->a1;
+	float32_t b0 = obj->b0;
+	float32_t b1 = obj->b1;
+	float32_t x1 = obj->x1;
+	float32_t y1 = obj->y1;
+
+
+	// compute the output
+	float32_t y0 = (b0 * inputValue) + (b1 * x1) - (a1 * y1);
+
+
+	// store values for next time
+	obj->x1 = inputValue;
+	obj->y1 = y0;
+
+	return(y0);
+} // end of FILTER_FO_run() function
+
+
+//! \brief     Runs a first-order filter of the form
+//!            y[n] = b0*x[n] - a1*y[n-1]
+//!
+//! \param[in] handle      The filter handle
+//! \param[in] inputValue  The input value to filter
+//! \return    The output value from the filter
+static inline float32_t FILTER_FO_run_form_0(volatile FILTER_FO_Obj *handle, const float32_t inputValue)
+{
+	FILTER_FO_Obj *obj = (FILTER_FO_Obj *)handle;
+
+	float32_t a1 = obj->a1;
+	float32_t b0 = obj->b0;
+	float32_t y1 = obj->y1;
+
+
+	// compute the output
+	float32_t y0 = (b0 * inputValue) - (a1 * y1);
+
+
+	// store values for next time
+	obj->y1 = y0;
+
+	return(y0);
+} // end of FILTER_FO_run_form_0() function
+
+#endif /* UTILITIES_H_ */
\ No newline at end of file
diff --git a/Twincat/MotorData/.vs/MotorData/v15/.suo b/Twincat/MotorData/.vs/MotorData/v15/.suo
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