From a5a470eac52fc262bfbe52404cfa6fec7775b72c Mon Sep 17 00:00:00 2001 From: Nicolas Trimborn Date: Tue, 7 Sep 2021 17:28:15 +0200 Subject: [PATCH] modified more locations with preprocessor directives --- .../Two_Motor_D51/Two_Motor_D51/MSIF_slave.h | 22 +- .../Two_Motor_D51/Two_Motor_D51.cproj | 492 +++++++++--------- .../Two_Motor_D51/configuration.h | 255 +++++---- .../Two_Motor_D51/Two_Motor_D51/main.c | 1 - 4 files changed, 405 insertions(+), 365 deletions(-) diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/MSIF_slave.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/MSIF_slave.h index a81bf72..8dbc2c7 100644 --- a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/MSIF_slave.h +++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/MSIF_slave.h @@ -9,6 +9,8 @@ #ifndef MASTER_SLAVE_IF_H_ #define MASTER_SLAVE_IF_H_ +#include "bldc.h" + #define SLAVE_BUFFER_SIZE_BYTES 64 #define SLAVE_BUFFER_SIZE_LONG SLAVE_BUFFER_SIZE_BYTES/4 @@ -61,24 +63,24 @@ static volatile int16_t *Pressure_CH3 = (((int16_t *)&SPI_tx_buffer[15])+1); //rx_buffer ///* Motor 3*/ static volatile uint8_t *M3_Control_mode = (uint8_t *)&SPI_rx_buffer[0]; //1 byte - 0 of 32 -static volatile uint8_t *M3_Control_set = (((uint8_t *)&SPI_rx_buffer[0])+1); //1 byte - 1 of 32 -static volatile int16_t *M3_Desired_pos = ((int16_t *)&SPI_rx_buffer[0]+1); //2 byte - 2 of 32 +static volatile uint8_t *M3_Control_set = (((uint8_t *)&SPI_rx_buffer[0])+1); //1 byte - 1 of 32 +static volatile int16_t *M3_Desired_pos = ((int16_t *)&SPI_rx_buffer[0]+1); //2 byte - 2 of 32 static volatile int16_t *M3_Desired_speed = (int16_t *)&SPI_rx_buffer[1]; //2 byte - 4 of 32 -static volatile int16_t *M3_Desired_current = ((int16_t *)&SPI_rx_buffer[1]+1); //2 byte - 6 of 32 +static volatile int16_t *M3_Desired_current = ((int16_t *)&SPI_rx_buffer[1]+1); //2 byte - 6 of 32 static volatile int16_t *M3_Max_pos = (int16_t *)&SPI_rx_buffer[2]; //2 byte - 8 of 32 -static volatile int16_t *M3_Max_velocity = ((int16_t *)&SPI_rx_buffer[2]+1); //2 byte - 10 of 32 +static volatile int16_t *M3_Max_velocity = ((int16_t *)&SPI_rx_buffer[2]+1); //2 byte - 10 of 32 static volatile int16_t *M3_Max_current = (int16_t *)&SPI_rx_buffer[3]; //2 byte - 12 of 32 -static volatile int16_t *M3_Spare = ((int16_t *)&SPI_rx_buffer[3]+1); //2 byte - 14 of 32 +static volatile int16_t *M3_Spare = ((int16_t *)&SPI_rx_buffer[3]+1); //2 byte - 14 of 32 ///* Motor 4*/ static volatile uint8_t *M4_Control_mode = (uint8_t *)&SPI_rx_buffer[4]; //1 byte - 16 of 32 -static volatile uint8_t *M4_Control_set = (((uint8_t *)&SPI_rx_buffer[4])+1); //1 byte - 17 of 32 -static volatile int16_t *M4_Desired_pos = ((int16_t *)&SPI_rx_buffer[4]+1); //2 byte - 18 of 32 +static volatile uint8_t *M4_Control_set = (((uint8_t *)&SPI_rx_buffer[4])+1); //1 byte - 17 of 32 +static volatile int16_t *M4_Desired_pos = ((int16_t *)&SPI_rx_buffer[4]+1); //2 byte - 18 of 32 static volatile int16_t *M4_Desired_speed = (int16_t *)&SPI_rx_buffer[5]; //2 byte - 20 of 32 -static volatile int16_t *M4_Desired_current = ((int16_t *)&SPI_rx_buffer[5]+1); //2 byte - 22 of 32 +static volatile int16_t *M4_Desired_current = ((int16_t *)&SPI_rx_buffer[5]+1); //2 byte - 22 of 32 static volatile int16_t *M4_Max_pos = (int16_t *)&SPI_rx_buffer[6]; //2 byte - 24 of 32 -static volatile int16_t *M4_Max_velocity = ((int16_t *)&SPI_rx_buffer[6]+1); //2 byte - 26 of 32 +static volatile int16_t *M4_Max_velocity = ((int16_t *)&SPI_rx_buffer[6]+1); //2 byte - 26 of 32 static volatile int16_t *M4_Max_current = (int16_t *)&SPI_rx_buffer[7]; //2 byte - 28 of 32 -static volatile int16_t *M4_Spare = ((int16_t *)&SPI_rx_buffer[7]+1); //2 byte - 30 of 32 +static volatile int16_t *M4_Spare = ((int16_t *)&SPI_rx_buffer[7]+1); //2 byte - 30 of 32 ////tx_buffer diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.cproj b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.cproj index 6c68523..7a21197 100644 --- a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.cproj +++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.cproj @@ -245,256 +245,258 @@ - True - True - True - True - True - - - NDEBUG - - - - - %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ - ../Config - ../ - ../examples - ../hal/include - ../hal/utils/include - ../hpl/adc - ../hpl/ccl - ../hpl/cmcc - ../hpl/core - ../hpl/dmac - ../hpl/eic - ../hpl/evsys - ../hpl/gclk - ../hpl/mclk - ../hpl/osc32kctrl - ../hpl/oscctrl - ../hpl/pm - ../hpl/port - ../hpl/qspi - ../hpl/ramecc - ../hpl/sercom - ../hpl/tc - ../hpl/tcc - ../hri - %24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include - - - Optimize for size (-Os) - True - True - -std=gnu99 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 - True - - - libm - libarm_cortexM4lf_math.a - - - - - C:\Users\ge37vez\Documents\Git Repos\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master_D51\Two_Motor_D51\Two_Motor_D51\cmsis - %24(ProjectDir)\Device_Startup - - - True - -Tsamd51j18a_flash.ld - - - %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ - ../Config - ../ - ../examples - ../hal/include - ../hal/utils/include - ../hpl/adc - ../hpl/ccl - ../hpl/cmcc - ../hpl/core - ../hpl/dmac - ../hpl/eic - ../hpl/evsys - ../hpl/gclk - ../hpl/mclk - ../hpl/osc32kctrl - ../hpl/oscctrl - ../hpl/pm - ../hpl/port - ../hpl/qspi - ../hpl/ramecc - ../hpl/sercom - ../hpl/tc - ../hpl/tcc - ../hri - %24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include - - - - - %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ - ../Config - ../ - ../examples - ../hal/include - ../hal/utils/include - ../hpl/adc - ../hpl/ccl - ../hpl/cmcc - ../hpl/core - ../hpl/dmac - ../hpl/eic - ../hpl/evsys - ../hpl/gclk - ../hpl/mclk - ../hpl/osc32kctrl - ../hpl/oscctrl - ../hpl/pm - ../hpl/port - ../hpl/qspi - ../hpl/ramecc - ../hpl/sercom - ../hpl/tc - ../hpl/tcc - ../hri - %24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include - - - + True + True + True + True + True + + + NDEBUG + + + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/adc + ../hpl/ccl + ../hpl/cmcc + ../hpl/core + ../hpl/dmac + ../hpl/eic + ../hpl/evsys + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/qspi + ../hpl/ramecc + ../hpl/sercom + ../hpl/tc + ../hpl/tcc + ../hri + %24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include + + + Optimize for size (-Os) + True + True + -std=gnu99 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 + True + + + libm + libarm_cortexM4lf_math.a + + + + + C:\Users\ge37vez\Documents\Git Repos\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master_D51\Two_Motor_D51\Two_Motor_D51\cmsis + %24(ProjectDir)\Device_Startup + C:\Users\trim_ni\Documents\Git\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master_D51\Two_Motor_D51\Two_Motor_D51\cmsis + + + True + -Tsamd51j18a_flash.ld + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/adc + ../hpl/ccl + ../hpl/cmcc + ../hpl/core + ../hpl/dmac + ../hpl/eic + ../hpl/evsys + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/qspi + ../hpl/ramecc + ../hpl/sercom + ../hpl/tc + ../hpl/tcc + ../hri + %24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include + + + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/adc + ../hpl/ccl + ../hpl/cmcc + ../hpl/core + ../hpl/dmac + ../hpl/eic + ../hpl/evsys + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/qspi + ../hpl/ramecc + ../hpl/sercom + ../hpl/tc + ../hpl/tcc + ../hri + %24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include + + + - True - True - True - True - True - - - DEBUG - ARM_MATH_CM4=1 - - - - - %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ - ../Config - ../ - ../examples - ../hal/include - ../hal/utils/include - ../hpl/adc - ../hpl/ccl - ../hpl/cmcc - ../hpl/core - ../hpl/dmac - ../hpl/eic - ../hpl/evsys - ../hpl/gclk - ../hpl/mclk - ../hpl/osc32kctrl - ../hpl/oscctrl - ../hpl/pm - ../hpl/port - ../hpl/qspi - ../hpl/ramecc - ../hpl/sercom - ../hpl/tc - ../hpl/tcc - ../hri - %24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include - - - Optimize debugging experience (-Og) - True - Maximum (-g3) - True - -std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16 - True - - - libm - libarm_cortexM4lf_math.a - - - - - C:\Users\ge37vez\Documents\Git Repos\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master_D51\Two_Motor_D51\Two_Motor_D51\cmsis - %24(ProjectDir)\Device_Startup - - - True - - -Tsamd51j18a_flash.ld -std=gnu99 -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mfp16-format=ieee - - - %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ - ../Config - ../ - ../examples - ../hal/include - ../hal/utils/include - ../hpl/adc - ../hpl/ccl - ../hpl/cmcc - ../hpl/core - ../hpl/dmac - ../hpl/eic - ../hpl/evsys - ../hpl/gclk - ../hpl/mclk - ../hpl/osc32kctrl - ../hpl/oscctrl - ../hpl/pm - ../hpl/port - ../hpl/qspi - ../hpl/ramecc - ../hpl/sercom - ../hpl/tc - ../hpl/tcc - ../hri - %24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include - - - Default (-g) - - - %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ - ../Config - ../ - ../examples - ../hal/include - ../hal/utils/include - ../hpl/adc - ../hpl/ccl - ../hpl/cmcc - ../hpl/core - ../hpl/dmac - ../hpl/eic - ../hpl/evsys - ../hpl/gclk - ../hpl/mclk - ../hpl/osc32kctrl - ../hpl/oscctrl - ../hpl/pm - ../hpl/port - ../hpl/qspi - ../hpl/ramecc - ../hpl/sercom - ../hpl/tc - ../hpl/tcc - ../hri - %24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include - - - Default (-Wa,-g) - + True + True + True + True + True + + + DEBUG + ARM_MATH_CM4=1 + + + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/adc + ../hpl/ccl + ../hpl/cmcc + ../hpl/core + ../hpl/dmac + ../hpl/eic + ../hpl/evsys + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/qspi + ../hpl/ramecc + ../hpl/sercom + ../hpl/tc + ../hpl/tcc + ../hri + %24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include + + + Optimize debugging experience (-Og) + True + Maximum (-g3) + True + -std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16 + True + + + libm + libarm_cortexM4lf_math.a + + + + + C:\Users\ge37vez\Documents\Git Repos\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master_D51\Two_Motor_D51\Two_Motor_D51\cmsis + %24(ProjectDir)\Device_Startup + C:\Users\trim_ni\Documents\Git\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master_D51\Two_Motor_D51\Two_Motor_D51\cmsis + + + True + + -Tsamd51j18a_flash.ld -std=gnu99 -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mfp16-format=ieee + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/adc + ../hpl/ccl + ../hpl/cmcc + ../hpl/core + ../hpl/dmac + ../hpl/eic + ../hpl/evsys + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/qspi + ../hpl/ramecc + ../hpl/sercom + ../hpl/tc + ../hpl/tcc + ../hri + %24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include + + + Default (-g) + + + %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/adc + ../hpl/ccl + ../hpl/cmcc + ../hpl/core + ../hpl/dmac + ../hpl/eic + ../hpl/evsys + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/qspi + ../hpl/ramecc + ../hpl/sercom + ../hpl/tc + ../hpl/tcc + ../hri + %24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include + + + Default (-Wa,-g) + diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/configuration.h b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/configuration.h index dec4c31..4b91c3c 100644 --- a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/configuration.h +++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/configuration.h @@ -8,17 +8,30 @@ #ifndef CONFIGURATION_H_ #define CONFIGURATION_H_ -// Conditional Inclusion Only Select One +// ---------------------------------------------------------------------- +// ---------------------------------------------------------------------- +// ---------------------------------------------------------------------- +// Configure System to be either Master or Slave. Set only one of these +// ---------------------------------------------------------------------- #define _MASTER //#define _SLAVE - -#ifdef _MASTER -#include "EtherCAT_QSPI.h" -#endif // MASTER +// ---------------------------------------------------------------------- +// ---------------------------------------------------------------------- +// ---------------------------------------------------------------------- +// ---------------------------------------------------------------------- + // ---------------------------------------------------------------------- // Header Files // ---------------------------------------------------------------------- + +#ifdef _MASTER +#include "EtherCAT_QSPI.h" +#endif // MASTER +#ifdef _SLAVE +#include "MSIF_slave.h" +#endif // SLAVE + #include "atmel_start_pins.h" #include "bldc.h" #include "interrupts.h" @@ -38,6 +51,26 @@ extern DmacDescriptor _write_back_section[DMAC_CH_NUM]; // ---------------------------------------------------------------------- // DMA CHANNEL NUMBER CONFIGURATION // ---------------------------------------------------------------------- +/* MASTER +* CH0 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin +* CH1 - SERCOM5_RX(SPI3) - Angle Sensor +* CH2 - SERCOM2_RX(SPI2) - Expansion IF (EMG) - Beat Transfer Event Drives CS Pin +* CH3 - ADC1 - Result Ready +* CH4 - ADC1 - Sequencer - Triggered by TCC0 overflow event +* CH5 - SERCOM2_TX(SPI2) - Expansion IF (EMG) +* CH6 - SERCOM5_TX(SPI3) - Angle Sensor +* CH7 - SERCOM1_TX(SPI1) - Master-Slave IF +SLAVE +* CH0 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin +* CH1 - SERCOM5_RX(SPI3) - Angle Sensor +* CH2 - ADC0 - Result Ready +* CH3 - ADC1 - Result Ready +* CH4 - ADC1 - Sequencer - Triggered by TCC0 overflow event +* CH5 - ADC0 - Sequencer +* CH6 - SERCOM5_TX(SPI3) - Angle Sensor +* CH7 - SERCOM1_TX(SPI1) - Master-Slave IF +*/ + #define CONF_SERCOM_1_SPI_DMA_RX_CHANNEL 0U #define CONF_SERCOM_1_SPI_DMA_TX_CHANNEL 7U #define CONF_ADC_1_ADC_RES_READY_CHANNEL 3U @@ -101,55 +134,108 @@ static void configure_tcc_pwm(void) //pwm_register_callback(&PWM_0, PWM_PERIOD_CB, pwm_cb); pwm_enable(&PWM_0); pwm_enable(&PWM_1); - } // ---------------------------------------------------------------------- // ADC DMA Initialization // M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6] +// FSR1 =ADC0_AIN[0], FSR2 =ADC0_AIN[3], FSR3 =ADC0_AIN[7], FSR4 =ADC0_AIN[10], FSR5 =ADC0_AIN[11] // ---------------------------------------------------------------------- -const uint32_t adc0_seq_regs[4] = {0}; -const uint32_t adc1_seq_regs[4] = {0x0089, 0x0088, 0x0087, 0x0086}; /* Differential */ -//const uint32_t adc1_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808}; /* Single Ended */ -volatile int16_t adc0_res[4] = {0}; -volatile int16_t adc1_res[4] = {0}; +#define CURRENT_SENSOR_CHANNELS 4U +#define SENSOR_CHANNELS 5U +const uint32_t adc0_seq_regs[SENSOR_CHANNELS] = {0x1801, 0x1803, 0x1807, 0x180A, 0x180B }; /* Single Ended */ +const uint32_t adc1_seq_regs[4] = {0x0089, 0x0088, 0x0087, 0x0086}; /* Differential */ +//const uint32_t adc1_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808}; /* Single Ended */ +volatile int16_t adc1_res[CURRENT_SENSOR_CHANNELS] = {0}; -struct _dma_resource *adc_sram_dma_resource; -struct _dma_resource *adc_dmac_sequence_resource; +struct _dma_resource *adc0_sram_dma_resource; +struct _dma_resource *adc1_sram_dma_resource; -static void adc_dmac_sequence_init() +#ifdef _SLAVE +static void adc0_dmac_sequence_init() +{ + /* Configure the DMAC source address, destination address, + * next descriptor address, data count and Enable the DMAC Channel + */ + _dma_set_source_address(CONF_ADC_0_SEQUENCER_CHANNEL, (const void *)adc0_seq_regs); + _dma_set_destination_address(CONF_ADC_0_SEQUENCER_CHANNEL, (const void *)&ADC0->DSEQDATA.reg); + _dma_set_data_amount(CONF_ADC_0_SEQUENCER_CHANNEL, 4); + _dma_set_next_descriptor(CONF_ADC_0_SEQUENCER_CHANNEL, CONF_ADC_0_SEQUENCER_CHANNEL); + _dma_enable_transaction(CONF_ADC_0_SEQUENCER_CHANNEL, false); + hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[CONF_ADC_0_SEQUENCER_CHANNEL], 0x01); //Suspend +} + +static void adc0_sram_dmac_init() +{ + _dma_set_source_address(CONF_ADC_0_ADC_RES_READY_CHANNEL, (const void *)&ADC0->RESULT.reg); + _dma_set_destination_address(CONF_ADC_0_ADC_RES_READY_CHANNEL, (const void *)&FSR_CH1); + _dma_set_data_amount(CONF_ADC_0_ADC_RES_READY_CHANNEL, SENSOR_CHANNELS); + _dma_set_irq_state(CONF_ADC_0_ADC_RES_READY_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true); + _dma_get_channel_resource(&adc1_sram_dma_resource, CONF_ADC_0_ADC_RES_READY_CHANNEL); + adc1_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback; + _dma_set_next_descriptor(CONF_ADC_0_ADC_RES_READY_CHANNEL, CONF_ADC_0_ADC_RES_READY_CHANNEL); /*?????*/ + _dma_enable_transaction(CONF_ADC_0_ADC_RES_READY_CHANNEL, false); +} +#endif //SLAVE + +static void adc1_dmac_sequence_init() { /* Configure the DMAC source address, destination address, * next descriptor address, data count and Enable the DMAC Channel */ _dma_set_source_address(CONF_ADC_1_SEQUENCER_CHANNEL, (const void *)adc1_seq_regs); _dma_set_destination_address(CONF_ADC_1_SEQUENCER_CHANNEL, (const void *)&ADC1->DSEQDATA.reg); - _dma_set_data_amount(CONF_ADC_1_SEQUENCER_CHANNEL, 4); + _dma_set_data_amount(CONF_ADC_1_SEQUENCER_CHANNEL, CURRENT_SENSOR_CHANNELS); _dma_set_next_descriptor(CONF_ADC_1_SEQUENCER_CHANNEL, CONF_ADC_1_SEQUENCER_CHANNEL); _dma_enable_transaction(CONF_ADC_1_SEQUENCER_CHANNEL, false); hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[CONF_ADC_1_SEQUENCER_CHANNEL], 0x01); //Suspend } -static void adc_sram_dmac_init() +static void adc1_sram_dmac_init() { _dma_set_source_address(CONF_ADC_1_ADC_RES_READY_CHANNEL, (const void *)&ADC1->RESULT.reg); _dma_set_destination_address(CONF_ADC_1_ADC_RES_READY_CHANNEL, (const void *)adc1_res); - _dma_set_data_amount(CONF_ADC_1_ADC_RES_READY_CHANNEL, 4); + _dma_set_data_amount(CONF_ADC_1_ADC_RES_READY_CHANNEL, CURRENT_SENSOR_CHANNELS); _dma_set_irq_state(CONF_ADC_1_ADC_RES_READY_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true); - _dma_get_channel_resource(&adc_sram_dma_resource, CONF_ADC_1_ADC_RES_READY_CHANNEL); - adc_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback; + _dma_get_channel_resource(&adc1_sram_dma_resource, CONF_ADC_1_ADC_RES_READY_CHANNEL); + adc1_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback; _dma_set_next_descriptor(CONF_ADC_1_ADC_RES_READY_CHANNEL, CONF_ADC_1_ADC_RES_READY_CHANNEL); /*?????*/ _dma_enable_transaction(CONF_ADC_1_ADC_RES_READY_CHANNEL, false); } - // ---------------------------------------------------------------------- // ADC Initialization // ---------------------------------------------------------------------- -static void adc1_init_dma_descriptors(void) +#ifdef _SLAVE +static void adc0_dma_init(void) { - adc_sram_dmac_init(); - adc_dmac_sequence_init(); + // Disable digital pin circuitry + gpio_set_pin_direction(GPIO(GPIO_PORTA, 2), GPIO_DIRECTION_OFF); + gpio_set_pin_function(GPIO(GPIO_PORTA, 2), PINMUX_PA02B_ADC0_AIN0); + // Disable digital pin circuitry + gpio_set_pin_direction(GPIO(GPIO_PORTB, 9), GPIO_DIRECTION_OFF); + gpio_set_pin_function(GPIO(GPIO_PORTB, 9), PINMUX_PB09B_ADC0_AIN3); + // Disable digital pin circuitry + gpio_set_pin_direction(GPIO(GPIO_PORTA, 7), GPIO_DIRECTION_OFF); + gpio_set_pin_function(GPIO(GPIO_PORTA, 7), PINMUX_PA07B_ADC0_AIN7); + // Disable digital pin circuitry + gpio_set_pin_direction(GPIO(GPIO_PORTA, 10), GPIO_DIRECTION_OFF); + gpio_set_pin_function(GPIO(GPIO_PORTA, 10), PINMUX_PA10B_ADC0_AIN10); + // Disable digital pin circuitry + gpio_set_pin_direction(GPIO(GPIO_PORTA, 11), GPIO_DIRECTION_OFF); + gpio_set_pin_function(GPIO(GPIO_PORTA, 11), PINMUX_PA11B_ADC0_AIN11); + + adc0_sram_dmac_init(); + adc0_dmac_sequence_init(); + hri_adc_set_DSEQCTRL_INPUTCTRL_bit(ADC0); + hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC0); +} +#endif //SLAVE + +static void adc1_dma_init(void) +{ + adc1_sram_dmac_init(); + adc1_dmac_sequence_init(); hri_adc_set_DSEQCTRL_INPUTCTRL_bit(ADC1); hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC1); } @@ -195,102 +281,74 @@ static void boardToBoardTransferInit(void) #endif //SLAVE } + +#ifdef _SLAVE void SPI_1_MSIF_Slave_PORT_init(void) { // Set pin direction to input gpio_set_pin_direction(SPI1_MOSI, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(SPI1_MOSI, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - + gpio_set_pin_pull_mode(SPI1_MOSI, GPIO_PULL_OFF); gpio_set_pin_function(SPI1_MOSI, PINMUX_PA00D_SERCOM1_PAD0); - gpio_set_pin_level(SPI1_SCK, - // Initial level - // pad_initial_level - // Low - // High - false); - + gpio_set_pin_level(SPI1_SCK, false); // Set pin direction to output gpio_set_pin_direction(SPI1_SCK, GPIO_DIRECTION_OUT); - gpio_set_pin_function(SPI1_SCK, PINMUX_PA01D_SERCOM1_PAD1); // Set pin direction to input gpio_set_pin_direction(SPI1_CS, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(SPI1_CS, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); + gpio_set_pin_pull_mode(SPI1_CS, GPIO_PULL_OFF); gpio_set_pin_function(SPI1_CS, PINMUX_PB22C_SERCOM1_PAD2); - - gpio_set_pin_level(SPI1_MISO, - // Initial level - // pad_initial_level - // Low - // High - false); + gpio_set_pin_level(SPI1_MISO, false); // Set pin direction to output gpio_set_pin_direction(SPI1_MISO, GPIO_DIRECTION_OUT); - gpio_set_pin_function(SPI1_MISO, PINMUX_PB23C_SERCOM1_PAD3); } - +#endif //SLAVE static void spi_master_slave_if_dma_descriptor_init() { #ifdef _MASTER - _dma_set_source_address(CONF_SERCOM_1_SPI_DMA_RX_CHANNEL, - (uint32_t *)&(((SercomSpi *)(SPI_1_MSIF_M.dev.prvt))->DATA.reg)); - _dma_set_destination_address(CONF_SERCOM_1_SPI_DMA_RX_CHANNEL, &QSPI_tx_buffer[16]); - _dma_set_data_amount(CONF_SERCOM_1_SPI_DMA_RX_CHANNEL, MASTER_SLAVE_BUFFER_SIZE_LONG); - _dma_set_next_descriptor(CONF_SERCOM_1_SPI_DMA_RX_CHANNEL, CONF_SERCOM_1_SPI_DMA_RX_CHANNEL); - - - _dma_set_source_address(CONF_SERCOM_1_SPI_DMA_TX_CHANNEL, &QSPI_rx_buffer[16]); - _dma_set_destination_address(CONF_SERCOM_1_SPI_DMA_TX_CHANNEL, + _dma_set_source_address(CONF_SERCOM_1_SPI_DMA_RX_CHANNEL, (uint32_t *)&(((SercomSpi *)(SPI_1_MSIF_M.dev.prvt))->DATA.reg)); - _dma_set_data_amount(CONF_SERCOM_1_SPI_DMA_TX_CHANNEL, MASTER_SLAVE_BUFFER_SIZE_LONG); - _dma_set_next_descriptor(CONF_SERCOM_1_SPI_DMA_TX_CHANNEL, CONF_SERCOM_1_SPI_DMA_TX_CHANNEL); + _dma_set_destination_address(CONF_SERCOM_1_SPI_DMA_RX_CHANNEL, &QSPI_tx_buffer[16]); + _dma_set_data_amount(CONF_SERCOM_1_SPI_DMA_RX_CHANNEL, MASTER_SLAVE_BUFFER_SIZE_LONG); + _dma_set_next_descriptor(CONF_SERCOM_1_SPI_DMA_RX_CHANNEL, CONF_SERCOM_1_SPI_DMA_RX_CHANNEL); - hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_DMA_TX_CHANNEL]); - hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_DMA_RX_CHANNEL]); + _dma_set_source_address(CONF_SERCOM_1_SPI_DMA_TX_CHANNEL, &QSPI_rx_buffer[16]); + _dma_set_destination_address(CONF_SERCOM_1_SPI_DMA_TX_CHANNEL, + (uint32_t *)&(((SercomSpi *)(SPI_1_MSIF_M.dev.prvt))->DATA.reg)); + _dma_set_data_amount(CONF_SERCOM_1_SPI_DMA_TX_CHANNEL, MASTER_SLAVE_BUFFER_SIZE_LONG); + _dma_set_next_descriptor(CONF_SERCOM_1_SPI_DMA_TX_CHANNEL, CONF_SERCOM_1_SPI_DMA_TX_CHANNEL); - /* callback */ - //struct _dma_resource *resource_rx, *resource_tx; - //_dma_get_channel_resource(&resource_rx, CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL); - //_dma_get_channel_resource(&resource_tx, CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL); - //resource_rx->dma_cb.transfer_done = spi_slave_rx_complete_cb; - //resource_tx->dma_cb.transfer_done = b2bTransferComplete_cb; + + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_DMA_TX_CHANNEL]); + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_DMA_RX_CHANNEL]); + + /* callback */ + //struct _dma_resource *resource_rx, *resource_tx; + //_dma_get_channel_resource(&resource_rx, CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL); + //_dma_get_channel_resource(&resource_tx, CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL); + //resource_rx->dma_cb.transfer_done = spi_slave_rx_complete_cb; + //resource_tx->dma_cb.transfer_done = b2bTransferComplete_cb; - /* Enable DMA transfer complete interrupt */ - //_dma_set_irq_state(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, DMA_TRANSFER_COMPLETE_CB, true); + /* Enable DMA transfer complete interrupt */ + //_dma_set_irq_state(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, DMA_TRANSFER_COMPLETE_CB, true); #endif //MASTER + #ifdef _SLAVE + + + #endif //SLAVE } #ifdef _MASTER -/* 219 Bites total -* Number format is 24 bit -* 7 (uint_32) - 24 bits -*/ extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE]; -// static void spi_ads1299_init_dma_descriptors() { _dma_set_source_address(CONF_SERCOM_2_SPI_DMA_RX_CHANNEL, @@ -329,38 +387,17 @@ static void spi_ads1299_init_dma_descriptors() // ---------------------------------------------------------------------- // Overall DMA Init // ---------------------------------------------------------------------- -/* MASTER -* CH0 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin -* CH1 - SERCOM5_RX(SPI3) - Angle Sensor -* CH2 - SERCOM2_RX(SPI2) - Expansion IF (EMG) - Beat Transfer Event Drives CS Pin -* CH3 - ADC1 - Result Ready -* CH4 - ADC1 - Sequencer - Triggered by TCC0 overflow event -* CH5 - SERCOM2_TX(SPI2) - Expansion IF (EMG) -* CH6 - SERCOM5_TX(SPI3) - Angle Sensor -* CH7 - SERCOM1_TX(SPI1) - Master-Slave IF -*/ - -/* SLAVE -* CH0 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin -* CH1 - SERCOM5_RX(SPI3) - Angle Sensor -* CH2 - ADC0 - Result Ready -* CH3 - ADC1 - Result Ready -* CH4 - ADC1 - Sequencer - Triggered by TCC0 overflow event -* CH5 - ADC0 - Sequencer -* CH6 - SERCOM5_TX(SPI3) - Angle Sensor -* CH7 - SERCOM1_TX(SPI1) - Master-Slave IF -*/ - static void init_dma(void) { spi_master_slave_if_dma_descriptor_init(); - adc1_init_dma_descriptors(); + adc1_dma_init(); #ifdef _MASTER - spi_ads1299_init_dma_descriptors(); - #endif // _MASTER + spi_ads1299_init_dma_descriptors(); + #else + adc0_dma_init(); + #endif //MASTER } - // ---------------------------------------------------------------------- // Overall DMA Init // ---------------------------------------------------------------------- diff --git a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/main.c b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/main.c index 1a6ef50..2c404e2 100644 --- a/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/main.c +++ b/2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/main.c @@ -23,7 +23,6 @@ #endif // SLAVE - void process_currents() { Motor1.timerflags.adc_readings_ready_tic = false;