diff --git a/BLDC_E54/.vs/BLDC_E54/v14/.atsuo b/BLDC_E54/.vs/BLDC_E54/v14/.atsuo index 5d8f3cc..ac508ab 100644 Binary files a/BLDC_E54/.vs/BLDC_E54/v14/.atsuo and b/BLDC_E54/.vs/BLDC_E54/v14/.atsuo differ diff --git a/BLDC_E54/BLDC_E54/.atmelstart/atmel_start_config.atstart b/BLDC_E54/BLDC_E54/.atmelstart/atmel_start_config.atstart index 5f6d02e..73f4306 100644 --- a/BLDC_E54/BLDC_E54/.atmelstart/atmel_start_config.atstart +++ b/BLDC_E54/BLDC_E54/.atmelstart/atmel_start_config.atstart @@ -894,7 +894,7 @@ drivers: evsys_channel_41: No channel output selected evsys_channel_42: No channel output selected evsys_channel_43: No channel output selected - evsys_channel_44: No channel output selected + evsys_channel_44: Channel 1 evsys_channel_45: No channel output selected evsys_channel_46: No channel output selected evsys_channel_47: No channel output selected @@ -923,7 +923,7 @@ drivers: evsys_channel_8: No channel output selected evsys_channel_9: No channel output selected evsys_channel_setting_0: true - evsys_channel_setting_1: false + evsys_channel_setting_1: true evsys_channel_setting_10: false evsys_channel_setting_11: false evsys_channel_setting_12: false @@ -1051,7 +1051,7 @@ drivers: evsys_evd_8: false evsys_evd_9: false evsys_evgen_0: TCC1 overflow - evsys_evgen_1: No event generator + evsys_evgen_1: CCL LUT output 0 evsys_evgen_10: No event generator evsys_evgen_11: No event generator evsys_evgen_12: No event generator @@ -1147,7 +1147,7 @@ drivers: evsys_ovr_8: false evsys_ovr_9: false evsys_path_0: Asynchronous path - evsys_path_1: Synchronous path + evsys_path_1: Asynchronous path evsys_path_10: Synchronous path evsys_path_11: Synchronous path evsys_path_12: Synchronous path diff --git a/BLDC_E54/BLDC_E54/BLDC_E54.cproj b/BLDC_E54/BLDC_E54/BLDC_E54.cproj index 1d7b923..3e2b8d8 100644 --- a/BLDC_E54/BLDC_E54/BLDC_E54.cproj +++ b/BLDC_E54/BLDC_E54/BLDC_E54.cproj @@ -148,7 +148,7 @@ - + @@ -205,7 +205,7 @@ - + diff --git a/BLDC_E54/BLDC_E54/Config/hpl_evsys_config.h b/BLDC_E54/BLDC_E54/Config/hpl_evsys_config.h index 36955a2..4c68b9e 100644 --- a/BLDC_E54/BLDC_E54/Config/hpl_evsys_config.h +++ b/BLDC_E54/BLDC_E54/Config/hpl_evsys_config.h @@ -188,7 +188,7 @@ // Channel 1 settings // evsys_channel_setting_1 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_1 -#define CONF_EVSYS_CHANNEL_SETTINGS_1 0 +#define CONF_EVSYS_CHANNEL_SETTINGS_1 1 #endif // Edge detection @@ -209,7 +209,7 @@ // Asynchronous path // evsys_path_1 #ifndef CONF_PATH_1 -#define CONF_PATH_1 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#define CONF_PATH_1 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val #endif // Event generator @@ -333,7 +333,7 @@ // <0x77=>CCL LUT output 3 // evsys_evgen_1 #ifndef CONF_EVGEN_1 -#define CONF_EVGEN_1 0 +#define CONF_EVGEN_1 116 #endif // Overrun channel interrupt @@ -7464,7 +7464,7 @@ // evsys_channel_44 // Indicates which channel is chosen for user #ifndef CONF_CHANNEL_44 -#define CONF_CHANNEL_44 0 +#define CONF_CHANNEL_44 2 #endif // Channel selection for TC1 event diff --git a/BLDC_E54/BLDC_E54/Config/hpl_tcc_config.h b/BLDC_E54/BLDC_E54/Config/hpl_tcc_config.h new file mode 100644 index 0000000..558bc00 --- /dev/null +++ b/BLDC_E54/BLDC_E54/Config/hpl_tcc_config.h @@ -0,0 +1,1124 @@ +/* Auto-generated config file hpl_tcc_config.h */ +#ifndef HPL_TCC_CONFIG_H +#define HPL_TCC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include +#ifndef CONF_TCC0_ENABLE +#define CONF_TCC0_ENABLE 1 +#endif + +#ifndef CONF_TCC0_PWM_ENABLE +#define CONF_TCC0_PWM_ENABLE 1 +#endif + +// Basic settings +// TCC0 Prescaler +// No division +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 64 +// Divide by 256 +// Divide by 1024 +// This defines the TCC0 prescaler value +// tcc_prescaler +#ifndef CONF_TCC0_PRESCALER +#define CONF_TCC0_PRESCALER TCC_CTRLA_PRESCALER_DIV2_Val +#endif + +// +// TCC0 Period Value <0x000000-0xFFFFFF> +// tcc_per +#ifndef CONF_TCC0_PER +#define CONF_TCC0_PER 0x2710 +#endif +// + +// + +// PWM Waveform Output settings +// TCC0 Waveform Period Value (uS) <0x00-0xFFFFFFFF> +// The unit of this value is us. +// tcc_arch_wave_per_val +#ifndef CONF_TCC0_WAVE_PER_VAL +#define CONF_TCC0_WAVE_PER_VAL 0x28 +#endif + +// TCC0 Waveform Duty Value (0.1%) <0x00-0x03E8> +// The unit of this value is 1/1000. +// tcc_arch_wave_duty_val +#ifndef CONF_TCC0_WAVE_DUTY_VAL +#define CONF_TCC0_WAVE_DUTY_VAL 0x1f4 +#endif + +// TCC0 Waveform Channel Select <0x00-0x05> +// Index of the Compare Channel register, into which the Waveform Duty Value is written. +// Give index of the Compare Channel register here in 0x00-0x05 range. +// tcc_arch_sel_ch +#ifndef CONF_TCC0_SEL_CH +#define CONF_TCC0_SEL_CH 0x0 +#endif + +/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ +#if CONF_TCC0_PRESCALER < TCC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TCC0_PER_REG \ + ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1000000 / (1 << CONF_TCC0_PRESCALER) - 1)) +#define CONF_TCC0_CCX_REG ((uint32_t)(((double)(double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000)) + +#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 64000000 - 1)) +#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000)) + +#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV256_Val +#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 256000000 - 1)) +#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000)) + +#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV1024_Val +#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1024000000 - 1)) +#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000)) +#endif +// + +// Advanced settings +/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL A register. + * May be used by other abstractions based on TC. */ +//#define CONF_TCC0_RESOLUTION TCC_CTRLA_RESOLUTION_NONE_Val +// Run in standby +// Indicates whether the TCC0 will continue running in standby sleep mode or not +// tcc_arch_runstdby +#ifndef CONF_TCC0_RUNSTDBY +#define CONF_TCC0_RUNSTDBY 0 +#endif + +// TCC0 Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock. +// tcc_arch_prescsync +#ifndef CONF_TCC0_PRESCSYNC +#define CONF_TCC0_PRESCSYNC TCC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +// TCC0 Waveform Generation Selection +// Single-slope PWM +// Dual-slope, critical interrupt/event at ZERO (DSCRITICAL) +// Dual-slope, interrupt/event at ZERO (DSBOTTOM) +// Dual-slope, interrupt/event at Top and ZERO (DSBOTH) +// Dual-slope, interrupt/event at Top (DSTOP) +// tcc_arch_wavegen +#ifndef CONF_TCC0_WAVEGEN +#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_DSBOTTOM_Val +#endif +// TCC0 Auto Lock +// Indicates whether the TCC0 Auto Lock is enabled or not +// tcc_arch_alock +#ifndef CONF_TCC0_ALOCK +#define CONF_TCC0_ALOCK 0 +#endif + +// TCC0 Capture Channel 0 Enable +// Indicates whether the TCC0 Capture Channel 0 is enabled or not +// tcc_arch_cpten0 +#ifndef CONF_TCC0_CPTEN0 +#define CONF_TCC0_CPTEN0 0 +#endif + +// TCC0 Capture Channel 1 Enable +// Indicates whether the TCC0 Capture Channel 1 is enabled or not +// tcc_arch_cpten1 +#ifndef CONF_TCC0_CPTEN1 +#define CONF_TCC0_CPTEN1 0 +#endif + +// TCC0 Capture Channel 2 Enable +// Indicates whether the TCC0 Capture Channel 2 is enabled or not +// tcc_arch_cpten2 +#ifndef CONF_TCC0_CPTEN2 +#define CONF_TCC0_CPTEN2 0 +#endif + +// TCC0 Capture Channel 3 Enable +// Indicates whether the TCC0 Capture Channel 3 is enabled or not +// tcc_arch_cpten3 +#ifndef CONF_TCC0_CPTEN3 +#define CONF_TCC0_CPTEN3 0 +#endif + +// TCC0 Capture Channel 4 Enable +// Indicates whether the TCC0 Capture Channel 4 is enabled or not +// tcc_arch_cpten4 +#ifndef CONF_TCC0_CPTEN4 +#define CONF_TCC0_CPTEN4 0 +#endif + +// TCC0 Capture Channel 5 Enable +// Indicates whether the TCC0 Capture Channel 5 is enabled or not +// tcc_arch_cpten5 +#ifndef CONF_TCC0_CPTEN5 +#define CONF_TCC0_CPTEN5 0 +#endif + +// +// TCC0 Capture Channel 6 Enable +// Indicates whether the TCC0 Capture Channel 6 is enabled or not +// tcc_arch_cpten6 +#ifndef CONF_TCC0_CPTEN6 +#define CONF_TCC0_CPTEN6 0 +#endif +// +// +// TCC0 Capture Channel 7 Enable +// Indicates whether the TCC0 Capture Channel 7 is enabled or not +// tcc_arch_cpten7 +#ifndef CONF_TCC0_CPTEN7 +#define CONF_TCC0_CPTEN7 0 +#endif +// + +// TCC0 Lock update +// Indicates whether the TCC0 Lock update is enabled or not +// tcc_arch_lupd +#ifndef CONF_TCC0_LUPD +#define CONF_TCC0_LUPD 0 +#endif + +/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL B register. + * May be used by other abstractions based on TC. */ +//#define CONF_TCC0_DIR 0 +//#define CONF_TCC0_ONESHOT 0 + +/* Commented intentionally. No fault control for timers. */ +/*#define CONF_TCC0_FAULT_A_SRC TCC_FCTRLA_SRC_DISABLE_Val +#define CONF_TCC0_FAULT_A_KEEP 0 +#define CONF_TCC0_FAULT_A_QUAL 0 +#define CONF_TCC0_FAULT_A_BLANK TCC_FCTRLA_BLANK_DISABLE_Val +#define CONF_TCC0_FAULT_A_RESTART 0 +#define CONF_TCC0_FAULT_A_HALT TCC_FCTRLA_HALT_DISABLE_Val +#define CONF_TCC0_FAULT_A_CHSEL TCC_FCTRLA_CHSEL_CC0_Val +#define CONF_TCC0_FAULT_A_CAPTURE TCC_FCTRLA_CAPTURE_DISABLE_Val +#define CONF_TCC0_FAULT_A_BLACNKPRESC 0 +#define CONF_TCC0_FAULT_A_BLANKVAL 0 +#define CONF_TCC0_FAULT_A_FILTERVAL 0 + +#define CONF_TCC0_FAULT_B_SRC TCC_FCTRLB_SRC_DISABLE_Val +#define CONF_TCC0_FAULT_B_KEEP 0 +#define CONF_TCC0_FAULT_B_QUAL 0 +#define CONF_TCC0_FAULT_B_BLANK TCC_FCTRLB_BLANK_DISABLE_Val +#define CONF_TCC0_FAULT_B_RESTART 0 +#define CONF_TCC0_FAULT_B_HALT TCC_FCTRLB_HALT_DISABLE_Val +#define CONF_TCC0_FAULT_B_CHSEL TCC_FCTRLB_CHSEL_CC0_Val +#define CONF_TCC0_FAULT_B_CAPTURE TCC_FCTRLB_CAPTURE_DISABLE_Val +#define CONF_TCC0_FAULT_B_BLACNKPRESC 0 +#define CONF_TCC0_FAULT_B_BLANKVAL 0 +#define CONF_TCC0_FAULT_B_FILTERVAL 0*/ + +/* Commented intentionally. No dead-time control for timers. */ +/*#define CONF_TCC0_OTMX 0 +#define CONF_TCC0_DTIEN0 0 +#define CONF_TCC0_DTIEN1 0 +#define CONF_TCC0_DTIEN2 0 +#define CONF_TCC0_DTIEN3 0 +#define CONF_TCC0_DTHS 0*/ + +/* Commented intentionally. No driver control for timers. */ +/*#define CONF_TCC0_NRE0 0 +#define CONF_TCC0_NRE1 0 +#define CONF_TCC0_NRE2 0 +#define CONF_TCC0_NRE3 0 +#define CONF_TCC0_NRE4 0 +#define CONF_TCC0_NRE5 0 +#define CONF_TCC0_NRE6 0 +#define CONF_TCC0_NRE7 0 +#define CONF_TCC0_NVR0 0 +#define CONF_TCC0_NVR1 0 +#define CONF_TCC0_NVR2 0 +#define CONF_TCC0_NVR3 0 +#define CONF_TCC0_NVR4 0 +#define CONF_TCC0_NVR5 0 +#define CONF_TCC0_NVR6 0 +#define CONF_TCC0_NVR7 0 +#define CONF_TCC0_INVEN0 0 +#define CONF_TCC0_INVEN1 0 +#define CONF_TCC0_INVEN2 0 +#define CONF_TCC0_INVEN3 0 +#define CONF_TCC0_INVEN4 0 +#define CONF_TCC0_INVEN5 0 +#define CONF_TCC0_INVEN6 0 +#define CONF_TCC0_INVEN7 0 +#define CONF_TCC0_FILTERVAL0 0 +#define CONF_TCC0_FILTERVAL1 0*/ + +// TCC0 Debug Running Mode +// Indicates whether the TCC0 Debug Running Mode is enabled or not +// tcc_arch_dbgrun +#ifndef CONF_TCC0_DBGRUN +#define CONF_TCC0_DBGRUN 0 +#endif + +/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of Debug Control register. + * May be used by other abstractions based on TC. */ +//#define CONF_TCC0_FDDBD 0 + +// Event control +// timer_event_control +#ifndef CONF_TCC0_EVENT_CONTROL_ENABLE +#define CONF_TCC0_EVENT_CONTROL_ENABLE 1 +#endif + +// Match or Capture Channel 0 Event Output +// This bit indicates whether match/capture event on channel 0 is enabled and will be generated +// tcc_arch_mceo0 +#ifndef CONF_TCC0_MCEO0 +#define CONF_TCC0_MCEO0 0 +#endif + +// Match or Capture Channel 0 Event Input +// This bit indicates whether match/capture 0 incoming event is enabled +// tcc_arch_mcei0 +#ifndef CONF_TCC0_MCEI0 +#define CONF_TCC0_MCEI0 0 +#endif +// Match or Capture Channel 1 Event Output +// This bit indicates whether match/capture event on channel 1 is enabled and will be generated +// tcc_arch_mceo1 +#ifndef CONF_TCC0_MCEO1 +#define CONF_TCC0_MCEO1 0 +#endif + +// Match or Capture Channel 1 Event Input +// This bit indicates whether match/capture 1 incoming event is enabled +// tcc_arch_mcei1 +#ifndef CONF_TCC0_MCEI1 +#define CONF_TCC0_MCEI1 0 +#endif +// Match or Capture Channel 2 Event Output +// This bit indicates whether match/capture event on channel 2 is enabled and will be generated +// tcc_arch_mceo2 +#ifndef CONF_TCC0_MCEO2 +#define CONF_TCC0_MCEO2 0 +#endif + +// Match or Capture Channel 2 Event Input +// This bit indicates whether match/capture 2 incoming event is enabled +// tcc_arch_mcei2 +#ifndef CONF_TCC0_MCEI2 +#define CONF_TCC0_MCEI2 0 +#endif +// Match or Capture Channel 3 Event Output +// This bit indicates whether match/capture event on channel 3 is enabled and will be generated +// tcc_arch_mceo3 +#ifndef CONF_TCC0_MCEO3 +#define CONF_TCC0_MCEO3 0 +#endif + +// Match or Capture Channel 3 Event Input +// This bit indicates whether match/capture 3 incoming event is enabled +// tcc_arch_mcei3 +#ifndef CONF_TCC0_MCEI3 +#define CONF_TCC0_MCEI3 0 +#endif +// Match or Capture Channel 4 Event Output +// This bit indicates whether match/capture event on channel 4 is enabled and will be generated +// tcc_arch_mceo4 +#ifndef CONF_TCC0_MCEO4 +#define CONF_TCC0_MCEO4 0 +#endif + +// Match or Capture Channel 4 Event Input +// This bit indicates whether match/capture 4 incoming event is enabled +// tcc_arch_mcei4 +#ifndef CONF_TCC0_MCEI4 +#define CONF_TCC0_MCEI4 0 +#endif +// Match or Capture Channel 5 Event Output +// This bit indicates whether match/capture event on channel 5 is enabled and will be generated +// tcc_arch_mceo5 +#ifndef CONF_TCC0_MCEO5 +#define CONF_TCC0_MCEO5 0 +#endif + +// Match or Capture Channel 5 Event Input +// This bit indicates whether match/capture 5 incoming event is enabled +// tcc_arch_mcei5 +#ifndef CONF_TCC0_MCEI5 +#define CONF_TCC0_MCEI5 0 +#endif + +// Timer/Counter Event Input 0 +// This bit is used to enable input event 0 to the TCC +// tcc_arch_tcei0 +#ifndef CONF_TCC0_TCEI0 +#define CONF_TCC0_TCEI0 0 +#endif + +// Timer/Counter Event Input 0 Invert +// This bit inverts the event 0 input +// tcc_arch_tceinv0 +#ifndef CONF_TCC0_TCINV0 +#define CONF_TCC0_TCINV0 0 +#endif +// Timer/Counter Event Input 1 +// This bit is used to enable input event 1 to the TCC +// tcc_arch_tcei1 +#ifndef CONF_TCC0_TCEI1 +#define CONF_TCC0_TCEI1 0 +#endif + +// Timer/Counter Event Input 1 Invert +// This bit inverts the event 1 input +// tcc_arch_tceinv1 +#ifndef CONF_TCC0_TCINV1 +#define CONF_TCC0_TCINV1 0 +#endif + +// Timer/Counter Event Output +// This bit is used to enable the counter cycle event. +// tcc_arch_cnteo +#ifndef CONF_TCC0_CNTEO +#define CONF_TCC0_CNTEO 0 +#endif + +// Re-trigger Event Output +// This bit is used to enable the counter re-trigger event. +// tcc_arch_trgeo +#ifndef CONF_TCC0_TRGEO +#define CONF_TCC0_TRGEO 0 +#endif + +// Overflow/Underflow Event Output +// This bit is used to enable enable event on overflow/underflow. +// tcc_arch_ovfeo +#ifndef CONF_TCC0_OVFEO +#define CONF_TCC0_OVFEO 1 +#endif + +// Timer/Counter Interrupt and Event Output Selection +// <0=> An interrupt/event is generated when a new counter cycle starts +// <1=> An interrupt/event is generated when a counter cycle ends +// <2=> An interrupt/event is generated when a counter cycle ends, except for the first and last cycles +// <3=> An interrupt/event is generated when a new counter cycle starts or a counter cycle ends +// These bits define on which part of the counter cycle the counter event output is generated +// tcc_arch_cntsel +#ifndef CONF_TCC0_CNTSEL +#define CONF_TCC0_CNTSEL 0 +#endif + +// Timer/Counter Event Input 0 Action +// <0=>Event action disabled +// <1=>Start restart or re-trigger on event +// <2=>Count on event +// <3=>Start on event +// <4=>Increment on event +// <5=>Count on active state of asynchronous event +// <6=>Capture overflow times (Max value) +// <7=>Non-recoverable fault +// These bits define the action the TCC performs on TCE0 event input 0 +// tcc_arch_evact0 +#ifndef CONF_TCC0_EVACT0 +#define CONF_TCC0_EVACT0 0 +#endif + +// Timer/Counter Event Input 1 Action +// <0=>Event action disabled +// <1=>Re-trigger counter on event +// <2=>Direction control +// <3=>Stop counter on event +// <4=>Decrement counter on event +// <5=>Period capture value in CC0 register, pulse width capture value in CC1 register +// <6=>Period capture value in CC1 register, pulse width capture value in CC0 register +// <7=>Non-recoverable fault +// These bits define the action the TCC performs on TCE0 event input 0 +// tcc_arch_evact1 +#ifndef CONF_TCC0_EVACT1 +#define CONF_TCC0_EVACT1 0 +#endif +// + +/* Commented intentionally. No pattern control for timers. */ +/*#define CONF_TCC0_PGE0 0 +#define CONF_TCC0_PGE1 0 +#define CONF_TCC0_PGE2 0 +#define CONF_TCC0_PGE3 0 +#define CONF_TCC0_PGE4 0 +#define CONF_TCC0_PGE5 0 +#define CONF_TCC0_PGE6 0 +#define CONF_TCC0_PGE7 0 +#define CONF_TCC0_PGV0 0 +#define CONF_TCC0_PGV1 0 +#define CONF_TCC0_PGV2 0 +#define CONF_TCC0_PGV3 0 +#define CONF_TCC0_PGV4 0 +#define CONF_TCC0_PGV5 0 +#define CONF_TCC0_PGV6 0 +#define CONF_TCC0_PGV7 0*/ + +/* Commented intentionally. No pattern waveform control for timers. */ +/*#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_MFRQ_Val +#define CONF_TCC0_RAMP TCC_WAVE_RAMP_RAMP1_Val +#define CONF_TCC0_CIPEREN 0 +#define CONF_TCC0_CICCEN0 0 +#define CONF_TCC0_CICCEN1 0 +#define CONF_TCC0_CICCEN2 0 +#define CONF_TCC0_CICCEN3 0 +#define CONF_TCC0_POL0 0 +#define CONF_TCC0_POL1 0 +#define CONF_TCC0_POL2 0 +#define CONF_TCC0_POL3 0 +#define CONF_TCC0_POL4 0 +#define CONF_TCC0_POL5 0 +#define CONF_TCC0_POL6 0 +#define CONF_TCC0_POL7 0 +#define CONF_TCC0_SWAP0 0 +#define CONF_TCC0_SWAP1 0 +#define CONF_TCC0_SWAP2 0 +#define CONF_TCC0_SWAP3 0*/ + +// TCC0 Compare and Capture value 0 <0x00-0xFFFFFF> +// tcc_arch_cc0 +#ifndef CONF_TCC0_CC0 +#define CONF_TCC0_CC0 0x0 +#endif + +// TCC0 Compare and Capture value 1 <0x00-0xFFFFFF> +// tcc_arch_cc1 +#ifndef CONF_TCC0_CC1 +#define CONF_TCC0_CC1 0x0 +#endif + +// TCC0 Compare and Capture value 2 <0x00-0xFFFFFF> +// tcc_arch_cc2 +#ifndef CONF_TCC0_CC2 +#define CONF_TCC0_CC2 0x0 +#endif + +// TCC0 Compare and Capture value 3 <0x00-0xFFFFFF> +// tcc_arch_cc3 +#ifndef CONF_TCC0_CC3 +#define CONF_TCC0_CC3 0x0 +#endif + +// TCC0 Compare and Capture value 4 <0x00-0xFFFFFF> +// tcc_arch_cc4 +#ifndef CONF_TCC0_CC4 +#define CONF_TCC0_CC4 0x0 +#endif + +// TCC0 Compare and Capture value 5 <0x00-0xFFFFFF> +// tcc_arch_cc5 +#ifndef CONF_TCC0_CC5 +#define CONF_TCC0_CC5 0x0 +#endif + +/* Commented intentionally. No pattern control for timers. */ +/*#define CONF_TCC0_PATTB_PGEB0 0 +#define CONF_TCC0_PATTB_PGEB1 0 +#define CONF_TCC0_PATTB_PGEB2 0 +#define CONF_TCC0_PATTB_PGEB3 0 +#define CONF_TCC0_PATTB_PGEB4 0 +#define CONF_TCC0_PATTB_PGEB5 0 +#define CONF_TCC0_PATTB_PGEB6 0 +#define CONF_TCC0_PATTB_PGEB7 0 +#define CONF_TCC0_PATTB_PGVB0 0 +#define CONF_TCC0_PATTB_PGVB1 0 +#define CONF_TCC0_PATTB_PGVB2 0 +#define CONF_TCC0_PATTB_PGVB3 0 +#define CONF_TCC0_PATTB_PGVB4 0 +#define CONF_TCC0_PATTB_PGVB5 0 +#define CONF_TCC0_PATTB_PGVB6 0 +#define CONF_TCC0_PATTB_PGVB7 0*/ + +/* Commented intentionally. No waveform control for timers. */ +/*#define CONF_TCC0_WAVEGENB TCC_WAVEB_WAVEGENB_MFRQ_Val +#define CONF_TCC0_RAMPB TCC_WAVE_RAMP_RAMP1_Val +#define CONF_TCC0_CIPERENB 0 +#define CONF_TCC0_CICCEN0B 0 +#define CONF_TCC0_CICCEN1B 0 +#define CONF_TCC0_CICCEN2B 0 +#define CONF_TCC0_CICCEN3B 0 +#define CONF_TCC0_POL0B 0 +#define CONF_TCC0_POL1B 0 +#define CONF_TCC0_POL2B 0 +#define CONF_TCC0_POL3B 0 +#define CONF_TCC0_POL4B 0 +#define CONF_TCC0_POL5B 0 +#define CONF_TCC0_POL6B 0 +#define CONF_TCC0_POL7B 0 +#define CONF_TCC0_SWAP0B 0 +#define CONF_TCC0_SWAP1B 0 +#define CONF_TCC0_SWAP2B 0 +#define CONF_TCC0_SWAP3B 0*/ + +/* Commented intentionally. No buffering for timers. */ +/*#define CONF_TCC0_PERB 0 +#define CONF_TCC0_CCB0 0 +#define CONF_TCC0_CCB1 0 +#define CONF_TCC0_CCB2 0 +#define CONF_TCC0_CCB3 0*/ +// + +#define CONF_TCC0_CTRLA \ + TCC_CTRLA_PRESCALER(CONF_TCC0_PRESCALER) | (CONF_TCC0_RUNSTDBY << TCC_CTRLA_RUNSTDBY_Pos) \ + | TCC_CTRLA_PRESCSYNC(CONF_TCC0_PRESCSYNC) | (CONF_TCC0_CPTEN0 << TCC_CTRLA_CPTEN0_Pos) \ + | (CONF_TCC0_CPTEN1 << TCC_CTRLA_CPTEN1_Pos) | (CONF_TCC0_CPTEN2 << TCC_CTRLA_CPTEN2_Pos) \ + | (CONF_TCC0_CPTEN3 << TCC_CTRLA_CPTEN3_Pos) | (CONF_TCC0_CPTEN4 << TCC_CTRLA_CPTEN4_Pos) \ + | (CONF_TCC0_CPTEN5 << TCC_CTRLA_CPTEN5_Pos) | (CONF_TCC0_ALOCK << TCC_CTRLA_ALOCK_Pos) +#define CONF_TCC0_CTRLB (CONF_TCC0_LUPD << TCC_CTRLBSET_LUPD_Pos) +#define CONF_TCC0_DBGCTRL (CONF_TCC0_DBGRUN << TCC_DBGCTRL_DBGRUN_Pos) +#define CONF_TCC0_EVCTRL \ + TCC_EVCTRL_CNTSEL(CONF_TCC0_CNTSEL) | (CONF_TCC0_OVFEO << TCC_EVCTRL_OVFEO_Pos) \ + | (CONF_TCC0_TRGEO << TCC_EVCTRL_TRGEO_Pos) | (CONF_TCC0_CNTEO << TCC_EVCTRL_CNTEO_Pos) \ + | (CONF_TCC0_MCEO0 << TCC_EVCTRL_MCEO0_Pos) | (CONF_TCC0_MCEI0 << TCC_EVCTRL_MCEI0_Pos) \ + | (CONF_TCC0_MCEO1 << TCC_EVCTRL_MCEO1_Pos) | (CONF_TCC0_MCEI1 << TCC_EVCTRL_MCEI1_Pos) \ + | (CONF_TCC0_MCEO2 << TCC_EVCTRL_MCEO2_Pos) | (CONF_TCC0_MCEI2 << TCC_EVCTRL_MCEI2_Pos) \ + | (CONF_TCC0_MCEO3 << TCC_EVCTRL_MCEO3_Pos) | (CONF_TCC0_MCEI3 << TCC_EVCTRL_MCEI3_Pos) \ + | (CONF_TCC0_MCEO4 << TCC_EVCTRL_MCEO4_Pos) | (CONF_TCC0_MCEI4 << TCC_EVCTRL_MCEI4_Pos) \ + | (CONF_TCC0_MCEO5 << TCC_EVCTRL_MCEO5_Pos) | (CONF_TCC0_MCEI5 << TCC_EVCTRL_MCEI5_Pos) \ + | (CONF_TCC0_TCEI0 << TCC_EVCTRL_TCEI0_Pos) | (CONF_TCC0_TCEI1 << TCC_EVCTRL_TCEI1_Pos) \ + | (CONF_TCC0_TCINV0 << TCC_EVCTRL_TCINV0_Pos) | (CONF_TCC0_TCINV1 << TCC_EVCTRL_TCINV1_Pos) \ + | TCC_EVCTRL_EVACT1(CONF_TCC0_EVACT1) | TCC_EVCTRL_EVACT0(CONF_TCC0_EVACT0) + +#include +#ifndef CONF_TCC1_ENABLE +#define CONF_TCC1_ENABLE 1 +#endif + +#ifndef CONF_TCC1_PWM_ENABLE +#define CONF_TCC1_PWM_ENABLE 1 +#endif + +// Basic settings +// TCC1 Prescaler +// No division +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 64 +// Divide by 256 +// Divide by 1024 +// This defines the TCC1 prescaler value +// tcc_prescaler +#ifndef CONF_TCC1_PRESCALER +#define CONF_TCC1_PRESCALER TCC_CTRLA_PRESCALER_DIV2_Val +#endif + +// +// TCC1 Period Value <0x000000-0xFFFFFF> +// tcc_per +#ifndef CONF_TCC1_PER +#define CONF_TCC1_PER 0x2710 +#endif +// + +// + +// PWM Waveform Output settings +// TCC1 Waveform Period Value (uS) <0x00-0xFFFFFFFF> +// The unit of this value is us. +// tcc_arch_wave_per_val +#ifndef CONF_TCC1_WAVE_PER_VAL +#define CONF_TCC1_WAVE_PER_VAL 0x28 +#endif + +// TCC1 Waveform Duty Value (0.1%) <0x00-0x03E8> +// The unit of this value is 1/1000. +// tcc_arch_wave_duty_val +#ifndef CONF_TCC1_WAVE_DUTY_VAL +#define CONF_TCC1_WAVE_DUTY_VAL 0x1f4 +#endif + +// TCC1 Waveform Channel Select <0x00-0x03> +// Index of the Compare Channel register, into which the Waveform Duty Value is written. +// Give index of the Compare Channel register here in 0x00-0x03 range. +// tcc_arch_sel_ch +#ifndef CONF_TCC1_SEL_CH +#define CONF_TCC1_SEL_CH 0x3 +#endif + +/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ +#if CONF_TCC1_PRESCALER < TCC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TCC1_PER_REG \ + ((uint32_t)(((double)CONF_TCC1_WAVE_PER_VAL * CONF_GCLK_TCC1_FREQUENCY) / 1000000 / (1 << CONF_TCC1_PRESCALER) - 1)) +#define CONF_TCC1_CCX_REG ((uint32_t)(((double)(double)CONF_TCC1_PER_REG * CONF_TCC1_WAVE_DUTY_VAL) / 1000)) + +#elif CONF_TCC1_PRESCALER == TCC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TCC1_PER_REG ((uint32_t)(((double)CONF_TCC1_WAVE_PER_VAL * CONF_GCLK_TCC1_FREQUENCY) / 64000000 - 1)) +#define CONF_TCC1_CCX_REG ((uint32_t)(((double)CONF_TCC1_PER_REG * CONF_TCC1_WAVE_DUTY_VAL) / 1000)) + +#elif CONF_TCC1_PRESCALER == TCC_CTRLA_PRESCALER_DIV256_Val +#define CONF_TCC1_PER_REG ((uint32_t)(((double)CONF_TCC1_WAVE_PER_VAL * CONF_GCLK_TCC1_FREQUENCY) / 256000000 - 1)) +#define CONF_TCC1_CCX_REG ((uint32_t)(((double)CONF_TCC1_PER_REG * CONF_TCC1_WAVE_DUTY_VAL) / 1000)) + +#elif CONF_TCC1_PRESCALER == TCC_CTRLA_PRESCALER_DIV1024_Val +#define CONF_TCC1_PER_REG ((uint32_t)(((double)CONF_TCC1_WAVE_PER_VAL * CONF_GCLK_TCC1_FREQUENCY) / 1024000000 - 1)) +#define CONF_TCC1_CCX_REG ((uint32_t)(((double)CONF_TCC1_PER_REG * CONF_TCC1_WAVE_DUTY_VAL) / 1000)) +#endif +// + +// Advanced settings +/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL A register. + * May be used by other abstractions based on TC. */ +//#define CONF_TCC1_RESOLUTION TCC_CTRLA_RESOLUTION_NONE_Val +// Run in standby +// Indicates whether the TCC1 will continue running in standby sleep mode or not +// tcc_arch_runstdby +#ifndef CONF_TCC1_RUNSTDBY +#define CONF_TCC1_RUNSTDBY 0 +#endif + +// TCC1 Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock. +// tcc_arch_prescsync +#ifndef CONF_TCC1_PRESCSYNC +#define CONF_TCC1_PRESCSYNC TCC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +// TCC1 Waveform Generation Selection +// Single-slope PWM +// Dual-slope, critical interrupt/event at ZERO (DSCRITICAL) +// Dual-slope, interrupt/event at ZERO (DSBOTTOM) +// Dual-slope, interrupt/event at Top and ZERO (DSBOTH) +// Dual-slope, interrupt/event at Top (DSTOP) +// tcc_arch_wavegen +#ifndef CONF_TCC1_WAVEGEN +#define CONF_TCC1_WAVEGEN TCC_WAVE_WAVEGEN_DSBOTTOM_Val +#endif +// TCC1 Auto Lock +// Indicates whether the TCC1 Auto Lock is enabled or not +// tcc_arch_alock +#ifndef CONF_TCC1_ALOCK +#define CONF_TCC1_ALOCK 0 +#endif + +// TCC1 Capture Channel 0 Enable +// Indicates whether the TCC1 Capture Channel 0 is enabled or not +// tcc_arch_cpten0 +#ifndef CONF_TCC1_CPTEN0 +#define CONF_TCC1_CPTEN0 0 +#endif + +// TCC1 Capture Channel 1 Enable +// Indicates whether the TCC1 Capture Channel 1 is enabled or not +// tcc_arch_cpten1 +#ifndef CONF_TCC1_CPTEN1 +#define CONF_TCC1_CPTEN1 0 +#endif + +// TCC1 Capture Channel 2 Enable +// Indicates whether the TCC1 Capture Channel 2 is enabled or not +// tcc_arch_cpten2 +#ifndef CONF_TCC1_CPTEN2 +#define CONF_TCC1_CPTEN2 0 +#endif + +// TCC1 Capture Channel 3 Enable +// Indicates whether the TCC1 Capture Channel 3 is enabled or not +// tcc_arch_cpten3 +#ifndef CONF_TCC1_CPTEN3 +#define CONF_TCC1_CPTEN3 0 +#endif + +// +// TCC1 Capture Channel 4 Enable +// Indicates whether the TCC1 Capture Channel 4 is enabled or not +// tcc_arch_cpten4 +#ifndef CONF_TCC1_CPTEN4 +#define CONF_TCC1_CPTEN4 0 +#endif +// +// +// TCC1 Capture Channel 5 Enable +// Indicates whether the TCC1 Capture Channel 5 is enabled or not +// tcc_arch_cpten5 +#ifndef CONF_TCC1_CPTEN5 +#define CONF_TCC1_CPTEN5 0 +#endif +// +// +// TCC1 Capture Channel 6 Enable +// Indicates whether the TCC1 Capture Channel 6 is enabled or not +// tcc_arch_cpten6 +#ifndef CONF_TCC1_CPTEN6 +#define CONF_TCC1_CPTEN6 0 +#endif +// +// +// TCC1 Capture Channel 7 Enable +// Indicates whether the TCC1 Capture Channel 7 is enabled or not +// tcc_arch_cpten7 +#ifndef CONF_TCC1_CPTEN7 +#define CONF_TCC1_CPTEN7 0 +#endif +// + +// TCC1 Lock update +// Indicates whether the TCC1 Lock update is enabled or not +// tcc_arch_lupd +#ifndef CONF_TCC1_LUPD +#define CONF_TCC1_LUPD 0 +#endif + +/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL B register. + * May be used by other abstractions based on TC. */ +//#define CONF_TCC1_DIR 0 +//#define CONF_TCC1_ONESHOT 0 + +/* Commented intentionally. No fault control for timers. */ +/*#define CONF_TCC1_FAULT_A_SRC TCC_FCTRLA_SRC_DISABLE_Val +#define CONF_TCC1_FAULT_A_KEEP 0 +#define CONF_TCC1_FAULT_A_QUAL 0 +#define CONF_TCC1_FAULT_A_BLANK TCC_FCTRLA_BLANK_DISABLE_Val +#define CONF_TCC1_FAULT_A_RESTART 0 +#define CONF_TCC1_FAULT_A_HALT TCC_FCTRLA_HALT_DISABLE_Val +#define CONF_TCC1_FAULT_A_CHSEL TCC_FCTRLA_CHSEL_CC0_Val +#define CONF_TCC1_FAULT_A_CAPTURE TCC_FCTRLA_CAPTURE_DISABLE_Val +#define CONF_TCC1_FAULT_A_BLACNKPRESC 0 +#define CONF_TCC1_FAULT_A_BLANKVAL 0 +#define CONF_TCC1_FAULT_A_FILTERVAL 0 + +#define CONF_TCC1_FAULT_B_SRC TCC_FCTRLB_SRC_DISABLE_Val +#define CONF_TCC1_FAULT_B_KEEP 0 +#define CONF_TCC1_FAULT_B_QUAL 0 +#define CONF_TCC1_FAULT_B_BLANK TCC_FCTRLB_BLANK_DISABLE_Val +#define CONF_TCC1_FAULT_B_RESTART 0 +#define CONF_TCC1_FAULT_B_HALT TCC_FCTRLB_HALT_DISABLE_Val +#define CONF_TCC1_FAULT_B_CHSEL TCC_FCTRLB_CHSEL_CC0_Val +#define CONF_TCC1_FAULT_B_CAPTURE TCC_FCTRLB_CAPTURE_DISABLE_Val +#define CONF_TCC1_FAULT_B_BLACNKPRESC 0 +#define CONF_TCC1_FAULT_B_BLANKVAL 0 +#define CONF_TCC1_FAULT_B_FILTERVAL 0*/ + +/* Commented intentionally. No dead-time control for timers. */ +/*#define CONF_TCC1_OTMX 0 +#define CONF_TCC1_DTIEN0 0 +#define CONF_TCC1_DTIEN1 0 +#define CONF_TCC1_DTIEN2 0 +#define CONF_TCC1_DTIEN3 0 +#define CONF_TCC1_DTHS 0*/ + +/* Commented intentionally. No driver control for timers. */ +/*#define CONF_TCC1_NRE0 0 +#define CONF_TCC1_NRE1 0 +#define CONF_TCC1_NRE2 0 +#define CONF_TCC1_NRE3 0 +#define CONF_TCC1_NRE4 0 +#define CONF_TCC1_NRE5 0 +#define CONF_TCC1_NRE6 0 +#define CONF_TCC1_NRE7 0 +#define CONF_TCC1_NVR0 0 +#define CONF_TCC1_NVR1 0 +#define CONF_TCC1_NVR2 0 +#define CONF_TCC1_NVR3 0 +#define CONF_TCC1_NVR4 0 +#define CONF_TCC1_NVR5 0 +#define CONF_TCC1_NVR6 0 +#define CONF_TCC1_NVR7 0 +#define CONF_TCC1_INVEN0 0 +#define CONF_TCC1_INVEN1 0 +#define CONF_TCC1_INVEN2 0 +#define CONF_TCC1_INVEN3 0 +#define CONF_TCC1_INVEN4 0 +#define CONF_TCC1_INVEN5 0 +#define CONF_TCC1_INVEN6 0 +#define CONF_TCC1_INVEN7 0 +#define CONF_TCC1_FILTERVAL0 0 +#define CONF_TCC1_FILTERVAL1 0*/ + +// TCC1 Debug Running Mode +// Indicates whether the TCC1 Debug Running Mode is enabled or not +// tcc_arch_dbgrun +#ifndef CONF_TCC1_DBGRUN +#define CONF_TCC1_DBGRUN 0 +#endif + +/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of Debug Control register. + * May be used by other abstractions based on TC. */ +//#define CONF_TCC1_FDDBD 0 + +// Event control +// timer_event_control +#ifndef CONF_TCC1_EVENT_CONTROL_ENABLE +#define CONF_TCC1_EVENT_CONTROL_ENABLE 1 +#endif + +// Match or Capture Channel 0 Event Output +// This bit indicates whether match/capture event on channel 0 is enabled and will be generated +// tcc_arch_mceo0 +#ifndef CONF_TCC1_MCEO0 +#define CONF_TCC1_MCEO0 0 +#endif + +// Match or Capture Channel 0 Event Input +// This bit indicates whether match/capture 0 incoming event is enabled +// tcc_arch_mcei0 +#ifndef CONF_TCC1_MCEI0 +#define CONF_TCC1_MCEI0 0 +#endif +// Match or Capture Channel 1 Event Output +// This bit indicates whether match/capture event on channel 1 is enabled and will be generated +// tcc_arch_mceo1 +#ifndef CONF_TCC1_MCEO1 +#define CONF_TCC1_MCEO1 0 +#endif + +// Match or Capture Channel 1 Event Input +// This bit indicates whether match/capture 1 incoming event is enabled +// tcc_arch_mcei1 +#ifndef CONF_TCC1_MCEI1 +#define CONF_TCC1_MCEI1 0 +#endif +// Match or Capture Channel 2 Event Output +// This bit indicates whether match/capture event on channel 2 is enabled and will be generated +// tcc_arch_mceo2 +#ifndef CONF_TCC1_MCEO2 +#define CONF_TCC1_MCEO2 0 +#endif + +// Match or Capture Channel 2 Event Input +// This bit indicates whether match/capture 2 incoming event is enabled +// tcc_arch_mcei2 +#ifndef CONF_TCC1_MCEI2 +#define CONF_TCC1_MCEI2 0 +#endif +// Match or Capture Channel 3 Event Output +// This bit indicates whether match/capture event on channel 3 is enabled and will be generated +// tcc_arch_mceo3 +#ifndef CONF_TCC1_MCEO3 +#define CONF_TCC1_MCEO3 0 +#endif + +// Match or Capture Channel 3 Event Input +// This bit indicates whether match/capture 3 incoming event is enabled +// tcc_arch_mcei3 +#ifndef CONF_TCC1_MCEI3 +#define CONF_TCC1_MCEI3 0 +#endif + +// Timer/Counter Event Input 0 +// This bit is used to enable input event 0 to the TCC +// tcc_arch_tcei0 +#ifndef CONF_TCC1_TCEI0 +#define CONF_TCC1_TCEI0 0 +#endif + +// Timer/Counter Event Input 0 Invert +// This bit inverts the event 0 input +// tcc_arch_tceinv0 +#ifndef CONF_TCC1_TCINV0 +#define CONF_TCC1_TCINV0 0 +#endif +// Timer/Counter Event Input 1 +// This bit is used to enable input event 1 to the TCC +// tcc_arch_tcei1 +#ifndef CONF_TCC1_TCEI1 +#define CONF_TCC1_TCEI1 0 +#endif + +// Timer/Counter Event Input 1 Invert +// This bit inverts the event 1 input +// tcc_arch_tceinv1 +#ifndef CONF_TCC1_TCINV1 +#define CONF_TCC1_TCINV1 0 +#endif + +// Timer/Counter Event Output +// This bit is used to enable the counter cycle event. +// tcc_arch_cnteo +#ifndef CONF_TCC1_CNTEO +#define CONF_TCC1_CNTEO 0 +#endif + +// Re-trigger Event Output +// This bit is used to enable the counter re-trigger event. +// tcc_arch_trgeo +#ifndef CONF_TCC1_TRGEO +#define CONF_TCC1_TRGEO 0 +#endif + +// Overflow/Underflow Event Output +// This bit is used to enable enable event on overflow/underflow. +// tcc_arch_ovfeo +#ifndef CONF_TCC1_OVFEO +#define CONF_TCC1_OVFEO 1 +#endif + +// Timer/Counter Interrupt and Event Output Selection +// <0=> An interrupt/event is generated when a new counter cycle starts +// <1=> An interrupt/event is generated when a counter cycle ends +// <2=> An interrupt/event is generated when a counter cycle ends, except for the first and last cycles +// <3=> An interrupt/event is generated when a new counter cycle starts or a counter cycle ends +// These bits define on which part of the counter cycle the counter event output is generated +// tcc_arch_cntsel +#ifndef CONF_TCC1_CNTSEL +#define CONF_TCC1_CNTSEL 0 +#endif + +// Timer/Counter Event Input 0 Action +// <0=>Event action disabled +// <1=>Start restart or re-trigger on event +// <2=>Count on event +// <3=>Start on event +// <4=>Increment on event +// <5=>Count on active state of asynchronous event +// <6=>Capture overflow times (Max value) +// <7=>Non-recoverable fault +// These bits define the action the TCC performs on TCE0 event input 0 +// tcc_arch_evact0 +#ifndef CONF_TCC1_EVACT0 +#define CONF_TCC1_EVACT0 0 +#endif + +// Timer/Counter Event Input 1 Action +// <0=>Event action disabled +// <1=>Re-trigger counter on event +// <2=>Direction control +// <3=>Stop counter on event +// <4=>Decrement counter on event +// <5=>Period capture value in CC0 register, pulse width capture value in CC1 register +// <6=>Period capture value in CC1 register, pulse width capture value in CC0 register +// <7=>Non-recoverable fault +// These bits define the action the TCC performs on TCE0 event input 0 +// tcc_arch_evact1 +#ifndef CONF_TCC1_EVACT1 +#define CONF_TCC1_EVACT1 0 +#endif +// + +/* Commented intentionally. No pattern control for timers. */ +/*#define CONF_TCC1_PGE0 0 +#define CONF_TCC1_PGE1 0 +#define CONF_TCC1_PGE2 0 +#define CONF_TCC1_PGE3 0 +#define CONF_TCC1_PGE4 0 +#define CONF_TCC1_PGE5 0 +#define CONF_TCC1_PGE6 0 +#define CONF_TCC1_PGE7 0 +#define CONF_TCC1_PGV0 0 +#define CONF_TCC1_PGV1 0 +#define CONF_TCC1_PGV2 0 +#define CONF_TCC1_PGV3 0 +#define CONF_TCC1_PGV4 0 +#define CONF_TCC1_PGV5 0 +#define CONF_TCC1_PGV6 0 +#define CONF_TCC1_PGV7 0*/ + +/* Commented intentionally. No pattern waveform control for timers. */ +/*#define CONF_TCC1_WAVEGEN TCC_WAVE_WAVEGEN_MFRQ_Val +#define CONF_TCC1_RAMP TCC_WAVE_RAMP_RAMP1_Val +#define CONF_TCC1_CIPEREN 0 +#define CONF_TCC1_CICCEN0 0 +#define CONF_TCC1_CICCEN1 0 +#define CONF_TCC1_CICCEN2 0 +#define CONF_TCC1_CICCEN3 0 +#define CONF_TCC1_POL0 0 +#define CONF_TCC1_POL1 0 +#define CONF_TCC1_POL2 0 +#define CONF_TCC1_POL3 0 +#define CONF_TCC1_POL4 0 +#define CONF_TCC1_POL5 0 +#define CONF_TCC1_POL6 0 +#define CONF_TCC1_POL7 0 +#define CONF_TCC1_SWAP0 0 +#define CONF_TCC1_SWAP1 0 +#define CONF_TCC1_SWAP2 0 +#define CONF_TCC1_SWAP3 0*/ + +// TCC1 Compare and Capture value 0 <0x00-0xFFFFFF> +// tcc_arch_cc0 +#ifndef CONF_TCC1_CC0 +#define CONF_TCC1_CC0 0x0 +#endif + +// TCC1 Compare and Capture value 1 <0x00-0xFFFFFF> +// tcc_arch_cc1 +#ifndef CONF_TCC1_CC1 +#define CONF_TCC1_CC1 0x0 +#endif + +// TCC1 Compare and Capture value 2 <0x00-0xFFFFFF> +// tcc_arch_cc2 +#ifndef CONF_TCC1_CC2 +#define CONF_TCC1_CC2 0x0 +#endif + +// TCC1 Compare and Capture value 3 <0x00-0xFFFFFF> +// tcc_arch_cc3 +#ifndef CONF_TCC1_CC3 +#define CONF_TCC1_CC3 0x0 +#endif + +/* Commented intentionally. No pattern control for timers. */ +/*#define CONF_TCC1_PATTB_PGEB0 0 +#define CONF_TCC1_PATTB_PGEB1 0 +#define CONF_TCC1_PATTB_PGEB2 0 +#define CONF_TCC1_PATTB_PGEB3 0 +#define CONF_TCC1_PATTB_PGEB4 0 +#define CONF_TCC1_PATTB_PGEB5 0 +#define CONF_TCC1_PATTB_PGEB6 0 +#define CONF_TCC1_PATTB_PGEB7 0 +#define CONF_TCC1_PATTB_PGVB0 0 +#define CONF_TCC1_PATTB_PGVB1 0 +#define CONF_TCC1_PATTB_PGVB2 0 +#define CONF_TCC1_PATTB_PGVB3 0 +#define CONF_TCC1_PATTB_PGVB4 0 +#define CONF_TCC1_PATTB_PGVB5 0 +#define CONF_TCC1_PATTB_PGVB6 0 +#define CONF_TCC1_PATTB_PGVB7 0*/ + +/* Commented intentionally. No waveform control for timers. */ +/*#define CONF_TCC1_WAVEGENB TCC_WAVEB_WAVEGENB_MFRQ_Val +#define CONF_TCC1_RAMPB TCC_WAVE_RAMP_RAMP1_Val +#define CONF_TCC1_CIPERENB 0 +#define CONF_TCC1_CICCEN0B 0 +#define CONF_TCC1_CICCEN1B 0 +#define CONF_TCC1_CICCEN2B 0 +#define CONF_TCC1_CICCEN3B 0 +#define CONF_TCC1_POL0B 0 +#define CONF_TCC1_POL1B 0 +#define CONF_TCC1_POL2B 0 +#define CONF_TCC1_POL3B 0 +#define CONF_TCC1_POL4B 0 +#define CONF_TCC1_POL5B 0 +#define CONF_TCC1_POL6B 0 +#define CONF_TCC1_POL7B 0 +#define CONF_TCC1_SWAP0B 0 +#define CONF_TCC1_SWAP1B 0 +#define CONF_TCC1_SWAP2B 0 +#define CONF_TCC1_SWAP3B 0*/ + +/* Commented intentionally. No buffering for timers. */ +/*#define CONF_TCC1_PERB 0 +#define CONF_TCC1_CCB0 0 +#define CONF_TCC1_CCB1 0 +#define CONF_TCC1_CCB2 0 +#define CONF_TCC1_CCB3 0*/ +// + +#define CONF_TCC1_CTRLA \ + TCC_CTRLA_PRESCALER(CONF_TCC1_PRESCALER) | (CONF_TCC1_RUNSTDBY << TCC_CTRLA_RUNSTDBY_Pos) \ + | TCC_CTRLA_PRESCSYNC(CONF_TCC1_PRESCSYNC) | (CONF_TCC1_CPTEN0 << TCC_CTRLA_CPTEN0_Pos) \ + | (CONF_TCC1_CPTEN1 << TCC_CTRLA_CPTEN1_Pos) | (CONF_TCC1_CPTEN2 << TCC_CTRLA_CPTEN2_Pos) \ + | (CONF_TCC1_CPTEN3 << TCC_CTRLA_CPTEN3_Pos) | (CONF_TCC1_ALOCK << TCC_CTRLA_ALOCK_Pos) +#define CONF_TCC1_CTRLB (CONF_TCC1_LUPD << TCC_CTRLBSET_LUPD_Pos) +#define CONF_TCC1_DBGCTRL (CONF_TCC1_DBGRUN << TCC_DBGCTRL_DBGRUN_Pos) +#define CONF_TCC1_EVCTRL \ + TCC_EVCTRL_CNTSEL(CONF_TCC1_CNTSEL) | (CONF_TCC1_OVFEO << TCC_EVCTRL_OVFEO_Pos) \ + | (CONF_TCC1_TRGEO << TCC_EVCTRL_TRGEO_Pos) | (CONF_TCC1_CNTEO << TCC_EVCTRL_CNTEO_Pos) \ + | (CONF_TCC1_MCEO0 << TCC_EVCTRL_MCEO0_Pos) | (CONF_TCC1_MCEI0 << TCC_EVCTRL_MCEI0_Pos) \ + | (CONF_TCC1_MCEO1 << TCC_EVCTRL_MCEO1_Pos) | (CONF_TCC1_MCEI1 << TCC_EVCTRL_MCEI1_Pos) \ + | (CONF_TCC1_MCEO2 << TCC_EVCTRL_MCEO2_Pos) | (CONF_TCC1_MCEI2 << TCC_EVCTRL_MCEI2_Pos) \ + | (CONF_TCC1_MCEO3 << TCC_EVCTRL_MCEO3_Pos) | (CONF_TCC1_MCEI3 << TCC_EVCTRL_MCEI3_Pos) \ + | (CONF_TCC1_TCEI0 << TCC_EVCTRL_TCEI0_Pos) | (CONF_TCC1_TCEI1 << TCC_EVCTRL_TCEI1_Pos) \ + | (CONF_TCC1_TCINV0 << TCC_EVCTRL_TCINV0_Pos) | (CONF_TCC1_TCINV1 << TCC_EVCTRL_TCINV1_Pos) \ + | TCC_EVCTRL_EVACT1(CONF_TCC1_EVACT1) | TCC_EVCTRL_EVACT0(CONF_TCC1_EVACT0) + +// <<< end of configuration section >>> + +#endif // HPL_TCC_CONFIG_H diff --git a/BLDC_E54/BLDC_E54/Debug/bldc.o b/BLDC_E54/BLDC_E54/Debug/bldc.o index 5960b2e..46ec334 100644 Binary files a/BLDC_E54/BLDC_E54/Debug/bldc.o and b/BLDC_E54/BLDC_E54/Debug/bldc.o differ diff --git a/BLDC_E54/BLDC_E54/Debug/driver_init.o b/BLDC_E54/BLDC_E54/Debug/driver_init.o index 793b47b..9d04b5f 100644 Binary files a/BLDC_E54/BLDC_E54/Debug/driver_init.o and b/BLDC_E54/BLDC_E54/Debug/driver_init.o differ diff --git a/BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.o b/BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.o index 08ff890..5d4dfc0 100644 Binary files a/BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.o and b/BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.o differ diff --git a/BLDC_E54/BLDC_E54/Debug/hpl/dmac/hpl_dmac.o b/BLDC_E54/BLDC_E54/Debug/hpl/dmac/hpl_dmac.o index a73eb57..1021fbe 100644 Binary files a/BLDC_E54/BLDC_E54/Debug/hpl/dmac/hpl_dmac.o and b/BLDC_E54/BLDC_E54/Debug/hpl/dmac/hpl_dmac.o differ diff --git a/BLDC_E54/BLDC_E54/Debug/hpl/evsys/hpl_evsys.o b/BLDC_E54/BLDC_E54/Debug/hpl/evsys/hpl_evsys.o index 77ef915..dfd950b 100644 Binary files a/BLDC_E54/BLDC_E54/Debug/hpl/evsys/hpl_evsys.o and b/BLDC_E54/BLDC_E54/Debug/hpl/evsys/hpl_evsys.o differ diff --git a/BLDC_E54/BLDC_E54/Debug/main.o b/BLDC_E54/BLDC_E54/Debug/main.o index 638bca8..5f2bbae 100644 Binary files a/BLDC_E54/BLDC_E54/Debug/main.o and b/BLDC_E54/BLDC_E54/Debug/main.o differ diff --git a/BLDC_E54/BLDC_E54/bldc.c b/BLDC_E54/BLDC_E54/bldc.c index e74110f..f33343c 100644 --- a/BLDC_E54/BLDC_E54/bldc.c +++ b/BLDC_E54/BLDC_E54/bldc.c @@ -332,10 +332,10 @@ void exec_commutation(void) // ---------------------------------------------------------------------- // Multi Motor Register Masking // ---------------------------------------------------------------------- - volatile uint16_t temp_M1 = COMMUTATION_PATTERN_M1[Motor1.motor_status.currentHallPattern]; - volatile uint16_t temp_M2 = COMMUTATION_PATTERN_M2[Motor2.motor_status.currentHallPattern]; - volatile uint16_t temp_M3_tcc1_des = COMMUTATION_PATTERN_M1[Motor3.motor_status.currentHallPattern] & m3_TCC1_mask; - volatile uint16_t temp_M3_tcc0_des = COMMUTATION_PATTERN_M2[Motor3.motor_status.currentHallPattern] & m3_TCC0_mask; + volatile uint16_t temp_M1 = COMMUTATION_PATTERN_M1[Motor1.motor_status.currentHallPattern + Motor1.motor_setpoints.directionOffset]; + volatile uint16_t temp_M2 = COMMUTATION_PATTERN_M2[Motor2.motor_status.currentHallPattern + Motor2.motor_setpoints.directionOffset]; + volatile uint16_t temp_M3_tcc1_des = COMMUTATION_PATTERN_M1[Motor3.motor_status.currentHallPattern + Motor3.motor_setpoints.directionOffset] & m3_TCC1_mask; + volatile uint16_t temp_M3_tcc0_des = COMMUTATION_PATTERN_M2[Motor3.motor_status.currentHallPattern + Motor3.motor_setpoints.directionOffset] & m3_TCC0_mask; /* Zero target bits */ temp_M1 &= m3_TCC1_inv_mask; temp_M2 &= m3_TCC0_inv_mask; @@ -353,7 +353,7 @@ void exec_commutation(void) // Set Remaining GPIO lines responsible for M3 Commutation // ---------------------------------------------------------------------- ///* GPIO En Pin Setting for M3 */ - switch(Motor3.motor_status.currentHallPattern) + switch(Motor3.motor_status.currentHallPattern + Motor3.motor_setpoints.directionOffset) { // REG_PORT_OUTSET0 = Port A // REG_PORT_OUTSET1 = Port B @@ -383,32 +383,10 @@ void exec_commutation(void) // Set Calculated Duty Cycles // ---------------------------------------------------------------------- Motor1.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle); - Motor2.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle+1); - Motor3.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle+2); + //Motor2.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle); + //Motor3.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle); - //TCC1->CCBUF->reg = (uint16_t)Motor1.motor_status.duty_cycle; - //hri_tcc_write_PATTBUF_reg(TCC1, (COMMUTATION_PATTERN[(Motor1.currentHallPattern + Motor1.directionOffset)])); - - //hri_tcc_write_CCBUF_CCBUF_bf(TCC1, 0, 150); - //hri_tcc_write_CCBUF_CCBUF_bf(TCC1, 0, Motor1.duty_cycle); - - - //if ((Motor1.currentHallPattern != INVALID_HALL_0) && (Motor1.currentHallPattern != INVALID_HALL_7)) - //{ - // hri_tcc_write_PATTBUF_reg(TCC1, COMMUTATION_PATTERN[(Motor1.currentHallPattern + Motor1.directionOffset)]); - //} else { - //hall error - // return; - //} - - //hri_tcc_write_CCBUF_reg(TCC1, 0, Motor1.duty_cycle); - - /* Update the next pattern in the pattern array */ - //Motor1.nextHallPattern = HALL_PATTERN_ARRAY[(Motor1.currentHallPattern+Motor1.directionOffset)]; - //} - //volatile uint8_t curHallState = hallCode & 0x07; //ABC format - //volatile uint8_t curHallState = get_hall_state(); //ABC format Motor1.motor_status.cur_comm_step = MOTOR_COMMUTATION_STEPS[Motor1.motor_status.currentHallPattern]; volatile int8_t step_change = Motor1.motor_status.cur_comm_step - Motor1.motor_status.prev_comm_step; @@ -418,13 +396,13 @@ void exec_commutation(void) case -5: Motor1.motor_status.Num_Steps = Motor1.motor_status.Num_Steps+1; Motor1.motor_status.actualDirection = CW; - //Motor1.directionOffset = DIRECTION_CW_OFFSET; + Motor1.motor_setpoints.directionOffset = DIRECTION_CW_OFFSET; break; case -1: case 5: Motor1.motor_status.Num_Steps = Motor1.motor_status.Num_Steps-1; Motor1.motor_status.actualDirection = CCW; - //Motor1.directionOffset = DIRECTION_CCW_OFFSET; + //Motor1.motor_setpoints.directionOffset = DIRECTION_CCW_OFFSET; break; default: // do nothing @@ -520,7 +498,7 @@ void BLDC_runSpeedCntl(BLDCMotor_t *motor, volatile float speedfbk, volatile flo { motor->controllers.Pid_Speed.Fbk_pu = speedfbk; - motor->controllers.Pid_Speed.Ref_pu = f_clamp(speedRef, -MAX_VEL, MAX_VEL); // Convert Speed Ref to Q16 Format + motor->controllers.Pid_Speed.Ref_pu = f_clamp(speedRef, -MOTOR_MAX_SPD_RPM, MOTOR_MAX_SPD_RPM); // Convert Speed Ref to Q16 Format if (applicationStatus.currentstate == MOTOR_V_CTRL_STATE) { @@ -556,8 +534,8 @@ void BLDC_runSpeedCntl(BLDCMotor_t *motor, volatile float speedfbk, volatile flo void BLDC_runPosCntl(BLDCMotor_t *motor, int16_t posfbk, int16_t posRef) { /* Output Pu in RPM */ - motor->controllers.Pi_Pos.OutMax_pu = MAX_VEL; - motor->controllers.Pi_Pos.OutMin_pu = -MAX_VEL; + motor->controllers.Pi_Pos.OutMax_pu = MOTOR_MAX_SPD_RPM; + motor->controllers.Pi_Pos.OutMin_pu = -MOTOR_MAX_SPD_RPM; motor->controllers.Pi_Pos.Fbk_pu = posfbk; motor->controllers.Pi_Pos.Ref_pu = posRef; PI_run_series(&motor->controllers.Pi_Pos); diff --git a/BLDC_E54/BLDC_E54/bldc.h b/BLDC_E54/BLDC_E54/bldc.h index 1ad1291..bda5913 100644 --- a/BLDC_E54/BLDC_E54/bldc.h +++ b/BLDC_E54/BLDC_E54/bldc.h @@ -153,9 +153,8 @@ volatile BLDCMotor_t Motor2; volatile BLDCMotor_t Motor3; -static uint8_t currentSensorCount = 4; -static uint32_t adc_seq_regs[4] = {0x1802, 0x1803, 0x1802, 0x1803}; -static volatile uint16_t adc_res[4] = {0}; +static uint32_t adc_seq_regs[6] = {0x1802, 0x1803, 0x1802, 0x1803, 0x1802, 0x1803}; +static volatile uint16_t adc_res[6] = {0}; static volatile bool adc_dma_done = 0; struct _dma_resource *adc_sram_dma_resource; diff --git a/BLDC_E54/BLDC_E54/configuration.h b/BLDC_E54/BLDC_E54/configuration.h index 6690b29..fbc69f7 100644 --- a/BLDC_E54/BLDC_E54/configuration.h +++ b/BLDC_E54/BLDC_E54/configuration.h @@ -20,24 +20,24 @@ #define DMAC_CHANNEL_ADC_SRAM 3U -void dummy2 (void){ - while(1); -} - -void dummy3 (void){ - while(1); -} - -void dummy4 (void){ - while(1); -} -void dummy5 (void){ - while(1); -} - -void dummy6 (void){ - while(1); -} +//void dummy2 (void){ + //while(1); +//} +// +//void dummy3 (void){ + //while(1); +//} +// +//void dummy4 (void){ + //while(1); +//} +//void dummy5 (void){ + //while(1); +//} +// +//void dummy6 (void){ + //while(1); +//} inline void configure_tcc_pwm(void) { @@ -129,13 +129,13 @@ inline void adc_dmac_sequence_init() * next descriptor address, data count and Enable the DMAC Channel */ _dma_set_source_address(DMAC_CHANNEL_ADC_SEQ, (const void *)adc_seq_regs); _dma_set_destination_address(DMAC_CHANNEL_ADC_SEQ, (const void *)&ADC0->DSEQDATA.reg); - _dma_set_data_amount(DMAC_CHANNEL_ADC_SEQ, 4); + _dma_set_data_amount(DMAC_CHANNEL_ADC_SEQ, 6); _dma_set_next_descriptor(DMAC_CHANNEL_ADC_SEQ, DMAC_CHANNEL_ADC_SEQ); _dma_enable_transaction(DMAC_CHANNEL_ADC_SEQ, false); - _dma_get_channel_resource(&adc_dmac_sequence_resource, DMAC_CHANNEL_ADC_SEQ); - adc_dmac_sequence_resource[0].dma_cb.error = dummy2; - adc_dmac_sequence_resource[0].dma_cb.suspend = dummy3; - adc_dmac_sequence_resource[0].dma_cb.transfer_done = dummy4; + //_dma_get_channel_resource(&adc_dmac_sequence_resource, DMAC_CHANNEL_ADC_SEQ); + //adc_dmac_sequence_resource[0].dma_cb.error = dummy2; + //adc_dmac_sequence_resource[0].dma_cb.suspend = dummy3; + //adc_dmac_sequence_resource[0].dma_cb.transfer_done = dummy4; hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[2], 0x01); //Suspend @@ -147,13 +147,12 @@ inline void adc_sram_dmac_init() * next descriptor address, data count and Enable the DMAC Channel */ _dma_set_source_address(DMAC_CHANNEL_ADC_SRAM, (const void *)&ADC0->RESULT.reg); _dma_set_destination_address(DMAC_CHANNEL_ADC_SRAM, (const void *)adc_res); - _dma_set_data_amount(DMAC_CHANNEL_ADC_SRAM, 4); + _dma_set_data_amount(DMAC_CHANNEL_ADC_SRAM, 6); _dma_set_irq_state(DMAC_CHANNEL_ADC_SRAM, DMA_TRANSFER_COMPLETE_CB, true); _dma_get_channel_resource(&adc_sram_dma_resource, DMAC_CHANNEL_ADC_SRAM); adc_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback; - adc_sram_dma_resource[0].dma_cb.error = dummy6; - adc_sram_dma_resource[0].dma_cb.suspend = dummy5; - + //adc_sram_dma_resource[0].dma_cb.error = dummy6; + //adc_sram_dma_resource[0].dma_cb.suspend = dummy5; _dma_set_next_descriptor(DMAC_CHANNEL_ADC_SRAM, DMAC_CHANNEL_ADC_SRAM); _dma_enable_transaction(DMAC_CHANNEL_ADC_SRAM, false); } diff --git a/BLDC_E54/BLDC_E54/driver_init.c b/BLDC_E54/BLDC_E54/driver_init.c index 9cef5b4..3df62a2 100644 --- a/BLDC_E54/BLDC_E54/driver_init.c +++ b/BLDC_E54/BLDC_E54/driver_init.c @@ -97,6 +97,7 @@ void EXTERNAL_IRQ_0_init(void) void EVENT_SYSTEM_0_init(void) { hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_1, CONF_GCLK_EVSYS_CHANNEL_1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_mclk_set_APBBMASK_EVSYS_bit(MCLK); diff --git a/BLDC_E54/BLDC_E54/ethercat/ethercat_e54.c b/BLDC_E54/BLDC_E54/ethercat/ethercat_e54.c index b822f00..2e41e2c 100644 --- a/BLDC_E54/BLDC_E54/ethercat/ethercat_e54.c +++ b/BLDC_E54/BLDC_E54/ethercat/ethercat_e54.c @@ -43,8 +43,8 @@ void update_telemetry(void) *motor_currentPHC = convert_to_mA(Motor1.Iphase_pu.C); *motor_currentBUS = convert_to_mA(Motor1.Iphase_pu.Bus); *hall_state = Motor1.motor_status.currentHallPattern; - *Spare_byte1 = Motor1.motor_status.actualDirection; - //*Spare_1 = 0; + *Spare_byte1 = Motor1.motor_setpoints.directionOffset; + *Spare_1 = Motor1.motor_status.actualDirection; //*Spare_2 = 0; } diff --git a/BLDC_E54/BLDC_E54/ethercat/ethercat_slave_def.h b/BLDC_E54/BLDC_E54/ethercat/ethercat_slave_def.h index 538b672..b38c744 100644 --- a/BLDC_E54/BLDC_E54/ethercat/ethercat_slave_def.h +++ b/BLDC_E54/BLDC_E54/ethercat/ethercat_slave_def.h @@ -14,7 +14,7 @@ //Write To Ecat Total Bytes (38 bytes) //write (2 Bytes) static volatile uint8_t *status =&ram_buffer[ram_wr_start]; -static volatile uint8_t *state =(((uint8_t *)&ram_buffer[ram_wr_start])+1); +static volatile uint8_t *state =(((uint8_t *)&ram_buffer[ram_wr_start])+1); //Joint (10 Bytes) static volatile int16_t *joint_rel_position =&ram_buffer[ram_wr_start+1]; static volatile int16_t *joint_revolution =&ram_buffer[ram_wr_start+2]; @@ -44,7 +44,7 @@ static volatile uint8_t *control_set =(((uint8_t *)&ram_buffer[ram_rd_start])+ // (34 Byte) static volatile int16_t *desired_position =&ram_buffer[ram_rd_start+1]; static volatile int16_t *desired_speed =&ram_buffer[ram_rd_start+2]; -static volatile int16_t *desired_torque =&ram_buffer[ram_rd_start+3]; +static volatile int16_t *desired_torque =&ram_buffer[ram_rd_start+3]; static volatile int16_t *i_kp =&ram_buffer[ram_rd_start+4]; static volatile int16_t *i_ki =&ram_buffer[ram_rd_start+5]; static volatile int16_t *v_kp =&ram_buffer[ram_rd_start+6]; diff --git a/BLDC_E54/BLDC_E54/hal/documentation/adc_sync.rst b/BLDC_E54/BLDC_E54/hal/documentation/adc_sync.rst new file mode 100644 index 0000000..d189565 --- /dev/null +++ b/BLDC_E54/BLDC_E54/hal/documentation/adc_sync.rst @@ -0,0 +1,74 @@ +====================== +ADC Synchronous driver +====================== + +An ADC (Analog-to-Digital Converter) converts analog signals to digital values. +A reference signal with a known voltage level is quantified into equally +sized chunks, each representing a digital value from 0 to the highest number +possible with the bit resolution supported by the ADC. The input voltage +measured by the ADC is compared against these chunks and the chunk with the +closest voltage level defines the digital value that can be used to represent +the analog input voltage level. + +Usually an ADC can operate in either differential or single-ended mode. +In differential mode two signals (V+ and V-) are compared against each other +and the resulting digital value represents the relative voltage level between +V+ and V-. This means that if the input voltage level on V+ is lower than on +V- the digital value is negative, which also means that in differential +mode one bit is lost to the sign. In single-ended mode only V+ is compared +against the reference voltage, and the resulting digital value can only be +positive, but the full bit-range of the ADC can be used. + +Usually multiple resolutions are supported by the ADC, lower resolution can +reduce the conversion time, but lose accuracy. + +Some ADCs has a gain stage on the input lines which can be used to increase the +dynamic range. The default gain value is usually x1, which means that the +conversion range is from 0V to the reference voltage. +Applications can change the gain stage, to increase or reduce the conversion +range. + +The window mode allows the conversion result to be compared to a set of +predefined threshold values. Applications can use callback function to monitor +if the conversion result exceeds predefined threshold value. + +Usually multiple reference voltages are supported by the ADC, both internal and +external with difference voltage levels. The reference voltage have an impact +on the accuracy, and should be selected to cover the full range of the analog +input signal and never less than the expected maximum input voltage. + +There are two conversion modes supported by ADC, single shot and free running. +In single shot mode the ADC only make one conversion when triggered by the +application, in free running mode it continues to make conversion from it +is triggered until it is stopped by the application. When window monitoring, +the ADC should be set to free running mode. + +Features +-------- +* Initialization and de-initialization +* Support multiple Conversion Mode, Single or Free run +* Start ADC Conversion +* Read Conversion Result + +Applications +------------ +* Measurement of internal sensor. E.g., MCU internal temperature sensor value. +* Measurement of external sensor. E.g., Temperature, humidity sensor value. +* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave. + +Dependencies +------------ +* ADC hardware + +Concurrency +----------- +N/A + +Limitations +----------- +N/A + +Knows issues and workarounds +---------------------------- +N/A + diff --git a/BLDC_E54/BLDC_E54/hal/documentation/pwm.rst b/BLDC_E54/BLDC_E54/hal/documentation/pwm.rst new file mode 100644 index 0000000..71785c6 --- /dev/null +++ b/BLDC_E54/BLDC_E54/hal/documentation/pwm.rst @@ -0,0 +1,53 @@ +The PWM Driver(bare-bone) +========================= + +Pulse-width modulation (PWM) is used to create an analog behavior +digitally by controlling the amount of power transferred to the +connected peripheral. This is achieved by controlling the high period +(duty-cycle) of a periodic signal. + +User can change the period or duty cycle whenever PWM is running. The +function pwm_set_parameters is used to configure these two parameters. +Note these are raw register values and the parameter duty_cycle means +the period of first half during one cycle, which should be not beyond +total period value. + +In addition, user can also get multi PWM channels output from different +peripherals at the same time, which is implemented more flexible by the +function pointers. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Run-time control of PWM duty-cycle and period +* Notifications about errors and one PWM cycle is done + +Applications +------------ + +Motor control, ballast, LED, H-bridge, power converters, and +other types of power control applications. + +Dependencies +------------ + +The peripheral which can perform waveform generation like frequency +generation and pulse-width modulation, such as Timer/Counter. + +Concurrency +----------- + +N/A + +Limitations +----------- + +The current driver doesn't support the features like recoverable, +non-recoverable faults, dithering, dead-time insertion. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/BLDC_E54/BLDC_E54/hal/include/hal_adc_sync.h b/BLDC_E54/BLDC_E54/hal/include/hal_adc_sync.h new file mode 100644 index 0000000..1b66e3d --- /dev/null +++ b/BLDC_E54/BLDC_E54/hal/include/hal_adc_sync.h @@ -0,0 +1,277 @@ +/** + * \file + * + * \brief ADC functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ADC_SYNC_H_INCLUDED +#define _HAL_ADC_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_adc_sync + * + * @{ + */ + +/** + * \brief ADC descriptor + * + * The ADC descriptor forward declaration. + */ +struct adc_sync_descriptor; + +/** + * \brief ADC descriptor + */ +struct adc_sync_descriptor { + /** ADC device */ + struct _adc_sync_device device; +}; + +/** + * \brief Initialize ADC + * + * This function initializes the given ADC descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[out] descr An ADC descriptor to initialize + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to a set of functions pointers + * + * \return Initialization status. + */ +int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize ADC + * + * This function deinitializes the given ADC descriptor. + * It checks if the given hardware is initialized and if the given hardware is + * permitted to be deinitialized. + * + * \param[in] descr An ADC descriptor to deinitialize + * + * \return De-initialization status. + */ +int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr); + +/** + * \brief Enable ADC + * + * Use this function to set the ADC peripheral to enabled state. + * + * \param[in] descr Pointer to the ADC descriptor + * \param[in] channel Channel number + * + * \return Operation status + * + */ +int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel); + +/** + * \brief Disable ADC + * + * Use this function to set the ADC peripheral to disabled state. + * + * \param[in] descr Pointer to the ADC descriptor + * \param[in] channel Channel number + * + * \return Operation status + * + */ +int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel); + +/** + * \brief Read data from ADC + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] channel Channel number + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, + const uint16_t length); + +/** + * \brief Set ADC reference source + * + * This function sets ADC reference source. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] reference A reference source to set + * + * \return Status of the ADC reference source setting. + */ +int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference); + +/** + * \brief Set ADC resolution + * + * This function sets ADC resolution. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] resolution A resolution to set + * + * \return Status of the ADC resolution setting. + */ +int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution); + +/** + * \brief Set ADC input source of a channel + * + * This function sets ADC positive and negative input sources. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] pos_input A positive input source to set + * \param[in] neg_input A negative input source to set + * \param[in] channel Channel number + * + * \return Status of the ADC channels setting. + */ +int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel); + +/** + * \brief Set ADC conversion mode + * + * This function sets ADC conversion mode. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] mode A conversion mode to set + * + * \return Status of the ADC conversion mode setting. + */ +int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode); + +/** + * \brief Set ADC differential mode + * + * This function sets ADC differential mode. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] channel Channel number + * \param[in] mode A differential mode to set + * + * \return Status of the ADC differential mode setting. + */ +int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel, + const enum adc_differential_mode mode); + +/** + * \brief Set ADC channel gain + * + * This function sets ADC channel gain. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] channel Channel number + * \param[in] gain A gain to set + * + * \return Status of the ADC gain setting. + */ +int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, + const adc_gain_t gain); + +/** + * \brief Set ADC window mode + * + * This function sets ADC window mode. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] mode A window mode to set + * + * \return Status of the ADC window mode setting. + */ +int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode); + +/** + * \brief Set ADC thresholds + * + * This function sets ADC positive and negative thresholds. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] low_threshold A lower thresholds to set + * \param[in] up_threshold An upper thresholds to set + * + * \return Status of the ADC thresholds setting. + */ +int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold); + +/** + * \brief Retrieve threshold state + * + * This function retrieves ADC threshold state. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[out] state The threshold state + * + * \return The state of ADC thresholds state retrieving. + */ +int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, + adc_threshold_status_t *const state); + +/** + * \brief Check if conversion is complete + * + * This function checks if the ADC has finished the conversion. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] channel Channel number + * + * \return The status of ADC conversion completion checking. + * \retval 1 The conversion is complete + * \retval 0 The conversion is not complete + */ +int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t adc_sync_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#include + +#endif /* _HAL_ADC_SYNC_H_INCLUDED */ diff --git a/BLDC_E54/BLDC_E54/hal/include/hal_pwm.h b/BLDC_E54/BLDC_E54/hal/include/hal_pwm.h new file mode 100644 index 0000000..c8ed842 --- /dev/null +++ b/BLDC_E54/BLDC_E54/hal/include/hal_pwm.h @@ -0,0 +1,151 @@ +/** + * \file + * + * \brief PWM functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HAL_PWM_H_INCLUDED +#define HAL_PWM_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_pwm_async + * + *@{ + */ + +/** + * \brief PWM descriptor + * + * The PWM descriptor forward declaration. + */ +struct pwm_descriptor; + +/** + * \brief PWM callback type + */ +typedef void (*pwm_cb_t)(const struct pwm_descriptor *const descr); + +/** + * \brief PWM callback types + */ +enum pwm_callback_type { PWM_PERIOD_CB, PWM_ERROR_CB }; + +/** + * \brief PWM callbacks + */ +struct pwm_callbacks { + pwm_cb_t period; + pwm_cb_t error; +}; + +/** \brief PWM descriptor + */ +struct pwm_descriptor { + /** PWM device */ + struct _pwm_device device; + /** PWM callback structure */ + struct pwm_callbacks pwm_cb; +}; + +/** \brief Initialize the PWM HAL instance and hardware + * + * \param[in] descr Pointer to the HAL PWM descriptor + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to a set of functions pointers + * + * \return Operation status. + */ +int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func); + +/** \brief Deinitialize the PWM HAL instance and hardware + * + * \param[in] descr Pointer to the HAL PWM descriptor + * + * \return Operation status. + */ +int32_t pwm_deinit(struct pwm_descriptor *const descr); + +/** \brief PWM output start + * + * \param[in] descr Pointer to the HAL PWM descriptor + * + * \return Operation status. + */ +int32_t pwm_enable(struct pwm_descriptor *const descr); + +/** \brief PWM output stop + * + * \param[in] descr Pointer to the HAL PWM descriptor + * + * \return Operation status. + */ +int32_t pwm_disable(struct pwm_descriptor *const descr); + +/** \brief Register PWM callback + * + * \param[in] descr Pointer to the HAL PWM descriptor + * \param[in] type Callback type + * \param[in] cb A callback function, passing NULL de-registers callback + * + * \return Operation status. + * \retval 0 Success + * \retval -1 Error + */ +int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb); + +/** \brief Change PWM parameter + * + * \param[in] descr Pointer to the HAL PWM descriptor + * \param[in] period Total period of one PWM cycle + * \param[in] duty_cycle Period of PWM first half during one cycle + * + * \return Operation status. + */ +int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, + const pwm_period_t duty_cycle); + +/** \brief Get PWM driver version + * + * \return Current driver version. + */ +uint32_t pwm_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_PWM;_H_INCLUDED */ diff --git a/BLDC_E54/BLDC_E54/hal/include/hpl_pwm.h b/BLDC_E54/BLDC_E54/hal/include/hpl_pwm.h new file mode 100644 index 0000000..ff87052 --- /dev/null +++ b/BLDC_E54/BLDC_E54/hal/include/hpl_pwm.h @@ -0,0 +1,193 @@ +/** + * \file + * + * \brief PWM related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_PWM_H_INCLUDED +#define _HPL_PWM_H_INCLUDED + +/** + * \addtogroup HPL PWM + * + * \section hpl_pwm_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief PWM callback types + */ +enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB }; + +/** + * \brief PWM pulse-width period + */ +typedef uint32_t pwm_period_t; + +/** + * \brief PWM device structure + * + * The PWM device structure forward declaration. + */ +struct _pwm_device; + +/** + * \brief PWM interrupt callbacks + */ +struct _pwm_callback { + void (*pwm_period_cb)(struct _pwm_device *device); + void (*pwm_error_cb)(struct _pwm_device *device); +}; + +/** + * \brief PWM descriptor device structure + */ +struct _pwm_device { + struct _pwm_callback callback; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief PWM functions, pointers to low-level functions + */ +struct _pwm_hpl_interface { + int32_t (*init)(struct _pwm_device *const device, void *const hw); + void (*deinit)(struct _pwm_device *const device); + void (*start_pwm)(struct _pwm_device *const device); + void (*stop_pwm)(struct _pwm_device *const device); + void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + bool (*is_pwm_enabled)(const struct _pwm_device *const device); + pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device); + uint32_t (*pwm_get_duty)(const struct _pwm_device *const device); + void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); +}; +/** + * \brief Initialize TC + * + * This function does low level TC configuration. + * + * \param[in] device The pointer to PWM device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _pwm_init(struct _pwm_device *const device, void *const hw); + +/** + * \brief Deinitialize TC + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_deinit(struct _pwm_device *const device); + +/** + * \brief Retrieve offset of the given tc hardware instance + * + * \param[in] device The pointer to PWM device instance + * + * \return The offset of the given tc hardware instance + */ +uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device); + +/** + * \brief Start hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_enable(struct _pwm_device *const device); + +/** + * \brief Stop hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_disable(struct _pwm_device *const device); + +/** + * \brief Set pwm parameter + * + * \param[in] device The pointer to PWM device instance + * \param[in] period Total period of one PWM cycle. + * \param[in] duty_cycle Period of PWM first half during one cycle. + */ +void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + +/** + * \brief Check if pwm is working + * + * \param[in] device The pointer to PWM device instance + * + * \return Check status. + * \retval true The given pwm is working + * \retval false The given pwm is not working + */ +bool _pwm_is_enabled(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform period value + * + * \param[in] device The pointer to PWM device instance + * + * \return Period value. + */ +pwm_period_t _pwm_get_period(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform duty cycle value + * + * \param[in] device The pointer to PWM device instance + * + * \return Duty cycle value + */ +uint32_t _pwm_get_duty(const struct _pwm_device *const device); + +/** + * \brief Enable/disable PWM interrupt + * + * param[in] device The pointer to PWM device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_PWM_H_INCLUDED */ diff --git a/BLDC_E54/BLDC_E54/hal/include/hpl_timer.h b/BLDC_E54/BLDC_E54/hal/include/hpl_timer.h new file mode 100644 index 0000000..9bdfbb7 --- /dev/null +++ b/BLDC_E54/BLDC_E54/hal/include/hpl_timer.h @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief Timer related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIMER_H_INCLUDED +#define _HPL_TIMER_H_INCLUDED + +/** + * \addtogroup HPL Timer + * + * \section hpl_timer_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Timer device structure + * + * The Timer device structure forward declaration. + */ +struct _timer_device; + +/** + * \brief Timer interrupt callbacks + */ +struct _timer_callbacks { + void (*period_expired)(struct _timer_device *device); +}; + +/** + * \brief Timer device structure + */ +struct _timer_device { + struct _timer_callbacks timer_cb; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief Timer functions, pointers to low-level functions + */ +struct _timer_hpl_interface { + int32_t (*init)(struct _timer_device *const device, void *const hw); + void (*deinit)(struct _timer_device *const device); + void (*start_timer)(struct _timer_device *const device); + void (*stop_timer)(struct _timer_device *const device); + void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); + uint32_t (*get_period)(const struct _timer_device *const device); + bool (*is_timer_started)(const struct _timer_device *const device); + void (*set_timer_irq)(struct _timer_device *const device); +}; +/** + * \brief Initialize TCC + * + * This function does low level TCC configuration. + * + * \param[in] device The pointer to timer device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _timer_init(struct _timer_device *const device, void *const hw); + +/** + * \brief Deinitialize TCC + * + * \param[in] device The pointer to timer device instance + */ +void _timer_deinit(struct _timer_device *const device); + +/** + * \brief Start hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_start(struct _timer_device *const device); + +/** + * \brief Stop hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_stop(struct _timer_device *const device); + +/** + * \brief Set timer period + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); + +/** + * \brief Retrieve timer period + * + * \param[in] device The pointer to timer device instance + * + * \return Timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const device); + +/** + * \brief Check if timer is running + * + * \param[in] device The pointer to timer device instance + * + * \return Check status. + * \retval true The given timer is running + * \retval false The given timer is not running + */ +bool _timer_is_started(const struct _timer_device *const device); + +/** + * \brief Set timer IRQ + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_irq(struct _timer_device *const device); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIMER_H_INCLUDED */ diff --git a/BLDC_E54/BLDC_E54/hal/src/hal_adc_sync.c b/BLDC_E54/BLDC_E54/hal/src/hal_adc_sync.c new file mode 100644 index 0000000..33e0d92 --- /dev/null +++ b/BLDC_E54/BLDC_E54/hal/src/hal_adc_sync.c @@ -0,0 +1,244 @@ +/** + * \file + * + * \brief ADC functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +/** + * \brief Indicates HAL being compiled. Must be defined before including. + */ +#define _COMPILING_HAL + +#include "hal_adc_sync.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Maximum amount of ADC interface instances + */ +#define MAX_ADC_AMOUNT ADC_INST_NUM + +/** + * \brief Initialize ADC + */ +int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func) +{ + ASSERT(descr && hw); + + return _adc_sync_init(&descr->device, hw); +} + +/** + * \brief Deinitialize ADC + */ +int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr) +{ + ASSERT(descr); + _adc_sync_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Enable ADC + */ +int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel) +{ + ASSERT(descr); + _adc_sync_enable_channel(&descr->device, channel); + + return ERR_NONE; +} + +/** + * \brief Disable ADC + */ +int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel) +{ + ASSERT(descr); + _adc_sync_disable_channel(&descr->device, channel); + return ERR_NONE; +} + +/* + * \brief Read data from ADC + */ +int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, + const uint16_t length) +{ + uint8_t data_size; + uint16_t offset = 0; + + ASSERT(descr && buffer && length); + data_size = _adc_sync_get_data_size(&descr->device); + ASSERT(!(length % data_size)); + + do { + uint16_t result; + _adc_sync_convert(&descr->device); + + while (!_adc_sync_is_channel_conversion_done(&descr->device, channel)) + ; + + result = _adc_sync_read_channel_data(&descr->device, channel); + buffer[offset] = result; + if (1 < data_size) { + buffer[offset + 1] = result >> 8; + } + offset += data_size; + } while (offset < length); + + return offset; +} + +/** + * \brief Set ADC reference source + */ +int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference) +{ + ASSERT(descr); + _adc_sync_set_reference_source(&descr->device, reference); + + return ERR_NONE; +} + +/** + * \brief Set ADC resolution + */ +int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution) +{ + ASSERT(descr); + _adc_sync_set_resolution(&descr->device, resolution); + + return ERR_NONE; +} + +/** + * \brief Set ADC input source of a channel + */ +int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel) +{ + ASSERT(descr); + _adc_sync_set_inputs(&descr->device, pos_input, neg_input, channel); + + return ERR_NONE; +} + +/** + * \brief Set ADC thresholds + */ +int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold) +{ + ASSERT(descr); + _adc_sync_set_thresholds(&descr->device, low_threshold, up_threshold); + + return ERR_NONE; +} + +/** + * \brief Set ADC gain + */ +int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, const adc_gain_t gain) +{ + ASSERT(descr); + _adc_sync_set_channel_gain(&descr->device, channel, gain); + + return ERR_NONE; +} + +/** + * \brief Set ADC conversion mode + */ +int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode) +{ + ASSERT(descr); + _adc_sync_set_conversion_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set ADC differential mode + */ +int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel, + const enum adc_differential_mode mode) +{ + ASSERT(descr); + _adc_sync_set_channel_differential_mode(&descr->device, channel, mode); + + return ERR_NONE; +} + +/** + * \brief Set ADC window mode + */ +int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode) +{ + ASSERT(descr); + _adc_sync_set_window_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Retrieve threshold state + */ +int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, adc_threshold_status_t *const state) +{ + ASSERT(descr && state); + _adc_sync_get_threshold_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Check if conversion is complete + */ +int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel) +{ + ASSERT(descr); + return _adc_sync_is_channel_conversion_done(&descr->device, channel); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t adc_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +//@} diff --git a/BLDC_E54/BLDC_E54/hal/src/hal_pwm.c b/BLDC_E54/BLDC_E54/hal/src/hal_pwm.c new file mode 100644 index 0000000..b586972 --- /dev/null +++ b/BLDC_E54/BLDC_E54/hal/src/hal_pwm.c @@ -0,0 +1,159 @@ +/** + * \file + * + * \brief PWM functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_pwm.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static void pwm_period_expired(struct _pwm_device *device); +static void pwm_detect_fault(struct _pwm_device *device); + +/** + * \brief Initialize pwm + */ +int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func) +{ + ASSERT(descr && hw); + _pwm_init(&descr->device, hw); + descr->device.callback.pwm_period_cb = pwm_period_expired; + descr->device.callback.pwm_error_cb = pwm_detect_fault; + return ERR_NONE; +} + +/** + * \brief Deinitialize pwm + */ +int32_t pwm_deinit(struct pwm_descriptor *const descr) +{ + ASSERT(descr); + _pwm_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Start pwm + */ +int32_t pwm_enable(struct pwm_descriptor *const descr) +{ + ASSERT(descr); + if (_pwm_is_enabled(&descr->device)) { + return ERR_DENIED; + } + _pwm_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Stop pwm + */ +int32_t pwm_disable(struct pwm_descriptor *const descr) +{ + ASSERT(descr); + if (!_pwm_is_enabled(&descr->device)) { + return ERR_DENIED; + } + _pwm_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Register PWM callback + */ +int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb) +{ + switch (type) { + case PWM_PERIOD_CB: + descr->pwm_cb.period = cb; + break; + + case PWM_ERROR_CB: + descr->pwm_cb.error = cb; + break; + + default: + return ERR_INVALID_ARG; + } + ASSERT(descr); + _pwm_set_irq_state(&descr->device, (enum _pwm_callback_type)type, NULL != cb); + return ERR_NONE; +} + +/** + * \brief Change PWM parameter + */ +int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, const pwm_period_t duty_cycle) +{ + ASSERT(descr); + _pwm_set_param(&descr->device, period, duty_cycle); + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t pwm_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal Process interrupts caused by period experied + */ +static void pwm_period_expired(struct _pwm_device *device) +{ + struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device); + + if (descr->pwm_cb.period) { + descr->pwm_cb.period(descr); + } +} + +/** + * \internal Process interrupts caused by pwm fault + */ +static void pwm_detect_fault(struct _pwm_device *device) +{ + struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device); + + if (descr->pwm_cb.error) { + descr->pwm_cb.error(descr); + } +} diff --git a/BLDC_E54/BLDC_E54/hpl/dmac/hpl_dmac.c b/BLDC_E54/BLDC_E54/hpl/dmac/hpl_dmac.c index fc3b059..34ef8b5 100644 --- a/BLDC_E54/BLDC_E54/hpl/dmac/hpl_dmac.c +++ b/BLDC_E54/BLDC_E54/hpl/dmac/hpl_dmac.c @@ -220,7 +220,7 @@ int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) /** * \internal DMAC interrupt handler */ -static void _dmac_handler(uint8_t channel) +static void _dmac_handler(uint8_t channel) // Added Channel { //uint8_t channel = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk); struct _dma_resource *tmp_resource = &_resources[channel]; @@ -231,12 +231,8 @@ static void _dmac_handler(uint8_t channel) } else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)|hri_dmac_get_CHINTEN_TCMPL_bit(DMAC,channel)) { hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel); tmp_resource->dma_cb.transfer_done(tmp_resource); - } else if (hri_dmac_get_INTPEND_SUSP_bit(DMAC)|hri_dmac_get_CHINTEN_SUSP_bit(DMAC,channel)) { - hri_dmac_clear_CHINTFLAG_SUSP_bit(DMAC, channel); - if(channel == 3) - { - volatile int i = 0; - } + } else if (hri_dmac_get_INTPEND_SUSP_bit(DMAC)|hri_dmac_get_CHINTEN_SUSP_bit(DMAC,channel)) { //added + hri_dmac_clear_CHINTFLAG_SUSP_bit(DMAC, channel); //added tmp_resource->dma_cb.suspend(tmp_resource); } diff --git a/BLDC_E54/BLDC_E54/hpl/tcc/hpl_tcc.c b/BLDC_E54/BLDC_E54/hpl/tcc/hpl_tcc.c new file mode 100644 index 0000000..eafcced --- /dev/null +++ b/BLDC_E54/BLDC_E54/hpl/tcc/hpl_tcc.c @@ -0,0 +1,394 @@ +/** + * \file + * + * \brief SAM TCC + * + * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/** + * \brief TCC configuration type + */ +struct tcc_cfg { + void * hw; /*!< instance of TCC */ + IRQn_Type irq; + hri_tcc_ctrla_reg_t ctrl_a; + hri_tcc_ctrlbset_reg_t ctrl_b; + hri_tcc_dbgctrl_reg_t dbg_ctrl; + hri_tcc_evctrl_reg_t event_ctrl; + hri_tcc_cc_reg_t cc0; + hri_tcc_cc_reg_t cc1; + hri_tcc_cc_reg_t cc2; + hri_tcc_cc_reg_t cc3; + hri_tcc_cc_reg_t cc4; + hri_tcc_cc_reg_t cc5; + hri_tcc_per_reg_t per; +}; +/** + * \brief pwm configuration type + */ +struct tcc_pwm_cfg { + void * hw; /*!< instance of TCC */ + IRQn_Type irq; + uint8_t sel_ch; + uint32_t period; + uint32_t duty_cycle; + uint32_t wave; +}; + +/** + * \internal Retrieve configuration + * + * \param[in] hw The pointer of TCC base address + * + * \return The configuration + */ +static struct tcc_cfg *_get_tcc_cfg(void *hw); + +/** + * \brief Array of TCC configurations + */ +static struct tcc_cfg _cfgs[2] = { + {(void *)TCC0, + TCC0_0_IRQn, + CONF_TCC0_CTRLA, + CONF_TCC0_CTRLB, + CONF_TCC0_DBGCTRL, + CONF_TCC0_EVCTRL, + CONF_TCC0_CC0, + CONF_TCC0_CC1, + CONF_TCC0_CC2, + CONF_TCC0_CC3, + CONF_TCC0_CC4, + CONF_TCC0_CC5, + CONF_TCC0_PER}, + + {(void *)TCC1, + TCC1_0_IRQn, + CONF_TCC1_CTRLA, + CONF_TCC1_CTRLB, + CONF_TCC1_DBGCTRL, + CONF_TCC1_EVCTRL, + CONF_TCC1_CC0, + CONF_TCC1_CC1, + CONF_TCC1_CC2, + CONF_TCC1_CC3, + 0, + 0, + CONF_TCC1_PER}, +}; + +/** + * \internal Retrieve configuration + * + * \param[in] hw The pointer of TCC base address + * + * \return The configuration + */ +static struct tcc_pwm_cfg *_get_tcc_pwm_cfg(void *hw); + +/** + * \brief Array of PWM configurations + */ +static struct tcc_pwm_cfg _cfgs_pwm[2] = { + {(void *)TCC0, + TCC0_0_IRQn, + CONF_TCC0_SEL_CH, + CONF_TCC0_PER_REG, + CONF_TCC0_CCX_REG, + (CONF_TCC0_WAVEGEN << TCC_WAVE_WAVEGEN_Pos)}, + {(void *)TCC1, + TCC1_0_IRQn, + CONF_TCC1_SEL_CH, + CONF_TCC1_PER_REG, + CONF_TCC1_CCX_REG, + (CONF_TCC1_WAVEGEN << TCC_WAVE_WAVEGEN_Pos)}, +}; +/* Renamed access REG name PERB -> PERBUF */ +#define hri_tcc_write_PERB_reg hri_tcc_write_PERBUF_reg +#define hri_tcc_read_PERB_reg hri_tcc_read_PERBUF_reg + +/** Renamed access REG name CCB -> CCBUF */ +#define hri_tcc_write_CCB_reg hri_tcc_write_CCBUF_reg +#define hri_tcc_read_CCB_reg hri_tcc_read_CCBUF_reg + +static struct _pwm_device *_tcc0_dev = NULL; + +static struct _pwm_device *_tcc1_dev = NULL; + +/** + * \brief Init irq param with the given tcc hardware instance + */ +static void _tcc_init_irq_param(const void *const hw, void *dev) +{ + if (hw == TCC0) { + _tcc0_dev = (struct _pwm_device *)dev; + } + if (hw == TCC1) { + _tcc1_dev = (struct _pwm_device *)dev; + } +} +/** + * \brief Initialize TCC for PWM mode + */ +int32_t _pwm_init(struct _pwm_device *const device, void *const hw) +{ + struct tcc_cfg *cfg = _get_tcc_cfg(hw); + if (cfg == NULL) { + return ERR_NOT_FOUND; + } + struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw); + if (cfg_pwm == NULL) { + return ERR_NOT_FOUND; + } + + device->hw = hw; + + if (!hri_tcc_is_syncing(hw, TCC_SYNCBUSY_SWRST)) { + if (hri_tcc_get_CTRLA_reg(hw, TCC_CTRLA_ENABLE)) { + hri_tcc_clear_CTRLA_ENABLE_bit(hw); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_ENABLE); + } + hri_tcc_write_CTRLA_reg(hw, TCC_CTRLA_SWRST); + } + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + + hri_tcc_write_CTRLA_reg(hw, cfg->ctrl_a); + hri_tcc_set_CTRLB_reg(hw, cfg->ctrl_b); + hri_tcc_write_DBGCTRL_reg(hw, cfg->dbg_ctrl); + hri_tcc_write_EVCTRL_reg(hw, cfg->event_ctrl); + + hri_tcc_write_WAVE_reg(hw, cfg_pwm->wave); + hri_tcc_write_PER_reg(hw, cfg_pwm->period); + cfg->per = cfg_pwm->period; + switch (cfg_pwm->sel_ch) { + case 0: + cfg->cc0 = cfg_pwm->duty_cycle; + hri_tcc_write_CC_reg(hw, 0, cfg->cc0); + break; + case 1: + cfg->cc1 = cfg_pwm->duty_cycle; + hri_tcc_write_CC_reg(hw, 1, cfg->cc1); + break; + case 2: + cfg->cc2 = cfg_pwm->duty_cycle; + hri_tcc_write_CC_reg(hw, 2, cfg->cc2); + break; + case 3: + cfg->cc3 = cfg_pwm->duty_cycle; + hri_tcc_write_CC_reg(hw, 3, cfg->cc3); + break; + case 4: + cfg->cc4 = cfg_pwm->duty_cycle; + hri_tcc_write_CC_reg(hw, 4, cfg->cc4); + break; + case 5: + cfg->cc5 = cfg_pwm->duty_cycle; + hri_tcc_write_CC_reg(hw, 5, cfg->cc5); + break; + default: + return ERR_NO_RESOURCE; + break; + } + hri_tcc_clear_CTRLB_LUPD_bit(hw); + + _tcc_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)cfg_pwm->irq); + NVIC_ClearPendingIRQ((IRQn_Type)cfg_pwm->irq); + NVIC_EnableIRQ((IRQn_Type)cfg_pwm->irq); + + return ERR_NONE; +} +/** + * \brief De-initialize TCC for PWM mode + */ +void _pwm_deinit(struct _pwm_device *const device) +{ + void *const hw = device->hw; + struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw); + if (cfg_pwm != NULL) { + NVIC_DisableIRQ((IRQn_Type)cfg_pwm->irq); + hri_tcc_clear_CTRLA_ENABLE_bit(hw); + hri_tcc_set_CTRLA_SWRST_bit(hw); + } +} +/** + * \brief Start PWM + */ +void _pwm_enable(struct _pwm_device *const device) +{ + hri_tcc_set_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Stop PWM + */ +void _pwm_disable(struct _pwm_device *const device) +{ + hri_tcc_clear_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Set PWM parameter + */ +void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle) +{ + void *const hw = device->hw; + struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw); + if (cfg_pwm != NULL) { + hri_tcc_write_PERB_reg(hw, period); + hri_tcc_write_CCB_reg(hw, cfg_pwm->sel_ch, duty_cycle); + ; + } +} +/** + * \brief Get pwm waveform period value + */ +pwm_period_t _pwm_get_period(const struct _pwm_device *const device) +{ + return (pwm_period_t)(hri_tcc_read_PERB_reg(device->hw)); +} +/** + * \brief Get pwm waveform duty cycle + */ +uint32_t _pwm_get_duty(const struct _pwm_device *const device) +{ + void *const hw = device->hw; + struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw); + if (cfg_pwm == NULL) { + return ERR_NOT_FOUND; + } + uint32_t per = hri_tcc_read_PERB_reg(hw); + uint32_t duty_cycle = hri_tcc_read_CCB_reg(hw, cfg_pwm->sel_ch); + + return ((duty_cycle * 1000) / per); +} +/** + * \brief Check if PWM is running + */ +bool _pwm_is_enabled(const struct _pwm_device *const device) +{ + return hri_tcc_get_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Enable/disable PWM interrupt + */ +void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable) +{ + ASSERT(device); + + if (PWM_DEVICE_PERIOD_CB == type) { + hri_tcc_write_INTEN_OVF_bit(device->hw, disable); + } else if (PWM_DEVICE_ERROR_CB == type) { + hri_tcc_write_INTEN_ERR_bit(device->hw, disable); + } +} + +/** + * \brief Retrieve timer helper functions + */ +struct _timer_hpl_interface *_tcc_get_timer(void) +{ + return NULL; +} + +/** + * \brief Retrieve pwm helper functions + */ +struct _pwm_hpl_interface *_tcc_get_pwm(void) +{ + return NULL; +} +/** + * \internal TC interrupt handler for PWM + * + * \param[in] instance TC instance number + */ +static void tcc_pwm_interrupt_handler(struct _pwm_device *device) +{ + void *const hw = device->hw; + + if (hri_tcc_get_interrupt_OVF_bit(hw)) { + hri_tcc_clear_interrupt_OVF_bit(hw); + if (NULL != device->callback.pwm_period_cb) { + device->callback.pwm_period_cb(device); + } + } + if (hri_tcc_get_INTEN_ERR_bit(hw)) { + hri_tcc_clear_interrupt_ERR_bit(hw); + if (NULL != device->callback.pwm_error_cb) { + device->callback.pwm_error_cb(device); + } + } +} + +/** + * \brief TCC interrupt handler + */ +void TCC0_0_Handler(void) +{ + tcc_pwm_interrupt_handler(_tcc0_dev); +} + +/** + * \brief TCC interrupt handler + */ +void TCC1_0_Handler(void) +{ + tcc_pwm_interrupt_handler(_tcc1_dev); +} + +static struct tcc_cfg *_get_tcc_cfg(void *hw) +{ + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_cfgs); i++) { + if (_cfgs[i].hw == hw) { + return &(_cfgs[i]); + } + } + return NULL; +} + +static struct tcc_pwm_cfg *_get_tcc_pwm_cfg(void *hw) +{ + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_cfgs_pwm); i++) { + if (_cfgs_pwm[i].hw == hw) { + return &(_cfgs_pwm[i]); + } + } + return NULL; +} diff --git a/BLDC_E54/BLDC_E54/hpl/tcc/hpl_tcc.h b/BLDC_E54/BLDC_E54/hpl/tcc/hpl_tcc.h new file mode 100644 index 0000000..4ccac85 --- /dev/null +++ b/BLDC_E54/BLDC_E54/hpl/tcc/hpl_tcc.h @@ -0,0 +1,77 @@ +/** + * \file + * + * \brief SAM Timer/Counter for Control Applications + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_TCC_V101_BASE_H_INCLUDED +#define _HPL_TCC_V101_BASE_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup tcc_group TCC Low Level Driver Helpers + * + * \section tcc_helpers_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Retrieve timer helper functions + * + * \return A pointer to set of timer helper functions + */ +struct _timer_hpl_interface *_tcc_get_timer(void); + +/** + * \brief Retrieve pwm helper functions + * + * \return A pointer to set of pwm helper functions + */ +struct _pwm_hpl_interface *_tcc_get_pwm(void); + +//@} +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_TCC_V101_BASE_H_INCLUDED */ diff --git a/BLDC_E54/BLDC_E54/interrupt_handlers.h b/BLDC_E54/BLDC_E54/interrupt_handlers.h index 6bdcd1e..385a1c1 100644 --- a/BLDC_E54/BLDC_E54/interrupt_handlers.h +++ b/BLDC_E54/BLDC_E54/interrupt_handlers.h @@ -30,7 +30,7 @@ void TC7_Handler(void) //One_ms_cycle_callback(); //gpio_toggle_pin_level(DEBUG_1); One_ms_cycle_callback(); - Motor1.timerflags.motor_telemetry_flag = true; + //Motor1.timerflags.motor_telemetry_flag = true; } } diff --git a/BLDC_E54/BLDC_E54/main.c b/BLDC_E54/BLDC_E54/main.c index 43884fd..9c51b9c 100644 --- a/BLDC_E54/BLDC_E54/main.c +++ b/BLDC_E54/BLDC_E54/main.c @@ -50,8 +50,8 @@ inline void CONTROLLER_StateMachine(void) break; case MOTOR_IDLE: applicationStatus.previousstate = applicationStatus.currentstate; - //applicationStatus.currentstate = MOTOR_PVI_CTRL_STATE; - applicationStatus.currentstate = MOTOR_V_CTRL_STATE; + applicationStatus.currentstate = MOTOR_PVI_CTRL_STATE; + //applicationStatus.currentstate = MOTOR_V_CTRL_STATE; break; case MOTOR_I_CTRL_STATE: @@ -64,8 +64,8 @@ inline void CONTROLLER_StateMachine(void) /* Blank */ case 6: /* PWM FREQ / 6.25 - 4kHz */ calculate_motor_speed(); - //BLDC_runSpeedCntl(&Motor1, Motor1.motor_status.calc_rpm, Motor1.motor_setpoints.desired_speed); - BLDC_runSpeedCntl(&Motor1, Motor1.motor_status.calc_rpm, 3000); + BLDC_runSpeedCntl(&Motor1, Motor1.motor_status.calc_rpm, Motor1.motor_setpoints.desired_speed); + //BLDC_runSpeedCntl(&Motor1, Motor1.motor_status.calc_rpm, 3000); default: /* PWM FREQ - 25kHz */ select_active_phase(&Motor1, Motor1.motor_status.currentHallPattern); /* Still measure current */ break; @@ -212,36 +212,19 @@ int main(void) /* Replace with your application code */ while (1) { - //tic(DEBUG_1); - //tic_port(DEBUG_3_PORT); - //toc(DEBUG_1); - //toc_port(DEBUG_3_PORT); - - - //tic(DEBUG_1_PORT); - //toc(DEBUG_1_PORT); - if(Motor1.timerflags.motor_telemetry_flag) { Motor1.timerflags.motor_telemetry_flag = false; update_setpoints(); update_telemetry(); } - //{ - //gpio_set_pin_level(DRV_RST, true); - //Motor1.timerflags.pwm_cycle_tic = false; - //tic(DEBUG_1); - //exec_commutation(); - //toc(DEBUG_1); - //} + if(Motor1.timerflags.current_loop_tic) { Motor1.timerflags.current_loop_tic = false; //tic_port(DEBUG_1_PORT); CONTROLLER_StateMachine(); //toc_port(DEBUG_1_PORT); } - - - + //do { //delay_ms(10); //} while (gpio_get_pin_level(SW0)); diff --git a/BLDC_E54/BLDC_E54/motor_params.h b/BLDC_E54/BLDC_E54/motor_params.h index 810e79c..7fb4b52 100644 --- a/BLDC_E54/BLDC_E54/motor_params.h +++ b/BLDC_E54/BLDC_E54/motor_params.h @@ -44,14 +44,16 @@ #define MOTOR_LD_H (0.001290f) #define MOTOR_LQ_H (0.001290f) #define MOTOR_FLUX_WB (0.0063879968f) -#define MOTOR_MAX_SPD_RPM (4200.0f) +//#define MOTOR_MAX_SPD_RPM (3000.0f) +#define MOTOR_MAX_SPD_RPM (500.0f) #define MOTOR_MAX_SPD_ELEC ((MOTOR_MAX_SPD_RPM/60)*MOTOR_POLEPAIRS) #define MOTOR_MEASURINGRANGE_RPM (1.2f * MOTOR_MAX_SPD_RPM)f // give 20% headroom #define MOTOR_MAX_CURRENT_IDC_A (1.2f) +//#define MOTOR_MAX_CURRENT_IDC_A (0.5f) #define PWM_TOP 1000 -#define MAX_PWM 700 -#define MAX_VEL 3800 +#define MAX_PWM 600 +//#define MAX_VEL 3800 #define CW 0 //CBA #define DIRECTION_CW_OFFSET 0 //CBA