diff --git a/2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart b/2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart index 7949299..6222e30 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart +++ b/2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart @@ -41,7 +41,7 @@ drivers: adc_arch_refcomp: false adc_arch_resrdyeo: true adc_arch_runstdby: false - adc_arch_samplen: 3 + adc_arch_samplen: 2 adc_arch_samplenum: 1 sample adc_arch_seqen: 0 adc_arch_startei: false @@ -237,7 +237,7 @@ drivers: api: HAL:HPL:DMAC configuration: dmac_beatsize_0: 8-bit bus transfer - dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_1: 16-bit bus transfer dmac_beatsize_10: 8-bit bus transfer dmac_beatsize_11: 8-bit bus transfer dmac_beatsize_12: 8-bit bus transfer @@ -259,7 +259,7 @@ drivers: dmac_beatsize_27: 8-bit bus transfer dmac_beatsize_28: 8-bit bus transfer dmac_beatsize_29: 8-bit bus transfer - dmac_beatsize_3: 16-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer dmac_beatsize_30: 8-bit bus transfer dmac_beatsize_31: 8-bit bus transfer dmac_beatsize_4: 8-bit bus transfer @@ -271,7 +271,7 @@ drivers: dmac_blockact_0: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_1: Channel will be disabled if it is the last block transfer in - the transaction + the transaction and block interrupt dmac_blockact_10: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_11: Channel will be disabled if it is the last block transfer @@ -314,7 +314,7 @@ drivers: dmac_blockact_29: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_3: Channel will be disabled if it is the last block transfer in - the transaction and block interrupt + the transaction dmac_blockact_30: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_31: Channel will be disabled if it is the last block transfer @@ -365,7 +365,7 @@ drivers: dmac_channel_9_settings: false dmac_dbgrun: false dmac_dstinc_0: true - dmac_dstinc_1: false + dmac_dstinc_1: true dmac_dstinc_10: false dmac_dstinc_11: false dmac_dstinc_12: false @@ -387,7 +387,7 @@ drivers: dmac_dstinc_27: false dmac_dstinc_28: false dmac_dstinc_29: false - dmac_dstinc_3: true + dmac_dstinc_3: false dmac_dstinc_30: false dmac_dstinc_31: false dmac_dstinc_4: false @@ -537,7 +537,7 @@ drivers: dmac_lvl_17: Channel priority 0 dmac_lvl_18: Channel priority 0 dmac_lvl_19: Channel priority 0 - dmac_lvl_2: Channel priority 1 + dmac_lvl_2: Channel priority 0 dmac_lvl_20: Channel priority 0 dmac_lvl_21: Channel priority 0 dmac_lvl_22: Channel priority 0 @@ -548,7 +548,7 @@ drivers: dmac_lvl_27: Channel priority 0 dmac_lvl_28: Channel priority 0 dmac_lvl_29: Channel priority 0 - dmac_lvl_3: Channel priority 1 + dmac_lvl_3: Channel priority 0 dmac_lvl_30: Channel priority 0 dmac_lvl_31: Channel priority 0 dmac_lvl_4: Channel priority 0 @@ -562,15 +562,15 @@ drivers: dmac_lvlen2: true dmac_lvlen3: true dmac_lvlpri0: 0 - dmac_lvlpri1: 1 + dmac_lvlpri1: 0 dmac_lvlpri2: 0 dmac_lvlpri3: 0 dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 - dmac_runstdby_0: false - dmac_runstdby_1: false + dmac_runstdby_0: true + dmac_runstdby_1: true dmac_runstdby_10: false dmac_runstdby_11: false dmac_runstdby_12: false @@ -581,7 +581,7 @@ drivers: dmac_runstdby_17: false dmac_runstdby_18: false dmac_runstdby_19: false - dmac_runstdby_2: false + dmac_runstdby_2: true dmac_runstdby_20: false dmac_runstdby_21: false dmac_runstdby_22: false @@ -592,7 +592,7 @@ drivers: dmac_runstdby_27: false dmac_runstdby_28: false dmac_runstdby_29: false - dmac_runstdby_3: false + dmac_runstdby_3: true dmac_runstdby_30: false dmac_runstdby_31: false dmac_runstdby_4: false @@ -602,7 +602,7 @@ drivers: dmac_runstdby_8: false dmac_runstdby_9: false dmac_srcinc_0: false - dmac_srcinc_1: true + dmac_srcinc_1: false dmac_srcinc_10: false dmac_srcinc_11: false dmac_srcinc_12: false @@ -624,7 +624,7 @@ drivers: dmac_srcinc_27: false dmac_srcinc_28: false dmac_srcinc_29: false - dmac_srcinc_3: false + dmac_srcinc_3: true dmac_srcinc_30: false dmac_srcinc_31: false dmac_srcinc_4: false @@ -656,7 +656,7 @@ drivers: dmac_stepsel_27: Step size settings apply to the destination address dmac_stepsel_28: Step size settings apply to the destination address dmac_stepsel_29: Step size settings apply to the destination address - dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the source address dmac_stepsel_30: Step size settings apply to the destination address dmac_stepsel_31: Step size settings apply to the destination address dmac_stepsel_4: Step size settings apply to the destination address @@ -698,7 +698,7 @@ drivers: dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_trifsrc_0: SERCOM1 RX Trigger - dmac_trifsrc_1: SERCOM1 TX Trigger + dmac_trifsrc_1: ADC1 Result Ready Trigger dmac_trifsrc_10: Only software/event triggers dmac_trifsrc_11: Only software/event triggers dmac_trifsrc_12: Only software/event triggers @@ -720,7 +720,7 @@ drivers: dmac_trifsrc_27: Only software/event triggers dmac_trifsrc_28: Only software/event triggers dmac_trifsrc_29: Only software/event triggers - dmac_trifsrc_3: ADC1 Result Ready Trigger + dmac_trifsrc_3: SERCOM1 TX Trigger dmac_trifsrc_30: Only software/event triggers dmac_trifsrc_31: Only software/event triggers dmac_trifsrc_4: Only software/event triggers @@ -1758,10 +1758,10 @@ drivers: spi_master_arch_dord: MSB first spi_master_arch_ibon: In data stream spi_master_arch_runstdby: false - spi_master_baud_rate: 8000000 + spi_master_baud_rate: 2000000 spi_master_character_size: 8 bits spi_master_dma_rx_channel: 0 - spi_master_dma_tx_channel: 1 + spi_master_dma_tx_channel: 3 spi_master_dummybyte: 511 spi_master_rx_channel: true spi_master_rx_enable: true diff --git a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_adc_config.h b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_adc_config.h index 55aa07c..3b5e1c9 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_adc_config.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_adc_config.h @@ -209,7 +209,7 @@ // These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN) // adc_arch_samplen #ifndef CONF_ADC_1_SAMPLEN -#define CONF_ADC_1_SAMPLEN 3 +#define CONF_ADC_1_SAMPLEN 2 #endif // Window Monitor Mode diff --git a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_dmac_config.h b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_dmac_config.h index c69200d..78d6df5 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_dmac_config.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_dmac_config.h @@ -51,7 +51,7 @@ // Level 1 Channel Priority Number <0x00-0xFF> // dmac_lvlpri1 #ifndef CONF_DMAC_LVLPRI1 -#define CONF_DMAC_LVLPRI1 1 +#define CONF_DMAC_LVLPRI1 0 #endif // Priority Level 2 // Indicates whether Priority Level 2 is enabled or not @@ -112,7 +112,7 @@ // Indicates whether channel 0 is running in standby mode or not // dmac_runstdby_0 #ifndef CONF_DMAC_RUNSTDBY_0 -#define CONF_DMAC_RUNSTDBY_0 0 +#define CONF_DMAC_RUNSTDBY_0 1 #endif // Trigger action @@ -336,7 +336,7 @@ // Indicates whether channel 1 is running in standby mode or not // dmac_runstdby_1 #ifndef CONF_DMAC_RUNSTDBY_1 -#define CONF_DMAC_RUNSTDBY_1 0 +#define CONF_DMAC_RUNSTDBY_1 1 #endif // Trigger action @@ -438,7 +438,7 @@ // Defines the peripheral trigger which is source of the transfer // dmac_trifsrc_1 #ifndef CONF_DMAC_TRIGSRC_1 -#define CONF_DMAC_TRIGSRC_1 7 +#define CONF_DMAC_TRIGSRC_1 70 #endif // Channel Arbitration Level @@ -508,14 +508,14 @@ // Indicates whether the source address incrementation is enabled or not // dmac_srcinc_1 #ifndef CONF_DMAC_SRCINC_1 -#define CONF_DMAC_SRCINC_1 1 +#define CONF_DMAC_SRCINC_1 0 #endif // Destination Address Increment // Indicates whether the destination address incrementation is enabled or not // dmac_dstinc_1 #ifndef CONF_DMAC_DSTINC_1 -#define CONF_DMAC_DSTINC_1 0 +#define CONF_DMAC_DSTINC_1 1 #endif // Beat Size @@ -525,7 +525,7 @@ // Defines the size of one beat // dmac_beatsize_1 #ifndef CONF_DMAC_BEATSIZE_1 -#define CONF_DMAC_BEATSIZE_1 0 +#define CONF_DMAC_BEATSIZE_1 1 #endif // Block Action @@ -536,7 +536,7 @@ // Defines the the DMAC should take after a block transfer has completed // dmac_blockact_1 #ifndef CONF_DMAC_BLOCKACT_1 -#define CONF_DMAC_BLOCKACT_1 0 +#define CONF_DMAC_BLOCKACT_1 1 #endif // Event Output Selection @@ -560,7 +560,7 @@ // Indicates whether channel 2 is running in standby mode or not // dmac_runstdby_2 #ifndef CONF_DMAC_RUNSTDBY_2 -#define CONF_DMAC_RUNSTDBY_2 0 +#define CONF_DMAC_RUNSTDBY_2 1 #endif // Trigger action @@ -673,7 +673,7 @@ // Defines the arbitration level for this channel // dmac_lvl_2 #ifndef CONF_DMAC_LVL_2 -#define CONF_DMAC_LVL_2 1 +#define CONF_DMAC_LVL_2 0 #endif // Channel Event Output @@ -784,7 +784,7 @@ // Indicates whether channel 3 is running in standby mode or not // dmac_runstdby_3 #ifndef CONF_DMAC_RUNSTDBY_3 -#define CONF_DMAC_RUNSTDBY_3 0 +#define CONF_DMAC_RUNSTDBY_3 1 #endif // Trigger action @@ -886,7 +886,7 @@ // Defines the peripheral trigger which is source of the transfer // dmac_trifsrc_3 #ifndef CONF_DMAC_TRIGSRC_3 -#define CONF_DMAC_TRIGSRC_3 70 +#define CONF_DMAC_TRIGSRC_3 7 #endif // Channel Arbitration Level @@ -897,7 +897,7 @@ // Defines the arbitration level for this channel // dmac_lvl_3 #ifndef CONF_DMAC_LVL_3 -#define CONF_DMAC_LVL_3 1 +#define CONF_DMAC_LVL_3 0 #endif // Channel Event Output @@ -949,21 +949,21 @@ // Defines whether source or destination addresses are using the step size settings // dmac_stepsel_3 #ifndef CONF_DMAC_STEPSEL_3 -#define CONF_DMAC_STEPSEL_3 0 +#define CONF_DMAC_STEPSEL_3 1 #endif // Source Address Increment // Indicates whether the source address incrementation is enabled or not // dmac_srcinc_3 #ifndef CONF_DMAC_SRCINC_3 -#define CONF_DMAC_SRCINC_3 0 +#define CONF_DMAC_SRCINC_3 1 #endif // Destination Address Increment // Indicates whether the destination address incrementation is enabled or not // dmac_dstinc_3 #ifndef CONF_DMAC_DSTINC_3 -#define CONF_DMAC_DSTINC_3 1 +#define CONF_DMAC_DSTINC_3 0 #endif // Beat Size @@ -973,7 +973,7 @@ // Defines the size of one beat // dmac_beatsize_3 #ifndef CONF_DMAC_BEATSIZE_3 -#define CONF_DMAC_BEATSIZE_3 1 +#define CONF_DMAC_BEATSIZE_3 0 #endif // Block Action @@ -984,7 +984,7 @@ // Defines the the DMAC should take after a block transfer has completed // dmac_blockact_3 #ifndef CONF_DMAC_BLOCKACT_3 -#define CONF_DMAC_BLOCKACT_3 1 +#define CONF_DMAC_BLOCKACT_3 0 #endif // Event Output Selection diff --git a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h index 42009f6..e6ecf04 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h @@ -15,7 +15,7 @@ // This defines DMA channel to be used // spi_master_dma_tx_channel #ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL -#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 1 +#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 3 #endif // SPI RX Channel Enable @@ -59,7 +59,7 @@ // The SPI data transfer rate // spi_master_baud_rate #ifndef CONF_SERCOM_1_SPI_BAUD -#define CONF_SERCOM_1_SPI_BAUD 8000000 +#define CONF_SERCOM_1_SPI_BAUD 2000000 #endif // diff --git a/2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj b/2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj index 14e459e..8d6c7c3 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj +++ b/2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj @@ -207,10 +207,10 @@ - + - + @@ -219,7 +219,7 @@ - + @@ -417,7 +417,7 @@ True Maximum (-g3) True - -std=gnu11 -mfloat-abi=hard -mfpu=fpv4-sp-d16 + -std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16 True diff --git a/2_Motor_Master/Motor_Master/Motor_Master/configuration.h b/2_Motor_Master/Motor_Master/Motor_Master/configuration.h index b41ddeb..2887c60 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/configuration.h +++ b/2_Motor_Master/Motor_Master/Motor_Master/configuration.h @@ -21,7 +21,7 @@ // M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6] // ---------------------------------------------------------------------- #define DMAC_CHANNEL_ADC_SEQ 2U -#define DMAC_CHANNEL_ADC_SRAM 3U +#define DMAC_CHANNEL_ADC_SRAM 1U /* Single Ended */ //const uint32_t adc_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808}; @@ -152,7 +152,7 @@ extern DmacDescriptor _write_back_section[DMAC_CH_NUM]; #define DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE 0u -#define DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT 1U +#define DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT 3U void boardToBoardTransferInit(void) { diff --git a/2_Motor_Master/Motor_Master/Motor_Master/main.c b/2_Motor_Master/Motor_Master/Motor_Master/main.c index 3e886c9..c502d57 100644 --- a/2_Motor_Master/Motor_Master/Motor_Master/main.c +++ b/2_Motor_Master/Motor_Master/Motor_Master/main.c @@ -63,14 +63,6 @@ void One_ms_timer_init(void) timer_start(&TIMER_0); } -//void speed_timer_init(void) -//{ - //hri_tc_write_WAVE_reg(TC_SPEED_M1.device.hw, 0x00); - //hri_tc_set_CTRLA_CAPTEN0_bit(TC_SPEED_M1.device.hw); - //hri_tc_set_CTRLA_CAPTEN1_bit(TC_SPEED_M1.device.hw); - //timer_start(&TC_SPEED_M1); -//} - void enable_NVIC_IRQ(void) { @@ -192,9 +184,9 @@ int main(void) Motor1.timerflags.motor_telemetry_flag = false; update_telemetry(); update_setpoints(); - //PORT->Group[1].OUTCLR.reg = (1<Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - //DMAC->Channel[1].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + PORT->Group[1].OUTCLR.reg = (1<Channel[DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC->Channel[DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; //_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, false); //_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, false); diff --git a/2_Motor_Slave/Motor_Slave/Motor_Slave/.atmelstart/atmel_start_config.atstart b/2_Motor_Slave/Motor_Slave/Motor_Slave/.atmelstart/atmel_start_config.atstart index 9cd0c5c..4d78ae5 100644 --- a/2_Motor_Slave/Motor_Slave/Motor_Slave/.atmelstart/atmel_start_config.atstart +++ b/2_Motor_Slave/Motor_Slave/Motor_Slave/.atmelstart/atmel_start_config.atstart @@ -113,7 +113,7 @@ drivers: adc_arch_refcomp: false adc_arch_resrdyeo: true adc_arch_runstdby: false - adc_arch_samplen: 3 + adc_arch_samplen: 2 adc_arch_samplenum: 1 sample adc_arch_seqen: 0 adc_arch_startei: false @@ -309,7 +309,7 @@ drivers: api: HAL:HPL:DMAC configuration: dmac_beatsize_0: 8-bit bus transfer - dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_1: 16-bit bus transfer dmac_beatsize_10: 8-bit bus transfer dmac_beatsize_11: 8-bit bus transfer dmac_beatsize_12: 8-bit bus transfer @@ -331,7 +331,7 @@ drivers: dmac_beatsize_27: 8-bit bus transfer dmac_beatsize_28: 8-bit bus transfer dmac_beatsize_29: 8-bit bus transfer - dmac_beatsize_3: 16-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer dmac_beatsize_30: 8-bit bus transfer dmac_beatsize_31: 8-bit bus transfer dmac_beatsize_4: 8-bit bus transfer @@ -343,7 +343,7 @@ drivers: dmac_blockact_0: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_1: Channel will be disabled if it is the last block transfer in - the transaction + the transaction and block interrupt dmac_blockact_10: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_11: Channel will be disabled if it is the last block transfer @@ -386,7 +386,7 @@ drivers: dmac_blockact_29: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_3: Channel will be disabled if it is the last block transfer in - the transaction and block interrupt + the transaction dmac_blockact_30: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_31: Channel will be disabled if it is the last block transfer @@ -437,7 +437,7 @@ drivers: dmac_channel_9_settings: false dmac_dbgrun: false dmac_dstinc_0: true - dmac_dstinc_1: false + dmac_dstinc_1: true dmac_dstinc_10: false dmac_dstinc_11: false dmac_dstinc_12: false @@ -459,7 +459,7 @@ drivers: dmac_dstinc_27: false dmac_dstinc_28: false dmac_dstinc_29: false - dmac_dstinc_3: true + dmac_dstinc_3: false dmac_dstinc_30: false dmac_dstinc_31: false dmac_dstinc_4: false @@ -630,9 +630,9 @@ drivers: dmac_lvl_8: Channel priority 0 dmac_lvl_9: Channel priority 0 dmac_lvlen0: true - dmac_lvlen1: true - dmac_lvlen2: true - dmac_lvlen3: true + dmac_lvlen1: false + dmac_lvlen2: false + dmac_lvlen3: false dmac_lvlpri0: 0 dmac_lvlpri1: 0 dmac_lvlpri2: 0 @@ -641,8 +641,8 @@ drivers: dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 - dmac_runstdby_0: false - dmac_runstdby_1: false + dmac_runstdby_0: true + dmac_runstdby_1: true dmac_runstdby_10: false dmac_runstdby_11: false dmac_runstdby_12: false @@ -653,7 +653,7 @@ drivers: dmac_runstdby_17: false dmac_runstdby_18: false dmac_runstdby_19: false - dmac_runstdby_2: false + dmac_runstdby_2: true dmac_runstdby_20: false dmac_runstdby_21: false dmac_runstdby_22: false @@ -664,7 +664,7 @@ drivers: dmac_runstdby_27: false dmac_runstdby_28: false dmac_runstdby_29: false - dmac_runstdby_3: false + dmac_runstdby_3: true dmac_runstdby_30: false dmac_runstdby_31: false dmac_runstdby_4: false @@ -674,7 +674,7 @@ drivers: dmac_runstdby_8: false dmac_runstdby_9: false dmac_srcinc_0: false - dmac_srcinc_1: true + dmac_srcinc_1: false dmac_srcinc_10: false dmac_srcinc_11: false dmac_srcinc_12: false @@ -696,7 +696,7 @@ drivers: dmac_srcinc_27: false dmac_srcinc_28: false dmac_srcinc_29: false - dmac_srcinc_3: false + dmac_srcinc_3: true dmac_srcinc_30: false dmac_srcinc_31: false dmac_srcinc_4: false @@ -706,7 +706,7 @@ drivers: dmac_srcinc_8: false dmac_srcinc_9: false dmac_stepsel_0: Step size settings apply to the destination address - dmac_stepsel_1: Step size settings apply to the source address + dmac_stepsel_1: Step size settings apply to the destination address dmac_stepsel_10: Step size settings apply to the destination address dmac_stepsel_11: Step size settings apply to the destination address dmac_stepsel_12: Step size settings apply to the destination address @@ -728,7 +728,7 @@ drivers: dmac_stepsel_27: Step size settings apply to the destination address dmac_stepsel_28: Step size settings apply to the destination address dmac_stepsel_29: Step size settings apply to the destination address - dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the source address dmac_stepsel_30: Step size settings apply to the destination address dmac_stepsel_31: Step size settings apply to the destination address dmac_stepsel_4: Step size settings apply to the destination address @@ -770,7 +770,7 @@ drivers: dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_trifsrc_0: SERCOM1 RX Trigger - dmac_trifsrc_1: SERCOM1 TX Trigger + dmac_trifsrc_1: ADC1 Result Ready Trigger dmac_trifsrc_10: Only software/event triggers dmac_trifsrc_11: Only software/event triggers dmac_trifsrc_12: Only software/event triggers @@ -792,7 +792,7 @@ drivers: dmac_trifsrc_27: Only software/event triggers dmac_trifsrc_28: Only software/event triggers dmac_trifsrc_29: Only software/event triggers - dmac_trifsrc_3: ADC1 Result Ready Trigger + dmac_trifsrc_3: SERCOM1 TX Trigger dmac_trifsrc_30: Only software/event triggers dmac_trifsrc_31: Only software/event triggers dmac_trifsrc_4: Only software/event triggers diff --git a/2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_adc_config.h b/2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_adc_config.h index 82de8c4..9675725 100644 --- a/2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_adc_config.h +++ b/2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_adc_config.h @@ -502,7 +502,7 @@ // These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN) // adc_arch_samplen #ifndef CONF_ADC_1_SAMPLEN -#define CONF_ADC_1_SAMPLEN 3 +#define CONF_ADC_1_SAMPLEN 2 #endif // Window Monitor Mode diff --git a/2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_dmac_config.h b/2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_dmac_config.h index a181af5..2cf78b5 100644 --- a/2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_dmac_config.h +++ b/2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_dmac_config.h @@ -36,7 +36,7 @@ // Indicates whether Priority Level 1 is enabled or not // dmac_lvlen1 #ifndef CONF_DMAC_LVLEN1 -#define CONF_DMAC_LVLEN1 1 +#define CONF_DMAC_LVLEN1 0 #endif // Level 1 Round-Robin Arbitration @@ -57,7 +57,7 @@ // Indicates whether Priority Level 2 is enabled or not // dmac_lvlen2 #ifndef CONF_DMAC_LVLEN2 -#define CONF_DMAC_LVLEN2 1 +#define CONF_DMAC_LVLEN2 0 #endif // Level 2 Round-Robin Arbitration @@ -78,7 +78,7 @@ // Indicates whether Priority Level 3 is enabled or not // dmac_lvlen3 #ifndef CONF_DMAC_LVLEN3 -#define CONF_DMAC_LVLEN3 1 +#define CONF_DMAC_LVLEN3 0 #endif // Level 3 Round-Robin Arbitration @@ -112,7 +112,7 @@ // Indicates whether channel 0 is running in standby mode or not // dmac_runstdby_0 #ifndef CONF_DMAC_RUNSTDBY_0 -#define CONF_DMAC_RUNSTDBY_0 0 +#define CONF_DMAC_RUNSTDBY_0 1 #endif // Trigger action @@ -336,7 +336,7 @@ // Indicates whether channel 1 is running in standby mode or not // dmac_runstdby_1 #ifndef CONF_DMAC_RUNSTDBY_1 -#define CONF_DMAC_RUNSTDBY_1 0 +#define CONF_DMAC_RUNSTDBY_1 1 #endif // Trigger action @@ -438,7 +438,7 @@ // Defines the peripheral trigger which is source of the transfer // dmac_trifsrc_1 #ifndef CONF_DMAC_TRIGSRC_1 -#define CONF_DMAC_TRIGSRC_1 7 +#define CONF_DMAC_TRIGSRC_1 70 #endif // Channel Arbitration Level @@ -501,21 +501,21 @@ // Defines whether source or destination addresses are using the step size settings // dmac_stepsel_1 #ifndef CONF_DMAC_STEPSEL_1 -#define CONF_DMAC_STEPSEL_1 1 +#define CONF_DMAC_STEPSEL_1 0 #endif // Source Address Increment // Indicates whether the source address incrementation is enabled or not // dmac_srcinc_1 #ifndef CONF_DMAC_SRCINC_1 -#define CONF_DMAC_SRCINC_1 1 +#define CONF_DMAC_SRCINC_1 0 #endif // Destination Address Increment // Indicates whether the destination address incrementation is enabled or not // dmac_dstinc_1 #ifndef CONF_DMAC_DSTINC_1 -#define CONF_DMAC_DSTINC_1 0 +#define CONF_DMAC_DSTINC_1 1 #endif // Beat Size @@ -525,7 +525,7 @@ // Defines the size of one beat // dmac_beatsize_1 #ifndef CONF_DMAC_BEATSIZE_1 -#define CONF_DMAC_BEATSIZE_1 0 +#define CONF_DMAC_BEATSIZE_1 1 #endif // Block Action @@ -536,7 +536,7 @@ // Defines the the DMAC should take after a block transfer has completed // dmac_blockact_1 #ifndef CONF_DMAC_BLOCKACT_1 -#define CONF_DMAC_BLOCKACT_1 0 +#define CONF_DMAC_BLOCKACT_1 1 #endif // Event Output Selection @@ -560,7 +560,7 @@ // Indicates whether channel 2 is running in standby mode or not // dmac_runstdby_2 #ifndef CONF_DMAC_RUNSTDBY_2 -#define CONF_DMAC_RUNSTDBY_2 0 +#define CONF_DMAC_RUNSTDBY_2 1 #endif // Trigger action @@ -784,7 +784,7 @@ // Indicates whether channel 3 is running in standby mode or not // dmac_runstdby_3 #ifndef CONF_DMAC_RUNSTDBY_3 -#define CONF_DMAC_RUNSTDBY_3 0 +#define CONF_DMAC_RUNSTDBY_3 1 #endif // Trigger action @@ -886,7 +886,7 @@ // Defines the peripheral trigger which is source of the transfer // dmac_trifsrc_3 #ifndef CONF_DMAC_TRIGSRC_3 -#define CONF_DMAC_TRIGSRC_3 70 +#define CONF_DMAC_TRIGSRC_3 7 #endif // Channel Arbitration Level @@ -949,21 +949,21 @@ // Defines whether source or destination addresses are using the step size settings // dmac_stepsel_3 #ifndef CONF_DMAC_STEPSEL_3 -#define CONF_DMAC_STEPSEL_3 0 +#define CONF_DMAC_STEPSEL_3 1 #endif // Source Address Increment // Indicates whether the source address incrementation is enabled or not // dmac_srcinc_3 #ifndef CONF_DMAC_SRCINC_3 -#define CONF_DMAC_SRCINC_3 0 +#define CONF_DMAC_SRCINC_3 1 #endif // Destination Address Increment // Indicates whether the destination address incrementation is enabled or not // dmac_dstinc_3 #ifndef CONF_DMAC_DSTINC_3 -#define CONF_DMAC_DSTINC_3 1 +#define CONF_DMAC_DSTINC_3 0 #endif // Beat Size @@ -973,7 +973,7 @@ // Defines the size of one beat // dmac_beatsize_3 #ifndef CONF_DMAC_BEATSIZE_3 -#define CONF_DMAC_BEATSIZE_3 1 +#define CONF_DMAC_BEATSIZE_3 0 #endif // Block Action @@ -984,7 +984,7 @@ // Defines the the DMAC should take after a block transfer has completed // dmac_blockact_3 #ifndef CONF_DMAC_BLOCKACT_3 -#define CONF_DMAC_BLOCKACT_3 1 +#define CONF_DMAC_BLOCKACT_3 0 #endif // Event Output Selection diff --git a/2_Motor_Slave/Motor_Slave/Motor_Slave/Motor_Slave.cproj b/2_Motor_Slave/Motor_Slave/Motor_Slave/Motor_Slave.cproj index f7b8646..ccfc355 100644 --- a/2_Motor_Slave/Motor_Slave/Motor_Slave/Motor_Slave.cproj +++ b/2_Motor_Slave/Motor_Slave/Motor_Slave/Motor_Slave.cproj @@ -209,10 +209,10 @@ - + - + @@ -389,7 +389,6 @@ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ - %24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include ../Config ../ ../examples @@ -414,12 +413,13 @@ ../hpl/tcc ../hri ../bosch_sensor + %24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include True Maximum (-g3) True - -std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16 + -std=gnu11 -mfloat-abi=hard -mfpu=fpv4-sp-d16 True @@ -440,7 +440,6 @@ %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ - %24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include ../Config ../ ../examples @@ -465,13 +464,13 @@ ../hpl/tcc ../hri ../bosch_sensor + %24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include Default (-g) %24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\ - %24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include ../Config ../ ../examples @@ -496,6 +495,7 @@ ../hpl/tcc ../hri ../bosch_sensor + %24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include Default (-Wa,-g) diff --git a/2_Motor_Slave/Motor_Slave/Motor_Slave/bldc.c b/2_Motor_Slave/Motor_Slave/Motor_Slave/bldc.c index fc99b5a..8520781 100644 --- a/2_Motor_Slave/Motor_Slave/Motor_Slave/bldc.c +++ b/2_Motor_Slave/Motor_Slave/Motor_Slave/bldc.c @@ -35,10 +35,10 @@ void motor_StateMachine(BLDCMotor_t* const motor) case MOTOR_IDLE: //hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw, DISABLE_PATTERN); motor->motor_state.previousstate = motor->motor_state.currentstate; - //motor->motor_state.currentstate = MOTOR_PVI_CTRL_STATE; + motor->motor_state.currentstate = MOTOR_PVI_CTRL_STATE; break; case MOTOR_OPEN_LOOP_STATE: - BLDC_runOpenLoop(motor, *M1_Desired_dc); + BLDC_runOpenLoop(motor, 0); calculate_motor_speed(motor); motor->motor_state.previousstate = motor->motor_state.currentstate; break; @@ -104,6 +104,7 @@ void BldcInitStruct(BLDCMotor_t* const motor, BLDCMotor_param_t * const motor_pa motor->motor_status.actualDirection = 0; motor->motor_status.duty_cycle = 0; motor->motor_status.calc_rpm = 0; + //motor->motor_status.abs_position = 0; motor->motor_status.Num_Steps = 0; motor->motor_status.cur_comm_step = 0; motor->motor_status.currentHallPattern = 1; @@ -238,7 +239,8 @@ void exec_commutation(BLDCMotor_t* const motor) // ---------------------------------------------------------------------- //hri_tcc_write_CCBUF_CCBUF_bf(motor->motor_param->pwm_desc->device.hw, 0, motor->motor_status.duty_cycle); tmp->CCBUF[0].reg = (uint32_t)motor->motor_status.duty_cycle; - + + volatile uint8_t cur_comm_step = MOTOR_COMMUTATION_STEPS[currentHall]; motor->motor_status.cur_comm_step = cur_comm_step; volatile int8_t step_change = (cur_comm_step - motor->motor_status.prev_comm_step); @@ -379,7 +381,9 @@ void BLDC_runCurrentCntl(BLDCMotor_t *motor, const float32_t curfbk, const float } volatile float32_t duty_pu = f_abs((motor->controllers.Pi_Idc.Out_pu * motor->VoneByDcBus_pu)); - motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM); + //motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM); + //motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM); + motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * motor->motor_param->motor_MaxPWM, 0.0f, (float32_t)MAX_PWM); // Remove Low duty cycle values //if(duty_cycle < 80.0) motor->duty_cycle = (uint16_t)0; //else motor->duty_cycle = (uint16_t)duty_cycle; @@ -457,7 +461,7 @@ volatile uint8_t readHallSensorM1(void) motor_read = (motor_read & M1_HALL_B_MASK) | (uint8_t)((PORT->Group[M1_HALL_B_GROUP].IN.reg & M1_HALL_B_PORT)>>(M1_HALL_B_LSR)); motor_read = (motor_read & M1_HALL_C_MASK) | (uint8_t)((PORT->Group[M1_HALL_C_GROUP].IN.reg & M1_HALL_C_PORT)>>(M1_HALL_C_LSR)); return motor_read; - // + //volatile uint8_t a = gpio_get_pin_level(M1_HALL_A_PIN); //volatile uint8_t b = gpio_get_pin_level(M1_HALL_B_PIN); //volatile uint8_t c = gpio_get_pin_level(M1_HALL_C_PIN); @@ -469,13 +473,13 @@ volatile uint8_t readHallSensorM1(void) volatile uint8_t readHallSensorM2(void) { + volatile uint8_t motor_read = 0; - motor_read = (motor_read & M2_HALL_A_MASK) | (uint8_t)((PORT->Group[M2_HALL_A_GROUP].IN.reg & M2_HALL_A_PORT)>>(M2_HALL_A_LSR)); - motor_read = (motor_read & M2_HALL_B_MASK) | (uint8_t)((PORT->Group[M2_HALL_B_GROUP].IN.reg & M2_HALL_B_PORT)>>(M2_HALL_B_LSR)); - motor_read = (motor_read & M2_HALL_C_MASK) | (uint8_t)((PORT->Group[M2_HALL_C_GROUP].IN.reg & M2_HALL_C_PORT)>>(M2_HALL_C_LSR)); + motor_read = (motor_read & M2_HALL_A_MASK) | (uint8_t)((PORT->Group[M2_HALL_A_GROUP].IN.reg & M2_HALL_A_PORT)>>(M2_HALL_A_LSR)); + motor_read = (motor_read & M2_HALL_B_MASK) | (uint8_t)((PORT->Group[M2_HALL_B_GROUP].IN.reg & M2_HALL_B_PORT)>>(M2_HALL_B_LSR)); + motor_read = (motor_read & M2_HALL_C_MASK) | (uint8_t)((PORT->Group[M2_HALL_C_GROUP].IN.reg & M2_HALL_C_PORT)>>(M2_HALL_C_LSR)); return motor_read; - //if(((motor_read == INVALID_HALL_0) || (motor_read == INVALID_HALL_7))) { //Motor2.motor_state.fault = MOTOR_HALLSENSORINVALID; //Motor2.motor_state.currentstate = MOTOR_FAULT; diff --git a/2_Motor_Slave/Motor_Slave/Motor_Slave/bldc.h b/2_Motor_Slave/Motor_Slave/Motor_Slave/bldc.h index c07cdb6..55b82cc 100644 --- a/2_Motor_Slave/Motor_Slave/Motor_Slave/bldc.h +++ b/2_Motor_Slave/Motor_Slave/Motor_Slave/bldc.h @@ -17,7 +17,7 @@ #include "statemachine.h" #define PWM_TOP (1000) -#define MAX_PWM (300) +#define MAX_PWM (800) //#define MAX_VEL 3800 #define CW (0) //CBA diff --git a/2_Motor_Slave/Motor_Slave/Motor_Slave/configuration.h b/2_Motor_Slave/Motor_Slave/Motor_Slave/configuration.h index 8b43432..5ced8ec 100644 --- a/2_Motor_Slave/Motor_Slave/Motor_Slave/configuration.h +++ b/2_Motor_Slave/Motor_Slave/Motor_Slave/configuration.h @@ -23,7 +23,7 @@ // M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6] // ---------------------------------------------------------------------- #define DMAC_CHANNEL_ADC_SEQ 2U -#define DMAC_CHANNEL_ADC_SRAM 3U +#define DMAC_CHANNEL_ADC_SRAM 1U /* Single Ended */ //const uint32_t adc_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808}; @@ -40,7 +40,7 @@ struct _dma_resource *adc_dmac_sequence_resource; /* DMA channel for SPI Slave TX and RX */ #define CONF_SERCOM_1_RECEIVE_DMA_CHANNEL 0U -#define CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL 1U +#define CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL 3U //static uint8_t tx_buffer[SLAVE_BUFFER_SIZE] = {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, 0xff, 0xff}; diff --git a/2_Motor_Slave/Motor_Slave/Motor_Slave/main.c b/2_Motor_Slave/Motor_Slave/Motor_Slave/main.c index 99a1c4f..d884679 100644 --- a/2_Motor_Slave/Motor_Slave/Motor_Slave/main.c +++ b/2_Motor_Slave/Motor_Slave/Motor_Slave/main.c @@ -87,8 +87,8 @@ void SERCOM1_1_Handler() //SPI_tx_buffer[0] += 1; //tx_buffer[31] += 1; - DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - DMAC->Channel[1].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC->Channel[CONF_SERCOM_1_RECEIVE_DMA_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC->Channel[CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; //_dma_enable_transaction(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, false); //_dma_enable_transaction(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, false); @@ -140,6 +140,8 @@ void enable_NVIC_IRQ(void) NVIC_EnableIRQ(TCC1_0_IRQn); //NVIC_EnableIRQ(SERCOM1_3_IRQn); //NVIC_SetPriority(SERCOM1_3_IRQn, 0); + NVIC_EnableIRQ(SERCOM1_1_IRQn); + NVIC_SetPriority(SERCOM1_1_IRQn, 1); //NVIC_EnableIRQ(SERCOM1_3_IRQn); //NVIC_EnableIRQ(EIC_5_IRQn); } @@ -223,7 +225,7 @@ int main(void) configure_tcc_pwm(); adc_sync_enable_channel(&ADC_1, 6); //ECAT_STATE_MACHINE(); - //adc_init_dma(); + adc_init_dma(); boardToBoardTransferInit(); init_spi_slave_dma_descriptors(); @@ -232,8 +234,8 @@ int main(void) custom_logic_enable(); enable_NVIC_IRQ(); - DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - DMAC->Channel[1].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC->Channel[CONF_SERCOM_1_RECEIVE_DMA_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC->Channel[CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; //_dma_enable_transaction(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, false); //_dma_enable_transaction(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, false); @@ -247,19 +249,19 @@ int main(void) /* Replace with your application code */ while (1) { - //if (Motor1.timerflags.adc_readings_ready_tic) {process_currents();} - //if (Motor1.timerflags.current_loop_tic) { - //APPLICATION_StateMachine(); - //exec_commutation(&Motor1); + if (Motor1.timerflags.adc_readings_ready_tic) {process_currents();} + if (Motor1.timerflags.current_loop_tic) { + APPLICATION_StateMachine(); + exec_commutation(&Motor1); ////exec_commutation(&Motor2); - //} + } if (Motor1.timerflags.motor_telemetry_flag) { Motor1.timerflags.motor_telemetry_flag = false; update_telemetry(); update_setpoints(); - APPLICATION_StateMachine(); - exec_commutation(&Motor1); + //APPLICATION_StateMachine(); + //exec_commutation(&Motor1); //exec_commutation(&Motor2); //*M3_Joint_abs_position = as5048a_getRawRotation(&AS_1); //*M3_Joint_abs_position = as5048a_getRotationDecInt(&AS_1); diff --git a/2_Motor_Slave/Motor_Slave/Motor_Slave/motorparameters.h b/2_Motor_Slave/Motor_Slave/Motor_Slave/motorparameters.h index 4e405b4..8491f2d 100644 --- a/2_Motor_Slave/Motor_Slave/Motor_Slave/motorparameters.h +++ b/2_Motor_Slave/Motor_Slave/Motor_Slave/motorparameters.h @@ -133,6 +133,7 @@ typedef struct const float32_t motor_Max_Spd_ELEC; const float32_t motor_Max_Current_IDC_A; MOTOR_Control_Structs controller_param; + float32_t motor_MaxPWM; } BLDCMotor_param_t; //static BLDCMotor_param_t FH_22mm24BXTR; @@ -152,12 +153,41 @@ const static BLDCMotor_param_t FH_22mm24BXTR = { .motor_Max_Spd_RPM = 3000, .motor_MeasureRange_RPM = 3000 * 1.2, //(1.2f * MOTOR_MAX_SPD_RPM)f // give 20% headroom .motor_Max_Spd_ELEC = (3000/60)*7.0, //(MOTOR_MAX_SPD_RPM/60)*MOTOR_POLEPAIRS - .motor_Max_Current_IDC_A = 0.368, + //.motor_Max_Current_IDC_A = 0.368, + .motor_Max_Current_IDC_A = 0.180, .controller_param.Pid_Speed.Kp = 0.00008f, .controller_param.Pid_Speed.Ki = 0.0000001f, //.controller_param.Pid_Speed.Ki = 0.0000001f, .controller_param.Pi_Pos.Kp = 50.0f, .controller_param.Pi_Pos.Ki = 0.0f, + .motor_MaxPWM = 800.0, +}; + + +/* Big Motor - 3216W012BXTR */ +const static BLDCMotor_param_t FH_32mm12BXTR = { + .pwm_desc = &PWM_1, + .speedtimer_hw = TC4, + .motor_Poles = 14, + .motor_polePairs = 7, + .motor_commutationStates = 42, //polePairs * 6 + .motor_RS_Ohm = 0.88, + .motor_LD_H = 0.000331, + .motor_LQ_H = 0.000331, + .motor_Flux_WB = 0.0063879968, + .motor_Max_Spd_RPM = 1000, + .motor_MeasureRange_RPM = 3200, //(1.2f * MOTOR_MAX_SPD_RPM)f // give 20% headroom + .motor_Max_Spd_ELEC = 12000, //(MOTOR_MAX_SPD_RPM/60)*MOTOR_POLEPAIRS + .motor_Max_Current_IDC_A = (1.2), + .controller_param.Pid_Speed.Kp = 0.0004f, + .controller_param.Pid_Speed.Ki = 0.0000001f, + .controller_param.Pi_Pos.Kp = 50.0f, + .controller_param.Pi_Pos.Ki = 0.000f, + //.controller_param.Pid_Speed.Kp = 0.00002f, + //.controller_param.Pid_Speed.Ki = 0.0f, + //.controller_param.Pi_Pos.Kp = 4.0f, + //.controller_param.Pi_Pos.Ki = 0.0f, + .motor_MaxPWM = 250.0, }; /* Big Motor - 3216W024BXTR */ @@ -179,6 +209,11 @@ const static BLDCMotor_param_t FH_32mm24BXTR = { .controller_param.Pid_Speed.Ki = 0.0000001f, .controller_param.Pi_Pos.Kp = 40.0f, .controller_param.Pi_Pos.Ki = 0.0f, + .motor_MaxPWM = 800.0, + //.controller_param.Pid_Speed.Kp = 0.00002f, + //.controller_param.Pid_Speed.Ki = 0.0f, + //.controller_param.Pi_Pos.Kp = 4.0f, + //.controller_param.Pi_Pos.Ki = 0.0f, }; #endif /* MOTORPARAMETERS_H_ */ \ No newline at end of file diff --git a/Twincat/MotorData/.vs/MotorData/v15/.suo b/Twincat/MotorData/.vs/MotorData/v15/.suo index b8c8bf1..fd8227e 100644 Binary files a/Twincat/MotorData/.vs/MotorData/v15/.suo and b/Twincat/MotorData/.vs/MotorData/v15/.suo differ diff --git a/Twincat/MotorData/MotorData/Motordata_PLC/POUs/POU_Position_Seq.TcPOU b/Twincat/MotorData/MotorData/Motordata_PLC/POUs/POU_Position_Seq.TcPOU index 2d4df4b..7661377 100644 --- a/Twincat/MotorData/MotorData/Motordata_PLC/POUs/POU_Position_Seq.TcPOU +++ b/Twincat/MotorData/MotorData/Motordata_PLC/POUs/POU_Position_Seq.TcPOU @@ -1102,7 +1102,8 @@ END_VAR +GVL_motor_data.M2_Desired_pos := 1000; +GVL_motor_data.M3_Desired_pos := 1000;]]> @@ -1121,7 +1122,8 @@ GVL_motor_data.M2_Desired_pos := 1000;]]> +GVL_motor_data.M2_Desired_pos := -500; +GVL_motor_data.M3_Desired_pos := -500;]]> @@ -1140,7 +1142,8 @@ GVL_motor_data.M2_Desired_pos := -500;]]> +GVL_motor_data.M2_Desired_pos := 0; +GVL_motor_data.M3_Desired_pos := 0;]]> @@ -1254,14 +1257,17 @@ GVL_motor_data.M2_Desired_pos := 0;]]> + + + \ No newline at end of file diff --git a/Twincat/MotorData/Scope Project1.svdx b/Twincat/MotorData/Scope Project1.svdx index 5d82329..821ca84 100644 Binary files a/Twincat/MotorData/Scope Project1.svdx and b/Twincat/MotorData/Scope Project1.svdx differ diff --git a/Twincat/MotorData/TwinCAT Measurement Project1/Scope Project1.tcscopex b/Twincat/MotorData/TwinCAT Measurement Project1/Scope Project1.tcscopex index bd3a210..560edf3 100644 --- a/Twincat/MotorData/TwinCAT Measurement Project1/Scope Project1.tcscopex +++ b/Twincat/MotorData/TwinCAT Measurement Project1/Scope Project1.tcscopex @@ -15,8 +15,8 @@ false <?xml version="1.0" encoding="utf-16"?> <Layout> - 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