nick
/
thesis_bldc_controller
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fixed stuff with edmundo

This commit is contained in:
Nicolas Trimborn 2021-08-31 19:38:28 +02:00
parent 2d40de8228
commit fc9c6b483c
11 changed files with 94 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

59
2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart
View File

@ -272,8 +272,7 @@ drivers:
the transaction
dmac_blockact_1: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_10: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_10: Channel suspend operation is complete
dmac_blockact_11: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_12: Channel will be disabled if it is the last block transfer
@ -326,10 +325,8 @@ drivers:
the transaction and block interrupt
dmac_blockact_6: Channel suspend operation is complete
dmac_blockact_7: Channel suspend operation is complete
dmac_blockact_8: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_9: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_8: Channel suspend operation is complete
dmac_blockact_9: Channel suspend operation is complete
dmac_channel_0_settings: false
dmac_channel_10_settings: true
dmac_channel_11_settings: false
@ -398,7 +395,7 @@ drivers:
dmac_enable: true
dmac_evact_0: No action
dmac_evact_1: No action
dmac_evact_10: No action
dmac_evact_10: Channel resume operation
dmac_evact_11: No action
dmac_evact_12: No action
dmac_evact_13: No action
@ -426,11 +423,11 @@ drivers:
dmac_evact_5: No action
dmac_evact_6: Channel resume operation
dmac_evact_7: Channel resume operation
dmac_evact_8: No action
dmac_evact_9: No action
dmac_evact_8: Channel resume operation
dmac_evact_9: Channel resume operation
dmac_evie_0: false
dmac_evie_1: false
dmac_evie_10: false
dmac_evie_10: true
dmac_evie_11: false
dmac_evie_12: false
dmac_evie_13: false
@ -458,8 +455,8 @@ drivers:
dmac_evie_5: false
dmac_evie_6: true
dmac_evie_7: true
dmac_evie_8: false
dmac_evie_9: false
dmac_evie_8: true
dmac_evie_9: true
dmac_evoe_0: false
dmac_evoe_1: true
dmac_evoe_10: false
@ -827,7 +824,7 @@ drivers:
eic_arch_extinteo13: false
eic_arch_extinteo14: false
eic_arch_extinteo15: false
eic_arch_extinteo2: false
eic_arch_extinteo2: true
eic_arch_extinteo3: false
eic_arch_extinteo4: false
eic_arch_extinteo5: false
@ -951,7 +948,7 @@ drivers:
evsys_channel_37: No channel output selected
evsys_channel_38: No channel output selected
evsys_channel_39: No channel output selected
evsys_channel_4: No channel output selected
evsys_channel_4: Channel 6
evsys_channel_40: No channel output selected
evsys_channel_41: No channel output selected
evsys_channel_42: No channel output selected
@ -1011,8 +1008,8 @@ drivers:
evsys_channel_setting_30: false
evsys_channel_setting_31: false
evsys_channel_setting_4: true
evsys_channel_setting_5: false
evsys_channel_setting_6: false
evsys_channel_setting_5: true
evsys_channel_setting_6: true
evsys_channel_setting_7: false
evsys_channel_setting_8: false
evsys_channel_setting_9: false
@ -1072,8 +1069,8 @@ drivers:
generator
evsys_edgsel_5: Event is detected on the rising edge of the signal from event
generator
evsys_edgsel_6: No event output when using the resynchronized or synchronous
path
evsys_edgsel_6: Event is detected on the rising edge of the signal from event
generator
evsys_edgsel_7: No event output when using the resynchronized or synchronous
path
evsys_edgsel_8: No event output when using the resynchronized or synchronous
@ -1108,7 +1105,7 @@ drivers:
evsys_evd_31: false
evsys_evd_4: true
evsys_evd_5: true
evsys_evd_6: false
evsys_evd_6: true
evsys_evd_7: false
evsys_evd_8: false
evsys_evd_9: false
@ -1140,7 +1137,7 @@ drivers:
evsys_evgen_31: No event generator
evsys_evgen_4: DMAC channel 1
evsys_evgen_5: DMAC channel 2
evsys_evgen_6: No event generator
evsys_evgen_6: EIC external interrupt 2
evsys_evgen_7: No event generator
evsys_evgen_8: No event generator
evsys_evgen_9: No event generator
@ -1236,7 +1233,7 @@ drivers:
evsys_path_31: Synchronous path
evsys_path_4: Synchronous path
evsys_path_5: Synchronous path
evsys_path_6: Synchronous path
evsys_path_6: Asynchronous path
evsys_path_7: Synchronous path
evsys_path_8: Synchronous path
evsys_path_9: Synchronous path
@ -1344,10 +1341,10 @@ drivers:
functionality: System
api: HAL:HPL:GCLK
configuration:
$input: 100000000
$input_id: Digital Phase Locked Loop (DPLL1)
RESERVED_InputFreq: 100000000
RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL1)
$input: 12000000
$input_id: External Crystal Oscillator 8-48MHz (XOSC1)
RESERVED_InputFreq: 12000000
RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1)
_$freq_output_Generic clock generator 0: 100000000
_$freq_output_Generic clock generator 1: 2000000
_$freq_output_Generic clock generator 10: 12000000
@ -1643,20 +1640,20 @@ drivers:
configuration:
enable_port_input_event_0: true
enable_port_input_event_1: true
enable_port_input_event_2: false
enable_port_input_event_3: false
enable_port_input_event_2: true
enable_port_input_event_3: true
porta_event_action_0: Output register of pin will be set to level of event
porta_event_action_1: Output register of pin will be set to level of event
porta_event_action_2: Set output register of pin on event
porta_event_action_3: Output register of pin will be set to level of event
porta_event_action_3: Clear output register of pin on event
porta_event_pin_identifier_0: 0
porta_event_pin_identifier_1: 0
porta_event_pin_identifier_2: 14
porta_event_pin_identifier_3: 0
porta_event_pin_identifier_3: 14
porta_input_event_enable_0: false
porta_input_event_enable_1: false
porta_input_event_enable_2: false
porta_input_event_enable_3: false
porta_input_event_enable_2: true
porta_input_event_enable_3: true
portb_event_action_0: Clear output register of pin on event
portb_event_action_1: Set output register of pin on event
portb_event_action_2: Output register of pin will be set to level of event

1
2_Motor_Master/Motor_Master/Motor_Master/ADS1299.c
View File

@ -120,7 +120,6 @@ void ADS1299_START() { //start data conversion
gpio_set_pin_level(ADS1299.SS_pin, false);
_transfer_byte(ADS1299.SPI_descr, _START);
gpio_set_pin_level(ADS1299.SS_pin, true);
delay_us(20);
init_streaming_mode();
}

18
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_dmac_config.h
View File

@ -2031,7 +2031,7 @@
// <i> Indicates whether channel event reception is enabled or not
// <id> dmac_evie_8
#ifndef CONF_DMAC_EVIE_8
#define CONF_DMAC_EVIE_8 0
#define CONF_DMAC_EVIE_8 1
#endif
// <o> Event Input Action
@ -2045,7 +2045,7 @@
// <i> Defines the event input action
// <id> dmac_evact_8
#ifndef CONF_DMAC_EVACT_8
#define CONF_DMAC_EVACT_8 0
#define CONF_DMAC_EVACT_8 5
#endif
// <o> Address Increment Step Size
@ -2104,7 +2104,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_8
#ifndef CONF_DMAC_BLOCKACT_8
#define CONF_DMAC_BLOCKACT_8 0
#define CONF_DMAC_BLOCKACT_8 2
#endif
// <o> Event Output Selection
@ -2255,7 +2255,7 @@
// <i> Indicates whether channel event reception is enabled or not
// <id> dmac_evie_9
#ifndef CONF_DMAC_EVIE_9
#define CONF_DMAC_EVIE_9 0
#define CONF_DMAC_EVIE_9 1
#endif
// <o> Event Input Action
@ -2269,7 +2269,7 @@
// <i> Defines the event input action
// <id> dmac_evact_9
#ifndef CONF_DMAC_EVACT_9
#define CONF_DMAC_EVACT_9 0
#define CONF_DMAC_EVACT_9 5
#endif
// <o> Address Increment Step Size
@ -2328,7 +2328,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_9
#ifndef CONF_DMAC_BLOCKACT_9
#define CONF_DMAC_BLOCKACT_9 0
#define CONF_DMAC_BLOCKACT_9 2
#endif
// <o> Event Output Selection
@ -2479,7 +2479,7 @@
// <i> Indicates whether channel event reception is enabled or not
// <id> dmac_evie_10
#ifndef CONF_DMAC_EVIE_10
#define CONF_DMAC_EVIE_10 0
#define CONF_DMAC_EVIE_10 1
#endif
// <o> Event Input Action
@ -2493,7 +2493,7 @@
// <i> Defines the event input action
// <id> dmac_evact_10
#ifndef CONF_DMAC_EVACT_10
#define CONF_DMAC_EVACT_10 0
#define CONF_DMAC_EVACT_10 5
#endif
// <o> Address Increment Step Size
@ -2552,7 +2552,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_10
#ifndef CONF_DMAC_BLOCKACT_10
#define CONF_DMAC_BLOCKACT_10 0
#define CONF_DMAC_BLOCKACT_10 2
#endif
// <o> Event Output Selection

2
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_eic_config.h
View File

@ -182,7 +182,7 @@
// <i> Indicates whether the external interrupt 2 event output is enabled or not
// <id> eic_arch_extinteo2
#ifndef CONF_EIC_EXTINTEO2
#define CONF_EIC_EXTINTEO2 0
#define CONF_EIC_EXTINTEO2 1
#endif
// <y> Input 2 Sense Configuration

14
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_evsys_config.h
View File

@ -912,7 +912,7 @@
// <e> Channel 5 settings
// <id> evsys_channel_setting_5
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_5
#define CONF_EVSYS_CHANNEL_SETTINGS_5 0
#define CONF_EVSYS_CHANNEL_SETTINGS_5 1
#endif
// <y> Edge detection
@ -1093,7 +1093,7 @@
// <e> Channel 6 settings
// <id> evsys_channel_setting_6
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_6
#define CONF_EVSYS_CHANNEL_SETTINGS_6 0
#define CONF_EVSYS_CHANNEL_SETTINGS_6 1
#endif
// <y> Edge detection
@ -1104,7 +1104,7 @@
// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
// <id> evsys_edgsel_6
#ifndef CONF_EDGSEL_6
#define CONF_EDGSEL_6 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
#define CONF_EDGSEL_6 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
#endif
// <y> Path selection
@ -1114,7 +1114,7 @@
// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
// <id> evsys_path_6
#ifndef CONF_PATH_6
#define CONF_PATH_6 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
#define CONF_PATH_6 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
#endif
// <o> Event generator
@ -1238,7 +1238,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_6
#ifndef CONF_EVGEN_6
#define CONF_EVGEN_6 0
#define CONF_EVGEN_6 20
#endif
// <q> Overrun channel interrupt
@ -1252,7 +1252,7 @@
// <i> Indicates whether event detected interrupt is enabled or not
// <id> evsys_evd_6
#ifndef CONF_EVD_6
#define CONF_EVD_6 0
#define CONF_EVD_6 1
#endif
// <q> On demand clock
@ -6000,7 +6000,7 @@
// <id> evsys_channel_4
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_4
#define CONF_CHANNEL_4 0
#define CONF_CHANNEL_4 7
#endif
//</h>

12
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_port_config.h
View File

@ -137,7 +137,7 @@
// <e> PORT Input Event 2 configuration
// <id> enable_port_input_event_2
#ifndef CONF_PORT_EVCTRL_PORT_2
#define CONF_PORT_EVCTRL_PORT_2 0
#define CONF_PORT_EVCTRL_PORT_2 1
#endif
// <h> PORT Input Event 2 configuration on PORT A
@ -146,7 +146,7 @@
// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
// <id> porta_input_event_enable_2
#ifndef CONF_PORTA_EVCTRL_PORTEI_2
#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
#define CONF_PORTA_EVCTRL_PORTEI_2 0x1
#endif
// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
@ -202,7 +202,7 @@
// <e> PORT Input Event 3 configuration
// <id> enable_port_input_event_3
#ifndef CONF_PORT_EVCTRL_PORT_3
#define CONF_PORT_EVCTRL_PORT_3 0
#define CONF_PORT_EVCTRL_PORT_3 1
#endif
// <h> PORT Input Event 3 configuration on PORT A
@ -211,14 +211,14 @@
// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
// <id> porta_input_event_enable_3
#ifndef CONF_PORTA_EVCTRL_PORTEI_3
#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
#define CONF_PORTA_EVCTRL_PORTEI_3 0x1
#endif
// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_3
#ifndef CONF_PORTA_EVCTRL_PID_3
#define CONF_PORTA_EVCTRL_PID_3 0x0
#define CONF_PORTA_EVCTRL_PID_3 0xe
#endif
// <o> PORTA Event 3 Action
@ -229,7 +229,7 @@
// <i> These bits define the event action the PORT A will perform on event input 3
// <id> porta_event_action_3
#ifndef CONF_PORTA_EVCTRL_EVACT_3
#define CONF_PORTA_EVCTRL_EVACT_3 0
#define CONF_PORTA_EVCTRL_EVACT_3 2
#endif
// </h>

10
2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj
View File

@ -150,7 +150,7 @@
<AcmeProjectActionInfo Action="File" Source="hri/hri_usb_e51.h" IsConfig="false" Hash="x6M7vYgNCS2oECqykr5+yw" />
<AcmeProjectActionInfo Action="File" Source="hri/hri_wdt_e51.h" IsConfig="false" Hash="o9Rg/hyuMzwOCphVc7uG1w" />
<AcmeProjectActionInfo Action="File" Source="main.c" IsConfig="false" Hash="k0AH7j+BrmdFhBPzCCMptA" />
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="G20g4A90o1iiMw5JKqZlrQ" />
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="FNBo89HkbG68dEmgi30eyQ" />
<AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="NyJtBqCuH2RlTy0iltvcfg" />
<AcmeProjectActionInfo Action="File" Source="atmel_start_pins.h" IsConfig="false" Hash="q332kmNEqTBha3F9F86pCg" />
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="yuNriNBbj5kyY6X2I3Qu+A" />
@ -206,14 +206,14 @@
<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="IJeJ3sDxG9f3mmsLxoMLlA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="GtvN6cIK8Fs/kg861j+0lg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="q6198/8IUrGygCgey3ZoQw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="VFsyUAbyj+4noNzt5pFGdg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="Ugqkh4JI/bavEsL6AOVmkA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="Zre11F0UnVVaJqMRScEOwA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="45sXrEEoF/ulrCsrA93KmA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Xe5v62bijwZLOPLD+rPcrA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="GyB7m/Yo05896J0mPhiOaw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="ClWspYc5VwPMxMXzZp6pSw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_qspi_config.h" IsConfig="true" Hash="CwZ360eeEYs7T9SYFSvDug" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="YhOvJRia1eKe9odgdXn9EQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" />

9
2_Motor_Master/Motor_Master/Motor_Master/configuration.h
View File

@ -162,14 +162,18 @@ static void spi_master_init_dma_descriptors()
_dma_set_data_amount(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, MASTER_BUFFER_SIZE_LONG);
_dma_set_next_descriptor(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL);
_dma_set_source_address(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, &QSPI_rx_buffer[16]);
_dma_set_destination_address(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
_dma_set_data_amount(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, MASTER_BUFFER_SIZE_LONG);
_dma_set_next_descriptor(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL]);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL]);
/* callback */
//struct _dma_resource *resource_rx, *resource_tx;
//_dma_get_channel_resource(&resource_rx, CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL);
@ -204,13 +208,14 @@ static void spi_ads1299_init_dma_descriptors()
(uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg));
_dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, &_ads1299_channel_data[0]);
_dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, ADS_BUFFER_SIZE);
//_dma_set_next_descriptor(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL);
_dma_set_next_descriptor(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL);
_dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, &ads1299_buffer[0]);
_dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg));
_dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, ADS_BUFFER_SIZE);
_dma_set_next_descriptor(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL]);
@ -228,6 +233,8 @@ static void spi_ads1299_init_dma_descriptors()
_dma_set_irq_state(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
//_dma_set_irq_state(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, DMA_TRANSFER_ERROR_CB, true);
}

1
2_Motor_Master/Motor_Master/Motor_Master/driver_init.c
View File

@ -165,6 +165,7 @@ void EVENT_SYSTEM_0_init(void)
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_3, CONF_GCLK_EVSYS_CHANNEL_3_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_4, CONF_GCLK_EVSYS_CHANNEL_4_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_5, CONF_GCLK_EVSYS_CHANNEL_5_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_6, CONF_GCLK_EVSYS_CHANNEL_6_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);

2
2_Motor_Master/Motor_Master/Motor_Master/interrupts.h
View File

@ -139,7 +139,7 @@ void ADS1299_dataReadyISR(void)
void ADS1299_Transfer_Complete_cb(void)
{
PORT->Group[0].OUTSET.reg = (1<<GPIO_PIN(SPI2_SS));
//PORT->Group[0].OUTSET.reg = (1<<GPIO_PIN(SPI2_SS));
volatile int x = 1;
}

41
2_Motor_Master/Motor_Master/Motor_Master/main.c
View File

@ -184,9 +184,16 @@ int main(void)
__enable_irq();
ADS1299_START();
/* ADS Result Ready Interrupt, active low */
/* Enable Reception */
_dma_enable_transaction(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, false);
_dma_enable_transaction(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, false);
EIC->INTFLAG.bit.EXTINT = (1<<2);
ext_irq_register(GPIO_PIN(ADS_DATA_RDY), ADS1299_dataReadyISR);
enable_NVIC_IRQ();
/* Replace with your application code */
while (1) {
if (Motor1.timerflags.adc_readings_ready_tic) {process_currents();}
@ -194,16 +201,18 @@ int main(void)
if (Motor1.timerflags.motor_telemetry_flag) {
Motor1.timerflags.motor_telemetry_flag = false;
//delay_us(10);
DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
//DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
if (DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLA.bit.ENABLE)
{
/* Resume */
DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLB.bit.CMD = 0x02;
}
else {
/* Enable */
DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
}
if (DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHSTATUS.bit.PEND == true)
{
volatile int x = 0;
}
update_telemetry();
update_setpoints();
@ -235,15 +244,21 @@ int main(void)
if (ADS1299.data_ReadyFlag){
ADS1299.data_ReadyFlag = false;
PORT->Group[0].OUTCLR.reg = (1<<GPIO_PIN(SPI2_SS));
//PORT->Group[0].OUTCLR.reg = (1<<GPIO_PIN(SPI2_SS));
if ((DMAC->Channel[2].CHSTATUS.bit.FERR == true) || (DMAC->Channel[8].CHSTATUS.bit.FERR == true))
if (DMAC->Channel[8].CHCTRLA.bit.ENABLE)
{
/* Resume */
DMAC->Channel[8].CHCTRLB.bit.CMD = 0x02;
volatile int x = 0;
}
DMAC->Channel[2].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
else {
//DMAC->Channel[2].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
/* Enable */
DMAC->Channel[8].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
}
//_dma_enable_transaction(2, false);
//_dma_enable_transaction(8, false);