85 lines
3.1 KiB
C
85 lines
3.1 KiB
C
#include <samd21g18a.h>
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#include <string.h>
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#include "DMA.h"
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#define MAX_DESCRIPTORS 2
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__attribute__((__aligned__(16))) static DmacDescriptor descriptor_section[MAX_DESCRIPTORS];
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__attribute__((__aligned__(16))) static DmacDescriptor write_back_section[MAX_DESCRIPTORS];
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static int used_channels = 0;
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int volatile dma_frame = 0;
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void DMA_init(void)
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{
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static int initialized = 0;
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if (!initialized)
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{
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/* enable peripheral clock */
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PM->APBBMASK.bit.DMAC_ = 1;
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/* enable AHB master clock */
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PM->AHBMASK.bit.DMAC_ = 1;
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/* configure DMA controller */
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DMAC->BASEADDR.reg = (uint32_t)descriptor_section; // descriptor memory section start
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DMAC->WRBADDR.reg = (uint32_t)write_back_section; // descriptor write-back memory section start
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DMAC->CTRL.bit.LVLEN0 = 1; // enable level 0 priority
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DMAC->CTRL.bit.LVLEN1 = 1; // enable level 1 priority
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DMAC->CTRL.bit.LVLEN2 = 1; // enable level 2 priority
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DMAC->CTRL.bit.LVLEN3 = 1; // enable level 3 priority
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/* DMA is initialized */
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initialized = 1;
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}
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}
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/* add the first least significant free channel with its descriptor (TODO: implement linked descriptors) */
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void DMA_add_channel(int source, DmacDescriptor *descriptor)
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{
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/* disable DMA if enabled */
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if (DMAC->CTRL.bit.DMAENABLE)
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DMAC->CTRL.bit.DMAENABLE = 0;
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while (DMAC->CTRL.bit.DMAENABLE)
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;
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/* add transfer descriptor to transfer descriptor section (before enabling channel!) */
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memcpy(descriptor_section + used_channels * sizeof(DmacDescriptor), descriptor, sizeof(DmacDescriptor));
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/* configure and enable first least significant free channel */
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DMAC->CHID.bit.ID = used_channels++; // use first free channel
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DMAC->CHCTRLB.bit.LVL = 0x00; // channel priority level 0
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DMAC->CHCTRLB.bit.TRIGACT = 0x02; // one trigger each beat transfer
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DMAC->CHCTRLB.bit.TRIGSRC = source; // select trigger source
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DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; // enable channel
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/* enable DMA block transfer complete interrupt */
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DMAC->CHINTENSET.bit.TCMPL = 1; // enable DMA block transfer complete interrupt
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NVIC_EnableIRQ(DMAC_IRQn); // enable DMA interrupt in NVIC
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}
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void DMA_enable(void)
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{
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/* enable DMA controller */
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DMAC->CTRL.bit.DMAENABLE = 1;
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}
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void DMAC_Handler(void)
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{
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//static int count;
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for (int channel = 0 ; channel < used_channels ; channel++) // check interrupt for every registered channel
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{
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DMAC->CHID.bit.ID = channel;
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if (DMAC->CHINTFLAG.bit.TCMPL && DMAC->CHINTENSET.bit.TCMPL)
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{
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if (DMAC->CHID.bit.ID == 0x00) // handle SPI transfer complete interrupt
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{
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DMAC->CHINTFLAG.bit.TCMPL = 1; // acknowledge interrupt
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DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; // re-enable DMA channel
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}
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}
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}
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}
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