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added net ties and additional memory footprints

This commit is contained in:
Nick Trimborn 2023-08-22 17:48:35 +02:00
parent 643944d758
commit 9f5585cf3c
4 changed files with 48 additions and 20 deletions
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Footprint-Lib-NickPartLib.PcbLib
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Memory.SchLib
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Net_Ties.SchLib Normal file
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NicksPartsLib.LibPkg
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@ -37,7 +37,7 @@ OutputPath=
LogFolderPath=
ManagedProjectGUID=
IncludeDesignInRelease=0
CrossRefSheetStyle=1
CrossRefSheetStyle=2
CrossRefLocationStyle=1
CrossRefPorts=3
CrossRefCrossSheets=1
@ -507,6 +507,23 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=DCRBOPUS
[Document28]
DocumentPath=Net_Ties.SchLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=MRFWLEEX
[GeneratedDocument1]
DocumentPath=Mosfets.cmp
DItemRevisionGUID=
@ -736,18 +753,6 @@ OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType14=PCBDrawing
OutputName14=Draftsman
OutputDocumentPath14=
OutputVariantName14=[No Variations]
OutputDefault14=0
PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType15=PCBDrawing
OutputName15=Draftsman
OutputDocumentPath15=
OutputVariantName15=[No Variations]
OutputDefault15=0
PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
[OutputGroup4]
Name=Assembly Outputs
@ -891,12 +896,6 @@ OutputName8=Report Single Pin Nets
OutputDocumentPath8=
OutputVariantName8=[No Variations]
OutputDefault8=0
OutputType9=Project History
OutputName9=Project History
OutputDocumentPath9=
OutputVariantName9=[No Variations]
OutputDefault9=0
PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
[OutputGroup7]
Name=Other Outputs
@ -1115,6 +1114,36 @@ OutputName12=Web Review Data
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=Ansoft Neutral
OutputName13=Ansoft Neutral (AutoPCB)
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=HyperLynx
OutputName14=HyperLynx (AutoPCB)
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=Orcad v7 Capture Design
OutputName15=Orcad v7 Capture Design (AutoSCH)
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=P-CAD ASCII
OutputName16=P-CAD ASCII (AutoPCB)
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=P-CAD V16 Schematic Design
OutputName17=P-CAD V16 Schematic Design (AutoSCH)
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
OutputType18=SiSoft
OutputName18=SiSoft (AutoPCB)
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
[OutputGroup10]
Name=PostProcess Outputs
@ -1247,7 +1276,6 @@ Type116=1
Type117=1
Type118=1
Type119=1
Type120=1
[Difference Levels]
Type1=1