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added master/slave IF. Still having issues with ADC and SPI dma

This commit is contained in:
Nicolas Trimborn 2021-08-18 19:38:37 +02:00
parent c415d29ee0
commit 012e0f87c5
238 changed files with 186131 additions and 185 deletions
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3
2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/AtmelStart.gpdsc
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@ -49,6 +49,7 @@
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/pwm.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/quad_spi_dma.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_async.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_dma.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_sync.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/timer.rst"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
@ -63,6 +64,7 @@
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_qspi_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_cmcc.h"/>
@ -176,6 +178,7 @@
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_ext_irq.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_pwm.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_async.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_dma.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_timer.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>

44
2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart
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@ -393,7 +393,7 @@ drivers:
the transaction
dmac_blockact_9: Channel will be disabled if it is the last block transfer in
the transaction
dmac_channel_0_settings: false
dmac_channel_0_settings: true
dmac_channel_10_settings: false
dmac_channel_11_settings: false
dmac_channel_12_settings: false
@ -404,7 +404,7 @@ drivers:
dmac_channel_17_settings: false
dmac_channel_18_settings: false
dmac_channel_19_settings: false
dmac_channel_1_settings: false
dmac_channel_1_settings: true
dmac_channel_20_settings: false
dmac_channel_21_settings: false
dmac_channel_22_settings: false
@ -426,7 +426,7 @@ drivers:
dmac_channel_8_settings: false
dmac_channel_9_settings: false
dmac_dbgrun: false
dmac_dstinc_0: false
dmac_dstinc_0: true
dmac_dstinc_1: false
dmac_dstinc_10: false
dmac_dstinc_11: false
@ -599,7 +599,7 @@ drivers:
dmac_lvl_17: Channel priority 0
dmac_lvl_18: Channel priority 0
dmac_lvl_19: Channel priority 0
dmac_lvl_2: Channel priority 0
dmac_lvl_2: Channel priority 1
dmac_lvl_20: Channel priority 0
dmac_lvl_21: Channel priority 0
dmac_lvl_22: Channel priority 0
@ -610,7 +610,7 @@ drivers:
dmac_lvl_27: Channel priority 0
dmac_lvl_28: Channel priority 0
dmac_lvl_29: Channel priority 0
dmac_lvl_3: Channel priority 0
dmac_lvl_3: Channel priority 1
dmac_lvl_30: Channel priority 0
dmac_lvl_31: Channel priority 0
dmac_lvl_4: Channel priority 0
@ -624,7 +624,7 @@ drivers:
dmac_lvlen2: true
dmac_lvlen3: true
dmac_lvlpri0: 0
dmac_lvlpri1: 0
dmac_lvlpri1: 1
dmac_lvlpri2: 0
dmac_lvlpri3: 0
dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
@ -664,7 +664,7 @@ drivers:
dmac_runstdby_8: false
dmac_runstdby_9: false
dmac_srcinc_0: false
dmac_srcinc_1: false
dmac_srcinc_1: true
dmac_srcinc_10: false
dmac_srcinc_11: false
dmac_srcinc_12: false
@ -696,7 +696,7 @@ drivers:
dmac_srcinc_8: false
dmac_srcinc_9: false
dmac_stepsel_0: Step size settings apply to the destination address
dmac_stepsel_1: Step size settings apply to the destination address
dmac_stepsel_1: Step size settings apply to the source address
dmac_stepsel_10: Step size settings apply to the destination address
dmac_stepsel_11: Step size settings apply to the destination address
dmac_stepsel_12: Step size settings apply to the destination address
@ -759,8 +759,8 @@ drivers:
dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_trifsrc_0: Only software/event triggers
dmac_trifsrc_1: Only software/event triggers
dmac_trifsrc_0: SERCOM1 RX Trigger
dmac_trifsrc_1: SERCOM1 TX Trigger
dmac_trifsrc_10: Only software/event triggers
dmac_trifsrc_11: Only software/event triggers
dmac_trifsrc_12: Only software/event triggers
@ -791,8 +791,8 @@ drivers:
dmac_trifsrc_7: Only software/event triggers
dmac_trifsrc_8: Only software/event triggers
dmac_trifsrc_9: Only software/event triggers
dmac_trigact_0: One trigger required for each block transfer
dmac_trigact_1: One trigger required for each block transfer
dmac_trigact_0: One trigger required for each beat transfer
dmac_trigact_1: One trigger required for each beat transfer
dmac_trigact_10: One trigger required for each block transfer
dmac_trigact_11: One trigger required for each block transfer
dmac_trigact_12: One trigger required for each block transfer
@ -1800,22 +1800,25 @@ drivers:
variant: null
clocks:
domain_group: null
SPI_1:
user_label: SPI_1
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::SERCOM1::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync
SPI_1_MSIF:
user_label: SPI_1_MSIF
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::SERCOM1::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.DMA
functionality: SPI
api: HAL:Driver:SPI_Master_Sync
api: HAL:Driver:SPI_Master_DMA
configuration:
spi_master_advanced: false
spi_master_advanced: true
spi_master_arch_cpha: Sample input on leading edge
spi_master_arch_cpol: SCK is low when idle
spi_master_arch_dbgstop: Keep running
spi_master_arch_dord: MSB first
spi_master_arch_ibon: In data stream
spi_master_arch_runstdby: false
spi_master_baud_rate: 50000
spi_master_baud_rate: 8000000
spi_master_character_size: 8 bits
spi_master_dma_rx_channel: 0
spi_master_dma_tx_channel: 1
spi_master_dummybyte: 511
spi_master_rx_channel: true
spi_master_rx_enable: true
optional_signals: []
variant:
@ -2535,9 +2538,10 @@ pads:
SPI1_CS:
name: PB22
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::pad::PB22
mode: Peripheral IO
mode: Digital output
user_label: SPI1_CS
configuration: null
configuration:
pad_initial_level: High
SPI1_MISO:
name: PB23
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::pad::PB23

24
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_dmac_config.h
View File

@ -51,7 +51,7 @@
// <o> Level 1 Channel Priority Number <0x00-0xFF>
// <id> dmac_lvlpri1
#ifndef CONF_DMAC_LVLPRI1
#define CONF_DMAC_LVLPRI1 0
#define CONF_DMAC_LVLPRI1 1
#endif
// <q> Priority Level 2
// <i> Indicates whether Priority Level 2 is enabled or not
@ -105,7 +105,7 @@
// <e> Channel 0 settings
// <id> dmac_channel_0_settings
#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
#define CONF_DMAC_CHANNEL_0_SETTINGS 0
#define CONF_DMAC_CHANNEL_0_SETTINGS 1
#endif
// <q> Channel Run in Standby
@ -122,7 +122,7 @@
// <i> Defines the trigger action used for a transfer
// <id> dmac_trigact_0
#ifndef CONF_DMAC_TRIGACT_0
#define CONF_DMAC_TRIGACT_0 0
#define CONF_DMAC_TRIGACT_0 2
#endif
// <o> Trigger source
@ -214,7 +214,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_0
#ifndef CONF_DMAC_TRIGSRC_0
#define CONF_DMAC_TRIGSRC_0 0
#define CONF_DMAC_TRIGSRC_0 6
#endif
// <o> Channel Arbitration Level
@ -291,7 +291,7 @@
// <i> Indicates whether the destination address incrementation is enabled or not
// <id> dmac_dstinc_0
#ifndef CONF_DMAC_DSTINC_0
#define CONF_DMAC_DSTINC_0 0
#define CONF_DMAC_DSTINC_0 1
#endif
// <o> Beat Size
@ -329,7 +329,7 @@
// <e> Channel 1 settings
// <id> dmac_channel_1_settings
#ifndef CONF_DMAC_CHANNEL_1_SETTINGS
#define CONF_DMAC_CHANNEL_1_SETTINGS 0
#define CONF_DMAC_CHANNEL_1_SETTINGS 1
#endif
// <q> Channel Run in Standby
@ -346,7 +346,7 @@
// <i> Defines the trigger action used for a transfer
// <id> dmac_trigact_1
#ifndef CONF_DMAC_TRIGACT_1
#define CONF_DMAC_TRIGACT_1 0
#define CONF_DMAC_TRIGACT_1 2
#endif
// <o> Trigger source
@ -438,7 +438,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_1
#ifndef CONF_DMAC_TRIGSRC_1
#define CONF_DMAC_TRIGSRC_1 0
#define CONF_DMAC_TRIGSRC_1 7
#endif
// <o> Channel Arbitration Level
@ -501,14 +501,14 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_1
#ifndef CONF_DMAC_STEPSEL_1
#define CONF_DMAC_STEPSEL_1 0
#define CONF_DMAC_STEPSEL_1 1
#endif
// <q> Source Address Increment
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_1
#ifndef CONF_DMAC_SRCINC_1
#define CONF_DMAC_SRCINC_1 0
#define CONF_DMAC_SRCINC_1 1
#endif
// <q> Destination Address Increment
@ -673,7 +673,7 @@
// <i> Defines the arbitration level for this channel
// <id> dmac_lvl_2
#ifndef CONF_DMAC_LVL_2
#define CONF_DMAC_LVL_2 0
#define CONF_DMAC_LVL_2 1
#endif
// <q> Channel Event Output
@ -897,7 +897,7 @@
// <i> Defines the arbitration level for this channel
// <id> dmac_lvl_3
#ifndef CONF_DMAC_LVL_3
#define CONF_DMAC_LVL_3 0
#define CONF_DMAC_LVL_3 1
#endif
// <q> Channel Event Output

26
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h
View File

@ -11,6 +11,28 @@
#define CONF_SERCOM_1_SPI_ENABLE 1
#endif
//<o> SPI DMA TX Channel <0-32>
//<i> This defines DMA channel to be used
//<id> spi_master_dma_tx_channel
#ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 1
#endif
// <e> SPI RX Channel Enable
// <id> spi_master_rx_channel
#ifndef CONF_SERCOM_1_SPI_RX_CHANNEL
#define CONF_SERCOM_1_SPI_RX_CHANNEL 1
#endif
//<o> DMA Channel <0-32>
//<i> This defines DMA channel to be used
//<id> spi_master_dma_rx_channel
#ifndef CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL
#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 0
#endif
// </e>
// Set module in SPI Master mode
#ifndef CONF_SERCOM_1_SPI_MODE
#define CONF_SERCOM_1_SPI_MODE 0x03
@ -37,7 +59,7 @@
// <i> The SPI data transfer rate
// <id> spi_master_baud_rate
#ifndef CONF_SERCOM_1_SPI_BAUD
#define CONF_SERCOM_1_SPI_BAUD 50000
#define CONF_SERCOM_1_SPI_BAUD 8000000
#endif
// </h>
@ -45,7 +67,7 @@
// <e> Advanced Configuration
// <id> spi_master_advanced
#ifndef CONF_SERCOM_1_SPI_ADVANCED
#define CONF_SERCOM_1_SPI_ADVANCED 0
#define CONF_SERCOM_1_SPI_ADVANCED 1
#endif
// <o> Dummy byte <0x00-0x1ff>

131
2_Motor_Master/Motor_Master/Motor_Master/EtherCAT_SlaveDef.h
View File

@ -45,44 +45,51 @@ static volatile int16_t *EMG_CH5 = (((int16_t *)&QSPI_tx_buffer[12]));
static volatile int16_t *EMG_CH6 = (((int16_t *)&QSPI_tx_buffer[12])+1);
static volatile int16_t *EMG_CH7 = (((int16_t *)&QSPI_tx_buffer[13]));
static volatile int16_t *EMG_CH8 = (((int16_t *)&QSPI_tx_buffer[13])+1);
/* Reserved space */
static volatile int16_t *Spare1_tx = (((int16_t *)&QSPI_tx_buffer[14]));
static volatile int16_t *Spare2_tx = (((int16_t *)&QSPI_tx_buffer[14])+1);
static volatile int16_t *Spare3_tx = (((int16_t *)&QSPI_tx_buffer[15]));
static volatile int16_t *Spare4_tx = (((int16_t *)&QSPI_tx_buffer[15])+1);
/* Motor 3*/
static volatile uint8_t *M3_Status = (uint8_t *)&QSPI_tx_buffer[14];
static volatile uint8_t *M3_Mode = (((uint8_t *)&QSPI_tx_buffer[14])+1);
static volatile int16_t *M3_Joint_rel_position = (((int16_t *)&QSPI_tx_buffer[14])+1);
static volatile int16_t *M3_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[15]);
static volatile int16_t *M3_Motor_speed = (((int16_t *)&QSPI_tx_buffer[15])+1);
static volatile int16_t *M3_Motor_current_bus = ((int16_t *)&QSPI_tx_buffer[16]);
static volatile int16_t *M3_Motor_currentPhA = (((int16_t *)&QSPI_tx_buffer[16])+1);
static volatile int16_t *M3_Motor_currentPhB = ((int16_t *)&QSPI_tx_buffer[17]);
static volatile int16_t *M3_Motor_currentPhC = (((int16_t *)&QSPI_tx_buffer[17])+1);
static volatile int16_t *M3_Motor__hallState = ((int16_t *)&QSPI_tx_buffer[18]);
static volatile int16_t *M3_Motor_dutyCycle = (((int16_t *)&QSPI_tx_buffer[18])+1);
static volatile uint8_t *M3_Status = (uint8_t *)&QSPI_tx_buffer[16];
static volatile uint8_t *M3_Mode = (((uint8_t *)&QSPI_tx_buffer[16])+1);
static volatile int16_t *M3_Joint_rel_position = (((int16_t *)&QSPI_tx_buffer[16])+1);
static volatile int16_t *M3_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[17]);
static volatile int16_t *M3_Motor_speed = (((int16_t *)&QSPI_tx_buffer[17])+1);
static volatile int16_t *M3_Motor_current_bus = ((int16_t *)&QSPI_tx_buffer[18]);
static volatile int16_t *M3_Motor_currentPhA = (((int16_t *)&QSPI_tx_buffer[18])+1);
static volatile int16_t *M3_Motor_currentPhB = ((int16_t *)&QSPI_tx_buffer[19]);
static volatile int16_t *M3_Motor_currentPhC = (((int16_t *)&QSPI_tx_buffer[19])+1);
static volatile int16_t *M3_Motor__hallState = ((int16_t *)&QSPI_tx_buffer[20]);
static volatile int16_t *M3_Motor_dutyCycle = (((int16_t *)&QSPI_tx_buffer[20])+1);
/* Motor 4*/
static volatile uint8_t *M4_Status = (uint8_t *)&QSPI_tx_buffer[19];
static volatile uint8_t *M4_Mode = (((uint8_t *)&QSPI_tx_buffer[19])+1);
static volatile int16_t *M4_Joint_rel_position = (((int16_t *)&QSPI_tx_buffer[19])+1);
static volatile int16_t *M4_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[20]);
static volatile int16_t *M4_Motor_speed = (((int16_t *)&QSPI_tx_buffer[20])+1);
static volatile int16_t *M4_Motor_current_bus = ((int16_t *)&QSPI_tx_buffer[21]);
static volatile int16_t *M4_Motor_currentPhA = (((int16_t *)&QSPI_tx_buffer[21])+1);
static volatile int16_t *M4_Motor_currentPhB = ((int16_t *)&QSPI_tx_buffer[22]);
static volatile int16_t *M4_Motor_currentPhC = (((int16_t *)&QSPI_tx_buffer[22])+1);
static volatile int16_t *M4_Motor__hallState = ((int16_t *)&QSPI_tx_buffer[23]);
static volatile int16_t *M4_Motor_dutyCycle = (((int16_t *)&QSPI_tx_buffer[23])+1);
static volatile uint8_t *M4_Status = (uint8_t *)&QSPI_tx_buffer[21];
static volatile uint8_t *M4_Mode = (((uint8_t *)&QSPI_tx_buffer[21])+1);
static volatile int16_t *M4_Joint_rel_position = (((int16_t *)&QSPI_tx_buffer[21])+1);
static volatile int16_t *M4_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[22]);
static volatile int16_t *M4_Motor_speed = (((int16_t *)&QSPI_tx_buffer[22])+1);
static volatile int16_t *M4_Motor_current_bus = ((int16_t *)&QSPI_tx_buffer[23]);
static volatile int16_t *M4_Motor_currentPhA = (((int16_t *)&QSPI_tx_buffer[23])+1);
static volatile int16_t *M4_Motor_currentPhB = ((int16_t *)&QSPI_tx_buffer[24]);
static volatile int16_t *M4_Motor_currentPhC = (((int16_t *)&QSPI_tx_buffer[24])+1);
static volatile int16_t *M4_Motor__hallState = ((int16_t *)&QSPI_tx_buffer[25]);
static volatile int16_t *M4_Motor_dutyCycle = (((int16_t *)&QSPI_tx_buffer[25])+1);
/* IMU */
static volatile int16_t *q_x0 = (((int16_t *)&QSPI_tx_buffer[24]));
static volatile int16_t *q_y0 = (((int16_t *)&QSPI_tx_buffer[24])+1);
static volatile int16_t *q_z0 = (((int16_t *)&QSPI_tx_buffer[25]));
static volatile int16_t *q_w0 = (((int16_t *)&QSPI_tx_buffer[25])+1);
static volatile int16_t *q_x0 = (((int16_t *)&QSPI_tx_buffer[26]));
static volatile int16_t *q_y0 = (((int16_t *)&QSPI_tx_buffer[26])+1);
static volatile int16_t *q_z0 = (((int16_t *)&QSPI_tx_buffer[27]));
static volatile int16_t *q_w0 = (((int16_t *)&QSPI_tx_buffer[27])+1);
/* EMG */
static volatile int16_t *FSR_CH1 = (((int16_t *)&QSPI_tx_buffer[26]));
static volatile int16_t *FSR_CH2 = (((int16_t *)&QSPI_tx_buffer[26])+1);
static volatile int16_t *FSR_CH3 = (((int16_t *)&QSPI_tx_buffer[27]));
static volatile int16_t *FSR_CH4 = (((int16_t *)&QSPI_tx_buffer[27])+1);
static volatile int16_t *FSR_CH5 = (((int16_t *)&QSPI_tx_buffer[28]));
static volatile int16_t *Pressure_CH1 = (((int16_t *)&QSPI_tx_buffer[28])+1);
static volatile int16_t *Pressure_CH2 = (((int16_t *)&QSPI_tx_buffer[29]));
static volatile int16_t *Pressure_CH3 = (((int16_t *)&QSPI_tx_buffer[29])+1);
static volatile int16_t *FSR_CH1 = (((int16_t *)&QSPI_tx_buffer[28]));
static volatile int16_t *FSR_CH2 = (((int16_t *)&QSPI_tx_buffer[28])+1);
static volatile int16_t *FSR_CH3 = (((int16_t *)&QSPI_tx_buffer[29]));
static volatile int16_t *FSR_CH4 = (((int16_t *)&QSPI_tx_buffer[29])+1);
static volatile int16_t *FSR_CH5 = (((int16_t *)&QSPI_tx_buffer[30]));
static volatile int16_t *Pressure_CH1 = (((int16_t *)&QSPI_tx_buffer[30])+1);
static volatile int16_t *Pressure_CH2 = (((int16_t *)&QSPI_tx_buffer[31]));
static volatile int16_t *Pressure_CH3 = (((int16_t *)&QSPI_tx_buffer[31])+1);
//Read From Ecat Total (XX Bytes)
//QSPI_rx_buffer
@ -106,26 +113,46 @@ static volatile int16_t *M2_Max_pos = ((int16_t *)&QSPI_rx_buffer[6]);
static volatile int16_t *M2_Max_velocity = ((int16_t *)&QSPI_rx_buffer[6]+1);
static volatile int16_t *M2_Max_current = ((int16_t *)&QSPI_rx_buffer[7]);
static volatile int16_t *M2_Desired_dc = ((int16_t *)&QSPI_rx_buffer[7]+1); //Spare
/* Reserved space */
/* 64 bytes reserved for each */
static volatile int16_t *Spare1_rx = ((int16_t *)&QSPI_rx_buffer[8]); //Spare
static volatile int16_t *Spare2_rx = ((int16_t *)&QSPI_rx_buffer[8]+1); //Spare
static volatile int16_t *Spare3_rx = ((int16_t *)&QSPI_rx_buffer[9]); //Spare
static volatile int16_t *Spare4_rx = ((int16_t *)&QSPI_rx_buffer[9]+1); //Spare
static volatile int16_t *Spare5_rx = ((int16_t *)&QSPI_rx_buffer[10]); //Spare
static volatile int16_t *Spare6_rx = ((int16_t *)&QSPI_rx_buffer[10]+1); //Spare
static volatile int16_t *Spare7_rx = ((int16_t *)&QSPI_rx_buffer[11]); //Spare
static volatile int16_t *Spare8_rx = ((int16_t *)&QSPI_rx_buffer[11]+1); //Spare
static volatile int16_t *Spare9_rx = ((int16_t *)&QSPI_rx_buffer[12]); //Spare
static volatile int16_t *Spare10_rx = ((int16_t *)&QSPI_rx_buffer[12]+1); //Spare
static volatile int16_t *Spare11_rx = ((int16_t *)&QSPI_rx_buffer[13]); //Spare
static volatile int16_t *Spare12_rx = ((int16_t *)&QSPI_rx_buffer[13]+1); //Spare
static volatile int16_t *Spare13_rx = ((int16_t *)&QSPI_rx_buffer[14]); //Spare
static volatile int16_t *Spare14_rx = ((int16_t *)&QSPI_rx_buffer[14]+1); //Spare
static volatile int16_t *Spare15_rx = ((int16_t *)&QSPI_rx_buffer[15]); //Spare
static volatile int16_t *Spare16_rx = ((int16_t *)&QSPI_rx_buffer[15]+1); //Spare
///* Motor 3*/
static volatile uint8_t *M3_Control_mode = ((uint8_t *)&QSPI_rx_buffer[8]);
static volatile uint8_t *M3_Control_set = (((uint8_t *)&QSPI_rx_buffer[8])+1);
static volatile int16_t *M3_Desired_pos = ((int16_t *)&QSPI_rx_buffer[8]+1);
static volatile int16_t *M3_Desired_speed = ((int16_t *)&QSPI_rx_buffer[9]);
static volatile int16_t *M3_Desired_current = ((int16_t *)&QSPI_rx_buffer[9]+1);
static volatile int16_t *M3_Max_pos = ((int16_t *)&QSPI_rx_buffer[10]);
static volatile int16_t *M3_Max_velocity = ((int16_t *)&QSPI_rx_buffer[10]+1);
static volatile int16_t *M3_Max_current = ((int16_t *)&QSPI_rx_buffer[11]);
static volatile int16_t *M3_Spare = ((int16_t *)&QSPI_rx_buffer[11]+1); //Spare
static volatile uint8_t *M3_Control_mode = ((uint8_t *)&QSPI_rx_buffer[16]);
static volatile uint8_t *M3_Control_set = (((uint8_t *)&QSPI_rx_buffer[16])+1);
static volatile int16_t *M3_Desired_pos = ((int16_t *)&QSPI_rx_buffer[16]+1);
static volatile int16_t *M3_Desired_speed = ((int16_t *)&QSPI_rx_buffer[17]);
static volatile int16_t *M3_Desired_current = ((int16_t *)&QSPI_rx_buffer[17]+1);
static volatile int16_t *M3_Max_pos = ((int16_t *)&QSPI_rx_buffer[18]);
static volatile int16_t *M3_Max_velocity = ((int16_t *)&QSPI_rx_buffer[18]+1);
static volatile int16_t *M3_Max_current = ((int16_t *)&QSPI_rx_buffer[19]);
static volatile int16_t *M3_Spare = ((int16_t *)&QSPI_rx_buffer[19]+1); //Spare
///* Motor 4*/
static volatile uint8_t *M4_Control_mode = ((uint8_t *)&QSPI_rx_buffer[12]);
static volatile uint8_t *M4_Control_set = (((uint8_t *)&QSPI_rx_buffer[12])+1);
static volatile int16_t *M4_Desired_pos = ((int16_t *)&QSPI_rx_buffer[12]+1);
static volatile int16_t *M4_Desired_speed = ((int16_t *)&QSPI_rx_buffer[13]);
static volatile int16_t *M4_Desired_current = ((int16_t *)&QSPI_rx_buffer[13]+1);
static volatile int16_t *M4_Max_pos = ((int16_t *)&QSPI_rx_buffer[14]);
static volatile int16_t *M4_Max_velocity = ((int16_t *)&QSPI_rx_buffer[14]+1);
static volatile int16_t *M4_Max_current = ((int16_t *)&QSPI_rx_buffer[15]);
static volatile int16_t *M4_Spare = ((int16_t *)&QSPI_rx_buffer[15]+1);//Spare
static volatile uint8_t *M4_Control_mode = ((uint8_t *)&QSPI_rx_buffer[20]);
static volatile uint8_t *M4_Control_set = (((uint8_t *)&QSPI_rx_buffer[20])+1);
static volatile int16_t *M4_Desired_pos = ((int16_t *)&QSPI_rx_buffer[20]+1);
static volatile int16_t *M4_Desired_speed = ((int16_t *)&QSPI_rx_buffer[21]);
static volatile int16_t *M4_Desired_current = ((int16_t *)&QSPI_rx_buffer[21]+1);
static volatile int16_t *M4_Max_pos = ((int16_t *)&QSPI_rx_buffer[22]);
static volatile int16_t *M4_Max_velocity = ((int16_t *)&QSPI_rx_buffer[22]+1);
static volatile int16_t *M4_Max_current = ((int16_t *)&QSPI_rx_buffer[23]);
static volatile int16_t *M4_Spare = ((int16_t *)&QSPI_rx_buffer[23]+1); //Spare
static void update_telemetry(void)
{

131
2_Motor_Master/Motor_Master/Motor_Master/Ethercat_SlaveDef.h
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@ -45,44 +45,51 @@ static volatile int16_t *EMG_CH5 = (((int16_t *)&QSPI_tx_buffer[12]));
static volatile int16_t *EMG_CH6 = (((int16_t *)&QSPI_tx_buffer[12])+1);
static volatile int16_t *EMG_CH7 = (((int16_t *)&QSPI_tx_buffer[13]));
static volatile int16_t *EMG_CH8 = (((int16_t *)&QSPI_tx_buffer[13])+1);
/* Reserved space */
static volatile int16_t *Spare1_tx = (((int16_t *)&QSPI_tx_buffer[14]));
static volatile int16_t *Spare2_tx = (((int16_t *)&QSPI_tx_buffer[14])+1);
static volatile int16_t *Spare3_tx = (((int16_t *)&QSPI_tx_buffer[15]));
static volatile int16_t *Spare4_tx = (((int16_t *)&QSPI_tx_buffer[15])+1);
/* Motor 3*/
static volatile uint8_t *M3_Status = (uint8_t *)&QSPI_tx_buffer[14];
static volatile uint8_t *M3_Mode = (((uint8_t *)&QSPI_tx_buffer[14])+1);
static volatile int16_t *M3_Joint_rel_position = (((int16_t *)&QSPI_tx_buffer[14])+1);
static volatile int16_t *M3_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[15]);
static volatile int16_t *M3_Motor_speed = (((int16_t *)&QSPI_tx_buffer[15])+1);
static volatile int16_t *M3_Motor_current_bus = ((int16_t *)&QSPI_tx_buffer[16]);
static volatile int16_t *M3_Motor_currentPhA = (((int16_t *)&QSPI_tx_buffer[16])+1);
static volatile int16_t *M3_Motor_currentPhB = ((int16_t *)&QSPI_tx_buffer[17]);
static volatile int16_t *M3_Motor_currentPhC = (((int16_t *)&QSPI_tx_buffer[17])+1);
static volatile int16_t *M3_Motor__hallState = ((int16_t *)&QSPI_tx_buffer[18]);
static volatile int16_t *M3_Motor_dutyCycle = (((int16_t *)&QSPI_tx_buffer[18])+1);
static volatile uint8_t *M3_Status = (uint8_t *)&QSPI_tx_buffer[16];
static volatile uint8_t *M3_Mode = (((uint8_t *)&QSPI_tx_buffer[16])+1);
static volatile int16_t *M3_Joint_rel_position = (((int16_t *)&QSPI_tx_buffer[16])+1);
static volatile int16_t *M3_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[17]);
static volatile int16_t *M3_Motor_speed = (((int16_t *)&QSPI_tx_buffer[17])+1);
static volatile int16_t *M3_Motor_current_bus = ((int16_t *)&QSPI_tx_buffer[18]);
static volatile int16_t *M3_Motor_currentPhA = (((int16_t *)&QSPI_tx_buffer[18])+1);
static volatile int16_t *M3_Motor_currentPhB = ((int16_t *)&QSPI_tx_buffer[19]);
static volatile int16_t *M3_Motor_currentPhC = (((int16_t *)&QSPI_tx_buffer[19])+1);
static volatile int16_t *M3_Motor__hallState = ((int16_t *)&QSPI_tx_buffer[20]);
static volatile int16_t *M3_Motor_dutyCycle = (((int16_t *)&QSPI_tx_buffer[20])+1);
/* Motor 4*/
static volatile uint8_t *M4_Status = (uint8_t *)&QSPI_tx_buffer[19];
static volatile uint8_t *M4_Mode = (((uint8_t *)&QSPI_tx_buffer[19])+1);
static volatile int16_t *M4_Joint_rel_position = (((int16_t *)&QSPI_tx_buffer[19])+1);
static volatile int16_t *M4_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[20]);
static volatile int16_t *M4_Motor_speed = (((int16_t *)&QSPI_tx_buffer[20])+1);
static volatile int16_t *M4_Motor_current_bus = ((int16_t *)&QSPI_tx_buffer[21]);
static volatile int16_t *M4_Motor_currentPhA = (((int16_t *)&QSPI_tx_buffer[21])+1);
static volatile int16_t *M4_Motor_currentPhB = ((int16_t *)&QSPI_tx_buffer[22]);
static volatile int16_t *M4_Motor_currentPhC = (((int16_t *)&QSPI_tx_buffer[22])+1);
static volatile int16_t *M4_Motor__hallState = ((int16_t *)&QSPI_tx_buffer[23]);
static volatile int16_t *M4_Motor_dutyCycle = (((int16_t *)&QSPI_tx_buffer[23])+1);
static volatile uint8_t *M4_Status = (uint8_t *)&QSPI_tx_buffer[21];
static volatile uint8_t *M4_Mode = (((uint8_t *)&QSPI_tx_buffer[21])+1);
static volatile int16_t *M4_Joint_rel_position = (((int16_t *)&QSPI_tx_buffer[21])+1);
static volatile int16_t *M4_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[22]);
static volatile int16_t *M4_Motor_speed = (((int16_t *)&QSPI_tx_buffer[22])+1);
static volatile int16_t *M4_Motor_current_bus = ((int16_t *)&QSPI_tx_buffer[23]);
static volatile int16_t *M4_Motor_currentPhA = (((int16_t *)&QSPI_tx_buffer[23])+1);
static volatile int16_t *M4_Motor_currentPhB = ((int16_t *)&QSPI_tx_buffer[24]);
static volatile int16_t *M4_Motor_currentPhC = (((int16_t *)&QSPI_tx_buffer[24])+1);
static volatile int16_t *M4_Motor__hallState = ((int16_t *)&QSPI_tx_buffer[25]);
static volatile int16_t *M4_Motor_dutyCycle = (((int16_t *)&QSPI_tx_buffer[25])+1);
/* IMU */
static volatile int16_t *q_x0 = (((int16_t *)&QSPI_tx_buffer[24]));
static volatile int16_t *q_y0 = (((int16_t *)&QSPI_tx_buffer[24])+1);
static volatile int16_t *q_z0 = (((int16_t *)&QSPI_tx_buffer[25]));
static volatile int16_t *q_w0 = (((int16_t *)&QSPI_tx_buffer[25])+1);
static volatile int16_t *q_x0 = (((int16_t *)&QSPI_tx_buffer[26]));
static volatile int16_t *q_y0 = (((int16_t *)&QSPI_tx_buffer[26])+1);
static volatile int16_t *q_z0 = (((int16_t *)&QSPI_tx_buffer[27]));
static volatile int16_t *q_w0 = (((int16_t *)&QSPI_tx_buffer[27])+1);
/* EMG */
static volatile int16_t *FSR_CH1 = (((int16_t *)&QSPI_tx_buffer[26]));
static volatile int16_t *FSR_CH2 = (((int16_t *)&QSPI_tx_buffer[26])+1);
static volatile int16_t *FSR_CH3 = (((int16_t *)&QSPI_tx_buffer[27]));
static volatile int16_t *FSR_CH4 = (((int16_t *)&QSPI_tx_buffer[27])+1);
static volatile int16_t *FSR_CH5 = (((int16_t *)&QSPI_tx_buffer[28]));
static volatile int16_t *Pressure_CH1 = (((int16_t *)&QSPI_tx_buffer[28])+1);
static volatile int16_t *Pressure_CH2 = (((int16_t *)&QSPI_tx_buffer[29]));
static volatile int16_t *Pressure_CH3 = (((int16_t *)&QSPI_tx_buffer[29])+1);
static volatile int16_t *FSR_CH1 = (((int16_t *)&QSPI_tx_buffer[28]));
static volatile int16_t *FSR_CH2 = (((int16_t *)&QSPI_tx_buffer[28])+1);
static volatile int16_t *FSR_CH3 = (((int16_t *)&QSPI_tx_buffer[29]));
static volatile int16_t *FSR_CH4 = (((int16_t *)&QSPI_tx_buffer[29])+1);
static volatile int16_t *FSR_CH5 = (((int16_t *)&QSPI_tx_buffer[30]));
static volatile int16_t *Pressure_CH1 = (((int16_t *)&QSPI_tx_buffer[30])+1);
static volatile int16_t *Pressure_CH2 = (((int16_t *)&QSPI_tx_buffer[31]));
static volatile int16_t *Pressure_CH3 = (((int16_t *)&QSPI_tx_buffer[31])+1);
//Read From Ecat Total (XX Bytes)
//QSPI_rx_buffer
@ -106,26 +113,46 @@ static volatile int16_t *M2_Max_pos = ((int16_t *)&QSPI_rx_buffer[6]);
static volatile int16_t *M2_Max_velocity = ((int16_t *)&QSPI_rx_buffer[6]+1);
static volatile int16_t *M2_Max_current = ((int16_t *)&QSPI_rx_buffer[7]);
static volatile int16_t *M2_Desired_dc = ((int16_t *)&QSPI_rx_buffer[7]+1); //Spare
/* Reserved space */
/* 64 bytes reserved for each */
static volatile int16_t *Spare1_rx = ((int16_t *)&QSPI_rx_buffer[8]); //Spare
static volatile int16_t *Spare2_rx = ((int16_t *)&QSPI_rx_buffer[8]+1); //Spare
static volatile int16_t *Spare3_rx = ((int16_t *)&QSPI_rx_buffer[9]); //Spare
static volatile int16_t *Spare4_rx = ((int16_t *)&QSPI_rx_buffer[9]+1); //Spare
static volatile int16_t *Spare5_rx = ((int16_t *)&QSPI_rx_buffer[10]); //Spare
static volatile int16_t *Spare6_rx = ((int16_t *)&QSPI_rx_buffer[10]+1); //Spare
static volatile int16_t *Spare7_rx = ((int16_t *)&QSPI_rx_buffer[11]); //Spare
static volatile int16_t *Spare8_rx = ((int16_t *)&QSPI_rx_buffer[11]+1); //Spare
static volatile int16_t *Spare9_rx = ((int16_t *)&QSPI_rx_buffer[12]); //Spare
static volatile int16_t *Spare10_rx = ((int16_t *)&QSPI_rx_buffer[12]+1); //Spare
static volatile int16_t *Spare11_rx = ((int16_t *)&QSPI_rx_buffer[13]); //Spare
static volatile int16_t *Spare12_rx = ((int16_t *)&QSPI_rx_buffer[13]+1); //Spare
static volatile int16_t *Spare13_rx = ((int16_t *)&QSPI_rx_buffer[14]); //Spare
static volatile int16_t *Spare14_rx = ((int16_t *)&QSPI_rx_buffer[14]+1); //Spare
static volatile int16_t *Spare15_rx = ((int16_t *)&QSPI_rx_buffer[15]); //Spare
static volatile int16_t *Spare16_rx = ((int16_t *)&QSPI_rx_buffer[15]+1); //Spare
///* Motor 3*/
static volatile uint8_t *M3_Control_mode = ((uint8_t *)&QSPI_rx_buffer[8]);
static volatile uint8_t *M3_Control_set = (((uint8_t *)&QSPI_rx_buffer[8])+1);
static volatile int16_t *M3_Desired_pos = ((int16_t *)&QSPI_rx_buffer[8]+1);
static volatile int16_t *M3_Desired_speed = ((int16_t *)&QSPI_rx_buffer[9]);
static volatile int16_t *M3_Desired_current = ((int16_t *)&QSPI_rx_buffer[9]+1);
static volatile int16_t *M3_Max_pos = ((int16_t *)&QSPI_rx_buffer[10]);
static volatile int16_t *M3_Max_velocity = ((int16_t *)&QSPI_rx_buffer[10]+1);
static volatile int16_t *M3_Max_current = ((int16_t *)&QSPI_rx_buffer[11]);
static volatile int16_t *M3_Spare = ((int16_t *)&QSPI_rx_buffer[11]+1); //Spare
static volatile uint8_t *M3_Control_mode = ((uint8_t *)&QSPI_rx_buffer[16]);
static volatile uint8_t *M3_Control_set = (((uint8_t *)&QSPI_rx_buffer[16])+1);
static volatile int16_t *M3_Desired_pos = ((int16_t *)&QSPI_rx_buffer[16]+1);
static volatile int16_t *M3_Desired_speed = ((int16_t *)&QSPI_rx_buffer[17]);
static volatile int16_t *M3_Desired_current = ((int16_t *)&QSPI_rx_buffer[17]+1);
static volatile int16_t *M3_Max_pos = ((int16_t *)&QSPI_rx_buffer[18]);
static volatile int16_t *M3_Max_velocity = ((int16_t *)&QSPI_rx_buffer[18]+1);
static volatile int16_t *M3_Max_current = ((int16_t *)&QSPI_rx_buffer[19]);
static volatile int16_t *M3_Spare = ((int16_t *)&QSPI_rx_buffer[19]+1); //Spare
///* Motor 4*/
static volatile uint8_t *M4_Control_mode = ((uint8_t *)&QSPI_rx_buffer[12]);
static volatile uint8_t *M4_Control_set = (((uint8_t *)&QSPI_rx_buffer[12])+1);
static volatile int16_t *M4_Desired_pos = ((int16_t *)&QSPI_rx_buffer[12]+1);
static volatile int16_t *M4_Desired_speed = ((int16_t *)&QSPI_rx_buffer[13]);
static volatile int16_t *M4_Desired_current = ((int16_t *)&QSPI_rx_buffer[13]+1);
static volatile int16_t *M4_Max_pos = ((int16_t *)&QSPI_rx_buffer[14]);
static volatile int16_t *M4_Max_velocity = ((int16_t *)&QSPI_rx_buffer[14]+1);
static volatile int16_t *M4_Max_current = ((int16_t *)&QSPI_rx_buffer[15]);
static volatile int16_t *M4_Spare = ((int16_t *)&QSPI_rx_buffer[15]+1);//Spare
static volatile uint8_t *M4_Control_mode = ((uint8_t *)&QSPI_rx_buffer[20]);
static volatile uint8_t *M4_Control_set = (((uint8_t *)&QSPI_rx_buffer[20])+1);
static volatile int16_t *M4_Desired_pos = ((int16_t *)&QSPI_rx_buffer[20]+1);
static volatile int16_t *M4_Desired_speed = ((int16_t *)&QSPI_rx_buffer[21]);
static volatile int16_t *M4_Desired_current = ((int16_t *)&QSPI_rx_buffer[21]+1);
static volatile int16_t *M4_Max_pos = ((int16_t *)&QSPI_rx_buffer[22]);
static volatile int16_t *M4_Max_velocity = ((int16_t *)&QSPI_rx_buffer[22]+1);
static volatile int16_t *M4_Max_current = ((int16_t *)&QSPI_rx_buffer[23]);
static volatile int16_t *M4_Spare = ((int16_t *)&QSPI_rx_buffer[23]+1); //Spare
static void update_telemetry(void)
{

215
2_Motor_Master/Motor_Master/Motor_Master/MSIF_master.h Normal file
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@ -0,0 +1,215 @@
/*
* master_slave_IF.h
*
* Created: 8/18/2021 4:32:19 PM
* Author: ge37vez
*/
#ifndef MASTER_SLAVE_IF_H_
#define MASTER_SLAVE_IF_H_
#define MASTER_BUFFER_SIZE 64
static uint8_t SPI_rx_buffer[MASTER_BUFFER_SIZE] = {0};
static uint8_t SPI_tx_buffer[MASTER_BUFFER_SIZE] = {0};
//static uint8_t SPI_rx_buffer[SLAVE_BUFFER_SIZE] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,
//18,19,20,21,22,23,24,25,26,27,28,29,30,31};
//tx_buffer
/* Motor 3*/
static volatile uint8_t *M3_Status = (uint8_t *)&SPI_rx_buffer[0]; //1 byte - 0 of 64
static volatile uint8_t *M3_Mode = (uint8_t *)&SPI_rx_buffer[1]; //1 byte - 1 of 64
static volatile int16_t *M3_Joint_rel_position = (int16_t *)&SPI_rx_buffer[2]; //2 byte - 2 of 64
static volatile int16_t *M3_Joint_abs_position = (int16_t *)&SPI_rx_buffer[4]; //2 byte - 4 of 64
static volatile int16_t *M3_Motor_speed = (int16_t *)&SPI_rx_buffer[6]; //2 byte - 6 of 64
static volatile int16_t *M3_Motor_current_bus = (int16_t *)&SPI_rx_buffer[8]; //2 byte - 8 of 64
static volatile int16_t *M3_Motor_currentPhA = (int16_t *)&SPI_rx_buffer[10]; //2 byte - 10 of 64
static volatile int16_t *M3_Motor_currentPhB = (int16_t *)&SPI_rx_buffer[12]; //2 byte - 12 of 64
static volatile int16_t *M3_Motor_currentPhC = (int16_t *)&SPI_rx_buffer[14]; //2 byte - 14 of 64
static volatile int16_t *M3_Motor__hallState = (int16_t *)&SPI_rx_buffer[16]; //2 byte - 16 of 64
static volatile int16_t *M3_Motor_dutyCycle = (int16_t *)&SPI_rx_buffer[18]; //2 byte - 18 of 64
/* Motor 4*/
static volatile uint8_t *M4_Status = (uint8_t *)&SPI_rx_buffer[20]; //1 byte - 20 of 64
static volatile uint8_t *M4_Mode = (uint8_t *)&SPI_rx_buffer[21]; //1 byte - 21 of 64
static volatile int16_t *M4_Joint_rel_position = (int16_t *)&SPI_rx_buffer[22]; //2 byte - 22 of 64
static volatile int16_t *M4_Joint_abs_position = (int16_t *)&SPI_rx_buffer[24]; //2 byte - 24 of 64
static volatile int16_t *M4_Motor_speed = (int16_t *)&SPI_rx_buffer[26]; //2 byte - 26 of 64
static volatile int16_t *M4_Motor_current_bus = (int16_t *)&SPI_rx_buffer[28]; //2 byte - 28 of 64
static volatile int16_t *M4_Motor_currentPhA = (int16_t *)&SPI_rx_buffer[30]; //2 byte - 30 of 64
static volatile int16_t *M4_Motor_currentPhB = (int16_t *)&SPI_rx_buffer[32]; //2 byte - 32 of 64
static volatile int16_t *M4_Motor_currentPhC = (int16_t *)&SPI_rx_buffer[34]; //2 byte - 34 of 64
static volatile int16_t *M4_Motor__hallState = (int16_t *)&SPI_rx_buffer[36]; //2 byte - 36 of 64
static volatile int16_t *M4_Motor_dutyCycle = (int16_t *)&SPI_rx_buffer[38]; //2 byte - 38 of 64
/* IMU */
static volatile int16_t *q_x0 = (int16_t *)&SPI_rx_buffer[40]; //2 byte - 40 of 64
static volatile int16_t *q_y0 = (int16_t *)&SPI_rx_buffer[42]; //2 byte - 42 of 64
static volatile int16_t *q_z0 = (int16_t *)&SPI_rx_buffer[44]; //2 byte - 44 of 64
static volatile int16_t *q_w0 = (int16_t *)&SPI_rx_buffer[46]; //2 byte - 46 of 64
/* EMG */
static volatile int16_t *FSR_CH1 = (int16_t *)&SPI_rx_buffer[48]; //2 byte - 48 of 64
static volatile int16_t *FSR_CH2 = (int16_t *)&SPI_rx_buffer[50]; //2 byte - 50 of 64
static volatile int16_t *FSR_CH3 = (int16_t *)&SPI_rx_buffer[52]; //2 byte - 52 of 64
static volatile int16_t *FSR_CH4 = (int16_t *)&SPI_rx_buffer[54]; //2 byte - 54 of 64
static volatile int16_t *FSR_CH5 = (int16_t *)&SPI_rx_buffer[56]; //2 byte - 56 of 64
static volatile int16_t *Pressure_CH1 = (int16_t *)&SPI_rx_buffer[58]; //2 byte - 58 of 64
static volatile int16_t *Pressure_CH2 = (int16_t *)&SPI_rx_buffer[60]; //2 byte - 60 of 64
static volatile int16_t *Pressure_CH3 = (int16_t *)&SPI_rx_buffer[62]; //2 byte - 62 of 64
//tx_buffer
///* Motor 3*/
static volatile uint8_t *M3_Control_mode = (uint8_t *)&SPI_tx_buffer[0]; //1 byte - 0 of 32
static volatile uint8_t *M3_Control_set = (uint8_t *)&SPI_tx_buffer[1]; //1 byte - 1 of 32
static volatile int16_t *M3_Desired_pos = (int16_t *)&SPI_tx_buffer[2]; //2 byte - 2 of 32
static volatile int16_t *M3_Desired_speed = (int16_t *)&SPI_tx_buffer[4]; //2 byte - 4 of 32
static volatile int16_t *M3_Desired_current = (int16_t *)&SPI_tx_buffer[6]; //2 byte - 6 of 32
static volatile int16_t *M3_Max_pos = (int16_t *)&SPI_tx_buffer[8]; //2 byte - 8 of 32
static volatile int16_t *M3_Max_velocity = (int16_t *)&SPI_tx_buffer[10]; //2 byte - 10 of 32
static volatile int16_t *M3_Max_current = (int16_t *)&SPI_tx_buffer[12]; //2 byte - 12 of 32
static volatile int16_t *M3_Spare = (int16_t *)&SPI_tx_buffer[14]; //2 byte - 14 of 32
///* Motor 4*/
static volatile uint8_t *M4_Control_mode = (int16_t *)&SPI_tx_buffer[16]; //1 byte - 16 of 32
static volatile uint8_t *M4_Control_set = (int16_t *)&SPI_tx_buffer[17]; //1 byte - 17 of 32
static volatile int16_t *M4_Desired_pos = (int16_t *)&SPI_tx_buffer[18]; //2 byte - 18 of 32
static volatile int16_t *M4_Desired_speed = (int16_t *)&SPI_tx_buffer[20]; //2 byte - 20 of 32
static volatile int16_t *M4_Desired_current = (int16_t *)&SPI_tx_buffer[22]; //2 byte - 22 of 32
static volatile int16_t *M4_Max_pos = (int16_t *)&SPI_tx_buffer[24]; //2 byte - 24 of 32
static volatile int16_t *M4_Max_velocity = (int16_t *)&SPI_tx_buffer[26]; //2 byte - 26 of 32
static volatile int16_t *M4_Max_current = (int16_t *)&SPI_tx_buffer[28]; //2 byte - 28 of 32
static volatile int16_t *M4_Spare = (int16_t *)&SPI_tx_buffer[30]; //2 byte - 30 of 32
static void update_telemetry(void)
{
inline int16_t convert_to_mA(volatile float32_t current_PU)
{
return (int16_t)(current_PU*1000.0f);
}
//
//*M3_Status = 0;
//*M3_Mode = 0;
/* Motor 1 */
*M3_Status = Motor1.motor_state.currentstate;
*M3_Joint_rel_position = Motor1.motor_status.Num_Steps;
//*M3_Joint_abs_position = ((int16_t *)&QSPI_rx_buffer[1];
//*M3_Motor_speed = (((int16_t *)&QSPI_rx_buffer[1]+1);
*M3_Motor_current_bus = convert_to_mA(Motor1.Iphase_pu.Bus);
*M3_Motor_currentPhA = convert_to_mA(Motor1.Iphase_pu.A);
*M3_Motor_currentPhB = convert_to_mA(Motor1.Iphase_pu.B);
*M3_Motor_currentPhC = convert_to_mA(Motor1.Iphase_pu.C);
*M3_Motor__hallState = Motor1.motor_status.currentHallPattern;
*M3_Motor_dutyCycle = Motor1.motor_status.duty_cycle;
*M3_Motor_speed = (int16_t)Motor1.motor_status.calc_rpm;
*M3_Joint_abs_position = Motor1.motor_status.actualDirection;
/* Motor 2 */
*M4_Status = Motor2.motor_state.currentstate;
*M4_Joint_rel_position = Motor2.motor_status.Num_Steps;
//*M3_Joint_abs_position = ((int16_t *)&QSPI_rx_buffer[1];
//*M3_Motor_speed = (((int16_t *)&QSPI_rx_buffer[1]+1);
*M4_Motor_current_bus = convert_to_mA( Motor2.Iphase_pu.Bus);
*M4_Motor_currentPhA = convert_to_mA( Motor2.Iphase_pu.A);
*M4_Motor_currentPhB = convert_to_mA( Motor2.Iphase_pu.B);
*M4_Motor_currentPhC = convert_to_mA(Motor2.Iphase_pu.C);
*M4_Motor__hallState = Motor2.motor_status.currentHallPattern;
*M4_Motor_dutyCycle = Motor2.motor_status.duty_cycle;
*M4_Motor_speed = (int16_t)Motor2.motor_status.calc_rpm;
*M4_Joint_abs_position = Motor2.motor_status.actualDirection;
}
static void update_setpoints(void)
{
Motor1.motor_setpoints.desired_position = *M3_Desired_pos;
Motor1.motor_setpoints.desired_speed = *M3_Desired_speed;
Motor1.motor_setpoints.desired_torque = *M3_Desired_current;
Motor1.motor_setpoints.max_current = *M3_Max_current;
Motor1.motor_setpoints.max_torque = *M3_Max_current;
Motor1.motor_setpoints.max_velocity = *M3_Max_velocity;
Motor2.motor_setpoints.desired_position = *M4_Desired_pos;
Motor2.motor_setpoints.desired_speed = *M4_Desired_speed;
Motor2.motor_setpoints.desired_torque = *M4_Desired_current;
Motor2.motor_setpoints.max_current = *M4_Max_current;
Motor2.motor_setpoints.max_torque = *M4_Max_current;
Motor2.motor_setpoints.max_velocity = *M4_Max_velocity;
//volatile uint8_t a = *M3_Control_mode;
//volatile uint8_t b = *M3_Control_set;
//volatile int16_t c = *M3_Desired_pos;
//volatile int16_t d = *M3_Desired_speed;
//volatile int16_t e = *M3_Desired_current;
//volatile int16_t f = *M3_Max_pos;
//volatile int16_t g = *M3_Max_velocity;
//volatile int16_t h = *M3_Max_current;
//volatile int16_t i = *M3_Spare;
//inline float32_t convert_int_to_PU(volatile int16_t input)
//{
//return ((float32_t)(input/1000.0f));
//}
////Motor1.des_mode = 0;
////Motor1.set = 0;
//Motor1.motor_setpoints.desired_position = *desired_position;
//Motor1.motor_setpoints.desired_speed = *desired_speed;
////Motor1.desired_speed = 1500;
//Motor1.motor_setpoints.desired_torque = convert_int_to_PU(*desired_torque);
////Motor1.controllerParam.I_kp = 0;
////Motor1.controllerParam.I_ki = 0;
////Motor1.controllerParam.V_kp = 0;
////Motor1.controllerParam.V_kd = 0;
////Motor1.controllerParam.V_kd = 0;
////Motor1.controllerParam.P_kp = 0;
////Motor1.controllerParam.P_ki = 0;
////Motor1.reductionRatio = 0;
//Motor1.motor_setpoints.max_velocity = *max_velocity;
//Motor1.motor_setpoints.max_current = convert_int_to_PU(*max_current);
//Motor1.motor_setpoints.max_torque = convert_int_to_PU(*max_torque);
////Motor1.Spare1 = 0;
////Motor1.Spare2 = 0;
////Motor1.Spare3 = 0;
////Motor1.Spare4 = 0;
}
static inline void comms_check(void)
{
/* Motor 1*/
*M3_Status = 1;
*M3_Mode = 2;
*M3_Joint_rel_position = -3;
*M3_Joint_abs_position = 4;
*M3_Motor_speed = -5;
*M3_Motor_current_bus = 6;
*M3_Motor_currentPhA = -7;
*M3_Motor_currentPhB = 8;
*M3_Motor_currentPhC = -9;
*M3_Motor__hallState = 10;
*M3_Motor_dutyCycle = -11;
/* Motor 2*/
*M4_Status = 12;
*M4_Mode = 13;
*M4_Joint_rel_position = 14;
*M4_Joint_abs_position = -15;
*M4_Motor_speed = 16;
*M4_Motor_current_bus = -17;
*M4_Motor_currentPhA = 18;
*M4_Motor_currentPhB = -19;
*M4_Motor_currentPhC = 20;
*M4_Motor__hallState = -21;
*M4_Motor_dutyCycle = 22;
/* IMU */
*q_x0 = 23;
*q_y0 = -24;
*q_z0 = 25;
*q_w0 = -26;
/* EMG */
*FSR_CH1 = 27;
*FSR_CH2 = -28;
*FSR_CH3 = 29;
*FSR_CH4 = -30;
*FSR_CH5 = 31;
*Pressure_CH1 = -32;
*Pressure_CH2 = 33;
*Pressure_CH3 = -34;
}
#endif /* MASTER_SLAVE_IF_H_ */

25
2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj
View File

@ -63,6 +63,7 @@
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_qspi_dma.h" IsConfig="false" Hash="Z34LPTgquoHUOOWcEGA5XA" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_sleep.h" IsConfig="false" Hash="KuZDwgrLdU+fuMG82ZFTqg" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_spi_m_async.h" IsConfig="false" Hash="kNWiys4SwzwGn2qCqzFQlA" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_spi_m_dma.h" IsConfig="false" Hash="MRP9iaBaY97VrZIf+yI+nQ" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_spi_m_sync.h" IsConfig="false" Hash="2oma6hRMCcowUy2wVveqMg" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_adc_dma.h" IsConfig="false" Hash="ZNWJ5APLfPqPLqI7LDqlMA" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_cmcc.h" IsConfig="false" Hash="mDAHEzTxsniAe2HtqO43oA" />
@ -150,11 +151,11 @@
<AcmeProjectActionInfo Action="File" Source="hri/hri_usb_e51.h" IsConfig="false" Hash="x6M7vYgNCS2oECqykr5+yw" />
<AcmeProjectActionInfo Action="File" Source="hri/hri_wdt_e51.h" IsConfig="false" Hash="o9Rg/hyuMzwOCphVc7uG1w" />
<AcmeProjectActionInfo Action="File" Source="main.c" IsConfig="false" Hash="k0AH7j+BrmdFhBPzCCMptA" />
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="Yq1q1Sa7cd5/H8qv36yeFQ" />
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<AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="9Vb0j3AjI95MGRCecrCnLQ" />
<AcmeProjectActionInfo Action="File" Source="atmel_start_pins.h" IsConfig="false" Hash="ByCGTBpkOpAk+zk9txhJSA" />
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="kvd7eb1e9guBnXkzUfLueg" />
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.c" IsConfig="false" Hash="/OR9xzATKmeDfzhivaESBw" />
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="gLjWgjni3Z8tNpbOMxpapQ" />
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.c" IsConfig="false" Hash="M3T31wmDXMA5AqAp9Pm+7A" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_adc_sync.h" IsConfig="false" Hash="ez1X5T9kpYwT+1+5x4Pxqg" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_pwm.h" IsConfig="false" Hash="RXcBZcci/7vXKRJKNIq/Kw" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_timer.h" IsConfig="false" Hash="5pZVthtMl40VMvofOld2ng" />
@ -175,6 +176,7 @@
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_ext_irq.c" IsConfig="false" Hash="l6Jmb4zu10+HvXQ0Iej4dQ" />
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_pwm.c" IsConfig="false" Hash="ZFJmg7/0rhQ6JMKyxuk9kw" />
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_spi_m_async.c" IsConfig="false" Hash="hErEkp5CHigcW3olA6Csrg" />
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_spi_m_dma.c" IsConfig="false" Hash="KMrinO/3xx7qWxy2PsJB7g" />
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_spi_m_sync.c" IsConfig="false" Hash="Q0IudnTEWeoIkfQIoYIqxA" />
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_timer.c" IsConfig="false" Hash="F2MrEXhHq4umI9xpONnlGg" />
<AcmeProjectActionInfo Action="File" Source="hal/utils/include/parts.h" IsConfig="false" Hash="zv0TWdxXtsu5Y1B88PQgiA" />
@ -198,7 +200,7 @@
<AcmeProjectActionInfo Action="File" Source="hpl/port/hpl_gpio_base.h" IsConfig="false" Hash="YjSLMahiT5jdYvqMYVQ8zg" />
<AcmeProjectActionInfo Action="File" Source="hpl/qspi/hpl_qspi.c" IsConfig="false" Hash="woXbbCFkSWus6J14PHJlHw" />
<AcmeProjectActionInfo Action="File" Source="hpl/ramecc/hpl_ramecc.c" IsConfig="false" Hash="pMdmwVWBg16VG8HOwA3DPw" />
<AcmeProjectActionInfo Action="File" Source="hpl/sercom/hpl_sercom.c" IsConfig="false" Hash="MLflsL/S4ZuAfydm9ax0cA" />
<AcmeProjectActionInfo Action="File" Source="hpl/sercom/hpl_sercom.c" IsConfig="false" Hash="z3dKgPu8whuFF0HDwi0isw" />
<AcmeProjectActionInfo Action="File" Source="hpl/tc/hpl_tc.c" IsConfig="false" Hash="CwAdaARrfhpCcFm3bk4PtA" />
<AcmeProjectActionInfo Action="File" Source="hpl/tc/hpl_tc_base.h" IsConfig="false" Hash="gjj5IyaZPy6sUReifzS1GQ" />
<AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.c" IsConfig="false" Hash="035J+hUWZyoUFfzslZgZwg" />
@ -210,7 +212,7 @@
<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="XAOTvk5xMalucgzL/ILTWw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="xCXhbdBwXKUe304TPFonTw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="JdAljBjm3ndwImqgZ6Oc5w" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="xKw8xm4k4XPALg++/jSPcw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="/3bNiu/UgpvPbmvfRA+w3g" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
@ -219,7 +221,7 @@
<AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Uje5LXAS+nQpGryt9t0fYA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="rMTNR+5FXtu+wfT1NbfRRA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_qspi_config.h" IsConfig="true" Hash="CwZ360eeEYs7T9SYFSvDug" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="Es2tGk0V59kfHKXDA1geTw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="x9H2b9FAETnTpR8cbaWLOg" />
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<AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" />
<AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="rqTY1slZEq9V5moV+8Q+hw" />
@ -648,6 +650,9 @@
<Compile Include="hal\include\hal_spi_m_async.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hal_spi_m_dma.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hal_spi_m_sync.h">
<SubType>compile</SubType>
</Compile>
@ -807,6 +812,9 @@
<Compile Include="hal\src\hal_spi_m_async.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_spi_m_dma.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_spi_m_sync.c">
<SubType>compile</SubType>
</Compile>
@ -1127,6 +1135,9 @@
<None Include="hal\documentation\spi_master_async.rst">
<SubType>compile</SubType>
</None>
<None Include="hal\documentation\spi_master_dma.rst">
<SubType>compile</SubType>
</None>
<None Include="hal\documentation\spi_master_sync.rst">
<SubType>compile</SubType>
</None>

4
2_Motor_Master/Motor_Master/Motor_Master/bldc.c
View File

@ -35,11 +35,11 @@ void motor_StateMachine(BLDCMotor_t* const motor)
case MOTOR_IDLE:
//hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw, DISABLE_PATTERN);
motor->motor_state.previousstate = motor->motor_state.currentstate;
motor->motor_state.currentstate = MOTOR_PVI_CTRL_STATE;
motor->motor_state.currentstate = MOTOR_IDLE;
break;
case MOTOR_OPEN_LOOP_STATE:
BLDC_runOpenLoop(motor, *M1_Desired_dc);
calculate_motor_speed(motor);
//calculate_motor_speed(motor);
motor->motor_state.previousstate = motor->motor_state.currentstate;
break;
case MOTOR_V_CTRL_STATE:

26
2_Motor_Master/Motor_Master/Motor_Master/configuration.h
View File

@ -16,13 +16,15 @@
#include "bldc.h"
#include "interrupts.h"
// ----------------------------------------------------------------------
// ADC DMA Initialization
// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
// ----------------------------------------------------------------------
#define DMAC_CHANNEL_ADC_SEQ 2U
#define DMAC_CHANNEL_ADC_SRAM 3U
// ----------------------------------------------------------------------
// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
// ----------------------------------------------------------------------
/* Single Ended */
//const uint32_t adc_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808};
/* Differential */
@ -32,6 +34,9 @@ volatile int16_t adc_res[4] = {0};
struct _dma_resource *adc_sram_dma_resource;
struct _dma_resource *adc_dmac_sequence_resource;
// ----------------------------------------------------------------------
// PWM Timer Initialization
// ----------------------------------------------------------------------
inline static void configure_tcc_pwm(void)
{
//gpio_set_pin_pull_mode(M1_HALLA, GPIO_PULL_UP);
@ -138,6 +143,19 @@ inline void adc_sram_dmac_init()
_dma_enable_transaction(DMAC_CHANNEL_ADC_SRAM, false);
}
// ----------------------------------------------------------------------
// Init SPI DMA communication between Master & Slave Board
// ----------------------------------------------------------------------
void boardToBoardTransferInit(void)
{
struct io_descriptor *io;
spi_m_dma_get_io_descriptor(&SPI_1_MSIF, &io);
spi_m_dma_register_callback(&SPI_1_MSIF, SPI_M_DMA_CB_RX_DONE, b2bTransferComplete_cb);
//SERCOM4->SPI.CTRLC.bit.DATA32B = true;
gpio_set_pin_level(SPI1_CS, true);
spi_m_dma_enable(&SPI_1_MSIF);
}
#endif /* CONFIGURATION_H_ */

27
2_Motor_Master/Motor_Master/Motor_Master/driver_init.c
View File

@ -14,7 +14,6 @@
#include <hpl_adc_base.h>
#include <hpl_adc_base.h>
struct spi_m_sync_descriptor SPI_1;
struct spi_m_sync_descriptor SPI_3;
struct timer_descriptor TIMER_0;
@ -24,6 +23,8 @@ struct adc_sync_descriptor ADC_1;
struct qspi_dma_descriptor ECAT_QSPI;
struct spi_m_dma_descriptor SPI_1_MSIF;
struct spi_m_async_descriptor SPI_2;
struct pwm_descriptor PWM_0;
@ -410,7 +411,7 @@ void ECAT_QSPI_init(void)
ECAT_QSPI_PORT_init();
}
void SPI_1_PORT_init(void)
void SPI_1_MSIF_PORT_init(void)
{
gpio_set_pin_level(SPI1_MOSI,
@ -451,7 +452,7 @@ void SPI_1_PORT_init(void)
gpio_set_pin_function(SPI1_MISO, PINMUX_PB23C_SERCOM1_PAD3);
}
void SPI_1_CLOCK_init(void)
void SPI_1_MSIF_CLOCK_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
@ -459,11 +460,11 @@ void SPI_1_CLOCK_init(void)
hri_mclk_set_APBAMASK_SERCOM1_bit(MCLK);
}
void SPI_1_init(void)
void SPI_1_MSIF_init(void)
{
SPI_1_CLOCK_init();
spi_m_sync_init(&SPI_1, SERCOM1);
SPI_1_PORT_init();
SPI_1_MSIF_CLOCK_init();
spi_m_dma_init(&SPI_1_MSIF, SERCOM1);
SPI_1_MSIF_PORT_init();
}
void SPI_2_PORT_init(void)
@ -716,6 +717,16 @@ void system_init(void)
// GPIO on PB22
gpio_set_pin_level(SPI1_CS,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
true);
// Set pin direction to output
gpio_set_pin_direction(SPI1_CS, GPIO_DIRECTION_OUT);
gpio_set_pin_function(SPI1_CS, GPIO_PIN_FUNCTION_OFF);
ADC_0_init();
@ -730,7 +741,7 @@ void system_init(void)
ECAT_QSPI_init();
SPI_1_init();
SPI_1_MSIF_init();
SPI_2_init();

13
2_Motor_Master/Motor_Master/Motor_Master/driver_init.h
View File

@ -33,7 +33,7 @@ extern "C" {
#include <hal_qspi_dma.h>
#include <hal_spi_m_sync.h>
#include <hal_spi_m_dma.h>
#include <hal_spi_m_async.h>
#include <hal_spi_m_sync.h>
@ -52,8 +52,9 @@ extern struct adc_sync_descriptor ADC_0;
extern struct adc_sync_descriptor ADC_1;
extern struct qspi_dma_descriptor ECAT_QSPI;
extern struct spi_m_sync_descriptor SPI_1;
extern struct qspi_dma_descriptor ECAT_QSPI;
extern struct spi_m_dma_descriptor SPI_1_MSIF;
extern struct spi_m_async_descriptor SPI_2;
extern struct spi_m_sync_descriptor SPI_3;
@ -79,9 +80,9 @@ void ECAT_QSPI_PORT_init(void);
void ECAT_QSPI_CLOCK_init(void);
void ECAT_QSPI_init(void);
void SPI_1_PORT_init(void);
void SPI_1_CLOCK_init(void);
void SPI_1_init(void);
void SPI_1_MSIF_PORT_init(void);
void SPI_1_MSIF_CLOCK_init(void);
void SPI_1_MSIF_init(void);
void SPI_2_PORT_init(void);
void SPI_2_CLOCK_init(void);

24
2_Motor_Master/Motor_Master/Motor_Master/examples/driver_examples.c
View File

@ -101,17 +101,29 @@ void ECAT_QSPI_example(void)
}
/**
* Example of using SPI_1 to write "Hello World" using the IO abstraction.
* Example of using SPI_1_MSIF to write "Hello World" using the IO abstraction.
*
* Since the driver is asynchronous we need to use statically allocated memory for string
* because driver initiates transfer and then returns before the transmission is completed.
*
* Once transfer has been completed the tx_cb function will be called.
*/
static uint8_t example_SPI_1[12] = "Hello World!";
void SPI_1_example(void)
static uint8_t example_SPI_1_MSIF[12] = "Hello World!";
static void tx_complete_cb_SPI_1_MSIF(struct _dma_resource *resource)
{
/* Transfer completed */
}
void SPI_1_MSIF_example(void)
{
struct io_descriptor *io;
spi_m_sync_get_io_descriptor(&SPI_1, &io);
spi_m_dma_get_io_descriptor(&SPI_1_MSIF, &io);
spi_m_sync_enable(&SPI_1);
io_write(io, example_SPI_1, 12);
spi_m_dma_register_callback(&SPI_1_MSIF, SPI_M_DMA_CB_TX_DONE, tx_complete_cb_SPI_1_MSIF);
spi_m_dma_enable(&SPI_1_MSIF);
io_write(io, example_SPI_1_MSIF, 12);
}
/**

2
2_Motor_Master/Motor_Master/Motor_Master/examples/driver_examples.h
View File

@ -22,6 +22,8 @@ void EXTERNAL_IRQ_0_example(void);
void ECAT_QSPI_example(void);
void SPI_1_MSIF_example(void);
void SPI_2_example(void);
void TIMER_0_example(void);

56
2_Motor_Master/Motor_Master/Motor_Master/hal/documentation/spi_master_dma.rst Normal file
View File

@ -0,0 +1,56 @@
The SPI Master DMA Driver
==================================
The serial peripheral interface (SPI) is a DMA serial communication
interface.
The SPI Master DMA driver uses DMA system to transfer data from
a memory buffer to SPI (Memory to Peripheral), and receive data
from SPI to a memory buffer (Peripheral to Memory).User must configure
DMA system driver accordingly. A callback is called when all the data
is transfered or all the data is received, if it is registered via
spi_m_dma_register_callback function.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Control of the following settings:
* Baudrate
* SPI mode
* Character size
* Data order
* Data transfer: transmission, reception and full-duplex
* Notifications about transfer completion and errors via callbacks
Applications
------------
Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card,
LCD controller, etc.
Dependencies
------------
SPI master capable hardware and DMA hardware, with data sent/received.
Concurrency
-----------
N/A
Limitations
-----------
When only uses DMA channel to receive data, the transfer channel must enable to
send dummy data to the slave.
While read/write/transfer is in progress, the data buffer used must be kept
unchanged.
Known issues and workarounds
----------------------------
N/A

257
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@ -0,0 +1,257 @@
/**
* \file
*
* \brief SPI DMA related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SPI_M_DMA_H_INCLUDED
#define _HAL_SPI_M_DMA_H_INCLUDED
#include <hal_io.h>
#include <hpl_spi_m_dma.h>
/**
* \addtogroup doc_driver_hal_spi_master_dma
*
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/* Forward declaration of spi_descriptor. */
struct spi_m_dma_descriptor;
/** The callback types */
enum spi_m_dma_cb_type {
/** Callback type for DMA transfer buffer done */
SPI_M_DMA_CB_TX_DONE,
/** Callback type for DMA receive buffer done */
SPI_M_DMA_CB_RX_DONE,
/** Callback type for DMA errors */
SPI_M_DMA_CB_ERROR,
SPI_M_DMA_CB_N
};
/**
* \brief SPI Master DMA callback type
*/
typedef void (*spi_m_dma_cb_t)(struct _dma_resource *resource);
/** \brief SPI HAL driver struct for DMA access
*/
struct spi_m_dma_descriptor {
struct _spi_m_dma_hpl_interface *func;
/** Pointer to SPI device instance */
struct _spi_m_dma_dev dev;
/** I/O read/write */
struct io_descriptor io;
/** DMA resource */
struct _dma_resource *resource;
};
/** \brief Set the SPI HAL instance function pointer for HPL APIs.
*
* Set SPI HAL instance function pointer for HPL APIs.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] func Pointer to the HPL api structure.
*
*/
void spi_m_dma_set_func_ptr(struct spi_m_dma_descriptor *spi, void *const func);
/** \brief Initialize the SPI HAL instance and hardware for DMA mode
*
* Initialize SPI HAL with dma mode.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] hw Pointer to the hardware base.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_INVALID_DATA Error, initialized.
*/
int32_t spi_m_dma_init(struct spi_m_dma_descriptor *spi, void *const hw);
/** \brief Deinitialize the SPI HAL instance
*
* Abort transfer, disable and reset SPI, de-init software.
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_dma_deinit(struct spi_m_dma_descriptor *spi);
/** \brief Enable SPI
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_dma_enable(struct spi_m_dma_descriptor *spi);
/** \brief Disable SPI
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_dma_disable(struct spi_m_dma_descriptor *spi);
/** \brief Set SPI baudrate
*
* Works if SPI is initialized as master.
* In the function a sanity check is used to confirm it's called in the correct mode.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] baud_val The target baudrate value
* (See "baudrate calculation" for calculating the value).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy.
*
* note: This api should be used to write the baudrate register with the given baud_val
* paramter, the user has to calculate the baud_val for required baud rate and pass it as
* argument(baud_val) to this api
*/
int32_t spi_m_dma_set_baudrate(struct spi_m_dma_descriptor *spi, const uint32_t baud_val);
/** \brief Set SPI mode
*
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase:
* - Mode 0: leading edge is rising edge, data sample on leading edge.
* - Mode 1: leading edge is rising edge, data sample on trailing edge.
* - Mode 2: leading edge is falling edge, data sample on leading edge.
* - Mode 3: leading edge is falling edge, data sample on trailing edge.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] mode The mode (\ref spi_transfer_mode).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy, CS activated.
*/
int32_t spi_m_dma_set_mode(struct spi_m_dma_descriptor *spi, const enum spi_transfer_mode mode);
/** \brief Set the SPI transfer character size in number of bits
*
* The character size (\ref spi_char_size) influence the way the data is
* sent/received.
* For char size <= 8-bit, data is stored byte by byte.
* For char size between 9-bit ~ 16-bit, data is stored in 2-byte length.
* Note that the default and recommended char size is 8-bit since it's
* supported by all system.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] char_size The char size (\ref spi_char_size).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy, CS activated.
* \retval ERR_INVALID_ARG The char size is not supported.
*/
int32_t spi_m_dma_set_char_size(struct spi_m_dma_descriptor *spi, const enum spi_char_size char_size);
/** \brief Set SPI transfer data order
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] dord The data order: send LSB/MSB first.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy, CS activated.
* \retval ERR_INVALID The data order is not supported.
*/
int32_t spi_m_dma_set_data_order(struct spi_m_dma_descriptor *spi, const enum spi_data_order dord);
/** \brief Perform the SPI data transfer (TX and RX) with the DMA
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] txbuf Pointer to the transfer information.
* \param[out] rxbuf Pointer to the receiver information.
* \param[in] length SPI transfer data length.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy.
*/
int32_t spi_m_dma_transfer(struct spi_m_dma_descriptor *spi, uint8_t const *txbuf, uint8_t *const rxbuf,
const uint16_t length);
/** \brief Register a function as an SPI transfer completion callback
*
* Register a callback function specified by its \c type.
* - SPI_CB_COMPLETE: set the function that will be called on the SPI transfer
* completion including deactivating the CS.
* - SPI_CB_XFER: set the function that will be called on the SPI buffer transfer
* completion.
* Register a NULL function to not use the callback.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] type Callback type (\ref spi_m_dma_cb_type).
* \param[in] func Pointer to callback function.
*/
void spi_m_dma_register_callback(struct spi_m_dma_descriptor *spi, const enum spi_m_dma_cb_type type,
spi_m_dma_cb_t func);
/**
* \brief Return I/O descriptor for this SPI instance
*
* This function will return an I/O instance for this SPI driver instance
*
* \param[in] spi An SPI master descriptor, which is used to communicate through
* SPI
* \param[in, out] io A pointer to an I/O descriptor pointer type
*
* \retval ERR_NONE
*/
int32_t spi_m_dma_get_io_descriptor(struct spi_m_dma_descriptor *const spi, struct io_descriptor **io);
/** \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t spi_m_dma_get_version(void);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HAL_SPI_M_DMA_H_INCLUDED */

183
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@ -0,0 +1,183 @@
/**
* \file
*
* \brief I/O SPI DMA related functionality implementation.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_atomic.h"
#include "hal_spi_m_dma.h"
#include <utils_assert.h>
#include <utils.h>
/**
* \brief Driver version
*/
#define SPI_DRIVER_VERSION 0x00000001u
static int32_t _spi_m_dma_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length);
static int32_t _spi_m_dma_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length);
/**
* \brief Initialize the SPI HAL instance function pointer for HPL APIs.
*/
void spi_m_dma_set_func_ptr(struct spi_m_dma_descriptor *spi, void *const func)
{
ASSERT(spi);
spi->func = (struct _spi_m_dma_hpl_interface *)func;
}
int32_t spi_m_dma_init(struct spi_m_dma_descriptor *spi, void *const hw)
{
int32_t rc = 0;
ASSERT(spi && hw);
spi->dev.prvt = (void *)hw;
rc = _spi_m_dma_init(&spi->dev, hw);
if (rc) {
return rc;
}
spi->io.read = _spi_m_dma_io_read;
spi->io.write = _spi_m_dma_io_write;
return ERR_NONE;
}
void spi_m_dma_deinit(struct spi_m_dma_descriptor *spi)
{
ASSERT(spi);
_spi_m_dma_deinit(&spi->dev);
}
void spi_m_dma_enable(struct spi_m_dma_descriptor *spi)
{
ASSERT(spi);
_spi_m_dma_enable(&spi->dev);
}
void spi_m_dma_disable(struct spi_m_dma_descriptor *spi)
{
ASSERT(spi);
_spi_m_dma_disable(&spi->dev);
}
int32_t spi_m_dma_set_baudrate(struct spi_m_dma_descriptor *spi, const uint32_t baud_val)
{
ASSERT(spi);
return _spi_m_dma_set_baudrate(&spi->dev, baud_val);
}
int32_t spi_m_dma_set_mode(struct spi_m_dma_descriptor *spi, const enum spi_transfer_mode mode)
{
ASSERT(spi);
return _spi_m_dma_set_mode(&spi->dev, mode);
}
int32_t spi_m_dma_set_char_size(struct spi_m_dma_descriptor *spi, const enum spi_char_size char_size)
{
ASSERT(spi);
return _spi_m_dma_set_char_size(&spi->dev, char_size);
}
int32_t spi_m_dma_set_data_order(struct spi_m_dma_descriptor *spi, const enum spi_data_order dord)
{
ASSERT(spi);
return _spi_m_dma_set_data_order(&spi->dev, dord);
}
/** \brief Do SPI read in background
*
* It never blocks and return quickly, user check status or set callback to
* know when data is ready to process.
*
* \param[in, out] spi Pointer to the HAL SPI instance.
* \param[out] p_buf Pointer to the buffer to store read data.
* \param[in] size Size of the data in number of characters.
* \return ERR_NONE on success, or an error code on failure.
* \retval ERR_NONE Success, transfer started.
* \retval ERR_BUSY Busy.
*/
static int32_t _spi_m_dma_io_read(struct io_descriptor *io, uint8_t *const buf, const uint16_t length)
{
ASSERT(io);
struct spi_m_dma_descriptor *spi = CONTAINER_OF(io, struct spi_m_dma_descriptor, io);
return _spi_m_dma_transfer(&spi->dev, NULL, buf, length);
}
/** \brief Do SPI data write in background
*
* The data read back is discarded.
*
* It never blocks and return quickly, user check status or set callback to
* know when data is sent.
*
* \param[in, out] spi Pointer to the HAL SPI instance.
* \param[in] p_buf Pointer to the buffer to store data to write.
* \param[in] size Size of the data in number of characters.
*
* \return ERR_NONE on success, or an error code on failure.
* \retval ERR_NONE Success, transfer started.
* \retval ERR_BUSY Busy.
*/
static int32_t _spi_m_dma_io_write(struct io_descriptor *io, const uint8_t *const buf, const uint16_t length)
{
ASSERT(io);
struct spi_m_dma_descriptor *spi = CONTAINER_OF(io, struct spi_m_dma_descriptor, io);
return _spi_m_dma_transfer(&spi->dev, buf, NULL, length);
}
int32_t spi_m_dma_transfer(struct spi_m_dma_descriptor *spi, uint8_t const *txbuf, uint8_t *const rxbuf,
const uint16_t length)
{
ASSERT(spi);
return _spi_m_dma_transfer(&spi->dev, txbuf, rxbuf, length);
}
void spi_m_dma_register_callback(struct spi_m_dma_descriptor *spi, const enum spi_m_dma_cb_type type,
spi_m_dma_cb_t func)
{
ASSERT(spi);
_spi_m_dma_register_callback(&spi->dev, (enum _spi_dma_dev_cb_type)type, func);
}
int32_t spi_m_dma_get_io_descriptor(struct spi_m_dma_descriptor *const spi, struct io_descriptor **io)
{
ASSERT(spi && io);
*io = &spi->io;
return 0;
}
uint32_t spi_m_dma_get_version(void)
{
return SPI_DRIVER_VERSION;
}

426
2_Motor_Master/Motor_Master/Motor_Master/hpl/sercom/hpl_sercom.c
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@ -31,6 +31,7 @@
* \asf_license_stop
*
*/
#include <hpl_spi_m_dma.h>
#include <hpl_dma.h>
#include <hpl_i2c_m_async.h>
#include <hpl_i2c_m_sync.h>
@ -3018,3 +3019,428 @@ void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum
{
_spi_m_async_set_irq_state(device, type, state);
}
#ifndef CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_0_SPI_M_DMA_RX_CHANNEL
#define CONF_SERCOM_0_SPI_M_DMA_RX_CHANNEL 1
#endif
#ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL
#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 1
#endif
#ifndef CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL
#define CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL 1
#endif
#ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL
#define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1
#endif
#ifndef CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL
#define CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL 1
#endif
#ifndef CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL
#define CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL 1
#endif
#ifndef CONF_SERCOM_6_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_6_SPI_M_DMA_TX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_6_SPI_M_DMA_RX_CHANNEL
#define CONF_SERCOM_6_SPI_M_DMA_RX_CHANNEL 1
#endif
#ifndef CONF_SERCOM_7_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_7_SPI_M_DMA_TX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_7_SPI_M_DMA_RX_CHANNEL
#define CONF_SERCOM_7_SPI_M_DMA_RX_CHANNEL 1
#endif
#ifndef CONF_SERCOM_0_SPI_RX_CHANNEL
#define CONF_SERCOM_0_SPI_RX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_1_SPI_RX_CHANNEL
#define CONF_SERCOM_1_SPI_RX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_2_SPI_RX_CHANNEL
#define CONF_SERCOM_2_SPI_RX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_3_SPI_RX_CHANNEL
#define CONF_SERCOM_3_SPI_RX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_4_SPI_RX_CHANNEL
#define CONF_SERCOM_4_SPI_RX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_5_SPI_RX_CHANNEL
#define CONF_SERCOM_5_SPI_RX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_6_SPI_RX_CHANNEL
#define CONF_SERCOM_6_SPI_RX_CHANNEL 0
#endif
#ifndef CONF_SERCOM_7_SPI_RX_CHANNEL
#define CONF_SERCOM_7_SPI_RX_CHANNEL 0
#endif
/** \internal Enable SERCOM SPI RX
*
* \param[in] hw Pointer to the hardware register base.
*
* \return Enabling status
*/
static int32_t _spi_sync_rx_enable(void *const hw)
{
if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_CTRLB)) {
return ERR_BUSY;
}
hri_sercomspi_set_CTRLB_RXEN_bit(hw);
return ERR_NONE;
}
/** \internal Disable SERCOM SPI RX
*
* \param[in] hw Pointer to the hardware register base.
*
* \return Disabling status
*/
static int32_t _spi_sync_rx_disable(void *const hw)
{
if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_CTRLB)) {
return ERR_BUSY;
}
hri_sercomspi_clear_CTRLB_RXEN_bit(hw);
return ERR_NONE;
}
static int32_t _spi_m_dma_rx_enable(struct _spi_m_dma_dev *dev)
{
ASSERT(dev && dev->prvt);
return _spi_sync_rx_enable(dev->prvt);
}
static int32_t _spi_m_dma_rx_disable(struct _spi_m_dma_dev *dev)
{
ASSERT(dev && dev->prvt);
return _spi_sync_rx_disable(dev->prvt);
}
/**
* \brief Get the spi source address for DMA
* \param[in] dev Pointer to the SPI device instance
*
* \return The spi source address
*/
static uint32_t _spi_m_get_source_for_dma(void *const hw)
{
return (uint32_t) & (((Sercom *)hw)->SPI.DATA);
}
/**
* \brief Get the spi destination address for DMA
* \param[in] dev Pointer to the SPI device instance
*
* \return The spi destination address
*/
static uint32_t _spi_m_get_destination_for_dma(void *const hw)
{
return (uint32_t) & (((Sercom *)hw)->SPI.DATA);
}
/**
* \brief Return the SPI TX DMA channel index
* \param[in] hw_addr The hardware register base address
*
* \return SPI TX DMA channel index.
*/
static uint8_t _spi_get_tx_dma_channel(const void *const hw)
{
uint8_t index = _sercom_get_hardware_index(hw);
switch (index) {
case 0:
return CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL;
case 1:
return CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL;
case 2:
return CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL;
case 3:
return CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL;
case 4:
return CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL;
case 5:
return CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL;
case 6:
return CONF_SERCOM_6_SPI_M_DMA_TX_CHANNEL;
case 7:
return CONF_SERCOM_7_SPI_M_DMA_TX_CHANNEL;
default:
return CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL;
}
}
/**
* \brief Return whether SPI RX DMA channel is enabled or not
* \param[in] hw_addr The hardware register base address
*
* \return one if enabled.
*/
static uint8_t _spi_is_rx_dma_channel_enabled(const void *const hw)
{
uint8_t index = _sercom_get_hardware_index(hw);
switch (index) {
case 0:
return CONF_SERCOM_0_SPI_RX_CHANNEL;
case 1:
return CONF_SERCOM_1_SPI_RX_CHANNEL;
case 2:
return CONF_SERCOM_2_SPI_RX_CHANNEL;
case 3:
return CONF_SERCOM_3_SPI_RX_CHANNEL;
case 4:
return CONF_SERCOM_4_SPI_RX_CHANNEL;
case 5:
return CONF_SERCOM_5_SPI_RX_CHANNEL;
case 6:
return CONF_SERCOM_6_SPI_RX_CHANNEL;
case 7:
return CONF_SERCOM_7_SPI_RX_CHANNEL;
default:
return false;
}
}
/**
* \brief Return the SPI RX DMA channel index
* \param[in] hw_addr The hardware register base address
*
* \return SPI RX DMA channel index.
*/
static uint8_t _spi_get_rx_dma_channel(const void *const hw)
{
uint8_t index = _sercom_get_hardware_index(hw);
switch (index) {
case 0:
return CONF_SERCOM_0_SPI_M_DMA_RX_CHANNEL;
case 1:
return CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL;
case 2:
return CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL;
case 3:
return CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL;
case 4:
return CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL;
case 5:
return CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL;
case 6:
return CONF_SERCOM_6_SPI_M_DMA_RX_CHANNEL;
case 7:
return CONF_SERCOM_7_SPI_M_DMA_RX_CHANNEL;
default:
return CONF_SERCOM_0_SPI_M_DMA_TX_CHANNEL;
}
}
/**
* \brief Callback for RX
* \param[in, out] dev Pointer to the DMA resource.
*/
static void _spi_dma_rx_complete(struct _dma_resource *resource)
{
struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back;
if (dev->callbacks.rx) {
dev->callbacks.rx(resource);
}
}
/**
* \brief Callback for TX
* \param[in, out] dev Pointer to the DMA resource.
*/
static void _spi_dma_tx_complete(struct _dma_resource *resource)
{
struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back;
if (dev->callbacks.tx) {
dev->callbacks.tx(resource);
}
}
/**
* \brief Callback for ERROR
* \param[in, out] dev Pointer to the DMA resource.
*/
static void _spi_dma_error_occured(struct _dma_resource *resource)
{
struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back;
if (dev->callbacks.error) {
dev->callbacks.error(resource);
}
}
int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw)
{
const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw);
ASSERT(dev && hw);
if (regs == NULL) {
return ERR_INVALID_ARG;
}
if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE);
}
hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode);
}
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
dev->prvt = hw;
_spi_load_regs_master(hw, regs);
/* If enabled, initialize DMA rx channel */
if (_spi_is_rx_dma_channel_enabled(hw)) {
_dma_get_channel_resource(&dev->resource, _spi_get_rx_dma_channel(hw));
dev->resource->back = dev;
dev->resource->dma_cb.transfer_done = _spi_dma_rx_complete;
dev->resource->dma_cb.error = _spi_dma_error_occured;
}
/* Initialize DMA tx channel */
_dma_get_channel_resource(&dev->resource, _spi_get_tx_dma_channel(hw));
dev->resource->back = dev;
dev->resource->dma_cb.transfer_done = _spi_dma_tx_complete;
dev->resource->dma_cb.error = _spi_dma_error_occured;
return ERR_NONE;
}
int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev)
{
return _spi_deinit(dev->prvt);
}
int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev)
{
ASSERT(dev && dev->prvt);
return _spi_sync_enable(dev->prvt);
}
int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev)
{
ASSERT(dev && dev->prvt);
return _spi_sync_disable(dev->prvt);
}
int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode)
{
ASSERT(dev && dev->prvt);
return _spi_set_mode(dev->prvt, mode);
}
int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val)
{
ASSERT(dev && dev->prvt);
return _spi_set_baudrate(dev->prvt, baud_val);
}
int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord)
{
ASSERT(dev && dev->prvt);
return _spi_set_data_order(dev->prvt, dord);
}
int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size)
{
uint8_t size;
ASSERT(dev && dev->prvt);
_spi_set_char_size(dev->prvt, char_size, &size);
return size;
}
void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type type, _spi_dma_cb_t func)
{
switch (type) {
case SPI_DEV_CB_DMA_TX:
dev->callbacks.tx = func;
_dma_set_irq_state(_spi_get_tx_dma_channel(dev->prvt), DMA_TRANSFER_COMPLETE_CB, func != NULL);
break;
case SPI_DEV_CB_DMA_RX:
dev->callbacks.rx = func;
_dma_set_irq_state(_spi_get_rx_dma_channel(dev->prvt), DMA_TRANSFER_COMPLETE_CB, func != NULL);
break;
case SPI_DEV_CB_DMA_ERROR:
dev->callbacks.error = func;
_dma_set_irq_state(_spi_get_rx_dma_channel(dev->prvt), DMA_TRANSFER_ERROR_CB, func != NULL);
_dma_set_irq_state(_spi_get_tx_dma_channel(dev->prvt), DMA_TRANSFER_ERROR_CB, func != NULL);
break;
case SPI_DEV_CB_DMA_N:
break;
}
}
int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf,
const uint16_t length)
{
const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)dev->prvt);
uint8_t rx_ch = _spi_get_rx_dma_channel(dev->prvt);
uint8_t tx_ch = _spi_get_tx_dma_channel(dev->prvt);
if (rxbuf) {
/* Enable spi rx */
_spi_m_dma_rx_enable(dev);
_dma_set_source_address(rx_ch, (void *)_spi_m_get_source_for_dma(dev->prvt));
_dma_set_destination_address(rx_ch, rxbuf);
_dma_set_data_amount(rx_ch, length);
_dma_enable_transaction(rx_ch, false);
} else {
/* Disable spi rx */
_spi_m_dma_rx_disable(dev);
}
if (txbuf) {
/* Enable spi tx */
_dma_set_source_address(tx_ch, txbuf);
_dma_set_destination_address(tx_ch, (void *)_spi_m_get_destination_for_dma(dev->prvt));
_dma_srcinc_enable(tx_ch, true);
_dma_set_data_amount(tx_ch, length);
} else {
_dma_set_source_address(tx_ch, &regs->dummy_byte);
_dma_set_destination_address(tx_ch, (void *)_spi_m_get_destination_for_dma(dev->prvt));
_dma_srcinc_enable(tx_ch, false);
_dma_set_data_amount(tx_ch, length);
}
_dma_enable_transaction(tx_ch, false);
return ERR_NONE;
}

11
2_Motor_Master/Motor_Master/Motor_Master/interrupts.h
View File

@ -9,6 +9,17 @@
#ifndef INTERRUPTS_H_
#define INTERRUPTS_H_
// ----------------------------------------------------------------------
// Master/Slave IF Callback
// ----------------------------------------------------------------------
static void b2bTransferComplete_cb(struct _dma_resource *resource)
{
gpio_set_pin_level(SPI1_CS, true);
}
// ----------------------------------------------------------------------
// ADC Callback for Motor Phase Current Measurement.
// Phase A & B Sampled and converted from LSB to Process Unit PU(Amps)

29
2_Motor_Master/Motor_Master/Motor_Master/main.c
View File

@ -7,10 +7,31 @@
#include "bldc_types.h"
#include "EtherCAT_QSPI.h"
#include "EtherCAT_SlaveDef.h"
//#include "MSIF_master.h"
#include "configuration.h"
#include "interrupts.h"
#include "statemachine.h"
#define MASTER_BUFFER_SIZE 64
struct SPI_slaveboard {
struct spi_m_dma_descriptor *SPI_Mn;
uint8_t state;
uint32_t SS_pin;
uint32_t *tx_buffer;
uint32_t *rx_buffer;
};
struct SPI_slaveboard Slave_1 = {
.SPI_Mn = &SPI_1_MSIF,
.state = 0,
.SS_pin = SPI1_CS,
.tx_buffer = &QSPI_tx_buffer[16],
.rx_buffer = &QSPI_rx_buffer[16],
};
void process_currents()
{
@ -56,6 +77,13 @@ static void One_ms_cycle_callback(const struct timer_task *const timer_task)
update_telemetry();
update_setpoints();
/*Master Slave Transfer */
//tx_buffer[0] += 1;
//tx_buffer[31] += 1;
//gpio_set_pin_level(SPI1_CS, false);
//spi_m_dma_transfer(&SPI_1_MSIF, (uint8_t*)Slave_1.tx_buffer, (uint8_t*)Slave_1.rx_buffer, MASTER_BUFFER_SIZE);
//run_ECAT = true;
}
@ -173,6 +201,7 @@ int main(void)
configure_tcc_pwm();
adc_sync_enable_channel(&ADC_1, 6);
adc_init_dma();
boardToBoardTransferInit();
ECAT_STATE_MACHINE();
One_ms_timer_init();
custom_logic_enable();

22
2_Motor_Slave/Motor_Slave/Motor_Slave.atsln Normal file
View File

@ -0,0 +1,22 @@

Microsoft Visual Studio Solution File, Format Version 12.00
# Atmel Studio Solution File, Format Version 11.00
VisualStudioVersion = 14.0.23107.0
MinimumVisualStudioVersion = 10.0.40219.1
Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "Motor_Slave", "Motor_Slave\Motor_Slave.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
Debug|ARM = Debug|ARM
Release|ARM = Release|ARM
EndGlobalSection
GlobalSection(ProjectConfigurationPlatforms) = postSolution
{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
EndGlobalSection
GlobalSection(SolutionProperties) = preSolution
HideSolutionNode = FALSE
EndGlobalSection
EndGlobal

6
2_Motor_Slave/Motor_Slave/Motor_Slave/.atmelstart/AtmelStart.env_conf Normal file
View File

@ -0,0 +1,6 @@
<environment>
<configurations/>
<device-packs>
<device-pack device="ATSAME51J19A" name="SAME51_DFP" vendor="Atmel" version="1.1.139"/>
</device-packs>
</environment>

258
2_Motor_Slave/Motor_Slave/Motor_Slave/.atmelstart/AtmelStart.gpdsc Normal file
View File

@ -0,0 +1,258 @@
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
<vendor>Atmel</vendor>
<name>Motor_Slave</name>
<description>Project generated by Atmel Start</description>
<url>http://start.atmel.com/</url>
<releases>
<release version="1.0.1">Initial version</release>
</releases>
<taxonomy>
<description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
</taxonomy>
<generators>
<generator id="AtmelStart">
<description>Atmel Start</description>
<select Dname="ATSAME51J19A" Dvendor="Atmel:3"/>
<command>http://start.atmel.com/</command>
<files>
<file category="generator" name="atmel_start_config.atstart"/>
<file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
</files>
</generator>
</generators>
<conditions>
<condition id="CMSIS Device Startup">
<description>Dependency on CMSIS core and Device Startup components</description>
<require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
<require Cclass="Device" Cgroup="Startup" Cversion="1.1.0"/>
</condition>
<condition id="ARMCC, GCC, IAR">
<require Dname="ATSAME51J19A"/>
<accept Tcompiler="ARMCC"/>
<accept Tcompiler="GCC"/>
<accept Tcompiler="IAR"/>
</condition>
<condition id="GCC">
<require Dname="ATSAME51J19A"/>
<accept Tcompiler="GCC"/>
</condition>
</conditions>
<components generator="AtmelStart">
<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
<description>Atmel Start Framework</description>
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
<files>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/custom_logic.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/evsys.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/ext_irq.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/pwm.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/quad_spi_dma.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_async.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_sync.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_slave_sync.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/timer.rst"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_custom_logic.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_evsys.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_ext_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_qspi_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_s_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_cmcc.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_custom_logic.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_evsys.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ext_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_cache.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_evsys.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_qspi_dma.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hpl/doc_lite/tc.rst"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_can_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_cmcc_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dac_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hmatrixb_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_i2s_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_icm_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pcc_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pdec_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_qspi_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ramecc_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sdhc_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_e51.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e51.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_pwm.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_timer.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_pwm.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_timer.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_ext_irq.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_pwm.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_async.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_s_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_timer.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ccl/hpl_ccl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/cmcc/hpl_cmcc.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m4.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/eic/hpl_eic.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/evsys/hpl_evsys.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/qspi/hpl_qspi.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_adc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_ccl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_eic_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_evsys_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_qspi_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tcc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/adc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/ccl"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/cmcc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/eic"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/evsys"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/qspi"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/ramecc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/tc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/tcc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
</files>
</component>
</components>
</package>

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/**
* \file
*
* \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
*
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
*
* \acme_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \acme_license_stop
*
* Project: Motor_Slave
* Target: ATSAME51J19A
*
**/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#define ATMEL_START
#endif /* RTE_COMPONENTS_H */

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/* Auto-generated config file hpl_adc_config.h */
#ifndef HPL_ADC_CONFIG_H
#define HPL_ADC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef CONF_ADC_0_ENABLE
#define CONF_ADC_0_ENABLE 1
#endif
// <h> Basic Configuration
// <o> Conversion Result Resolution
// <0x0=>12-bit
// <0x1=>16-bit (averaging must be enabled)
// <0x2=>10-bit
// <0x3=>8-bit
// <i> Defines the bit resolution for the ADC sample values (RESSEL)
// <id> adc_resolution
#ifndef CONF_ADC_0_RESSEL
#define CONF_ADC_0_RESSEL 0x0
#endif
// <o> Reference Selection
// <0x0=>Internal bandgap reference
// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
// <0x3=>VDDANA
// <0x4=>External reference A
// <0x5=>External reference B
// <0x6=>External reference C
// <i> Select the reference for the ADC (REFSEL)
// <id> adc_reference
#ifndef CONF_ADC_0_REFSEL
#define CONF_ADC_0_REFSEL 0x4
#endif
// <o> Prescaler configuration
// <0x0=>Peripheral clock divided by 2
// <0x1=>Peripheral clock divided by 4
// <0x2=>Peripheral clock divided by 8
// <0x3=>Peripheral clock divided by 16
// <0x4=>Peripheral clock divided by 32
// <0x5=>Peripheral clock divided by 64
// <0x6=>Peripheral clock divided by 128
// <0x7=>Peripheral clock divided by 256
// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
// <id> adc_prescaler
#ifndef CONF_ADC_0_PRESCALER
#define CONF_ADC_0_PRESCALER 0x0
#endif
// <q> Free Running Mode
// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
// <id> adc_freerunning_mode
#ifndef CONF_ADC_0_FREERUN
#define CONF_ADC_0_FREERUN 0
#endif
// <q> Differential Mode
// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
// <id> adc_differential_mode
#ifndef CONF_ADC_0_DIFFMODE
#define CONF_ADC_0_DIFFMODE 1
#endif
// <o> Positive Mux Input Selection
// <0x00=>ADC AIN0 pin
// <0x01=>ADC AIN1 pin
// <0x02=>ADC AIN2 pin
// <0x03=>ADC AIN3 pin
// <0x04=>ADC AIN4 pin
// <0x05=>ADC AIN5 pin
// <0x06=>ADC AIN6 pin
// <0x07=>ADC AIN7 pin
// <0x08=>ADC AIN8 pin
// <0x09=>ADC AIN9 pin
// <0x0A=>ADC AIN10 pin
// <0x0B=>ADC AIN11 pin
// <0x0C=>ADC AIN12 pin
// <0x0D=>ADC AIN13 pin
// <0x0E=>ADC AIN14 pin
// <0x0F=>ADC AIN15 pin
// <0x18=>1/4 scaled core supply
// <0x19=>1/4 Scaled VBAT Supply
// <0x1A=>1/4 scaled I/O supply
// <0x1B=>Bandgap voltage
// <0x1C=>Temperature reference (PTAT)
// <0x1D=>Temperature reference (CTAT)
// <0x1E=>DAC Output
// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
// <id> adc_pinmux_positive
#ifndef CONF_ADC_0_MUXPOS
#define CONF_ADC_0_MUXPOS 0x0
#endif
// <o> Negative Mux Input Selection
// <0x00=>ADC AIN0 pin
// <0x01=>ADC AIN1 pin
// <0x02=>ADC AIN2 pin
// <0x03=>ADC AIN3 pin
// <0x04=>ADC AIN4 pin
// <0x05=>ADC AIN5 pin
// <0x06=>ADC AIN6 pin
// <0x07=>ADC AIN7 pin
// <0x18=>Internal ground
// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
// <id> adc_pinmux_negative
#ifndef CONF_ADC_0_MUXNEG
#define CONF_ADC_0_MUXNEG 0x2
#endif
// </h>
// <e> Advanced Configuration
// <id> adc_advanced_settings
#ifndef CONF_ADC_0_ADVANCED
#define CONF_ADC_0_ADVANCED 0
#endif
// <q> Run in standby
// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
// <id> adc_arch_runstdby
#ifndef CONF_ADC_0_RUNSTDBY
#define CONF_ADC_0_RUNSTDBY 0
#endif
// <q>Debug Run
// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
// <id> adc_arch_dbgrun
#ifndef CONF_ADC_0_DBGRUN
#define CONF_ADC_0_DBGRUN 0
#endif
// <q> On Demand Control
// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
// <id> adc_arch_ondemand
#ifndef CONF_ADC_0_ONDEMAND
#define CONF_ADC_0_ONDEMAND 0
#endif
// <q> Left-Adjusted Result
// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
// <id> adc_arch_leftadj
#ifndef CONF_ADC_0_LEFTADJ
#define CONF_ADC_0_LEFTADJ 0
#endif
// <q> Reference Buffer Offset Compensation Enable
// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
// <id> adc_arch_refcomp
#ifndef CONF_ADC_0_REFCOMP
#define CONF_ADC_0_REFCOMP 0
#endif
// <q>Comparator Offset Compensation Enable
// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
// <id> adc_arch_offcomp
#ifndef CONF_ADC_0_OFFCOMP
#define CONF_ADC_0_OFFCOMP 0
#endif
// <q> Digital Correction Logic Enabled
// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
// <id> adc_arch_corren
#ifndef CONF_ADC_0_CORREN
#define CONF_ADC_0_CORREN 0
#endif
// <o> Offset Correction Value <0-4095>
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
// <id> adc_arch_offsetcorr
#ifndef CONF_ADC_0_OFFSETCORR
#define CONF_ADC_0_OFFSETCORR 0
#endif
// <o> Gain Correction Value <0-4095>
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
// <id> adc_arch_gaincorr
#ifndef CONF_ADC_0_GAINCORR
#define CONF_ADC_0_GAINCORR 0
#endif
// <o> Adjusting Result / Division Coefficient <0-7>
// <i> These bits define the division coefficient in 2n steps. (ADJRES)
// <id> adc_arch_adjres
#ifndef CONF_ADC_0_ADJRES
#define CONF_ADC_0_ADJRES 0x0
#endif
// <o.0..10> Number of Samples to be Collected
// <0x0=>1 sample
// <0x1=>2 samples
// <0x2=>4 samples
// <0x3=>8 samples
// <0x4=>16 samples
// <0x5=>32 samples
// <0x6=>64 samples
// <0x7=>128 samples
// <0x8=>256 samples
// <0x9=>512 samples
// <0xA=>1024 samples
// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
// <id> adc_arch_samplenum
#ifndef CONF_ADC_0_SAMPLENUM
#define CONF_ADC_0_SAMPLENUM 0x0
#endif
// <o> Sampling Time Length <0-63>
// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
// <id> adc_arch_samplen
#ifndef CONF_ADC_0_SAMPLEN
#define CONF_ADC_0_SAMPLEN 0
#endif
// <o> Window Monitor Mode
// <0x0=>No window mode
// <0x1=>Mode 1: RESULT above lower threshold
// <0x2=>Mode 2: RESULT beneath upper threshold
// <0x3=>Mode 3: RESULT inside lower and upper threshold
// <0x4=>Mode 4: RESULT outside lower and upper threshold
// <i> These bits enable and define the window monitor mode. (WINMODE)
// <id> adc_arch_winmode
#ifndef CONF_ADC_0_WINMODE
#define CONF_ADC_0_WINMODE 0x0
#endif
// <o> Window Monitor Lower Threshold <0-65535>
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
// <id> adc_arch_winlt
#ifndef CONF_ADC_0_WINLT
#define CONF_ADC_0_WINLT 0
#endif
// <o> Window Monitor Upper Threshold <0-65535>
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
// <id> adc_arch_winut
#ifndef CONF_ADC_0_WINUT
#define CONF_ADC_0_WINUT 0
#endif
// <o> Bitmask for positive input sequence <0-4294967295>
// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
// <id> adc_arch_seqen
#ifndef CONF_ADC_0_SEQEN
#define CONF_ADC_0_SEQEN 0x0
#endif
// </e>
// <e> Event Control
// <id> adc_arch_event_settings
#ifndef CONF_ADC_0_EVENT_CONTROL
#define CONF_ADC_0_EVENT_CONTROL 0
#endif
// <q> Window Monitor Event Out
// <i> Enables event output on window event (WINMONEO)
// <id> adc_arch_winmoneo
#ifndef CONF_ADC_0_WINMONEO
#define CONF_ADC_0_WINMONEO 0
#endif
// <q> Result Ready Event Out
// <i> Enables event output on result ready event (RESRDEO)
// <id> adc_arch_resrdyeo
#ifndef CONF_ADC_0_RESRDYEO
#define CONF_ADC_0_RESRDYEO 0
#endif
// <q> Invert flush Event Signal
// <i> Invert the flush event input signal (FLUSHINV)
// <id> adc_arch_flushinv
#ifndef CONF_ADC_0_FLUSHINV
#define CONF_ADC_0_FLUSHINV 0
#endif
// <q> Trigger Flush On Event
// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
// <id> adc_arch_flushei
#ifndef CONF_ADC_0_FLUSHEI
#define CONF_ADC_0_FLUSHEI 0
#endif
// <q> Invert Start Conversion Event Signal
// <i> Invert the start conversion event input signal (STARTINV)
// <id> adc_arch_startinv
#ifndef CONF_ADC_0_STARTINV
#define CONF_ADC_0_STARTINV 0
#endif
// <q> Trigger Conversion On Event
// <i> Trigger a conversion on event. (STARTEI)
// <id> adc_arch_startei
#ifndef CONF_ADC_0_STARTEI
#define CONF_ADC_0_STARTEI 0
#endif
// </e>
#ifndef CONF_ADC_1_ENABLE
#define CONF_ADC_1_ENABLE 1
#endif
// <h> Basic Configuration
// <o> Conversion Result Resolution
// <0x0=>12-bit
// <0x1=>16-bit (averaging must be enabled)
// <0x2=>10-bit
// <0x3=>8-bit
// <i> Defines the bit resolution for the ADC sample values (RESSEL)
// <id> adc_resolution
#ifndef CONF_ADC_1_RESSEL
#define CONF_ADC_1_RESSEL 0x0
#endif
// <o> Reference Selection
// <0x0=>Internal bandgap reference
// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
// <0x3=>VDDANA
// <0x4=>External reference A
// <0x5=>External reference B
// <0x6=>External reference C
// <i> Select the reference for the ADC (REFSEL)
// <id> adc_reference
#ifndef CONF_ADC_1_REFSEL
#define CONF_ADC_1_REFSEL 0x4
#endif
// <o> Prescaler configuration
// <0x0=>Peripheral clock divided by 2
// <0x1=>Peripheral clock divided by 4
// <0x2=>Peripheral clock divided by 8
// <0x3=>Peripheral clock divided by 16
// <0x4=>Peripheral clock divided by 32
// <0x5=>Peripheral clock divided by 64
// <0x6=>Peripheral clock divided by 128
// <0x7=>Peripheral clock divided by 256
// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
// <id> adc_prescaler
#ifndef CONF_ADC_1_PRESCALER
#define CONF_ADC_1_PRESCALER 0x2
#endif
// <q> Free Running Mode
// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
// <id> adc_freerunning_mode
#ifndef CONF_ADC_1_FREERUN
#define CONF_ADC_1_FREERUN 0
#endif
// <q> Differential Mode
// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
// <id> adc_differential_mode
#ifndef CONF_ADC_1_DIFFMODE
#define CONF_ADC_1_DIFFMODE 1
#endif
// <o> Positive Mux Input Selection
// <0x00=>ADC AIN0 pin
// <0x01=>ADC AIN1 pin
// <0x02=>ADC AIN2 pin
// <0x03=>ADC AIN3 pin
// <0x04=>ADC AIN4 pin
// <0x05=>ADC AIN5 pin
// <0x06=>ADC AIN6 pin
// <0x07=>ADC AIN7 pin
// <0x08=>ADC AIN8 pin
// <0x09=>ADC AIN9 pin
// <0x0A=>ADC AIN10 pin
// <0x0B=>ADC AIN11 pin
// <0x0C=>ADC AIN12 pin
// <0x0D=>ADC AIN13 pin
// <0x0E=>ADC AIN14 pin
// <0x0F=>ADC AIN15 pin
// <0x18=>1/4 scaled core supply
// <0x19=>1/4 Scaled VBAT Supply
// <0x1A=>1/4 scaled I/O supply
// <0x1B=>Bandgap voltage
// <0x1C=>Temperature reference (PTAT)
// <0x1D=>Temperature reference (CTAT)
// <0x1E=>DAC Output
// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
// <id> adc_pinmux_positive
#ifndef CONF_ADC_1_MUXPOS
#define CONF_ADC_1_MUXPOS 0x6
#endif
// <o> Negative Mux Input Selection
// <0x00=>ADC AIN0 pin
// <0x01=>ADC AIN1 pin
// <0x02=>ADC AIN2 pin
// <0x03=>ADC AIN3 pin
// <0x04=>ADC AIN4 pin
// <0x05=>ADC AIN5 pin
// <0x06=>ADC AIN6 pin
// <0x07=>ADC AIN7 pin
// <0x18=>Internal ground
// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
// <id> adc_pinmux_negative
#ifndef CONF_ADC_1_MUXNEG
#define CONF_ADC_1_MUXNEG 0x0
#endif
// </h>
// <e> Advanced Configuration
// <id> adc_advanced_settings
#ifndef CONF_ADC_1_ADVANCED
#define CONF_ADC_1_ADVANCED 1
#endif
// <q> Run in standby
// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
// <id> adc_arch_runstdby
#ifndef CONF_ADC_1_RUNSTDBY
#define CONF_ADC_1_RUNSTDBY 0
#endif
// <q>Debug Run
// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
// <id> adc_arch_dbgrun
#ifndef CONF_ADC_1_DBGRUN
#define CONF_ADC_1_DBGRUN 0
#endif
// <q> On Demand Control
// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
// <id> adc_arch_ondemand
#ifndef CONF_ADC_1_ONDEMAND
#define CONF_ADC_1_ONDEMAND 0
#endif
// <q> Left-Adjusted Result
// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
// <id> adc_arch_leftadj
#ifndef CONF_ADC_1_LEFTADJ
#define CONF_ADC_1_LEFTADJ 0
#endif
// <q> Reference Buffer Offset Compensation Enable
// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
// <id> adc_arch_refcomp
#ifndef CONF_ADC_1_REFCOMP
#define CONF_ADC_1_REFCOMP 0
#endif
// <q>Comparator Offset Compensation Enable
// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
// <id> adc_arch_offcomp
#ifndef CONF_ADC_1_OFFCOMP
#define CONF_ADC_1_OFFCOMP 0
#endif
// <q> Digital Correction Logic Enabled
// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
// <id> adc_arch_corren
#ifndef CONF_ADC_1_CORREN
#define CONF_ADC_1_CORREN 0
#endif
// <o> Offset Correction Value <0-4095>
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
// <id> adc_arch_offsetcorr
#ifndef CONF_ADC_1_OFFSETCORR
#define CONF_ADC_1_OFFSETCORR 0
#endif
// <o> Gain Correction Value <0-4095>
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
// <id> adc_arch_gaincorr
#ifndef CONF_ADC_1_GAINCORR
#define CONF_ADC_1_GAINCORR 0
#endif
// <o> Adjusting Result / Division Coefficient <0-7>
// <i> These bits define the division coefficient in 2n steps. (ADJRES)
// <id> adc_arch_adjres
#ifndef CONF_ADC_1_ADJRES
#define CONF_ADC_1_ADJRES 0x0
#endif
// <o.0..10> Number of Samples to be Collected
// <0x0=>1 sample
// <0x1=>2 samples
// <0x2=>4 samples
// <0x3=>8 samples
// <0x4=>16 samples
// <0x5=>32 samples
// <0x6=>64 samples
// <0x7=>128 samples
// <0x8=>256 samples
// <0x9=>512 samples
// <0xA=>1024 samples
// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
// <id> adc_arch_samplenum
#ifndef CONF_ADC_1_SAMPLENUM
#define CONF_ADC_1_SAMPLENUM 0x0
#endif
// <o> Sampling Time Length <0-63>
// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
// <id> adc_arch_samplen
#ifndef CONF_ADC_1_SAMPLEN
#define CONF_ADC_1_SAMPLEN 3
#endif
// <o> Window Monitor Mode
// <0x0=>No window mode
// <0x1=>Mode 1: RESULT above lower threshold
// <0x2=>Mode 2: RESULT beneath upper threshold
// <0x3=>Mode 3: RESULT inside lower and upper threshold
// <0x4=>Mode 4: RESULT outside lower and upper threshold
// <i> These bits enable and define the window monitor mode. (WINMODE)
// <id> adc_arch_winmode
#ifndef CONF_ADC_1_WINMODE
#define CONF_ADC_1_WINMODE 0x0
#endif
// <o> Window Monitor Lower Threshold <0-65535>
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
// <id> adc_arch_winlt
#ifndef CONF_ADC_1_WINLT
#define CONF_ADC_1_WINLT 0
#endif
// <o> Window Monitor Upper Threshold <0-65535>
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
// <id> adc_arch_winut
#ifndef CONF_ADC_1_WINUT
#define CONF_ADC_1_WINUT 0
#endif
// <o> Bitmask for positive input sequence <0-4294967295>
// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
// <id> adc_arch_seqen
#ifndef CONF_ADC_1_SEQEN
#define CONF_ADC_1_SEQEN 0x0
#endif
// </e>
// <e> Event Control
// <id> adc_arch_event_settings
#ifndef CONF_ADC_1_EVENT_CONTROL
#define CONF_ADC_1_EVENT_CONTROL 1
#endif
// <q> Window Monitor Event Out
// <i> Enables event output on window event (WINMONEO)
// <id> adc_arch_winmoneo
#ifndef CONF_ADC_1_WINMONEO
#define CONF_ADC_1_WINMONEO 0
#endif
// <q> Result Ready Event Out
// <i> Enables event output on result ready event (RESRDEO)
// <id> adc_arch_resrdyeo
#ifndef CONF_ADC_1_RESRDYEO
#define CONF_ADC_1_RESRDYEO 1
#endif
// <q> Invert flush Event Signal
// <i> Invert the flush event input signal (FLUSHINV)
// <id> adc_arch_flushinv
#ifndef CONF_ADC_1_FLUSHINV
#define CONF_ADC_1_FLUSHINV 0
#endif
// <q> Trigger Flush On Event
// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
// <id> adc_arch_flushei
#ifndef CONF_ADC_1_FLUSHEI
#define CONF_ADC_1_FLUSHEI 0
#endif
// <q> Invert Start Conversion Event Signal
// <i> Invert the start conversion event input signal (STARTINV)
// <id> adc_arch_startinv
#ifndef CONF_ADC_1_STARTINV
#define CONF_ADC_1_STARTINV 0
#endif
// <q> Trigger Conversion On Event
// <i> Trigger a conversion on event. (STARTEI)
// <id> adc_arch_startei
#ifndef CONF_ADC_1_STARTEI
#define CONF_ADC_1_STARTEI 0
#endif
// </e>
// <<< end of configuration section >>>
#endif // HPL_ADC_CONFIG_H

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/* Auto-generated config file hpl_ccl_config.h */
#ifndef HPL_CCL_CONFIG_H
#define HPL_CCL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <o> Sequential Control Logic 0
// <0x0=> Sequential logic is disabled
// <0x1=> D flip flop
// <0x2=> JK flip flop
// <0x3=> D latch
// <0x4=> RS latch
// <i> Selects mode for sequential module 0
// <id> ccl_arch_seqsel_0
#ifndef CONF_CCL_SEQSEL_0
#define CONF_CCL_SEQSEL_0 0x0
#endif
// <o> Sequential Control Logic 1
// <0x0=> Sequential logic is disabled
// <0x1=> D flip flop
// <0x2=> JK flip flop
// <0x3=> D latch
// <0x4=> RS latch
// <i> Selects mode for sequential module 1
// <id> ccl_arch_seqsel_1
#ifndef CONF_CCL_SEQSEL_1
#define CONF_CCL_SEQSEL_1 0x0
#endif
// <e> Lookup Table Control 0
// <i> Enable and setup the lookup table module 0
// <id> ccl_arch_lutctrl0
#ifndef CONF_CCL_LUTCTRL_EN_0
#define CONF_CCL_LUTCTRL_EN_0 1
#endif
// <o> Truth Table <0x00-0xFF>
// <i> Define the value of truth logic according to inputs IN[2:0]
// <id> ccl_arch_truth_0
#ifndef CONF_CCL_TRUTH_0
#define CONF_CCL_TRUTH_0 0x96
#endif
// <o> Input Source Selection 0
// <0x0=> Masked input
// <0x1=> Feedback input source
// <0x2=> Linked LookUpTable input source
// <0x3=> Event input source
// <0x4=> IO pin input source
// <0x5=> AC input source
// <0x6=> TC input source
// <0x7=> Alternative TC input source
// <0x8=> TCC input source
// <0x9=> SERCOM input source
// <id> ccl_arch_insel0_0
#ifndef CONF_CCL_INSEL0_0
#define CONF_CCL_INSEL0_0 0x4
#endif
// <o> Input Source Selection 1
// <0x0=> Masked input
// <0x1=> Feedback input source
// <0x2=> Linked LookUpTable input source
// <0x3=> Event input source
// <0x4=> IO pin input source
// <0x5=> AC input source
// <0x6=> TC input source
// <0x7=> Alternative TC input source
// <0x8=> TCC input source
// <0x9=> SERCOM input source
// <id> ccl_arch_insel1_0
#ifndef CONF_CCL_INSEL1_0
#define CONF_CCL_INSEL1_0 0x4
#endif
// <o> Input Source Selection 2
// <0x0=> Masked input
// <0x1=> Feedback input source
// <0x2=> Linked LookUpTable input source
// <0x3=> Event input source
// <0x4=> IO pin input source
// <0x5=> AC input source
// <0x6=> TC input source
// <0x7=> Alternative TC input source
// <0x8=> TCC input source
// <0x9=> SERCOM input source
// <id> ccl_arch_insel2_0
#ifndef CONF_CCL_INSEL2_0
#define CONF_CCL_INSEL2_0 0x4
#endif
// <q> Edge detector enable
// <id> ccl_arch_edgesel_0
#ifndef CONF_CCL_EDGESEL_0
#define CONF_CCL_EDGESEL_0 0
#endif
// <o> Output Filter
// <0x0=> Disabled
// <0x1=> Synchronizer Enabled
// <0x2=> Filter Enabled
// <id> ccl_arch_filtsel_0
#ifndef CONF_CCL_FILTSEL_0
#define CONF_CCL_FILTSEL_0 0x0
#endif
// <h> Event settings 0
// <q> Event output enable
// <id> ccl_arch_luteo_0
#ifndef CONF_CCL_LUTEO_0
#define CONF_CCL_LUTEO_0 1
#endif
// <q> Event input enable
// <id> ccl_arch_lutei_0
#ifndef CONF_CCL_LUTEI_0
#define CONF_CCL_LUTEI_0 0
#endif
// <q> Event input invert
// <id> ccl_arch_invei_0
#ifndef CONF_CCL_INVEI_0
#define CONF_CCL_INVEI_0 0
#endif
// </h>
// </e>
// <hidden> Persistance settings 0
// <s> Expression Persistance
// <id> ccl_e_persistance_0
#define EXPRESSION_PERSISTANCE_0 ""
// <s> Logic Persistance
// <id> ccl_l_persistance_0
#define LOGIC_PERSISTANCE_0 ""
// </hidden>
// <e> Lookup Table Control 1
// <i> Enable and setup the lookup table module 1
// <id> ccl_arch_lutctrl1
#ifndef CONF_CCL_LUTCTRL_EN_1
#define CONF_CCL_LUTCTRL_EN_1 0
#endif
// <o> Truth Table <0x00-0xFF>
// <i> Define the value of truth logic according to inputs IN[2:0]
// <id> ccl_arch_truth_1
#ifndef CONF_CCL_TRUTH_1
#define CONF_CCL_TRUTH_1 0x0
#endif
// <o> Input Source Selection 0
// <0x0=> Masked input
// <0x1=> Feedback input source
// <0x2=> Linked LookUpTable input source
// <0x3=> Event input source
// <0x4=> IO pin input source
// <0x5=> AC input source
// <0x6=> TC input source
// <0x7=> Alternative TC input source
// <0x8=> TCC input source
// <0x9=> SERCOM input source
// <id> ccl_arch_insel0_1
#ifndef CONF_CCL_INSEL0_1
#define CONF_CCL_INSEL0_1 0x4
#endif
// <o> Input Source Selection 1
// <0x0=> Masked input
// <0x1=> Feedback input source
// <0x2=> Linked LookUpTable input source
// <0x3=> Event input source
// <0x4=> IO pin input source
// <0x5=> AC input source
// <0x6=> TC input source
// <0x7=> Alternative TC input source
// <0x8=> TCC input source
// <0x9=> SERCOM input source
// <id> ccl_arch_insel1_1
#ifndef CONF_CCL_INSEL1_1
#define CONF_CCL_INSEL1_1 0x4
#endif
// <o> Input Source Selection 2
// <0x0=> Masked input
// <0x1=> Feedback input source
// <0x2=> Linked LookUpTable input source
// <0x3=> Event input source
// <0x4=> IO pin input source
// <0x5=> AC input source
// <0x6=> TC input source
// <0x7=> Alternative TC input source
// <0x8=> TCC input source
// <0x9=> SERCOM input source
// <id> ccl_arch_insel2_1
#ifndef CONF_CCL_INSEL2_1
#define CONF_CCL_INSEL2_1 0x4
#endif
// <q> Edge detector enable
// <id> ccl_arch_edgesel_1
#ifndef CONF_CCL_EDGESEL_1
#define CONF_CCL_EDGESEL_1 0
#endif
// <o> Output Filter
// <0x0=> Disabled
// <0x1=> Synchronizer Enabled
// <0x2=> Filter Enabled
// <id> ccl_arch_filtsel_1
#ifndef CONF_CCL_FILTSEL_1
#define CONF_CCL_FILTSEL_1 0x0
#endif
// <h> Event settings 1
// <q> Event output enable
// <id> ccl_arch_luteo_1
#ifndef CONF_CCL_LUTEO_1
#define CONF_CCL_LUTEO_1 0
#endif
// <q> Event input enable
// <id> ccl_arch_lutei_1
#ifndef CONF_CCL_LUTEI_1
#define CONF_CCL_LUTEI_1 0
#endif
// <q> Event input invert
// <id> ccl_arch_invei_1
#ifndef CONF_CCL_INVEI_1
#define CONF_CCL_INVEI_1 0
#endif
// </h>
// </e>
// <hidden> Persistance settings 1
// <s> Expression Persistance
// <id> ccl_e_persistance_1
#define EXPRESSION_PERSISTANCE_1 ""
// <s> Logic Persistance
// <id> ccl_l_persistance_1
#define LOGIC_PERSISTANCE_1 ""
// </hidden>
// <e> Lookup Table Control 2
// <i> Enable and setup the lookup table module 2
// <id> ccl_arch_lutctrl2
#ifndef CONF_CCL_LUTCTRL_EN_2
#define CONF_CCL_LUTCTRL_EN_2 1
#endif
// <o> Truth Table <0x00-0xFF>
// <i> Define the value of truth logic according to inputs IN[2:0]
// <id> ccl_arch_truth_2
#ifndef CONF_CCL_TRUTH_2
#define CONF_CCL_TRUTH_2 0x96
#endif
// <o> Input Source Selection 0
// <0x0=> Masked input
// <0x1=> Feedback input source
// <0x2=> Linked LookUpTable input source
// <0x3=> Event input source
// <0x4=> IO pin input source
// <0x5=> AC input source
// <0x6=> TC input source
// <0x7=> Alternative TC input source
// <0x8=> TCC input source
// <0x9=> SERCOM input source
// <id> ccl_arch_insel0_2
#ifndef CONF_CCL_INSEL0_2
#define CONF_CCL_INSEL0_2 0x4
#endif
// <o> Input Source Selection 1
// <0x0=> Masked input
// <0x1=> Feedback input source
// <0x2=> Linked LookUpTable input source
// <0x3=> Event input source
// <0x4=> IO pin input source
// <0x5=> AC input source
// <0x6=> TC input source
// <0x7=> Alternative TC input source
// <0x8=> TCC input source
// <0x9=> SERCOM input source
// <id> ccl_arch_insel1_2
#ifndef CONF_CCL_INSEL1_2
#define CONF_CCL_INSEL1_2 0x4
#endif
// <o> Input Source Selection 2
// <0x0=> Masked input
// <0x1=> Feedback input source
// <0x2=> Linked LookUpTable input source
// <0x3=> Event input source
// <0x4=> IO pin input source
// <0x5=> AC input source
// <0x6=> TC input source
// <0x7=> Alternative TC input source
// <0x8=> TCC input source
// <0x9=> SERCOM input source
// <id> ccl_arch_insel2_2
#ifndef CONF_CCL_INSEL2_2
#define CONF_CCL_INSEL2_2 0x4
#endif
// <q> Edge detector enable
// <id> ccl_arch_edgesel_2
#ifndef CONF_CCL_EDGESEL_2
#define CONF_CCL_EDGESEL_2 0
#endif
// <o> Output Filter
// <0x0=> Disabled
// <0x1=> Synchronizer Enabled
// <0x2=> Filter Enabled
// <id> ccl_arch_filtsel_2
#ifndef CONF_CCL_FILTSEL_2
#define CONF_CCL_FILTSEL_2 0x0
#endif
// <h> Event settings 2
// <q> Event output enable
// <id> ccl_arch_luteo_2
#ifndef CONF_CCL_LUTEO_2
#define CONF_CCL_LUTEO_2 1
#endif
// <q> Event input enable
// <id> ccl_arch_lutei_2
#ifndef CONF_CCL_LUTEI_2
#define CONF_CCL_LUTEI_2 0
#endif
// <q> Event input invert
// <id> ccl_arch_invei_2
#ifndef CONF_CCL_INVEI_2
#define CONF_CCL_INVEI_2 0
#endif
// </h>
// </e>
// <hidden> Persistance settings 2
// <s> Expression Persistance
// <id> ccl_e_persistance_2
#define EXPRESSION_PERSISTANCE_2 ""
// <s> Logic Persistance
// <id> ccl_l_persistance_2
#define LOGIC_PERSISTANCE_2 ""
// </hidden>
// <e> Lookup Table Control 3
// <i> Enable and setup the lookup table module 3
// <id> ccl_arch_lutctrl3
#ifndef CONF_CCL_LUTCTRL_EN_3
#define CONF_CCL_LUTCTRL_EN_3 0
#endif
// <o> Truth Table <0x00-0xFF>
// <i> Define the value of truth logic according to inputs IN[2:0]
// <id> ccl_arch_truth_3
#ifndef CONF_CCL_TRUTH_3
#define CONF_CCL_TRUTH_3 0x0
#endif
// <o> Input Source Selection 0
// <0x0=> Masked input
// <0x1=> Feedback input source
// <0x2=> Linked LookUpTable input source
// <0x3=> Event input source
// <0x4=> IO pin input source
// <0x5=> AC input source
// <0x6=> TC input source
// <0x7=> Alternative TC input source
// <0x8=> TCC input source
// <0x9=> SERCOM input source
// <id> ccl_arch_insel0_3
#ifndef CONF_CCL_INSEL0_3
#define CONF_CCL_INSEL0_3 0x4
#endif
// <o> Input Source Selection 1
// <0x0=> Masked input
// <0x1=> Feedback input source
// <0x2=> Linked LookUpTable input source
// <0x3=> Event input source
// <0x4=> IO pin input source
// <0x5=> AC input source
// <0x6=> TC input source
// <0x7=> Alternative TC input source
// <0x8=> TCC input source
// <0x9=> SERCOM input source
// <id> ccl_arch_insel1_3
#ifndef CONF_CCL_INSEL1_3
#define CONF_CCL_INSEL1_3 0x4
#endif
// <o> Input Source Selection 2
// <0x0=> Masked input
// <0x1=> Feedback input source
// <0x2=> Linked LookUpTable input source
// <0x3=> Event input source
// <0x4=> IO pin input source
// <0x5=> AC input source
// <0x6=> TC input source
// <0x7=> Alternative TC input source
// <0x8=> TCC input source
// <0x9=> SERCOM input source
// <id> ccl_arch_insel2_3
#ifndef CONF_CCL_INSEL2_3
#define CONF_CCL_INSEL2_3 0x4
#endif
// <q> Edge detector enable
// <id> ccl_arch_edgesel_3
#ifndef CONF_CCL_EDGESEL_3
#define CONF_CCL_EDGESEL_3 0
#endif
// <o> Output Filter
// <0x0=> Disabled
// <0x1=> Synchronizer Enabled
// <0x2=> Filter Enabled
// <id> ccl_arch_filtsel_3
#ifndef CONF_CCL_FILTSEL_3
#define CONF_CCL_FILTSEL_3 0x0
#endif
// <h> Event settings 3
// <q> Event output enable
// <id> ccl_arch_luteo_3
#ifndef CONF_CCL_LUTEO_3
#define CONF_CCL_LUTEO_3 0
#endif
// <q> Event input enable
// <id> ccl_arch_lutei_3
#ifndef CONF_CCL_LUTEI_3
#define CONF_CCL_LUTEI_3 0
#endif
// <q> Event input invert
// <id> ccl_arch_invei_3
#ifndef CONF_CCL_INVEI_3
#define CONF_CCL_INVEI_3 0
#endif
// </h>
// </e>
// <hidden> Persistance settings 3
// <s> Expression Persistance
// <id> ccl_e_persistance_3
#define EXPRESSION_PERSISTANCE_3 ""
// <s> Logic Persistance
// <id> ccl_l_persistance_3
#define LOGIC_PERSISTANCE_3 ""
// </hidden>
// <e> Advanced configurations
// <id> ccl_arch_advanced_settings
#ifndef CONF_CCL_ADVANCED
#define CONF_CCL_ADVANCED 0
#endif
// <q> Run in Standby
// <id> ccl_arch_runstdby
#ifndef CONF_CCL_RUNSTDBY
#define CONF_CCL_RUNSTDBY 0
#endif
// </e>
// <<< end of configuration section >>>
#endif // HPL_CCL_CONFIG_H

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/* Auto-generated config file hpl_cmcc_config.h */
#ifndef HPL_CMCC_CONFIG_H
#define HPL_CMCC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Configuration
// <q> Cache enable
//<i> Defines the cache should be enabled or not.
// <id> cmcc_enable
#ifndef CONF_CMCC_ENABLE
#define CONF_CMCC_ENABLE 0x0
#endif
// <o> Cache Size
//<i> Defines the cache memory size to be configured.
// <0x0=>1 KB
// <0x1=>2 KB
// <0x2=>4 KB
// <id> cache_size
#ifndef CONF_CMCC_CACHE_SIZE
#define CONF_CMCC_CACHE_SIZE 0x2
#endif
// <e> Advanced Configuration
// <id> cmcc_advanced_configuration
// <q> Data cache disable
//<i> Defines the data cache should be disabled or not.
// <id> cmcc_data_cache_disable
#ifndef CONF_CMCC_DATA_CACHE_DISABLE
#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
#endif
// <q> Instruction cache disable
//<i> Defines the Instruction cache should be disabled or not.
// <id> cmcc_inst_cache_disable
#ifndef CONF_CMCC_INST_CACHE_DISABLE
#define CONF_CMCC_INST_CACHE_DISABLE 0x0
#endif
// <q> Clock Gating disable
//<i> Defines the clock gating should be disabled or not.
// <id> cmcc_clock_gating_disable
#ifndef CONF_CMCC_CLK_GATING_DISABLE
#define CONF_CMCC_CLK_GATING_DISABLE 0x0
#endif
// </e>
// </h>
// <<< end of configuration section >>>
#endif // HPL_CMCC_CONFIG_H

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/* Auto-generated config file hpl_eic_config.h */
#ifndef HPL_EIC_CONFIG_H
#define HPL_EIC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Settings
// <o> Clock Selection
// <i> Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or
// <i> either by CLK_ULP32K when power consumption is the priority.
// <0x0=> Clocked by GCLK
// <0x1=> Clocked by ULPOSC32K
// <id> eic_arch_cksel
#ifndef CONF_EIC_CKSEL
#define CONF_EIC_CKSEL 0
#endif
// <o> Pin Sampler frequency selection
// <i> Indicates the sampling rate of the EXTINT pin.
// <0x0=> The sampling rate is EIC clock
// <0x1=> The sampling rate is the prescaled clock
// <id> eic_arch_tickon
#ifndef CONF_EIC_TICKON
#define CONF_EIC_TICKON 0
#endif
// </h>
// <e> Non-Maskable Interrupt Control
// <id> eic_arch_nmi_ctrl
#ifndef CONF_EIC_ENABLE_NMI_CTRL
#define CONF_EIC_ENABLE_NMI_CTRL 0
#endif
// <q> Non-Maskable Interrupt Filter Enable
// <i> Indicates whether the mon-maskable interrupt filter is enabled or not
// <id> eic_arch_nmifilten
#ifndef CONF_EIC_NMIFILTEN
#define CONF_EIC_NMIFILTEN 0
#endif
// <y> Non-Maskable Interrupt Sense
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines non-maskable interrupt sense
// <id> eic_arch_nmisense
#ifndef CONF_EIC_NMISENSE
#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> Asynchronous Edge Detection Mode
// <i> Indicates the interrupt detection mode operated synchronously or asynchronousl
// <id> eic_arch_nmiasynch
#ifndef CONF_EIC_NMIASYNCH
#define CONF_EIC_NMIASYNCH 0
#endif
// </e>
// <e> Interrupt 0 Settings
// <id> eic_arch_enable_irq_setting0
#ifndef CONF_EIC_ENABLE_IRQ_SETTING0
#define CONF_EIC_ENABLE_IRQ_SETTING0 0
#endif
// <q> External Interrupt 0 Filter Enable
// <i> Indicates whether the external interrupt 0 filter is enabled or not
// <id> eic_arch_filten0
#ifndef CONF_EIC_FILTEN0
#define CONF_EIC_FILTEN0 0
#endif
// <q> External Interrupt 0 Debounce Enable
// <i> Indicates whether the external interrupt 0 debounce is enabled or not
// <id> eic_arch_debounce_enable0
#ifndef CONF_EIC_DEBOUNCE_ENABLE0
#define CONF_EIC_DEBOUNCE_ENABLE0 0
#endif
// <q> External Interrupt 0 Event Output Enable
// <i> Indicates whether the external interrupt 0 event output is enabled or not
// <id> eic_arch_extinteo0
#ifndef CONF_EIC_EXTINTEO0
#define CONF_EIC_EXTINTEO0 0
#endif
// <y> Input 0 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense0
#ifndef CONF_EIC_SENSE0
#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 0 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch0
#ifndef CONF_EIC_ASYNCH0
#define CONF_EIC_ASYNCH0 0
#endif
// </e>
// <e> Interrupt 1 Settings
// <id> eic_arch_enable_irq_setting1
#ifndef CONF_EIC_ENABLE_IRQ_SETTING1
#define CONF_EIC_ENABLE_IRQ_SETTING1 0
#endif
// <q> External Interrupt 1 Filter Enable
// <i> Indicates whether the external interrupt 1 filter is enabled or not
// <id> eic_arch_filten1
#ifndef CONF_EIC_FILTEN1
#define CONF_EIC_FILTEN1 0
#endif
// <q> External Interrupt 1 Debounce Enable
// <i> Indicates whether the external interrupt 1 debounce is enabled or not
// <id> eic_arch_debounce_enable1
#ifndef CONF_EIC_DEBOUNCE_ENABLE1
#define CONF_EIC_DEBOUNCE_ENABLE1 0
#endif
// <q> External Interrupt 1 Event Output Enable
// <i> Indicates whether the external interrupt 1 event output is enabled or not
// <id> eic_arch_extinteo1
#ifndef CONF_EIC_EXTINTEO1
#define CONF_EIC_EXTINTEO1 0
#endif
// <y> Input 1 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense1
#ifndef CONF_EIC_SENSE1
#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 1 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch1
#ifndef CONF_EIC_ASYNCH1
#define CONF_EIC_ASYNCH1 0
#endif
// </e>
// <e> Interrupt 2 Settings
// <id> eic_arch_enable_irq_setting2
#ifndef CONF_EIC_ENABLE_IRQ_SETTING2
#define CONF_EIC_ENABLE_IRQ_SETTING2 0
#endif
// <q> External Interrupt 2 Filter Enable
// <i> Indicates whether the external interrupt 2 filter is enabled or not
// <id> eic_arch_filten2
#ifndef CONF_EIC_FILTEN2
#define CONF_EIC_FILTEN2 0
#endif
// <q> External Interrupt 2 Debounce Enable
// <i> Indicates whether the external interrupt 2 debounce is enabled or not
// <id> eic_arch_debounce_enable2
#ifndef CONF_EIC_DEBOUNCE_ENABLE2
#define CONF_EIC_DEBOUNCE_ENABLE2 0
#endif
// <q> External Interrupt 2 Event Output Enable
// <i> Indicates whether the external interrupt 2 event output is enabled or not
// <id> eic_arch_extinteo2
#ifndef CONF_EIC_EXTINTEO2
#define CONF_EIC_EXTINTEO2 0
#endif
// <y> Input 2 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense2
#ifndef CONF_EIC_SENSE2
#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 2 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch2
#ifndef CONF_EIC_ASYNCH2
#define CONF_EIC_ASYNCH2 0
#endif
// </e>
// <e> Interrupt 3 Settings
// <id> eic_arch_enable_irq_setting3
#ifndef CONF_EIC_ENABLE_IRQ_SETTING3
#define CONF_EIC_ENABLE_IRQ_SETTING3 0
#endif
// <q> External Interrupt 3 Filter Enable
// <i> Indicates whether the external interrupt 3 filter is enabled or not
// <id> eic_arch_filten3
#ifndef CONF_EIC_FILTEN3
#define CONF_EIC_FILTEN3 0
#endif
// <q> External Interrupt 3 Debounce Enable
// <i> Indicates whether the external interrupt 3 debounce is enabled or not
// <id> eic_arch_debounce_enable3
#ifndef CONF_EIC_DEBOUNCE_ENABLE3
#define CONF_EIC_DEBOUNCE_ENABLE3 0
#endif
// <q> External Interrupt 3 Event Output Enable
// <i> Indicates whether the external interrupt 3 event output is enabled or not
// <id> eic_arch_extinteo3
#ifndef CONF_EIC_EXTINTEO3
#define CONF_EIC_EXTINTEO3 0
#endif
// <y> Input 3 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense3
#ifndef CONF_EIC_SENSE3
#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 3 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch3
#ifndef CONF_EIC_ASYNCH3
#define CONF_EIC_ASYNCH3 0
#endif
// </e>
// <e> Interrupt 4 Settings
// <id> eic_arch_enable_irq_setting4
#ifndef CONF_EIC_ENABLE_IRQ_SETTING4
#define CONF_EIC_ENABLE_IRQ_SETTING4 0
#endif
// <q> External Interrupt 4 Filter Enable
// <i> Indicates whether the external interrupt 4 filter is enabled or not
// <id> eic_arch_filten4
#ifndef CONF_EIC_FILTEN4
#define CONF_EIC_FILTEN4 0
#endif
// <q> External Interrupt 4 Debounce Enable
// <i> Indicates whether the external interrupt 4 debounce is enabled or not
// <id> eic_arch_debounce_enable4
#ifndef CONF_EIC_DEBOUNCE_ENABLE4
#define CONF_EIC_DEBOUNCE_ENABLE4 0
#endif
// <q> External Interrupt 4 Event Output Enable
// <i> Indicates whether the external interrupt 4 event output is enabled or not
// <id> eic_arch_extinteo4
#ifndef CONF_EIC_EXTINTEO4
#define CONF_EIC_EXTINTEO4 0
#endif
// <y> Input 4 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense4
#ifndef CONF_EIC_SENSE4
#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 4 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch4
#ifndef CONF_EIC_ASYNCH4
#define CONF_EIC_ASYNCH4 0
#endif
// </e>
// <e> Interrupt 5 Settings
// <id> eic_arch_enable_irq_setting5
#ifndef CONF_EIC_ENABLE_IRQ_SETTING5
#define CONF_EIC_ENABLE_IRQ_SETTING5 0
#endif
// <q> External Interrupt 5 Filter Enable
// <i> Indicates whether the external interrupt 5 filter is enabled or not
// <id> eic_arch_filten5
#ifndef CONF_EIC_FILTEN5
#define CONF_EIC_FILTEN5 0
#endif
// <q> External Interrupt 5 Debounce Enable
// <i> Indicates whether the external interrupt 5 debounce is enabled or not
// <id> eic_arch_debounce_enable5
#ifndef CONF_EIC_DEBOUNCE_ENABLE5
#define CONF_EIC_DEBOUNCE_ENABLE5 0
#endif
// <q> External Interrupt 5 Event Output Enable
// <i> Indicates whether the external interrupt 5 event output is enabled or not
// <id> eic_arch_extinteo5
#ifndef CONF_EIC_EXTINTEO5
#define CONF_EIC_EXTINTEO5 0
#endif
// <y> Input 5 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense5
#ifndef CONF_EIC_SENSE5
#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 5 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch5
#ifndef CONF_EIC_ASYNCH5
#define CONF_EIC_ASYNCH5 0
#endif
// </e>
// <e> Interrupt 6 Settings
// <id> eic_arch_enable_irq_setting6
#ifndef CONF_EIC_ENABLE_IRQ_SETTING6
#define CONF_EIC_ENABLE_IRQ_SETTING6 0
#endif
// <q> External Interrupt 6 Filter Enable
// <i> Indicates whether the external interrupt 6 filter is enabled or not
// <id> eic_arch_filten6
#ifndef CONF_EIC_FILTEN6
#define CONF_EIC_FILTEN6 0
#endif
// <q> External Interrupt 6 Debounce Enable
// <i> Indicates whether the external interrupt 6 debounce is enabled or not
// <id> eic_arch_debounce_enable6
#ifndef CONF_EIC_DEBOUNCE_ENABLE6
#define CONF_EIC_DEBOUNCE_ENABLE6 0
#endif
// <q> External Interrupt 6 Event Output Enable
// <i> Indicates whether the external interrupt 6 event output is enabled or not
// <id> eic_arch_extinteo6
#ifndef CONF_EIC_EXTINTEO6
#define CONF_EIC_EXTINTEO6 0
#endif
// <y> Input 6 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense6
#ifndef CONF_EIC_SENSE6
#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 6 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch6
#ifndef CONF_EIC_ASYNCH6
#define CONF_EIC_ASYNCH6 0
#endif
// </e>
// <e> Interrupt 7 Settings
// <id> eic_arch_enable_irq_setting7
#ifndef CONF_EIC_ENABLE_IRQ_SETTING7
#define CONF_EIC_ENABLE_IRQ_SETTING7 0
#endif
// <q> External Interrupt 7 Filter Enable
// <i> Indicates whether the external interrupt 7 filter is enabled or not
// <id> eic_arch_filten7
#ifndef CONF_EIC_FILTEN7
#define CONF_EIC_FILTEN7 0
#endif
// <q> External Interrupt 7 Debounce Enable
// <i> Indicates whether the external interrupt 7 debounce is enabled or not
// <id> eic_arch_debounce_enable7
#ifndef CONF_EIC_DEBOUNCE_ENABLE7
#define CONF_EIC_DEBOUNCE_ENABLE7 0
#endif
// <q> External Interrupt 7 Event Output Enable
// <i> Indicates whether the external interrupt 7 event output is enabled or not
// <id> eic_arch_extinteo7
#ifndef CONF_EIC_EXTINTEO7
#define CONF_EIC_EXTINTEO7 0
#endif
// <y> Input 7 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense7
#ifndef CONF_EIC_SENSE7
#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 7 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch7
#ifndef CONF_EIC_ASYNCH7
#define CONF_EIC_ASYNCH7 0
#endif
// </e>
// <e> Interrupt 8 Settings
// <id> eic_arch_enable_irq_setting8
#ifndef CONF_EIC_ENABLE_IRQ_SETTING8
#define CONF_EIC_ENABLE_IRQ_SETTING8 0
#endif
// <q> External Interrupt 8 Filter Enable
// <i> Indicates whether the external interrupt 8 filter is enabled or not
// <id> eic_arch_filten8
#ifndef CONF_EIC_FILTEN8
#define CONF_EIC_FILTEN8 0
#endif
// <q> External Interrupt 8 Debounce Enable
// <i> Indicates whether the external interrupt 8 debounce is enabled or not
// <id> eic_arch_debounce_enable8
#ifndef CONF_EIC_DEBOUNCE_ENABLE8
#define CONF_EIC_DEBOUNCE_ENABLE8 0
#endif
// <q> External Interrupt 8 Event Output Enable
// <i> Indicates whether the external interrupt 8 event output is enabled or not
// <id> eic_arch_extinteo8
#ifndef CONF_EIC_EXTINTEO8
#define CONF_EIC_EXTINTEO8 0
#endif
// <y> Input 8 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense8
#ifndef CONF_EIC_SENSE8
#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 8 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch8
#ifndef CONF_EIC_ASYNCH8
#define CONF_EIC_ASYNCH8 0
#endif
// </e>
// <e> Interrupt 9 Settings
// <id> eic_arch_enable_irq_setting9
#ifndef CONF_EIC_ENABLE_IRQ_SETTING9
#define CONF_EIC_ENABLE_IRQ_SETTING9 0
#endif
// <q> External Interrupt 9 Filter Enable
// <i> Indicates whether the external interrupt 9 filter is enabled or not
// <id> eic_arch_filten9
#ifndef CONF_EIC_FILTEN9
#define CONF_EIC_FILTEN9 0
#endif
// <q> External Interrupt 9 Debounce Enable
// <i> Indicates whether the external interrupt 9 debounce is enabled or not
// <id> eic_arch_debounce_enable9
#ifndef CONF_EIC_DEBOUNCE_ENABLE9
#define CONF_EIC_DEBOUNCE_ENABLE9 0
#endif
// <q> External Interrupt 9 Event Output Enable
// <i> Indicates whether the external interrupt 9 event output is enabled or not
// <id> eic_arch_extinteo9
#ifndef CONF_EIC_EXTINTEO9
#define CONF_EIC_EXTINTEO9 0
#endif
// <y> Input 9 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense9
#ifndef CONF_EIC_SENSE9
#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 9 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch9
#ifndef CONF_EIC_ASYNCH9
#define CONF_EIC_ASYNCH9 0
#endif
// </e>
// <e> Interrupt 10 Settings
// <id> eic_arch_enable_irq_setting10
#ifndef CONF_EIC_ENABLE_IRQ_SETTING10
#define CONF_EIC_ENABLE_IRQ_SETTING10 0
#endif
// <q> External Interrupt 10 Filter Enable
// <i> Indicates whether the external interrupt 10 filter is enabled or not
// <id> eic_arch_filten10
#ifndef CONF_EIC_FILTEN10
#define CONF_EIC_FILTEN10 0
#endif
// <q> External Interrupt 10 Debounce Enable
// <i> Indicates whether the external interrupt 10 debounce is enabled or not
// <id> eic_arch_debounce_enable10
#ifndef CONF_EIC_DEBOUNCE_ENABLE10
#define CONF_EIC_DEBOUNCE_ENABLE10 0
#endif
// <q> External Interrupt 10 Event Output Enable
// <i> Indicates whether the external interrupt 10 event output is enabled or not
// <id> eic_arch_extinteo10
#ifndef CONF_EIC_EXTINTEO10
#define CONF_EIC_EXTINTEO10 0
#endif
// <y> Input 10 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense10
#ifndef CONF_EIC_SENSE10
#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 10 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch10
#ifndef CONF_EIC_ASYNCH10
#define CONF_EIC_ASYNCH10 0
#endif
// </e>
// <e> Interrupt 11 Settings
// <id> eic_arch_enable_irq_setting11
#ifndef CONF_EIC_ENABLE_IRQ_SETTING11
#define CONF_EIC_ENABLE_IRQ_SETTING11 0
#endif
// <q> External Interrupt 11 Filter Enable
// <i> Indicates whether the external interrupt 11 filter is enabled or not
// <id> eic_arch_filten11
#ifndef CONF_EIC_FILTEN11
#define CONF_EIC_FILTEN11 0
#endif
// <q> External Interrupt 11 Debounce Enable
// <i> Indicates whether the external interrupt 11 debounce is enabled or not
// <id> eic_arch_debounce_enable11
#ifndef CONF_EIC_DEBOUNCE_ENABLE11
#define CONF_EIC_DEBOUNCE_ENABLE11 0
#endif
// <q> External Interrupt 11 Event Output Enable
// <i> Indicates whether the external interrupt 11 event output is enabled or not
// <id> eic_arch_extinteo11
#ifndef CONF_EIC_EXTINTEO11
#define CONF_EIC_EXTINTEO11 0
#endif
// <y> Input 11 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense11
#ifndef CONF_EIC_SENSE11
#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 11 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch11
#ifndef CONF_EIC_ASYNCH11
#define CONF_EIC_ASYNCH11 0
#endif
// </e>
// <e> Interrupt 12 Settings
// <id> eic_arch_enable_irq_setting12
#ifndef CONF_EIC_ENABLE_IRQ_SETTING12
#define CONF_EIC_ENABLE_IRQ_SETTING12 0
#endif
// <q> External Interrupt 12 Filter Enable
// <i> Indicates whether the external interrupt 12 filter is enabled or not
// <id> eic_arch_filten12
#ifndef CONF_EIC_FILTEN12
#define CONF_EIC_FILTEN12 0
#endif
// <q> External Interrupt 12 Debounce Enable
// <i> Indicates whether the external interrupt 12 debounce is enabled or not
// <id> eic_arch_debounce_enable12
#ifndef CONF_EIC_DEBOUNCE_ENABLE12
#define CONF_EIC_DEBOUNCE_ENABLE12 0
#endif
// <q> External Interrupt 12 Event Output Enable
// <i> Indicates whether the external interrupt 12 event output is enabled or not
// <id> eic_arch_extinteo12
#ifndef CONF_EIC_EXTINTEO12
#define CONF_EIC_EXTINTEO12 0
#endif
// <y> Input 12 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense12
#ifndef CONF_EIC_SENSE12
#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 12 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch12
#ifndef CONF_EIC_ASYNCH12
#define CONF_EIC_ASYNCH12 0
#endif
// </e>
// <e> Interrupt 13 Settings
// <id> eic_arch_enable_irq_setting13
#ifndef CONF_EIC_ENABLE_IRQ_SETTING13
#define CONF_EIC_ENABLE_IRQ_SETTING13 0
#endif
// <q> External Interrupt 13 Filter Enable
// <i> Indicates whether the external interrupt 13 filter is enabled or not
// <id> eic_arch_filten13
#ifndef CONF_EIC_FILTEN13
#define CONF_EIC_FILTEN13 0
#endif
// <q> External Interrupt 13 Debounce Enable
// <i> Indicates whether the external interrupt 13 debounce is enabled or not
// <id> eic_arch_debounce_enable13
#ifndef CONF_EIC_DEBOUNCE_ENABLE13
#define CONF_EIC_DEBOUNCE_ENABLE13 0
#endif
// <q> External Interrupt 13 Event Output Enable
// <i> Indicates whether the external interrupt 13 event output is enabled or not
// <id> eic_arch_extinteo13
#ifndef CONF_EIC_EXTINTEO13
#define CONF_EIC_EXTINTEO13 0
#endif
// <y> Input 13 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense13
#ifndef CONF_EIC_SENSE13
#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 13 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch13
#ifndef CONF_EIC_ASYNCH13
#define CONF_EIC_ASYNCH13 0
#endif
// </e>
// <e> Interrupt 14 Settings
// <id> eic_arch_enable_irq_setting14
#ifndef CONF_EIC_ENABLE_IRQ_SETTING14
#define CONF_EIC_ENABLE_IRQ_SETTING14 1
#endif
// <q> External Interrupt 14 Filter Enable
// <i> Indicates whether the external interrupt 14 filter is enabled or not
// <id> eic_arch_filten14
#ifndef CONF_EIC_FILTEN14
#define CONF_EIC_FILTEN14 0
#endif
// <q> External Interrupt 14 Debounce Enable
// <i> Indicates whether the external interrupt 14 debounce is enabled or not
// <id> eic_arch_debounce_enable14
#ifndef CONF_EIC_DEBOUNCE_ENABLE14
#define CONF_EIC_DEBOUNCE_ENABLE14 0
#endif
// <q> External Interrupt 14 Event Output Enable
// <i> Indicates whether the external interrupt 14 event output is enabled or not
// <id> eic_arch_extinteo14
#ifndef CONF_EIC_EXTINTEO14
#define CONF_EIC_EXTINTEO14 0
#endif
// <y> Input 14 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense14
#ifndef CONF_EIC_SENSE14
#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_BOTH_Val
#endif
// <q> External Interrupt 14 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch14
#ifndef CONF_EIC_ASYNCH14
#define CONF_EIC_ASYNCH14 1
#endif
// </e>
// <e> Interrupt 15 Settings
// <id> eic_arch_enable_irq_setting15
#ifndef CONF_EIC_ENABLE_IRQ_SETTING15
#define CONF_EIC_ENABLE_IRQ_SETTING15 1
#endif
// <q> External Interrupt 15 Filter Enable
// <i> Indicates whether the external interrupt 15 filter is enabled or not
// <id> eic_arch_filten15
#ifndef CONF_EIC_FILTEN15
#define CONF_EIC_FILTEN15 0
#endif
// <q> External Interrupt 15 Debounce Enable
// <i> Indicates whether the external interrupt 15 debounce is enabled or not
// <id> eic_arch_debounce_enable15
#ifndef CONF_EIC_DEBOUNCE_ENABLE15
#define CONF_EIC_DEBOUNCE_ENABLE15 0
#endif
// <q> External Interrupt 15 Event Output Enable
// <i> Indicates whether the external interrupt 15 event output is enabled or not
// <id> eic_arch_extinteo15
#ifndef CONF_EIC_EXTINTEO15
#define CONF_EIC_EXTINTEO15 0
#endif
// <y> Input 15 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense15
#ifndef CONF_EIC_SENSE15
#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_BOTH_Val
#endif
// <q> External Interrupt 15 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch15
#ifndef CONF_EIC_ASYNCH15
#define CONF_EIC_ASYNCH15 1
#endif
// </e>
// <h> Debouncer 0 Settings
// <o> Debouncer Frequency Selection
// <0x0=>Divided by 2
// <0x1=>Divided by 4
// <0x2=>Divided by 8
// <0x3=>Divided by 16
// <0x4=>Divided by 32
// <0x5=>Divided by 64
// <0x6=>Divided by 128
// <0x7=>Divided by 256
// <i> Select the debouncer low frequency clock for pins
// <i> EXTINT[7:0].
// <id> eic_arch_prescaler0
#ifndef CONF_EIC_DPRESCALER0
#define CONF_EIC_DPRESCALER0 EIC_DPRESCALER_PRESCALER0(0x0)
#endif
// <o> Low frequency samples
// <0x0=>3
// <0x1=>7
// <i> Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from
// <i> current pin state to next pin state in synchronous debouncing mode.
// <id> eic_arch_states0
#ifndef CONF_EIC_STATES0
#define CONF_EIC_STATES0 0x0
#endif
// </h>
// <h> Debouncer 1 Settings
// <o> Debouncer Frequency Selection
// <0x0=>Divided by 2
// <0x1=>Divided by 4
// <0x2=>Divided by 8
// <0x3=>Divided by 16
// <0x4=>Divided by 32
// <0x5=>Divided by 64
// <0x6=>Divided by 128
// <0x7=>Divided by 256
// <i> Select the debouncer low frequency clock for pins
// <i> EXTINT[15:8].
// <id> eic_arch_prescaler1
#ifndef CONF_EIC_DPRESCALER1
#define CONF_EIC_DPRESCALER1 EIC_DPRESCALER_PRESCALER1(0x0)
#endif
// <o> Low frequency samples
// <0x0=>3
// <0x1=>7
// <i> Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from
// <i> current pin state to next pin state in synchronous debouncing mode.
// <id> eic_arch_states1
#ifndef CONF_EIC_STATES1
#define CONF_EIC_STATES1 0x0
#endif
// </h>
#define CONFIG_EIC_EXTINT_MAP {7, PIN_PA07}, {14, PIN_PB30}, {15, PIN_PB31},
// <<< end of configuration section >>>
#endif // HPL_EIC_CONFIG_H

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/* Auto-generated config file hpl_gclk_config.h */
#ifndef HPL_GCLK_CONFIG_H
#define HPL_GCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> Generic clock generator 0 configuration
// <i> Indicates whether generic clock 0 configuration is enabled or not
// <id> enable_gclk_gen_0
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
#define CONF_GCLK_GENERATOR_0_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 0 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 0
// <id> gclk_gen_0_oscillator
#ifndef CONF_GCLK_GEN_0_SOURCE
#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_0_runstdby
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
#define CONF_GCLK_GEN_0_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_0_div_sel
#ifndef CONF_GCLK_GEN_0_DIVSEL
#define CONF_GCLK_GEN_0_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_0_oe
#ifndef CONF_GCLK_GEN_0_OE
#define CONF_GCLK_GEN_0_OE 1
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_0_oov
#ifndef CONF_GCLK_GEN_0_OOV
#define CONF_GCLK_GEN_0_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_0_idc
#ifndef CONF_GCLK_GEN_0_IDC
#define CONF_GCLK_GEN_0_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_0_enable
#ifndef CONF_GCLK_GEN_0_GENEN
#define CONF_GCLK_GEN_0_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 0 division <0x0000-0xFFFF>
// <id> gclk_gen_0_div
#ifndef CONF_GCLK_GEN_0_DIV
#define CONF_GCLK_GEN_0_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 1 configuration
// <i> Indicates whether generic clock 1 configuration is enabled or not
// <id> enable_gclk_gen_1
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
#define CONF_GCLK_GENERATOR_1_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 1 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 1
// <id> gclk_gen_1_oscillator
#ifndef CONF_GCLK_GEN_1_SOURCE
#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_1_runstdby
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
#define CONF_GCLK_GEN_1_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_1_div_sel
#ifndef CONF_GCLK_GEN_1_DIVSEL
#define CONF_GCLK_GEN_1_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_1_oe
#ifndef CONF_GCLK_GEN_1_OE
#define CONF_GCLK_GEN_1_OE 1
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_1_oov
#ifndef CONF_GCLK_GEN_1_OOV
#define CONF_GCLK_GEN_1_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_1_idc
#ifndef CONF_GCLK_GEN_1_IDC
#define CONF_GCLK_GEN_1_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_1_enable
#ifndef CONF_GCLK_GEN_1_GENEN
#define CONF_GCLK_GEN_1_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 1 division <0x0000-0xFFFF>
// <id> gclk_gen_1_div
#ifndef CONF_GCLK_GEN_1_DIV
#define CONF_GCLK_GEN_1_DIV 24
#endif
// </h>
// </e>
// <e> Generic clock generator 2 configuration
// <i> Indicates whether generic clock 2 configuration is enabled or not
// <id> enable_gclk_gen_2
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
#define CONF_GCLK_GENERATOR_2_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 2 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 2
// <id> gclk_gen_2_oscillator
#ifndef CONF_GCLK_GEN_2_SOURCE
#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSCULP32K
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_2_runstdby
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
#define CONF_GCLK_GEN_2_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_2_div_sel
#ifndef CONF_GCLK_GEN_2_DIVSEL
#define CONF_GCLK_GEN_2_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_2_oe
#ifndef CONF_GCLK_GEN_2_OE
#define CONF_GCLK_GEN_2_OE 1
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_2_oov
#ifndef CONF_GCLK_GEN_2_OOV
#define CONF_GCLK_GEN_2_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_2_idc
#ifndef CONF_GCLK_GEN_2_IDC
#define CONF_GCLK_GEN_2_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_2_enable
#ifndef CONF_GCLK_GEN_2_GENEN
#define CONF_GCLK_GEN_2_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 2 division <0x0000-0xFFFF>
// <id> gclk_gen_2_div
#ifndef CONF_GCLK_GEN_2_DIV
#define CONF_GCLK_GEN_2_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 3 configuration
// <i> Indicates whether generic clock 3 configuration is enabled or not
// <id> enable_gclk_gen_3
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
#define CONF_GCLK_GENERATOR_3_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 3 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 3
// <id> gclk_gen_3_oscillator
#ifndef CONF_GCLK_GEN_3_SOURCE
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_3_runstdby
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
#define CONF_GCLK_GEN_3_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_3_div_sel
#ifndef CONF_GCLK_GEN_3_DIVSEL
#define CONF_GCLK_GEN_3_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_3_oe
#ifndef CONF_GCLK_GEN_3_OE
#define CONF_GCLK_GEN_3_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_3_oov
#ifndef CONF_GCLK_GEN_3_OOV
#define CONF_GCLK_GEN_3_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_3_idc
#ifndef CONF_GCLK_GEN_3_IDC
#define CONF_GCLK_GEN_3_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_3_enable
#ifndef CONF_GCLK_GEN_3_GENEN
#define CONF_GCLK_GEN_3_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 3 division <0x0000-0xFFFF>
// <id> gclk_gen_3_div
#ifndef CONF_GCLK_GEN_3_DIV
#define CONF_GCLK_GEN_3_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 4 configuration
// <i> Indicates whether generic clock 4 configuration is enabled or not
// <id> enable_gclk_gen_4
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
#define CONF_GCLK_GENERATOR_4_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 4 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 4
// <id> gclk_gen_4_oscillator
#ifndef CONF_GCLK_GEN_4_SOURCE
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_4_runstdby
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
#define CONF_GCLK_GEN_4_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_4_div_sel
#ifndef CONF_GCLK_GEN_4_DIVSEL
#define CONF_GCLK_GEN_4_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_4_oe
#ifndef CONF_GCLK_GEN_4_OE
#define CONF_GCLK_GEN_4_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_4_oov
#ifndef CONF_GCLK_GEN_4_OOV
#define CONF_GCLK_GEN_4_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_4_idc
#ifndef CONF_GCLK_GEN_4_IDC
#define CONF_GCLK_GEN_4_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_4_enable
#ifndef CONF_GCLK_GEN_4_GENEN
#define CONF_GCLK_GEN_4_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
// <id> gclk_gen_4_div
#ifndef CONF_GCLK_GEN_4_DIV
#define CONF_GCLK_GEN_4_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 5 configuration
// <i> Indicates whether generic clock 5 configuration is enabled or not
// <id> enable_gclk_gen_5
#ifndef CONF_GCLK_GENERATOR_5_CONFIG
#define CONF_GCLK_GENERATOR_5_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 5 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 5
// <id> gclk_gen_5_oscillator
#ifndef CONF_GCLK_GEN_5_SOURCE
#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_5_runstdby
#ifndef CONF_GCLK_GEN_5_RUNSTDBY
#define CONF_GCLK_GEN_5_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_5_div_sel
#ifndef CONF_GCLK_GEN_5_DIVSEL
#define CONF_GCLK_GEN_5_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_5_oe
#ifndef CONF_GCLK_GEN_5_OE
#define CONF_GCLK_GEN_5_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_5_oov
#ifndef CONF_GCLK_GEN_5_OOV
#define CONF_GCLK_GEN_5_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_5_idc
#ifndef CONF_GCLK_GEN_5_IDC
#define CONF_GCLK_GEN_5_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_5_enable
#ifndef CONF_GCLK_GEN_5_GENEN
#define CONF_GCLK_GEN_5_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 5 division <0x0000-0xFFFF>
// <id> gclk_gen_5_div
#ifndef CONF_GCLK_GEN_5_DIV
#define CONF_GCLK_GEN_5_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 6 configuration
// <i> Indicates whether generic clock 6 configuration is enabled or not
// <id> enable_gclk_gen_6
#ifndef CONF_GCLK_GENERATOR_6_CONFIG
#define CONF_GCLK_GENERATOR_6_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 6 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 6
// <id> gclk_gen_6_oscillator
#ifndef CONF_GCLK_GEN_6_SOURCE
#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_6_runstdby
#ifndef CONF_GCLK_GEN_6_RUNSTDBY
#define CONF_GCLK_GEN_6_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_6_div_sel
#ifndef CONF_GCLK_GEN_6_DIVSEL
#define CONF_GCLK_GEN_6_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_6_oe
#ifndef CONF_GCLK_GEN_6_OE
#define CONF_GCLK_GEN_6_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_6_oov
#ifndef CONF_GCLK_GEN_6_OOV
#define CONF_GCLK_GEN_6_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_6_idc
#ifndef CONF_GCLK_GEN_6_IDC
#define CONF_GCLK_GEN_6_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_6_enable
#ifndef CONF_GCLK_GEN_6_GENEN
#define CONF_GCLK_GEN_6_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 6 division <0x0000-0xFFFF>
// <id> gclk_gen_6_div
#ifndef CONF_GCLK_GEN_6_DIV
#define CONF_GCLK_GEN_6_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 7 configuration
// <i> Indicates whether generic clock 7 configuration is enabled or not
// <id> enable_gclk_gen_7
#ifndef CONF_GCLK_GENERATOR_7_CONFIG
#define CONF_GCLK_GENERATOR_7_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 7 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 7
// <id> gclk_gen_7_oscillator
#ifndef CONF_GCLK_GEN_7_SOURCE
#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_7_runstdby
#ifndef CONF_GCLK_GEN_7_RUNSTDBY
#define CONF_GCLK_GEN_7_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_7_div_sel
#ifndef CONF_GCLK_GEN_7_DIVSEL
#define CONF_GCLK_GEN_7_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_7_oe
#ifndef CONF_GCLK_GEN_7_OE
#define CONF_GCLK_GEN_7_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_7_oov
#ifndef CONF_GCLK_GEN_7_OOV
#define CONF_GCLK_GEN_7_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_7_idc
#ifndef CONF_GCLK_GEN_7_IDC
#define CONF_GCLK_GEN_7_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_7_enable
#ifndef CONF_GCLK_GEN_7_GENEN
#define CONF_GCLK_GEN_7_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 7 division <0x0000-0xFFFF>
// <id> gclk_gen_7_div
#ifndef CONF_GCLK_GEN_7_DIV
#define CONF_GCLK_GEN_7_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 8 configuration
// <i> Indicates whether generic clock 8 configuration is enabled or not
// <id> enable_gclk_gen_8
#ifndef CONF_GCLK_GENERATOR_8_CONFIG
#define CONF_GCLK_GENERATOR_8_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 8 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 8
// <id> gclk_gen_8_oscillator
#ifndef CONF_GCLK_GEN_8_SOURCE
#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_8_runstdby
#ifndef CONF_GCLK_GEN_8_RUNSTDBY
#define CONF_GCLK_GEN_8_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_8_div_sel
#ifndef CONF_GCLK_GEN_8_DIVSEL
#define CONF_GCLK_GEN_8_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_8_oe
#ifndef CONF_GCLK_GEN_8_OE
#define CONF_GCLK_GEN_8_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_8_oov
#ifndef CONF_GCLK_GEN_8_OOV
#define CONF_GCLK_GEN_8_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_8_idc
#ifndef CONF_GCLK_GEN_8_IDC
#define CONF_GCLK_GEN_8_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_8_enable
#ifndef CONF_GCLK_GEN_8_GENEN
#define CONF_GCLK_GEN_8_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 8 division <0x0000-0xFFFF>
// <id> gclk_gen_8_div
#ifndef CONF_GCLK_GEN_8_DIV
#define CONF_GCLK_GEN_8_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 9 configuration
// <i> Indicates whether generic clock 9 configuration is enabled or not
// <id> enable_gclk_gen_9
#ifndef CONF_GCLK_GENERATOR_9_CONFIG
#define CONF_GCLK_GENERATOR_9_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 9 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 9
// <id> gclk_gen_9_oscillator
#ifndef CONF_GCLK_GEN_9_SOURCE
#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_9_runstdby
#ifndef CONF_GCLK_GEN_9_RUNSTDBY
#define CONF_GCLK_GEN_9_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_9_div_sel
#ifndef CONF_GCLK_GEN_9_DIVSEL
#define CONF_GCLK_GEN_9_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_9_oe
#ifndef CONF_GCLK_GEN_9_OE
#define CONF_GCLK_GEN_9_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_9_oov
#ifndef CONF_GCLK_GEN_9_OOV
#define CONF_GCLK_GEN_9_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_9_idc
#ifndef CONF_GCLK_GEN_9_IDC
#define CONF_GCLK_GEN_9_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_9_enable
#ifndef CONF_GCLK_GEN_9_GENEN
#define CONF_GCLK_GEN_9_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 9 division <0x0000-0xFFFF>
// <id> gclk_gen_9_div
#ifndef CONF_GCLK_GEN_9_DIV
#define CONF_GCLK_GEN_9_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 10 configuration
// <i> Indicates whether generic clock 10 configuration is enabled or not
// <id> enable_gclk_gen_10
#ifndef CONF_GCLK_GENERATOR_10_CONFIG
#define CONF_GCLK_GENERATOR_10_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 10 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 10
// <id> gclk_gen_10_oscillator
#ifndef CONF_GCLK_GEN_10_SOURCE
#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_10_runstdby
#ifndef CONF_GCLK_GEN_10_RUNSTDBY
#define CONF_GCLK_GEN_10_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_10_div_sel
#ifndef CONF_GCLK_GEN_10_DIVSEL
#define CONF_GCLK_GEN_10_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_10_oe
#ifndef CONF_GCLK_GEN_10_OE
#define CONF_GCLK_GEN_10_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_10_oov
#ifndef CONF_GCLK_GEN_10_OOV
#define CONF_GCLK_GEN_10_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_10_idc
#ifndef CONF_GCLK_GEN_10_IDC
#define CONF_GCLK_GEN_10_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_10_enable
#ifndef CONF_GCLK_GEN_10_GENEN
#define CONF_GCLK_GEN_10_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 10 division <0x0000-0xFFFF>
// <id> gclk_gen_10_div
#ifndef CONF_GCLK_GEN_10_DIV
#define CONF_GCLK_GEN_10_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 11 configuration
// <i> Indicates whether generic clock 11 configuration is enabled or not
// <id> enable_gclk_gen_11
#ifndef CONF_GCLK_GENERATOR_11_CONFIG
#define CONF_GCLK_GENERATOR_11_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 11 source
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 11
// <id> gclk_gen_11_oscillator
#ifndef CONF_GCLK_GEN_11_SOURCE
#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_11_runstdby
#ifndef CONF_GCLK_GEN_11_RUNSTDBY
#define CONF_GCLK_GEN_11_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_11_div_sel
#ifndef CONF_GCLK_GEN_11_DIVSEL
#define CONF_GCLK_GEN_11_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_11_oe
#ifndef CONF_GCLK_GEN_11_OE
#define CONF_GCLK_GEN_11_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_11_oov
#ifndef CONF_GCLK_GEN_11_OOV
#define CONF_GCLK_GEN_11_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_11_idc
#ifndef CONF_GCLK_GEN_11_IDC
#define CONF_GCLK_GEN_11_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_11_enable
#ifndef CONF_GCLK_GEN_11_GENEN
#define CONF_GCLK_GEN_11_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 11 division <0x0000-0xFFFF>
// <id> gclk_gen_11_div
#ifndef CONF_GCLK_GEN_11_DIV
#define CONF_GCLK_GEN_11_DIV 1
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_GCLK_CONFIG_H

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/* Auto-generated config file hpl_mclk_config.h */
#ifndef HPL_MCLK_CONFIG_H
#define HPL_MCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <e> System Configuration
// <i> Indicates whether configuration for system is enabled or not
// <id> enable_cpu_clock
#ifndef CONF_SYSTEM_CONFIG
#define CONF_SYSTEM_CONFIG 1
#endif
// <h> Basic settings
// <y> CPU Clock source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <i> This defines the clock source for the CPU
// <id> cpu_clock_source
#ifndef CONF_CPU_SRC
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> CPU Clock Division Factor
// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
// <i> Prescalar for CPU clock
// <id> cpu_div
#ifndef CONF_MCLK_CPUDIV
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
#endif
// <y> Low Power Clock Division
// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_lpdiv
#ifndef CONF_MCLK_LPDIV
#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
#endif
// <y> Backup Clock Division
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_bupdiv
#ifndef CONF_MCLK_BUPDIV
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
#endif
// <y> High-Speed Clock Division
// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
// <id> mclk_arch_hsdiv
#ifndef CONF_MCLK_HSDIV
#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
#endif
// </h>
// <h> NVM Settings
// <o> NVM Wait States
// <i> These bits select the number of wait states for a read operation.
// <0=> 0
// <1=> 1
// <2=> 2
// <3=> 3
// <4=> 4
// <5=> 5
// <6=> 6
// <7=> 7
// <8=> 8
// <9=> 9
// <10=> 10
// <11=> 11
// <12=> 12
// <13=> 13
// <14=> 14
// <15=> 15
// <id> nvm_wait_states
#ifndef CONF_NVM_WAIT_STATE
#define CONF_NVM_WAIT_STATE 0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_MCLK_CONFIG_H

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/* Auto-generated config file hpl_osc32kctrl_config.h */
#ifndef HPL_OSC32KCTRL_CONFIG_H
#define HPL_OSC32KCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> RTC Source configuration
// <id> enable_rtc_source
#ifndef CONF_RTCCTRL_CONFIG
#define CONF_RTCCTRL_CONFIG 0
#endif
// <h> RTC source control
// <y> RTC Clock Source Selection
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <i> This defines the clock source for RTC
// <id> rtc_source_oscillator
#ifndef CONF_RTCCTRL_SRC
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
#endif
// <q> Use 1 kHz output
// <id> rtc_1khz_selection
#ifndef CONF_RTCCTRL_1KHZ
#define CONF_RTCCTRL_1KHZ 0
#endif
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
#else
#error unexpected CONF_RTCCTRL_SRC
#endif
// </h>
// </e>
// <e> 32kHz External Crystal Oscillator Configuration
// <i> Indicates whether configuration for External 32K Osc is enabled or not
// <id> enable_xosc32k
#ifndef CONF_XOSC32K_CONFIG
#define CONF_XOSC32K_CONFIG 0
#endif
// <h> 32kHz External Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
// <id> xosc32k_arch_enable
#ifndef CONF_XOSC32K_ENABLE
#define CONF_XOSC32K_ENABLE 0
#endif
// <o> Start-Up Time
// <0x0=>62592us
// <0x1=>125092us
// <0x2=>500092us
// <0x3=>1000092us
// <0x4=>2000092us
// <0x5=>4000092us
// <0x6=>8000092us
// <id> xosc32k_arch_startup
#ifndef CONF_XOSC32K_STARTUP
#define CONF_XOSC32K_STARTUP 0x0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc32k_arch_ondemand
#ifndef CONF_XOSC32K_ONDEMAND
#define CONF_XOSC32K_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc32k_arch_runstdby
#ifndef CONF_XOSC32K_RUNSTDBY
#define CONF_XOSC32K_RUNSTDBY 0
#endif
// <q> 1kHz Output Enable
// <i> Indicates whether 1kHz Output is enabled or not
// <id> xosc32k_arch_en1k
#ifndef CONF_XOSC32K_EN1K
#define CONF_XOSC32K_EN1K 0
#endif
// <q> 32kHz Output Enable
// <i> Indicates whether 32kHz Output is enabled or not
// <id> xosc32k_arch_en32k
#ifndef CONF_XOSC32K_EN32K
#define CONF_XOSC32K_EN32K 0
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc32k_arch_swben
#ifndef CONF_XOSC32K_SWBEN
#define CONF_XOSC32K_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc32k_arch_cfden
#ifndef CONF_XOSC32K_CFDEN
#define CONF_XOSC32K_CFDEN 0
#endif
// <q> Clock Failure Detector Event Out
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
// <id> xosc32k_arch_cfdeo
#ifndef CONF_XOSC32K_CFDEO
#define CONF_XOSC32K_CFDEO 0
#endif
// <q> Crystal connected to XIN32/XOUT32 Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc32k_arch_xtalen
#ifndef CONF_XOSC32K_XTALEN
#define CONF_XOSC32K_XTALEN 1
#endif
// <o> Control Gain Mode
// <0x0=>Low Power mode
// <0x1=>Standard mode
// <0x2=>High Speed mode
// <id> xosc32k_arch_cgm
#ifndef CONF_XOSC32K_CGM
#define CONF_XOSC32K_CGM 0x1
#endif
// </h>
// </e>
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
// <i> Indicates whether configuration for OSCULP32K is enabled or not
// <id> enable_osculp32k
#ifndef CONF_OSCULP32K_CONFIG
#define CONF_OSCULP32K_CONFIG 1
#endif
// <h> 32kHz Ultra Low Power Internal Oscillator Control
// <q> Oscillator Calibration Control
// <i> Indicates whether Oscillator Calibration is enabled or not
// <id> osculp32k_calib_enable
#ifndef CONF_OSCULP32K_CALIB_ENABLE
#define CONF_OSCULP32K_CALIB_ENABLE 0
#endif
// <o> Oscillator Calibration <0x0-0x3F>
// <id> osculp32k_calib
#ifndef CONF_OSCULP32K_CALIB
#define CONF_OSCULP32K_CALIB 0x0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_OSC32KCTRL_CONFIG_H

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/* Auto-generated config file hpl_oscctrl_config.h */
#ifndef HPL_OSCCTRL_CONFIG_H
#define HPL_OSCCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> External Multipurpose Crystal Oscillator Configuration
// <i> Indicates whether configuration for XOSC0 is enabled or not
// <id> enable_xosc0
#ifndef CONF_XOSC0_CONFIG
#define CONF_XOSC0_CONFIG 0
#endif
// <o> Frequency <8000000-48000000>
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
// <id> xosc0_frequency
#ifndef CONF_XOSC_FREQUENCY
#define CONF_XOSC0_FREQUENCY 12000000
#endif
// <h> External Multipurpose Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
// <id> xosc0_arch_enable
#ifndef CONF_XOSC0_ENABLE
#define CONF_XOSC0_ENABLE 0
#endif
// <o> Start-Up Time
// <0x0=>31us
// <0x1=>61us
// <0x2=>122us
// <0x3=>244us
// <0x4=>488us
// <0x5=>977us
// <0x6=>1953us
// <0x7=>3906us
// <0x8=>7813us
// <0x9=>15625us
// <0xA=>31250us
// <0xB=>62500us
// <0xC=>125000us
// <0xD=>250000us
// <0xE=>500000us
// <0xF=>1000000us
// <id> xosc0_arch_startup
#ifndef CONF_XOSC0_STARTUP
#define CONF_XOSC0_STARTUP 0
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc0_arch_swben
#ifndef CONF_XOSC0_SWBEN
#define CONF_XOSC0_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc0_arch_cfden
#ifndef CONF_XOSC0_CFDEN
#define CONF_XOSC0_CFDEN 0
#endif
// <q> Automatic Loop Control Enable
// <i> Indicates whether Automatic Loop Control is enabled or not
// <id> xosc0_arch_enalc
#ifndef CONF_XOSC0_ENALC
#define CONF_XOSC0_ENALC 0
#endif
// <q> Low Buffer Gain Enable
// <i> Indicates whether Low Buffer Gain is enabled or not
// <id> xosc0_arch_lowbufgain
#ifndef CONF_XOSC0_LOWBUFGAIN
#define CONF_XOSC0_LOWBUFGAIN 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc0_arch_ondemand
#ifndef CONF_XOSC0_ONDEMAND
#define CONF_XOSC0_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc0_arch_runstdby
#ifndef CONF_XOSC0_RUNSTDBY
#define CONF_XOSC0_RUNSTDBY 0
#endif
// <q> Crystal connected to XIN/XOUT Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc0_arch_xtalen
#ifndef CONF_XOSC0_XTALEN
#define CONF_XOSC0_XTALEN 0
#endif
//</h>
//</e>
#if CONF_XOSC0_FREQUENCY >= 32000000
#define CONF_XOSC0_CFDPRESC 0x0
#define CONF_XOSC0_IMULT 0x7
#define CONF_XOSC0_IPTAT 0x3
#elif CONF_XOSC0_FREQUENCY >= 24000000
#define CONF_XOSC0_CFDPRESC 0x1
#define CONF_XOSC0_IMULT 0x6
#define CONF_XOSC0_IPTAT 0x3
#elif CONF_XOSC0_FREQUENCY >= 16000000
#define CONF_XOSC0_CFDPRESC 0x2
#define CONF_XOSC0_IMULT 0x5
#define CONF_XOSC0_IPTAT 0x3
#elif CONF_XOSC0_FREQUENCY >= 8000000
#define CONF_XOSC0_CFDPRESC 0x3
#define CONF_XOSC0_IMULT 0x4
#define CONF_XOSC0_IPTAT 0x3
#endif
// <e> External Multipurpose Crystal Oscillator Configuration
// <i> Indicates whether configuration for XOSC1 is enabled or not
// <id> enable_xosc1
#ifndef CONF_XOSC1_CONFIG
#define CONF_XOSC1_CONFIG 0
#endif
// <o> Frequency <8000000-48000000>
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
// <id> xosc1_frequency
#ifndef CONF_XOSC_FREQUENCY
#define CONF_XOSC1_FREQUENCY 12000000
#endif
// <h> External Multipurpose Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
// <id> xosc1_arch_enable
#ifndef CONF_XOSC1_ENABLE
#define CONF_XOSC1_ENABLE 0
#endif
// <o> Start-Up Time
// <0x0=>31us
// <0x1=>61us
// <0x2=>122us
// <0x3=>244us
// <0x4=>488us
// <0x5=>977us
// <0x6=>1953us
// <0x7=>3906us
// <0x8=>7813us
// <0x9=>15625us
// <0xA=>31250us
// <0xB=>62500us
// <0xC=>125000us
// <0xD=>250000us
// <0xE=>500000us
// <0xF=>1000000us
// <id> xosc1_arch_startup
#ifndef CONF_XOSC1_STARTUP
#define CONF_XOSC1_STARTUP 0
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc1_arch_swben
#ifndef CONF_XOSC1_SWBEN
#define CONF_XOSC1_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc1_arch_cfden
#ifndef CONF_XOSC1_CFDEN
#define CONF_XOSC1_CFDEN 0
#endif
// <q> Automatic Loop Control Enable
// <i> Indicates whether Automatic Loop Control is enabled or not
// <id> xosc1_arch_enalc
#ifndef CONF_XOSC1_ENALC
#define CONF_XOSC1_ENALC 0
#endif
// <q> Low Buffer Gain Enable
// <i> Indicates whether Low Buffer Gain is enabled or not
// <id> xosc1_arch_lowbufgain
#ifndef CONF_XOSC1_LOWBUFGAIN
#define CONF_XOSC1_LOWBUFGAIN 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc1_arch_ondemand
#ifndef CONF_XOSC1_ONDEMAND
#define CONF_XOSC1_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc1_arch_runstdby
#ifndef CONF_XOSC1_RUNSTDBY
#define CONF_XOSC1_RUNSTDBY 0
#endif
// <q> Crystal connected to XIN/XOUT Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc1_arch_xtalen
#ifndef CONF_XOSC1_XTALEN
#define CONF_XOSC1_XTALEN 1
#endif
//</h>
//</e>
#if CONF_XOSC1_FREQUENCY >= 32000000
#define CONF_XOSC1_CFDPRESC 0x0
#define CONF_XOSC1_IMULT 0x7
#define CONF_XOSC1_IPTAT 0x3
#elif CONF_XOSC1_FREQUENCY >= 24000000
#define CONF_XOSC1_CFDPRESC 0x1
#define CONF_XOSC1_IMULT 0x6
#define CONF_XOSC1_IPTAT 0x3
#elif CONF_XOSC1_FREQUENCY >= 16000000
#define CONF_XOSC1_CFDPRESC 0x2
#define CONF_XOSC1_IMULT 0x5
#define CONF_XOSC1_IPTAT 0x3
#elif CONF_XOSC1_FREQUENCY >= 8000000
#define CONF_XOSC1_CFDPRESC 0x3
#define CONF_XOSC1_IMULT 0x4
#define CONF_XOSC1_IPTAT 0x3
#endif
// <e> DFLL Configuration
// <i> Indicates whether configuration for DFLL is enabled or not
// <id> enable_dfll
#ifndef CONF_DFLL_CONFIG
#define CONF_DFLL_CONFIG 1
#endif
// <y> Reference Clock Source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source
// <id> dfll_ref_clock
#ifndef CONF_DFLL_GCLK
#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK2_Val
#endif
// <h> Digital Frequency Locked Loop Control
// <q> DFLL Enable
// <i> Indicates whether DFLL is enabled or not
// <id> dfll_arch_enable
#ifndef CONF_DFLL_ENABLE
#define CONF_DFLL_ENABLE 1
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> dfll_arch_ondemand
#ifndef CONF_DFLL_ONDEMAND
#define CONF_DFLL_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> dfll_arch_runstdby
#ifndef CONF_DFLL_RUNSTDBY
#define CONF_DFLL_RUNSTDBY 0
#endif
// <q> USB Clock Recovery Mode
// <i> Indicates whether USB Clock Recovery Mode is enabled or not
// <id> dfll_arch_usbcrm
#ifndef CONF_DFLL_USBCRM
#define CONF_DFLL_USBCRM 0
#endif
// <q> Wait Lock
// <i> Indicates whether Wait Lock is enabled or not
// <id> dfll_arch_waitlock
#ifndef CONF_DFLL_WAITLOCK
#define CONF_DFLL_WAITLOCK 1
#endif
// <q> Bypass Coarse Lock
// <i> Indicates whether Bypass Coarse Lock is enabled or not
// <id> dfll_arch_bplckc
#ifndef CONF_DFLL_BPLCKC
#define CONF_DFLL_BPLCKC 0
#endif
// <q> Quick Lock Disable
// <i> Indicates whether Quick Lock Disable is enabled or not
// <id> dfll_arch_qldis
#ifndef CONF_DFLL_QLDIS
#define CONF_DFLL_QLDIS 0
#endif
// <q> Chill Cycle Disable
// <i> Indicates whether Chill Cycle Disable is enabled or not
// <id> dfll_arch_ccdis
#ifndef CONF_DFLL_CCDIS
#define CONF_DFLL_CCDIS 0
#endif
// <q> Lose Lock After Wake
// <i> Indicates whether Lose Lock After Wake is enabled or not
// <id> dfll_arch_llaw
#ifndef CONF_DFLL_LLAW
#define CONF_DFLL_LLAW 0
#endif
// <q> Stable DFLL Frequency
// <i> Indicates whether Stable DFLL Frequency is enabled or not
// <id> dfll_arch_stable
#ifndef CONF_DFLL_STABLE
#define CONF_DFLL_STABLE 0
#endif
// <o> Operating Mode Selection
// <0=>Open Loop Mode
// <1=>Closed Loop Mode
// <id> dfll_mode
#ifndef CONF_DFLL_MODE
#define CONF_DFLL_MODE 0x0
#endif
// <o> Coarse Maximum Step <0x0-0x1F>
// <id> dfll_arch_cstep
#ifndef CONF_DFLL_CSTEP
#define CONF_DFLL_CSTEP 0x1
#endif
// <o> Fine Maximum Step <0x0-0xFF>
// <id> dfll_arch_fstep
#ifndef CONF_DFLL_FSTEP
#define CONF_DFLL_FSTEP 0x1
#endif
// <o> DFLL Multiply Factor <0x0-0xFFFF>
// <id> dfll_mul
#ifndef CONF_DFLL_MUL
#define CONF_DFLL_MUL 0x0
#endif
// <e> DFLL Calibration Overwrite
// <i> Indicates whether Overwrite Calibration value of DFLL
// <id> dfll_arch_calibration
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
#define CONF_DFLL_OVERWRITE_CALIBRATION 0
#endif
// <o> Coarse Value <0x0-0x3F>
// <id> dfll_arch_coarse
#ifndef CONF_DFLL_COARSE
#define CONF_DFLL_COARSE (0x1f / 4)
#endif
// <o> Fine Value <0x0-0xFF>
// <id> dfll_arch_fine
#ifndef CONF_DFLL_FINE
#define CONF_DFLL_FINE (0x80)
#endif
//</e>
//</h>
//</e>
// <e> FDPLL0 Configuration
// <i> Indicates whether configuration for FDPLL0 is enabled or not
// <id> enable_fdpll0
#ifndef CONF_FDPLL0_CONFIG
#define CONF_FDPLL0_CONFIG 0
#endif
// <y> Reference Clock Source
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source.
// <id> fdpll0_ref_clock
#ifndef CONF_FDPLL0_GCLK
#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K
#endif
// <h> Digital Phase Locked Loop Control
// <q> Enable
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
// <id> fdpll0_arch_enable
#ifndef CONF_FDPLL0_ENABLE
#define CONF_FDPLL0_ENABLE 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> fdpll0_arch_ondemand
#ifndef CONF_FDPLL0_ONDEMAND
#define CONF_FDPLL0_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> fdpll0_arch_runstdby
#ifndef CONF_FDPLL0_RUNSTDBY
#define CONF_FDPLL0_RUNSTDBY 0
#endif
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll0_ldrfrac
#ifndef CONF_FDPLL0_LDRFRAC
#define CONF_FDPLL0_LDRFRAC 0xd
#endif
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll0_ldr
#ifndef CONF_FDPLL0_LDR
#define CONF_FDPLL0_LDR 0x5b7
#endif
// <o> Clock Divider <0x0-0x7FF>
// <i> This Clock divider is only for XOSC clock input to DPLL
// <id> fdpll0_clock_div
#ifndef CONF_FDPLL0_DIV
#define CONF_FDPLL0_DIV 0x0
#endif
// <q> DCO Filter Enable
// <i> Indicates whether DCO Filter Enable is enabled or not
// <id> fdpll0_arch_dcoen
#ifndef CONF_FDPLL0_DCOEN
#define CONF_FDPLL0_DCOEN 0
#endif
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
// <id> fdpll0_clock_dcofilter
#ifndef CONF_FDPLL0_DCOFILTER
#define CONF_FDPLL0_DCOFILTER 0x0
#endif
// <q> Lock Bypass
// <i> Indicates whether Lock Bypass is enabled or not
// <id> fdpll0_arch_lbypass
#ifndef CONF_FDPLL0_LBYPASS
#define CONF_FDPLL0_LBYPASS 0
#endif
// <o> Lock Time
// <0x0=>No time-out, automatic lock
// <0x4=>The Time-out if no lock within 800 us
// <0x5=>The Time-out if no lock within 900 us
// <0x6=>The Time-out if no lock within 1 ms
// <0x7=>The Time-out if no lock within 11 ms
// <id> fdpll0_arch_ltime
#ifndef CONF_FDPLL0_LTIME
#define CONF_FDPLL0_LTIME 0x0
#endif
// <o> Reference Clock Selection
// <0x0=>GCLK clock reference
// <0x1=>XOSC32K clock reference
// <0x2=>XOSC0 clock reference
// <0x3=>XOSC1 clock reference
// <id> fdpll0_arch_refclk
#ifndef CONF_FDPLL0_REFCLK
#define CONF_FDPLL0_REFCLK 0x1
#endif
// <q> Wake Up Fast
// <i> Indicates whether Wake Up Fast is enabled or not
// <id> fdpll0_arch_wuf
#ifndef CONF_FDPLL0_WUF
#define CONF_FDPLL0_WUF 0
#endif
// <o> Proportional Integral Filter Selection <0x0-0xF>
// <id> fdpll0_arch_filter
#ifndef CONF_FDPLL0_FILTER
#define CONF_FDPLL0_FILTER 0x0
#endif
//</h>
//</e>
// <e> FDPLL1 Configuration
// <i> Indicates whether configuration for FDPLL1 is enabled or not
// <id> enable_fdpll1
#ifndef CONF_FDPLL1_CONFIG
#define CONF_FDPLL1_CONFIG 1
#endif
// <y> Reference Clock Source
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source.
// <id> fdpll1_ref_clock
#ifndef CONF_FDPLL1_GCLK
#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK1_Val
#endif
// <h> Digital Phase Locked Loop Control
// <q> Enable
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
// <id> fdpll1_arch_enable
#ifndef CONF_FDPLL1_ENABLE
#define CONF_FDPLL1_ENABLE 1
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> fdpll1_arch_ondemand
#ifndef CONF_FDPLL1_ONDEMAND
#define CONF_FDPLL1_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> fdpll1_arch_runstdby
#ifndef CONF_FDPLL1_RUNSTDBY
#define CONF_FDPLL1_RUNSTDBY 0
#endif
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll1_ldrfrac
#ifndef CONF_FDPLL1_LDRFRAC
#define CONF_FDPLL1_LDRFRAC 0x0
#endif
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll1_ldr
#ifndef CONF_FDPLL1_LDR
#define CONF_FDPLL1_LDR 0x3b
#endif
// <o> Clock Divider <0x0-0x7FF>
// <i> This Clock divider is only for XOSC clock input to DPLL
// <id> fdpll1_clock_div
#ifndef CONF_FDPLL1_DIV
#define CONF_FDPLL1_DIV 0x0
#endif
// <q> DCO Filter Enable
// <i> Indicates whether DCO Filter Enable is enabled or not
// <id> fdpll1_arch_dcoen
#ifndef CONF_FDPLL1_DCOEN
#define CONF_FDPLL1_DCOEN 0
#endif
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
// <id> fdpll1_clock_dcofilter
#ifndef CONF_FDPLL1_DCOFILTER
#define CONF_FDPLL1_DCOFILTER 0x0
#endif
// <q> Lock Bypass
// <i> Indicates whether Lock Bypass is enabled or not
// <id> fdpll1_arch_lbypass
#ifndef CONF_FDPLL1_LBYPASS
#define CONF_FDPLL1_LBYPASS 0
#endif
// <o> Lock Time
// <0x0=>No time-out, automatic lock
// <0x4=>The Time-out if no lock within 800 us
// <0x5=>The Time-out if no lock within 900 us
// <0x6=>The Time-out if no lock within 1 ms
// <0x7=>The Time-out if no lock within 11 ms
// <id> fdpll1_arch_ltime
#ifndef CONF_FDPLL1_LTIME
#define CONF_FDPLL1_LTIME 0x0
#endif
// <o> Reference Clock Selection
// <0x0=>GCLK clock reference
// <0x1=>XOSC32K clock reference
// <0x2=>XOSC0 clock reference
// <0x3=>XOSC1 clock reference
// <id> fdpll1_arch_refclk
#ifndef CONF_FDPLL1_REFCLK
#define CONF_FDPLL1_REFCLK 0x0
#endif
// <q> Wake Up Fast
// <i> Indicates whether Wake Up Fast is enabled or not
// <id> fdpll1_arch_wuf
#ifndef CONF_FDPLL1_WUF
#define CONF_FDPLL1_WUF 0
#endif
// <o> Proportional Integral Filter Selection <0x0-0xF>
// <id> fdpll1_arch_filter
#ifndef CONF_FDPLL1_FILTER
#define CONF_FDPLL1_FILTER 0x0
#endif
//</h>
//</e>
// <<< end of configuration section >>>
#endif // HPL_OSCCTRL_CONFIG_H

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/* Auto-generated config file hpl_port_config.h */
#ifndef HPL_PORT_CONFIG_H
#define HPL_PORT_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> PORT Input Event 0 configuration
// <id> enable_port_input_event_0
#ifndef CONF_PORT_EVCTRL_PORT_0
#define CONF_PORT_EVCTRL_PORT_0 0
#endif
// <h> PORT Input Event 0 configuration on PORT A
// <q> PORTA Input Event 0 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
// <id> porta_input_event_enable_0
#ifndef CONF_PORTA_EVCTRL_PORTEI_0
#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
#endif
// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_0
#ifndef CONF_PORTA_EVCTRL_PID_0
#define CONF_PORTA_EVCTRL_PID_0 0x0
#endif
// <o> PORTA Event 0 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 0
// <id> porta_event_action_0
#ifndef CONF_PORTA_EVCTRL_EVACT_0
#define CONF_PORTA_EVCTRL_EVACT_0 0
#endif
// </h>
// <h> PORT Input Event 0 configuration on PORT B
// <q> PORTB Input Event 0 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
// <id> portb_input_event_enable_0
#ifndef CONF_PORTB_EVCTRL_PORTEI_0
#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
#endif
// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_0
#ifndef CONF_PORTB_EVCTRL_PID_0
#define CONF_PORTB_EVCTRL_PID_0 0x0
#endif
// <o> PORTB Event 0 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 0
// <id> portb_event_action_0
#ifndef CONF_PORTB_EVCTRL_EVACT_0
#define CONF_PORTB_EVCTRL_EVACT_0 0
#endif
// </h>
// </e>
// <e> PORT Input Event 1 configuration
// <id> enable_port_input_event_1
#ifndef CONF_PORT_EVCTRL_PORT_1
#define CONF_PORT_EVCTRL_PORT_1 0
#endif
// <h> PORT Input Event 1 configuration on PORT A
// <q> PORTA Input Event 1 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
// <id> porta_input_event_enable_1
#ifndef CONF_PORTA_EVCTRL_PORTEI_1
#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
#endif
// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_1
#ifndef CONF_PORTA_EVCTRL_PID_1
#define CONF_PORTA_EVCTRL_PID_1 0x0
#endif
// <o> PORTA Event 1 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 1
// <id> porta_event_action_1
#ifndef CONF_PORTA_EVCTRL_EVACT_1
#define CONF_PORTA_EVCTRL_EVACT_1 0
#endif
// </h>
// <h> PORT Input Event 1 configuration on PORT B
// <q> PORTB Input Event 1 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
// <id> portb_input_event_enable_1
#ifndef CONF_PORTB_EVCTRL_PORTEI_1
#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
#endif
// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_1
#ifndef CONF_PORTB_EVCTRL_PID_1
#define CONF_PORTB_EVCTRL_PID_1 0x0
#endif
// <o> PORTB Event 1 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 1
// <id> portb_event_action_1
#ifndef CONF_PORTB_EVCTRL_EVACT_1
#define CONF_PORTB_EVCTRL_EVACT_1 0
#endif
// </h>
// </e>
// <e> PORT Input Event 2 configuration
// <id> enable_port_input_event_2
#ifndef CONF_PORT_EVCTRL_PORT_2
#define CONF_PORT_EVCTRL_PORT_2 0
#endif
// <h> PORT Input Event 2 configuration on PORT A
// <q> PORTA Input Event 2 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
// <id> porta_input_event_enable_2
#ifndef CONF_PORTA_EVCTRL_PORTEI_2
#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
#endif
// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_2
#ifndef CONF_PORTA_EVCTRL_PID_2
#define CONF_PORTA_EVCTRL_PID_2 0x0
#endif
// <o> PORTA Event 2 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 2
// <id> porta_event_action_2
#ifndef CONF_PORTA_EVCTRL_EVACT_2
#define CONF_PORTA_EVCTRL_EVACT_2 0
#endif
// </h>
// <h> PORT Input Event 2 configuration on PORT B
// <q> PORTB Input Event 2 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
// <id> portb_input_event_enable_2
#ifndef CONF_PORTB_EVCTRL_PORTEI_2
#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
#endif
// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_2
#ifndef CONF_PORTB_EVCTRL_PID_2
#define CONF_PORTB_EVCTRL_PID_2 0x0
#endif
// <o> PORTB Event 2 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 2
// <id> portb_event_action_2
#ifndef CONF_PORTB_EVCTRL_EVACT_2
#define CONF_PORTB_EVCTRL_EVACT_2 0
#endif
// </h>
// </e>
// <e> PORT Input Event 3 configuration
// <id> enable_port_input_event_3
#ifndef CONF_PORT_EVCTRL_PORT_3
#define CONF_PORT_EVCTRL_PORT_3 0
#endif
// <h> PORT Input Event 3 configuration on PORT A
// <q> PORTA Input Event 3 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
// <id> porta_input_event_enable_3
#ifndef CONF_PORTA_EVCTRL_PORTEI_3
#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
#endif
// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_3
#ifndef CONF_PORTA_EVCTRL_PID_3
#define CONF_PORTA_EVCTRL_PID_3 0x0
#endif
// <o> PORTA Event 3 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 3
// <id> porta_event_action_3
#ifndef CONF_PORTA_EVCTRL_EVACT_3
#define CONF_PORTA_EVCTRL_EVACT_3 0
#endif
// </h>
// <h> PORT Input Event 3 configuration on PORT B
// <q> PORTB Input Event 3 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
// <id> portb_input_event_enable_3
#ifndef CONF_PORTB_EVCTRL_PORTEI_3
#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
#endif
// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_3
#ifndef CONF_PORTB_EVCTRL_PID_3
#define CONF_PORTB_EVCTRL_PID_3 0x0
#endif
// <o> PORTB Event 3 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 3
// <id> portb_event_action_3
#ifndef CONF_PORTB_EVCTRL_EVACT_3
#define CONF_PORTB_EVCTRL_EVACT_3 0
#endif
// </h>
// </e>
#define CONF_PORTA_EVCTRL \
(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
| PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \
| CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \
| PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
| PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \
| CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
#define CONF_PORTB_EVCTRL \
(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
| PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \
| CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \
| PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
| PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \
| CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
// <<< end of configuration section >>>
#endif // HPL_PORT_CONFIG_H

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/* Auto-generated config file hpl_qspi_config.h */
#ifndef HPL_QSPI_CONFIG_H
#define HPL_QSPI_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <h> Basic settings
#ifndef CONF_CONF_QSPI_ENABLE
#define CONF_CONF_QSPI_ENABLE 1
#endif
// <o> Baud rate <1-150000000>
// <i> The SPI data transfer rate. Note: (fqspi_clock / baudrate) < 255
// <id> qspi_baud_rate
#ifndef CONF_QSPI_BAUD
#define CONF_QSPI_BAUD 6000000
#endif
// <o> Clock Polarity
// <0x0=>The inactive state value of SPCK is logic level zero.
// <0x1=>The inactive state value of SPCK is logic level one.
// <i> Determines the inactive state value of the serial clock (SPCK).
// <id> qspi_cpol
#ifndef CONF_QSPI_CPOL
#define CONF_QSPI_CPOL 0x0
#endif
// <o> Clock Phase
// <0x0=>Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
// <0x1=>Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
// <i> Determines which edge of SPCK causes data to change and which edge causes data to be captured.
// <id> qspi_cpha
#ifndef CONF_QSPI_CPHA
#define CONF_QSPI_CPHA 0x0
#endif
//<o> QSPI DMA TX Channel <0-32>
//<i> This defines DMA channel to be used
//<id> qspi_dma_tx_channel
#ifndef CONF_QSPI_DMA_TX_CHANNEL
#define CONF_QSPI_DMA_TX_CHANNEL 1
#endif
//<o> QSPI DMA RX Channel <0-32>
//<i> This defines DMA channel to be used
//<id> qspi_dma_rx_channel
#ifndef CONF_QSPI_DMA_RX_CHANNEL
#define CONF_QSPI_DMA_RX_CHANNEL 0
#endif
// </h>
// <e> Advanced Configuration
// <id> qspi_advanced
#ifndef CONF_QSPI_ADVANCED
#define CONF_QSPI_ADVANCED 0
#endif
// <o> Delay Before QSCK (ns) <0-255000>
// <i> This field defines the delay from QCS falling edge (activation) to the first valid QSCK transition (in ns).
// <id> qspi_dlybs
#ifndef CONF_QSPI_DLY_BS
#define CONF_QSPI_DLY_BS 0
#endif
// <o> Minimum Inactive QCS Delay (ns) <0-8160000>
// <i> This field defines the minimum delay between the deactivation and the activation of QCS (in ns).
// <id> qspi_dlycs
#ifndef CONF_QSPI_DLY_CS
#define CONF_QSPI_DLY_CS 0
#endif
// </e>
/* Calculate baud register value from requested baudrate value */
#ifndef CONF_QSPI_BAUD_RATE
#define CONF_QSPI_BAUD_RATE ((CONF_CPU_FREQUENCY / CONF_QSPI_BAUD) - 1)
#if CONF_QSPI_BAUD > CONF_CPU_FREQUENCY || CONF_QSPI_BAUD_RATE > 255
#warning Invalid baudrate, please check.
#endif
#endif
/* Calculates the value of the CSR DLYCS field given the desired delay (in ns) */
#ifndef CONF_QSPI_DLYCS
#define CONF_QSPI_DLYCS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_CS) / 1000)
#endif
/* Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
#ifndef CONF_QSPI_DLYBS
#define CONF_QSPI_DLYBS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_BS) / 1000)
#endif
// <<< end of configuration section >>>
#endif // HPL_QSPI_CONFIG_H

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/* Auto-generated config file hpl_sercom_config.h */
#ifndef HPL_SERCOM_CONFIG_H
#define HPL_SERCOM_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// Enable configuration of module
#ifndef CONF_SERCOM_1_SPI_ENABLE
#define CONF_SERCOM_1_SPI_ENABLE 1
#endif
// Set module in SPI Slave mode
#ifndef CONF_SERCOM_1_SPI_MODE
#define CONF_SERCOM_1_SPI_MODE 0x02
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable receive buffer to receive data from slave. (RXEN)
// <id> spi_slave_rx_enable
#ifndef CONF_SERCOM_1_SPI_RXEN
#define CONF_SERCOM_1_SPI_RXEN 0x1
#endif
// <o> Character Size
// <i> Bit size for all characters sent over the SPI bus. (CHSIZE)
// <0x0=>8 bits
// <0x1=>9 bits
// <id> spi_slave_character_size
#ifndef CONF_SERCOM_1_SPI_CHSIZE
#define CONF_SERCOM_1_SPI_CHSIZE 0x0
#endif
// </h>
// <e> Advanced Configuration
// <id> spi_slave_advanced
#ifndef CONF_SERCOM_1_SPI_ADVANCED
#define CONF_SERCOM_1_SPI_ADVANCED 1
#endif
// <o> Data Order
// <0=>MSB first
// <1=>LSB first
// <i> I least significant or most significant bit is shifted out first. (DORD)
// <id> spi_slave_arch_dord
#ifndef CONF_SERCOM_1_SPI_DORD
#define CONF_SERCOM_1_SPI_DORD 0x0
#endif
// <o> Clock Polarity
// <0=>SCK is low when idle
// <1=>SCK is high when idle
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
// <id> spi_slave_arch_cpol
#ifndef CONF_SERCOM_1_SPI_CPOL
#define CONF_SERCOM_1_SPI_CPOL 0x0
#endif
// <o> Clock Phase
// <0x0=>Sample input on leading edge
// <0x1=>Sample input on trailing edge
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
// <id> spi_slave_arch_cpha
#ifndef CONF_SERCOM_1_SPI_CPHA
#define CONF_SERCOM_1_SPI_CPHA 0x0
#endif
// <o> Immediate Buffer Overflow Notification
// <i> Controls when OVF is asserted. (IBON)
// <0x0=>In data stream
// <0x1=>On buffer overflow
// <id> spi_slave_arch_ibon
#ifndef CONF_SERCOM_1_SPI_IBON
#define CONF_SERCOM_1_SPI_IBON 0x0
#endif
// <q> Slave Select Low Detect Enable
// <i> This bit enables wake up when the slave select (_SS) pin transitions from high to low. (SSDE)
// <id> spi_slave_arch_ssde
#ifndef CONF_SERCOM_1_SPI_SSDE
#define CONF_SERCOM_1_SPI_SSDE 0
#endif
// <q> Slave Detect Preload Enable
// <i> Setting this bit will enable preloading of the slave shift register when there is no transfer in progress. (PLOADEN)
// <id> spi_slave_arch_ploaden
#ifndef CONF_SERCOM_1_SPI_PLOADEN
#define CONF_SERCOM_1_SPI_PLOADEN 1
#endif
// <q> Enable SPI address mode
// <i> This will enable SPI frames with address, first received character is treated as address. (FORM=SPI_ADDR)
// <id> spi_slave_arch_amode_en
#ifndef CONF_SERCOM_1_SPI_AMODE_EN
#define CONF_SERCOM_1_SPI_AMODE_EN 0
#endif
// <o> Address Mode
// <0x0=>Address mask
// <0x1=>Two unique addresses
// <0x2=>Address range
// <i> These bits set the slave addressing mode when the frame format with address is used. (AMODE)
// <id> spi_slave_arch_amode
#ifndef CONF_SERCOM_1_SPI_AMODE
#define CONF_SERCOM_1_SPI_AMODE 0
#endif
// <o> Address <0-255>
// <i> These bits hold the address when SPI address modes is enabled. (ADDR)
// <id> spi_slave_arch_addr
#ifndef CONF_SERCOM_1_SPI_ADDR
#define CONF_SERCOM_1_SPI_ADDR 0
#endif
// <o> Address mask <0-255>
// <i> These bits hold the address mask when SPI address mode is enabled. (ADDRMASK)
// <id> spi_slave_arch_addrmask
#ifndef CONF_SERCOM_1_SPI_ADDRMASK
#define CONF_SERCOM_1_SPI_ADDRMASK 0
#endif
// <q> Run in stand-by
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
// <id> spi_slave_arch_runstdby
#ifndef CONF_SERCOM_1_SPI_RUNSTDBY
#define CONF_SERCOM_1_SPI_RUNSTDBY 0x0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
// <0=>Keep running
// <1=>Halt
// <id> spi_slave_arch_dbgstop
#ifndef CONF_SERCOM_1_SPI_DBGSTOP
#define CONF_SERCOM_1_SPI_DBGSTOP 0
#endif
// </e>
// This bit is not applicable in slave mode
#ifndef CONF_SERCOM_1_SPI_MSSEN
#define CONF_SERCOM_1_SPI_MSSEN 0x0
#endif
// <o> Receive Data Pinout
// <0x0=>PAD[0]
// <0x1=>PAD[1]
// <0x2=>PAD[2]
// <0x3=>PAD[3]
// <id> spi_slave_rxpo
#ifndef CONF_SERCOM_1_SPI_RXPO
#define CONF_SERCOM_1_SPI_RXPO 0
#endif
// <o> Transmit Data Pinout
// <0x0=>PAD[0,1]_DO_SCK
// <0x1=>PAD[2,3]_DO_SCK
// <0x2=>PAD[3,1]_DO_SCK
// <0x3=>PAD[0,3]_DO_SCK
// <id> spi_slave_txpo
#ifndef CONF_SERCOM_1_SPI_TXPO
#define CONF_SERCOM_1_SPI_TXPO 2
#endif
#ifndef CONF_SERCOM_1_SPI_BAUD_RATE
#define CONF_SERCOM_1_SPI_BAUD_RATE 0
#endif
#ifndef CONF_SERCOM_1_SPI_DUMMYBYTE
#define CONF_SERCOM_1_SPI_DUMMYBYTE 0x0
#endif
#include <peripheral_clk_config.h>
// Enable configuration of module
#ifndef CONF_SERCOM_2_SPI_ENABLE
#define CONF_SERCOM_2_SPI_ENABLE 1
#endif
// Set module in SPI Master mode
#ifndef CONF_SERCOM_2_SPI_MODE
#define CONF_SERCOM_2_SPI_MODE 0x03
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable receive buffer to receive data from slave (RXEN)
// <id> spi_master_rx_enable
#ifndef CONF_SERCOM_2_SPI_RXEN
#define CONF_SERCOM_2_SPI_RXEN 0x1
#endif
// <o> Character Size
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
// <0x0=>8 bits
// <0x1=>9 bits
// <id> spi_master_character_size
#ifndef CONF_SERCOM_2_SPI_CHSIZE
#define CONF_SERCOM_2_SPI_CHSIZE 0x0
#endif
// <o> Baud rate <1-18000000>
// <i> The SPI data transfer rate
// <id> spi_master_baud_rate
#ifndef CONF_SERCOM_2_SPI_BAUD
#define CONF_SERCOM_2_SPI_BAUD 50000
#endif
// </h>
// <e> Advanced Configuration
// <id> spi_master_advanced
#ifndef CONF_SERCOM_2_SPI_ADVANCED
#define CONF_SERCOM_2_SPI_ADVANCED 0
#endif
// <o> Dummy byte <0x00-0x1ff>
// <id> spi_master_dummybyte
// <i> Dummy byte used when reading data from the slave without sending any data
#ifndef CONF_SERCOM_2_SPI_DUMMYBYTE
#define CONF_SERCOM_2_SPI_DUMMYBYTE 0x1ff
#endif
// <o> Data Order
// <0=>MSB first
// <1=>LSB first
// <i> I least significant or most significant bit is shifted out first (DORD)
// <id> spi_master_arch_dord
#ifndef CONF_SERCOM_2_SPI_DORD
#define CONF_SERCOM_2_SPI_DORD 0x0
#endif
// <o> Clock Polarity
// <0=>SCK is low when idle
// <1=>SCK is high when idle
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
// <id> spi_master_arch_cpol
#ifndef CONF_SERCOM_2_SPI_CPOL
#define CONF_SERCOM_2_SPI_CPOL 0x0
#endif
// <o> Clock Phase
// <0x0=>Sample input on leading edge
// <0x1=>Sample input on trailing edge
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
// <id> spi_master_arch_cpha
#ifndef CONF_SERCOM_2_SPI_CPHA
#define CONF_SERCOM_2_SPI_CPHA 0x0
#endif
// <o> Immediate Buffer Overflow Notification
// <i> Controls when OVF is asserted (IBON)
// <0x0=>In data stream
// <0x1=>On buffer overflow
// <id> spi_master_arch_ibon
#ifndef CONF_SERCOM_2_SPI_IBON
#define CONF_SERCOM_2_SPI_IBON 0x0
#endif
// <q> Run in stand-by
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
// <id> spi_master_arch_runstdby
#ifndef CONF_SERCOM_2_SPI_RUNSTDBY
#define CONF_SERCOM_2_SPI_RUNSTDBY 0x0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
// <0=>Keep running
// <1=>Halt
// <id> spi_master_arch_dbgstop
#ifndef CONF_SERCOM_2_SPI_DBGSTOP
#define CONF_SERCOM_2_SPI_DBGSTOP 0
#endif
// </e>
// Address mode disabled in master mode
#ifndef CONF_SERCOM_2_SPI_AMODE_EN
#define CONF_SERCOM_2_SPI_AMODE_EN 0
#endif
#ifndef CONF_SERCOM_2_SPI_AMODE
#define CONF_SERCOM_2_SPI_AMODE 0
#endif
#ifndef CONF_SERCOM_2_SPI_ADDR
#define CONF_SERCOM_2_SPI_ADDR 0
#endif
#ifndef CONF_SERCOM_2_SPI_ADDRMASK
#define CONF_SERCOM_2_SPI_ADDRMASK 0
#endif
#ifndef CONF_SERCOM_2_SPI_SSDE
#define CONF_SERCOM_2_SPI_SSDE 0
#endif
#ifndef CONF_SERCOM_2_SPI_MSSEN
#define CONF_SERCOM_2_SPI_MSSEN 0x0
#endif
#ifndef CONF_SERCOM_2_SPI_PLOADEN
#define CONF_SERCOM_2_SPI_PLOADEN 0
#endif
// <o> Receive Data Pinout
// <0x0=>PAD[0]
// <0x1=>PAD[1]
// <0x2=>PAD[2]
// <0x3=>PAD[3]
// <id> spi_master_rxpo
#ifndef CONF_SERCOM_2_SPI_RXPO
#define CONF_SERCOM_2_SPI_RXPO 3
#endif
// <o> Transmit Data Pinout
// <0x0=>PAD[0,1]_DO_SCK
// <0x1=>PAD[2,3]_DO_SCK
// <0x2=>PAD[3,1]_DO_SCK
// <0x3=>PAD[0,3]_DO_SCK
// <id> spi_master_txpo
#ifndef CONF_SERCOM_2_SPI_TXPO
#define CONF_SERCOM_2_SPI_TXPO 0
#endif
// Calculate baud register value from requested baudrate value
#ifndef CONF_SERCOM_2_SPI_BAUD_RATE
#define CONF_SERCOM_2_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM2_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_2_SPI_BAUD)) - 1
#endif
#include <peripheral_clk_config.h>
// Enable configuration of module
#ifndef CONF_SERCOM_5_SPI_ENABLE
#define CONF_SERCOM_5_SPI_ENABLE 1
#endif
// Set module in SPI Master mode
#ifndef CONF_SERCOM_5_SPI_MODE
#define CONF_SERCOM_5_SPI_MODE 0x03
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable receive buffer to receive data from slave (RXEN)
// <id> spi_master_rx_enable
#ifndef CONF_SERCOM_5_SPI_RXEN
#define CONF_SERCOM_5_SPI_RXEN 0x1
#endif
// <o> Character Size
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
// <0x0=>8 bits
// <0x1=>9 bits
// <id> spi_master_character_size
#ifndef CONF_SERCOM_5_SPI_CHSIZE
#define CONF_SERCOM_5_SPI_CHSIZE 0x0
#endif
// <o> Baud rate <1-18000000>
// <i> The SPI data transfer rate
// <id> spi_master_baud_rate
#ifndef CONF_SERCOM_5_SPI_BAUD
#define CONF_SERCOM_5_SPI_BAUD 50000
#endif
// </h>
// <e> Advanced Configuration
// <id> spi_master_advanced
#ifndef CONF_SERCOM_5_SPI_ADVANCED
#define CONF_SERCOM_5_SPI_ADVANCED 0
#endif
// <o> Dummy byte <0x00-0x1ff>
// <id> spi_master_dummybyte
// <i> Dummy byte used when reading data from the slave without sending any data
#ifndef CONF_SERCOM_5_SPI_DUMMYBYTE
#define CONF_SERCOM_5_SPI_DUMMYBYTE 0x1ff
#endif
// <o> Data Order
// <0=>MSB first
// <1=>LSB first
// <i> I least significant or most significant bit is shifted out first (DORD)
// <id> spi_master_arch_dord
#ifndef CONF_SERCOM_5_SPI_DORD
#define CONF_SERCOM_5_SPI_DORD 0x0
#endif
// <o> Clock Polarity
// <0=>SCK is low when idle
// <1=>SCK is high when idle
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
// <id> spi_master_arch_cpol
#ifndef CONF_SERCOM_5_SPI_CPOL
#define CONF_SERCOM_5_SPI_CPOL 0x0
#endif
// <o> Clock Phase
// <0x0=>Sample input on leading edge
// <0x1=>Sample input on trailing edge
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
// <id> spi_master_arch_cpha
#ifndef CONF_SERCOM_5_SPI_CPHA
#define CONF_SERCOM_5_SPI_CPHA 0x0
#endif
// <o> Immediate Buffer Overflow Notification
// <i> Controls when OVF is asserted (IBON)
// <0x0=>In data stream
// <0x1=>On buffer overflow
// <id> spi_master_arch_ibon
#ifndef CONF_SERCOM_5_SPI_IBON
#define CONF_SERCOM_5_SPI_IBON 0x0
#endif
// <q> Run in stand-by
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
// <id> spi_master_arch_runstdby
#ifndef CONF_SERCOM_5_SPI_RUNSTDBY
#define CONF_SERCOM_5_SPI_RUNSTDBY 0x0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
// <0=>Keep running
// <1=>Halt
// <id> spi_master_arch_dbgstop
#ifndef CONF_SERCOM_5_SPI_DBGSTOP
#define CONF_SERCOM_5_SPI_DBGSTOP 0
#endif
// </e>
// Address mode disabled in master mode
#ifndef CONF_SERCOM_5_SPI_AMODE_EN
#define CONF_SERCOM_5_SPI_AMODE_EN 0
#endif
#ifndef CONF_SERCOM_5_SPI_AMODE
#define CONF_SERCOM_5_SPI_AMODE 0
#endif
#ifndef CONF_SERCOM_5_SPI_ADDR
#define CONF_SERCOM_5_SPI_ADDR 0
#endif
#ifndef CONF_SERCOM_5_SPI_ADDRMASK
#define CONF_SERCOM_5_SPI_ADDRMASK 0
#endif
#ifndef CONF_SERCOM_5_SPI_SSDE
#define CONF_SERCOM_5_SPI_SSDE 0
#endif
#ifndef CONF_SERCOM_5_SPI_MSSEN
#define CONF_SERCOM_5_SPI_MSSEN 0x0
#endif
#ifndef CONF_SERCOM_5_SPI_PLOADEN
#define CONF_SERCOM_5_SPI_PLOADEN 0
#endif
// <o> Receive Data Pinout
// <0x0=>PAD[0]
// <0x1=>PAD[1]
// <0x2=>PAD[2]
// <0x3=>PAD[3]
// <id> spi_master_rxpo
#ifndef CONF_SERCOM_5_SPI_RXPO
#define CONF_SERCOM_5_SPI_RXPO 3
#endif
// <o> Transmit Data Pinout
// <0x0=>PAD[0,1]_DO_SCK
// <0x1=>PAD[2,3]_DO_SCK
// <0x2=>PAD[3,1]_DO_SCK
// <0x3=>PAD[0,3]_DO_SCK
// <id> spi_master_txpo
#ifndef CONF_SERCOM_5_SPI_TXPO
#define CONF_SERCOM_5_SPI_TXPO 0
#endif
// Calculate baud register value from requested baudrate value
#ifndef CONF_SERCOM_5_SPI_BAUD_RATE
#define CONF_SERCOM_5_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM5_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_5_SPI_BAUD)) - 1
#endif
// <<< end of configuration section >>>
#endif // HPL_SERCOM_CONFIG_H

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/* Auto-generated config file hpl_tc_config.h */
#ifndef HPL_TC_CONFIG_H
#define HPL_TC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef CONF_TC0_ENABLE
#define CONF_TC0_ENABLE 1
#endif
#include "peripheral_clk_config.h"
// <h> Basic configuration
// <o> Prescaler
// <0x0=> No division
// <0x1=> Divide by 2
// <0x2=> Divide by 4
// <0x3=> Divide by 8
// <0x4=> Divide by 16
// <0x5=> Divide by 64
// <0x6=> Divide by 256
// <0x7=> Divide by 1024
// <i> This defines the prescaler value
// <id> timer_prescaler
#ifndef CONF_TC0_PRESCALER
#define CONF_TC0_PRESCALER 0x5
#endif
// <o> Length of one timer tick in uS <0-4294967295>
// <id> timer_tick
#ifndef CONF_TC0_TIMER_TICK
#define CONF_TC0_TIMER_TICK 1000
#endif
// </h>
// <e> Advanced configuration
// <id> timer_advanced_configuration
#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE
#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 1
#endif
// <y> Prescaler and Counter Synchronization Selection
// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
// <id> tc_arch_presync
#ifndef CONF_TC0_PRESCSYNC
#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
#endif
// <q> Run in standby
// <i> Indicates whether the module will continue to run in standby sleep mode
// <id> tc_arch_runstdby
#ifndef CONF_TC0_RUNSTDBY
#define CONF_TC0_RUNSTDBY 0
#endif
// <q> Run in debug mode
// <i> Indicates whether the module will run in debug mode
// <id> tc_arch_dbgrun
#ifndef CONF_TC0_DBGRUN
#define CONF_TC0_DBGRUN 0
#endif
// <q> Run on demand
// <i> Run if requested by some other peripheral in the device
// <id> tc_arch_ondemand
#ifndef CONF_TC0_ONDEMAND
#define CONF_TC0_ONDEMAND 0
#endif
// </e>
// <e> Event control
// <id> timer_event_control
#ifndef CONF_TC0_EVENT_CONTROL_ENABLE
#define CONF_TC0_EVENT_CONTROL_ENABLE 0
#endif
// <q> Output Event On Match or Capture on Channel 0
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo0
#ifndef CONF_TC0_MCEO0
#define CONF_TC0_MCEO0 0
#endif
// <q> Output Event On Match or Capture on Channel 1
// <i> Enable output of event on timer tick
// <id> tc_arch_mceo1
#ifndef CONF_TC0_MCEO1
#define CONF_TC0_MCEO1 0
#endif
// <q> Output Event On Timer Tick
// <i> Enable output of event on timer tick
// <id> tc_arch_ovfeo
#ifndef CONF_TC0_OVFEO
#define CONF_TC0_OVFEO 0
#endif
// <q> Event Input
// <i> Enable asynchronous input events
// <id> tc_arch_tcei
#ifndef CONF_TC0_TCEI
#define CONF_TC0_TCEI 0
#endif
// <q> Inverted Event Input
// <i> Invert the asynchronous input events
// <id> tc_arch_tcinv
#ifndef CONF_TC0_TCINV
#define CONF_TC0_TCINV 0
#endif
// <o> Event action
// <0=> Event action disabled
// <1=> Start, restart or re-trigger TC on event
// <2=> Count on event
// <3=> Start on event
// <4=> Time stamp capture
// <5=> Period captured in CC0, pulse width in CC1
// <6=> Period captured in CC1, pulse width in CC0
// <7=> Pulse width capture
// <i> Event which will be performed on an event
//<id> tc_arch_evact
#ifndef CONF_TC0_EVACT
#define CONF_TC0_EVACT 0
#endif
// </e>
// Default values which the driver needs in order to work correctly
// Mode set to 32-bit
#ifndef CONF_TC0_MODE
#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val
#endif
// CC 1 register set to 0
#ifndef CONF_TC0_CC1
#define CONF_TC0_CC1 0
#endif
#ifndef CONF_TC0_ALOCK
#define CONF_TC0_ALOCK 0
#endif
// Not used in 32-bit mode
#define CONF_TC0_PER 0
// Calculating correct top value based on requested tick interval.
#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER)
// Prescaler set to 64
#if CONF_TC0_PRESCALER > 0x4
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 64
#endif
// Prescaler set to 256
#if CONF_TC0_PRESCALER > 0x5
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 256
#endif
// Prescaler set to 1024
#if CONF_TC0_PRESCALER > 0x6
#undef CONF_TC0_PRESCALE
#define CONF_TC0_PRESCALE 1024
#endif
#ifndef CONF_TC0_CC0
#define CONF_TC0_CC0 \
(uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE)))
#endif
// <<< end of configuration section >>>
#endif // HPL_TC_CONFIG_H

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<?xml version="1.0" encoding="utf-8"?>
<Configurations xmlns:i="http://www.w3.org/2001/XMLSchema-instance" z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/" xmlns="DefaultValues">
<Configurations>
<Configuration z:Id="i2">
<Compiler_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
<d4p1:KeyValueOfstringstring>
<d4p1:Key>DebugLevel</d4p1:Key>
<d4p1:Value>None</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>IncludePaths</d4p1:Key>
<d4p1:Value>NDEBUG</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>MiscellaneousSettings</d4p1:Key>
<d4p1:Value>-std=gnu99</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>OptimizationLevel</d4p1:Key>
<d4p1:Value>Optimize for size (-Os)</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>SymbolDefines</d4p1:Key>
<d4p1:Value>NDEBUG</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>SymbolUndefines</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>Verbose</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>WarningsAsErrors</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.general.CLanguageExp</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.general.ChangeDefaultCharTypeUnsigned</d4p1:Key>
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</d4p1:KeyValueOfstringstring>
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/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAME51J19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
2_Motor_Slave/Motor_Slave/Motor_Slave/Device_Startup/same51j19a_sram.ld Normal file
View File

@ -0,0 +1,162 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAME51J19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

546
2_Motor_Slave/Motor_Slave/Motor_Slave/Device_Startup/startup_same51.c Normal file
View File

@ -0,0 +1,546 @@
/**
* \file
*
* \brief gcc starttup file for SAME51
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#include "same51.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M4 core handlers */
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MemManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
void OSCCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
void OSCCTRL_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
void OSCCTRL_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
void OSCCTRL_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
void SUPC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
void EIC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
void EIC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
void EIC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
void EIC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
void EIC_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
void EIC_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
void EIC_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
void EIC_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
void EIC_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
void EIC_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
void EIC_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
void EIC_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
void EIC_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
void EIC_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
void EIC_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
void DMAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
void EVSYS_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
void SERCOM0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
void SERCOM1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
void SERCOM2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
void SERCOM3_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
#ifdef ID_SERCOM4
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
void SERCOM4_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
#endif
#ifdef ID_SERCOM5
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
void SERCOM5_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
#endif
#ifdef ID_SERCOM6
void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
void SERCOM6_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
#endif
#ifdef ID_SERCOM7
void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
void SERCOM7_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
#endif
#ifdef ID_CAN0
void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_CAN1
void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_USB
void USB_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
void USB_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
void USB_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
void USB_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
#endif
#ifdef ID_GMAC
void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void TCC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
void TCC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
void TCC0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
void TCC0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
void TCC0_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
void TCC0_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
void TCC0_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
void TCC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
void TCC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
void TCC1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
void TCC1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
void TCC1_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
void TCC2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
void TCC2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
void TCC2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
void TCC2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
#ifdef ID_TCC3
void TCC3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
void TCC3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
void TCC3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
#endif
#ifdef ID_TCC4
void TCC4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
void TCC4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
void TCC4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
#endif
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_TC4
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_TC5
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_TC6
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_TC7
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void PDEC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
void PDEC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
void PDEC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
void ADC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
void ADC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
void ADC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
void ADC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
void DAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
void DAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
void DAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
void DAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
#ifdef ID_I2S
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_ICM
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_PUKCC
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_SDHC0
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_SDHC1
void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void*) (&_estack),
.pfnReset_Handler = (void*) Reset_Handler,
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
.pfnHardFault_Handler = (void*) HardFault_Handler,
.pfnMemManagement_Handler = (void*) MemManagement_Handler,
.pfnBusFault_Handler = (void*) BusFault_Handler,
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
.pvReservedM9 = (void*) (0UL), /* Reserved */
.pvReservedM8 = (void*) (0UL), /* Reserved */
.pvReservedM7 = (void*) (0UL), /* Reserved */
.pvReservedM6 = (void*) (0UL), /* Reserved */
.pfnSVCall_Handler = (void*) SVCall_Handler,
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
.pvReservedM3 = (void*) (0UL), /* Reserved */
.pfnPendSV_Handler = (void*) PendSV_Handler,
.pfnSysTick_Handler = (void*) SysTick_Handler,
/* Configurable interrupts */
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
.pfnOSCCTRL_0_Handler = (void*) OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
.pfnOSCCTRL_1_Handler = (void*) OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
.pfnOSCCTRL_2_Handler = (void*) OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
.pfnOSCCTRL_3_Handler = (void*) OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
.pfnOSCCTRL_4_Handler = (void*) OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
.pfnSUPC_0_Handler = (void*) SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
.pfnSUPC_1_Handler = (void*) SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
.pfnEIC_0_Handler = (void*) EIC_0_Handler, /* 12 EIC_EXTINT_0 */
.pfnEIC_1_Handler = (void*) EIC_1_Handler, /* 13 EIC_EXTINT_1 */
.pfnEIC_2_Handler = (void*) EIC_2_Handler, /* 14 EIC_EXTINT_2 */
.pfnEIC_3_Handler = (void*) EIC_3_Handler, /* 15 EIC_EXTINT_3 */
.pfnEIC_4_Handler = (void*) EIC_4_Handler, /* 16 EIC_EXTINT_4 */
.pfnEIC_5_Handler = (void*) EIC_5_Handler, /* 17 EIC_EXTINT_5 */
.pfnEIC_6_Handler = (void*) EIC_6_Handler, /* 18 EIC_EXTINT_6 */
.pfnEIC_7_Handler = (void*) EIC_7_Handler, /* 19 EIC_EXTINT_7 */
.pfnEIC_8_Handler = (void*) EIC_8_Handler, /* 20 EIC_EXTINT_8 */
.pfnEIC_9_Handler = (void*) EIC_9_Handler, /* 21 EIC_EXTINT_9 */
.pfnEIC_10_Handler = (void*) EIC_10_Handler, /* 22 EIC_EXTINT_10 */
.pfnEIC_11_Handler = (void*) EIC_11_Handler, /* 23 EIC_EXTINT_11 */
.pfnEIC_12_Handler = (void*) EIC_12_Handler, /* 24 EIC_EXTINT_12 */
.pfnEIC_13_Handler = (void*) EIC_13_Handler, /* 25 EIC_EXTINT_13 */
.pfnEIC_14_Handler = (void*) EIC_14_Handler, /* 26 EIC_EXTINT_14 */
.pfnEIC_15_Handler = (void*) EIC_15_Handler, /* 27 EIC_EXTINT_15 */
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
.pfnDMAC_4_Handler = (void*) DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
.pfnEVSYS_4_Handler = (void*) EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 SERCOM0_0 */
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 SERCOM0_1 */
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 SERCOM0_2 */
.pfnSERCOM0_3_Handler = (void*) SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 SERCOM1_0 */
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 SERCOM1_1 */
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 SERCOM1_2 */
.pfnSERCOM1_3_Handler = (void*) SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 SERCOM2_0 */
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 SERCOM2_1 */
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 SERCOM2_2 */
.pfnSERCOM2_3_Handler = (void*) SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 SERCOM3_0 */
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 SERCOM3_1 */
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 SERCOM3_2 */
.pfnSERCOM3_3_Handler = (void*) SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
#ifdef ID_SERCOM4
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 SERCOM4_0 */
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 SERCOM4_1 */
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 SERCOM4_2 */
.pfnSERCOM4_3_Handler = (void*) SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
#else
.pvReserved62 = (void*) (0UL), /* 62 Reserved */
.pvReserved63 = (void*) (0UL), /* 63 Reserved */
.pvReserved64 = (void*) (0UL), /* 64 Reserved */
.pvReserved65 = (void*) (0UL), /* 65 Reserved */
#endif
#ifdef ID_SERCOM5
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 SERCOM5_0 */
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 SERCOM5_1 */
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 SERCOM5_2 */
.pfnSERCOM5_3_Handler = (void*) SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
#else
.pvReserved66 = (void*) (0UL), /* 66 Reserved */
.pvReserved67 = (void*) (0UL), /* 67 Reserved */
.pvReserved68 = (void*) (0UL), /* 68 Reserved */
.pvReserved69 = (void*) (0UL), /* 69 Reserved */
#endif
#ifdef ID_SERCOM6
.pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 SERCOM6_0 */
.pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 SERCOM6_1 */
.pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 SERCOM6_2 */
.pfnSERCOM6_3_Handler = (void*) SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
#else
.pvReserved70 = (void*) (0UL), /* 70 Reserved */
.pvReserved71 = (void*) (0UL), /* 71 Reserved */
.pvReserved72 = (void*) (0UL), /* 72 Reserved */
.pvReserved73 = (void*) (0UL), /* 73 Reserved */
#endif
#ifdef ID_SERCOM7
.pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 SERCOM7_0 */
.pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 SERCOM7_1 */
.pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 SERCOM7_2 */
.pfnSERCOM7_3_Handler = (void*) SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
#else
.pvReserved74 = (void*) (0UL), /* 74 Reserved */
.pvReserved75 = (void*) (0UL), /* 75 Reserved */
.pvReserved76 = (void*) (0UL), /* 76 Reserved */
.pvReserved77 = (void*) (0UL), /* 77 Reserved */
#endif
#ifdef ID_CAN0
.pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network 0 */
#else
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
#endif
#ifdef ID_CAN1
.pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network 1 */
#else
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
#endif
#ifdef ID_USB
.pfnUSB_0_Handler = (void*) USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
.pfnUSB_1_Handler = (void*) USB_1_Handler, /* 81 USB_SOF_HSOF */
.pfnUSB_2_Handler = (void*) USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
.pfnUSB_3_Handler = (void*) USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
#else
.pvReserved80 = (void*) (0UL), /* 80 Reserved */
.pvReserved81 = (void*) (0UL), /* 81 Reserved */
.pvReserved82 = (void*) (0UL), /* 82 Reserved */
.pvReserved83 = (void*) (0UL), /* 83 Reserved */
#endif
#ifdef ID_GMAC
.pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */
#else
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
#endif
.pfnTCC0_0_Handler = (void*) TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
.pfnTCC0_1_Handler = (void*) TCC0_1_Handler, /* 86 TCC0_MC_0 */
.pfnTCC0_2_Handler = (void*) TCC0_2_Handler, /* 87 TCC0_MC_1 */
.pfnTCC0_3_Handler = (void*) TCC0_3_Handler, /* 88 TCC0_MC_2 */
.pfnTCC0_4_Handler = (void*) TCC0_4_Handler, /* 89 TCC0_MC_3 */
.pfnTCC0_5_Handler = (void*) TCC0_5_Handler, /* 90 TCC0_MC_4 */
.pfnTCC0_6_Handler = (void*) TCC0_6_Handler, /* 91 TCC0_MC_5 */
.pfnTCC1_0_Handler = (void*) TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
.pfnTCC1_1_Handler = (void*) TCC1_1_Handler, /* 93 TCC1_MC_0 */
.pfnTCC1_2_Handler = (void*) TCC1_2_Handler, /* 94 TCC1_MC_1 */
.pfnTCC1_3_Handler = (void*) TCC1_3_Handler, /* 95 TCC1_MC_2 */
.pfnTCC1_4_Handler = (void*) TCC1_4_Handler, /* 96 TCC1_MC_3 */
.pfnTCC2_0_Handler = (void*) TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
.pfnTCC2_1_Handler = (void*) TCC2_1_Handler, /* 98 TCC2_MC_0 */
.pfnTCC2_2_Handler = (void*) TCC2_2_Handler, /* 99 TCC2_MC_1 */
.pfnTCC2_3_Handler = (void*) TCC2_3_Handler, /* 100 TCC2_MC_2 */
#ifdef ID_TCC3
.pfnTCC3_0_Handler = (void*) TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
.pfnTCC3_1_Handler = (void*) TCC3_1_Handler, /* 102 TCC3_MC_0 */
.pfnTCC3_2_Handler = (void*) TCC3_2_Handler, /* 103 TCC3_MC_1 */
#else
.pvReserved101 = (void*) (0UL), /* 101 Reserved */
.pvReserved102 = (void*) (0UL), /* 102 Reserved */
.pvReserved103 = (void*) (0UL), /* 103 Reserved */
#endif
#ifdef ID_TCC4
.pfnTCC4_0_Handler = (void*) TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
.pfnTCC4_1_Handler = (void*) TCC4_1_Handler, /* 105 TCC4_MC_0 */
.pfnTCC4_2_Handler = (void*) TCC4_2_Handler, /* 106 TCC4_MC_1 */
#else
.pvReserved104 = (void*) (0UL), /* 104 Reserved */
.pvReserved105 = (void*) (0UL), /* 105 Reserved */
.pvReserved106 = (void*) (0UL), /* 106 Reserved */
#endif
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter 0 */
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter 1 */
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter 2 */
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter 3 */
#ifdef ID_TC4
.pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter 4 */
#else
.pvReserved111 = (void*) (0UL), /* 111 Reserved */
#endif
#ifdef ID_TC5
.pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter 5 */
#else
.pvReserved112 = (void*) (0UL), /* 112 Reserved */
#endif
#ifdef ID_TC6
.pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter 6 */
#else
.pvReserved113 = (void*) (0UL), /* 113 Reserved */
#endif
#ifdef ID_TC7
.pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter 7 */
#else
.pvReserved114 = (void*) (0UL), /* 114 Reserved */
#endif
.pfnPDEC_0_Handler = (void*) PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
.pfnPDEC_1_Handler = (void*) PDEC_1_Handler, /* 116 PDEC_MC_0 */
.pfnPDEC_2_Handler = (void*) PDEC_2_Handler, /* 117 PDEC_MC_1 */
.pfnADC0_0_Handler = (void*) ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */
.pfnADC0_1_Handler = (void*) ADC0_1_Handler, /* 119 ADC0_RESRDY */
.pfnADC1_0_Handler = (void*) ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */
.pfnADC1_1_Handler = (void*) ADC1_1_Handler, /* 121 ADC1_RESRDY */
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
.pfnDAC_0_Handler = (void*) DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
.pfnDAC_1_Handler = (void*) DAC_1_Handler, /* 124 DAC_EMPTY_0 */
.pfnDAC_2_Handler = (void*) DAC_2_Handler, /* 125 DAC_EMPTY_1 */
.pfnDAC_3_Handler = (void*) DAC_3_Handler, /* 126 DAC_RESRDY_0 */
.pfnDAC_4_Handler = (void*) DAC_4_Handler, /* 127 DAC_RESRDY_1 */
#ifdef ID_I2S
.pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
#else
.pvReserved128 = (void*) (0UL), /* 128 Reserved */
#endif
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
#ifdef ID_ICM
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
#else
.pvReserved132 = (void*) (0UL), /* 132 Reserved */
#endif
#ifdef ID_PUKCC
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
#else
.pvReserved133 = (void*) (0UL), /* 133 Reserved */
#endif
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
#ifdef ID_SDHC0
.pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */
#else
.pvReserved135 = (void*) (0UL), /* 135 Reserved */
#endif
#ifdef ID_SDHC1
.pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller 1 */
#else
.pvReserved136 = (void*) (0UL) /* 136 Reserved */
#endif
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
#if __FPU_USED
/* Enable FPU */
SCB->CPACR |= (0xFu << 20);
__DSB();
__ISB();
#endif
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

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/**
* \file
*
* \brief Low-level initialization functions called upon chip startup.
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#include "same51.h"
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (48000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}

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/*
* Ethercat_QSPI.c
*
* Created: 31/07/2021 17:52:21
* Author: Nick-XMG
*/
#include "Ethercat_QSPI.h"
#include <hpl_qspi_config.h>
#include <hpl_sercom_config.h>
#define SQI_READ (0x0B<<16) #define SQI_WRITE (0x02<<16) #define SQI_INC (0x40<<8) #define SQI_DEC (0x80<<8)
#define ECAT_PRAM_RD_DATA 0x0000 #define ECAT_PRAM_WR_DATA 0x0020 #define HW_CFG 0x0074 #define BYTE_TEST 0x0064 #define ECAT_PRAM_RD_ADDR_LEN 0x0308 #define ECAT_PRAM_RD_CMD 0x030C #define ECAT_PRAM_WR_ADDR_LEN 0x0310 #define ECAT_PRAM_WR_CMD 0x0314 #define LAN9252_RDY (1<<27) #define PDRAM_RD_ADDRESS 0x1100 #define PDRAM_RD_LENGTH ECAT_SIZE_RD //do the math later to automatize. fixed to 64 for now. #define PDRAM_WR_ADDRESS 0x1800 #define PDRAM_WR_LENGTH ECAT_SIZE_WR #define PDRAM_LENGTH_MAX 64
#define PDRAM_LENGTH_SHORT 32
#define FIFO_DEPTH 16
#define PDRAM_REG_MAX PDRAM_LENGTH_SHORT/4
#define PRAM_X_ABORT (1<<30)
#define CSR_BUSY 0x80000000
COMPILER_ALIGNED(16)
DmacDescriptor dummy_rx_descriptor;
DmacDescriptor dummy_tx_descriptor;
volatile uint32_t QSPI_tx_buffer[buffer_size]={0};
volatile uint32_t QSPI_rx_buffer[buffer_size]={0};
volatile enum ecat_states ecat_state = wait;
volatile enum ecat_states next_ecat_state = wait;
volatile uint8_t wr_cnt = 0;
volatile uint8_t rd_cnt = 0;
static uint8_t sync_rx_buffer[2*2*buffer_size/3]={0};
static uint8_t sync_tx_buffer[2*2*buffer_size/3]={0xED};
static uint32_t QSPI_cmds[]={0,PRAM_X_ABORT,0,PRAM_X_ABORT,
((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS,CSR_BUSY,
((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX,CSR_BUSY,
((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX*2, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX*2,CSR_BUSY,
};
static uint32_t zero[FIFO_DEPTH]={0};
volatile uint32_t status = 0;
struct _qspi_command rd_cmd = {
.inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
.inst_frame.bits.inst_en = 0,
.inst_frame.bits.data_en = 1,
.inst_frame.bits.addr_en = 1,
.inst_frame.bits.dummy_cycles = 6,
.inst_frame.bits.tfr_type = QSPI_READMEM_ACCESS,
};
struct _qspi_command wr_cmd = {
.inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
.inst_frame.bits.inst_en = 0,
.inst_frame.bits.data_en = 1,
.inst_frame.bits.addr_en = 1,
.inst_frame.bits.dummy_cycles = 0,
.inst_frame.bits.tfr_type = QSPI_WRITEMEM_ACCESS,
};
struct _qspi_command qspi_cmd = {
.inst_frame.bits.width = QSPI_INST1_ADDR1_DATA1,
.inst_frame.bits.inst_en = 1,
.inst_frame.bits.data_en = 0,
.inst_frame.bits.addr_en = 0,
.inst_frame.bits.dummy_cycles = 0,
.instruction = 0x38,
.inst_frame.bits.tfr_type = QSPI_WRITE_ACCESS,
};
struct _qspi_command *spi_cmd= &wr_cmd;
volatile uint8_t tx_complete =3;
volatile uint32_t *ECAT_BYTE_TEST= QSPI_AHB+BYTE_TEST+SQI_READ;
volatile uint32_t *ECAT_FIFO_RD_RD= QSPI_AHB+SQI_READ +ECAT_PRAM_RD_DATA;
//volatile uint32_t *ECAT_FIFO_RD_RD= QSPI_AHB+SQI_READ +SQI_INC+ECAT_PRAM_RD_DATA;
volatile uint32_t *ECAT_FIFO_WR_WR= QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_DATA;
//volatile uint32_t *ECAT_FIFO_WR_WR= QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_DATA;
volatile uint32_t *ECAT_HW_CFG_RD= QSPI_AHB+SQI_READ+HW_CFG;
volatile uint32_t *ECAT_FIFO_RD_ADLEN_WR= QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_RD_ADDR_LEN;
volatile uint32_t *ECAT_FIFO_WR_ADLEN_WR= QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
volatile uint32_t *ECAT_FIFO_WR_ADLEN_RD= QSPI_AHB+SQI_READ+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
volatile uint32_t *ECAT_FIFO_WR_CMD_RD= QSPI_AHB+SQI_READ+ECAT_PRAM_WR_CMD;
volatile uint32_t *ECAT_FIFO_WR_CMD_WR= QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_CMD;
volatile uint32_t *INPUT_ADDRESS ;
volatile uint32_t *OUTPUT_ADDRESS;
volatile uint32_t read_buffer =0;
volatile uint8_t ecat_length= 0;
volatile bool run_ECAT = false;
volatile bool synced = false;
void ECAT_STATE_MACHINE(void){
if ((ecat_state != wait)&(ecat_state != wait2)){
run_ECAT = false;
switch(ecat_state){
case en_SQI:
spi_cmd = &qspi_cmd;
QSPI->INSTRCTRL.bit.INSTR=spi_cmd->instruction;
OUTPUT_ADDRESS = ECAT_FIFO_RD_ADLEN_WR;
INPUT_ADDRESS = &QSPI_cmds[0];
ecat_length = 0;
next_ecat_state = rd_rdy;
break;
case rd_rdy:
if (QSPI_rx_buffer[0]==LAN9252_RDY){
next_ecat_state = abort_fifo;
}
else if (QSPI_rx_buffer[0]== 0xFFFFFFFF){
next_ecat_state = en_SQI;
QSPI_rx_buffer[0] = 0;
}
else{
spi_cmd = &rd_cmd;
OUTPUT_ADDRESS = &QSPI_rx_buffer[0];
INPUT_ADDRESS = ECAT_HW_CFG_RD;
ecat_length = 1;
wr_cnt=0;
}
break;
case abort_fifo:
spi_cmd = &wr_cmd;
OUTPUT_ADDRESS = ECAT_FIFO_WR_CMD_WR;
INPUT_ADDRESS = &QSPI_cmds[1];
ecat_length = 1;
next_ecat_state = dlt_rdram;
wr_cnt=0;
rd_cnt=0;
break;
case dlt_rdram:
spi_cmd = &wr_cmd;
OUTPUT_ADDRESS = ECAT_FIFO_WR_WR;
INPUT_ADDRESS = &zero[0];
//if (wr_cnt >= 1) ecat_length = FIFO_DEPTH/2;
//else ecat_length = FIFO_DEPTH;
ecat_length = FIFO_DEPTH;
next_ecat_state = cf_dlt_rdram;
break;
case cf_dlt_rdram:
spi_cmd = &wr_cmd;
OUTPUT_ADDRESS = ECAT_FIFO_WR_ADLEN_WR;
INPUT_ADDRESS = &QSPI_cmds[4*(wr_cnt+1)];
ecat_length = 2;
if (wr_cnt >= 2) {
next_ecat_state = wait;
wr_cnt =0;
} else {
next_ecat_state = dlt_rdram;
wr_cnt++;
}
break;
case write_fifo:
spi_cmd = &wr_cmd;
OUTPUT_ADDRESS = ECAT_FIFO_WR_WR;
INPUT_ADDRESS = &QSPI_tx_buffer[wr_cnt*FIFO_DEPTH];
/*if (wr_cnt >= 1) ecat_length = FIFO_DEPTH/2;
else ecat_length = FIFO_DEPTH;*/
ecat_length = FIFO_DEPTH;
next_ecat_state = config_fifo;
break;
case config_fifo:
spi_cmd = &wr_cmd;
OUTPUT_ADDRESS = ECAT_FIFO_RD_ADLEN_WR;
INPUT_ADDRESS = &QSPI_cmds[4*(wr_cnt+1)];
ecat_length = 4;
next_ecat_state = read_fifo;
break;
case read_fifo:
spi_cmd = &rd_cmd;
OUTPUT_ADDRESS = &QSPI_rx_buffer[wr_cnt*FIFO_DEPTH];
INPUT_ADDRESS = ECAT_FIFO_RD_RD;
ecat_length = FIFO_DEPTH;
if (wr_cnt >= 2) {
// ecat_length = FIFO_DEPTH/2;
next_ecat_state = wait2;
wr_cnt=0;
}
else {
// ecat_length = FIFO_DEPTH;
next_ecat_state = write_fifo;
wr_cnt++;
}
break;
}
qspi_dma_enable(&ECAT_QSPI);
QSPI->INSTRFRAME.reg = ((*spi_cmd).inst_frame.word);
for (uint8_t i=0;i<ecat_length;i++)
{
*(OUTPUT_ADDRESS+i) = *(INPUT_ADDRESS+i);
}
QSPI->CTRLA.bit.LASTXFER = 1;
ecat_state = next_ecat_state;
}
}
void config_qspi()
{
QSPI->INTENSET.bit.CSRISE = 1;
NVIC_EnableIRQ(QSPI_IRQn);
ecat_state =en_SQI;
}
QSPI_Handler(){
if (QSPI->INTFLAG.bit.CSRISE == 1){
QSPI->INTFLAG.bit.CSRISE = 1;
run_ECAT =true;
}
}

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/*
* EtherCAT_QSPI.h
*
* Created: 31/07/2021 17:51:24
* Author: Nick-XMG
*/
#ifndef ETHERCAT_QSPI_H_
#define ETHERCAT_QSPI_H_
#include "atmel_start.h"
#define ECAT_SIZE_WR 64 //max fifo size
#define ECAT_SIZE_RD ECAT_SIZE_WR
#define ECAT_SIZE_WR_REG ECAT_SIZE_WR/4
#define ECAT_SIZE_RD_REG ECAT_SIZE_WR/4
#define buffer_size 3*ECAT_SIZE_WR_REG //changed to double
#define motor_buffer_size buffer_size/3
extern enum ecat_states {abort_fifo,dlt_rdram,cf_dlt_rdram,write_fifo,config_fifo,read_fifo,wait,wait2,en_SQI,temp,rd_rdy};
extern volatile enum ecat_states ecat_state;
extern volatile enum ecat_states next_ecat_state;
volatile uint32_t QSPI_tx_buffer[buffer_size];
volatile uint32_t QSPI_rx_buffer[buffer_size];
//static uint32_t QSPI_tx_buffer[buffer_size] = {47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,
//31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,
//15,14,13,12,11,10, 9,8,7,6,5,4,3,2,1,0};
//static uint32_t QSPI_rx_buffer[buffer_size] = {0};
extern volatile bool run_ECAT;
void config_qspi(void);
#endif /* ETHERCAT_QSPI_H_ */

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/*
* EtherCAT_SlaveDef.h
*
* Created: 01/08/2021 12:56:16
* Author: Nick-XMG
*/
#ifndef ETHERCAT_SLAVEDEF_H_
#define ETHERCAT_SLAVEDEF_H_
#include "Ethercat_QSPI.h"
//Write To Ecat Total Bytes (XX bytes)
/* Motor 1*/
static volatile uint8_t *M1_Status = (uint8_t *)&QSPI_tx_buffer[0];
static volatile uint8_t *M1_Mode = (((uint8_t *)&QSPI_tx_buffer[0])+1);
static volatile int16_t *M1_Joint_rel_position = (((int16_t *)&QSPI_tx_buffer[0])+1);
static volatile int16_t *M1_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[1]);
static volatile int16_t *M1_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1])+1);
static volatile int16_t *M1_Motor_current_bus = ((int16_t *)&QSPI_tx_buffer[2]);
static volatile int16_t *M1_Motor_currentPhA = (((int16_t *)&QSPI_tx_buffer[2])+1);
static volatile int16_t *M1_Motor_currentPhB = ((int16_t *)&QSPI_tx_buffer[3]);
static volatile int16_t *M1_Motor_currentPhC = (((int16_t *)&QSPI_tx_buffer[3])+1);
static volatile int16_t *M1_Motor__hallState = ((int16_t *)&QSPI_tx_buffer[4]);
static volatile int16_t *M1_Motor_dutyCycle = (((int16_t *)&QSPI_tx_buffer[4])+1);
/* Motor 2*/
static volatile uint8_t *M2_Status = (uint8_t *)&QSPI_tx_buffer[5];
static volatile uint8_t *M2_Mode = (((uint8_t *)&QSPI_tx_buffer[5])+1);
static volatile int16_t *M2_Joint_rel_position = (((int16_t *)&QSPI_tx_buffer[5])+1);
static volatile int16_t *M2_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[6]);
static volatile int16_t *M2_Motor_speed = (((int16_t *)&QSPI_tx_buffer[6])+1);
static volatile int16_t *M2_Motor_current_bus = ((int16_t *)&QSPI_tx_buffer[7]);
static volatile int16_t *M2_Motor_currentPhA = (((int16_t *)&QSPI_tx_buffer[7])+1);
static volatile int16_t *M2_Motor_currentPhB = ((int16_t *)&QSPI_tx_buffer[8]);
static volatile int16_t *M2_Motor_currentPhC = (((int16_t *)&QSPI_tx_buffer[8])+1);
static volatile int16_t *M2_Motor__hallState = ((int16_t *)&QSPI_tx_buffer[9]);
static volatile int16_t *M2_Motor_dutyCycle = (((int16_t *)&QSPI_tx_buffer[9])+1);
/* EMG */
static volatile int16_t *EMG_CH1 = (((int16_t *)&QSPI_tx_buffer[10]));
static volatile int16_t *EMG_CH2 = (((int16_t *)&QSPI_tx_buffer[10])+1);
static volatile int16_t *EMG_CH3 = (((int16_t *)&QSPI_tx_buffer[11]));
static volatile int16_t *EMG_CH4 = (((int16_t *)&QSPI_tx_buffer[11])+1);
static volatile int16_t *EMG_CH5 = (((int16_t *)&QSPI_tx_buffer[12]));
static volatile int16_t *EMG_CH6 = (((int16_t *)&QSPI_tx_buffer[12])+1);
static volatile int16_t *EMG_CH7 = (((int16_t *)&QSPI_tx_buffer[13]));
static volatile int16_t *EMG_CH8 = (((int16_t *)&QSPI_tx_buffer[13])+1);
/* Motor 3*/
static volatile uint8_t *M3_Status = (uint8_t *)&QSPI_tx_buffer[14];
static volatile uint8_t *M3_Mode = (((uint8_t *)&QSPI_tx_buffer[14])+1);
static volatile int16_t *M3_Joint_rel_position = (((int16_t *)&QSPI_tx_buffer[14])+1);
static volatile int16_t *M3_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[15]);
static volatile int16_t *M3_Motor_speed = (((int16_t *)&QSPI_tx_buffer[15])+1);
static volatile int16_t *M3_Motor_current_bus = ((int16_t *)&QSPI_tx_buffer[16]);
static volatile int16_t *M3_Motor_currentPhA = (((int16_t *)&QSPI_tx_buffer[16])+1);
static volatile int16_t *M3_Motor_currentPhB = ((int16_t *)&QSPI_tx_buffer[17]);
static volatile int16_t *M3_Motor_currentPhC = (((int16_t *)&QSPI_tx_buffer[17])+1);
static volatile int16_t *M3_Motor__hallState = ((int16_t *)&QSPI_tx_buffer[18]);
static volatile int16_t *M3_Motor_dutyCycle = (((int16_t *)&QSPI_tx_buffer[18])+1);
/* Motor 4*/
static volatile uint8_t *M4_Status = (uint8_t *)&QSPI_tx_buffer[19];
static volatile uint8_t *M4_Mode = (((uint8_t *)&QSPI_tx_buffer[19])+1);
static volatile int16_t *M4_Joint_rel_position = (((int16_t *)&QSPI_tx_buffer[19])+1);
static volatile int16_t *M4_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[20]);
static volatile int16_t *M4_Motor_speed = (((int16_t *)&QSPI_tx_buffer[20])+1);
static volatile int16_t *M4_Motor_current_bus = ((int16_t *)&QSPI_tx_buffer[21]);
static volatile int16_t *M4_Motor_currentPhA = (((int16_t *)&QSPI_tx_buffer[21])+1);
static volatile int16_t *M4_Motor_currentPhB = ((int16_t *)&QSPI_tx_buffer[22]);
static volatile int16_t *M4_Motor_currentPhC = (((int16_t *)&QSPI_tx_buffer[22])+1);
static volatile int16_t *M4_Motor__hallState = ((int16_t *)&QSPI_tx_buffer[23]);
static volatile int16_t *M4_Motor_dutyCycle = (((int16_t *)&QSPI_tx_buffer[23])+1);
/* IMU */
static volatile int16_t *q_x0 = (((int16_t *)&QSPI_tx_buffer[24]));
static volatile int16_t *q_y0 = (((int16_t *)&QSPI_tx_buffer[24])+1);
static volatile int16_t *q_z0 = (((int16_t *)&QSPI_tx_buffer[25]));
static volatile int16_t *q_w0 = (((int16_t *)&QSPI_tx_buffer[25])+1);
/* EMG */
static volatile int16_t *FSR_CH1 = (((int16_t *)&QSPI_tx_buffer[26]));
static volatile int16_t *FSR_CH2 = (((int16_t *)&QSPI_tx_buffer[26])+1);
static volatile int16_t *FSR_CH3 = (((int16_t *)&QSPI_tx_buffer[27]));
static volatile int16_t *FSR_CH4 = (((int16_t *)&QSPI_tx_buffer[27])+1);
static volatile int16_t *FSR_CH5 = (((int16_t *)&QSPI_tx_buffer[28]));
static volatile int16_t *Pressure_CH1 = (((int16_t *)&QSPI_tx_buffer[28])+1);
static volatile int16_t *Pressure_CH2 = (((int16_t *)&QSPI_tx_buffer[29]));
static volatile int16_t *Pressure_CH3 = (((int16_t *)&QSPI_tx_buffer[29])+1);
//Read From Ecat Total (XX Bytes)
//QSPI_rx_buffer
/* Motor 1*/
static volatile uint8_t *M1_Control_mode = ((uint8_t *)&QSPI_rx_buffer[0]);
static volatile uint8_t *M1_Control_set = (((uint8_t *)&QSPI_rx_buffer[0])+1);
static volatile int16_t *M1_Desired_pos = ((int16_t *)&QSPI_rx_buffer[0]+1);
static volatile int16_t *M1_Desired_speed = ((int16_t *)&QSPI_rx_buffer[1]);
static volatile int16_t *M1_Desired_current = ((int16_t *)&QSPI_rx_buffer[1]+1);
static volatile int16_t *M1_Max_pos = ((int16_t *)&QSPI_rx_buffer[2]);
static volatile int16_t *M1_Max_velocity = ((int16_t *)&QSPI_rx_buffer[2]+1);
static volatile int16_t *M1_Max_current = ((int16_t *)&QSPI_rx_buffer[3]);
static volatile int16_t *M1_Desired_dc = ((int16_t *)&QSPI_rx_buffer[3]+1); //Spare
///* Motor 2*/
static volatile uint8_t *M2_Control_mode = ((uint8_t *)&QSPI_rx_buffer[4]);
static volatile uint8_t *M2_Control_set = (((uint8_t *)&QSPI_rx_buffer[4])+1);
static volatile int16_t *M2_Desired_pos = ((int16_t *)&QSPI_rx_buffer[4]+1);
static volatile int16_t *M2_Desired_speed = ((int16_t *)&QSPI_rx_buffer[5]);
static volatile int16_t *M2_Desired_current = ((int16_t *)&QSPI_rx_buffer[5]+1);
static volatile int16_t *M2_Max_pos = ((int16_t *)&QSPI_rx_buffer[6]);
static volatile int16_t *M2_Max_velocity = ((int16_t *)&QSPI_rx_buffer[6]+1);
static volatile int16_t *M2_Max_current = ((int16_t *)&QSPI_rx_buffer[7]);
static volatile int16_t *M2_Desired_dc = ((int16_t *)&QSPI_rx_buffer[7]+1); //Spare
///* Motor 3*/
static volatile uint8_t *M3_Control_mode = ((uint8_t *)&QSPI_rx_buffer[8]);
static volatile uint8_t *M3_Control_set = (((uint8_t *)&QSPI_rx_buffer[8])+1);
static volatile int16_t *M3_Desired_pos = ((int16_t *)&QSPI_rx_buffer[8]+1);
static volatile int16_t *M3_Desired_speed = ((int16_t *)&QSPI_rx_buffer[9]);
static volatile int16_t *M3_Desired_current = ((int16_t *)&QSPI_rx_buffer[9]+1);
static volatile int16_t *M3_Max_pos = ((int16_t *)&QSPI_rx_buffer[10]);
static volatile int16_t *M3_Max_velocity = ((int16_t *)&QSPI_rx_buffer[10]+1);
static volatile int16_t *M3_Max_current = ((int16_t *)&QSPI_rx_buffer[11]);
static volatile int16_t *M3_Spare = ((int16_t *)&QSPI_rx_buffer[11]+1); //Spare
///* Motor 4*/
static volatile uint8_t *M4_Control_mode = ((uint8_t *)&QSPI_rx_buffer[12]);
static volatile uint8_t *M4_Control_set = (((uint8_t *)&QSPI_rx_buffer[12])+1);
static volatile int16_t *M4_Desired_pos = ((int16_t *)&QSPI_rx_buffer[12]+1);
static volatile int16_t *M4_Desired_speed = ((int16_t *)&QSPI_rx_buffer[13]);
static volatile int16_t *M4_Desired_current = ((int16_t *)&QSPI_rx_buffer[13]+1);
static volatile int16_t *M4_Max_pos = ((int16_t *)&QSPI_rx_buffer[14]);
static volatile int16_t *M4_Max_velocity = ((int16_t *)&QSPI_rx_buffer[14]+1);
static volatile int16_t *M4_Max_current = ((int16_t *)&QSPI_rx_buffer[15]);
static volatile int16_t *M4_Spare = ((int16_t *)&QSPI_rx_buffer[15]+1);//Spare
static void update_telemetry(void)
{
inline int16_t convert_to_mA(volatile float32_t current_PU)
{
return (int16_t)(current_PU*1000.0f);
}
//
//*M1_Status = 0;
//*M1_Mode = 0;
/* Motor 1 */
*M1_Status = Motor1.motor_state.currentstate;
*M1_Joint_rel_position = Motor1.motor_status.Num_Steps;
//*M1_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[1]);
//*M1_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1])+1);
*M1_Motor_current_bus = convert_to_mA(Motor1.Iphase_pu.Bus);
*M1_Motor_currentPhA = convert_to_mA(Motor1.Iphase_pu.A);
*M1_Motor_currentPhB = convert_to_mA(Motor1.Iphase_pu.B);
*M1_Motor_currentPhC = convert_to_mA(Motor1.Iphase_pu.C);
*M1_Motor__hallState = Motor1.motor_status.currentHallPattern;
*M1_Motor_dutyCycle = Motor1.motor_status.duty_cycle;
*M1_Motor_speed = (int16_t)Motor1.motor_status.calc_rpm;
*M1_Joint_abs_position = Motor1.motor_status.actualDirection;
/* Motor 2 */
*M2_Status = Motor2.motor_state.currentstate;
*M2_Joint_rel_position = Motor2.motor_status.Num_Steps;
//*M1_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[1]);
//*M1_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1])+1);
*M2_Motor_current_bus = convert_to_mA( Motor2.Iphase_pu.Bus);
*M2_Motor_currentPhA = convert_to_mA( Motor2.Iphase_pu.A);
*M2_Motor_currentPhB = convert_to_mA( Motor2.Iphase_pu.B);
*M2_Motor_currentPhC = convert_to_mA(Motor2.Iphase_pu.C);
*M2_Motor__hallState = Motor2.motor_status.currentHallPattern;
*M2_Motor_dutyCycle = Motor2.motor_status.duty_cycle;
*M2_Motor_speed = (int16_t)Motor2.motor_status.calc_rpm;
*M2_Joint_abs_position = Motor2.motor_status.actualDirection;
}
static void update_setpoints(void)
{
Motor1.motor_setpoints.desired_position = *M1_Desired_pos;
Motor1.motor_setpoints.desired_speed = *M1_Desired_speed;
Motor1.motor_setpoints.desired_torque = *M1_Desired_current;
Motor1.motor_setpoints.max_current = *M1_Max_current;
Motor1.motor_setpoints.max_torque = *M1_Max_current;
Motor1.motor_setpoints.max_velocity = *M1_Max_velocity;
Motor2.motor_setpoints.desired_position = *M2_Desired_pos;
Motor2.motor_setpoints.desired_speed = *M2_Desired_speed;
Motor2.motor_setpoints.desired_torque = *M2_Desired_current;
Motor2.motor_setpoints.max_current = *M2_Max_current;
Motor2.motor_setpoints.max_torque = *M2_Max_current;
Motor2.motor_setpoints.max_velocity = *M2_Max_velocity;
//volatile uint8_t a = *M1_Control_mode;
//volatile uint8_t b = *M1_Control_set;
//volatile int16_t c = *M1_Desired_pos;
//volatile int16_t d = *M1_Desired_speed;
//volatile int16_t e = *M1_Desired_current;
//volatile int16_t f = *M1_Max_pos;
//volatile int16_t g = *M1_Max_velocity;
//volatile int16_t h = *M1_Max_current;
//volatile int16_t i = *M1_Spare;
//inline float32_t convert_int_to_PU(volatile int16_t input)
//{
//return ((float32_t)(input/1000.0f));
//}
////Motor1.des_mode = 0;
////Motor1.set = 0;
//Motor1.motor_setpoints.desired_position = *desired_position;
//Motor1.motor_setpoints.desired_speed = *desired_speed;
////Motor1.desired_speed = 1500;
//Motor1.motor_setpoints.desired_torque = convert_int_to_PU(*desired_torque);
////Motor1.controllerParam.I_kp = 0;
////Motor1.controllerParam.I_ki = 0;
////Motor1.controllerParam.V_kp = 0;
////Motor1.controllerParam.V_kd = 0;
////Motor1.controllerParam.V_kd = 0;
////Motor1.controllerParam.P_kp = 0;
////Motor1.controllerParam.P_ki = 0;
////Motor1.reductionRatio = 0;
//Motor1.motor_setpoints.max_velocity = *max_velocity;
//Motor1.motor_setpoints.max_current = convert_int_to_PU(*max_current);
//Motor1.motor_setpoints.max_torque = convert_int_to_PU(*max_torque);
////Motor1.Spare1 = 0;
////Motor1.Spare2 = 0;
////Motor1.Spare3 = 0;
////Motor1.Spare4 = 0;
}
static inline void comms_check(void)
{
/* Motor 1*/
*M1_Status = 1;
*M1_Mode = 2;
*M1_Joint_rel_position = -3;
*M1_Joint_abs_position = 4;
*M1_Motor_speed = -5;
*M1_Motor_current_bus = 6;
*M1_Motor_currentPhA = -7;
*M1_Motor_currentPhB = 8;
*M1_Motor_currentPhC = -9;
*M1_Motor__hallState = 10;
*M1_Motor_dutyCycle = -11;
/* Motor 2*/
*M2_Status = 12;
*M2_Mode = 13;
*M2_Joint_rel_position = 14;
*M2_Joint_abs_position = -15;
*M2_Motor_speed = 16;
*M2_Motor_current_bus = -17;
*M2_Motor_currentPhA = 18;
*M2_Motor_currentPhB = -19;
*M2_Motor_currentPhC = 20;
*M2_Motor__hallState = -21;
*M3_Motor_dutyCycle = 22;
/* EMG */
*EMG_CH1 = -23;
*EMG_CH2 = 24;
*EMG_CH3 = -25;
*EMG_CH4 = 26;
*EMG_CH5 = -27;
*EMG_CH6 = 28;
*EMG_CH7 = -29;
*EMG_CH8 = 30;
/* Motor 3*/
*M3_Status = 1;
*M3_Mode = 2;
*M3_Joint_rel_position = -3;
*M3_Joint_abs_position = 4;
*M3_Motor_speed = -5;
*M3_Motor_current_bus = 6;
*M3_Motor_currentPhA = -7;
*M3_Motor_currentPhB = 8;
*M3_Motor_currentPhC = -9;
*M3_Motor__hallState = 10;
*M3_Motor_dutyCycle = -11;
/* Motor 4*/
*M4_Status = 12;
*M4_Mode = 13;
*M4_Joint_rel_position = 14;
*M4_Joint_abs_position = -15;
*M4_Motor_speed = 16;
*M4_Motor_current_bus = -17;
*M4_Motor_currentPhA = 18;
*M4_Motor_currentPhB = -19;
*M4_Motor_currentPhC = 20;
*M4_Motor__hallState = -21;
*M4_Motor_dutyCycle = 22;
/* IMU */
*q_x0 = 23;
*q_y0 = -24;
*q_z0 = 25;
*q_w0 = -26;
/* EMG */
*FSR_CH1 = 27;
*FSR_CH2 = -28;
*FSR_CH3 = 29;
*FSR_CH4 = -30;
*FSR_CH5 = 31;
*Pressure_CH1 = -32;
*Pressure_CH2 = 33;
*Pressure_CH3 = -34;
}
#endif /* ETHERCAT_SLAVEDEF_H_ */

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/*
* master_slave_IF.h
*
* Created: 8/18/2021 4:32:19 PM
* Author: ge37vez
*/
#ifndef MASTER_SLAVE_IF_H_
#define MASTER_SLAVE_IF_H_
#define SLAVE_BUFFER_SIZE 64
static uint8_t SPI_rx_buffer[SLAVE_BUFFER_SIZE] = {0};
static uint8_t SPI_tx_buffer[SLAVE_BUFFER_SIZE] = {0};
//static uint8_t SPI_tx_buffer[SLAVE_BUFFER_SIZE] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,
//18,19,20,21,22,23,24,25,26,27,28,29,30,31};
//tx_buffer
/* Motor 3*/
static volatile uint8_t *M3_Status = (uint8_t *)&SPI_tx_buffer[0]; //1 byte - 0 of 64
static volatile uint8_t *M3_Mode = (uint8_t *)&SPI_tx_buffer[1]; //1 byte - 1 of 64
static volatile int16_t *M3_Joint_rel_position = (int16_t *)&SPI_tx_buffer[2]; //2 byte - 2 of 64
static volatile int16_t *M3_Joint_abs_position = (int16_t *)&SPI_tx_buffer[4]; //2 byte - 4 of 64
static volatile int16_t *M3_Motor_speed = (int16_t *)&SPI_tx_buffer[6]; //2 byte - 6 of 64
static volatile int16_t *M3_Motor_current_bus = (int16_t *)&SPI_tx_buffer[8]; //2 byte - 8 of 64
static volatile int16_t *M3_Motor_currentPhA = (int16_t *)&SPI_tx_buffer[10]; //2 byte - 10 of 64
static volatile int16_t *M3_Motor_currentPhB = (int16_t *)&SPI_tx_buffer[12]; //2 byte - 12 of 64
static volatile int16_t *M3_Motor_currentPhC = (int16_t *)&SPI_tx_buffer[14]; //2 byte - 14 of 64
static volatile int16_t *M3_Motor__hallState = (int16_t *)&SPI_tx_buffer[16]; //2 byte - 16 of 64
static volatile int16_t *M3_Motor_dutyCycle = (int16_t *)&SPI_tx_buffer[18]; //2 byte - 18 of 64
/* Motor 4*/
static volatile uint8_t *M4_Status = (uint8_t *)&SPI_tx_buffer[20]; //1 byte - 20 of 64
static volatile uint8_t *M4_Mode = (uint8_t *)&SPI_tx_buffer[21]; //1 byte - 21 of 64
static volatile int16_t *M4_Joint_rel_position = (int16_t *)&SPI_tx_buffer[22]; //2 byte - 22 of 64
static volatile int16_t *M4_Joint_abs_position = (int16_t *)&SPI_tx_buffer[24]; //2 byte - 24 of 64
static volatile int16_t *M4_Motor_speed = (int16_t *)&SPI_tx_buffer[26]; //2 byte - 26 of 64
static volatile int16_t *M4_Motor_current_bus = (int16_t *)&SPI_tx_buffer[28]; //2 byte - 28 of 64
static volatile int16_t *M4_Motor_currentPhA = (int16_t *)&SPI_tx_buffer[30]; //2 byte - 30 of 64
static volatile int16_t *M4_Motor_currentPhB = (int16_t *)&SPI_tx_buffer[32]; //2 byte - 32 of 64
static volatile int16_t *M4_Motor_currentPhC = (int16_t *)&SPI_tx_buffer[34]; //2 byte - 34 of 64
static volatile int16_t *M4_Motor__hallState = (int16_t *)&SPI_tx_buffer[36]; //2 byte - 36 of 64
static volatile int16_t *M4_Motor_dutyCycle = (int16_t *)&SPI_tx_buffer[38]; //2 byte - 38 of 64
/* IMU */
static volatile int16_t *q_x0 = (int16_t *)&SPI_tx_buffer[40]; //2 byte - 40 of 64
static volatile int16_t *q_y0 = (int16_t *)&SPI_tx_buffer[42]; //2 byte - 42 of 64
static volatile int16_t *q_z0 = (int16_t *)&SPI_tx_buffer[44]; //2 byte - 44 of 64
static volatile int16_t *q_w0 = (int16_t *)&SPI_tx_buffer[46]; //2 byte - 46 of 64
/* EMG */
static volatile int16_t *FSR_CH1 = (int16_t *)&SPI_tx_buffer[48]; //2 byte - 48 of 64
static volatile int16_t *FSR_CH2 = (int16_t *)&SPI_tx_buffer[50]; //2 byte - 50 of 64
static volatile int16_t *FSR_CH3 = (int16_t *)&SPI_tx_buffer[52]; //2 byte - 52 of 64
static volatile int16_t *FSR_CH4 = (int16_t *)&SPI_tx_buffer[54]; //2 byte - 54 of 64
static volatile int16_t *FSR_CH5 = (int16_t *)&SPI_tx_buffer[56]; //2 byte - 56 of 64
static volatile int16_t *Pressure_CH1 = (int16_t *)&SPI_tx_buffer[58]; //2 byte - 58 of 64
static volatile int16_t *Pressure_CH2 = (int16_t *)&SPI_tx_buffer[60]; //2 byte - 60 of 64
static volatile int16_t *Pressure_CH3 = (int16_t *)&SPI_tx_buffer[62]; //2 byte - 62 of 64
//rx_buffer
///* Motor 3*/
static volatile uint8_t *M3_Control_mode = (uint8_t *)&SPI_rx_buffer[0]; //1 byte - 0 of 32
static volatile uint8_t *M3_Control_set = (uint8_t *)&SPI_rx_buffer[1]; //1 byte - 1 of 32
static volatile int16_t *M3_Desired_pos = (int16_t *)&SPI_tx_buffer[2]; //2 byte - 2 of 32
static volatile int16_t *M3_Desired_speed = (int16_t *)&SPI_tx_buffer[4]; //2 byte - 4 of 32
static volatile int16_t *M3_Desired_current = (int16_t *)&SPI_tx_buffer[6]; //2 byte - 6 of 32
static volatile int16_t *M3_Max_pos = (int16_t *)&SPI_tx_buffer[8]; //2 byte - 8 of 32
static volatile int16_t *M3_Max_velocity = (int16_t *)&SPI_tx_buffer[10]; //2 byte - 10 of 32
static volatile int16_t *M3_Max_current = (int16_t *)&SPI_tx_buffer[12]; //2 byte - 12 of 32
static volatile int16_t *M3_Spare = (int16_t *)&SPI_tx_buffer[14]; //2 byte - 14 of 32
///* Motor 4*/
static volatile uint8_t *M4_Control_mode = (int16_t *)&SPI_tx_buffer[16]; //1 byte - 16 of 32
static volatile uint8_t *M4_Control_set = (int16_t *)&SPI_tx_buffer[17]; //1 byte - 17 of 32
static volatile int16_t *M4_Desired_pos = (int16_t *)&SPI_tx_buffer[18]; //2 byte - 18 of 32
static volatile int16_t *M4_Desired_speed = (int16_t *)&SPI_tx_buffer[20]; //2 byte - 20 of 32
static volatile int16_t *M4_Desired_current = (int16_t *)&SPI_tx_buffer[22]; //2 byte - 22 of 32
static volatile int16_t *M4_Max_pos = (int16_t *)&SPI_tx_buffer[24]; //2 byte - 24 of 32
static volatile int16_t *M4_Max_velocity = (int16_t *)&SPI_tx_buffer[26]; //2 byte - 26 of 32
static volatile int16_t *M4_Max_current = (int16_t *)&SPI_tx_buffer[28]; //2 byte - 28 of 32
static volatile int16_t *M4_Spare = (int16_t *)&SPI_tx_buffer[30]; //2 byte - 30 of 32
static void update_telemetry(void)
{
inline int16_t convert_to_mA(volatile float32_t current_PU)
{
return (int16_t)(current_PU*1000.0f);
}
//
//*M3_Status = 0;
//*M3_Mode = 0;
/* Motor 1 */
*M3_Status = Motor1.motor_state.currentstate;
*M3_Joint_rel_position = Motor1.motor_status.Num_Steps;
//*M3_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[1];
//*M3_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1]+1);
*M3_Motor_current_bus = convert_to_mA(Motor1.Iphase_pu.Bus);
*M3_Motor_currentPhA = convert_to_mA(Motor1.Iphase_pu.A);
*M3_Motor_currentPhB = convert_to_mA(Motor1.Iphase_pu.B);
*M3_Motor_currentPhC = convert_to_mA(Motor1.Iphase_pu.C);
*M3_Motor__hallState = Motor1.motor_status.currentHallPattern;
*M3_Motor_dutyCycle = Motor1.motor_status.duty_cycle;
*M3_Motor_speed = (int16_t)Motor1.motor_status.calc_rpm;
*M3_Joint_abs_position = Motor1.motor_status.actualDirection;
/* Motor 2 */
*M4_Status = Motor2.motor_state.currentstate;
*M4_Joint_rel_position = Motor2.motor_status.Num_Steps;
//*M3_Joint_abs_position = ((int16_t *)&QSPI_tx_buffer[1];
//*M3_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1]+1);
*M4_Motor_current_bus = convert_to_mA( Motor2.Iphase_pu.Bus);
*M4_Motor_currentPhA = convert_to_mA( Motor2.Iphase_pu.A);
*M4_Motor_currentPhB = convert_to_mA( Motor2.Iphase_pu.B);
*M4_Motor_currentPhC = convert_to_mA(Motor2.Iphase_pu.C);
*M4_Motor__hallState = Motor2.motor_status.currentHallPattern;
*M4_Motor_dutyCycle = Motor2.motor_status.duty_cycle;
*M4_Motor_speed = (int16_t)Motor2.motor_status.calc_rpm;
*M4_Joint_abs_position = Motor2.motor_status.actualDirection;
}
static void update_setpoints(void)
{
Motor1.motor_setpoints.desired_position = *M3_Desired_pos;
Motor1.motor_setpoints.desired_speed = *M3_Desired_speed;
Motor1.motor_setpoints.desired_torque = *M3_Desired_current;
Motor1.motor_setpoints.max_current = *M3_Max_current;
Motor1.motor_setpoints.max_torque = *M3_Max_current;
Motor1.motor_setpoints.max_velocity = *M3_Max_velocity;
Motor2.motor_setpoints.desired_position = *M4_Desired_pos;
Motor2.motor_setpoints.desired_speed = *M4_Desired_speed;
Motor2.motor_setpoints.desired_torque = *M4_Desired_current;
Motor2.motor_setpoints.max_current = *M4_Max_current;
Motor2.motor_setpoints.max_torque = *M4_Max_current;
Motor2.motor_setpoints.max_velocity = *M4_Max_velocity;
//volatile uint8_t a = *M3_Control_mode;
//volatile uint8_t b = *M3_Control_set;
//volatile int16_t c = *M3_Desired_pos;
//volatile int16_t d = *M3_Desired_speed;
//volatile int16_t e = *M3_Desired_current;
//volatile int16_t f = *M3_Max_pos;
//volatile int16_t g = *M3_Max_velocity;
//volatile int16_t h = *M3_Max_current;
//volatile int16_t i = *M3_Spare;
//inline float32_t convert_int_to_PU(volatile int16_t input)
//{
//return ((float32_t)(input/1000.0f));
//}
////Motor1.des_mode = 0;
////Motor1.set = 0;
//Motor1.motor_setpoints.desired_position = *desired_position;
//Motor1.motor_setpoints.desired_speed = *desired_speed;
////Motor1.desired_speed = 1500;
//Motor1.motor_setpoints.desired_torque = convert_int_to_PU(*desired_torque);
////Motor1.controllerParam.I_kp = 0;
////Motor1.controllerParam.I_ki = 0;
////Motor1.controllerParam.V_kp = 0;
////Motor1.controllerParam.V_kd = 0;
////Motor1.controllerParam.V_kd = 0;
////Motor1.controllerParam.P_kp = 0;
////Motor1.controllerParam.P_ki = 0;
////Motor1.reductionRatio = 0;
//Motor1.motor_setpoints.max_velocity = *max_velocity;
//Motor1.motor_setpoints.max_current = convert_int_to_PU(*max_current);
//Motor1.motor_setpoints.max_torque = convert_int_to_PU(*max_torque);
////Motor1.Spare1 = 0;
////Motor1.Spare2 = 0;
////Motor1.Spare3 = 0;
////Motor1.Spare4 = 0;
}
static inline void comms_check(void)
{
/* Motor 1*/
*M3_Status = 1;
*M3_Mode = 2;
*M3_Joint_rel_position = -3;
*M3_Joint_abs_position = 4;
*M3_Motor_speed = -5;
*M3_Motor_current_bus = 6;
*M3_Motor_currentPhA = -7;
*M3_Motor_currentPhB = 8;
*M3_Motor_currentPhC = -9;
*M3_Motor__hallState = 10;
*M3_Motor_dutyCycle = -11;
/* Motor 2*/
*M4_Status = 12;
*M4_Mode = 13;
*M4_Joint_rel_position = 14;
*M4_Joint_abs_position = -15;
*M4_Motor_speed = 16;
*M4_Motor_current_bus = -17;
*M4_Motor_currentPhA = 18;
*M4_Motor_currentPhB = -19;
*M4_Motor_currentPhC = 20;
*M4_Motor__hallState = -21;
*M4_Motor_dutyCycle = 22;
/* IMU */
*q_x0 = 23;
*q_y0 = -24;
*q_z0 = 25;
*q_w0 = -26;
/* EMG */
*FSR_CH1 = 27;
*FSR_CH2 = -28;
*FSR_CH3 = 29;
*FSR_CH4 = -30;
*FSR_CH5 = 31;
*Pressure_CH1 = -32;
*Pressure_CH2 = 33;
*Pressure_CH3 = -34;
}
#endif /* MASTER_SLAVE_IF_H_ */

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2_Motor_Slave/Motor_Slave/Motor_Slave/arm_math.h Normal file
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2_Motor_Slave/Motor_Slave/Motor_Slave/atmel_start.c Normal file
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#include <atmel_start.h>
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
system_init();
}

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2_Motor_Slave/Motor_Slave/Motor_Slave/atmel_start.h Normal file
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#ifndef ATMEL_START_H_INCLUDED
#define ATMEL_START_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "driver_init.h"
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void);
#ifdef __cplusplus
}
#endif
#endif

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2_Motor_Slave/Motor_Slave/Motor_Slave/atmel_start_pins.h Normal file
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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef ATMEL_START_PINS_H_INCLUDED
#define ATMEL_START_PINS_H_INCLUDED
#include <hal_gpio.h>
// SAME51 has 14 pin functions
#define GPIO_PIN_FUNCTION_A 0
#define GPIO_PIN_FUNCTION_B 1
#define GPIO_PIN_FUNCTION_C 2
#define GPIO_PIN_FUNCTION_D 3
#define GPIO_PIN_FUNCTION_E 4
#define GPIO_PIN_FUNCTION_F 5
#define GPIO_PIN_FUNCTION_G 6
#define GPIO_PIN_FUNCTION_H 7
#define GPIO_PIN_FUNCTION_I 8
#define GPIO_PIN_FUNCTION_J 9
#define GPIO_PIN_FUNCTION_K 10
#define GPIO_PIN_FUNCTION_L 11
#define GPIO_PIN_FUNCTION_M 12
#define GPIO_PIN_FUNCTION_N 13
#define SPI1_MOSI GPIO(GPIO_PORTA, 0)
#define SPI1_SCK GPIO(GPIO_PORTA, 1)
#define ALOG_0 GPIO(GPIO_PORTA, 2)
#define ANAREF_2V48 GPIO(GPIO_PORTA, 3)
#define M1_HALLA GPIO(GPIO_PORTA, 4)
#define M1_HALLB GPIO(GPIO_PORTA, 5)
#define M1_HALLC GPIO(GPIO_PORTA, 6)
#define ECAT_SYNC GPIO(GPIO_PORTA, 7)
#define ECAT_QSPI_MOSI GPIO(GPIO_PORTA, 8)
#define ECAT_QSPI_MISO GPIO(GPIO_PORTA, 9)
#define ECAT_QSPI_DATA2 GPIO(GPIO_PORTA, 10)
#define ECAT_QSPI_DATA3 GPIO(GPIO_PORTA, 11)
#define SPI2_MOSI GPIO(GPIO_PORTA, 12)
#define SPI2_SCK GPIO(GPIO_PORTA, 13)
#define SPI2_SS GPIO(GPIO_PORTA, 14)
#define SPI2_MISO GPIO(GPIO_PORTA, 15)
#define M2_PWMA GPIO(GPIO_PORTA, 16)
#define M2_PWMB GPIO(GPIO_PORTA, 17)
#define M2_PWMC GPIO(GPIO_PORTA, 18)
#define M2_ENA GPIO(GPIO_PORTA, 19)
#define M2_ENB GPIO(GPIO_PORTA, 20)
#define M2_ENC GPIO(GPIO_PORTA, 21)
#define M2_HALLA GPIO(GPIO_PORTA, 22)
#define M2_HALLB GPIO(GPIO_PORTA, 23)
#define M2_HALLC GPIO(GPIO_PORTA, 24)
#define M1_RST GPIO(GPIO_PORTA, 25)
#define M2_RST GPIO(GPIO_PORTA, 27)
#define SPI3_SS GPIO(GPIO_PORTB, 0)
#define SPI3_MISO GPIO(GPIO_PORTB, 1)
#define SPI3_MOSI GPIO(GPIO_PORTB, 2)
#define SPI3_SCK GPIO(GPIO_PORTB, 3)
#define M1_IA GPIO(GPIO_PORTB, 4)
#define M1_IB GPIO(GPIO_PORTB, 5)
#define M2_IA GPIO(GPIO_PORTB, 6)
#define M2_IB GPIO(GPIO_PORTB, 7)
#define half_VREF GPIO(GPIO_PORTB, 8)
#define ALOG_2 GPIO(GPIO_PORTB, 9)
#define ECAT_QSPI_SCK GPIO(GPIO_PORTB, 10)
#define ECAT_QSPI_CS GPIO(GPIO_PORTB, 11)
#define M1_PWMA GPIO(GPIO_PORTB, 12)
#define M1_PWMB GPIO(GPIO_PORTB, 13)
#define M1_PWMC GPIO(GPIO_PORTB, 14)
#define M1_ENA GPIO(GPIO_PORTB, 15)
#define M1_ENB GPIO(GPIO_PORTB, 16)
#define M1_ENC GPIO(GPIO_PORTB, 17)
#define SPI1_CS GPIO(GPIO_PORTB, 22)
#define SPI1_MISO GPIO(GPIO_PORTB, 23)
#define M1_RST_Bar GPIO(GPIO_PORTB, 30)
#define M2_RST_Bar GPIO(GPIO_PORTB, 31)
#endif // ATMEL_START_PINS_H_INCLUDED

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2_Motor_Slave/Motor_Slave/Motor_Slave/bldc.c Normal file
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/*
* bldc.c
*
* Created: 31/07/2021 14:56:17
* Author: Nick-XMG
*/
#include "bldc.h"
#include "statemachine.h"
#include "utilities.h"
#include "Ethercat_SlaveDef.h"
void motor_StateMachine(BLDCMotor_t* const motor)
{
//if (motor->motor_state.fault)
//{
//motor->motor_state.previousstate = motor->motor_state.currentstate;
//motor->motor_state.currentstate = MOTOR_FAULT;
//}
switch (motor->motor_state.currentstate)
{
case MOTOR_INIT: ;
volatile uint8_t currentHall = motor->readHall();
if((currentHall > 6) || (currentHall < 1) ) {
motor->motor_state.fault = MOTOR_HALLSENSORINVALID;
motor->motor_state.currentstate = MOTOR_FAULT;
break;
}
motor->motor_state.previousstate = motor->motor_state.currentstate;
motor->motor_state.currentstate = MOTOR_IDLE;
break;
case MOTOR_IDLE:
//hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw, DISABLE_PATTERN);
motor->motor_state.previousstate = motor->motor_state.currentstate;
//motor->motor_state.currentstate = MOTOR_PVI_CTRL_STATE;
break;
case MOTOR_OPEN_LOOP_STATE:
BLDC_runOpenLoop(motor, *M1_Desired_dc);
calculate_motor_speed(motor);
motor->motor_state.previousstate = motor->motor_state.currentstate;
break;
case MOTOR_V_CTRL_STATE:
calculate_motor_speed(motor);
BLDC_runSpeedCntl(motor, (float32_t)motor->motor_status.calc_rpm, (float32_t)motor->motor_setpoints.desired_speed);
motor->motor_state.previousstate = motor->motor_state.currentstate;
break;
case MOTOR_VI_CTRL_STATE:
switch (motor->regulation_loop_count) {
case 0: /* PWM FREQ / 25 - 1kHz */
case 5: case 10: case 15: case 20:/* PWM FREQ / 5 - 5kHz */
calculate_motor_speed(motor);
BLDC_runSpeedCntl(motor, (float32_t)motor->motor_status.calc_rpm, (float32_t)motor->motor_setpoints.desired_speed);
default: /* PWM FREQ - 25kHz */
select_active_phase(motor);
BLDC_runCurrentCntl(motor,(float32_t)motor->Iphase_pu.Bus, (float32_t)motor->controllers.Pi_Idc.Ref_pu);
break;
} // end switch(regulation_loop_count)
if(motor->regulation_loop_count > 23) motor->regulation_loop_count = 0;
else motor->regulation_loop_count++;
break;
case MOTOR_PVI_CTRL_STATE:
switch (motor->regulation_loop_count) {
case 0: /* PWM FREQ / 25 - 1kHz */
BLDC_runPosCntl(motor, motor->motor_status.Num_Steps, motor->motor_setpoints.desired_position);
case 5: case 10: case 15: case 20:/* PWM FREQ / 5 - 5kHz */
calculate_motor_speed(motor);
BLDC_runSpeedCntl(motor, (float32_t)motor->motor_status.calc_rpm, (float32_t)motor->controllers.Pid_Speed.Ref_pu);
default: /* PWM FREQ - 25kHz */
select_active_phase(motor);
//select_active_phase(&Motor2, Motor2.motor_status.currentHallPattern);
BLDC_runCurrentCntl(motor, motor->Iphase_pu.Bus, motor->controllers.Pi_Idc.Ref_pu);
break;
} // end switch(regulation_loop_count)
if(motor->regulation_loop_count > 23) motor->regulation_loop_count = 0;
else motor->regulation_loop_count++;
break;
} //end switch (motor->motor_state.currentstate)
// ----------------------------------------------------------------------
// Run Commutation
// ----------------------------------------------------------------------
}
void BldcInitStruct(BLDCMotor_t* const motor, BLDCMotor_param_t * const motor_param)
{
// ----------------------------------------------------------------------
// Assign Motor Parameters:
// ----------------------------------------------------------------------
motor->motor_param = motor_param;
// ----------------------------------------------------------------------
// Initialize State Machine:
// ----------------------------------------------------------------------
motor->motor_state.currentstate = MOTOR_INIT;
motor->motor_state.previousstate = MOTOR_INIT;
motor->motor_state.fault = MOTOR_NOFAULT;
// ----------------------------------------------------------------------
// Initialize Status Struct:
// ----------------------------------------------------------------------
motor->motor_status.actualDirection = 0;
motor->motor_status.duty_cycle = 0;
motor->motor_status.calc_rpm = 0;
motor->motor_status.Num_Steps = 0;
motor->motor_status.cur_comm_step = 0;
motor->motor_status.currentHallPattern = 1;
//motor->motor_status.nextHallPattern = 3;
motor->motor_status.speed_average = 0;
motor->motor_status.count = 1;
// ----------------------------------------------------------------------
// Initialize Phase Current Struct:
// ----------------------------------------------------------------------
motor->Iphase_pu.A = 0;
motor->Iphase_pu.B = 0;
motor->Iphase_pu.C = 0;
motor->Iphase_pu.Bus = 0;
// ----------------------------------------------------------------------
// Initialize Timers:
// ----------------------------------------------------------------------
motor->timerflags.pwm_cycle_tic = false;
motor->timerflags.control_loop_tic = false;
motor->timerflags.motor_telemetry_flag = false;
motor->timerflags.control_loop_tic = false;
motor->timerflags.adc_readings_ready_tic = false;
// ----------------------------------------------------------------------
// Current Sensors Calibration offsets:
// ----------------------------------------------------------------------
motor->Voffset_lsb.A = 0;
motor->Voffset_lsb.B = 0;
// ----------------------------------------------------------------------
// Regulation Loop Counter
// ----------------------------------------------------------------------
motor->regulation_loop_count = 0;
// ----------------------------------------------------------------------
// Initialize Bus Voltage:
// ----------------------------------------------------------------------
motor->VdcBus_pu = DEVICE_DC_VOLTAGE_V;
motor->VoneByDcBus_pu = 1.0f/DEVICE_DC_VOLTAGE_V;
// ----------------------------------------------------------------------
// Initialize Setpoints Struct:
// ----------------------------------------------------------------------
motor->motor_setpoints.desiredDirection = 0;
motor->motor_setpoints.desired_torque = 0.0;
motor->motor_setpoints.desired_speed = 0;
motor->motor_setpoints.desired_position = 0;
motor->motor_setpoints.max_current = 0.0;
motor->motor_setpoints.max_torque = 0.0;
motor->motor_setpoints.max_velocity = 0;
motor->motor_setpoints.directionOffset = 0;
//// ------------------------------------------------------------------------------
//// Initialize PI current control
//// ------------------------------------------------------------------------------
PI_objectInit(&motor->controllers.Pi_Idc);
float32_t motorLs_H = motor_param->motor_LQ_H * 2.0f;
float32_t motorRs_OHM = motor_param->motor_RS_Ohm * 2.0f;
motor->controllers.Pi_Idc.Kp = PI_calcKp(motorLs_H, DEVICE_SHUNT_CURRENT_A, DEVICE_DC_VOLTAGE_V, DEVICE_ISR_PERIOD_Sec);
motor->controllers.Pi_Idc.Ki = PI_calcKi(motorRs_OHM, motorLs_H, DEVICE_ISR_PERIOD_Sec);
//// ------------------------------------------------------------------------------
//// Initialize PD Vel control
//// ------------------------------------------------------------------------------
PID_objectInit(&motor->controllers.Pid_Speed);
/* V Control Gains */
//motor->controllers.Pid_Speed.Kp = 0.005f;
//motor->controllers.Pid_Speed.Ki = 0.00001f;
//motor->controllers.Pid_Speed.Kd = 0.001f;
/* VI Control Gains */
//motor->controllers.Pid_Speed.Kp = 0.0002f;
//motor->controllers.Pid_Speed.Ki = 0.0000001f;
motor->controllers.Pid_Speed.Kp = motor_param->controller_param.Pid_Speed.Kp;
motor->controllers.Pid_Speed.Ki = motor_param->controller_param.Pid_Speed.Ki;
//motor->controllers.Pid_Speed.Kp = 0.0005f;
//motor->controllers.Pid_Speed.Ki = 0.0f;
//motor->controllers.Pid_Speed.Kd = 0.0001f;
/* Limits */
motor->controllers.Pid_Speed.OutMax_pu = (motor_param->motor_Max_Current_IDC_A);
motor->controllers.Pid_Speed.OutMin_pu = -(motor_param->motor_Max_Current_IDC_A);
//// ------------------------------------------------------------------------------
//// Initialize PI Position control
//// ------------------------------------------------------------------------------
PI_objectInit(&motor->controllers.Pi_Pos);
//motor->controllers.Pi_Pos.Kp = 40.0f;
//motor->controllers.Pi_Pos.Ki = 0.0f;
motor->controllers.Pi_Pos.Kp = motor_param->controller_param.Pi_Pos.Kp;
motor->controllers.Pi_Pos.Ki = motor_param->controller_param.Pi_Pos.Ki;
motor->controllers.Pi_Pos.OutMax_pu = (motor_param->motor_Max_Spd_RPM);
motor->controllers.Pi_Pos.OutMin_pu = -(motor_param->motor_Max_Spd_RPM);
}
void exec_commutation(BLDCMotor_t* const motor)
{
// ----------------------------------------------------------------------
// Read Motor Hall Sensors
// ----------------------------------------------------------------------
//tic_port(DEBUG_2_PORT);
//motor->motor_status.currentHallPattern = readM1Hall();
volatile uint8_t currentHall = motor->readHall();
motor->motor_status.currentHallPattern = currentHall;
//if ((currentHall == INVALID_HALL_0)||(currentHall == INVALID_HALL_7))
//{
//hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw, DISABLE_PATTERN);
//motor->motor_state.currentstate == MOTOR_FAULT;
//motor->motor_state.fault == MOTOR_HALLSENSORINVALID;
//return;
//}
// ----------------------------------------------------------------------
// Set Pattern Buffers
// ----------------------------------------------------------------------
volatile uint16_t temp_M1 = COMMUTATION_PATTERN[currentHall +
motor->motor_setpoints.directionOffset];
hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw, temp_M1);
// ----------------------------------------------------------------------
// Set Calculated Duty Cycle
// ----------------------------------------------------------------------
hri_tcc_write_CCBUF_CCBUF_bf(motor->motor_param->pwm_desc->device.hw, 0, motor->motor_status.duty_cycle);
volatile uint8_t cur_comm_step = MOTOR_COMMUTATION_STEPS[currentHall];
motor->motor_status.cur_comm_step = cur_comm_step;
volatile int8_t step_change = (cur_comm_step - motor->motor_status.prev_comm_step);
switch(step_change)
{
case 1: case -5:
motor->motor_status.Num_Steps += 1;
motor->motor_status.actualDirection = CW;
//Motor1.motor_setpoints.directionOffset = DIRECTION_CW_OFFSET;
break;
case -1: case 5:
motor->motor_status.Num_Steps -= 1;
motor->motor_status.actualDirection = CCW;
//Motor1.motor_setpoints.directionOffset = DIRECTION_CCW_OFFSET;
break;
default:
// do nothing
break;
}
motor->motor_status.prev_comm_step = cur_comm_step;
//toc_port(DEBUG_2_PORT);
}
//// ------------------------------------------------------------------------------
// Current Selection Based on Hall State
// Direction":
// CW -> Always positive current
// CCW -> Always negative current
//// ------------------------------------------------------------------------------
void select_active_phase(BLDCMotor_t* const Motor)
{
uint8_t hall_state = Motor->motor_status.currentHallPattern;
volatile float32_t phase_current = 0;
switch(hall_state)
{
case 0b001: case 0b011:
phase_current = Motor->Iphase_pu.C;
break;
case 0b010: case 0b110:
phase_current = Motor->Iphase_pu.B;
break;
case 0b100: case 0b101:
phase_current = Motor->Iphase_pu.A;
break;
default :
//phase_current = 0; // Invalid hall code
break;
}
Motor->Iphase_pu.Bus = phase_current;
}
void calculate_motor_speed(BLDCMotor_t* const motor)
{
//tic_port(DEBUG_2_PORT);
volatile uint32_t temp_rpm = 0;
hri_tccount32_read_CC_reg(motor->motor_param->speedtimer_hw, 0); /* Read CC0 but throw away)*/
volatile uint32_t period_after_capture = hri_tccount32_read_CC_reg(motor->motor_param->speedtimer_hw, 1);
if((period_after_capture >= UINT32_MAX)||(period_after_capture == 0)||(period_after_capture > 600000)) {
motor->motor_status.calc_rpm = 0;
} else {
////uint32_t test = (SPEEDFACTOR, period_after_capture);
////temp_rpm = SPEEDFACTOR / period_after_capture;
////tic_port(DEBUG_3_PORT);
temp_rpm = HZ_TO_RPM / (period_after_capture * motor->motor_param->motor_commutationStates);
//temp_rpm = HZ_TO_RPM * period_after_capture;
////toc_port(DEBUG_3_PORT);
//uint32_t muti = DEVICE_SPEEDTC_FREQUENCY_Hz*60;
//temp_rpm = (muti) / (period_after_capture*42);
}
if(motor->motor_status.actualDirection == CCW) /* Changed from CCW */
{
//*motor_speed = -1* Motor1.calc_rpm;
temp_rpm = -1 * temp_rpm;
} else {
//*motor_speed = Motor1.calc_rpm;
temp_rpm = temp_rpm;
}
//motor->motor_status.calc_rpm = (int16_t)temp_rpm;
#ifdef AVERAGE_SPEED_MEASURE
// To avoid noise an average is realized on 8 samples
motor->motor_status.speed_average += temp_rpm;
if(motor->motor_status.count >= n_SAMPLE)
{
motor->motor_status.count = 1;
motor->motor_status.calc_rpm = (motor->motor_status.speed_average >> 3); // divide by 8
//Motor1.motor_status.calc_rpm = (speed_average); // divide by 8
motor->motor_status.speed_average = 0;
//*Spare_byte1 = motorState.actualDirection;
if(motor->motor_status.actualDirection == CCW) /* Changed from CCW */
{
//*motor_speed = -1* Motor1.calc_rpm;
motor->motor_status.calc_rpm = -1* motor->motor_status.calc_rpm;
} else {
//*motor_speed = Motor1.calc_rpm;
motor->motor_status.calc_rpm = motor->motor_status.calc_rpm;
}
return;
}
else motor->motor_status.count++;
#endif
motor->motor_status.calc_rpm = (int16_t)temp_rpm;
//toc_port(DEBUG_2_PORT);
}
//------------------------------------------------------------------------------
// pi current control
//------------------------------------------------------------------------------
void BLDC_runCurrentCntl(BLDCMotor_t *motor, const float32_t curfbk, const float32_t curRef)
{
motor->controllers.Pi_Idc.Fbk_pu = f_clamp(curfbk, -DEVICE_SHUNT_CURRENT_A, DEVICE_SHUNT_CURRENT_A); // Clamped to max current sensor readingspeedfbk;
motor->controllers.Pi_Idc.Ref_pu = f_clamp(curRef, -motor->motor_param->motor_Max_Current_IDC_A,
motor->motor_param->motor_Max_Current_IDC_A); // Clamp desired to Motor Max Current i_ref_clamped;
//*Spare_1 = (int16_t)(motor->controllers.Pi_Idc.Ref_pu * 1000); // Send Req Current to TC
motor->controllers.Pi_Idc.OutMax_pu = motor->VdcBus_pu;
motor->controllers.Pi_Idc.OutMin_pu = -motor->VdcBus_pu;
PI_run_series(&motor->controllers.Pi_Idc);
if(motor->controllers.Pi_Idc.Out_pu > 0) {
motor->motor_setpoints.desiredDirection = 0;
motor->motor_setpoints.directionOffset = 0;
} else {
motor->motor_setpoints.desiredDirection = 1;
motor->motor_setpoints.directionOffset = 8;
}
volatile float32_t duty_pu = f_abs((motor->controllers.Pi_Idc.Out_pu * motor->VoneByDcBus_pu));
motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
// Remove Low duty cycle values
//if(duty_cycle < 80.0) motor->duty_cycle = (uint16_t)0;
//else motor->duty_cycle = (uint16_t)duty_cycle;
}
//// ------------------------------------------------------------------------------
// Speed Control: Input in RPM units (int16_t)
//------------------------------------------------------------------------------
void BLDC_runSpeedCntl(BLDCMotor_t *motor, const float32_t speedfbk, const float32_t speedRef)
{
//tic_port(DEBUG_3_PORT);
motor->controllers.Pid_Speed.Fbk_pu = speedfbk;
motor->controllers.Pid_Speed.Ref_pu = f_clamp(speedRef, -motor->motor_param->motor_Max_Spd_RPM,
motor->motor_param->motor_Max_Spd_RPM);
if (motor->motor_state.currentstate == MOTOR_V_CTRL_STATE)
{
/* Output Pu in Volts (PWM %) */
motor->controllers.Pid_Speed.OutMax_pu = motor->VdcBus_pu;
motor->controllers.Pid_Speed.OutMin_pu = -motor->VdcBus_pu;
PID_run_parallel(&motor->controllers.Pid_Speed);
if(motor->controllers.Pid_Speed.Out_pu > 0) {
motor->motor_setpoints.desiredDirection = 0;
motor->motor_setpoints.directionOffset = 0;
} else {
motor->motor_setpoints.desiredDirection = 1;
motor->motor_setpoints.directionOffset = 8;
}
/* Process unit is Volts */
volatile float32_t duty_pu = f_abs((motor->controllers.Pid_Speed.Out_pu * motor->VoneByDcBus_pu));
volatile float32_t duty_cycle = f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
motor->motor_status.duty_cycle = (uint16_t)duty_cycle;
} else {
/* Pu in Current (Amps) */
motor->controllers.Pid_Speed.OutMax_pu = (motor->motor_param->motor_Max_Current_IDC_A);
motor->controllers.Pid_Speed.OutMin_pu = -(motor->motor_param->motor_Max_Current_IDC_A);
PID_run_parallel(&motor->controllers.Pid_Speed);
motor->controllers.Pi_Idc.Ref_pu = motor->controllers.Pid_Speed.Out_pu;
}
//toc_port(DEBUG_3_PORT);
}
//// ------------------------------------------------------------------------------
// Position Control:Input in Hall step units (int16_t)
//------------------------------------------------------------------------------
void BLDC_runPosCntl(BLDCMotor_t *motor, const int16_t posfbk, const int16_t posRef)
{
/* Output Pu in RPM */
motor->controllers.Pi_Pos.OutMax_pu = motor->motor_param->motor_Max_Spd_RPM;
motor->controllers.Pi_Pos.OutMin_pu = -motor->motor_param->motor_Max_Spd_RPM;
motor->controllers.Pi_Pos.Fbk_pu = posfbk;
motor->controllers.Pi_Pos.Ref_pu = posRef;
PI_run_series(&motor->controllers.Pi_Pos);
motor->controllers.Pid_Speed.Ref_pu = motor->controllers.Pi_Pos.Out_pu;
}
void BLDC_runOpenLoop(BLDCMotor_t *motor, int16_t duty)
{
if (duty < 0){
motor->motor_setpoints.directionOffset = DIRECTION_CCW_OFFSET;
} else {
motor->motor_setpoints.directionOffset = DIRECTION_CW_OFFSET;
}
motor->motor_status.duty_cycle = u_clamp(abs(duty), 0, MAX_PWM);
}
volatile uint8_t readHallSensorM1(void)
{
volatile uint8_t motor_read = 0;
motor_read = (motor_read & M1_HALL_A_MASK) | (uint8_t)((PORT->Group[M1_HALL_A_GROUP].IN.reg & M1_HALL_A_PORT)>>(M1_HALL_A_LSR));
motor_read = (motor_read & M1_HALL_B_MASK) | (uint8_t)((PORT->Group[M1_HALL_B_GROUP].IN.reg & M1_HALL_B_PORT)>>(M1_HALL_B_LSR));
motor_read = (motor_read & M1_HALL_C_MASK) | (uint8_t)((PORT->Group[M1_HALL_C_GROUP].IN.reg & M1_HALL_C_PORT)>>(M1_HALL_C_LSR));
return motor_read;
//
//volatile uint8_t a = gpio_get_pin_level(M1_HALL_A_PIN);
//volatile uint8_t b = gpio_get_pin_level(M1_HALL_B_PIN);
//volatile uint8_t c = gpio_get_pin_level(M1_HALL_C_PIN);
//return ((a << 2) |
//(b << 1) |
//(c << 0));
}
volatile uint8_t readHallSensorM2(void)
{
volatile uint8_t motor_read = 0;
motor_read = (motor_read & M2_HALL_A_MASK) | (uint8_t)((PORT->Group[M2_HALL_A_GROUP].IN.reg & M2_HALL_A_PORT)>>(M2_HALL_A_LSR));
motor_read = (motor_read & M2_HALL_B_MASK) | (uint8_t)((PORT->Group[M2_HALL_B_GROUP].IN.reg & M2_HALL_B_PORT)>>(M2_HALL_B_LSR));
motor_read = (motor_read & M2_HALL_C_MASK) | (uint8_t)((PORT->Group[M2_HALL_C_GROUP].IN.reg & M2_HALL_C_PORT)>>(M2_HALL_C_LSR));
return motor_read;
//if(((motor_read == INVALID_HALL_0) || (motor_read == INVALID_HALL_7))) {
//Motor2.motor_state.fault = MOTOR_HALLSENSORINVALID;
//Motor2.motor_state.currentstate = MOTOR_FAULT;
////applicationStatus.currentstate = APP_FAULT;
//}
//volatile uint8_t a = gpio_get_pin_level(M2_HALL_A_PIN);
//volatile uint8_t b = gpio_get_pin_level(M2_HALL_B_PIN);
//volatile uint8_t c = gpio_get_pin_level(M2_HALL_C_PIN);
//volatile uint8_t motor_read2 = ((a << 2)|(b << 1)|(c << 0));
//return ((a << 2) |
//(b << 1) |
//(c << 0));
}
// ----------------------------------------------------------------------
// Before Power up, Measure and average offset voltage for Current Sensor
// This voltage is subtracted from all reading for Bi-Directional Current
// Measurement
// ----------------------------------------------------------------------
void read_zero_current_offset_value(BLDCMotor_t *motor1, BLDCMotor_t *motor2)
{
uint32_t phase_A_zero_current_offset_temp = 0;
uint32_t phase_B_zero_current_offset_temp = 0;
volatile uint16_t zero_current_offset_temp[2] = {0,0};
uint8_t samples = 32;
uint8_t i;
// ------------------------- Motor 1 ---------------------------------
adc_sync_enable_channel(&ADC_1, 9);
//adc_sync_enable_channel(&ADC_1, 0);
/* Single ended */
//ADC1->INPUTCTRL.reg = 0x1809;
/* Differential */
ADC1->INPUTCTRL.reg = 0x0089;
while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
for (i=0; i<samples; i++)
{
volatile uint16_t zero_current_offset_temp[2] = {0,0};
while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
ADC1->SWTRIG.bit.START = true; /* Start the ADC using a software trigger. */
while (ADC1->INTFLAG.bit.RESRDY == 0); /* Wait for the result ready flag to be set. */
ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY; /* Clear the flag. */
zero_current_offset_temp[0] = ADC1->RESULT.reg; /* Read the value. */
phase_A_zero_current_offset_temp += zero_current_offset_temp[0];
}
/* Set Motor Variables */
motor1->Voffset_lsb.A = phase_A_zero_current_offset_temp/samples;
/* Single ended */
//ADC1->INPUTCTRL.reg = 0x1808;
/* Differential */
ADC1->INPUTCTRL.reg = 0x0088;
while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
for (i=0; i<samples; i++)
{
while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
ADC1->SWTRIG.bit.START = true; /* Start the ADC using a software trigger. */
while (ADC1->INTFLAG.bit.RESRDY == 0); /* Wait for the result ready flag to be set. */
ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY; /* Clear the flag. */
zero_current_offset_temp[1] = ADC1->RESULT.reg; /* Read the value. */
phase_B_zero_current_offset_temp += zero_current_offset_temp[1];
}
/* Set Motor Variables */
motor1->Voffset_lsb.B = phase_B_zero_current_offset_temp/samples;
adc_sync_disable_channel(&ADC_1, 8);
adc_sync_enable_channel(&ADC_1, 7);
//adc_sync_enable_channel(&ADC_1, 0);
phase_A_zero_current_offset_temp = 0;
phase_B_zero_current_offset_temp = 0;
/* Single ended */
//ADC1->INPUTCTRL.reg = 0x1807;
/* Differential */
ADC1->INPUTCTRL.reg = 0x0087;
while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
for (i=0; i<samples; i++)
{
volatile uint16_t zero_current_offset_temp[2] = {0,0};
while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
ADC1->SWTRIG.bit.START = true; /* Start the ADC using a software trigger. */
while (ADC1->INTFLAG.bit.RESRDY == 0); /* Wait for the result ready flag to be set. */
ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY; /* Clear the flag. */
zero_current_offset_temp[0] = ADC1->RESULT.reg; /* Read the value. */
phase_A_zero_current_offset_temp += zero_current_offset_temp[0];
}
/* Set Motor Variables */
motor2->Voffset_lsb.A = phase_A_zero_current_offset_temp/samples;
/* Single ended */
//ADC1->INPUTCTRL.reg = 0x1806;
/* Differential */
ADC1->INPUTCTRL.reg = 0x0086;
while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
for (i=0; i<samples; i++)
{
while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
ADC1->SWTRIG.bit.START = true; /* Start the ADC using a software trigger. */
while (ADC1->INTFLAG.bit.RESRDY == 0); /* Wait for the result ready flag to be set. */
ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY; /* Clear the flag. */
zero_current_offset_temp[1] = ADC1->RESULT.reg; /* Read the value. */
phase_B_zero_current_offset_temp += zero_current_offset_temp[1];
}
/* Set Motor Variables */
motor2->Voffset_lsb.B = phase_B_zero_current_offset_temp/samples;
adc_sync_disable_channel(&ADC_1, 6);
//adc_sync_disable_channel(&ADC_1, 0);
}

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2_Motor_Slave/Motor_Slave/Motor_Slave/bldc.h Normal file
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/*
* bldc.h
*
* Created: 31/07/2021 14:56:02
* Author: Nick-XMG
*/
#ifndef BLDC_H_
#define BLDC_H_
// ----------------------------------------------------------------------
// header files
// ----------------------------------------------------------------------
#include "atmel_start.h"
#include "bldc_types.h"
#include "motorparameters.h"
#include "statemachine.h"
#define PWM_TOP (1000)
#define MAX_PWM (300)
//#define MAX_VEL 3800
#define CW (0) //CBA
#define DIRECTION_CW_OFFSET (0) //CBA
#define CCW (1) //ABC
#define DIRECTION_CCW_OFFSET (8) //CBA
/* if the Hall sensor reads 0x0 or 0x7 that means either one of the hall sensor is damaged or disconnected*/
#define INVALID_HALL_0 (0)
#define INVALID_HALL_7 (7)
//#define AVERAGE_SPEED_MEASURE 1
#define n_SAMPLE 8
// ----------------------------------------------------------------------
// ADC Parameters
// ----------------------------------------------------------------------
#define ADC_VOLTAGE_REFERENCE (3.3f)
#define ADC_RESOLUTION (12)
#define ADC_MAX_COUNTS (1<<ADC_RESOLUTION)
#define ADC_LSB_SIZE (ADC_VOLTAGE_REFERENCE/ADC_MAX_COUNTS)
#define LSB_TO_PU (ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY)
// ----------------------------------------------------------------------
// Define the control and PWM frequencies:
// ----------------------------------------------------------------------
// 16kHz is the maximum frequency according to the calculation duration in the mode run and spin.
#define DEVICE_MCU_FREQUENCY_Hz (120000000U)
#define DEVICE_SPEEDTC_DIV (4U)
#define DEVICE_SPEEDTC_FREQUENCY_Hz (DEVICE_MCU_FREQUENCY_Hz/DEVICE_SPEEDTC_DIV)
#define DEVICE_PWM_FREQUENCY_kHz (25.0f)
#define DEVICE_ISR_FREQUENCY_kHz DEVICE_PWM_FREQUENCY_kHz
#define DEVICE_ISR_PERIOD_Sec (0.001f/DEVICE_ISR_FREQUENCY_kHz)
#define HZ_TO_RPM (DEVICE_SPEEDTC_FREQUENCY_Hz * 60)
//#define HZ_TO_RPM MOTOR_COMUTATION_STATES/(DEVICE_SPEEDTC_FREQUENCY_Hz * 60)
// ----------------------------------------------------------------------
// Define the device quantities (voltage, current, speed)
// ----------------------------------------------------------------------
#define DEVICE_DC_VOLTAGE_V 24.0f // max. ADC bus voltage(PEAK) [V]
#define DEVICE_SHUNT_CURRENT_A 2.5f // phase current(PEAK) [A]
#define CURRENT_SENSOR_SENSITIVITY 0.4f //V/A
#define ONEON_CURRENT_SENSOR_SENSITIVITY 2.5f //V/A
// ----------------------------------------------------------------------
// global variables
// ----------------------------------------------------------------------
static const uint8_t HALL_PATTERN_ARRAY[16] = {0, 5, 3, 1, 6, 4, 2, 0, 0, 3, 6, 2, 5, 1, 4, 0 };
static const uint8_t MOTOR_COMMUTATION_STEPS[8] = {9, 1, 3, 2, 5, 6, 4, 9};
volatile BLDCMotor_t Motor1;
volatile BLDCMotor_t Motor2;
volatile MOTOR_STATE_t Motor1_Status;
volatile MOTOR_STATE_t Motor2_Status;
// ----------------------------------------------------------------------
// functions
// ----------------------------------------------------------------------
void motor_StateMachine(BLDCMotor_t* const motor);
void BldcInitStruct(BLDCMotor_t* const motor, BLDCMotor_param_t* constmotor_param);
void exec_commutation(BLDCMotor_t* const motor);
void select_active_phase(BLDCMotor_t* const Motor);
void calculate_motor_speed(BLDCMotor_t* const motor);
// ----------------------------------------------------------------------
// Static Functions
// ----------------------------------------------------------------------
static void BLDC_runSpeedCntl(BLDCMotor_t *motor, const float32_t speedfbk, const float32_t speedRef);
static void BLDC_runCurrentCntl(BLDCMotor_t *motor, const float32_t curfbk, const float32_t curRef);
static void BLDC_runPosCntl(BLDCMotor_t *motor, int16_t posfbk, int16_t posRef);
static void BLDC_runOpenLoop(BLDCMotor_t *motor, int16_t duty);
volatile uint8_t readHallSensorM1(void);
volatile uint8_t readHallSensorM2(void);
#endif /* BLDC_H_ */

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/*
* bldc_types.h
*
* Created: 8/5/2021 9:40:45 AM
* Author: ge37vez
*/
#ifndef BLDC_TYPES_H_
#define BLDC_TYPES_H_
#include "atmel_start.h"
#include "control.h"
#include "motorparameters.h"
#include "statemachine.h"
// ----------------------------------------------------------------------
// function Pointer
// ----------------------------------------------------------------------
typedef uint8_t (*readHallSensor)(void);
// ----------------------------------------------------------------------
// Type Definitions
// ----------------------------------------------------------------------
volatile typedef struct
{
volatile float32_t A; // Phase A
volatile float32_t B; // Phase B
volatile float32_t C; // Phase C
volatile float32_t Bus; // Currently Active Phase Current
} MOTOR_PHASES_t;
volatile typedef struct
{
volatile int16_t A; // Phase A measured offset
volatile int16_t B; // Phase B measured offset
} MOTOR_phase_offset_t;
volatile typedef struct timerflags
{
volatile bool pwm_cycle_tic;
volatile bool current_loop_tic;
volatile bool control_loop_tic;
volatile bool adc_readings_ready_tic;
volatile bool motor_telemetry_flag;
} TIMERflags_t;
volatile typedef struct
{
volatile uint8_t desiredDirection; //! The desired direction of rotation.
volatile uint8_t directionOffset;
volatile float32_t desired_torque;
volatile int16_t desired_speed;
volatile int16_t desired_position;
volatile float32_t max_torque;
volatile float32_t max_current;
volatile int16_t max_velocity;
} MOTOR_Setpoints;
volatile typedef struct
{
volatile uint8_t actualDirection; //! The actual direction of rotation.
volatile uint16_t duty_cycle;
volatile int16_t calc_rpm;
volatile int16_t Num_Steps;
/* Hall States */
//volatile uint8_t prevHallPattern;
volatile uint8_t currentHallPattern;
//volatile uint8_t nextHallPattern;
/* Commutation State */
volatile uint8_t cur_comm_step;
volatile uint8_t prev_comm_step;
volatile uint32_t speed_average;
volatile uint8_t count;
} MOTOR_Status;
// ----------------------------------------------------------------------
// Main BLDC Struct
// ----------------------------------------------------------------------
volatile typedef struct BLDCmotor
{
/* Hardware */
volatile BLDCMotor_param_t *motor_param;
volatile MOTOR_STATE_t motor_state;
/* Status */
volatile MOTOR_Status motor_status;
/* Measured Values */
volatile MOTOR_PHASES_t Iphase_pu;
volatile MOTOR_phase_offset_t Voffset_lsb;
volatile float32_t VdcBus_pu, VoneByDcBus_pu;
/* Motor Flags */
volatile TIMERflags_t timerflags;
volatile uint8_t regulation_loop_count;
/* Controllers */
volatile MOTOR_Control_Structs controllers;
/* Setpoints */
volatile MOTOR_Setpoints motor_setpoints;
/* Function Pointers*/
volatile readHallSensor readHall;
} BLDCMotor_t;
#endif /* BLDC_TYPES_H_ */

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/*
* configuration.h
*
* Created: 02/08/2021 21:15:49
* Author: Nick-XMG
*/
#ifndef CONFIGURATION_H_
#define CONFIGURATION_H_
// ----------------------------------------------------------------------
// Header Files
// ----------------------------------------------------------------------
#include "atmel_start_pins.h"
#include "bldc.h"
#include "interrupts.h"
#include "MSIF_slave.h"
// ----------------------------------------------------------------------
// ADC DMA Initialization
// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
// ----------------------------------------------------------------------
#define DMAC_CHANNEL_ADC_SEQ 2U
#define DMAC_CHANNEL_ADC_SRAM 3U
/* Single Ended */
//const uint32_t adc_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808};
/* Differential */
const uint32_t adc_seq_regs[4] = {0x0089, 0x0088, 0x0087, 0x0086};
volatile int16_t adc_res[4] = {0};
struct _dma_resource *adc_sram_dma_resource;
struct _dma_resource *adc_dmac_sequence_resource;
// ----------------------------------------------------------------------
// Master / Slave interface Initialization
// ----------------------------------------------------------------------
/* DMA channel for SPI Slave TX and RX */
#define CONF_SERCOM_1_RECEIVE_DMA_CHANNEL 0
#define CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL 1
//static uint8_t tx_buffer[SLAVE_BUFFER_SIZE] = {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, 0xff, 0xff};
/* DMA channel Descriptor */
extern DmacDescriptor _descriptor_section[DMAC_CH_NUM];
extern DmacDescriptor _write_back_section[DMAC_CH_NUM];
// ----------------------------------------------------------------------
// PWM Timer Initialization
// ----------------------------------------------------------------------
inline static void configure_tcc_pwm(void)
{
//gpio_set_pin_pull_mode(M1_HALLA, GPIO_PULL_UP);
//gpio_set_pin_pull_mode(M1_HALLB, GPIO_PULL_UP);
//gpio_set_pin_pull_mode(M1_HALLC, GPIO_PULL_UP);
//gpio_set_pin_pull_mode(M2_HALLA, GPIO_PULL_UP);
//gpio_set_pin_pull_mode(M2_HALLB, GPIO_PULL_UP);
//gpio_set_pin_pull_mode(M2_HALLC, GPIO_PULL_UP);
/* TCC0 */
hri_tcc_set_WEXCTRL_OTMX_bf(TCC0, 0x02);
hri_tcc_set_WAVE_POL0_bit(TCC0);
hri_tcc_set_WAVE_POL1_bit(TCC0);
hri_tcc_set_WAVE_POL2_bit(TCC0);
hri_tcc_set_WAVE_POL3_bit(TCC0);
hri_tcc_set_WAVE_POL4_bit(TCC0);
hri_tcc_set_WAVE_POL5_bit(TCC0);
hri_tcc_write_CC_CC_bf(TCC0, 0, 0);
hri_tcc_write_CC_CC_bf(TCC0, 1, 0);
hri_tcc_write_CC_CC_bf(TCC0, 2, 0);
hri_tcc_write_CC_CC_bf(TCC0, 3, 0);
hri_tcc_write_CC_CC_bf(TCC0, 4, 0);
hri_tcc_write_CC_CC_bf(TCC0, 5, 0);
hri_tcc_write_PER_reg(TCC0,1200);
//hri_tcc_write_CCBUF_CCBUF_bf(TCC0, 0,250);
hri_tcc_write_CTRLA_ENABLE_bit(TCC0, 1 << TCC_CTRLA_ENABLE_Pos);
/* TCC1 */
hri_tcc_set_WEXCTRL_OTMX_bf(TCC1, 0x02);
hri_tcc_write_CC_CC_bf(TCC1, 0, 0);
hri_tcc_write_CC_CC_bf(TCC1, 1, 0);
hri_tcc_write_CC_CC_bf(TCC1, 2, 0);
hri_tcc_write_CC_CC_bf(TCC1, 3, 0);
hri_tcc_write_CC_CC_bf(TCC0, 4, 0);
hri_tcc_write_CC_CC_bf(TCC0, 5, 0);
//
////pwm_set_parameters(&TCC_PWM, 1000, 250);
hri_tcc_set_WAVE_POL0_bit(TCC1);
hri_tcc_set_WAVE_POL1_bit(TCC1);
hri_tcc_set_WAVE_POL2_bit(TCC1);
hri_tcc_set_WAVE_POL3_bit(TCC1);
hri_tcc_set_WAVE_POL4_bit(TCC1);
hri_tcc_set_WAVE_POL5_bit(TCC1);
hri_tcc_write_PER_reg(TCC1,1200);
//hri_tcc_write_CCBUF_CCBUF_bf(TCC1, 0, 250);
hri_tcc_clear_CTRLA_ENABLE_bit(TCC1);
hri_tcc_write_CTRLA_MSYNC_bit(TCC1, true);
//hri_tcc_write_CTRLA_ENABLE_bit(TCC1, 1 << TCC_CTRLA_ENABLE_Pos); /* Enable: enabled */
//pwm_register_callback(&PWM_0, PWM_PERIOD_CB, pwm_cb);
pwm_enable(&PWM_0);
pwm_enable(&PWM_1);
}
inline void configure_adc(void)
{
adc_sync_enable_channel(&ADC_1, 0);
//adc_sync_enable_channel(&ADC_1, 0);
//adc_async_register_callback(&ADC_0, 0, ADC_ASYNC_CONVERT_CB, adc_cb);
//adc_async_register_callback(&ADC_1, 0, ADC_ASYNC_CONVERT_CB, convert_cb_ADC_1);
//adc_async_start_conversion(&ADC_0);
//adc_async_start_conversion(&ADC_1);
}
inline static void adc_init_dma(void)
{
adc_sram_dmac_init();
adc_dmac_sequence_init();
hri_adc_set_DSEQCTRL_INPUTCTRL_bit(ADC1);
hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC1);
}
inline void adc_dmac_sequence_init()
{
/* Configure the DMAC source address, destination address,
* next descriptor address, data count and Enable the DMAC Channel
*/
_dma_set_source_address(DMAC_CHANNEL_ADC_SEQ, (const void *)adc_seq_regs);
_dma_set_destination_address(DMAC_CHANNEL_ADC_SEQ, (const void *)&ADC1->DSEQDATA.reg);
_dma_set_data_amount(DMAC_CHANNEL_ADC_SEQ, 4);
_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SEQ, DMAC_CHANNEL_ADC_SEQ);
_dma_enable_transaction(DMAC_CHANNEL_ADC_SEQ, false);
//_dma_get_channel_resource(&adc_dmac_sequence_resource, DMAC_CHANNEL_ADC_SEQ);
//adc_dmac_sequence_resource[0].dma_cb.error = dummy2;
//adc_dmac_sequence_resource[0].dma_cb.suspend = dummy3;
//adc_dmac_sequence_resource[0].dma_cb.transfer_done = dummy4;
hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[DMAC_CHANNEL_ADC_SEQ], 0x01); //Suspend
}
inline void adc_sram_dmac_init()
{
/* Configure the DMAC source address, destination address,
* next descriptor address, data count and Enable the DMAC Channel */
_dma_set_source_address(DMAC_CHANNEL_ADC_SRAM, (const void *)&ADC1->RESULT.reg);
_dma_set_destination_address(DMAC_CHANNEL_ADC_SRAM, (const void *)adc_res);
_dma_set_data_amount(DMAC_CHANNEL_ADC_SRAM, 4);
_dma_set_irq_state(DMAC_CHANNEL_ADC_SRAM, DMA_TRANSFER_COMPLETE_CB, true);
_dma_get_channel_resource(&adc_sram_dma_resource, DMAC_CHANNEL_ADC_SRAM);
adc_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback;
_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SRAM, DMAC_CHANNEL_ADC_SRAM);
_dma_enable_transaction(DMAC_CHANNEL_ADC_SRAM, false);
}
static void spi_slave_tx_complete_cb(struct _dma_resource *const resource)
{
//hri_sercomspi_clear_INTEN_RXC_bit((SercomSpi *)(SPI_0.dev.prvt));
//tx_buffer[63] += 1;
//_dma_enable_transaction(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, false);
//_dma_enable_transaction(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, false);
//spi_slave_rx_complete = true;
}
void boardToBoardTransferInit(void)
{
hri_sercomspi_set_CTRLB_PLOADEN_bit(SPI_1_MSIF.dev.prvt);
spi_s_sync_enable(&SPI_1_MSIF);
}
void init_spi_slave_dma_descriptors()
{
_dma_set_source_address(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
_dma_set_destination_address(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, &SPI_rx_buffer[0]);
_dma_set_data_amount(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, SLAVE_BUFFER_SIZE);
_dma_set_source_address(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, &SPI_tx_buffer[0]);
_dma_set_destination_address(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
_dma_set_data_amount(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, SLAVE_BUFFER_SIZE);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_RECEIVE_DMA_CHANNEL]);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL]);
/* callback */
struct _dma_resource *resource_rx, *resource_tx;
_dma_get_channel_resource(&resource_rx, CONF_SERCOM_1_RECEIVE_DMA_CHANNEL);
_dma_get_channel_resource(&resource_tx, CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL);
//resource_rx->dma_cb.transfer_done = spi_slave_rx_complete_cb;
resource_tx->dma_cb.transfer_done = spi_slave_tx_complete_cb;
/* Enable DMA transfer complete interrupt */
//_dma_set_irq_state(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
}
/* Enable SPI slave select interrupt */
void spi_s_sync_enable_ss_detect(void *hw, bool state)
{
NVIC_DisableIRQ((IRQn_Type)SERCOM1_1_IRQn);
NVIC_ClearPendingIRQ((IRQn_Type)SERCOM1_1_IRQn);
NVIC_EnableIRQ((IRQn_Type)SERCOM1_1_IRQn);
if (state) {
hri_sercomspi_set_INTEN_TXC_bit(hw);
hri_sercomspi_set_INTEN_SSL_bit(hw);
//hri_sercomspi_set_INTEN_SSL_bit(hw);
//SERCOM_SPI_INTENSET_SSL
} else {
hri_sercomspi_clear_INTEN_TXC_bit(hw);
//hri_sercomspi_clear_INTEN_SSL_bit(hw);
}
}
#endif /* CONFIGURATION_H_ */

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/*
* pi.h
*
* Created: 01/02/2021 21:36:11
* Author: Nick-XMG
*/
#ifndef CONTROL_H_
#define CONTROL_H_
// ----------------------------------------------------------------------
// history
// ----------------------------------------------------------------------
// 01.02.2021 - initial Revision
// ----------------------------------------------------------------------
// header files
// ----------------------------------------------------------------------
#include "arm_math.h"
#include "atmel_start.h"
#include "utilities.h"
// ----------------------------------------------------------------------
// #defines
// ----------------------------------------------------------------------
// ----------------------------------------------------------------------
// global variables
// ----------------------------------------------------------------------
#ifdef __cplusplus
extern "C" {
#endif
/* PI Structure */
typedef volatile struct
{
volatile float32_t Kp; // the proportional gain for the PI controller
volatile float32_t Ki; // the integral gain for the PI controller
volatile float32_t Ref_pu; // the reference value [pu]
volatile float32_t Fbk_pu; // the feedback value [pu]
volatile float32_t Ff_pu; // the feedForward value [pu]
volatile float32_t OutMin_pu; // the saturation low limit for the controller output [pu]
volatile float32_t OutMax_pu; // the saturation high limit for the controller output [pu]
volatile float32_t Out_pu; // the controller output [pu]
volatile float32_t Ui; // the integrator value for the PI controller
volatile float32_t error; // the integrator value for the PI controller
volatile bool SatFlag; // flag to signal controller saturation
} PI_t;
/* PID Structure */
typedef volatile struct
{
volatile float32_t Kp; //!< the proportional gain for the PID controller
volatile float32_t Ki; //!< the integral gain for the PID controller
volatile float32_t Kd; //!< the derivative gain for the PID controller
volatile float32_t Ref_pu; //!< the reference input value
volatile float32_t Fbk_pu; //!< the feedback input value
volatile float32_t Ff_pu; //!< the feedforward input value
volatile float32_t OutMin_pu; //!< the minimum output value allowed for the PID controller
volatile float32_t OutMax_pu; //!< the maximum output value allowed for the PID controller
volatile float32_t Out_pu; // the controller output [pu]
volatile float32_t Ui; //!< the integrator start value for the PID controller
volatile float32_t Ud;
volatile float32_t error; // the integrator value for the PI controller
//FILTER_FO_Handle derFilterHandle; //!< the derivative filter handle
//FILTER_FO_Obj derFilter; //!< the derivative filter object
} PID_t;
volatile typedef struct
{
volatile PI_t Pi_Idc;
volatile PID_t Pid_Speed;
volatile PI_t Pi_Pos;
} MOTOR_Control_Structs;
// ----------------------------------------------------------------------
// functions
// ----------------------------------------------------------------------
// function to set default values for the object
//inline float32_t clamp(const float32_t d, const float32_t min, const float32_t max) {
//const float32_t t = d < min ? min : d;
//return t > max ? max : t;
//}
static inline void PI_objectInit(volatile PI_t *pPi_obj)
{
PI_t *obj = (PI_t *)pPi_obj;
// Function initializes the object with default values
//fix16_t Kp = fix16_from_float32_t(1.0);
obj->Kp = 0.0f;
obj->Ki = 0.0f;
obj->Fbk_pu = 0.0f;
obj->Ref_pu = 0.0f;
obj->Ff_pu = 0.0f;
obj->Out_pu = 0.0f;
obj->OutMax_pu = 0.0f;
obj->OutMin_pu = 0.0f;
obj->Ui = 0.0f;
obj->SatFlag = false;
}
static inline void PID_objectInit(volatile PID_t *pPiD_obj)
{
PID_t *obj = (PID_t *)pPiD_obj;
// Function initializes the object with default values
//fix16_t Kp = fix16_from_float32_t(1.0);
obj->Kp = 0.0f;
obj->Ki = 0.0f;
obj->Kd = 0.0f;
obj->Fbk_pu = 0.0f;
obj->Ref_pu = 0.0f;
obj->Ff_pu = 0.0f;
obj->Out_pu = 0.0f;
obj->OutMax_pu = 0.0f;
obj->OutMin_pu = 0.0f;
obj->Ui = 0.0f;
obj->Ud = 0.0f;
}
// ----------------------------------------------------------------------
// PI Calculation
// ----------------------------------------------------------------------
static inline void PI_run_series(volatile PI_t *pPi_obj)
{
PI_t *obj = (PI_t *)pPi_obj;
volatile float32_t Up;
// Compute the controller error
obj->error = obj->Ref_pu - obj->Fbk_pu;
// Compute the proportional term
Up = obj->Kp *obj->error;
// Compute the integral term in series form and saturate
obj->Ui = f_clamp((obj->Ui + (obj->Ki * Up)), obj->OutMin_pu, obj->OutMax_pu);
// Saturate the output
obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);
}
static inline void PI_run_parallel(volatile PI_t *pPi_obj)
{
PI_t *obj = (PI_t *)pPi_obj;
volatile float32_t Up;
// Compute the controller error
obj->error = obj->Ref_pu - obj->Fbk_pu;
// Compute the proportional term
Up = obj->Kp * obj->error;
// Compute the integral term in parallel form and saturate
obj->Ui = f_clamp((obj->Ui + (obj->Ki * obj->error)), obj->OutMin_pu, obj->OutMax_pu);
obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu); // Saturate the output
} // end of PI_run_parallel() function
// ----------------------------------------------------------------------
// PID Calculation
// ----------------------------------------------------------------------
static inline void PID_run_series(volatile PID_t *pPid_obj)
{
PID_t *obj = (PID_t *)pPid_obj;
volatile float32_t Up, Ud_tmp;
// Compute the controller error
obj->error = obj->Ref_pu - obj->Fbk_pu;
// Compute the proportional term
Up = obj->Kp * obj->error;
if(obj->Ki>0.0f){
// Compute the integral term in parallel form and saturate
obj->Ui = f_clamp((obj->Ui + (obj->Ki * Up)), obj->OutMin_pu, obj->OutMax_pu);
}
Ud_tmp = obj->Kd * obj->Ui; // Compute the derivative term
obj->Ud = Ud_tmp; // Replace with filter
obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ud + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu); // Saturate the output
}
static inline void PID_run_parallel(volatile PID_t *pPid_obj)
{
PID_t *obj = (PID_t *)pPid_obj;
volatile float32_t Up, Ud_tmp;
// Compute the controller error
obj->error = obj->Ref_pu - obj->Fbk_pu;
// Compute the proportional term
Up = obj->Kp * obj->error;
if(obj->Ki>0.0f){
// Compute the integral term in parallel form and saturate
obj->Ui = f_clamp((obj->Ui + (obj->Ki * obj->error)), obj->OutMin_pu, obj->OutMax_pu);
}
Ud_tmp = obj->Kd * obj->error; // Compute the derivative term
obj->Ud = Ud_tmp; // Replace with filter
obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ud + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu); // Saturate the output
}
// ----------------------------------------------------------------------
// Calculate Current Parameters
// ----------------------------------------------------------------------
static inline float32_t PI_calcKp(const float32_t Ls_H, const float32_t deviceCurrent_A, const float32_t deviceVoltage_V,
const float32_t deviceCtrlPeriode_Sec)
{
// calculation is based on "Betragsoptimum"
// Kp = Ls/(2*tau)
float32_t x1;
float32_t y1;
float32_t Kp;
// multiplication with deviceCurrent_A is to get per unit values
x1 = (float32_t)(Ls_H * deviceCurrent_A);
y1 = (float32_t)(2.0f * deviceCtrlPeriode_Sec);
// multiplication with deviceVoltage_V is to get per unit values
y1 = (float32_t)(y1 * deviceVoltage_V);
Kp = (x1 / y1);
return Kp;
}
static inline float32_t PI_calcKi(const float32_t Rs_Ohm, const float32_t Ls_H, const float32_t deviceCtrlPeriode_Sec)
{
// calculation is based on "TI - MotorWare's documentation"
float32_t RsByLs = (float32_t)(Rs_Ohm / Ls_H);
float32_t Ki = RsByLs * deviceCtrlPeriode_Sec;
//fix16_t Ki = 0;
return Ki;
}
// ----------------------------------------------------------------------
// end of file
// ----------------------------------------------------------------------
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif /* BLDC_PI_H_ */

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_init.h"
#include <peripheral_clk_config.h>
#include <utils.h>
#include <hal_init.h>
#include <hpl_adc_base.h>
#include <hpl_adc_base.h>
struct spi_m_sync_descriptor SPI_3;
struct timer_descriptor TIMER_0;
struct adc_sync_descriptor ADC_0;
struct adc_sync_descriptor ADC_1;
struct qspi_dma_descriptor ECAT_QSPI;
struct spi_s_sync_descriptor SPI_1_MSIF;
struct spi_m_async_descriptor SPI_2;
struct pwm_descriptor PWM_0;
struct pwm_descriptor PWM_1;
void ADC_0_PORT_init(void)
{
// Disable digital pin circuitry
gpio_set_pin_direction(ALOG_0, GPIO_DIRECTION_OFF);
gpio_set_pin_function(ALOG_0, PINMUX_PA02B_ADC0_AIN0);
// Disable digital pin circuitry
gpio_set_pin_direction(ALOG_2, GPIO_DIRECTION_OFF);
gpio_set_pin_function(ALOG_2, PINMUX_PB09B_ADC0_AIN3);
}
void ADC_0_CLOCK_init(void)
{
hri_mclk_set_APBDMASK_ADC0_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void ADC_0_init(void)
{
ADC_0_CLOCK_init();
ADC_0_PORT_init();
adc_sync_init(&ADC_0, ADC0, (void *)NULL);
}
void ADC_1_PORT_init(void)
{
// Disable digital pin circuitry
gpio_set_pin_direction(half_VREF, GPIO_DIRECTION_OFF);
gpio_set_pin_function(half_VREF, PINMUX_PB08B_ADC1_AIN0);
// Disable digital pin circuitry
gpio_set_pin_direction(M1_IA, GPIO_DIRECTION_OFF);
gpio_set_pin_function(M1_IA, PINMUX_PB04B_ADC1_AIN6);
// Disable digital pin circuitry
gpio_set_pin_direction(M1_IB, GPIO_DIRECTION_OFF);
gpio_set_pin_function(M1_IB, PINMUX_PB05B_ADC1_AIN7);
// Disable digital pin circuitry
gpio_set_pin_direction(M2_IA, GPIO_DIRECTION_OFF);
gpio_set_pin_function(M2_IA, PINMUX_PB06B_ADC1_AIN8);
// Disable digital pin circuitry
gpio_set_pin_direction(M2_IB, GPIO_DIRECTION_OFF);
gpio_set_pin_function(M2_IB, PINMUX_PB07B_ADC1_AIN9);
}
void ADC_1_CLOCK_init(void)
{
hri_mclk_set_APBDMASK_ADC1_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, ADC1_GCLK_ID, CONF_GCLK_ADC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void ADC_1_init(void)
{
ADC_1_CLOCK_init();
ADC_1_PORT_init();
adc_sync_init(&ADC_1, ADC1, (void *)NULL);
}
void DIGITAL_GLUE_LOGIC_0_PORT_init(void)
{
gpio_set_pin_function(M1_HALLA, PINMUX_PA04N_CCL_IN0);
gpio_set_pin_function(M1_HALLB, PINMUX_PA05N_CCL_IN1);
gpio_set_pin_function(M1_HALLC, PINMUX_PA06N_CCL_IN2);
gpio_set_pin_function(M2_HALLA, PINMUX_PA22N_CCL_IN6);
gpio_set_pin_function(M2_HALLB, PINMUX_PA23N_CCL_IN7);
gpio_set_pin_function(M2_HALLC, PINMUX_PA24N_CCL_IN8);
}
void DIGITAL_GLUE_LOGIC_0_CLOCK_init(void)
{
hri_mclk_set_APBCMASK_CCL_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, CCL_GCLK_ID, CONF_GCLK_CCL_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void DIGITAL_GLUE_LOGIC_0_init(void)
{
DIGITAL_GLUE_LOGIC_0_CLOCK_init();
custom_logic_init();
DIGITAL_GLUE_LOGIC_0_PORT_init();
}
void EXTERNAL_IRQ_0_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBAMASK_EIC_bit(MCLK);
// Set pin direction to input
gpio_set_pin_direction(ECAT_SYNC, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(ECAT_SYNC,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_SYNC, PINMUX_PA07A_EIC_EXTINT7);
// Set pin direction to input
gpio_set_pin_direction(M1_RST_Bar, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(M1_RST_Bar,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(M1_RST_Bar, PINMUX_PB30A_EIC_EXTINT14);
// Set pin direction to input
gpio_set_pin_direction(M2_RST_Bar, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(M2_RST_Bar,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(M2_RST_Bar, PINMUX_PB31A_EIC_EXTINT15);
ext_irq_init();
}
void EVENT_SYSTEM_0_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_1, CONF_GCLK_EVSYS_CHANNEL_1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_2, CONF_GCLK_EVSYS_CHANNEL_2_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);
event_system_init();
}
void ECAT_QSPI_PORT_init(void)
{
// Set pin direction to input
gpio_set_pin_direction(ECAT_QSPI_CS, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(ECAT_QSPI_CS,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_QSPI_CS, PINMUX_PB11H_QSPI_CS);
gpio_set_pin_direction(ECAT_QSPI_MOSI,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(ECAT_QSPI_MOSI,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(ECAT_QSPI_MOSI,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_QSPI_MOSI,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA08H_QSPI_DATA0"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
// <GPIO_PIN_FUNCTION_I"> I
// <GPIO_PIN_FUNCTION_J"> J
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA08H_QSPI_DATA0);
gpio_set_pin_direction(ECAT_QSPI_MISO,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(ECAT_QSPI_MISO,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(ECAT_QSPI_MISO,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_QSPI_MISO,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA09H_QSPI_DATA1"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
// <GPIO_PIN_FUNCTION_I"> I
// <GPIO_PIN_FUNCTION_J"> J
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA09H_QSPI_DATA1);
gpio_set_pin_direction(ECAT_QSPI_DATA2,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(ECAT_QSPI_DATA2,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(ECAT_QSPI_DATA2,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_QSPI_DATA2,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA10H_QSPI_DATA2"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
// <GPIO_PIN_FUNCTION_I"> I
// <GPIO_PIN_FUNCTION_J"> J
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA10H_QSPI_DATA2);
gpio_set_pin_direction(ECAT_QSPI_DATA3,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(ECAT_QSPI_DATA3,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(ECAT_QSPI_DATA3,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_QSPI_DATA3,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA11H_QSPI_DATA3"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
// <GPIO_PIN_FUNCTION_I"> I
// <GPIO_PIN_FUNCTION_J"> J
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA11H_QSPI_DATA3);
// Set pin direction to input
gpio_set_pin_direction(ECAT_QSPI_SCK, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(ECAT_QSPI_SCK,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_QSPI_SCK, PINMUX_PB10H_QSPI_SCK);
}
void ECAT_QSPI_CLOCK_init(void)
{
hri_mclk_set_AHBMASK_QSPI_bit(MCLK);
hri_mclk_set_AHBMASK_QSPI_2X_bit(MCLK);
hri_mclk_set_APBCMASK_QSPI_bit(MCLK);
}
void ECAT_QSPI_init(void)
{
ECAT_QSPI_CLOCK_init();
qspi_dma_init(&ECAT_QSPI, QSPI);
ECAT_QSPI_PORT_init();
}
void SPI_1_MSIF_PORT_init(void)
{
// Set pin direction to input
gpio_set_pin_direction(SPI1_MOSI, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(SPI1_MOSI,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(SPI1_MOSI, PINMUX_PA00D_SERCOM1_PAD0);
gpio_set_pin_level(SPI1_SCK,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(SPI1_SCK, GPIO_DIRECTION_OUT);
gpio_set_pin_function(SPI1_SCK, PINMUX_PA01D_SERCOM1_PAD1);
// Set pin direction to input
gpio_set_pin_direction(SPI1_CS, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(SPI1_CS,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(SPI1_CS, PINMUX_PB22C_SERCOM1_PAD2);
gpio_set_pin_level(SPI1_MISO,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(SPI1_MISO, GPIO_DIRECTION_OUT);
gpio_set_pin_function(SPI1_MISO, PINMUX_PB23C_SERCOM1_PAD3);
}
void SPI_1_MSIF_CLOCK_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBAMASK_SERCOM1_bit(MCLK);
}
void SPI_1_MSIF_init(void)
{
SPI_1_MSIF_CLOCK_init();
spi_s_sync_init(&SPI_1_MSIF, SERCOM1);
SPI_1_MSIF_PORT_init();
}
void SPI_2_PORT_init(void)
{
gpio_set_pin_level(SPI2_MOSI,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(SPI2_MOSI, GPIO_DIRECTION_OUT);
gpio_set_pin_function(SPI2_MOSI, PINMUX_PA12C_SERCOM2_PAD0);
gpio_set_pin_level(SPI2_SCK,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(SPI2_SCK, GPIO_DIRECTION_OUT);
gpio_set_pin_function(SPI2_SCK, PINMUX_PA13C_SERCOM2_PAD1);
// Set pin direction to input
gpio_set_pin_direction(SPI2_MISO, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(SPI2_MISO,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(SPI2_MISO, PINMUX_PA15C_SERCOM2_PAD3);
}
void SPI_2_CLOCK_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
}
void SPI_2_init(void)
{
SPI_2_CLOCK_init();
spi_m_async_init(&SPI_2, SERCOM2);
SPI_2_PORT_init();
}
void SPI_3_PORT_init(void)
{
gpio_set_pin_level(SPI3_MOSI,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(SPI3_MOSI, GPIO_DIRECTION_OUT);
gpio_set_pin_function(SPI3_MOSI, PINMUX_PB02D_SERCOM5_PAD0);
gpio_set_pin_level(SPI3_SCK,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(SPI3_SCK, GPIO_DIRECTION_OUT);
gpio_set_pin_function(SPI3_SCK, PINMUX_PB03D_SERCOM5_PAD1);
// Set pin direction to input
gpio_set_pin_direction(SPI3_MISO, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(SPI3_MISO,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(SPI3_MISO, PINMUX_PB01D_SERCOM5_PAD3);
}
void SPI_3_CLOCK_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_CORE, CONF_GCLK_SERCOM5_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_SLOW, CONF_GCLK_SERCOM5_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBDMASK_SERCOM5_bit(MCLK);
}
void SPI_3_init(void)
{
SPI_3_CLOCK_init();
spi_m_sync_init(&SPI_3, SERCOM5);
SPI_3_PORT_init();
}
/**
* \brief Timer initialization function
*
* Enables Timer peripheral, clocks and initializes Timer driver
*/
static void TIMER_0_init(void)
{
hri_mclk_set_APBAMASK_TC0_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
timer_init(&TIMER_0, TC0, _tc_get_timer());
}
void TC_SPEED_M1_CLOCK_init(void)
{
hri_mclk_set_APBBMASK_TC2_bit(MCLK);
hri_mclk_set_APBBMASK_TC3_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TC2_GCLK_ID, CONF_GCLK_TC2_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void TC_SPEED_M2_CLOCK_init(void)
{
hri_mclk_set_APBCMASK_TC4_bit(MCLK);
hri_mclk_set_APBCMASK_TC5_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TC4_GCLK_ID, CONF_GCLK_TC4_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void PWM_0_PORT_init(void)
{
gpio_set_pin_function(M1_PWMA, PINMUX_PB12G_TCC0_WO0);
gpio_set_pin_function(M1_PWMB, PINMUX_PB13G_TCC0_WO1);
gpio_set_pin_function(M1_PWMC, PINMUX_PB14G_TCC0_WO2);
gpio_set_pin_function(M1_ENA, PINMUX_PB15G_TCC0_WO3);
gpio_set_pin_function(M1_ENB, PINMUX_PB16G_TCC0_WO4);
gpio_set_pin_function(M1_ENC, PINMUX_PB17G_TCC0_WO5);
}
void PWM_0_CLOCK_init(void)
{
hri_mclk_set_APBBMASK_TCC0_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, CONF_GCLK_TCC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void PWM_0_init(void)
{
PWM_0_CLOCK_init();
PWM_0_PORT_init();
pwm_init(&PWM_0, TCC0, _tcc_get_pwm());
}
void PWM_1_PORT_init(void)
{
gpio_set_pin_function(M2_PWMA, PINMUX_PA16F_TCC1_WO0);
gpio_set_pin_function(M2_PWMB, PINMUX_PA17F_TCC1_WO1);
gpio_set_pin_function(M2_PWMC, PINMUX_PA18F_TCC1_WO2);
gpio_set_pin_function(M2_ENA, PINMUX_PA19F_TCC1_WO3);
gpio_set_pin_function(M2_ENB, PINMUX_PA20F_TCC1_WO4);
gpio_set_pin_function(M2_ENC, PINMUX_PA21F_TCC1_WO5);
}
void PWM_1_CLOCK_init(void)
{
hri_mclk_set_APBBMASK_TCC1_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TCC1_GCLK_ID, CONF_GCLK_TCC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void PWM_1_init(void)
{
PWM_1_CLOCK_init();
PWM_1_PORT_init();
pwm_init(&PWM_1, TCC1, _tcc_get_pwm());
}
void system_init(void)
{
init_mcu();
// GPIO on PA03
// Disable digital pin circuitry
gpio_set_pin_direction(ANAREF_2V48, GPIO_DIRECTION_OFF);
gpio_set_pin_function(ANAREF_2V48, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA14
gpio_set_pin_function(SPI2_SS, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA25
gpio_set_pin_level(M1_RST,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(M1_RST, GPIO_DIRECTION_OUT);
gpio_set_pin_function(M1_RST, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA27
gpio_set_pin_level(M2_RST,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(M2_RST, GPIO_DIRECTION_OUT);
gpio_set_pin_function(M2_RST, GPIO_PIN_FUNCTION_OFF);
// GPIO on PB00
gpio_set_pin_function(SPI3_SS, GPIO_PIN_FUNCTION_OFF);
ADC_0_init();
ADC_1_init();
DIGITAL_GLUE_LOGIC_0_init();
EXTERNAL_IRQ_0_init();
EVENT_SYSTEM_0_init();
ECAT_QSPI_init();
SPI_1_MSIF_init();
SPI_2_init();
SPI_3_init();
TIMER_0_init();
TC_SPEED_M1_CLOCK_init();
TC_SPEED_M1_init();
TC_SPEED_M2_CLOCK_init();
TC_SPEED_M2_init();
PWM_0_init();
PWM_1_init();
}

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2_Motor_Slave/Motor_Slave/Motor_Slave/driver_init.h Normal file
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@ -0,0 +1,121 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_INIT_INCLUDED
#define DRIVER_INIT_INCLUDED
#include "atmel_start_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <hal_atomic.h>
#include <hal_delay.h>
#include <hal_gpio.h>
#include <hal_init.h>
#include <hal_io.h>
#include <hal_sleep.h>
#include <hal_adc_sync.h>
#include <hal_adc_sync.h>
#include <hal_custom_logic.h>
#include <hal_ext_irq.h>
#include <hal_evsys.h>
#include <hal_qspi_dma.h>
#include <hal_spi_s_sync.h>
#include <hal_spi_m_async.h>
#include <hal_spi_m_sync.h>
#include <hal_timer.h>
#include <hpl_tc_base.h>
#include <tc_lite.h>
#include <tc_lite.h>
#include <hal_pwm.h>
#include <hpl_tcc.h>
#include <hal_pwm.h>
#include <hpl_tcc.h>
extern struct adc_sync_descriptor ADC_0;
extern struct adc_sync_descriptor ADC_1;
extern struct qspi_dma_descriptor ECAT_QSPI;
extern struct spi_s_sync_descriptor SPI_1_MSIF;
extern struct spi_m_async_descriptor SPI_2;
extern struct spi_m_sync_descriptor SPI_3;
extern struct timer_descriptor TIMER_0;
extern struct pwm_descriptor PWM_0;
extern struct pwm_descriptor PWM_1;
void ADC_0_PORT_init(void);
void ADC_0_CLOCK_init(void);
void ADC_0_init(void);
void ADC_1_PORT_init(void);
void ADC_1_CLOCK_init(void);
void ADC_1_init(void);
void DIGITAL_GLUE_LOGIC_0_PORT_init(void);
void DIGITAL_GLUE_LOGIC_0_CLOCK_init(void);
void DIGITAL_GLUE_LOGIC_0_init(void);
void ECAT_QSPI_PORT_init(void);
void ECAT_QSPI_CLOCK_init(void);
void ECAT_QSPI_init(void);
void SPI_1_MSIF_PORT_init(void);
void SPI_1_MSIF_CLOCK_init(void);
void SPI_1_MSIF_init(void);
void SPI_1_MSIF_example(void);
void SPI_2_PORT_init(void);
void SPI_2_CLOCK_init(void);
void SPI_2_init(void);
void SPI_3_PORT_init(void);
void SPI_3_CLOCK_init(void);
void SPI_3_init(void);
void TC_SPEED_M1_CLOCK_init(void);
int8_t TC_SPEED_M1_init(void);
void TC_SPEED_M2_CLOCK_init(void);
int8_t TC_SPEED_M2_init(void);
void PWM_0_PORT_init(void);
void PWM_0_CLOCK_init(void);
void PWM_0_init(void);
void PWM_1_PORT_init(void);
void PWM_1_CLOCK_init(void);
void PWM_1_init(void);
/**
* \brief Perform system initialization, initialize pins and clocks for
* peripherals
*/
void system_init(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_INIT_INCLUDED

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_examples.h"
#include "driver_init.h"
#include "utils.h"
/**
* Example of using ADC_0 to generate waveform.
*/
void ADC_0_example(void)
{
uint8_t buffer[2];
adc_sync_enable_channel(&ADC_0, 0);
while (1) {
adc_sync_read_channel(&ADC_0, 0, buffer, 2);
}
}
/**
* Example of using ADC_1 to generate waveform.
*/
void ADC_1_example(void)
{
uint8_t buffer[2];
adc_sync_enable_channel(&ADC_1, 0);
while (1) {
adc_sync_read_channel(&ADC_1, 0, buffer, 2);
}
}
/**
* Example of using DIGITAL_GLUE_LOGIC_0.
*/
void DIGITAL_GLUE_LOGIC_0_example(void)
{
custom_logic_enable();
/* Customer logic now works. */
}
static void button_on_PA07_pressed(void)
{
}
static void button_on_PB30_pressed(void)
{
}
static void button_on_PB31_pressed(void)
{
}
/**
* Example of using EXTERNAL_IRQ_0
*/
void EXTERNAL_IRQ_0_example(void)
{
ext_irq_register(PIN_PA07, button_on_PA07_pressed);
ext_irq_register(PIN_PB30, button_on_PB30_pressed);
ext_irq_register(PIN_PB31, button_on_PB31_pressed);
}
static uint8_t buf[16] = {0x0};
static void xfer_complete_cb_ECAT_QSPI(struct _dma_resource *resource)
{
/* Transfer completed */
}
/**
* Example of using ECAT_QSPI to get N25Q256A status value,
* and check bit 0 which indicate embedded operation is busy or not.
*/
void ECAT_QSPI_example(void)
{
struct _qspi_command cmd = {
.inst_frame.bits.inst_en = 1,
.inst_frame.bits.data_en = 1,
.inst_frame.bits.addr_en = 1,
.inst_frame.bits.dummy_cycles = 8,
.inst_frame.bits.tfr_type = QSPI_READMEM_ACCESS,
.instruction = 0x0B,
.address = 0,
.buf_len = 14,
.rx_buf = buf,
};
qspi_dma_register_callback(&ECAT_QSPI, QSPI_DMA_CB_XFER_DONE, xfer_complete_cb_ECAT_QSPI);
qspi_dma_enable(&ECAT_QSPI);
qspi_dma_serial_run_command(&ECAT_QSPI, &cmd);
}
/**
* Example of using SPI_1_MSIF to write "Hello World" using the IO abstraction.
*/
static uint8_t example_SPI_1_MSIF[12] = "Hello World!";
void SPI_1_MSIF_example(void)
{
struct io_descriptor *io;
spi_s_sync_get_io_descriptor(&SPI_1_MSIF, &io);
spi_s_sync_enable(&SPI_1_MSIF);
io_write(io, example_SPI_1_MSIF, 12);
}
/**
* Example of using SPI_2 to write "Hello World" using the IO abstraction.
*
* Since the driver is asynchronous we need to use statically allocated memory for string
* because driver initiates transfer and then returns before the transmission is completed.
*
* Once transfer has been completed the tx_cb function will be called.
*/
static uint8_t example_SPI_2[12] = "Hello World!";
static void complete_cb_SPI_2(const struct spi_m_async_descriptor *const io_descr)
{
/* Transfer completed */
}
void SPI_2_example(void)
{
struct io_descriptor *io;
spi_m_async_get_io_descriptor(&SPI_2, &io);
spi_m_async_register_callback(&SPI_2, SPI_M_ASYNC_CB_XFER, (FUNC_PTR)complete_cb_SPI_2);
spi_m_async_enable(&SPI_2);
io_write(io, example_SPI_2, 12);
}
/**
* Example of using SPI_3 to write "Hello World" using the IO abstraction.
*/
static uint8_t example_SPI_3[12] = "Hello World!";
void SPI_3_example(void)
{
struct io_descriptor *io;
spi_m_sync_get_io_descriptor(&SPI_3, &io);
spi_m_sync_enable(&SPI_3);
io_write(io, example_SPI_3, 12);
}
static struct timer_task TIMER_0_task1, TIMER_0_task2;
/**
* Example of using TIMER_0.
*/
static void TIMER_0_task1_cb(const struct timer_task *const timer_task)
{
}
static void TIMER_0_task2_cb(const struct timer_task *const timer_task)
{
}
void TIMER_0_example(void)
{
TIMER_0_task1.interval = 100;
TIMER_0_task1.cb = TIMER_0_task1_cb;
TIMER_0_task1.mode = TIMER_TASK_REPEAT;
TIMER_0_task2.interval = 200;
TIMER_0_task2.cb = TIMER_0_task2_cb;
TIMER_0_task2.mode = TIMER_TASK_REPEAT;
timer_add_task(&TIMER_0, &TIMER_0_task1);
timer_add_task(&TIMER_0, &TIMER_0_task2);
timer_start(&TIMER_0);
}
/**
* Example of using PWM_0.
*/
void PWM_0_example(void)
{
pwm_set_parameters(&PWM_0, 10000, 5000);
pwm_enable(&PWM_0);
}
/**
* Example of using PWM_1.
*/
void PWM_1_example(void)
{
pwm_set_parameters(&PWM_1, 10000, 5000);
pwm_enable(&PWM_1);
}

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_EXAMPLES_H_INCLUDED
#define DRIVER_EXAMPLES_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
void ADC_0_example(void);
void ADC_1_example(void);
void DIGITAL_GLUE_LOGIC_0_example(void);
void EXTERNAL_IRQ_0_example(void);
void ECAT_QSPI_example(void);
void SPI_2_example(void);
void TIMER_0_example(void);
void PWM_0_example(void);
void PWM_1_example(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_EXAMPLES_H_INCLUDED

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======================
ADC Synchronous driver
======================
An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
A reference signal with a known voltage level is quantified into equally
sized chunks, each representing a digital value from 0 to the highest number
possible with the bit resolution supported by the ADC. The input voltage
measured by the ADC is compared against these chunks and the chunk with the
closest voltage level defines the digital value that can be used to represent
the analog input voltage level.
Usually an ADC can operate in either differential or single-ended mode.
In differential mode two signals (V+ and V-) are compared against each other
and the resulting digital value represents the relative voltage level between
V+ and V-. This means that if the input voltage level on V+ is lower than on
V- the digital value is negative, which also means that in differential
mode one bit is lost to the sign. In single-ended mode only V+ is compared
against the reference voltage, and the resulting digital value can only be
positive, but the full bit-range of the ADC can be used.
Usually multiple resolutions are supported by the ADC, lower resolution can
reduce the conversion time, but lose accuracy.
Some ADCs has a gain stage on the input lines which can be used to increase the
dynamic range. The default gain value is usually x1, which means that the
conversion range is from 0V to the reference voltage.
Applications can change the gain stage, to increase or reduce the conversion
range.
The window mode allows the conversion result to be compared to a set of
predefined threshold values. Applications can use callback function to monitor
if the conversion result exceeds predefined threshold value.
Usually multiple reference voltages are supported by the ADC, both internal and
external with difference voltage levels. The reference voltage have an impact
on the accuracy, and should be selected to cover the full range of the analog
input signal and never less than the expected maximum input voltage.
There are two conversion modes supported by ADC, single shot and free running.
In single shot mode the ADC only make one conversion when triggered by the
application, in free running mode it continues to make conversion from it
is triggered until it is stopped by the application. When window monitoring,
the ADC should be set to free running mode.
Features
--------
* Initialization and de-initialization
* Support multiple Conversion Mode, Single or Free run
* Start ADC Conversion
* Read Conversion Result
Applications
------------
* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
* Measurement of external sensor. E.g., Temperature, humidity sensor value.
* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
Dependencies
------------
* ADC hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A

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===========================================================
Digital Glue Logic based on Configurable Custom Logic (CCL)
===========================================================
Custom logic driver offers a way to initialize on-chip programmable logic
units, so that a specific logic box is built. Then this "box" can be connected
to internal or external circuit to perform the logic operations.
Features
--------
* Initialization and de-initialization
* Enabling and disabling
Applications
------------
* Connected to external circuit, as a logic operation box, e.g., as adder.
Dependencies
------------
* Programmable logic control units
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A

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===================
Event system driver
===================
Event system allows autonomous, low-latency and configurable communication between peripherals.
Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition
to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that
respond to events are event users, peripherals that generate events are called event generators. A peripheral can have
one or more event generators and can have one or more event users.
Communication is made without CPU intervention and without consuming system resources such as bus or RAM bandwidth. This
reduces the load on the CPU and system resources, compared to a traditional interrupt-based system.
The Event System consists of several channels which route the internal events from generators
to users. Each event generator can be selected as source for multiple channels, but a channel cannot
be set to use multiple event generators at the same time.
Event system driver allows to configure event system of an MCU.
Limitations
-----------
- Event channel configuration is static

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==============
EXT IRQ driver
==============
The External Interrupt driver allows external pins to be
configured as interrupt lines. Each interrupt line can be
individually masked and can generate an interrupt on rising,
falling or both edges, or on high or low levels. Some of
external pin can also be configured to wake up the device
from sleep modes where all clocks have been disabled.
External pins can also generate an event.
Features
--------
* Initialization and de-initialization
* Enabling and disabling
* Detect external pins interrupt
Applications
------------
* Generate an interrupt on rising, falling or both edges,
or on high or low levels.
Dependencies
------------
* GPIO hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A

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The PWM Driver(bare-bone)
=========================
Pulse-width modulation (PWM) is used to create an analog behavior
digitally by controlling the amount of power transferred to the
connected peripheral. This is achieved by controlling the high period
(duty-cycle) of a periodic signal.
User can change the period or duty cycle whenever PWM is running. The
function pwm_set_parameters is used to configure these two parameters.
Note these are raw register values and the parameter duty_cycle means
the period of first half during one cycle, which should be not beyond
total period value.
In addition, user can also get multi PWM channels output from different
peripherals at the same time, which is implemented more flexible by the
function pointers.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Run-time control of PWM duty-cycle and period
* Notifications about errors and one PWM cycle is done
Applications
------------
Motor control, ballast, LED, H-bridge, power converters, and
other types of power control applications.
Dependencies
------------
The peripheral which can perform waveform generation like frequency
generation and pulse-width modulation, such as Timer/Counter.
Concurrency
-----------
N/A
Limitations
-----------
The current driver doesn't support the features like recoverable,
non-recoverable faults, dithering, dead-time insertion.
Known issues and workarounds
----------------------------
N/A

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The Quad SPI DMA Driver
=================================
The Quad SPI Interface (QSPI) is a synchronous serial data link that provides
communication with external devices in master mode.
The QSPI DMA driver uses DMA system to transfer data between QSPI Memory region
and external device. User must configure DMAC system driver accordingly. Callback
function is called when all the data is transferred or transfer error occurred,
if it is registered via qspi_dma_register_callback() function.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Register callback function
* Execute command in Serial Memory Mode
Applications
------------
They are commonly used in an application for using serial flash memory operating
in single-bit SPI, Dual SPI and Quad SPI.
Dependencies
------------
Serial NOR flash with Multiple I/O hardware
Concurrency
-----------
N/A
Limitations
-----------
N.A
Known issues and workarounds
----------------------------
N/A

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The SPI Master Asynchronous Driver
==================================
The serial peripheral interface (SPI) is a synchronous serial communication
interface.
SPI devices communicate in full duplex mode using a master-slave
architecture with a single master. The master device originates the frame for
reading and writing. Multiple slave devices are supported through selection
with individual slave select (SS) lines.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Control of the following settings:
* Baudrate
* SPI mode
* Character size
* Data order
* Data transfer: transmission, reception and full-duplex
* Notifications about transfer completion and errors via callbacks
* Status information with busy state and transfer count
Applications
------------
Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card,
LCD controller, etc.
Dependencies
------------
SPI master capable hardware, with interrupt on each character sent/received.
Concurrency
-----------
N/A
Limitations
-----------
The slave select (SS) is not automatically inserted during read/write/transfer,
user must use I/O to control the devices' SS.
While read/write/transfer is in progress, the data buffer used must be kept
unchanged.
Known issues and workarounds
----------------------------
N/A

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The SPI Master Synchronous Driver
=================================
The serial peripheral interface (SPI) is a synchronous serial communication
interface.
SPI devices communicate in full duplex mode using a master-slave
architecture with a single master. The master device originates the frame for
reading and writing. Multiple slave devices are supported through selection
with individual slave select (SS) lines.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Control of the following settings:
* Baudrate
* SPI mode
* Character size
* Data order
* Data transfer: transmission, reception and full-duplex
Applications
------------
Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card,
LCD controller, etc.
Dependencies
------------
SPI master capable hardware
Concurrency
-----------
N/A
Limitations
-----------
The slave select (SS) is not automatically inserted during read/write/transfer,
user must use I/O to control the devices' SS.
Known issues and workarounds
----------------------------
N/A

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The SPI Slave Synchronous Driver
================================
The serial peripheral interface (SPI) is a synchronous serial communication
interface.
SPI devices communicate in full duplex mode using a master-slave
architecture with a single master. The slave device uses the control signal
and clocks from master for reading and writing. Slave device is selected through
slave select (SS) line.
When data is read or written through the I/O writing function, the driver keeps
polling until amount of characters achieved. Also it's possible to perform
full-duplex read and write through transfer function, which process read and
write at the same time.
When SS detection is considered, a "break on SS detection" option can be enabled
to make it possible to terminate the read/write/transfer on SS desertion.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Control of the following settings:
* SPI mode
* Character size
* Data order
* Data transfer: transmission, reception and full-duplex
Applications
------------
* SPI to I2C bridge that bridges SPI commands to I2C interface.
Dependencies
------------
SPI slave capable hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Known issues and workarounds
----------------------------
When writing data through SPI slave, the time that the data appears on data line
depends on the SPI hardware, and previous writing state, since there can be
data in output fifo filled by previous broken transmitting. The number of such
dummy/broken characters is limited by hardware. Whether these dummy/broken
characters can be flushed is also limited by hardware.

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============================
The Timer driver (bare-bone)
============================
The Timer driver provides means for delayed and periodical function invocation.
A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has
been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a
configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically
changes execution delays and periods for all tasks in the timers task queue.
A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue
and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on
the period set in the task configuration.
In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to
reuse the memory of expired task in the callback.
Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available.
Features
--------
* Initialization and de-initialization
* Starting and stopping
* Timer tasks - periodical invocation of functions
* Changing and obtaining of the period of a timer
Applications
------------
* Delayed and periodical function execution for middle-ware stacks and applications.
Dependencies
------------
* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt.
Concurrency
-----------
The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during
the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed
until the task adding or removing is complete.
The task queue is not protected from the access by interrupts not used by the driver. Due to this
it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes
the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver.
Limitations
-----------
* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts.
* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task.
Knows issues and workarounds
----------------------------
Not applicable

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/**
* \file
*
* \brief ADC functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ADC_SYNC_H_INCLUDED
#define _HAL_ADC_SYNC_H_INCLUDED
#include <hpl_adc_sync.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_adc_sync
*
* @{
*/
/**
* \brief ADC descriptor
*
* The ADC descriptor forward declaration.
*/
struct adc_sync_descriptor;
/**
* \brief ADC descriptor
*/
struct adc_sync_descriptor {
/** ADC device */
struct _adc_sync_device device;
};
/**
* \brief Initialize ADC
*
* This function initializes the given ADC descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr An ADC descriptor to initialize
* \param[in] hw The pointer to hardware instance
* \param[in] func The pointer to a set of functions pointers
*
* \return Initialization status.
*/
int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func);
/**
* \brief Deinitialize ADC
*
* This function deinitializes the given ADC descriptor.
* It checks if the given hardware is initialized and if the given hardware is
* permitted to be deinitialized.
*
* \param[in] descr An ADC descriptor to deinitialize
*
* \return De-initialization status.
*/
int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr);
/**
* \brief Enable ADC
*
* Use this function to set the ADC peripheral to enabled state.
*
* \param[in] descr Pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return Operation status
*
*/
int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Disable ADC
*
* Use this function to set the ADC peripheral to disabled state.
*
* \param[in] descr Pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return Operation status
*
*/
int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Read data from ADC
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] buf A buffer to read data to
* \param[in] length The size of a buffer
*
* \return The number of bytes read.
*/
int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
const uint16_t length);
/**
* \brief Set ADC reference source
*
* This function sets ADC reference source.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] reference A reference source to set
*
* \return Status of the ADC reference source setting.
*/
int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference);
/**
* \brief Set ADC resolution
*
* This function sets ADC resolution.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] resolution A resolution to set
*
* \return Status of the ADC resolution setting.
*/
int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* This function sets ADC positive and negative input sources.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*
* \return Status of the ADC channels setting.
*/
int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set ADC conversion mode
*
* This function sets ADC conversion mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] mode A conversion mode to set
*
* \return Status of the ADC conversion mode setting.
*/
int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode);
/**
* \brief Set ADC differential mode
*
* This function sets ADC differential mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*
* \return Status of the ADC differential mode setting.
*/
int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set ADC channel gain
*
* This function sets ADC channel gain.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] gain A gain to set
*
* \return Status of the ADC gain setting.
*/
int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel,
const adc_gain_t gain);
/**
* \brief Set ADC window mode
*
* This function sets ADC window mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] mode A window mode to set
*
* \return Status of the ADC window mode setting.
*/
int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode);
/**
* \brief Set ADC thresholds
*
* This function sets ADC positive and negative thresholds.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] low_threshold A lower thresholds to set
* \param[in] up_threshold An upper thresholds to set
*
* \return Status of the ADC thresholds setting.
*/
int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* This function retrieves ADC threshold state.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[out] state The threshold state
*
* \return The state of ADC thresholds state retrieving.
*/
int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr,
adc_threshold_status_t *const state);
/**
* \brief Check if conversion is complete
*
* This function checks if the ADC has finished the conversion.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return The status of ADC conversion completion checking.
* \retval 1 The conversion is complete
* \retval 0 The conversion is not complete
*/
int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t adc_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#include <hpl_missing_features.h>
#endif /* _HAL_ADC_SYNC_H_INCLUDED */

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/**
* \file
*
* \brief Critical sections related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ATOMIC_H_INCLUDED
#define _HAL_ATOMIC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_atomic
*
*@{
*/
/**
* \brief Type for the register holding global interrupt enable flag
*/
typedef uint32_t hal_atomic_t;
/**
* \brief Helper macro for entering critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_enterCritical() function to enter critical
* sections. No semicolon is required after the macro.
*
* \section atomic_usage Usage Example
* \code
* CRITICAL_SECTION_ENTER()
* Critical code
* CRITICAL_SECTION_LEAVE()
* \endcode
*/
#define CRITICAL_SECTION_ENTER() \
{ \
volatile hal_atomic_t __atomic; \
atomic_enter_critical(&__atomic);
/**
* \brief Helper macro for leaving critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_leaveCritical() function to leave critical
* sections. No semicolon is required after the macro.
*/
#define CRITICAL_SECTION_LEAVE() \
atomic_leave_critical(&__atomic); \
}
/**
* \brief Disable interrupts, enter critical section
*
* Disables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[out] atomic The pointer to a variable to store the value of global
* interrupt enable flag
*/
void atomic_enter_critical(hal_atomic_t volatile *atomic);
/**
* \brief Exit atomic section
*
* Enables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[in] atomic The pointer to a variable, which stores the latest stored
* value of the global interrupt enable flag
*/
void atomic_leave_critical(hal_atomic_t volatile *atomic);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t atomic_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_ATOMIC_H_INCLUDED */

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/**
* \file
*
* \brief HAL cache functionality implementation.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef HAL_CACHE_H_
#define HAL_CACHE_H_
#include <hpl_cmcc.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Enable cache module
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_enable(const void *hw);
/**
* \brief Disable cache module
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_disable(const void *hw);
/**
* \brief Initialize cache module
*
* This function initialize cache module configuration.
*
* \return status of operation
*/
int32_t cache_init(void);
/**
* \brief Configure cache module
*
* \param[in] pointer pointing to the starting address of cache module
* \param[in] cache configuration structure pointer
*
* \return status of operation
*/
int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
/**
* \brief Invalidate entire cache entries
*
* \param[in] pointer pointing to the starting address of cache module
*
* \return status of operation
*/
int32_t cache_invalidate_all(const void *hw);
#ifdef __cplusplus
}
#endif
#endif /* HAL_CACHE_H_ */

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/**
* \file
*
* \brief Custom Control Logic functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hpl_custom_logic.h"
#ifndef _HAL_CUSTOM_LOGIC_H_INCLUDED
#define _HAL_CUSTOM_LOGIC_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_custom_logic
*
*@{
*/
/**
* \brief Initialize the custom logic hardware
* \return Initialization operation status
*/
static inline int32_t custom_logic_init(void)
{
return _custom_logic_init();
}
/**
* \brief Disable and reset the custom logic hardware
*/
static inline void custom_logic_deinit(void)
{
_custom_logic_deinit();
}
/**
* \brief Enable the custom logic hardware
* \return Initialization operation status
*/
static inline int32_t custom_logic_enable(void)
{
return _custom_logic_enable();
}
/**
* \brief Disable the custom logic hardware
*/
static inline void custom_logic_disable(void)
{
_custom_logic_disable();
}
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_CUSTOM_LOGIC_H_INCLUDED */

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/**
* \file
*
* \brief HAL delay related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_irq.h>
#include <hpl_reset.h>
#include <hpl_sleep.h>
#ifndef _HAL_DELAY_H_INCLUDED
#define _HAL_DELAY_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_delay Delay Driver
*
*@{
*/
/**
* \brief Initialize Delay driver
*
* \param[in] hw The pointer to hardware instance
*/
void delay_init(void *const hw);
/**
* \brief Perform delay in us
*
* This function performs delay for the given amount of microseconds.
*
* \param[in] us The amount delay in us
*/
void delay_us(const uint16_t us);
/**
* \brief Perform delay in ms
*
* This function performs delay for the given amount of milliseconds.
*
* \param[in] ms The amount delay in ms
*/
void delay_ms(const uint16_t ms);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t delay_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_DELAY_H_INCLUDED */

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/**
* \file
*
* \brief HAL event system related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_evsys.h>
#ifndef _HAL_EVSYS_H_INCLUDED
#define _HAL_EVSYS_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_evsys
*
* @{
*/
/**
* \brief Initialize event system.
*
* \return Initialization status.
*/
int32_t event_system_init(void);
/**
* \brief Deinitialize event system.
*
* \return De-initialization status.
*/
int32_t event_system_deinit(void);
/**
* \brief Enable event reception by the given user from the given channel
*
* \param[in] user A user to enable
* \param[in] channel A channel the user is assigned to
*
* \return Status of operation.
*/
int32_t event_system_enable_user(const uint16_t user, const uint16_t channel);
/**
* \brief Disable event reception by the given user from the given channel
*
* \param[in] user A user to disable
* \param[in] channel A channel the user is assigned to
*
* \return Status of operation.
*/
int32_t event_system_disable_user(const uint16_t user, const uint16_t channel);
/**
* \brief Enable event generation by the given generator for the given channel
*
* \param[in] generator A generator to disable
* \param[in] channel A channel the generator is assigned to
*
* \return Status of operation.
*/
int32_t event_system_enable_generator(const uint16_t generator, const uint16_t channel);
/**
* \brief Disable event generation by the given generator for the given channel
*
* \param[in] generator A generator to disable
* \param[in] channel A channel the generator is assigned to
*
* \return Status of operation.
*/
int32_t event_system_disable_generator(const uint16_t generator, const uint16_t channel);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t event_system_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_EVSYS_H_INCLUDED */

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/**
* \file
*
* \brief External interrupt functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_EXT_IRQ_H_INCLUDED
#define _HAL_EXT_IRQ_H_INCLUDED
#include <hpl_ext_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_ext_irq
*
* @{
*/
/**
* \brief External IRQ callback type
*/
typedef void (*ext_irq_cb_t)(void);
/**
* \brief Initialize external IRQ component, if any
*
* \return Initialization status.
* \retval -1 External IRQ module is already initialized
* \retval 0 The initialization is completed successfully
*/
int32_t ext_irq_init(void);
/**
* \brief Deinitialize external IRQ, if any
*
* \return De-initialization status.
* \retval -1 External IRQ module is already deinitialized
* \retval 0 The de-initialization is completed successfully
*/
int32_t ext_irq_deinit(void);
/**
* \brief Register callback for the given external interrupt
*
* \param[in] pin Pin to enable external IRQ on
* \param[in] cb Callback function
*
* \return Registration status.
* \retval -1 Passed parameters were invalid
* \retval 0 The callback registration is completed successfully
*/
int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb);
/**
* \brief Enable external IRQ
*
* \param[in] pin Pin to enable external IRQ on
*
* \return Enabling status.
* \retval -1 Passed parameters were invalid
* \retval 0 The enabling is completed successfully
*/
int32_t ext_irq_enable(const uint32_t pin);
/**
* \brief Disable external IRQ
*
* \param[in] pin Pin to enable external IRQ on
*
* \return Disabling status.
* \retval -1 Passed parameters were invalid
* \retval 0 The disabling is completed successfully
*/
int32_t ext_irq_disable(const uint32_t pin);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t ext_irq_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_EXT_IRQ_H_INCLUDED */

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/**
* \file
*
* \brief Port
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*/
#ifndef _HAL_GPIO_INCLUDED_
#define _HAL_GPIO_INCLUDED_
#include <hpl_gpio.h>
#include <utils_assert.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Set gpio pull mode
*
* Set pin pull mode, non existing pull modes throws an fatal assert
*
* \param[in] pin The pin number for device
* \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor
* GPIO_PULL_UP = Pull pin high with internal resistor
* GPIO_PULL_OFF = Disable pin pull mode
*/
static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode)
{
_gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode);
}
/**
* \brief Set pin function
*
* Select which function a pin will be used for
*
* \param[in] pin The pin number for device
* \param[in] function The pin function is given by a 32-bit wide bitfield
* found in the header files for the device
*
*/
static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
{
_gpio_set_pin_function(pin, function);
}
/**
* \brief Set port data direction
*
* Select if the pin data direction is input, output or disabled.
* If disabled state is not possible, this function throws an assert.
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to the
* corresponding pin
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
* GPIO_DIRECTION_OUT = Data direction out
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask,
const enum gpio_direction direction)
{
_gpio_set_direction(port, mask, direction);
}
/**
* \brief Set gpio data direction
*
* Select if the pin data direction is input, output or disabled.
* If disabled state is not possible, this function throws an assert.
*
* \param[in] pin The pin number for device
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
* GPIO_DIRECTION_OUT = Data direction out
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
{
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
}
/**
* \brief Set port level
*
* Sets output level on the pins defined by the bit mask
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply port level to the corresponding
* pin
* \param[in] level true = Pin levels set to "high" state
* false = Pin levels set to "low" state
*/
static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level)
{
_gpio_set_level(port, mask, level);
}
/**
* \brief Set gpio level
*
* Sets output level on a pin
*
* \param[in] pin The pin number for device
* \param[in] level true = Pin level set to "high" state
* false = Pin level set to "low" state
*/
static inline void gpio_set_pin_level(const uint8_t pin, const bool level)
{
_gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level);
}
/**
* \brief Toggle out level on pins
*
* Toggle the pin levels on pins defined by bit mask
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means toggle pin level to the corresponding
* pin
*/
static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask)
{
_gpio_toggle_level(port, mask);
}
/**
* \brief Toggle output level on pin
*
* Toggle the pin levels on pins defined by bit mask
*
* \param[in] pin The pin number for device
*/
static inline void gpio_toggle_pin_level(const uint8_t pin)
{
_gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin));
}
/**
* \brief Get input level on pins
*
* Read the input level on pins connected to a port
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
*/
static inline uint32_t gpio_get_port_level(const enum gpio_port port)
{
return _gpio_get_level(port);
}
/**
* \brief Get level on pin
*
* Reads the level on pins connected to a port
*
* \param[in] pin The pin number for device
*/
static inline bool gpio_get_pin_level(const uint8_t pin)
{
return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
}
/**
* \brief Get current driver version
*/
uint32_t gpio_get_version(void);
#ifdef __cplusplus
}
#endif
#endif

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/**
* \file
*
* \brief HAL initialization related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_INIT_H_INCLUDED
#define _HAL_INIT_H_INCLUDED
#include <hpl_init.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_init Init Driver
*
*@{
*/
/**
* \brief Initialize the hardware abstraction layer
*
* This function calls the various initialization functions.
* Currently the following initialization functions are supported:
* - System clock initialization
*/
static inline void init_mcu(void)
{
_init_chip();
}
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t init_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_INIT_H_INCLUDED */

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/**
* \file
*
* \brief I/O related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_IO_INCLUDED
#define _HAL_IO_INCLUDED
/**
* \addtogroup doc_driver_hal_helper_io I/O Driver
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief I/O descriptor
*
* The I/O descriptor forward declaration.
*/
struct io_descriptor;
/**
* \brief I/O write function pointer type
*/
typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
/**
* \brief I/O read function pointer type
*/
typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
/**
* \brief I/O descriptor
*/
struct io_descriptor {
io_write_t write; /*! The write function pointer. */
io_read_t read; /*! The read function pointer. */
};
/**
* \brief I/O write interface
*
* This function writes up to \p length of bytes to a given I/O descriptor.
* It returns the number of bytes actually write.
*
* \param[in] descr An I/O descriptor to write
* \param[in] buf The buffer pointer to story the write data
* \param[in] length The number of bytes to write
*
* \return The number of bytes written
*/
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
/**
* \brief I/O read interface
*
* This function reads up to \p length bytes from a given I/O descriptor, and
* stores it in the buffer pointed to by \p buf. It returns the number of bytes
* actually read.
*
* \param[in] descr An I/O descriptor to read
* \param[in] buf The buffer pointer to story the read data
* \param[in] length The number of bytes to read
*
* \return The number of bytes actually read. This number can be less than the
* requested length. E.g., in a driver that uses ring buffer for
* reception, it may depend on the availability of data in the
* ring buffer.
*/
int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HAL_IO_INCLUDED */

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/**
* \file
*
* \brief PWM functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef HAL_PWM_H_INCLUDED
#define HAL_PWM_H_INCLUDED
#include <hpl_pwm.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_pwm_async
*
*@{
*/
/**
* \brief PWM descriptor
*
* The PWM descriptor forward declaration.
*/
struct pwm_descriptor;
/**
* \brief PWM callback type
*/
typedef void (*pwm_cb_t)(const struct pwm_descriptor *const descr);
/**
* \brief PWM callback types
*/
enum pwm_callback_type { PWM_PERIOD_CB, PWM_ERROR_CB };
/**
* \brief PWM callbacks
*/
struct pwm_callbacks {
pwm_cb_t period;
pwm_cb_t error;
};
/** \brief PWM descriptor
*/
struct pwm_descriptor {
/** PWM device */
struct _pwm_device device;
/** PWM callback structure */
struct pwm_callbacks pwm_cb;
};
/** \brief Initialize the PWM HAL instance and hardware
*
* \param[in] descr Pointer to the HAL PWM descriptor
* \param[in] hw The pointer to hardware instance
* \param[in] func The pointer to a set of functions pointers
*
* \return Operation status.
*/
int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func);
/** \brief Deinitialize the PWM HAL instance and hardware
*
* \param[in] descr Pointer to the HAL PWM descriptor
*
* \return Operation status.
*/
int32_t pwm_deinit(struct pwm_descriptor *const descr);
/** \brief PWM output start
*
* \param[in] descr Pointer to the HAL PWM descriptor
*
* \return Operation status.
*/
int32_t pwm_enable(struct pwm_descriptor *const descr);
/** \brief PWM output stop
*
* \param[in] descr Pointer to the HAL PWM descriptor
*
* \return Operation status.
*/
int32_t pwm_disable(struct pwm_descriptor *const descr);
/** \brief Register PWM callback
*
* \param[in] descr Pointer to the HAL PWM descriptor
* \param[in] type Callback type
* \param[in] cb A callback function, passing NULL de-registers callback
*
* \return Operation status.
* \retval 0 Success
* \retval -1 Error
*/
int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb);
/** \brief Change PWM parameter
*
* \param[in] descr Pointer to the HAL PWM descriptor
* \param[in] period Total period of one PWM cycle
* \param[in] duty_cycle Period of PWM first half during one cycle
*
* \return Operation status.
*/
int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period,
const pwm_period_t duty_cycle);
/** \brief Get PWM driver version
*
* \return Current driver version.
*/
uint32_t pwm_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* HAL_PWM;_H_INCLUDED */

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/**
* \file
*
* \brief Quad SPI dma related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_QSPI_DMA_INCLUDED
#define _HAL_QSPI_DMA_INCLUDED
#include <hpl_qspi_dma.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_quad_spi_dma
*
*@{
*/
/**
* \brief QSPI descriptor structure
*/
struct qspi_dma_descriptor {
/** Pointer to QSPI device instance */
struct _qspi_dma_dev dev;
};
/**
* \brief Initialize QSPI low level driver.
*
* \param[in] qspi Pointer to the QSPI device instance
* \param[in] hw Pointer to the hardware base
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_dma_init(struct qspi_dma_descriptor *qspi, void *hw);
/**
* \brief Deinitialize QSPI low level driver.
*
* \param[in] qspi Pointer to the QSPI device instance
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_dma_deinit(struct qspi_dma_descriptor *qspi);
/**
* \brief Enable QSPI for access without interrupts
*
* \param[in] qspi Pointer to the QSPI device instance.
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_dma_enable(struct qspi_dma_descriptor *qspi);
/**
* \brief Disable QSPI for access without interrupts
*
* Disable QSPI. Deactivate all CS pins if it works as master.
*
* \param[in] qspi Pointer to the QSPI device instance.
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_dma_disable(struct qspi_dma_descriptor *qspi);
/** \brief Execute command in Serial Memory Mode.
*
* \param[in] qspi Pointer to the HAL QSPI instance
* \param[in] cmd Pointer to the command structure
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_dma_serial_run_command(struct qspi_dma_descriptor *qspi, const struct _qspi_command *cmd);
/** \brief Register a function as QSPI transfer completion callback
*
* Register callback function specified by its \c type.
* - QSPI_DMA_CB_XFER_DONE: set the function that will be called on QSPI transfer
* completion including deactivate the CS.
* - QSPI_DMA_CB_ERROR: set the function that will be called on QSPI transfer error.
* Register NULL function to not use the callback.
*
* \param[in] qspi Pointer to the HAL QSPI instance
* \param[in] type Callback type (\ref _qspi_dma_cb_type)
* \param[in] cb Pointer to callback function
*/
void qspi_dma_register_callback(struct qspi_dma_descriptor *qspi, const enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t qspi_dma_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_QSPI_DMA_INCLUDED */

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/**
* \file
*
* \brief Sleep related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SLEEP_H_INCLUDED
#define _HAL_SLEEP_H_INCLUDED
#include <hpl_sleep.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_sleep
*
*@{
*/
/**
* \brief Set the sleep mode of the device and put the MCU to sleep
*
* For an overview of which systems are disabled in sleep for the different
* sleep modes, see the data sheet.
*
* \param[in] mode Sleep mode to use
*
* \return The status of a sleep request
* \retval -1 The requested sleep mode was invalid or not available
* \retval 0 The operation completed successfully, returned after leaving the
* sleep
*/
int sleep(const uint8_t mode);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t sleep_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_SLEEP_H_INCLUDED */

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/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SPI_M_ASYNC_H_INCLUDED
#define _HAL_SPI_M_ASYNC_H_INCLUDED
#include <hal_io.h>
#include <hpl_spi_m_async.h>
/**
* \addtogroup doc_driver_hal_spi_master_async
*
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** \brief SPI status
*
* Status descriptor holds the current status of transfer.
*
* \c txcnt and \c rxcnt are always the status of progress in current TX/RX
* transfer buffer.
*
* For R/W/Transfer, simply check \c SPI_M_ASYNC_STATUS_BUSY to know that the
* transfer is in progress, check \c SPI_M_ASYNC_STATUS_TX_DONE and
* \c SPI_M_ASYNC_STATUS_RX_DONE to know that TX or RX is completed (since TX
* and RX happen in different clock edge the time stamp of completion is
* different), check \c SPI_M_ASYNC_STATUS_COMPLETE to confirm that CS has been
* deactivate.
*/
struct spi_m_async_status {
/** Status flags */
uint32_t flags;
/** Number of characters transmitted */
uint32_t xfercnt;
};
/** SPI is busy (read/write/transfer, with CS activated) */
#define SPI_M_ASYNC_STATUS_BUSY 0x0010
/** SPI finished transmit buffer */
#define SPI_M_ASYNC_STATUS_TX_DONE 0x0020
/** SPI finished receive buffer */
#define SPI_M_ASYNC_STATUS_RX_DONE 0x0040
/** SPI finished everything including CS deactivate */
#define SPI_M_ASYNC_STATUS_COMPLETE 0x0080
#define SPI_M_ASYNC_STATUS_ERR_MASK 0x000F
#define SPI_M_ASYNC_STATUS_ERR_POS 0
#define SPI_M_ASYNC_STATUS_ERR_OVRF ((-ERR_OVERFLOW) << SPI_M_ASYNC_STATUS_ERR_POS)
#define SPI_M_ASYNC_STATUS_ERR_ABORT ((-ERR_ABORTED) << SPI_M_ASYNC_STATUS_ERR_POS)
#define SPI_M_ASYNC_STATUS_ERR_EXTRACT(st) (((st) >> SPI_M_ASYNC_STATUS_ERR_POS) & SPI_M_ASYNC_STATUS_ERR_MASK)
/* Forward declaration of spi_descriptor. */
struct spi_m_async_descriptor;
/** The callback types */
enum spi_m_async_cb_type {
/** Callback type for read/write/transfer buffer done,
* see \ref spi_m_async_cb_xfer_t. */
SPI_M_ASYNC_CB_XFER,
/** Callback type for CS deactivate, error, or abort,
* see \ref spi_m_async_cb_error_t. */
SPI_M_ASYNC_CB_ERROR,
SPI_M_ASYNC_CB_N
};
/** \brief Prototype of callback on SPI transfer errors
*
* Invoked on transfer errors
* invoke \ref spi_get_status.
*/
typedef void (*spi_m_async_cb_error_t)(struct spi_m_async_descriptor *, const int32_t status);
/** \brief Prototype of callback on SPI read/write/transfer buffer completion
*
* Invoked on transfer completion, which means the transfer buffer has been
* completed, including all TX/RX data (TX and RX happen in different clock
* edges, but the callback is invoked after all TX and RX have been done).
*/
typedef void (*spi_m_async_cb_xfer_t)(struct spi_m_async_descriptor *);
/** \brief SPI HAL callbacks
*
*/
struct spi_m_callbacks {
/** Callback invoked when the buffer read/write/transfer done. */
spi_m_async_cb_xfer_t cb_xfer;
/** Callback invoked when the CS deactivates, goes wrong, or aborts. */
spi_m_async_cb_error_t cb_error;
};
/** \brief SPI HAL driver struct for asynchronous access
*/
struct spi_m_async_descriptor {
struct _spi_m_async_hpl_interface *func;
/** Pointer to the SPI device instance */
struct _spi_m_async_dev dev;
/** I/O read/write */
struct io_descriptor io;
/** SPI transfer status */
uint8_t stat;
/** Callbacks for asynchronous transfer */
struct spi_m_callbacks callbacks;
/** Transfer information copy, for R/W/Transfer */
struct spi_xfer xfer;
/** Character count in current transfer */
uint32_t xfercnt;
};
/** \brief Set the SPI HAL instance function pointer for HPL APIs.
*
* Set SPI HAL instance function pointer for HPL APIs.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] func Pointer to the HPL api structure.
*
*/
void spi_m_async_set_func_ptr(struct spi_m_async_descriptor *spi, void *const func);
/** \brief Initialize the SPI HAL instance and hardware for callback mode
*
* Initialize SPI HAL with interrupt mode (uses callbacks).
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] hw Pointer to the hardware base.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_INVALID_DATA Error, initialized.
*/
int32_t spi_m_async_init(struct spi_m_async_descriptor *spi, void *const hw);
/** \brief Deinitialize the SPI HAL instance
*
* Abort transfer, disable and reset SPI, de-init software.
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_async_deinit(struct spi_m_async_descriptor *spi);
/** \brief Enable SPI
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_async_enable(struct spi_m_async_descriptor *spi);
/** \brief Disable the SPI and abort any pending transfer in progress
*
* If there is any pending transfer, the complete callback is invoked
* with the \c ERR_ABORTED status.
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_async_disable(struct spi_m_async_descriptor *spi);
/** \brief Set SPI baudrate
*
* Works if the SPI is initialized as master.
* In the function a sanity check is used to confirm it's called in the correct mode.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] baud_val The target baudrate value
* (see "baudrate calculation" for calculating the value).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy.
*/
int32_t spi_m_async_set_baudrate(struct spi_m_async_descriptor *spi, const uint32_t baud_val);
/** \brief Set SPI mode
*
* Set the SPI transfer mode (\ref spi_transfer_mode),
* which controls the clock polarity and clock phase:
* - Mode 0: leading edge is rising edge, data sample on leading edge.
* - Mode 1: leading edge is rising edge, data sample on trailing edge.
* - Mode 2: leading edge is falling edge, data sample on leading edge.
* - Mode 3: leading edge is falling edge, data sample on trailing edge.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] mode The mode (\ref spi_transfer_mode).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy, CS activated.
*/
int32_t spi_m_async_set_mode(struct spi_m_async_descriptor *spi, const enum spi_transfer_mode mode);
/** \brief Set SPI transfer character size in number of bits
*
* The character size (\ref spi_char_size) influence the way the data is
* sent/received.
* For char size <= 8-bit, data is stored byte by byte.
* For char size between 9-bit ~ 16-bit, data is stored in 2-byte length.
* Note that the default and recommended char size is 8-bit since it's
* supported by all system.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] char_size The char size (\ref spi_char_size).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy, CS activated.
* \retval ERR_INVALID_ARG The char size is not supported.
*/
int32_t spi_m_async_set_char_size(struct spi_m_async_descriptor *spi, const enum spi_char_size char_size);
/** \brief Set SPI transfer data order
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] dord The data order: send LSB/MSB first.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy, CS activated.
* \retval ERR_INVALID The data order is not supported.
*/
int32_t spi_m_async_set_data_order(struct spi_m_async_descriptor *spi, const enum spi_data_order dord);
/** \brief Perform the SPI data transfer (TX and RX) asynchronously
*
* Log the TX and RX buffers and transfer them in the background. It never blocks.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] txbuf Pointer to the transfer information (\ref spi_transfer).
* \param[out] rxbuf Pointer to the receiver information (\ref spi_receive).
* \param[in] length SPI transfer data length.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy.
*/
int32_t spi_m_async_transfer(struct spi_m_async_descriptor *spi, uint8_t const *txbuf, uint8_t *const rxbuf,
const uint16_t length);
/** \brief Get the SPI transfer status
*
* Get transfer status, transfer counts in a structured way.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[out] stat Pointer to the detailed status descriptor, set to NULL
* to not return details.
*
* \return Status.
* \retval ERR_NONE Not busy.
* \retval ERR_BUSY Busy.
*/
int32_t spi_m_async_get_status(struct spi_m_async_descriptor *spi, struct spi_m_async_status *stat);
/** \brief Register a function as SPI transfer completion callback
*
* Register callback function specified by its \c type.
* - SPI_CB_COMPLETE: set the function that will be called on the SPI transfer
* completion including deactivating the CS.
* - SPI_CB_XFER: set the function that will be called on the SPI buffer transfer
* completion.
* Register NULL function to not use the callback.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] type Callback type (\ref spi_m_async_cb_type).
* \param[in] func Pointer to callback function.
*/
void spi_m_async_register_callback(struct spi_m_async_descriptor *spi, const enum spi_m_async_cb_type type,
FUNC_PTR func);
/**
* \brief Return I/O descriptor for this SPI instance
*
* This function will return an I/O instance for this SPI driver instance
*
* \param[in] spi An SPI master descriptor, which is used to communicate through
* SPI
* \param[in, out] io A pointer to an I/O descriptor pointer type
*
* \retval ERR_NONE
*/
int32_t spi_m_async_get_io_descriptor(struct spi_m_async_descriptor *const spi, struct io_descriptor **io);
/** \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t spi_m_async_get_version(void);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HAL_SPI_M_ASYNC_H_INCLUDED */

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/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SPI_M_SYNC_H_INCLUDED
#define _HAL_SPI_M_SYNC_H_INCLUDED
#include <hal_io.h>
#include <hpl_spi_m_sync.h>
/**
* \addtogroup doc_driver_hal_spi_master_sync
*
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** \brief SPI HAL driver struct for polling mode
*
*/
struct spi_m_sync_descriptor {
struct _spi_m_sync_hpl_interface *func;
/** SPI device instance */
struct _spi_sync_dev dev;
/** I/O read/write */
struct io_descriptor io;
/** Flags for HAL driver */
uint16_t flags;
};
/** \brief Set the SPI HAL instance function pointer for HPL APIs.
*
* Set SPI HAL instance function pointer for HPL APIs.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] func Pointer to the HPL api structure.
*
*/
void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func);
/** \brief Initialize SPI HAL instance and hardware for polling mode
*
* Initialize SPI HAL with polling mode.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] hw Pointer to the hardware base.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_INVALID_DATA Error, initialized.
*/
int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw);
/** \brief Deinitialize the SPI HAL instance and hardware
*
* Abort transfer, disable and reset SPI, deinit software.
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi);
/** \brief Enable SPI
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_sync_enable(struct spi_m_sync_descriptor *spi);
/** \brief Disable SPI
*
* \param[in] spi Pointer to the HAL SPI instance.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval <0 Error code.
*/
void spi_m_sync_disable(struct spi_m_sync_descriptor *spi);
/** \brief Set SPI baudrate
*
* Works if SPI is initialized as master, it sets the baudrate.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] baud_val The target baudrate value
* (see "baudrate calculation" for calculating the value).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy
* \retval ERR_INVALID_ARG The baudrate is not supported.
*/
int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val);
/** \brief Set SPI mode
*
* Set the SPI transfer mode (\ref spi_transfer_mode),
* which controls the clock polarity and clock phase:
* - Mode 0: leading edge is rising edge, data sample on leading edge.
* - Mode 1: leading edge is rising edge, data sample on trailing edge.
* - Mode 2: leading edge is falling edge, data sample on leading edge.
* - Mode 3: leading edge is falling edge, data sample on trailing edge.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] mode The mode (0~3).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy
* \retval ERR_INVALID_ARG The mode is not supported.
*/
int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode);
/** \brief Set SPI transfer character size in number of bits
*
* The character size (\ref spi_char_size) influence the way the data is
* sent/received.
* For char size <= 8-bit, data is stored byte by byte.
* For char size between 9-bit ~ 16-bit, data is stored in 2-byte length.
* Note that the default and recommended char size is 8-bit since it's
* supported by all system.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] char_size The char size (~16, recommended 8).
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy
* \retval ERR_INVALID_ARG The char size is not supported.
*/
int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size);
/** \brief Set SPI transfer data order
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] dord The data order: send LSB/MSB first.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy
* \retval ERR_INVALID_ARG The data order is not supported.
*/
int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord);
/** \brief Perform the SPI data transfer (TX and RX) in polling way
*
* Activate CS, do TX and RX and deactivate CS. It blocks.
*
* \param[in, out] spi Pointer to the HAL SPI instance.
* \param[in] xfer Pointer to the transfer information (\ref spi_xfer).
*
* \retval size Success.
* \retval >=0 Timeout, with number of characters transferred.
* \retval ERR_BUSY SPI is busy
*/
int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *xfer);
/**
* \brief Return the I/O descriptor for this SPI instance
*
* This function will return an I/O instance for this SPI driver instance.
*
* \param[in] spi An SPI master descriptor, which is used to communicate through
* SPI
* \param[in, out] io A pointer to an I/O descriptor pointer type
*
* \retval ERR_NONE
*/
int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io);
/** \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t spi_m_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* ifndef _HAL_SPI_M_SYNC_H_INCLUDED */

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/**
* \file
*
* \brief SPI Slave functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SPI_S_SYNC_H_INCLUDED
#define _HAL_SPI_S_SYNC_H_INCLUDED
#include "hpl_spi_s_sync.h"
#include "utils.h"
#include "hal_io.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_spi_slave_sync
*
* @{
*/
/** \brief SPI Slave HAL driver struct for synchronous access
*/
struct spi_s_sync_descriptor {
struct _spi_s_sync_hpl_interface *func;
/** SPI device instance */
struct _spi_sync_dev dev;
/** I/O read/write */
struct io_descriptor io;
/** Break on SS desert detection. */
uint8_t break_on_ss_det;
};
/** \brief Set the SPI HAL instance function pointer for HPL APIs.
*
* Set SPI HAL instance function pointer for HPL APIs.
*
* \param[in] spi Pointer to the HAL SPI instance.
* \param[in] func Pointer to the HPL api structure.
*
*/
void spi_s_sync_set_func_ptr(struct spi_s_sync_descriptor *spi, void *const func);
/** \brief Initialize the SPI Slave HAL instance and hardware
*
* Initialize SPI Slave HAL with polling mode.
*
* \param[in, out] spi Pointer to the SPI Slave HAL instance.
* \param[in] hw Pointer to the hardware base.
*
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error.
*/
int32_t spi_s_sync_init(struct spi_s_sync_descriptor *spi, void *const hw);
/** \brief Deinitialize the SPI HAL instance
*
* Disable and reset SPI, de-init software.
*
* \param[in,out] spi Pointer to the SPI Slave HAL instance.
*/
void spi_s_sync_deinit(struct spi_s_sync_descriptor *spi);
/** \brief Enable SPI
*
* \param[in,out] spi Pointer to the SPI Slave HAL instance.
*/
void spi_s_sync_enable(struct spi_s_sync_descriptor *spi);
/** \brief Disable SPI
*
* \param[in,out] spi Pointer to the SPI Slave HAL instance.
*/
void spi_s_sync_disable(struct spi_s_sync_descriptor *spi);
/** \brief Set SPI mode
*
* Set the SPI transfer mode (\ref spi_transfer_mode_t),
* which controls the clock polarity and clock phase:
* - Mode 0: leading edge is rising edge, data sample on leading edge.
* - Mode 1: leading edge is rising edge, data sample on trailing edge.
* - Mode 2: leading edge is falling edge, data sample on leading edge.
* - Mode 3: leading edge is falling edge, data sample on trailing edge.
* Note that SPI must be disabled to change mode.
*
* \param[in,out] spi Pointer to the HAL SPI instance.
* \param[in] mode The mode (\ref spi_transfer_mode_t).
*
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error.
*/
int32_t spi_s_sync_set_mode(struct spi_s_sync_descriptor *spi, const enum spi_transfer_mode mode);
/** \brief Set SPI transfer character size in number of bits
*
* The character size (\ref spi_char_size_t) influence the way the data is
* sent/received.
* For char size <= 8-bit, data is stored byte by byte.
* For char size between 9-bit ~ 16-bit, data is stored in 2-byte length.
* Note that the default and recommended char size is 8-bit since it's
* supported by all system.
* Note that the SPI must be disabled to change character size. Also it affects
* buffer accessing, the ring buffer should be flushed before changing it to
* avoid conflicts.
*
* \param[in,out] spi Pointer to the HAL SPI instance.
* \param[in] char_size The char size (~32, recommended 8).
*
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error.
*/
int32_t spi_s_sync_set_char_size(struct spi_s_sync_descriptor *spi, const enum spi_char_size char_size);
/** \brief Set SPI transfer data order
*
* Note that the SPI must be disabled to change data order.
*
* \param[in,out] spi Pointer to the HAL SPI instance.
* \param[in] dord The data order: send LSB/MSB first.
*
* \return Operation status.
* \retval 0 Success.
* \retval <0 Error.
*/
int32_t spi_s_sync_set_data_order(struct spi_s_sync_descriptor *spi, const enum spi_data_order dord);
/** \brief Enable/disable break on SS desert detection
*
* \param[in,out] spi Pointer to the HAL SPI instance.
* \param[in] enable Set to \c true to break R/W loop on SS desert.
*/
void spi_s_sync_break_on_ss_detect(struct spi_s_sync_descriptor *spi, const bool enable);
/** \brief Write/read at the same time
*
* \param[in,out] spi Pointer to the HAL SPI instance.
* \param[in] xfer Pointer to the transfer information (\ref spi_xfer).
*
* \return Operation result.
* \retval <0 Error.
* \retval >=0 Number of characters transferred.
*/
int32_t spi_s_sync_transfer(struct spi_s_sync_descriptor *spi, const struct spi_xfer *xfer);
/**
* \brief Return I/O descriptor for this SPI instance
*
* This function will return an I/O instance for this SPI driver instance
*
* \param[in] spi An SPI slave descriptor, which is used to communicate through
* SPI
* \param[in] io A pointer to an I/O descriptor pointer type
*
* \return Error code.
* \retval 0 No error detected
* \retval <0 Error code
*/
int32_t spi_s_sync_get_io_descriptor(struct spi_s_sync_descriptor *spi, struct io_descriptor **io);
/** \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t spi_s_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_SPI_S_SYNC_H_INCLUDED */

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/**
* \file
*
* \brief Timer task functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_TIMER_H_INCLUDED
#define _HAL_TIMER_H_INCLUDED
#include <utils_list.h>
#include <hpl_timer.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_timer
*
* @{
*/
/**
* \brief Timer mode type
*/
enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT };
/**
* \brief Timer task descriptor
*
* The timer task descriptor forward declaration.
*/
struct timer_task;
/**
* \brief Timer task callback function type
*/
typedef void (*timer_cb_t)(const struct timer_task *const timer_task);
/**
* \brief Timer task structure
*/
struct timer_task {
struct list_element elem; /*! List element. */
uint32_t time_label; /*! Absolute timer start time. */
uint32_t interval; /*! Number of timer ticks before calling the task. */
timer_cb_t cb; /*! Function pointer to the task. */
enum timer_task_mode mode; /*! Task mode: one shot or repeat. */
};
/**
* \brief Timer structure
*/
struct timer_descriptor {
struct _timer_device device;
uint32_t time;
struct list_descriptor tasks; /*! Timer tasks list. */
volatile uint8_t flags;
};
/**
* \brief Initialize timer
*
* This function initializes the given timer.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr A timer descriptor to initialize
* \param[in] hw The pointer to the hardware instance
* \param[in] func The pointer to a set of function pointers
*
* \return Initialization status.
*/
int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func);
/**
* \brief Deinitialize timer
*
* This function deinitializes the given timer.
* It checks if the given hardware is initialized and if the given hardware is
* permitted to be deinitialized.
*
* \param[in] descr A timer descriptor to deinitialize
*
* \return De-initialization status.
*/
int32_t timer_deinit(struct timer_descriptor *const descr);
/**
* \brief Start timer
*
* This function starts the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to start
*
* \return Timer starting status.
*/
int32_t timer_start(struct timer_descriptor *const descr);
/**
* \brief Stop timer
*
* This function stops the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to stop
*
* \return Timer stopping status.
*/
int32_t timer_stop(struct timer_descriptor *const descr);
/**
* \brief Set amount of clock cycles per timer tick
*
* This function sets the amount of clock cycles per timer tick for the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to stop
* \param[in] clock_cycles The amount of clock cycles per tick to set
*
* \return Setting clock cycles amount status.
*/
int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles);
/**
* \brief Retrieve the amount of clock cycles in a tick
*
* This function retrieves how many clock cycles there are in a single timer tick.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to convert ticks to
* clock cycles
* \param[out] cycles The amount of clock cycles
*
* \return The status of clock cycles retrieving.
*/
int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles);
/**
* \brief Add timer task
*
* This function adds the given timer task to the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to add task to
* \param[in] task A task to add
*
* \return Timer's task adding status.
*/
int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task);
/**
* \brief Remove timer task
*
* This function removes the given timer task from the given timer.
* It checks if the given hardware is initialized.
*
* \param[in] descr The timer descriptor of a timer to remove task from
* \param[in] task A task to remove
*
* \return Timer's task removing status.
*/
int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t timer_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_TIMER_H_INCLUDED */

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/**
* \file
*
* \brief ADC related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_ADC_ASYNC_H_INCLUDED
#define _HPL_ADC_ASYNC_H_INCLUDED
/**
* \addtogroup HPL ADC
*
* \section hpl_async_adc_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_adc_sync.h"
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief ADC device structure
*
* The ADC device structure forward declaration.
*/
struct _adc_async_device;
/**
* \brief ADC callback types
*/
enum _adc_async_callback_type { ADC_ASYNC_DEVICE_CONVERT_CB, ADC_ASYNC_DEVICE_MONITOR_CB, ADC_ASYNC_DEVICE_ERROR_CB };
/**
* \brief ADC interrupt callbacks
*/
struct _adc_async_callbacks {
void (*window_cb)(struct _adc_async_device *device, const uint8_t channel);
void (*error_cb)(struct _adc_async_device *device, const uint8_t channel);
};
/**
* \brief ADC channel interrupt callbacks
*/
struct _adc_async_ch_callbacks {
void (*convert_done)(struct _adc_async_device *device, const uint8_t channel, const uint16_t data);
};
/**
* \brief ADC descriptor device structure
*/
struct _adc_async_device {
struct _adc_async_callbacks adc_async_cb;
struct _adc_async_ch_callbacks adc_async_ch_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous ADC
*
* This function does low level ADC configuration.
*
* param[in] device The pointer to ADC device instance
* param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw);
/**
* \brief Deinitialize ADC
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_async_deinit(struct _adc_async_device *const device);
/**
* \brief Enable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Disable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Retrieve ADC conversion data size
*
* \param[in] device The pointer to ADC device instance
*
* \return The data size in bytes
*/
uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device);
/**
* \brief Check if conversion is done
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* \return The status of conversion
* \retval true The conversion is done
* \retval false The conversion is not done
*/
bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Make conversion
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_async_convert(struct _adc_async_device *const device);
/**
* \brief Retrieve the conversion result
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* The result value
*/
uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Set reference source
*
* \param[in] device The pointer to ADC device instance
* \param[in] reference A reference source to set
*/
void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference);
/**
* \brief Set resolution
*
* \param[in] device The pointer to ADC device instance
* \param[in] resolution A resolution to set
*/
void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* \param[in] device The pointer to ADC device instance
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*/
void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set conversion mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A conversion mode to set
*/
void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode);
/**
* \brief Set differential mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*/
void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set gain
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] gain A gain to set
*/
void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain);
/**
* \brief Set window mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A mode to set
*/
void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode);
/**
* \brief Set lower threshold
*
* \param[in] device The pointer to ADC device instance
* \param[in] low_threshold A lower threshold to set
* \param[in] up_threshold An upper thresholds to set
*/
void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* \param[in] device The pointer to ADC device instance
* \param[out] state The threshold state
*/
void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state);
/**
* \brief Enable/disable ADC channel interrupt
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] type The type of interrupt to disable/enable if applicable
* \param[in] state Enable or disable
*/
void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
const enum _adc_async_callback_type type, const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_ADC_ASYNC_H_INCLUDED */

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/**
* \file
*
* \brief ADC related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_ADC_DMA_H_INCLUDED
#define _HPL_ADC_DMA_H_INCLUDED
/**
* \addtogroup HPL ADC
*
* \section hpl_dma_adc_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <hpl_adc_sync.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief ADC device structure
*
* The ADC device structure forward declaration.
*/
struct _adc_dma_device;
/**
* \brief ADC callback types
*/
enum _adc_dma_callback_type { ADC_DMA_DEVICE_COMPLETE_CB, ADC_DMA_DEVICE_ERROR_CB };
/**
* \brief ADC interrupt callbacks
*/
struct _adc_dma_callbacks {
void (*complete)(struct _adc_dma_device *device, const uint16_t data);
void (*error)(struct _adc_dma_device *device);
};
/**
* \brief ADC descriptor device structure
*/
struct _adc_dma_device {
struct _adc_dma_callbacks adc_dma_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous ADC
*
* This function does low level ADC configuration.
*
* param[in] device The pointer to ADC device instance
* param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw);
/**
* \brief Deinitialize ADC
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_dma_deinit(struct _adc_dma_device *const device);
/**
* \brief Enable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel);
/**
* \brief Disable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel);
/**
* \brief Return address of ADC DMA source
*
* \param[in] device The pointer to ADC device instance
*
* \return ADC DMA source address
*/
uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device);
/**
* \brief Retrieve ADC conversion data size
*
* \param[in] device The pointer to ADC device instance
*
* \return The data size in bytes
*/
uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device);
/**
* \brief Check if conversion is done
*
* \param[in] device The pointer to ADC device instance
*
* \return The status of conversion
* \retval true The conversion is done
* \retval false The conversion is not done
*/
bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device);
/**
* \brief Make conversion
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_dma_convert(struct _adc_dma_device *const device);
/**
* \brief Set reference source
*
* \param[in] device The pointer to ADC device instance
* \param[in] reference A reference source to set
*/
void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference);
/**
* \brief Set resolution
*
* \param[in] device The pointer to ADC device instance
* \param[in] resolution A resolution to set
*/
void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* \param[in] device The pointer to ADC device instance
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*/
void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set conversion mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A conversion mode to set
*/
void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode);
/**
* \brief Set differential mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*/
void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set gain
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] gain A gain to set
*/
void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain);
/**
* \brief Set window mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A mode to set
*/
void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode);
/**
* \brief Set thresholds
*
* \param[in] device The pointer to ADC device instance
* \param[in] low_threshold A lower thresholds to set
* \param[in] up_threshold An upper thresholds to set
*/
void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* \param[in] device The pointer to ADC device instance
* \param[out] state The threshold state
*/
void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_ADC_DMA_H_INCLUDED */

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/**
* \file
*
* \brief ADC related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_ADC_SYNC_H_INCLUDED
#define _HPL_ADC_SYNC_H_INCLUDED
/**
* \addtogroup HPL ADC
*
* \section hpl_adc_sync_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "compiler.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief ADC reference source
*/
typedef uint8_t adc_reference_t;
/**
* \brief ADC resolution
*/
typedef uint8_t adc_resolution_t;
/**
* \brief ADC positive input for channel
*/
typedef uint8_t adc_pos_input_t;
/**
* \brief ADC negative input for channel
*/
typedef uint8_t adc_neg_input_t;
/**
* \brief ADC threshold
*/
typedef uint16_t adc_threshold_t;
/**
* \brief ADC gain
*/
typedef uint8_t adc_gain_t;
/**
* \brief ADC conversion mode
*/
enum adc_conversion_mode { ADC_CONVERSION_MODE_SINGLE_CONVERSION = 0, ADC_CONVERSION_MODE_FREERUN };
/**
* \brief ADC differential mode
*/
enum adc_differential_mode { ADC_DIFFERENTIAL_MODE_SINGLE_ENDED = 0, ADC_DIFFERENTIAL_MODE_DIFFERENTIAL };
/**
* \brief ADC window mode
*/
typedef uint8_t adc_window_mode_t;
/**
* \brief ADC threshold status
*/
typedef bool adc_threshold_status_t;
/**
* \brief ADC sync descriptor device structure
*/
struct _adc_sync_device {
void *hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous ADC
*
* This function does low level ADC configuration.
*
* param[in] device The pointer to ADC device instance
* param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw);
/**
* \brief Deinitialize ADC
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_sync_deinit(struct _adc_sync_device *const device);
/**
* \brief Enable ADC
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Disable ADC
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Retrieve ADC conversion data size
*
* \param[in] device The pointer to ADC device instance
*
* \return The data size in bytes
*/
uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device);
/**
* \brief Check if conversion is done
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* \return The status of conversion
* \retval true The conversion is done
* \retval false The conversion is not done
*/
bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Make conversion
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_sync_convert(struct _adc_sync_device *const device);
/**
* \brief Retrieve the conversion result
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* \return The result value of channel
*/
uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Set reference source
*
* \param[in] device The pointer to ADC device instance
* \param[in] reference A reference source to set
*/
void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference);
/**
* \brief Set resolution
*
* \param[in] device The pointer to ADC device instance
* \param[in] resolution A resolution to set
*/
void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* \param[in] device The pointer to ADC device instance
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*/
void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set conversion mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A conversion mode to set
*/
void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode);
/**
* \brief Set differential mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*/
void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set gain
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] gain A gain to set
*/
void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain);
/**
* \brief Set window mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A mode to set
*/
void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode);
/**
* \brief Set threshold
*
* \param[in] device The pointer to ADC device instance
* \param[in] low_threshold A lower threshold to set
* \param[in] up_threshold An upper thresholds to set
*/
void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* \param[in] device The pointer to ADC device instance
* \param[out] state The threshold state
*/
void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_ADC_SYNC_H_INCLUDED */

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/**
* \file
*
* \brief Generic CMCC(Cortex M Cache Controller) related functionality.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef HPL_CMCC_H_
#define HPL_CMCC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
/**
* \Cache driver MACROS
*/
#define CMCC_DISABLE 0U
#define CMCC_ENABLE 1U
#define IS_CMCC_DISABLED 0U
#define IS_CMCC_ENABLED 1U
#define CMCC_WAY_NOS 4U
#define CMCC_LINE_NOS 64U
#define CMCC_MONITOR_DISABLE 0U
/**
* \brief Cache size configurations
*/
enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB };
/**
* \brief Way Numbers
*/
enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 };
/**
* \brief Cache monitor configurations
*/
enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT };
/**
* \brief Cache configuration structure
*/
struct _cache_cfg {
enum conf_cache_size cache_size;
bool data_cache_disable;
bool inst_cache_disable;
bool gclk_gate_disable;
};
/**
* \brief Cache enable status
*/
static inline bool _is_cache_enabled(const void *hw)
{
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false);
}
/**
* \brief Cache disable status
*/
static inline bool _is_cache_disabled(const void *hw)
{
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false);
}
/**
* \brief Cache enable
*/
static inline int32_t _cmcc_enable(const void *hw)
{
int32_t return_value;
if (_is_cache_disabled(hw)) {
hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN);
return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE;
} else {
return_value = ERR_NO_CHANGE;
}
return return_value;
}
/**
* \brief Cache disable
*/
static inline int32_t _cmcc_disable(const void *hw)
{
hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos));
while (!(_is_cache_disabled(hw)))
;
return ERR_NONE;
}
/**
* \brief Initialize Cache Module
*
* This function initialize low level cmcc module configuration.
*
* \return initialize status
*/
int32_t _cmcc_init(void);
/**
* \brief Configure CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] cache configuration structure pointer
*
* \return status of operation
*/
int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl);
/**
* \brief Enable data cache in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
*
* \return status of operation
*/
int32_t _cmcc_enable_data_cache(const void *hw, bool value);
/**
* \brief Enable instruction cache in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
*
* \return status of operation
*/
int32_t _cmcc_enable_inst_cache(const void *hw, bool value);
/**
* \brief Enable clock gating in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
*
* \return status of operation
*/
int32_t _cmcc_enable_clock_gating(const void *hw, bool value);
/**
* \brief Configure the cache size in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from cache size configuration enumerator
* 0->1K, 1->2K, 2->4K(default)
*
* \return status of operation
*/
int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size);
/**
* \brief Lock the mentioned WAY in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num_index" enumerator
*
* \return status of operation
*/
int32_t _cmcc_lock_way(const void *hw, enum way_num_index);
/**
* \brief Unlock the mentioned WAY in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num_index" enumerator
*
* \return status of operation
*/
int32_t _cmcc_unlock_way(const void *hw, enum way_num_index);
/**
* \brief Invalidate the mentioned cache line in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num" enumerator (valid arg is 0-3)
* \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
*
* \return status of operation
*/
int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num);
/**
* \brief Invalidate entire cache entries in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_invalidate_all(const void *hw);
/**
* \brief Configure cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from cache monitor configurations enumerator
*
* \return status of operation
*/
int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg);
/**
* \brief Enable cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_enable_monitor(const void *hw);
/**
* \brief Disable cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_disable_monitor(const void *hw);
/**
* \brief Reset cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_reset_monitor(const void *hw);
/**
* \brief Get cache monitor event counter value from CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return event counter value
*/
uint32_t _cmcc_get_monitor_event_count(const void *hw);
#ifdef __cplusplus
}
#endif
#endif /* HPL_CMCC_H_ */

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/**
* \file
*
* \brief CPU core related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_CORE_H_INCLUDED
#define _HPL_CORE_H_INCLUDED
/**
* \addtogroup HPL Core
*
* \section hpl_core_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_core_port.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_CORE_H_INCLUDED */

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/**
* \file
*
* \brief Custom Control Logic functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_CUSTOM_LOGIC_H_INCLUDED
#define _HPL_CUSTOM_LOGIC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Initialize the custom logic hardware
* \return Initialization operation status
*/
int32_t _custom_logic_init(void);
/**
* \brief Disable and reset the custom logic hardware
*/
void _custom_logic_deinit(void);
/**
* \brief Enable the custom logic hardware
* \return Initialization operation status
*/
int32_t _custom_logic_enable(void);
/**
* \brief Disable the custom logic hardware
*/
void _custom_logic_disable(void);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_CUSTOM_LOGIC_H_INCLUDED */

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