fixed current calibration, before merging to slave
This commit is contained in:
parent
02ade8660d
commit
02162af995
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@ -10,6 +10,7 @@
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#define ETHERCAT_SLAVEDEF_H_
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#include "Ethercat_QSPI.h"
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#include "arm_math.h"
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extern volatile int32_t _channel_data[8];
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@ -10,6 +10,7 @@
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#define ETHERCAT_SLAVEDEF_H_
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#include "Ethercat_QSPI.h"
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#include "arm_math.h"
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extern volatile int32_t _channel_data[8];
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@ -7,7 +7,6 @@
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#include "bldc.h"
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#include "statemachine.h"
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#include "utilities.h"
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#include "Ethercat_SlaveDef.h"
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@ -217,13 +216,12 @@ void exec_commutation(BLDCMotor_t* const motor)
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volatile uint8_t currentHall = motor->readHall();
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motor->motor_status.currentHallPattern = currentHall;
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//if ((currentHall == INVALID_HALL_0)||(currentHall == INVALID_HALL_7))
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//{
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//hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw, DISABLE_PATTERN);
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//motor->motor_state.currentstate == MOTOR_FAULT;
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//motor->motor_state.fault == MOTOR_HALLSENSORINVALID;
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//return;
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//}
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if (currentHall == INVALID_HALL_7)
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{
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motor->motor_state.currentstate == MOTOR_FAULT;
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motor->motor_state.fault == MOTOR_HALLSENSORINVALID;
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return;
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}
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// ----------------------------------------------------------------------
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// Set Pattern Buffers
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@ -232,7 +230,7 @@ void exec_commutation(BLDCMotor_t* const motor)
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motor->motor_setpoints.directionOffset];
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//TCC0->PATTBUF.reg = temp_M1;
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Tcc * tmp = (Tcc *)motor->motor_param->pwm_desc->device.hw;
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Tcc * tmp = (Tcc *)motor->pwm_desc->device.hw;
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tmp->PATTBUF.reg = (uint16_t)temp_M1;
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//motor->motor_param->pwm_desc->device.hw->PATTBUF.reg = temp_M1;
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//hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw, temp_M1);
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@ -303,8 +301,8 @@ void calculate_motor_speed(BLDCMotor_t* const motor)
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{
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//tic_port(DEBUG_2_PORT);
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volatile uint32_t temp_rpm = 0;
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hri_tccount32_read_CC_reg(motor->motor_param->speedtimer_hw, 0); /* Read CC0 but throw away)*/
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volatile uint32_t period_after_capture = hri_tccount32_read_CC_reg(motor->motor_param->speedtimer_hw, 1);
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hri_tccount32_read_CC_reg(motor->speedtimer_hw, 0); /* Read CC0 but throw away)*/
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volatile uint32_t period_after_capture = hri_tccount32_read_CC_reg(motor->speedtimer_hw, 1);
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if((period_after_capture >= UINT32_MAX)||(period_after_capture == 0)||(period_after_capture > 600000)) {
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motor->motor_status.calc_rpm = 0;
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} else {
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@ -362,7 +360,7 @@ void calculate_motor_speed(BLDCMotor_t* const motor)
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void disable_phases(BLDCMotor_t* const motor)
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{
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Tcc * tmp = (Tcc *)motor->motor_param->pwm_desc->device.hw;
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Tcc * tmp = (Tcc *)motor->pwm_desc->device.hw;
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tmp->PATTBUF.reg = DISABLE_PATTERN;
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}
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@ -512,124 +510,40 @@ volatile uint8_t readHallSensorM2(void)
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// ----------------------------------------------------------------------
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void read_zero_current_offset_value(BLDCMotor_t *motor1, BLDCMotor_t *motor2)
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{
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uint32_t phase_A_zero_current_offset_temp = 0;
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uint32_t phase_B_zero_current_offset_temp = 0;
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volatile uint16_t zero_current_offset_temp[2] = {0,0};
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uint8_t samples = 32;
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uint8_t i;
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// ------------------------------------------------------------------
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// Motor 1
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// -------------------------------------------------------------------
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volatile int32_t phase_zero_current_offset [NUM_CUR_SENSORS] = {0};
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volatile int16_t zero_current_offset_temp = 0;
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const uint8_t samples = 32;
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adc_sync_enable_channel(&ADC_1, 9);
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//adc_sync_enable_channel(&ADC_1, 0);
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/* Single ended */
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//ADC1->INPUTCTRL.reg = 0x1809;
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/* Differential */
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ADC1->INPUTCTRL.reg = 0x0089;
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while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
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for (i=0; i<samples; i++)
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for (int n=0; n<NUM_CUR_SENSORS; n++)
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{
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volatile uint16_t zero_current_offset_temp[2] = {0,0};
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while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
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ADC1->SWTRIG.bit.START = true; /* Start the ADC using a software trigger. */
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while (ADC1->INTFLAG.bit.RESRDY == 0); /* Wait for the result ready flag to be set. */
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ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY; /* Clear the flag. */
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zero_current_offset_temp[0] = ADC1->RESULT.reg; /* Read the value. */
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phase_A_zero_current_offset_temp += zero_current_offset_temp[0];
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ADC1->INPUTCTRL.reg = adc1_seq_regs[n];
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for (int i=0; i<samples; i++)
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{
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while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
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ADC1->SWTRIG.bit.START = true; /* Start the ADC using a software trigger. */
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while (ADC1->INTFLAG.bit.RESRDY == 0); /* Wait for the result ready flag to be set. */
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ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY; /* Clear the flag. */
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zero_current_offset_temp = (int16_t)ADC1->RESULT.reg; /* Read the value. */
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phase_zero_current_offset[n] += zero_current_offset_temp;
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}
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phase_zero_current_offset[n] = phase_zero_current_offset[n]/samples;
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}
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adc_sync_disable_channel(&ADC_1, 9);
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/* Set Motor Variables */
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motor1->Voffset_lsb.A = phase_A_zero_current_offset_temp/samples;
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motor1->Voffset_lsb.A = phase_zero_current_offset[0];
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motor1->Voffset_lsb.B = phase_zero_current_offset[1];
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motor2->Voffset_lsb.A = phase_zero_current_offset[2];
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motor2->Voffset_lsb.B = phase_zero_current_offset[3];
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/* Single ended */
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//ADC1->INPUTCTRL.reg = 0x1808;
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/* Differential */
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ADC1->INPUTCTRL.reg = 0x0088;
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while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
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for (i=0; i<samples; i++)
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{
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while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
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ADC1->SWTRIG.bit.START = true; /* Start the ADC using a software trigger. */
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while (ADC1->INTFLAG.bit.RESRDY == 0); /* Wait for the result ready flag to be set. */
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ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY; /* Clear the flag. */
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zero_current_offset_temp[1] = ADC1->RESULT.reg; /* Read the value. */
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phase_B_zero_current_offset_temp += zero_current_offset_temp[1];
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}
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/* Set Motor Variables */
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motor1->Voffset_lsb.B = phase_B_zero_current_offset_temp/samples;
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adc_sync_disable_channel(&ADC_1, 8);
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adc_sync_enable_channel(&ADC_1, 7);
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//adc_sync_enable_channel(&ADC_1, 0);
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/* Check for Defective current sensor based on offset from nominal 1.5V (O current voltage) */
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if ((abs(motor1->Voffset_lsb.A) > MAX_CUR_SENSE_OFFSET) || (abs(motor1->Voffset_lsb.B) > MAX_CUR_SENSE_OFFSET))
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{
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motor1->motor_state.currentstate = MOTOR_FAULT;
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motor1->motor_state.fault = MOTOR_CURRENTS_SENSOR;
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}
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// ------------------------------------------------------------------
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// Motor 2
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// -------------------------------------------------------------------
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phase_A_zero_current_offset_temp = 0;
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phase_B_zero_current_offset_temp = 0;
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/* Single ended */
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//ADC1->INPUTCTRL.reg = 0x1807;
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/* Differential */
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ADC1->INPUTCTRL.reg = 0x0087;
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while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
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for (i=0; i<samples; i++)
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{
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volatile uint16_t zero_current_offset_temp[2] = {0,0};
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while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
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ADC1->SWTRIG.bit.START = true; /* Start the ADC using a software trigger. */
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while (ADC1->INTFLAG.bit.RESRDY == 0); /* Wait for the result ready flag to be set. */
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ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY; /* Clear the flag. */
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zero_current_offset_temp[0] = ADC1->RESULT.reg; /* Read the value. */
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phase_A_zero_current_offset_temp += zero_current_offset_temp[0];
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}
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/* Set Motor Variables */
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motor2->Voffset_lsb.A = phase_A_zero_current_offset_temp/samples;
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/* Single ended */
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//ADC1->INPUTCTRL.reg = 0x1806;
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/* Differential */
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ADC1->INPUTCTRL.reg = 0x0086;
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while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
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for (i=0; i<samples; i++)
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{
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while (ADC1->STATUS.bit.ADCBUSY) {}; /* Wait for bus synchronization. */
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ADC1->SWTRIG.bit.START = true; /* Start the ADC using a software trigger. */
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while (ADC1->INTFLAG.bit.RESRDY == 0); /* Wait for the result ready flag to be set. */
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ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY; /* Clear the flag. */
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zero_current_offset_temp[1] = ADC1->RESULT.reg; /* Read the value. */
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phase_B_zero_current_offset_temp += zero_current_offset_temp[1];
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}
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/* Set Motor Variables */
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motor2->Voffset_lsb.B = phase_B_zero_current_offset_temp/samples;
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adc_sync_disable_channel(&ADC_1, 6);
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//adc_sync_disable_channel(&ADC_1, 0);
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if ((abs(motor2->Voffset_lsb.A) > MAX_CUR_SENSE_OFFSET) || (abs(motor2->Voffset_lsb.B) > MAX_CUR_SENSE_OFFSET))
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{
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motor2->motor_state.currentstate = MOTOR_FAULT;
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@ -41,10 +41,16 @@
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#define ADC_LSB_SIZE (ADC_VOLTAGE_REFERENCE/ADC_MAX_COUNTS)
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#define LSB_TO_PU (ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY)
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//static const uint32_t adc1_seq_regs[4] = {0x0089, 0x0088, 0x0087, 0x0086};
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//static volatile int16_t adc0_res[4] = {0};
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//static volatile int16_t adc1_res[4] = {0};
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extern const uint32_t adc1_seq_regs[4];
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extern volatile int16_t adc1_res[4];
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// ----------------------------------------------------------------------
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// Define the control and PWM frequencies:
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// ----------------------------------------------------------------------
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// 16kHz is the maximum frequency according to the calculation duration in the mode run and spin.
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#define DEVICE_MCU_FREQUENCY_Hz (120000000U)
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#define DEVICE_SPEEDTC_DIV (4U)
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#define DEVICE_SPEEDTC_FREQUENCY_Hz (DEVICE_MCU_FREQUENCY_Hz/DEVICE_SPEEDTC_DIV)
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#define CURRENT_SENSOR_SENSITIVITY 0.4f //V/A
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#define ONEON_CURRENT_SENSOR_SENSITIVITY 2.5f //V/A
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#define MAX_CUR_SENSE_OFFSET 100
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#define NUM_CUR_SENSORS 4
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// ----------------------------------------------------------------------
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// global variables
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// ----------------------------------------------------------------------
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static const uint8_t HALL_PATTERN_ARRAY[16] = {0, 5, 3, 1, 6, 4, 2, 0, 0, 3, 6, 2, 5, 1, 4, 0 };
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static const uint8_t MOTOR_COMMUTATION_STEPS[8] = {9, 1, 3, 2, 5, 6, 4, 9};
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volatile BLDCMotor_t Motor1;
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volatile BLDCMotor_t Motor2;
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volatile MOTOR_STATE_t Motor1_Status;
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volatile MOTOR_STATE_t Motor2_Status;
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static volatile BLDCMotor_t Motor1 = {
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.pwm_desc = &PWM_0,
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.speedtimer_hw = TC2,
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};
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static volatile BLDCMotor_t Motor2 = {
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.pwm_desc = &PWM_1,
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.speedtimer_hw = TC4,
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};
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static volatile MOTOR_STATE_t Motor1_Status;
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static volatile MOTOR_STATE_t Motor2_Status;
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// ----------------------------------------------------------------------
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// functions
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@ -82,8 +82,10 @@ volatile typedef struct BLDCmotor
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{
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/* Hardware */
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volatile BLDCMotor_param_t *motor_param;
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volatile MOTOR_STATE_t motor_state;
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struct pwm_descriptor const *pwm_desc;
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void *const speedtimer_hw;
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/* Status */
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volatile MOTOR_STATE_t motor_state;
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volatile MOTOR_Status motor_status;
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/* Measured Values */
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volatile MOTOR_PHASES_t Iphase_pu;
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@ -27,19 +27,19 @@
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#define CONF_ADC_0_SEQUENCER_CHANNEL 6U
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#define CONF_ADC_1_SEQUENCER_CHANNEL 7U
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/* Single Ended */
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//const uint32_t adc_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808};
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/* Differential */
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const uint32_t adc_seq_regs[4] = {0x0089, 0x0088, 0x0087, 0x0086};
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const uint32_t adc0_seq_regs[4] = {0};
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const uint32_t adc1_seq_regs[4] = {0x0089, 0x0088, 0x0087, 0x0086}; /* Differential */
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//const uint32_t adc1_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808}; /* Single Ended */
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volatile int16_t adc0_res[4] = {0};
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volatile int16_t adc1_res[4] = {0};
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volatile int16_t adc_res[4] = {0};
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struct _dma_resource *adc_sram_dma_resource;
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struct _dma_resource *adc_dmac_sequence_resource;
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// ----------------------------------------------------------------------
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// PWM Timer Initialization
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// ----------------------------------------------------------------------
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inline static void configure_tcc_pwm(void)
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static void configure_tcc_pwm(void)
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{
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/* TCC0 */
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hri_tcc_set_WEXCTRL_OTMX_bf(TCC0, 0x02);
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}
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/* Peripherals should be configured before interacting with dma
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* CH0 - QSPI_RX - For ECAT DMA Mode - Currently Disabled in ASTART
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* CH1 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin
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* CH2 - SERCOM2_RX(SPI2) - Expansion IF (EMG) - Beat Transfer Event Drives CS Pin
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* CH3 - SERCOM5_RX(SPI3) - Angle Sensor
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* CH4 - ADC0 - Result Ready (Unused on master) - Currently Disabled in ASTART
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* CH5 - ADC1 - Result Ready
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* CH6 - ADC0 - Sequencer (Unused on master) - Currently Disabled in ASTART
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* CH7 - ADC1 - Sequencer - Triggered by TCC0 overflow event
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* CH8 - SERCOM2_TX(SPI2)
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* CH9 - SERCOM5_TX(SPI3)
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* CH10 - SERCOM1_TX(SPI1)
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* CH11 - QSPI_TX - For ECAT DMA Mode - Currently Disabled in ASTART
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*/
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inline static void init_dma(void)
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{
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spi_master_init_dma_descriptors();
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adc_init_dma_descriptors();
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}
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// ----------------------------------------------------------------------
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// ADC Initialization
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// ----------------------------------------------------------------------
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inline void adc_init_dma_descriptors(void)
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{
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adc_sram_dmac_init();
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adc_dmac_sequence_init();
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hri_adc_set_DSEQCTRL_INPUTCTRL_bit(ADC1);
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hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC1);
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}
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inline void adc_dmac_sequence_init()
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static void adc_dmac_sequence_init()
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{
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/* Configure the DMAC source address, destination address,
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* next descriptor address, data count and Enable the DMAC Channel
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*/
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_dma_set_source_address(CONF_ADC_1_SEQUENCER_CHANNEL, (const void *)adc_seq_regs);
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_dma_set_source_address(CONF_ADC_1_SEQUENCER_CHANNEL, (const void *)adc1_seq_regs);
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_dma_set_destination_address(CONF_ADC_1_SEQUENCER_CHANNEL, (const void *)&ADC1->DSEQDATA.reg);
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_dma_set_data_amount(CONF_ADC_1_SEQUENCER_CHANNEL, 4);
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_dma_set_next_descriptor(CONF_ADC_1_SEQUENCER_CHANNEL, CONF_ADC_1_SEQUENCER_CHANNEL);
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@ -137,10 +105,10 @@ inline void adc_dmac_sequence_init()
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hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[CONF_ADC_1_SEQUENCER_CHANNEL], 0x01); //Suspend
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}
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inline void adc_sram_dmac_init()
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static void adc_sram_dmac_init()
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{
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_dma_set_source_address(CONF_ADC_1_ADC_RES_READY_CHANNEL, (const void *)&ADC1->RESULT.reg);
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_dma_set_destination_address(CONF_ADC_1_ADC_RES_READY_CHANNEL, (const void *)adc_res);
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_dma_set_destination_address(CONF_ADC_1_ADC_RES_READY_CHANNEL, (const void *)adc1_res);
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_dma_set_data_amount(CONF_ADC_1_ADC_RES_READY_CHANNEL, 4);
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_dma_set_irq_state(CONF_ADC_1_ADC_RES_READY_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
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_dma_get_channel_resource(&adc_sram_dma_resource, CONF_ADC_1_ADC_RES_READY_CHANNEL);
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_dma_enable_transaction(CONF_ADC_1_ADC_RES_READY_CHANNEL, false);
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}
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// ----------------------------------------------------------------------
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// ADC Initialization
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// ----------------------------------------------------------------------
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static void adc_init_dma_descriptors(void)
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{
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adc_sram_dmac_init();
|
||||
adc_dmac_sequence_init();
|
||||
hri_adc_set_DSEQCTRL_INPUTCTRL_bit(ADC1);
|
||||
hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC1);
|
||||
}
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// SPI DMA communication between Master & Slave Board
|
||||
// ----------------------------------------------------------------------
|
||||
|
@ -160,7 +141,7 @@ inline void adc_sram_dmac_init()
|
|||
extern DmacDescriptor _descriptor_section[DMAC_CH_NUM];
|
||||
extern DmacDescriptor _write_back_section[DMAC_CH_NUM];
|
||||
|
||||
void boardToBoardTransferInit(void)
|
||||
static void boardToBoardTransferInit(void)
|
||||
{
|
||||
struct io_descriptor *io;
|
||||
spi_m_dma_get_io_descriptor(&SPI_1_MSIF, &io);
|
||||
|
@ -175,7 +156,7 @@ void boardToBoardTransferInit(void)
|
|||
spi_m_dma_enable(&SPI_1_MSIF);
|
||||
}
|
||||
|
||||
void spi_master_init_dma_descriptors()
|
||||
static void spi_master_init_dma_descriptors()
|
||||
{
|
||||
_dma_set_source_address(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL,
|
||||
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
|
||||
|
@ -203,7 +184,25 @@ void spi_master_init_dma_descriptors()
|
|||
|
||||
}
|
||||
|
||||
|
||||
/* Peripherals should be configured before interacting with dma
|
||||
* CH0 - QSPI_RX - For ECAT DMA Mode - Currently Disabled in ASTART
|
||||
* CH1 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin
|
||||
* CH2 - SERCOM2_RX(SPI2) - Expansion IF (EMG) - Beat Transfer Event Drives CS Pin
|
||||
* CH3 - SERCOM5_RX(SPI3) - Angle Sensor
|
||||
* CH4 - ADC0 - Result Ready (Unused on master) - Currently Disabled in ASTART
|
||||
* CH5 - ADC1 - Result Ready
|
||||
* CH6 - ADC0 - Sequencer (Unused on master) - Currently Disabled in ASTART
|
||||
* CH7 - ADC1 - Sequencer - Triggered by TCC0 overflow event
|
||||
* CH8 - SERCOM2_TX(SPI2)
|
||||
* CH9 - SERCOM5_TX(SPI3)
|
||||
* CH10 - SERCOM1_TX(SPI1)
|
||||
* CH11 - QSPI_TX - For ECAT DMA Mode - Currently Disabled in ASTART
|
||||
*/
|
||||
static void init_dma(void)
|
||||
{
|
||||
spi_master_init_dma_descriptors();
|
||||
adc_init_dma_descriptors();
|
||||
}
|
||||
|
||||
|
||||
#endif /* CONFIGURATION_H_ */
|
|
@ -10,7 +10,6 @@
|
|||
#define INTERRUPTS_H_
|
||||
|
||||
|
||||
|
||||
/* TC0 - Interrupt Handler
|
||||
* Configured to trigger @ 1ms
|
||||
*/
|
||||
|
@ -79,7 +78,7 @@ static void pwm_cb(const struct pwm_descriptor *const descr)
|
|||
volatile int x = 0;
|
||||
}
|
||||
|
||||
void adc_sram_dma_callback(struct _dma_resource *adc_dma_res)
|
||||
static void adc_sram_dma_callback(struct _dma_resource *adc_dma_res)
|
||||
{
|
||||
Motor1.timerflags.adc_readings_ready_tic = true;
|
||||
Motor2.timerflags.adc_readings_ready_tic = true;
|
||||
|
@ -125,7 +124,7 @@ static void M2_RESET_BAR(void)
|
|||
// ----------------------------------------------------------------------
|
||||
void ADS1299_dataReadyISR(void)
|
||||
{
|
||||
ADS1299.data_ReadyFlag = true;
|
||||
//ADS1299.data_ReadyFlag = true;
|
||||
//int32_t* temp = ADS1299_UPDATECHANNELDATA();
|
||||
volatile int x = 1;
|
||||
}
|
||||
|
|
|
@ -3,17 +3,20 @@
|
|||
// ----------------------------------------------------------------------
|
||||
// Header Files
|
||||
// ----------------------------------------------------------------------
|
||||
#include "bldc.h"
|
||||
#include "bldc_types.h"
|
||||
|
||||
|
||||
#include "EtherCAT_QSPI.h"
|
||||
#include "ADS1299.h"
|
||||
#include "EtherCAT_SlaveDef.h"
|
||||
|
||||
//#include "MSIF_master.h"
|
||||
#include "configuration.h"
|
||||
#include "bldc.h"
|
||||
#include "bldc_types.h"
|
||||
#include "EtherCAT_SlaveDef.h"
|
||||
#include "interrupts.h"
|
||||
#include "statemachine.h"
|
||||
|
||||
#include "angle_sensors.h"
|
||||
#include "ADS1299.h"
|
||||
|
||||
|
||||
|
||||
|
@ -26,8 +29,8 @@ void process_currents()
|
|||
volatile int16_t phase_A_current_raw, phase_B_current_raw;
|
||||
|
||||
/* Motor 1 */
|
||||
phase_A_current_raw = (adc_res[0] - Motor1.Voffset_lsb.A);
|
||||
phase_B_current_raw = (adc_res[1] - Motor1.Voffset_lsb.B)*-1;
|
||||
phase_A_current_raw = (adc1_res[0] + Motor1.Voffset_lsb.A);
|
||||
phase_B_current_raw = (adc1_res[1] + Motor1.Voffset_lsb.B)*-1;
|
||||
// Covert from LSB to PU (A) and filter out small readings
|
||||
Motor1.Iphase_pu.A = phase_A_current_raw * LSB_TO_PU;
|
||||
Motor1.Iphase_pu.B = phase_B_current_raw * LSB_TO_PU;
|
||||
|
@ -35,8 +38,8 @@ void process_currents()
|
|||
Motor1.Iphase_pu.C = -Motor1.Iphase_pu.A - Motor1.Iphase_pu.B;
|
||||
|
||||
/* Motor 2 negative is A instead of B*/
|
||||
phase_A_current_raw = (adc_res[2] - Motor2.Voffset_lsb.A);
|
||||
phase_B_current_raw = (adc_res[3] - Motor2.Voffset_lsb.B)*-1;
|
||||
phase_A_current_raw = (adc1_res[2] + Motor2.Voffset_lsb.A);
|
||||
phase_B_current_raw = (adc1_res[3] + Motor2.Voffset_lsb.B)*-1;
|
||||
// Covert from LSB to PU (A) and filter out small readings
|
||||
Motor2.Iphase_pu.A = phase_A_current_raw * LSB_TO_PU;
|
||||
Motor2.Iphase_pu.B = phase_B_current_raw * LSB_TO_PU;
|
||||
|
|
|
@ -119,8 +119,6 @@ static const uint16_t COMMUTATION_PATTERN[16] = {
|
|||
// ----------------------------------------------------------------------
|
||||
typedef struct
|
||||
{
|
||||
struct pwm_descriptor const *pwm_desc;
|
||||
void *const speedtimer_hw;
|
||||
const uint16_t motor_Poles;
|
||||
const uint16_t motor_polePairs;
|
||||
const uint16_t motor_commutationStates;
|
||||
|
@ -141,8 +139,6 @@ typedef struct
|
|||
|
||||
/* Small Motor - 2214S024BXTR*/
|
||||
const static BLDCMotor_param_t FH_22mm24BXTR = {
|
||||
.pwm_desc = &PWM_0,
|
||||
.speedtimer_hw = TC2,
|
||||
.motor_Poles = 14,
|
||||
.motor_polePairs = 7,
|
||||
.motor_commutationStates = 42, //polePairs * 6
|
||||
|
@ -166,8 +162,6 @@ const static BLDCMotor_param_t FH_22mm24BXTR = {
|
|||
|
||||
/* Big Motor - 3216W012BXTR */
|
||||
const static BLDCMotor_param_t FH_32mm12BXTR = {
|
||||
.pwm_desc = &PWM_1,
|
||||
.speedtimer_hw = TC4,
|
||||
.motor_Poles = 14,
|
||||
.motor_polePairs = 7,
|
||||
.motor_commutationStates = 42, //polePairs * 6
|
||||
|
@ -192,8 +186,6 @@ const static BLDCMotor_param_t FH_32mm12BXTR = {
|
|||
|
||||
/* Big Motor - 3216W024BXTR */
|
||||
const static BLDCMotor_param_t FH_32mm24BXTR = {
|
||||
.pwm_desc = &PWM_1,
|
||||
.speedtimer_hw = TC4,
|
||||
.motor_Poles = 14,
|
||||
.motor_polePairs = 7,
|
||||
.motor_commutationStates = 42, //polePairs * 6
|
||||
|
|
Loading…
Reference in New Issue