fixed master slave spi issue

2_Motor_Slave/Motor_Slave/Motor_Slave/.atmelstart/atmel_start_config.atstart

@@ -1410,11 +1410,11 @@ drivers:
     functionality: System
     api: HAL:HPL:GCLK
     configuration:
-      $input: 12000000
-      $input_id: External Crystal Oscillator 8-48MHz (XOSC1)
-      RESERVED_InputFreq: 12000000
-      RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1)
-      _$freq_output_Generic clock generator 0: 120000000
+      $input: 100000000
+      $input_id: Digital Phase Locked Loop (DPLL1)
+      RESERVED_InputFreq: 100000000
+      RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL1)
+      _$freq_output_Generic clock generator 0: 100000000
       _$freq_output_Generic clock generator 1: 2000000
       _$freq_output_Generic clock generator 10: 12000000
       _$freq_output_Generic clock generator 11: 12000000
@@ -1556,11 +1556,11 @@ drivers:
     functionality: System
     api: HAL:HPL:MCLK
     configuration:
-      $input: 120000000
+      $input: 100000000
       $input_id: Generic clock generator 0
-      RESERVED_InputFreq: 120000000
+      RESERVED_InputFreq: 100000000
       RESERVED_InputFreq_id: Generic clock generator 0
-      _$freq_output_CPU: 120000000
+      _$freq_output_CPU: 100000000
       cpu_clock_source: Generic clock generator 0
       cpu_div: '1'
       enable_cpu_clock: true
@@ -1623,7 +1623,7 @@ drivers:
       RESERVED_InputFreq_id: Generic clock generator 1
       _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
       _$freq_output_Digital Phase Locked Loop (DPLL0): 47985664
-      _$freq_output_Digital Phase Locked Loop (DPLL1): 120000000
+      _$freq_output_Digital Phase Locked Loop (DPLL1): 100000000
       _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000
       _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000
       dfll_arch_bplckc: false
@@ -1674,7 +1674,7 @@ drivers:
       fdpll1_arch_wuf: false
       fdpll1_clock_dcofilter: 0
       fdpll1_clock_div: 0
-      fdpll1_ldr: 59
+      fdpll1_ldr: 49
       fdpll1_ldrfrac: 0
       fdpll1_ref_clock: Generic clock generator 1
       xosc0_arch_cfden: false

2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_oscctrl_config.h

@@ -568,7 +568,7 @@
 // <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
 // <id> fdpll1_ldr
 #ifndef CONF_FDPLL1_LDR
-#define CONF_FDPLL1_LDR 0x3b
+#define CONF_FDPLL1_LDR 0x31
 #endif
 
 // <o> Clock Divider <0x0-0x7FF>

2_Motor_Slave/Motor_Slave/Motor_Slave/Config/peripheral_clk_config.h

@@ -41,7 +41,7 @@
  * \brief ADC0's Clock frequency
  */
 #ifndef CONF_GCLK_ADC0_FREQUENCY
-#define CONF_GCLK_ADC0_FREQUENCY 120000000
+#define CONF_GCLK_ADC0_FREQUENCY 100000000
 #endif
 
 // <y> ADC Clock Source
@@ -81,7 +81,7 @@
  * \brief ADC1's Clock frequency
  */
 #ifndef CONF_GCLK_ADC1_FREQUENCY
-#define CONF_GCLK_ADC1_FREQUENCY 120000000
+#define CONF_GCLK_ADC1_FREQUENCY 100000000
 #endif
 
 // <y> CCL Clock Source
@@ -121,7 +121,7 @@
  * \brief CCL's Clock frequency
  */
 #ifndef CONF_GCLK_CCL_FREQUENCY
-#define CONF_GCLK_CCL_FREQUENCY 120000000
+#define CONF_GCLK_CCL_FREQUENCY 100000000
 #endif
 
 // <y> EIC Clock Source
@@ -161,7 +161,7 @@
  * \brief EIC's Clock frequency
  */
 #ifndef CONF_GCLK_EIC_FREQUENCY
-#define CONF_GCLK_EIC_FREQUENCY 120000000
+#define CONF_GCLK_EIC_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 0 Clock Source
@@ -202,7 +202,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 1 Clock Source
@@ -243,7 +243,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 2 Clock Source
@@ -284,7 +284,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 3 Clock Source
@@ -325,7 +325,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 4 Clock Source
@@ -366,7 +366,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 5 Clock Source
@@ -407,7 +407,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 6 Clock Source
@@ -448,7 +448,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 7 Clock Source
@@ -489,7 +489,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 8 Clock Source
@@ -530,7 +530,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 9 Clock Source
@@ -571,7 +571,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 10 Clock Source
@@ -612,7 +612,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 11 Clock Source
@@ -653,7 +653,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 100000000
 #endif
 
 /**
@@ -661,7 +661,7 @@
  * \brief CPU's Clock frequency
  */
 #ifndef CONF_CPU_FREQUENCY
-#define CONF_CPU_FREQUENCY 120000000
+#define CONF_CPU_FREQUENCY 100000000
 #endif
 
 // <y> Core Clock Source
@@ -733,7 +733,7 @@
  * \brief SERCOM0's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 120000000
+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 100000000
 #endif
 
 /**
@@ -813,7 +813,7 @@
  * \brief SERCOM1's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 120000000
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 100000000
 #endif
 
 /**
@@ -893,7 +893,7 @@
  * \brief SERCOM2's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 120000000
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000
 #endif
 
 /**
@@ -973,7 +973,7 @@
  * \brief SERCOM5's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 120000000
+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 100000000
 #endif
 
 /**
@@ -1021,7 +1021,7 @@
  * \brief TC0's Clock frequency
  */
 #ifndef CONF_GCLK_TC0_FREQUENCY
-#define CONF_GCLK_TC0_FREQUENCY 120000000
+#define CONF_GCLK_TC0_FREQUENCY 100000000
 #endif
 
 // <y> TC Clock Source
@@ -1061,7 +1061,7 @@
  * \brief TC2's Clock frequency
  */
 #ifndef CONF_GCLK_TC2_FREQUENCY
-#define CONF_GCLK_TC2_FREQUENCY 120000000
+#define CONF_GCLK_TC2_FREQUENCY 100000000
 #endif
 
 // <y> TC Clock Source
@@ -1101,7 +1101,7 @@
  * \brief TC4's Clock frequency
  */
 #ifndef CONF_GCLK_TC4_FREQUENCY
-#define CONF_GCLK_TC4_FREQUENCY 120000000
+#define CONF_GCLK_TC4_FREQUENCY 100000000
 #endif
 
 // <y> TCC Clock Source
@@ -1141,7 +1141,7 @@
  * \brief TCC0's Clock frequency
  */
 #ifndef CONF_GCLK_TCC0_FREQUENCY
-#define CONF_GCLK_TCC0_FREQUENCY 120000000
+#define CONF_GCLK_TCC0_FREQUENCY 100000000
 #endif
 
 // <y> TCC Clock Source
@@ -1181,7 +1181,7 @@
  * \brief TCC1's Clock frequency
  */
 #ifndef CONF_GCLK_TCC1_FREQUENCY
-#define CONF_GCLK_TCC1_FREQUENCY 120000000
+#define CONF_GCLK_TCC1_FREQUENCY 100000000
 #endif
 
 // <<< end of configuration section >>>

2_Motor_Slave/Motor_Slave/Motor_Slave/MSIF_slave.h

@@ -160,7 +160,7 @@ static void update_telemetry(void)
 	*M3_Status					= Motor1.motor_state.fault;
 	*M3_Mode					= Motor1.motor_state.currentstate;
 	*M3_Joint_rel_position		= Motor1.motor_status.Num_Steps;
-	//*M3_Joint_abs_position	=  ((int16_t *)&QSPI_tx_buffer[1];
+	*M3_Joint_abs_position		= Motor1.motor_setpoints.desired_position + 1 ;
 	//*M3_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[1]+1);
 	*M3_Motor_current_bus		= convert_to_mA(Motor1.Iphase_pu.Bus);
 	*M3_Motor_currentPhA		= convert_to_mA(Motor1.Iphase_pu.A);
@@ -174,7 +174,7 @@ static void update_telemetry(void)
 	*M4_Status					= Motor2.motor_state.fault;
 	*M4_Mode					= Motor2.motor_state.currentstate;
 	*M4_Joint_rel_position		= Motor2.motor_status.Num_Steps;
-	//*M3_Joint_abs_position	=  ((int16_t *)&QSPI_tx_buffer[1];
+	*M4_Joint_abs_position		= Motor2.motor_setpoints.desired_position + 1 ;
 	//*M3_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[1]+1);
 	*M4_Motor_current_bus		= convert_to_mA( Motor2.Iphase_pu.Bus);
 	*M4_Motor_currentPhA		= convert_to_mA( Motor2.Iphase_pu.A); 

2_Motor_Slave/Motor_Slave/Motor_Slave/Motor_Slave.cproj

@@ -218,12 +218,12 @@
           <AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Uje5LXAS+nQpGryt9t0fYA" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Xe5v62bijwZLOPLD+rPcrA" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="rMTNR+5FXtu+wfT1NbfRRA" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="Vm7v7a4F40Wzv368v+pLEw" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_tc_config.h" IsConfig="true" Hash="T93Kr6C+WDuufZob89oPeg" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" />
-          <AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="6eU7+fZNEY4RDC37iHjvJQ" />
+          <AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="GuMSQybrrAFfKR9u1GzqsQ" />
           <AcmeProjectActionInfo Action="File" Source="config/bno055_config.h" IsConfig="true" Hash="2hRq4Yx9B3nZuMEdrYIG8Q" />
         </AcmeActionInfos>
         <NonsecureFilesInfo />
@@ -419,7 +419,7 @@
   <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
   <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
   <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
-  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
   <armgcc.linker.general.UseNewlibNano>True</armgcc.linker.general.UseNewlibNano>
   <armgcc.linker.libraries.Libraries>
     <ListValues>

2_Motor_Slave/Motor_Slave/Motor_Slave/configuration.h

@@ -174,8 +174,10 @@ void boardToBoardTransferInit(void)
 {
 	hri_sercomspi_set_CTRLB_PLOADEN_bit(SPI_1_MSIF.dev.prvt);
 	
-	SERCOM1->SPI.CTRLC.bit.ICSPACE = 5;
+	//SERCOM1->SPI.CTRLC.bit.ICSPACE = 5;
 	SERCOM1->SPI.CTRLC.bit.DATA32B= true;
+	//SERCOM1->SPI.LENGTH.bit.LENEN = true;
+	//SERCOM1->SPI.LENGTH.bit.LEN = 16;
 	spi_s_sync_enable(&SPI_1_MSIF);
 }
 
@@ -185,12 +187,14 @@ void init_spi_slave_dma_descriptors()
 							(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
 	_dma_set_destination_address(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, &SPI_rx_buffer[0]);
 	_dma_set_data_amount(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, SLAVE_BUFFER_SIZE_LONG);
+	_dma_set_next_descriptor(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, CONF_SERCOM_1_RECEIVE_DMA_CHANNEL);
 	
 	_dma_set_source_address(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, &SPI_tx_buffer[0]);
 	_dma_set_destination_address(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL,
 								(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
 	_dma_set_data_amount(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, SLAVE_BUFFER_SIZE_LONG);
 	
+	
 	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_RECEIVE_DMA_CHANNEL]);
 	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL]);
 	/* callback */
@@ -212,12 +216,12 @@ void spi_s_sync_enable_ss_detect(void *hw, bool state)
 	NVIC_ClearPendingIRQ((IRQn_Type)SERCOM1_1_IRQn);
 	NVIC_EnableIRQ((IRQn_Type)SERCOM1_1_IRQn);
 	if (state) {
-		//hri_sercomspi_set_INTEN_TXC_bit(hw);
+		hri_sercomspi_set_INTEN_TXC_bit(hw);
 		//hri_sercomspi_set_INTEN_SSL_bit(hw);
 		//hri_sercomspi_set_INTEN_SSL_bit(hw);
 		//SERCOM_SPI_INTENSET_SSL
 		} else {
-		//hri_sercomspi_clear_INTEN_TXC_bit(hw);
+		hri_sercomspi_clear_INTEN_TXC_bit(hw);
 		//hri_sercomspi_clear_INTEN_SSL_bit(hw);
 	}
 }

2_Motor_Slave/Motor_Slave/Motor_Slave/interrupts.h

@@ -1,54 +1,54 @@
-/*
- * interrupts.h
- *
- * Created: 02/08/2021 21:54:14
- *  Author: Nick-XMG
- */ 
-
-
-#ifndef INTERRUPTS_H_
-#define INTERRUPTS_H_
-
-
-
-// ----------------------------------------------------------------------
-// 	ADC Callback for Motor Phase Current Measurement.
-// Phase A & B Sampled and converted from LSB to Process Unit PU(Amps)
-// ----------------------------------------------------------------------
-static void pwm_cb(const struct pwm_descriptor *const descr)
-{
-	
-}
-
-void adc_sram_dma_callback(struct _dma_resource *adc_dma_res)
-{
-	Motor1.timerflags.adc_readings_ready_tic = true;
-	Motor2.timerflags.adc_readings_ready_tic = true;
-}
-
-// ----------------------------------------------------------------------
-// 	EtherCAT Cycle Timer - 1kHz
-// ----------------------------------------------------------------------
-void TC2_Handler(void)
-{
-	if (TC2->COUNT32.INTFLAG.bit.OVF == 0x01) {
-		TC2->COUNT32.INTFLAG.bit.OVF = 0x01;
-		Motor1.motor_status.calc_rpm = 0;
-	}
-}
-
-// ----------------------------------------------------------------------
-//
-// ----------------------------------------------------------------------
-void TC4_Handler(void)
-{
-	if (TC4->COUNT32.INTFLAG.bit.OVF == 0x01) {
-		TC4->COUNT32.INTFLAG.bit.OVF = 0x01;
-		Motor2.motor_status.calc_rpm = 0;	
-	}
-}
-
-
+/*
+ * interrupts.h
+ *
+ * Created: 02/08/2021 21:54:14
+ *  Author: Nick-XMG
+ */ 
+
+
+#ifndef INTERRUPTS_H_
+#define INTERRUPTS_H_
+
+#include "hpl_dma.h"
+
+// ----------------------------------------------------------------------
+// 	ADC Callback for Motor Phase Current Measurement.
+// Phase A & B Sampled and converted from LSB to Process Unit PU(Amps)
+// ----------------------------------------------------------------------
+static void pwm_cb(const struct pwm_descriptor *const descr)
+{
+	
+}
+
+void adc_sram_dma_callback(struct _dma_resource *adc_dma_res)
+{
+	Motor1.timerflags.adc_readings_ready_tic = true;
+	Motor2.timerflags.adc_readings_ready_tic = true;
+}
+
+// ----------------------------------------------------------------------
+// 	EtherCAT Cycle Timer - 1kHz
+// ----------------------------------------------------------------------
+void TC2_Handler(void)
+{
+	if (TC2->COUNT32.INTFLAG.bit.OVF == 0x01) {
+		TC2->COUNT32.INTFLAG.bit.OVF = 0x01;
+		Motor1.motor_status.calc_rpm = 0;
+	}
+}
+
+// ----------------------------------------------------------------------
+//
+// ----------------------------------------------------------------------
+void TC4_Handler(void)
+{
+	if (TC4->COUNT32.INTFLAG.bit.OVF == 0x01) {
+		TC4->COUNT32.INTFLAG.bit.OVF = 0x01;
+		Motor2.motor_status.calc_rpm = 0;	
+	}
+}
+
+
 static void M1_RESET_BAR(void)
 {
 	volatile int x = 0;
@@ -59,20 +59,21 @@ static void M2_RESET_BAR(void)
 	volatile int x = 0;
 }
 
-// ----------------------------------------------------------------------
-// 	Master/Slave IF Callback
-// ----------------------------------------------------------------------
-static void	b2bTransferComplete_cb(struct _dma_resource *resource)
-{
-			
-	DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
-	DMAC->Channel[3].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
-	volatile int x = 0;
-	//PORT->Group[GPIO_PORTB].OUTCLR.reg = (1<<Slave_1->SS_pin);
-	//gpio_set_pin_level(SPI1_CS, true);
+// ----------------------------------------------------------------------
+// 	Master/Slave IF Callback
+// ----------------------------------------------------------------------
+static void	b2bTransferComplete_cb(struct _dma_resource *resource)
+{
+	//_dma_enable_transaction(0, false);
+	//_dma_enable_transaction(3, false);	
+			
+	DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC->Channel[3].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	//volatile int x = 0;
+	//PORT->Group[GPIO_PORTB].OUTCLR.reg = (1<<Slave_1->SS_pin);
 	//gpio_set_pin_level(SPI1_CS, true);
-
-
-
-
+}
+
+
+
 

2_Motor_Slave/Motor_Slave/Motor_Slave/main.c

@@ -86,7 +86,9 @@ void SERCOM1_1_Handler()
 	//SERCOM1->SPI.INTFLAG.bit.TXC = 0x01;
 	//SPI_tx_buffer[0] += 1;
 	//tx_buffer[31] += 1;
-
+		
+	DMAC->Channel[3].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
 		
 	//_dma_enable_transaction(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, false);
 	//_dma_enable_transaction(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, false);
@@ -107,8 +109,8 @@ void SERCOM1_3_Handler()
 	//tx_buffer[31] += 1;
 	
 	//
-	//DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
-	//DMAC->Channel[1].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC->Channel[3].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
 	//_dma_enable_transaction(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, false);
 	//_dma_enable_transaction(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, false);
 	
@@ -132,14 +134,14 @@ void enable_NVIC_IRQ(void)
 	//NVIC_EnableIRQ(TC4_IRQn);	 // TC4: M2_Speed_Timer
 	NVIC_EnableIRQ(DMAC_0_IRQn);
 	NVIC_EnableIRQ(DMAC_1_IRQn);
-	NVIC_SetPriority(DMAC_0_IRQn, 2);
-	NVIC_SetPriority(ADC1_0_IRQn, 3);
+//	NVIC_SetPriority(DMAC_0_IRQn, 2);
+	//NVIC_SetPriority(ADC1_0_IRQn, 3);
 	NVIC_EnableIRQ(TCC0_0_IRQn);
 	NVIC_EnableIRQ(TCC1_0_IRQn);
 	NVIC_EnableIRQ(SERCOM1_3_IRQn);
-	//NVIC_SetPriority(SERCOM1_3_IRQn, 0);
-	//NVIC_EnableIRQ(SERCOM1_1_IRQn);
-	//NVIC_SetPriority(SERCOM1_1_IRQn, 1);
+	NVIC_SetPriority(SERCOM1_3_IRQn, 0);
+	NVIC_EnableIRQ(SERCOM1_1_IRQn);
+	NVIC_SetPriority(SERCOM1_1_IRQn, 0);
 	//NVIC_EnableIRQ(SERCOM1_3_IRQn);
 	//NVIC_EnableIRQ(EIC_5_IRQn);
 }
@@ -214,19 +216,18 @@ int main(void)
 {
 	/* Initializes MCU, drivers and middleware */
 	atmel_start_init();
-	
-	
+	__disable_irq();
 	BldcInitStruct(&Motor1, &FH_22mm24BXTR);
 	BldcInitStruct(&Motor2, &FH_22mm24BXTR_temp);
 	Motor1.readHall = &readHallSensorM1;
 	Motor2.readHall = &readHallSensorM2;
 	read_zero_current_offset_value(&Motor1, &Motor2);
-	__disable_irq();
+	
 	//config_qspi();
 	configure_tcc_pwm();
 	adc_sync_enable_channel(&ADC_1, 6);
 	//ECAT_STATE_MACHINE();
-	//adc_init_dma();
+	adc_init_dma();
 	boardToBoardTransferInit();
 	init_spi_slave_dma_descriptors();