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still havent fixed the adc issue on the slave

This commit is contained in:
Nicolas Trimborn 2021-08-20 10:40:50 +02:00
parent d44c95512a
commit 0bd8db92ac
24 changed files with 117 additions and 1662 deletions
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9
2_Motor_Slave/Motor_Slave/Motor_Slave/.atmelstart/AtmelStart.gpdsc
View File

@ -47,7 +47,6 @@
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/evsys.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/ext_irq.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/pwm.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/quad_spi_dma.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_async.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_sync.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_slave_sync.rst"/>
@ -61,7 +60,6 @@
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_qspi_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_sync.h"/>
@ -81,9 +79,6 @@
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
@ -98,7 +93,6 @@
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_qspi_dma.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
@ -200,7 +194,6 @@
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/qspi/hpl_qspi.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc.c"/>
@ -222,7 +215,6 @@
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_qspi_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tcc_config.h"/>
@ -245,7 +237,6 @@
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/qspi"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/ramecc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/tc"/>

109
2_Motor_Slave/Motor_Slave/Motor_Slave/.atmelstart/atmel_start_config.atstart
View File

@ -587,8 +587,8 @@ drivers:
dmac_evosel_7: Event generation disabled
dmac_evosel_8: Event generation disabled
dmac_evosel_9: Event generation disabled
dmac_lvl_0: Channel priority 0
dmac_lvl_1: Channel priority 0
dmac_lvl_0: Channel priority 1
dmac_lvl_1: Channel priority 1
dmac_lvl_10: Channel priority 0
dmac_lvl_11: Channel priority 0
dmac_lvl_12: Channel priority 0
@ -599,7 +599,7 @@ drivers:
dmac_lvl_17: Channel priority 0
dmac_lvl_18: Channel priority 0
dmac_lvl_19: Channel priority 0
dmac_lvl_2: Channel priority 1
dmac_lvl_2: Channel priority 0
dmac_lvl_20: Channel priority 0
dmac_lvl_21: Channel priority 0
dmac_lvl_22: Channel priority 0
@ -610,7 +610,7 @@ drivers:
dmac_lvl_27: Channel priority 0
dmac_lvl_28: Channel priority 0
dmac_lvl_29: Channel priority 0
dmac_lvl_3: Channel priority 1
dmac_lvl_3: Channel priority 0
dmac_lvl_30: Channel priority 0
dmac_lvl_31: Channel priority 0
dmac_lvl_4: Channel priority 0
@ -628,7 +628,7 @@ drivers:
dmac_lvlpri2: 0
dmac_lvlpri3: 0
dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
dmac_rrlvlen1: Round-robin arbitration scheme for channel with priority 1
dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
dmac_runstdby_0: false
@ -1729,67 +1729,6 @@ drivers:
variant: null
clocks:
domain_group: null
ECAT_QSPI:
user_label: ECAT_QSPI
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::QSPI::driver_config_definition::QSPI.Master::HAL:Driver:QSPI.DMA
functionality: Quad_SPI
api: HAL:Driver:QSPI_DMA
configuration:
qspi_advanced: false
qspi_baud_rate: 6000000
qspi_cpha: Data is changed on the leading edge of SPCK and captured on the following
edge of SPCK.
qspi_cpol: The inactive state value of SPCK is logic level zero.
qspi_dlybs: 0
qspi_dlycs: 0
qspi_dma_rx_channel: 0
qspi_dma_tx_channel: 1
optional_signals:
- identifier: ECAT_QSPI:CS
pad: PB11
mode: Enabled
configuration: null
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::optional_signal_definition::QSPI.CS
name: QSPI/CS
label: CS
- identifier: ECAT_QSPI:DATA/0
pad: PA08
mode: Enabled
configuration: null
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::optional_signal_definition::QSPI.DATA.0
name: QSPI/DATA/0
label: DATA/0
- identifier: ECAT_QSPI:DATA/1
pad: PA09
mode: Enabled
configuration: null
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::optional_signal_definition::QSPI.DATA.1
name: QSPI/DATA/1
label: DATA/1
- identifier: ECAT_QSPI:DATA/2
pad: PA10
mode: Enabled
configuration: null
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::optional_signal_definition::QSPI.DATA.2
name: QSPI/DATA/2
label: DATA/2
- identifier: ECAT_QSPI:DATA/3
pad: PA11
mode: Enabled
configuration: null
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::optional_signal_definition::QSPI.DATA.3
name: QSPI/DATA/3
label: DATA/3
- identifier: ECAT_QSPI:SCK
pad: PB10
mode: Enabled
configuration: null
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::optional_signal_definition::QSPI.SCK
name: QSPI/SCK
label: SCK
variant: null
clocks:
domain_group: null
RAMECC:
user_label: RAMECC
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC
@ -1818,7 +1757,7 @@ drivers:
spi_slave_arch_ibon: In data stream
spi_slave_arch_ploaden: true
spi_slave_arch_runstdby: false
spi_slave_arch_ssde: false
spi_slave_arch_ssde: true
spi_slave_character_size: 8 bits
spi_slave_rx_enable: true
optional_signals: []
@ -2383,42 +2322,6 @@ pads:
mode: Digital input
user_label: ECAT_SYNC
configuration: null
ECAT_QSPI_MOSI:
name: PA08
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::pad::PA08
mode: Advanced
user_label: ECAT_QSPI_MOSI
configuration: null
ECAT_QSPI_MISO:
name: PA09
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::pad::PA09
mode: Advanced
user_label: ECAT_QSPI_MISO
configuration: null
ECAT_QSPI_DATA2:
name: PA10
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::pad::PA10
mode: Advanced
user_label: ECAT_QSPI_DATA2
configuration: null
ECAT_QSPI_DATA3:
name: PA11
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::pad::PA11
mode: Advanced
user_label: ECAT_QSPI_DATA3
configuration: null
ECAT_QSPI_SCK:
name: PB10
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::pad::PB10
mode: Digital input
user_label: ECAT_QSPI_SCK
configuration: null
ECAT_QSPI_CS:
name: PB11
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::pad::PB11
mode: Digital input
user_label: ECAT_QSPI_CS
configuration: null
M1_PWMA:
name: PB12
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::pad::PB12

10
2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_dmac_config.h
View File

@ -45,7 +45,7 @@
// <i> Defines Level 1 Arbitration for DMA channels
// <id> dmac_rrlvlen1
#ifndef CONF_DMAC_RRLVLEN1
#define CONF_DMAC_RRLVLEN1 1
#define CONF_DMAC_RRLVLEN1 0
#endif
// <o> Level 1 Channel Priority Number <0x00-0xFF>
@ -225,7 +225,7 @@
// <i> Defines the arbitration level for this channel
// <id> dmac_lvl_0
#ifndef CONF_DMAC_LVL_0
#define CONF_DMAC_LVL_0 0
#define CONF_DMAC_LVL_0 1
#endif
// <q> Channel Event Output
@ -449,7 +449,7 @@
// <i> Defines the arbitration level for this channel
// <id> dmac_lvl_1
#ifndef CONF_DMAC_LVL_1
#define CONF_DMAC_LVL_1 0
#define CONF_DMAC_LVL_1 1
#endif
// <q> Channel Event Output
@ -673,7 +673,7 @@
// <i> Defines the arbitration level for this channel
// <id> dmac_lvl_2
#ifndef CONF_DMAC_LVL_2
#define CONF_DMAC_LVL_2 1
#define CONF_DMAC_LVL_2 0
#endif
// <q> Channel Event Output
@ -897,7 +897,7 @@
// <i> Defines the arbitration level for this channel
// <id> dmac_lvl_3
#ifndef CONF_DMAC_LVL_3
#define CONF_DMAC_LVL_3 1
#define CONF_DMAC_LVL_3 0
#endif
// <q> Channel Event Output

98
2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_qspi_config.h
View File

@ -1,98 +0,0 @@
/* Auto-generated config file hpl_qspi_config.h */
#ifndef HPL_QSPI_CONFIG_H
#define HPL_QSPI_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <h> Basic settings
#ifndef CONF_CONF_QSPI_ENABLE
#define CONF_CONF_QSPI_ENABLE 1
#endif
// <o> Baud rate <1-150000000>
// <i> The SPI data transfer rate. Note: (fqspi_clock / baudrate) < 255
// <id> qspi_baud_rate
#ifndef CONF_QSPI_BAUD
#define CONF_QSPI_BAUD 6000000
#endif
// <o> Clock Polarity
// <0x0=>The inactive state value of SPCK is logic level zero.
// <0x1=>The inactive state value of SPCK is logic level one.
// <i> Determines the inactive state value of the serial clock (SPCK).
// <id> qspi_cpol
#ifndef CONF_QSPI_CPOL
#define CONF_QSPI_CPOL 0x0
#endif
// <o> Clock Phase
// <0x0=>Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
// <0x1=>Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
// <i> Determines which edge of SPCK causes data to change and which edge causes data to be captured.
// <id> qspi_cpha
#ifndef CONF_QSPI_CPHA
#define CONF_QSPI_CPHA 0x0
#endif
//<o> QSPI DMA TX Channel <0-32>
//<i> This defines DMA channel to be used
//<id> qspi_dma_tx_channel
#ifndef CONF_QSPI_DMA_TX_CHANNEL
#define CONF_QSPI_DMA_TX_CHANNEL 1
#endif
//<o> QSPI DMA RX Channel <0-32>
//<i> This defines DMA channel to be used
//<id> qspi_dma_rx_channel
#ifndef CONF_QSPI_DMA_RX_CHANNEL
#define CONF_QSPI_DMA_RX_CHANNEL 0
#endif
// </h>
// <e> Advanced Configuration
// <id> qspi_advanced
#ifndef CONF_QSPI_ADVANCED
#define CONF_QSPI_ADVANCED 0
#endif
// <o> Delay Before QSCK (ns) <0-255000>
// <i> This field defines the delay from QCS falling edge (activation) to the first valid QSCK transition (in ns).
// <id> qspi_dlybs
#ifndef CONF_QSPI_DLY_BS
#define CONF_QSPI_DLY_BS 0
#endif
// <o> Minimum Inactive QCS Delay (ns) <0-8160000>
// <i> This field defines the minimum delay between the deactivation and the activation of QCS (in ns).
// <id> qspi_dlycs
#ifndef CONF_QSPI_DLY_CS
#define CONF_QSPI_DLY_CS 0
#endif
// </e>
/* Calculate baud register value from requested baudrate value */
#ifndef CONF_QSPI_BAUD_RATE
#define CONF_QSPI_BAUD_RATE ((CONF_CPU_FREQUENCY / CONF_QSPI_BAUD) - 1)
#if CONF_QSPI_BAUD > CONF_CPU_FREQUENCY || CONF_QSPI_BAUD_RATE > 255
#warning Invalid baudrate, please check.
#endif
#endif
/* Calculates the value of the CSR DLYCS field given the desired delay (in ns) */
#ifndef CONF_QSPI_DLYCS
#define CONF_QSPI_DLYCS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_CS) / 1000)
#endif
/* Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
#ifndef CONF_QSPI_DLYBS
#define CONF_QSPI_DLYBS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_BS) / 1000)
#endif
// <<< end of configuration section >>>
#endif // HPL_QSPI_CONFIG_H

2
2_Motor_Slave/Motor_Slave/Motor_Slave/Config/hpl_sercom_config.h
View File

@ -80,7 +80,7 @@
// <i> This bit enables wake up when the slave select (_SS) pin transitions from high to low. (SSDE)
// <id> spi_slave_arch_ssde
#ifndef CONF_SERCOM_1_SPI_SSDE
#define CONF_SERCOM_1_SPI_SSDE 0
#define CONF_SERCOM_1_SPI_SSDE 1
#endif
// <q> Slave Detect Preload Enable

33
2_Motor_Slave/Motor_Slave/Motor_Slave/MSIF_slave.h
View File

@ -10,6 +10,7 @@
#define MASTER_SLAVE_IF_H_
#define SLAVE_BUFFER_SIZE 64
static uint8_t SPI_rx_buffer[SLAVE_BUFFER_SIZE] = {0};
static uint8_t SPI_tx_buffer[SLAVE_BUFFER_SIZE] = {0};
@ -60,23 +61,23 @@ static volatile int16_t *Pressure_CH3 = (int16_t *)&SPI_tx_buffer[62]; //2
///* Motor 3*/
static volatile uint8_t *M3_Control_mode = (uint8_t *)&SPI_rx_buffer[0]; //1 byte - 0 of 32
static volatile uint8_t *M3_Control_set = (uint8_t *)&SPI_rx_buffer[1]; //1 byte - 1 of 32
static volatile int16_t *M3_Desired_pos = (int16_t *)&SPI_tx_buffer[2]; //2 byte - 2 of 32
static volatile int16_t *M3_Desired_speed = (int16_t *)&SPI_tx_buffer[4]; //2 byte - 4 of 32
static volatile int16_t *M3_Desired_current = (int16_t *)&SPI_tx_buffer[6]; //2 byte - 6 of 32
static volatile int16_t *M3_Max_pos = (int16_t *)&SPI_tx_buffer[8]; //2 byte - 8 of 32
static volatile int16_t *M3_Max_velocity = (int16_t *)&SPI_tx_buffer[10]; //2 byte - 10 of 32
static volatile int16_t *M3_Max_current = (int16_t *)&SPI_tx_buffer[12]; //2 byte - 12 of 32
static volatile int16_t *M3_Spare = (int16_t *)&SPI_tx_buffer[14]; //2 byte - 14 of 32
static volatile int16_t *M3_Desired_pos = (int16_t *)&SPI_rx_buffer[2]; //2 byte - 2 of 32
static volatile int16_t *M3_Desired_speed = (int16_t *)&SPI_rx_buffer[4]; //2 byte - 4 of 32
static volatile int16_t *M3_Desired_current = (int16_t *)&SPI_rx_buffer[6]; //2 byte - 6 of 32
static volatile int16_t *M3_Max_pos = (int16_t *)&SPI_rx_buffer[8]; //2 byte - 8 of 32
static volatile int16_t *M3_Max_velocity = (int16_t *)&SPI_rx_buffer[10]; //2 byte - 10 of 32
static volatile int16_t *M3_Max_current = (int16_t *)&SPI_rx_buffer[12]; //2 byte - 12 of 32
static volatile int16_t *M3_Spare = (int16_t *)&SPI_rx_buffer[14]; //2 byte - 14 of 32
///* Motor 4*/
static volatile uint8_t *M4_Control_mode = (int16_t *)&SPI_tx_buffer[16]; //1 byte - 16 of 32
static volatile uint8_t *M4_Control_set = (int16_t *)&SPI_tx_buffer[17]; //1 byte - 17 of 32
static volatile int16_t *M4_Desired_pos = (int16_t *)&SPI_tx_buffer[18]; //2 byte - 18 of 32
static volatile int16_t *M4_Desired_speed = (int16_t *)&SPI_tx_buffer[20]; //2 byte - 20 of 32
static volatile int16_t *M4_Desired_current = (int16_t *)&SPI_tx_buffer[22]; //2 byte - 22 of 32
static volatile int16_t *M4_Max_pos = (int16_t *)&SPI_tx_buffer[24]; //2 byte - 24 of 32
static volatile int16_t *M4_Max_velocity = (int16_t *)&SPI_tx_buffer[26]; //2 byte - 26 of 32
static volatile int16_t *M4_Max_current = (int16_t *)&SPI_tx_buffer[28]; //2 byte - 28 of 32
static volatile int16_t *M4_Spare = (int16_t *)&SPI_tx_buffer[30]; //2 byte - 30 of 32
static volatile uint8_t *M4_Control_mode = (int16_t *)&SPI_rx_buffer[16]; //1 byte - 16 of 32
static volatile uint8_t *M4_Control_set = (int16_t *)&SPI_rx_buffer[17]; //1 byte - 17 of 32
static volatile int16_t *M4_Desired_pos = (int16_t *)&SPI_rx_buffer[18]; //2 byte - 18 of 32
static volatile int16_t *M4_Desired_speed = (int16_t *)&SPI_rx_buffer[20]; //2 byte - 20 of 32
static volatile int16_t *M4_Desired_current = (int16_t *)&SPI_rx_buffer[22]; //2 byte - 22 of 32
static volatile int16_t *M4_Max_pos = (int16_t *)&SPI_rx_buffer[24]; //2 byte - 24 of 32
static volatile int16_t *M4_Max_velocity = (int16_t *)&SPI_rx_buffer[26]; //2 byte - 26 of 32
static volatile int16_t *M4_Max_current = (int16_t *)&SPI_rx_buffer[28]; //2 byte - 28 of 32
static volatile int16_t *M4_Spare = (int16_t *)&SPI_rx_buffer[30]; //2 byte - 30 of 32
static void update_telemetry(void)

60
2_Motor_Slave/Motor_Slave/Motor_Slave/Motor_Slave.cproj
View File

@ -60,7 +60,6 @@
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_gpio.h" IsConfig="false" Hash="3mBEQ9Ix28YOArddDes83Q" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_init.h" IsConfig="false" Hash="OrYSVpF3YA5XrOBImWpdSg" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_io.h" IsConfig="false" Hash="XZRSabc39WU/0MFBLYGLvQ" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_qspi_dma.h" IsConfig="false" Hash="Z34LPTgquoHUOOWcEGA5XA" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_sleep.h" IsConfig="false" Hash="KuZDwgrLdU+fuMG82ZFTqg" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_spi_m_async.h" IsConfig="false" Hash="kNWiys4SwzwGn2qCqzFQlA" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_spi_m_sync.h" IsConfig="false" Hash="2oma6hRMCcowUy2wVveqMg" />
@ -80,9 +79,6 @@
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_i2c_s_sync.h" IsConfig="false" Hash="JNLMe72Fd6Uy3vXkh8HGxg" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_init.h" IsConfig="false" Hash="QtMCPnjBzySOYli3ce/dyQ" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_irq.h" IsConfig="false" Hash="n8mGC0gLHfUhVTjLflKVXw" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_qspi.h" IsConfig="false" Hash="3pJJ6N4ADy/bJ+2DogLk4g" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_qspi_dma.h" IsConfig="false" Hash="lk4Jucsw6aNOKkh1omfXow" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_qspi_sync.h" IsConfig="false" Hash="4zf+sgXtmRMPXlmNh5HEAA" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_ramecc.h" IsConfig="false" Hash="jEqIEhx0d2x1jduY0A9CFQ" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_sleep.h" IsConfig="false" Hash="JOXa2/KqNtt950+B1ZJfSQ" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_spi.h" IsConfig="false" Hash="wAxvxvj1p/CvWEoawsWIBw" />
@ -97,7 +93,6 @@
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_gpio.c" IsConfig="false" Hash="wIzN9zQd1b8qd+RDoSkD7Q" />
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_init.c" IsConfig="false" Hash="bJvq8kpNbbOE2nZfChOGTQ" />
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_io.c" IsConfig="false" Hash="FYpavzYSxhFzVrBQtcH2ZA" />
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_qspi_dma.c" IsConfig="false" Hash="O8vNsAeTvY5ze+/jC3wd3g" />
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_sleep.c" IsConfig="false" Hash="3ebghfB3jYLpnqoi3fhq3g" />
<AcmeProjectActionInfo Action="File" Source="hal/utils/include/compiler.h" IsConfig="false" Hash="8BnWsmkWteo58vaF6VHKHA" />
<AcmeProjectActionInfo Action="File" Source="hal/utils/include/err_codes.h" IsConfig="false" Hash="csatJsZ0ym9p7PojjaFNeQ" />
@ -151,11 +146,11 @@
<AcmeProjectActionInfo Action="File" Source="hri/hri_usb_e51.h" IsConfig="false" Hash="x6M7vYgNCS2oECqykr5+yw" />
<AcmeProjectActionInfo Action="File" Source="hri/hri_wdt_e51.h" IsConfig="false" Hash="o9Rg/hyuMzwOCphVc7uG1w" />
<AcmeProjectActionInfo Action="File" Source="main.c" IsConfig="false" Hash="k0AH7j+BrmdFhBPzCCMptA" />
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="9/ohhOV6padL6taf4jQEFA" />
<AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="Vzx/EsAqY1t+JsaenO3kMA" />
<AcmeProjectActionInfo Action="File" Source="atmel_start_pins.h" IsConfig="false" Hash="ByCGTBpkOpAk+zk9txhJSA" />
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="kvd7eb1e9guBnXkzUfLueg" />
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.c" IsConfig="false" Hash="3FGWBVOfzzrDMygdb9HoNA" />
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="Hu+v5td2Bt9AhrhbYtm1iQ" />
<AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="ZxylnjHZ7Ov2Jlrlr3r1RA" />
<AcmeProjectActionInfo Action="File" Source="atmel_start_pins.h" IsConfig="false" Hash="jhbQsyKOzZ+9eewfwdzIxQ" />
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="UdXjxLfbMqByNE44aloMqA" />
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.c" IsConfig="false" Hash="Pjg3RztiNdKibSzIRtrm7A" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_adc_sync.h" IsConfig="false" Hash="ez1X5T9kpYwT+1+5x4Pxqg" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_pwm.h" IsConfig="false" Hash="RXcBZcci/7vXKRJKNIq/Kw" />
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_timer.h" IsConfig="false" Hash="5pZVthtMl40VMvofOld2ng" />
@ -187,7 +182,7 @@
<AcmeProjectActionInfo Action="File" Source="hpl/core/hpl_core_m4.c" IsConfig="false" Hash="VG4QALndju794J3HSKhsEQ" />
<AcmeProjectActionInfo Action="File" Source="hpl/core/hpl_core_port.h" IsConfig="false" Hash="RXrDMMracCeflR1F9jWiGg" />
<AcmeProjectActionInfo Action="File" Source="hpl/core/hpl_init.c" IsConfig="false" Hash="HyXCJRfb4vfXmyMmlE0xcg" />
<AcmeProjectActionInfo Action="File" Source="hpl/dmac/hpl_dmac.c" IsConfig="false" Hash="hfo1VP6av1KthYmILu3PCg" />
<AcmeProjectActionInfo Action="File" Source="hpl/dmac/hpl_dmac.c" IsConfig="false" Hash="RW/GgakK2RoVdDBtrCxYaA" />
<AcmeProjectActionInfo Action="File" Source="hpl/eic/hpl_eic.c" IsConfig="false" Hash="KiF+rS1TM+CpPUqcR0DdYw" />
<AcmeProjectActionInfo Action="File" Source="hpl/evsys/hpl_evsys.c" IsConfig="false" Hash="YFXyIZne7hxDvOF/5YjFTg" />
<AcmeProjectActionInfo Action="File" Source="hpl/gclk/hpl_gclk.c" IsConfig="false" Hash="5XO/19EedZQ0lq6yB8UTWQ" />
@ -198,7 +193,6 @@
<AcmeProjectActionInfo Action="File" Source="hpl/pm/hpl_pm.c" IsConfig="false" Hash="bcht9HqY6EFL6gVGYXeVfQ" />
<AcmeProjectActionInfo Action="File" Source="hpl/pm/hpl_pm_base.h" IsConfig="false" Hash="KOec1StxUZxY/RKBDbMkpg" />
<AcmeProjectActionInfo Action="File" Source="hpl/port/hpl_gpio_base.h" IsConfig="false" Hash="YjSLMahiT5jdYvqMYVQ8zg" />
<AcmeProjectActionInfo Action="File" Source="hpl/qspi/hpl_qspi.c" IsConfig="false" Hash="woXbbCFkSWus6J14PHJlHw" />
<AcmeProjectActionInfo Action="File" Source="hpl/ramecc/hpl_ramecc.c" IsConfig="false" Hash="pMdmwVWBg16VG8HOwA3DPw" />
<AcmeProjectActionInfo Action="File" Source="hpl/sercom/hpl_sercom.c" IsConfig="false" Hash="MLflsL/S4ZuAfydm9ax0cA" />
<AcmeProjectActionInfo Action="File" Source="hpl/tc/hpl_tc.c" IsConfig="false" Hash="CwAdaARrfhpCcFm3bk4PtA" />
@ -212,7 +206,7 @@
<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="XAOTvk5xMalucgzL/ILTWw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="34JhTN5KS3XoBvZxddUQWA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="G918OUWkTWu+b35DeetjBg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="xKw8xm4k4XPALg++/jSPcw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="/3bNiu/UgpvPbmvfRA+w3g" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
@ -220,8 +214,7 @@
<AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Uje5LXAS+nQpGryt9t0fYA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="rMTNR+5FXtu+wfT1NbfRRA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_qspi_config.h" IsConfig="true" Hash="CwZ360eeEYs7T9SYFSvDug" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="ML9xORsroakk/0eCBfOWSA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="numF6I4TztrS530yBeH4SA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_tc_config.h" IsConfig="true" Hash="T93Kr6C+WDuufZob89oPeg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" />
<AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="rqTY1slZEq9V5moV+8Q+hw" />
@ -280,7 +273,6 @@
<Value>../hpl/oscctrl</Value>
<Value>../hpl/pm</Value>
<Value>../hpl/port</Value>
<Value>../hpl/qspi</Value>
<Value>../hpl/ramecc</Value>
<Value>../hpl/sercom</Value>
<Value>../hpl/tc</Value>
@ -330,7 +322,6 @@
<Value>../hpl/oscctrl</Value>
<Value>../hpl/pm</Value>
<Value>../hpl/port</Value>
<Value>../hpl/qspi</Value>
<Value>../hpl/ramecc</Value>
<Value>../hpl/sercom</Value>
<Value>../hpl/tc</Value>
@ -360,7 +351,6 @@
<Value>../hpl/oscctrl</Value>
<Value>../hpl/pm</Value>
<Value>../hpl/port</Value>
<Value>../hpl/qspi</Value>
<Value>../hpl/ramecc</Value>
<Value>../hpl/sercom</Value>
<Value>../hpl/tc</Value>
@ -389,7 +379,6 @@
<armgcc.compiler.directories.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -408,12 +397,12 @@
<Value>../hpl/oscctrl</Value>
<Value>../hpl/pm</Value>
<Value>../hpl/port</Value>
<Value>../hpl/qspi</Value>
<Value>../hpl/ramecc</Value>
<Value>../hpl/sercom</Value>
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.compiler.directories.IncludePaths>
<armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
@ -440,7 +429,6 @@
<armgcc.assembler.general.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -459,19 +447,18 @@
<Value>../hpl/oscctrl</Value>
<Value>../hpl/pm</Value>
<Value>../hpl/port</Value>
<Value>../hpl/qspi</Value>
<Value>../hpl/ramecc</Value>
<Value>../hpl/sercom</Value>
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.assembler.general.IncludePaths>
<armgcc.assembler.debugging.DebugLevel>Default (-g)</armgcc.assembler.debugging.DebugLevel>
<armgcc.preprocessingassembler.general.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -490,12 +477,12 @@
<Value>../hpl/oscctrl</Value>
<Value>../hpl/pm</Value>
<Value>../hpl/port</Value>
<Value>../hpl/qspi</Value>
<Value>../hpl/ramecc</Value>
<Value>../hpl/sercom</Value>
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.preprocessingassembler.general.IncludePaths>
<armgcc.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcc.preprocessingassembler.debugging.DebugLevel>
@ -560,9 +547,6 @@
<Compile Include="Config\hpl_port_config.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="Config\hpl_qspi_config.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="Config\hpl_sercom_config.h">
<SubType>compile</SubType>
</Compile>
@ -632,9 +616,6 @@
<Compile Include="hal\include\hal_pwm.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hal_qspi_dma.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hal_sleep.h">
<SubType>compile</SubType>
</Compile>
@ -707,15 +688,6 @@
<Compile Include="hal\include\hpl_pwm.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hpl_qspi.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hpl_qspi_dma.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hpl_qspi_sync.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hpl_ramecc.h">
<SubType>compile</SubType>
</Compile>
@ -794,9 +766,6 @@
<Compile Include="hal\src\hal_pwm.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_qspi_dma.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_sleep.c">
<SubType>compile</SubType>
</Compile>
@ -908,9 +877,6 @@
<Compile Include="hpl\port\hpl_gpio_base.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\qspi\hpl_qspi.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\ramecc\hpl_ramecc.c">
<SubType>compile</SubType>
</Compile>
@ -1094,7 +1060,6 @@
<Folder Include="hpl\oscctrl\" />
<Folder Include="hpl\pm\" />
<Folder Include="hpl\port\" />
<Folder Include="hpl\qspi\" />
<Folder Include="hpl\ramecc\" />
<Folder Include="hpl\sercom\" />
<Folder Include="hpl\tcc\" />
@ -1123,9 +1088,6 @@
<None Include="hal\documentation\pwm.rst">
<SubType>compile</SubType>
</None>
<None Include="hal\documentation\quad_spi_dma.rst">
<SubType>compile</SubType>
</None>
<None Include="hal\documentation\spi_master_async.rst">
<SubType>compile</SubType>
</None>

6
2_Motor_Slave/Motor_Slave/Motor_Slave/atmel_start_pins.h
View File

@ -35,10 +35,6 @@
#define M1_HALLB GPIO(GPIO_PORTA, 5)
#define M1_HALLC GPIO(GPIO_PORTA, 6)
#define ECAT_SYNC GPIO(GPIO_PORTA, 7)
#define ECAT_QSPI_MOSI GPIO(GPIO_PORTA, 8)
#define ECAT_QSPI_MISO GPIO(GPIO_PORTA, 9)
#define ECAT_QSPI_DATA2 GPIO(GPIO_PORTA, 10)
#define ECAT_QSPI_DATA3 GPIO(GPIO_PORTA, 11)
#define SPI2_MOSI GPIO(GPIO_PORTA, 12)
#define SPI2_SCK GPIO(GPIO_PORTA, 13)
#define SPI2_SS GPIO(GPIO_PORTA, 14)
@ -64,8 +60,6 @@
#define M2_IB GPIO(GPIO_PORTB, 7)
#define half_VREF GPIO(GPIO_PORTB, 8)
#define ALOG_2 GPIO(GPIO_PORTB, 9)
#define ECAT_QSPI_SCK GPIO(GPIO_PORTB, 10)
#define ECAT_QSPI_CS GPIO(GPIO_PORTB, 11)
#define M1_PWMA GPIO(GPIO_PORTB, 12)
#define M1_PWMB GPIO(GPIO_PORTB, 13)
#define M1_PWMC GPIO(GPIO_PORTB, 14)

22
2_Motor_Slave/Motor_Slave/Motor_Slave/configuration.h
View File

@ -16,6 +16,7 @@
#include "bldc.h"
#include "interrupts.h"
#include "MSIF_slave.h"
#include "hpl_dma.h"
// ----------------------------------------------------------------------
// ADC DMA Initialization
@ -38,8 +39,8 @@ struct _dma_resource *adc_dmac_sequence_resource;
// ----------------------------------------------------------------------
/* DMA channel for SPI Slave TX and RX */
#define CONF_SERCOM_1_RECEIVE_DMA_CHANNEL 0
#define CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL 1
#define CONF_SERCOM_1_RECEIVE_DMA_CHANNEL 0U
#define CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL 1U
//static uint8_t tx_buffer[SLAVE_BUFFER_SIZE] = {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, 0xff, 0xff};
@ -155,6 +156,9 @@ inline void adc_sram_dmac_init()
adc_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback;
_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SRAM, DMAC_CHANNEL_ADC_SRAM);
_dma_enable_transaction(DMAC_CHANNEL_ADC_SRAM, false);
//hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[DMAC_CHANNEL_ADC_SRAM], 0x01); //Suspend
}
static void spi_slave_tx_complete_cb(struct _dma_resource *const resource)
@ -175,23 +179,23 @@ void boardToBoardTransferInit(void)
void init_spi_slave_dma_descriptors()
{
_dma_set_source_address(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
_dma_set_destination_address(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, &SPI_rx_buffer[0]);
_dma_set_data_amount(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, SLAVE_BUFFER_SIZE);
_dma_set_source_address(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, &SPI_tx_buffer[0]);
_dma_set_destination_address(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
_dma_set_data_amount(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, SLAVE_BUFFER_SIZE);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_RECEIVE_DMA_CHANNEL]);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL]);
/* callback */
struct _dma_resource *resource_rx, *resource_tx;
_dma_get_channel_resource(&resource_rx, CONF_SERCOM_1_RECEIVE_DMA_CHANNEL);
_dma_get_channel_resource(&resource_tx, CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL);
//struct _dma_resource *resource_rx, *resource_tx;
//_dma_get_channel_resource(&resource_rx, CONF_SERCOM_1_RECEIVE_DMA_CHANNEL);
//_dma_get_channel_resource(&resource_tx, CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL);
//resource_rx->dma_cb.transfer_done = spi_slave_rx_complete_cb;
resource_tx->dma_cb.transfer_done = spi_slave_tx_complete_cb;
//resource_tx->dma_cb.transfer_done = spi_slave_tx_complete_cb;
/* Enable DMA transfer complete interrupt */
//_dma_set_irq_state(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
@ -206,7 +210,7 @@ void spi_s_sync_enable_ss_detect(void *hw, bool state)
NVIC_EnableIRQ((IRQn_Type)SERCOM1_1_IRQn);
if (state) {
hri_sercomspi_set_INTEN_TXC_bit(hw);
hri_sercomspi_set_INTEN_SSL_bit(hw);
//hri_sercomspi_set_INTEN_SSL_bit(hw);
//hri_sercomspi_set_INTEN_SSL_bit(hw);
//SERCOM_SPI_INTENSET_SSL
} else {

228
2_Motor_Slave/Motor_Slave/Motor_Slave/driver_init.c
View File

@ -21,8 +21,6 @@ struct adc_sync_descriptor ADC_0;
struct adc_sync_descriptor ADC_1;
struct qspi_dma_descriptor ECAT_QSPI;
struct spi_s_sync_descriptor SPI_1_MSIF;
struct spi_m_async_descriptor SPI_2;
@ -187,230 +185,6 @@ void EVENT_SYSTEM_0_init(void)
event_system_init();
}
void ECAT_QSPI_PORT_init(void)
{
// Set pin direction to input
gpio_set_pin_direction(ECAT_QSPI_CS, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(ECAT_QSPI_CS,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_QSPI_CS, PINMUX_PB11H_QSPI_CS);
gpio_set_pin_direction(ECAT_QSPI_MOSI,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(ECAT_QSPI_MOSI,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(ECAT_QSPI_MOSI,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_QSPI_MOSI,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA08H_QSPI_DATA0"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
// <GPIO_PIN_FUNCTION_I"> I
// <GPIO_PIN_FUNCTION_J"> J
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA08H_QSPI_DATA0);
gpio_set_pin_direction(ECAT_QSPI_MISO,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(ECAT_QSPI_MISO,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(ECAT_QSPI_MISO,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_QSPI_MISO,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA09H_QSPI_DATA1"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
// <GPIO_PIN_FUNCTION_I"> I
// <GPIO_PIN_FUNCTION_J"> J
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA09H_QSPI_DATA1);
gpio_set_pin_direction(ECAT_QSPI_DATA2,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(ECAT_QSPI_DATA2,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(ECAT_QSPI_DATA2,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_QSPI_DATA2,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA10H_QSPI_DATA2"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
// <GPIO_PIN_FUNCTION_I"> I
// <GPIO_PIN_FUNCTION_J"> J
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA10H_QSPI_DATA2);
gpio_set_pin_direction(ECAT_QSPI_DATA3,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(ECAT_QSPI_DATA3,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(ECAT_QSPI_DATA3,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_QSPI_DATA3,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA11H_QSPI_DATA3"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
// <GPIO_PIN_FUNCTION_I"> I
// <GPIO_PIN_FUNCTION_J"> J
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA11H_QSPI_DATA3);
// Set pin direction to input
gpio_set_pin_direction(ECAT_QSPI_SCK, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(ECAT_QSPI_SCK,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(ECAT_QSPI_SCK, PINMUX_PB10H_QSPI_SCK);
}
void ECAT_QSPI_CLOCK_init(void)
{
hri_mclk_set_AHBMASK_QSPI_bit(MCLK);
hri_mclk_set_AHBMASK_QSPI_2X_bit(MCLK);
hri_mclk_set_APBCMASK_QSPI_bit(MCLK);
}
void ECAT_QSPI_init(void)
{
ECAT_QSPI_CLOCK_init();
qspi_dma_init(&ECAT_QSPI, QSPI);
ECAT_QSPI_PORT_init();
}
void SPI_1_MSIF_PORT_init(void)
{
@ -738,8 +512,6 @@ void system_init(void)
EVENT_SYSTEM_0_init();
ECAT_QSPI_init();
SPI_1_MSIF_init();
SPI_2_init();

8
2_Motor_Slave/Motor_Slave/Motor_Slave/driver_init.h
View File

@ -31,8 +31,6 @@ extern "C" {
#include <hal_evsys.h>
#include <hal_qspi_dma.h>
#include <hal_spi_s_sync.h>
#include <hal_spi_m_async.h>
@ -52,8 +50,6 @@ extern struct adc_sync_descriptor ADC_0;
extern struct adc_sync_descriptor ADC_1;
extern struct qspi_dma_descriptor ECAT_QSPI;
extern struct spi_s_sync_descriptor SPI_1_MSIF;
extern struct spi_m_async_descriptor SPI_2;
@ -76,10 +72,6 @@ void DIGITAL_GLUE_LOGIC_0_PORT_init(void);
void DIGITAL_GLUE_LOGIC_0_CLOCK_init(void);
void DIGITAL_GLUE_LOGIC_0_init(void);
void ECAT_QSPI_PORT_init(void);
void ECAT_QSPI_CLOCK_init(void);
void ECAT_QSPI_init(void);
void SPI_1_MSIF_PORT_init(void);
void SPI_1_MSIF_CLOCK_init(void);
void SPI_1_MSIF_init(void);

30
2_Motor_Slave/Motor_Slave/Motor_Slave/examples/driver_examples.c
View File

@ -70,36 +70,6 @@ void EXTERNAL_IRQ_0_example(void)
ext_irq_register(PIN_PB31, button_on_PB31_pressed);
}
static uint8_t buf[16] = {0x0};
static void xfer_complete_cb_ECAT_QSPI(struct _dma_resource *resource)
{
/* Transfer completed */
}
/**
* Example of using ECAT_QSPI to get N25Q256A status value,
* and check bit 0 which indicate embedded operation is busy or not.
*/
void ECAT_QSPI_example(void)
{
struct _qspi_command cmd = {
.inst_frame.bits.inst_en = 1,
.inst_frame.bits.data_en = 1,
.inst_frame.bits.addr_en = 1,
.inst_frame.bits.dummy_cycles = 8,
.inst_frame.bits.tfr_type = QSPI_READMEM_ACCESS,
.instruction = 0x0B,
.address = 0,
.buf_len = 14,
.rx_buf = buf,
};
qspi_dma_register_callback(&ECAT_QSPI, QSPI_DMA_CB_XFER_DONE, xfer_complete_cb_ECAT_QSPI);
qspi_dma_enable(&ECAT_QSPI);
qspi_dma_serial_run_command(&ECAT_QSPI, &cmd);
}
/**
* Example of using SPI_1_MSIF to write "Hello World" using the IO abstraction.
*/

2
2_Motor_Slave/Motor_Slave/Motor_Slave/examples/driver_examples.h
View File

@ -20,8 +20,6 @@ void DIGITAL_GLUE_LOGIC_0_example(void);
void EXTERNAL_IRQ_0_example(void);
void ECAT_QSPI_example(void);
void SPI_2_example(void);
void TIMER_0_example(void);

46
2_Motor_Slave/Motor_Slave/Motor_Slave/hal/documentation/quad_spi_dma.rst
View File

@ -1,46 +0,0 @@
The Quad SPI DMA Driver
=================================
The Quad SPI Interface (QSPI) is a synchronous serial data link that provides
communication with external devices in master mode.
The QSPI DMA driver uses DMA system to transfer data between QSPI Memory region
and external device. User must configure DMAC system driver accordingly. Callback
function is called when all the data is transferred or transfer error occurred,
if it is registered via qspi_dma_register_callback() function.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Register callback function
* Execute command in Serial Memory Mode
Applications
------------
They are commonly used in an application for using serial flash memory operating
in single-bit SPI, Dual SPI and Quad SPI.
Dependencies
------------
Serial NOR flash with Multiple I/O hardware
Concurrency
-----------
N/A
Limitations
-----------
N.A
Known issues and workarounds
----------------------------
N/A

137
2_Motor_Slave/Motor_Slave/Motor_Slave/hal/include/hal_qspi_dma.h
View File

@ -1,137 +0,0 @@
/**
* \file
*
* \brief Quad SPI dma related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_QSPI_DMA_INCLUDED
#define _HAL_QSPI_DMA_INCLUDED
#include <hpl_qspi_dma.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_quad_spi_dma
*
*@{
*/
/**
* \brief QSPI descriptor structure
*/
struct qspi_dma_descriptor {
/** Pointer to QSPI device instance */
struct _qspi_dma_dev dev;
};
/**
* \brief Initialize QSPI low level driver.
*
* \param[in] qspi Pointer to the QSPI device instance
* \param[in] hw Pointer to the hardware base
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_dma_init(struct qspi_dma_descriptor *qspi, void *hw);
/**
* \brief Deinitialize QSPI low level driver.
*
* \param[in] qspi Pointer to the QSPI device instance
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_dma_deinit(struct qspi_dma_descriptor *qspi);
/**
* \brief Enable QSPI for access without interrupts
*
* \param[in] qspi Pointer to the QSPI device instance.
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_dma_enable(struct qspi_dma_descriptor *qspi);
/**
* \brief Disable QSPI for access without interrupts
*
* Disable QSPI. Deactivate all CS pins if it works as master.
*
* \param[in] qspi Pointer to the QSPI device instance.
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_dma_disable(struct qspi_dma_descriptor *qspi);
/** \brief Execute command in Serial Memory Mode.
*
* \param[in] qspi Pointer to the HAL QSPI instance
* \param[in] cmd Pointer to the command structure
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_dma_serial_run_command(struct qspi_dma_descriptor *qspi, const struct _qspi_command *cmd);
/** \brief Register a function as QSPI transfer completion callback
*
* Register callback function specified by its \c type.
* - QSPI_DMA_CB_XFER_DONE: set the function that will be called on QSPI transfer
* completion including deactivate the CS.
* - QSPI_DMA_CB_ERROR: set the function that will be called on QSPI transfer error.
* Register NULL function to not use the callback.
*
* \param[in] qspi Pointer to the HAL QSPI instance
* \param[in] type Callback type (\ref _qspi_dma_cb_type)
* \param[in] cb Pointer to callback function
*/
void qspi_dma_register_callback(struct qspi_dma_descriptor *qspi, const enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t qspi_dma_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_QSPI_DMA_INCLUDED */

149
2_Motor_Slave/Motor_Slave/Motor_Slave/hal/include/hpl_qspi.h
View File

@ -1,149 +0,0 @@
/**
* \file
*
* \brief Quad SPI related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_QSPI_H_INCLUDED
#define _HPL_QSPI_H_INCLUDED
#include "compiler.h"
/**
* \addtogroup hpl_qspi HPL QSPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Qspi access modes
*/
enum qspi_access {
/* Read access */
QSPI_READ_ACCESS = 0,
/* Read memory access */
QSPI_READMEM_ACCESS,
/* Write access */
QSPI_WRITE_ACCESS,
/* Write memory access */
QSPI_WRITEMEM_ACCESS
};
/**
* \brief QSPI command instruction/address/data width
*/
enum qspi_cmd_width {
/** Instruction: Single-bit, Address: Single-bit, Data: Single-bit */
QSPI_INST1_ADDR1_DATA1,
/** Instruction: Single-bit, Address: Single-bit, Data: Dual-bit */
QSPI_INST1_ADDR1_DATA2,
/** Instruction: Single-bit, Address: Single-bit, Data: Quad-bit */
QSPI_INST1_ADDR1_DATA4,
/** Instruction: Single-bit, Address: Dual-bit, Data: Dual-bit */
QSPI_INST1_ADDR2_DATA2,
/** Instruction: Single-bit, Address: Quad-bit, Data: Quad-bit */
QSPI_INST1_ADDR4_DATA4,
/** Instruction: Dual-bit, Address: Dual-bit, Data: Dual-bit */
QSPI_INST2_ADDR2_DATA2,
/** Instruction: Quad-bit, Address: Quad-bit, Data: Quad-bit */
QSPI_INST4_ADDR4_DATA4
};
/**
* \brief QSPI command option code length in bits
*/
enum qspi_cmd_opt_len {
/** The option code is 1 bit long */
QSPI_OPT_1BIT,
/** The option code is 2 bits long */
QSPI_OPT_2BIT,
/** The option code is 4 bits long */
QSPI_OPT_4BIT,
/** The option code is 8 bits long */
QSPI_OPT_8BIT
};
/**
* \brief Qspi command structure
*/
struct _qspi_command {
union {
struct {
/* Width of QSPI Addr , inst data */
uint32_t width : 3;
/* Reserved */
uint32_t reserved0 : 1;
/* Enable Instruction */
uint32_t inst_en : 1;
/* Enable Address */
uint32_t addr_en : 1;
/* Enable Option */
uint32_t opt_en : 1;
/* Enable Data */
uint32_t data_en : 1;
/* Option Length */
uint32_t opt_len : 2;
/* Address Length */
uint32_t addr_len : 1;
/* Option Length */
uint32_t reserved1 : 1;
/* Transfer type */
uint32_t tfr_type : 2;
/* Continuous read mode */
uint32_t continues_read : 1;
/* Enable Double Data Rate */
uint32_t ddr_enable : 1;
/* Dummy Cycles Length */
uint32_t dummy_cycles : 5;
/* Reserved */
uint32_t reserved3 : 11;
} bits;
uint32_t word;
} inst_frame;
uint8_t instruction;
uint8_t option;
uint32_t address;
size_t buf_len;
const void *tx_buf;
void * rx_buf;
};
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_QSPI_H_INCLUDED */

146
2_Motor_Slave/Motor_Slave/Motor_Slave/hal/include/hpl_qspi_dma.h
View File

@ -1,146 +0,0 @@
/**
* \file
*
* \brief Quad SPI dma related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_QSPI_DMA_H_INCLUDED
#define _HPL_QSPI_DMA_H_INCLUDED
#include <hpl_qspi.h>
#include "hpl_irq.h"
#include "hpl_dma.h"
/**
* \addtogroup hpl_qspi_dma HPL QSPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** The callback types */
enum _qspi_dma_cb_type {
/** Callback type for DMA transfer done */
QSPI_DMA_CB_XFER_DONE,
/** Callback type for DMA errors */
QSPI_DMA_CB_ERROR,
};
/**
* \brief QSPI DMA callback type
*/
typedef void (*_qspi_dma_cb_t)(struct _dma_resource *resource);
/**
* \brief The callbacks offered by QSPI driver
*/
struct _qspi_dma_callbacks {
_qspi_dma_cb_t xfer_done;
_qspi_dma_cb_t error;
};
/**
* QSPI dma driver instance.
*/
struct _qspi_dma_dev {
/** Pointer to private data or hardware base */
void *prvt;
/**
* Pointer to the callback functions so that initialize the driver to
* handle interrupts.
*/
struct _qspi_dma_callbacks cb;
/** DMA resource */
struct _dma_resource *resource;
};
/**
* \brief Initialize QSPI for access without interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the QSPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_dma_init(struct _qspi_dma_dev *dev, void *const hw);
/**
* \brief Deinitialize QSPI
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the QSPI device instance.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_dma_deinit(struct _qspi_dma_dev *dev);
/**
* \brief Enable QSPI for access without interrupts
* \param[in, out] dev Pointer to the QSPI device instance.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_dma_enable(struct _qspi_dma_dev *dev);
/**
* \brief Disable QSPI for access without interrupts
* \param[in, out] dev Pointer to the QSPI device instance.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_dma_disable(struct _qspi_dma_dev *dev);
/**
* \brief Execute command in Serial Memory Mode.
*
* \param[in] dev The pointer to QSPI device instance
* \param[in] cmd The pointer to the command information
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_dma_serial_run_command(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd);
/**
* \brief Register the QSPI device callback
* \param[in] dev Pointer to the SPI device instance.
* \param[in] type The callback type.
* \param[in] cb The callback function to register. NULL to disable callback.
* \return Always 0.
*/
void _qspi_dma_register_callback(struct _qspi_dma_dev *dev, const enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_QSPI_DMA_H_INCLUDED */

105
2_Motor_Slave/Motor_Slave/Motor_Slave/hal/include/hpl_qspi_sync.h
View File

@ -1,105 +0,0 @@
/**
* \file
*
* \brief Quad SPI Sync related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_QSPI_SYNC_H_INCLUDED
#define _HPL_QSPI_SYNC_H_INCLUDED
#include <hpl_qspi.h>
/**
* \addtogroup hpl_qspi HPL QSPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Quad SPI polling driver instance. */
struct _qspi_sync_dev {
/** Pointer to private data or hardware base */
void *prvt;
};
/**
* \brief Initialize QSPI for access without interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the QSPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_sync_init(struct _qspi_sync_dev *dev, void *const hw);
/**
* \brief Deinitialize QSPI
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the QSPI device instance.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_sync_deinit(struct _qspi_sync_dev *dev);
/**
* \brief Enable QSPI for access without interrupts
* \param[in, out] dev Pointer to the QSPI device instance.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_sync_enable(struct _qspi_sync_dev *dev);
/**
* \brief Disable QSPI for access without interrupts
* \param[in, out] dev Pointer to the QSPI device instance.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_sync_disable(struct _qspi_sync_dev *dev);
/**
* \brief Execute command in Serial Memory Mode.
*
* \param[in] dev The pointer to QSPI device instance
* \param[in] cmd The pointer to the command information
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_sync_serial_run_command(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_QSPI_SYNC_H_INCLUDED */

96
2_Motor_Slave/Motor_Slave/Motor_Slave/hal/src/hal_qspi_dma.c
View File

@ -1,96 +0,0 @@
/**
* \file
*
* \brief Quad SPI dma related functionality implementation.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <utils_assert.h>
#include <utils.h>
#include "hal_qspi_dma.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Driver version
*/
#define QSPI_DMA_DRIVER_VERSION 0x00000001u
int32_t qspi_dma_init(struct qspi_dma_descriptor *qspi, void *const hw)
{
ASSERT(qspi && hw);
return _qspi_dma_init(&qspi->dev, hw);
}
int32_t qspi_dma_deinit(struct qspi_dma_descriptor *qspi)
{
ASSERT(qspi);
return _qspi_dma_deinit(&qspi->dev);
}
int32_t qspi_dma_enable(struct qspi_dma_descriptor *qspi)
{
ASSERT(qspi);
return _qspi_dma_enable(&qspi->dev);
}
int32_t qspi_dma_disable(struct qspi_dma_descriptor *qspi)
{
ASSERT(qspi);
return _qspi_dma_disable(&qspi->dev);
}
int32_t qspi_dma_serial_run_command(struct qspi_dma_descriptor *qspi, const struct _qspi_command *cmd)
{
ASSERT(qspi && cmd);
return _qspi_dma_serial_run_command(&qspi->dev, cmd);
}
void qspi_dma_register_callback(struct qspi_dma_descriptor *qspi, const enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb)
{
ASSERT(qspi);
_qspi_dma_register_callback(&qspi->dev, type, cb);
}
uint32_t qspi_dma_get_version(void)
{
return QSPI_DMA_DRIVER_VERSION;
}
#ifdef __cplusplus
}
#endif

3
2_Motor_Slave/Motor_Slave/Motor_Slave/hpl/dmac/hpl_dmac.c
View File

@ -37,6 +37,7 @@
#include <hpl_dmac_config.h>
#include <utils_repeat_macro.h>
#if CONF_DMAC_ENABLE
/* Section containing first descriptors for all DMAC channels */
COMPILER_ALIGNED(16)
DmacDescriptor _descriptor_section[DMAC_CH_NUM];
@ -258,3 +259,5 @@ void DMAC_4_Handler(void)
{
_dmac_handler();
}
#endif /* CONF_DMAC_ENABLE */

331
2_Motor_Slave/Motor_Slave/Motor_Slave/hpl/qspi/hpl_qspi.c
View File

@ -1,331 +0,0 @@
/**
* \file
*
* \brief QSPI Driver
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <utils_assert.h>
#include <hpl_qspi_sync.h>
#include <hpl_qspi_dma.h>
#include <hpl_qspi_config.h>
/**
* \brief Memory copy function.
*
* \param dst Pointer to destination buffer.
* \param src Pointer to source buffer.
* \param count Bytes to be copied.
*/
static void _qspi_memcpy(uint8_t *dst, uint8_t *src, uint32_t count)
{
while (count--) {
*dst++ = *src++;
}
}
/**
* \brief Ends ongoing transfer by releasing CS of QSPI peripheral.
*
* \param qspi Pointer to an Qspi instance.
*/
static inline void _qspi_end_transfer(void *hw)
{
hri_qspi_write_CTRLA_reg(hw, QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER);
}
int32_t _qspi_sync_init(struct _qspi_sync_dev *dev, void *const hw)
{
ASSERT(dev && hw);
dev->prvt = hw;
hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_SWRST);
hri_qspi_write_CTRLB_reg(hw,
QSPI_CTRLB_MODE_MEMORY | QSPI_CTRLB_CSMODE_LASTXFER | QSPI_CTRLB_DATALEN(0)
| QSPI_CTRLB_DLYBCT(0) | QSPI_CTRLB_DLYCS(CONF_QSPI_DLYCS));
hri_qspi_write_BAUD_reg(hw,
CONF_QSPI_CPOL << QSPI_BAUD_CPOL_Pos | CONF_QSPI_CPHA << QSPI_BAUD_CPHA_Pos
| QSPI_BAUD_BAUD(CONF_QSPI_BAUD_RATE) | QSPI_BAUD_DLYBS(CONF_QSPI_DLYBS));
return ERR_NONE;
}
int32_t _qspi_sync_deinit(struct _qspi_sync_dev *dev)
{
hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_SWRST);
return ERR_NONE;
}
int32_t _qspi_sync_enable(struct _qspi_sync_dev *dev)
{
hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_ENABLE);
return ERR_NONE;
}
int32_t _qspi_sync_disable(struct _qspi_sync_dev *dev)
{
hri_qspi_write_CTRLA_reg(dev->prvt, 0);
return ERR_NONE;
}
/**
* \brief Set instruction frame param.
*/
static void _qspi_sync_command_set_ifr(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd)
{
void *hw = dev->prvt;
if (cmd->inst_frame.bits.addr_en) {
hri_qspi_write_INSTRADDR_reg(hw, cmd->address);
}
if (cmd->inst_frame.bits.inst_en) {
hri_qspi_write_INSTRCTRL_INSTR_bf(hw, cmd->instruction);
}
if (cmd->inst_frame.bits.opt_en) {
hri_qspi_write_INSTRCTRL_OPTCODE_bf(hw, cmd->option);
}
hri_qspi_write_INSTRFRAME_reg(hw, cmd->inst_frame.word);
}
/**
* \brief Access QSPI mapping memory via AHB.
*/
static void _qspi_sync_run_transfer(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd)
{
void * hw = dev->prvt;
uint8_t *qspi_mem = (uint8_t *)QSPI_AHB;
if (cmd->inst_frame.bits.addr_en)
qspi_mem += cmd->address;
/* To synchronize system bus accesses */
hri_qspi_read_INSTRFRAME_reg(hw);
ASSERT(cmd->tx_buf || cmd->rx_buf);
if (cmd->tx_buf) {
_qspi_memcpy((uint8_t *)qspi_mem, (uint8_t *)cmd->tx_buf, cmd->buf_len);
} else {
_qspi_memcpy((uint8_t *)cmd->rx_buf, (uint8_t *)qspi_mem, cmd->buf_len);
}
__DSB();
__ISB();
}
int32_t _qspi_sync_serial_run_command(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd)
{
_qspi_sync_command_set_ifr(dev, cmd);
if (cmd->inst_frame.bits.data_en) {
_qspi_sync_run_transfer(dev, cmd);
}
_qspi_end_transfer(dev->prvt);
while (!hri_qspi_get_INTFLAG_INSTREND_bit(dev->prvt))
;
hri_qspi_clear_INTFLAG_INSTREND_bit(dev->prvt);
return ERR_NONE;
}
/**
* \brief Callback for RX
* \param[in, out] dev Pointer to the DMA resource.
*/
static void _qspi_dma_rx_complete(struct _dma_resource *resource)
{
struct _qspi_dma_dev *dev = (struct _qspi_dma_dev *)resource->back;
_qspi_end_transfer(dev->prvt);
if (dev->cb.xfer_done) {
dev->cb.xfer_done(resource);
}
}
/**
* \brief Callback for TX
* \param[in, out] dev Pointer to the DMA resource.
*/
static void _qspi_dma_tx_complete(struct _dma_resource *resource)
{
struct _qspi_dma_dev *dev = (struct _qspi_dma_dev *)resource->back;
_qspi_end_transfer(dev->prvt);
if (dev->cb.xfer_done) {
dev->cb.xfer_done(resource);
}
}
/**
* \brief Callback for ERROR
* \param[in, out] dev Pointer to the DMA resource.
*/
static void _qspi_dma_error_occured(struct _dma_resource *resource)
{
struct _qspi_dma_dev *dev = (struct _qspi_dma_dev *)resource->back;
if (dev->cb.error) {
dev->cb.error(resource);
}
}
int32_t _qspi_dma_init(struct _qspi_dma_dev *dev, void *const hw)
{
ASSERT(dev && hw);
dev->prvt = hw;
hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_SWRST);
hri_qspi_write_CTRLB_reg(hw,
QSPI_CTRLB_MODE_MEMORY | QSPI_CTRLB_CSMODE_LASTXFER | QSPI_CTRLB_DATALEN(0)
| QSPI_CTRLB_DLYBCT(0) | QSPI_CTRLB_DLYCS(CONF_QSPI_DLYCS));
hri_qspi_write_BAUD_reg(hw,
CONF_QSPI_CPOL << QSPI_BAUD_CPOL_Pos | CONF_QSPI_CPHA << QSPI_BAUD_CPHA_Pos
| QSPI_BAUD_BAUD(CONF_QSPI_BAUD_RATE) | QSPI_BAUD_DLYBS(CONF_QSPI_DLYBS));
/* Initialize DMA rx channel */
_dma_get_channel_resource(&dev->resource, CONF_QSPI_DMA_RX_CHANNEL);
dev->resource->back = dev;
dev->resource->dma_cb.transfer_done = _qspi_dma_rx_complete;
dev->resource->dma_cb.error = _qspi_dma_error_occured;
/* Initialize DMA tx channel */
_dma_get_channel_resource(&dev->resource, CONF_QSPI_DMA_TX_CHANNEL);
dev->resource->back = dev;
dev->resource->dma_cb.transfer_done = _qspi_dma_tx_complete;
dev->resource->dma_cb.error = _qspi_dma_error_occured;
return ERR_NONE;
}
int32_t _qspi_dma_deinit(struct _qspi_dma_dev *dev)
{
hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_SWRST);
return ERR_NONE;
}
int32_t _qspi_dma_enable(struct _qspi_dma_dev *dev)
{
hri_qspi_write_CTRLA_reg(dev->prvt, QSPI_CTRLA_ENABLE);
return ERR_NONE;
}
int32_t _qspi_dma_disable(struct _qspi_dma_dev *dev)
{
hri_qspi_write_CTRLA_reg(dev->prvt, 0);
return ERR_NONE;
}
/**
* \brief Set instruction frame param.
*/
static void _qspi_dma_command_set_ifr(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd)
{
void *hw = dev->prvt;
if (cmd->inst_frame.bits.addr_en) {
hri_qspi_write_INSTRADDR_reg(hw, cmd->address);
}
if (cmd->inst_frame.bits.inst_en) {
hri_qspi_write_INSTRCTRL_INSTR_bf(hw, cmd->instruction);
}
if (cmd->inst_frame.bits.opt_en) {
hri_qspi_write_INSTRCTRL_OPTCODE_bf(hw, cmd->option);
}
hri_qspi_write_INSTRFRAME_reg(hw, cmd->inst_frame.word);
}
/**
* \brief Access QSPI mapping memory via AHB.
*/
static void _qspi_dma_run_transfer(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd)
{
void * hw = dev->prvt;
uint8_t *qspi_mem = (uint8_t *)QSPI_AHB;
if (cmd->inst_frame.bits.addr_en) {
qspi_mem += cmd->address;
}
/* To synchronize system bus accesses */
hri_qspi_read_INSTRFRAME_reg(hw);
ASSERT(cmd->tx_buf || cmd->rx_buf);
if (cmd->tx_buf) {
_dma_set_source_address(CONF_QSPI_DMA_TX_CHANNEL, cmd->tx_buf);
_dma_set_destination_address(CONF_QSPI_DMA_TX_CHANNEL, (uint8_t *)qspi_mem);
_dma_set_data_amount(CONF_QSPI_DMA_TX_CHANNEL, cmd->buf_len);
_dma_enable_transaction(CONF_QSPI_DMA_TX_CHANNEL, false);
} else {
_dma_set_source_address(CONF_QSPI_DMA_RX_CHANNEL, (uint8_t *)qspi_mem);
_dma_set_destination_address(CONF_QSPI_DMA_RX_CHANNEL, cmd->rx_buf);
_dma_set_data_amount(CONF_QSPI_DMA_RX_CHANNEL, cmd->buf_len);
_dma_enable_transaction(CONF_QSPI_DMA_RX_CHANNEL, false);
/* first read and then trig DMA */
*(uint8_t *)(cmd->rx_buf) = qspi_mem[0];
}
__DSB();
__ISB();
}
int32_t _qspi_dma_serial_run_command(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd)
{
_qspi_dma_command_set_ifr(dev, cmd);
if (cmd->inst_frame.bits.data_en) {
_qspi_dma_run_transfer(dev, cmd);
}
return ERR_NONE;
}
void _qspi_dma_register_callback(struct _qspi_dma_dev *dev, enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb)
{
switch (type) {
case QSPI_DMA_CB_XFER_DONE:
dev->cb.xfer_done = cb;
_dma_set_irq_state(CONF_QSPI_DMA_TX_CHANNEL, DMA_TRANSFER_COMPLETE_CB, cb != NULL);
_dma_set_irq_state(CONF_QSPI_DMA_RX_CHANNEL, DMA_TRANSFER_COMPLETE_CB, cb != NULL);
break;
case QSPI_DMA_CB_ERROR:
dev->cb.error = cb;
_dma_set_irq_state(CONF_QSPI_DMA_TX_CHANNEL, DMA_TRANSFER_ERROR_CB, cb != NULL);
_dma_set_irq_state(CONF_QSPI_DMA_RX_CHANNEL, DMA_TRANSFER_ERROR_CB, cb != NULL);
break;
default:
break;
}
}

34
2_Motor_Slave/Motor_Slave/Motor_Slave/main.c
View File

@ -11,9 +11,6 @@
#include "interrupts.h"
#include "statemachine.h"
/* DMA channel for SPI Slave TX and RX */
#define CONF_SERCOM_1_RECEIVE_DMA_CHANNEL 0
#define CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL 1
void process_currents()
{
@ -104,8 +101,8 @@ void SERCOM1_3_Handler()
//SERCOM1->SPI.INTFLAG.bit.TXC = 0x01;
//tx_buffer[0] += 1;
//tx_buffer[31] += 1;
_dma_enable_transaction(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, false);
_dma_enable_transaction(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, false);
//_dma_enable_transaction(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, false);
//_dma_enable_transaction(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, false);
//slave_select_high();
//_dma_enable_transaction(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, false);
@ -115,16 +112,21 @@ void SERCOM1_3_Handler()
void enable_NVIC_IRQ(void)
{
ext_irq_register(M1_RST_Bar, M1_RESET_BAR);
ext_irq_register(M2_RST_Bar, M2_RESET_BAR);
NVIC_EnableIRQ(TC2_IRQn); // TC2: M1_Speed_Timer
NVIC_EnableIRQ(TC4_IRQn); // TC4: M2_Speed_Timer
//ext_irq_register(M1_RST_Bar, M1_RESET_BAR);
//ext_irq_register(M2_RST_Bar, M2_RESET_BAR);
//NVIC_EnableIRQ(TC2_IRQn); // TC2: M1_Speed_Timer
//NVIC_EnableIRQ(TC4_IRQn); // TC4: M2_Speed_Timer
NVIC_EnableIRQ(DMAC_0_IRQn);
NVIC_EnableIRQ(TCC1_0_IRQn);
NVIC_EnableIRQ(DMAC_1_IRQn);
NVIC_SetPriority(DMAC_0_IRQn, 2);
NVIC_SetPriority(ADC1_0_IRQn, 3);
NVIC_EnableIRQ(TCC0_0_IRQn);
NVIC_EnableIRQ(TCC1_0_IRQn);
NVIC_EnableIRQ(SERCOM1_1_IRQn);
NVIC_EnableIRQ(SERCOM1_3_IRQn);
//NVIC_EnableIRQ(SERCOM1_1_IRQn);
//NVIC_SetPriority(SERCOM1_1_IRQn, 1);
//NVIC_EnableIRQ(SERCOM1_3_IRQn);
//NVIC_SetPriority(SERCOM1_3_IRQn, 1);
//NVIC_EnableIRQ(SERCOM1_3_IRQn);
//NVIC_EnableIRQ(EIC_5_IRQn);
}
@ -197,17 +199,17 @@ int main(void)
//config_qspi();
configure_tcc_pwm();
adc_sync_enable_channel(&ADC_1, 6);
//ECAT_STATE_MACHINE();
//adc_init_dma();
boardToBoardTransferInit();
init_spi_slave_dma_descriptors();
_dma_enable_transaction(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, false);
_dma_enable_transaction(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, false);
spi_s_sync_enable_ss_detect((SercomSpi *)(SPI_1_MSIF.dev.prvt), true);
//adc_init_dma();
One_ms_timer_init();
custom_logic_enable();
enable_NVIC_IRQ();
_dma_enable_transaction(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, false);
_dma_enable_transaction(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, false);
/* Replace with your application code */
while (1) {

18
Examples/Board_to_Board_Coms/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave/Board_to_Board_Coms_Slave.cproj
View File

@ -30,15 +30,15 @@
<EraseKey />
<AsfFrameworkConfig>
<framework-data>
<options />
<configurations />
<files />
<documentation help="" />
<offline-documentation help="" />
<dependencies>
<content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.42.0" />
</dependencies>
</framework-data>
<options />
<configurations />
<files />
<documentation help="" />
<offline-documentation help="" />
<dependencies>
<content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.42.0" />
</dependencies>
</framework-data>
</AsfFrameworkConfig>
<Compiler>gcc</Compiler>
<atStartFilePath>.atmelstart\atmel_start_config.atstart</atStartFilePath>

97
Twincat/MotorData/MotorData/MotorData.tsproj
View File

@ -1,5 +1,5 @@
<?xml version="1.0"?>
<TcSmProject xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="http://www.beckhoff.com/schemas/2012/07/TcSmProject" TcSmVersion="1.0" TcVersion="3.1.4024.12">
<TcSmProject xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="http://www.beckhoff.com/schemas/2012/07/TcSmProject" TcSmVersion="1.0" TcVersion="3.1.4024.11">
<ImageDatas>
<ImageData Id="1000">424dd8020000000000003600000028000000100000000e0000000100180000000000a2020000120b0000120b000000000000000000001306e31306e3190ce42b1fe62b1fe61306e31f13e5190ce42519e51306e31306e3190ce42f24e7190ce41306e31306e31306e31306e35f56ec645ced645ced4137e91f13e5473de95f57ec3227e71306e3473de95a51ec271be61306e31306e31409ca524cc68e8ad74f48c1615cc82218d03e36bf716bce746fce453dc01307ce3931ba7d78d27671d1150cb21409ca1712801b1d1d1b1d1d1b1d1d1b1d1d120b891b1d1d1b1d1d1b1d1d1b1d1d120b891b1d1d1b1d1d1b1d1d1b1d1d1712801712807f8080d4d5d5d4d5d5383939120b89545656d4d5d5d4d5d5626464130c89292b2bd4d5d5d4d5d56264641915801712804647471b1d1daaaaaad4d5d5130e82383939292b2b717272d4d5d5151183d4d5d57f80801b1d1d7172721e1c81191580464747d4d5d5d4d5d51b1d1d19158a292b2bd4d5d5d4d5d5292b2b1b1b8ad4d5d56264641b1d1d1b1d1d2427821e1d81d4d5d54647476264643839391e208bd4d5d57f8080464747545656242a8bd4d5d59b9c9c292b2baaaaaa2d3683252882464747d4d5d5d4d5d51b1d1d272d85292b2bd4d5d5d4d5d5292b2b2e37861b1d1dd4d5d5d4d5d5464747394484323bb52324812122822426822526824554c0323883292b822a2d83353c84424cbf3238843940842e32834853865d6ebb5262eb3e43e83334e74147e94349e9535feb4d56ea5662eb484dea545deb636fed545aea5a63ec6671ed8ca0f290a5f2748aef6b7bee5d68ec6874ed788aef8397f17684ef7986ef8c9ff2818ff1818ef08e9df18a97f18791f19ba9f3b0c0f691a4f291a2f28390f192a1f29cacf3a3b3f498a6f3a4b3f4aebdf5b0bef59ea8f3a3adf4bbc7f7c4d1f8cad7f8ced9f9b4c4f6b8c8f6acb8f59aa3f3b6c1f6c5d2f8c2cdf8ccd7f9d2ddf9d5e0fad2daf9d5dcf9dfe7fbe2e9fbe5ebfbe8eefb0000</ImageData>
</ImageDatas>
@ -27,6 +27,11 @@
<Name>GVL_motor_data.M1_Mode</Name>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M2_Status</Name>
<Comment><![CDATA[ Motor 2 //]]></Comment>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M1_Joint_rel_position</Name>
<Type>INT</Type>
@ -64,12 +69,12 @@
<Type>INT</Type>
</Var>
<Var>
<Name>GVL_motor_data.M2_Status</Name>
<Comment><![CDATA[ Motor 2 //]]></Comment>
<Name>GVL_motor_data.M2_Mode</Name>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M2_Mode</Name>
<Name>GVL_motor_data.M3_Status</Name>
<Comment><![CDATA[ Motor 3 //]]></Comment>
<Type>BYTE</Type>
</Var>
<Var>
@ -142,12 +147,12 @@
<Type>INT</Type>
</Var>
<Var>
<Name>GVL_motor_data.M3_Status</Name>
<Comment><![CDATA[ Motor 3 //]]></Comment>
<Name>GVL_motor_data.M3_Mode</Name>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M3_Mode</Name>
<Name>GVL_motor_data.M4_Status</Name>
<Comment><![CDATA[ Motor 4//]]></Comment>
<Type>BYTE</Type>
</Var>
<Var>
@ -186,11 +191,6 @@
<Name>GVL_motor_data.M3_Motor_dutyCycle</Name>
<Type>INT</Type>
</Var>
<Var>
<Name>GVL_motor_data.M4_Status</Name>
<Comment><![CDATA[ Motor 4//]]></Comment>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M4_Mode</Name>
<Type>BYTE</Type>
@ -300,28 +300,6 @@ QSPI_rx_buffer
<Comment><![CDATA[* Motor 2*/]]></Comment>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M2_Control_set</Name>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M3_Control_mode</Name>
<Comment><![CDATA[* Motor 3*/]]></Comment>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M3_Control_set</Name>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M4_Control_mode</Name>
<Comment><![CDATA[* Motor 4*/]]></Comment>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M4_Control_set</Name>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M1_Desired_pos</Name>
<Type>INT</Type>
@ -350,6 +328,15 @@ QSPI_rx_buffer
<Name>GVL_motor_data.M1_Desired_dc</Name>
<Type>INT</Type>
</Var>
<Var>
<Name>GVL_motor_data.M2_Control_set</Name>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M3_Control_mode</Name>
<Comment><![CDATA[* Motor 3*/]]></Comment>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M2_Desired_pos</Name>
<Type>INT</Type>
@ -378,6 +365,15 @@ QSPI_rx_buffer
<Name>GVL_motor_data.M2_Desired_dc</Name>
<Type>INT</Type>
</Var>
<Var>
<Name>GVL_motor_data.M3_Control_set</Name>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M4_Control_mode</Name>
<Comment><![CDATA[* Motor 4*/]]></Comment>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M3_Desired_pos</Name>
<Type>INT</Type>
@ -406,6 +402,10 @@ QSPI_rx_buffer
<Name>GVL_motor_data.M3_Desired_dc</Name>
<Type>INT</Type>
</Var>
<Var>
<Name>GVL_motor_data.M4_Control_set</Name>
<Type>BYTE</Type>
</Var>
<Var>
<Name>GVL_motor_data.M4_Desired_pos</Name>
<Type>INT</Type>
@ -843,33 +843,4 @@ QSPI_rx_buffer
</Device>
</Io>
</Project>
<Mappings>
<MappingInfo Identifier="{00000000-2001-0850-0020-500810000403}" Id="#x02030010"/>
<OwnerA Name="TIPC^Motordata_PLC^Motordata_PLC Instance">
<OwnerB Name="TIID^Device 2 (EtherCAT)^Box 1 (LAN9252-2_motor_Master)">
<Link VarA="PlcTask Inputs^GVL_motor_data.M1_Joint_rel_position" VarB="MCU2ECAT^M1^Joint_rel_position"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M1_Mode" VarB="MCU2ECAT^M1^mode"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M1_Motor_HallState" VarB="MCU2ECAT^M1^Motor_hallState"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M1_Motor_currentPhA" VarB="MCU2ECAT^M1^Motor_currentPhA"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M1_Motor_currentPhB" VarB="MCU2ECAT^M1^Motor_currentPhB"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M1_Motor_currentPhC" VarB="MCU2ECAT^M1^Motor_currentPhC"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M1_Motor_current_bus" VarB="MCU2ECAT^M1^Motor_current_bus"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M1_Motor_dutyCycle" VarB="MCU2ECAT^M1^Motor_dutyCycle"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M1_Motor_speed" VarB="MCU2ECAT^M1^Motor_speed"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M1_Status" VarB="MCU2ECAT^M1^status"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M2_Joint_rel_position" VarB="MCU2ECAT^M2^Joint__rel_position"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M2_Mode" VarB="MCU2ECAT^M2^mode"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M2_Motor_HallState" VarB="MCU2ECAT^M2^Motor_hallState"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M2_Motor_currentPhA" VarB="MCU2ECAT^M2^Motor_currentPhA"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M2_Motor_currentPhB" VarB="MCU2ECAT^M2^Motor_currentPhB"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M2_Motor_currentPhC" VarB="MCU2ECAT^M2^Motor_currentPhC"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M2_Motor_current_bus" VarB="MCU2ECAT^M2^Motor_current_bus"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M2_Motor_dutyCycle" VarB="MCU2ECAT^M2^Motor_dutyCycle"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M2_Motor_speed" VarB="MCU2ECAT^M2^Motor_speed"/>
<Link VarA="PlcTask Inputs^GVL_motor_data.M2_Status" VarB="MCU2ECAT^M2^status"/>
<Link VarA="PlcTask Outputs^GVL_motor_data.M1_Desired_pos" VarB="ECAT2MCU^M1^desired_position"/>
<Link VarA="PlcTask Outputs^GVL_motor_data.M2_Desired_pos" VarB="ECAT2MCU^M2^desired_position"/>
</OwnerB>
</OwnerA>
</Mappings>
</TcSmProject>