fixed issue by changing interrupt priorities

This commit is contained in:
Nicolas Trimborn 2021-08-19 21:04:43 +02:00
parent 43a13554cf
commit d44c95512a
4 changed files with 6 additions and 3 deletions

View File

@ -35,7 +35,7 @@ void motor_StateMachine(BLDCMotor_t* const motor)
case MOTOR_IDLE:
//hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw, DISABLE_PATTERN);
motor->motor_state.previousstate = motor->motor_state.currentstate;
motor->motor_state.currentstate = MOTOR_IDLE;
motor->motor_state.currentstate = MOTOR_PVI_CTRL_STATE;
break;
case MOTOR_OPEN_LOOP_STATE:
BLDC_runOpenLoop(motor, *M1_Desired_dc);

View File

@ -77,7 +77,9 @@ void enable_NVIC_IRQ(void)
//NVIC_EnableIRQ(TC2_IRQn); // TC2: M1_Speed_Timer
//NVIC_EnableIRQ(TC4_IRQn); // TC4: M2_Speed_Timer
NVIC_EnableIRQ(DMAC_0_IRQn);
//NVIC_SetPriority(DMAC_0_IRQn, 1);
NVIC_EnableIRQ(DMAC_1_IRQn);
NVIC_SetPriority(DMAC_0_IRQn, 2);
NVIC_SetPriority(ADC1_0_IRQn, 3);
NVIC_EnableIRQ(TCC0_0_IRQn);
NVIC_EnableIRQ(TCC1_0_IRQn);
//NVIC_SetPriority(TCC0_0_IRQn, 3);
@ -184,6 +186,7 @@ int main(void)
PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, false);
_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, false);
volatile int x = 1;
//spi_m_dma_transfer(&SPI_1_MSIF, (uint8_t*)Slave_1.tx_buffer, (uint8_t*)Slave_1.rx_buffer, MASTER_BUFFER_SIZE);
}

View File

@ -1,6 +1,6 @@

Microsoft Visual Studio Solution File, Format Version 12.00
# Visual Studio 15
# TcXaeShell Solution File, Format Version 11.00
VisualStudioVersion = 15.0.28010.2050
MinimumVisualStudioVersion = 10.0.40219.1
Project("{B1E792BE-AA5F-4E3C-8C82-674BF9C0715B}") = "MotorData", "MotorData\MotorData.tsproj", "{627AF960-8AD6-492C-BE55-42F15976A40C}"