commiting examples
This commit is contained in:
Nicolas Trimborn
parent
76cd702edc
commit
312768d2cf
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@ -0,0 +1,727 @@
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<?xml version="1.0" encoding="utf-8"?>
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||||
<EtherCATInfo xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="EtherCATInfo.xsd" Version="1.8">
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<Vendor>
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<Id>#x000004D8</Id>
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<Name>Microchip Technology Inc</Name>
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</Vendor>
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<Descriptions>
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||||
<Groups>
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<Group>
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<Type>LAN9252-2_motor_Master</Type>
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<Name LcId="1033">LAN9252-2_motor_Master</Name>
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<ImageData16x14>424DD8020000000000003600000028000000100000000E0000000100180000000000A2020000120B0000120B000000000000000000001306E31306E3190CE42B1FE62B1FE61306E31F13E5190CE42519E51306E31306E3190CE42F24E7190CE41306E31306E31306E31306E35F56EC645CED645CED4137E91F13E5473DE95F57EC3227E71306E3473DE95A51EC271BE61306E31306E31409CA524CC68E8AD74F48C1615CC82218D03E36BF716BCE746FCE453DC01307CE3931BA7D78D27671D1150CB21409CA1712801B1D1D1B1D1D1B1D1D1B1D1D120B891B1D1D1B1D1D1B1D1D1B1D1D120B891B1D1D1B1D1D1B1D1D1B1D1D1712801712807F8080D4D5D5D4D5D5383939120B89545656D4D5D5D4D5D5626464130C89292B2BD4D5D5D4D5D56264641915801712804647471B1D1DAAAAAAD4D5D5130E82383939292B2B717272D4D5D5151183D4D5D57F80801B1D1D7172721E1C81191580464747D4D5D5D4D5D51B1D1D19158A292B2BD4D5D5D4D5D5292B2B1B1B8AD4D5D56264641B1D1D1B1D1D2427821E1D81D4D5D54647476264643839391E208BD4D5D57F8080464747545656242A8BD4D5D59B9C9C292B2BAAAAAA2D3683252882464747D4D5D5D4D5D51B1D1D272D85292B2BD4D5D5D4D5D5292B2B2E37861B1D1DD4D5D5D4D5D5464747394484323BB52324812122822426822526824554C0323883292B822A2D83353C84424CBF3238843940842E32834853865D6EBB5262EB3E43E83334E74147E94349E9535FEB4D56EA5662EB484DEA545DEB636FED545AEA5A63EC6671ED8CA0F290A5F2748AEF6B7BEE5D68EC6874ED788AEF8397F17684EF7986EF8C9FF2818FF1818EF08E9DF18A97F18791F19BA9F3B0C0F691A4F291A2F28390F192A1F29CACF3A3B3F498A6F3A4B3F4AEBDF5B0BEF59EA8F3A3ADF4BBC7F7C4D1F8CAD7F8CED9F9B4C4F6B8C8F6ACB8F59AA3F3B6C1F6C5D2F8C2CDF8CCD7F9D2DDF9D5E0FAD2DAF9D5DCF9DFE7FBE2E9FBE5EBFBE8EEFB0000</ImageData16x14>
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</Group>
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</Groups>
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<Devices>
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<Device Physics="YY">
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<Type ProductCode="#x00000002" RevisionNo="#x00000004">LAN9252-2_motor_Master</Type>
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<Name LcId="1033"><![CDATA[MSRM 2_motor_Master Ethercat Slave]]></Name>
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<Info>
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<EtherCATController>
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<DpramSize>4096</DpramSize>
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<SmCount>4</SmCount>
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<FmmuCount>3</FmmuCount>
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</EtherCATController>
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||||
<Port>
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<Type>MII</Type>
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<PhysicalPhyAddr>0</PhysicalPhyAddr>
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</Port>
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<Port>
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<Type>MII</Type>
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<PhysicalPhyAddr>1</PhysicalPhyAddr>
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</Port>
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<IdentificationAdo>#x0012</IdentificationAdo>
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</Info>
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<GroupType>LAN9252-2_motor_Master</GroupType>
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<Fmmu>Outputs</Fmmu>
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<Fmmu>Inputs</Fmmu>
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<Sm StartAddress="#x1100" ControlByte="#x04" Enable="1">Outputs</Sm>
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<Sm StartAddress="#x1800" ControlByte="0" Enable="1">Inputs</Sm>
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<RxPdo Fixed="1" Sm="0">
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<Index>#x1a00</Index>
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||||
<Name>ECAT2MCU</Name>
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||||
<Entry>
|
||||
<Index>#x3101</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>8</BitLen>
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||||
<Name>M1__control_mode</Name>
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||||
<DataType>BYTE</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3102</Index>
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||||
<SubIndex>1</SubIndex>
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<BitLen>8</BitLen>
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||||
<Name>M1__control_set</Name>
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<DataType>BYTE</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3103</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M1__desired_position</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x3104</Index>
|
||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
|
||||
<Name>M1__desired_speed</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x3105</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M1__desired__current</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x3106</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M1__Max_Pos</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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<Entry>
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||||
<Index>#x3107</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M1__Max_velocity</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x3108</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M1__Max_current</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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<Entry>
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||||
<Index>#x3109</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>8</BitLen>
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<Name>M2__control_mode</Name>
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||||
<DataType>BYTE</DataType>
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</Entry>
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<Entry>
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||||
<Index>#x310A</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>8</BitLen>
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||||
<Name>M2__control_set</Name>
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||||
<DataType>BYTE</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x310B</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M2__desired_position</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x310C</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M2__desired_speed</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x310D</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M2__desired__current</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x310E</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M2__Max_Pos</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x310F</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M2__Max_velocity</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3110</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M2__Max_current</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3111</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>8</BitLen>
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||||
<Name>M3__control_mode</Name>
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||||
<DataType>BYTE</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3112</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>8</BitLen>
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||||
<Name>M3__control_set</Name>
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||||
<DataType>BYTE</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3113</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M3__desired_position</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3114</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M3__desired_speed</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3115</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M3__desired__current</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3116</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M3__Max_Pos</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x3117</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M3__Max_velocity</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x3118</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
|
||||
<Name>M3__Max_current</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x3119</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>8</BitLen>
|
||||
<Name>M4__control_mode</Name>
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||||
<DataType>BYTE</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x311A</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>8</BitLen>
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||||
<Name>M4__control_set</Name>
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||||
<DataType>BYTE</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x311B</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
|
||||
<Name>M4__desired_position</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x311C</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
|
||||
<Name>M4__desired_speed</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x311D</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
|
||||
<Name>M4__desired__current</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x311E</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M4__Max_Pos</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x311F</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M4__Max_velocity</Name>
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||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3120</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M4__Max_current</Name>
|
||||
<DataType>INT</DataType>
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||||
</Entry>
|
||||
</RxPdo>
|
||||
<TxPdo Fixed="1" Sm="1">
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||||
<Index>#x1600</Index>
|
||||
<Name>MCU2ECAT</Name>
|
||||
<Entry>
|
||||
<Index>#x3001</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>M1__status</Name>
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||||
<DataType>BYTE</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3002</Index>
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||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>M1__mode</Name>
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||||
<DataType>BYTE</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3003</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
|
||||
<Name>M1__Joint_rel_position</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3004</Index>
|
||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
|
||||
<Name>M1__Joint_abs_position</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3005</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M1__Motor_speed</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x3006</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
|
||||
<Name>M1__Motor_current_bus</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3007</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
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||||
<Name>M1__Motor_currentPhA</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3008</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M1__Motor_currentPhB</Name>
|
||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x3009</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M1__Motor_currentPhC</Name>
|
||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x300A</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M1__Motor_hallState</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x300B</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M1__Motor_dutyCycle</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x300C</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>M2__status</Name>
|
||||
<DataType>BYTE</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x300D</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>M2__mode</Name>
|
||||
<DataType>BYTE</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x300E</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M2__Joint__rel_position</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
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||||
<Entry>
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||||
<Index>#x300F</Index>
|
||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M2__Joint_abs_position</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3010</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M2__Motor_speed</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3011</Index>
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||||
<SubIndex>1</SubIndex>
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||||
<BitLen>16</BitLen>
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||||
<Name>M2__Motor_current_bus</Name>
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||||
<DataType>INT</DataType>
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||||
</Entry>
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||||
<Entry>
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||||
<Index>#x3012</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
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||||
<Name>M2__Motor_currentPhA</Name>
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||||
<DataType>INT</DataType>
|
||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x3013</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M2__Motor_currentPhB</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x3014</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M2__Motor_currentPhC</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3015</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M2__Motor_hallState</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
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||||
<Entry>
|
||||
<Index>#x3016</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M2__Motor_dutyCycle</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3017</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>EMG__CH1</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3018</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>EMG__CH2</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3019</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>EMG__CH3</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x301A</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>EMG__CH4</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x301B</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>EMG__CH5</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x301C</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>EMG__CH6</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x301D</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>EMG__CH7</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x301E</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>EMG__CH8</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x301F</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>M3__status</Name>
|
||||
<DataType>BYTE</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3020</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>M3__mode</Name>
|
||||
<DataType>BYTE</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3021</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M3__Joint__rel_position</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3022</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M3__Joint_abs_position</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3023</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M3__Motor_speed</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3024</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M3__Motor_current_bus</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3025</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M3__Motor_currentPhA</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3026</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M3__Motor_currentPhB</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3027</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M3__Motor_currentPhC</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3028</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M3__Motor_hallState</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3029</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M3__Motor_dutyCycle</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x302A</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>M4__status</Name>
|
||||
<DataType>BYTE</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x302B</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>M4__mode</Name>
|
||||
<DataType>BYTE</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x302C</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M4__Joint__rel_position</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x302D</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M4__Joint_abs_position</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x302E</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M4__Motor_speed</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x302F</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M4__Motor_current_bus</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3030</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M4__Motor_currentPhA</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3031</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M4__Motor_currentPhB</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3032</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M4__Motor_currentPhC</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3033</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M4__Motor_hallState</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3034</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>M4__Motor_dutyCycle</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3035</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>IMU__q_x0</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3036</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>IMU__q_y0</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3037</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>IMU__q_z0</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3038</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>IMU__q_w0</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3039</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>FSR__CH1</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x303A</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>FSR__CH2</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x303B</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>FSR__CH3</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x303C</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>FSR__CH4</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x303D</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>FSR__CH5</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x303E</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Pressure__CH1</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x303F</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Pressure__CH2</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3040</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Pressure__CH3</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
</TxPdo>
|
||||
<Eeprom>
|
||||
<ByteSize>2048</ByteSize>
|
||||
<ConfigData>803100CC1000F0FF</ConfigData>
|
||||
</Eeprom>
|
||||
</Device>
|
||||
</Devices>
|
||||
</Descriptions>
|
||||
</EtherCATInfo>
|
||||
|
|
@ -0,0 +1,335 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<EtherCATInfo xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="EtherCATInfo.xsd" Version="1.8">
|
||||
<Vendor>
|
||||
<Id>#x000004D8</Id>
|
||||
<Name>Microchip Technology Inc</Name>
|
||||
</Vendor>
|
||||
<Descriptions>
|
||||
<Groups>
|
||||
<Group>
|
||||
<Type>LAN9252-BLDC</Type>
|
||||
<Name LcId="1033">LAN9252-BLDC</Name>
|
||||
<ImageData16x14>424DD8020000000000003600000028000000100000000E0000000100180000000000A2020000120B0000120B000000000000000000001306E31306E3190CE42B1FE62B1FE61306E31F13E5190CE42519E51306E31306E3190CE42F24E7190CE41306E31306E31306E31306E35F56EC645CED645CED4137E91F13E5473DE95F57EC3227E71306E3473DE95A51EC271BE61306E31306E31409CA524CC68E8AD74F48C1615CC82218D03E36BF716BCE746FCE453DC01307CE3931BA7D78D27671D1150CB21409CA1712801B1D1D1B1D1D1B1D1D1B1D1D120B891B1D1D1B1D1D1B1D1D1B1D1D120B891B1D1D1B1D1D1B1D1D1B1D1D1712801712807F8080D4D5D5D4D5D5383939120B89545656D4D5D5D4D5D5626464130C89292B2BD4D5D5D4D5D56264641915801712804647471B1D1DAAAAAAD4D5D5130E82383939292B2B717272D4D5D5151183D4D5D57F80801B1D1D7172721E1C81191580464747D4D5D5D4D5D51B1D1D19158A292B2BD4D5D5D4D5D5292B2B1B1B8AD4D5D56264641B1D1D1B1D1D2427821E1D81D4D5D54647476264643839391E208BD4D5D57F8080464747545656242A8BD4D5D59B9C9C292B2BAAAAAA2D3683252882464747D4D5D5D4D5D51B1D1D272D85292B2BD4D5D5D4D5D5292B2B2E37861B1D1DD4D5D5D4D5D5464747394484323BB52324812122822426822526824554C0323883292B822A2D83353C84424CBF3238843940842E32834853865D6EBB5262EB3E43E83334E74147E94349E9535FEB4D56EA5662EB484DEA545DEB636FED545AEA5A63EC6671ED8CA0F290A5F2748AEF6B7BEE5D68EC6874ED788AEF8397F17684EF7986EF8C9FF2818FF1818EF08E9DF18A97F18791F19BA9F3B0C0F691A4F291A2F28390F192A1F29CACF3A3B3F498A6F3A4B3F4AEBDF5B0BEF59EA8F3A3ADF4BBC7F7C4D1F8CAD7F8CED9F9B4C4F6B8C8F6ACB8F59AA3F3B6C1F6C5D2F8C2CDF8CCD7F9D2DDF9D5E0FAD2DAF9D5DCF9DFE7FBE2E9FBE5EBFBE8EEFB0000</ImageData16x14>
|
||||
</Group>
|
||||
</Groups>
|
||||
<Devices>
|
||||
<Device Physics="YY">
|
||||
<Type ProductCode="#x00000002" RevisionNo="#x00000003">LAN9252-BLDC</Type>
|
||||
<Name LcId="1033"><![CDATA[MSRM BLDC Ethercat Slave]]></Name>
|
||||
<Info>
|
||||
<EtherCATController>
|
||||
<DpramSize>4096</DpramSize>
|
||||
<SmCount>4</SmCount>
|
||||
<FmmuCount>3</FmmuCount>
|
||||
</EtherCATController>
|
||||
<Port>
|
||||
<Type>MII</Type>
|
||||
<PhysicalPhyAddr>0</PhysicalPhyAddr>
|
||||
</Port>
|
||||
<Port>
|
||||
<Type>MII</Type>
|
||||
<PhysicalPhyAddr>1</PhysicalPhyAddr>
|
||||
</Port>
|
||||
<IdentificationAdo>#x0012</IdentificationAdo>
|
||||
</Info>
|
||||
<GroupType>LAN9252-BLDC</GroupType>
|
||||
<Fmmu>Outputs</Fmmu>
|
||||
<Fmmu>Inputs</Fmmu>
|
||||
<Sm StartAddress="#x1100" ControlByte="#x04" Enable="1">Outputs</Sm>
|
||||
<Sm StartAddress="#x1800" ControlByte="0" Enable="1">Inputs</Sm>
|
||||
<RxPdo Fixed="1" Sm="0">
|
||||
<Index>#x1a00</Index>
|
||||
<Name>ECAT2MCU</Name>
|
||||
<Entry>
|
||||
<Index>#x3101</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>control__mode</Name>
|
||||
<DataType>BYTE</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3102</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>control__set</Name>
|
||||
<DataType>BYTE</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3103</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>desired__position</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3104</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>desired__speed</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3105</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>desired__torque</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3106</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>controlparam__I_kp</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3107</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>controlparam__I_ki</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3108</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>controlparam__V_kp</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3109</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>controlparam__V_kd</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x310A</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>controlparam__P_kp</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x310B</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>controlparam__P_ki</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x310C</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>controlparam__ReductionRatio</Name>
|
||||
<DataType>UINT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x310D</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>max__torque</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x310E</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>max__current</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x310F</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>max__velocity</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3110</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Spare__spare1</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3111</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Spare__spare2</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3112</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Spare__spare3</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3113</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Spare__spare4</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
</RxPdo>
|
||||
<TxPdo Fixed="1" Sm="1">
|
||||
<Index>#x1600</Index>
|
||||
<Name>MCU2ECAT</Name>
|
||||
<Entry>
|
||||
<Index>#x3001</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>status</Name>
|
||||
<DataType>BYTE</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3002</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>mode</Name>
|
||||
<DataType>BYTE</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3003</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Joint__rel_position</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3004</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Joint__rel_revolution</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3005</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Joint__abs_postion</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3006</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Joint__speed</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3007</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Joint__torque</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3008</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Motor__rel_revolution</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3009</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Motor__rel_position</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x300A</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Motor__abs_position</Name>
|
||||
<DataType>UINT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x300B</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Motor__dutyCycle</Name>
|
||||
<DataType>UINT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x300C</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Motor__speed</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x300D</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Motor__torque</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x300E</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Motor__currentPhA</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x300F</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Motor__currentPhB</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3010</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Motor__currentPhC</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3011</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Motor__currentBus</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3012</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>Motor__hallState</Name>
|
||||
<DataType>BYTE</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3013</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>8</BitLen>
|
||||
<Name>Motor__sparebyte</Name>
|
||||
<DataType>BYTE</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3014</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Spare__spare1</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Index>#x3015</Index>
|
||||
<SubIndex>1</SubIndex>
|
||||
<BitLen>16</BitLen>
|
||||
<Name>Spare__spare2</Name>
|
||||
<DataType>INT</DataType>
|
||||
</Entry>
|
||||
</TxPdo>
|
||||
<Eeprom>
|
||||
<ByteSize>2048</ByteSize>
|
||||
<ConfigData>803100CC1000F0FF</ConfigData>
|
||||
</Eeprom>
|
||||
</Device>
|
||||
</Devices>
|
||||
</Descriptions>
|
||||
</EtherCATInfo>
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
<environment>
|
||||
<configurations/>
|
||||
<device-packs>
|
||||
<device-pack device="ATSAME54P20A" name="SAME54_DFP" vendor="Atmel" version="1.1.134"/>
|
||||
</device-packs>
|
||||
</environment>
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
|
||||
<vendor>Atmel</vendor>
|
||||
<name>My Project</name>
|
||||
<description>Project generated by Atmel Start</description>
|
||||
<url>http://start.atmel.com/</url>
|
||||
<releases>
|
||||
<release version="1.0.1">Initial version</release>
|
||||
</releases>
|
||||
<taxonomy>
|
||||
<description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
|
||||
</taxonomy>
|
||||
<generators>
|
||||
<generator id="AtmelStart">
|
||||
<description>Atmel Start</description>
|
||||
<select Dname="ATSAME54P20A" Dvendor="Atmel:3"/>
|
||||
<command>http://start.atmel.com/</command>
|
||||
<files>
|
||||
<file category="generator" name="atmel_start_config.atstart"/>
|
||||
<file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
|
||||
</files>
|
||||
</generator>
|
||||
</generators>
|
||||
<conditions>
|
||||
<condition id="CMSIS Device Startup">
|
||||
<description>Dependency on CMSIS core and Device Startup components</description>
|
||||
<require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
|
||||
<require Cclass="Device" Cgroup="Startup" Cversion="1.1.0"/>
|
||||
</condition>
|
||||
<condition id="ARMCC, GCC, IAR">
|
||||
<require Dname="ATSAME54P20A"/>
|
||||
<accept Tcompiler="ARMCC"/>
|
||||
<accept Tcompiler="GCC"/>
|
||||
<accept Tcompiler="IAR"/>
|
||||
</condition>
|
||||
<condition id="GCC">
|
||||
<require Dname="ATSAME54P20A"/>
|
||||
<accept Tcompiler="GCC"/>
|
||||
</condition>
|
||||
</conditions>
|
||||
<components generator="AtmelStart">
|
||||
<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
|
||||
<description>Atmel Start Framework</description>
|
||||
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
|
||||
<files>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/evsys.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_dma.rst"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_evsys.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_dma.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_cmcc.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_evsys.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_dma.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_cache.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_evsys.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
|
||||
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hpl/doc_lite/tc.rst"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_can_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_cmcc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gmac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hmatrixb_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_i2s_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_icm_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pcc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pdec_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_qspi_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ramecc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sdhc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e54.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_dma.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/cmcc/hpl_cmcc.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m4.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/evsys/hpl_evsys.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_evsys_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/cmcc"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/evsys"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/ramecc"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/tc"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
|
||||
</files>
|
||||
</component>
|
||||
</components>
|
||||
</package>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,54 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
|
||||
*
|
||||
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \acme_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \acme_license_stop
|
||||
*
|
||||
* Project: Ecat_SPI_M_SPI_S
|
||||
* Target: ATSAME54P20A
|
||||
*
|
||||
**/
|
||||
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
#define ATMEL_START
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/* Auto-generated config file hpl_cmcc_config.h */
|
||||
#ifndef HPL_CMCC_CONFIG_H
|
||||
#define HPL_CMCC_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <q> Cache enable
|
||||
//<i> Defines the cache should be enabled or not.
|
||||
// <id> cmcc_enable
|
||||
#ifndef CONF_CMCC_ENABLE
|
||||
#define CONF_CMCC_ENABLE 0x0
|
||||
#endif
|
||||
|
||||
// <o> Cache Size
|
||||
//<i> Defines the cache memory size to be configured.
|
||||
// <0x0=>1 KB
|
||||
// <0x1=>2 KB
|
||||
// <0x2=>4 KB
|
||||
// <id> cache_size
|
||||
#ifndef CONF_CMCC_CACHE_SIZE
|
||||
#define CONF_CMCC_CACHE_SIZE 0x2
|
||||
#endif
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> cmcc_advanced_configuration
|
||||
// <q> Data cache disable
|
||||
//<i> Defines the data cache should be disabled or not.
|
||||
// <id> cmcc_data_cache_disable
|
||||
#ifndef CONF_CMCC_DATA_CACHE_DISABLE
|
||||
#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
|
||||
#endif
|
||||
|
||||
// <q> Instruction cache disable
|
||||
//<i> Defines the Instruction cache should be disabled or not.
|
||||
// <id> cmcc_inst_cache_disable
|
||||
#ifndef CONF_CMCC_INST_CACHE_DISABLE
|
||||
#define CONF_CMCC_INST_CACHE_DISABLE 0x0
|
||||
#endif
|
||||
|
||||
// <q> Clock Gating disable
|
||||
//<i> Defines the clock gating should be disabled or not.
|
||||
// <id> cmcc_clock_gating_disable
|
||||
#ifndef CONF_CMCC_CLK_GATING_DISABLE
|
||||
#define CONF_CMCC_CLK_GATING_DISABLE 0x0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_CMCC_CONFIG_H
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,920 @@
|
|||
/* Auto-generated config file hpl_gclk_config.h */
|
||||
#ifndef HPL_GCLK_CONFIG_H
|
||||
#define HPL_GCLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> Generic clock generator 0 configuration
|
||||
// <i> Indicates whether generic clock 0 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_0
|
||||
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_0_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 0 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 0
|
||||
// <id> gclk_gen_0_oscillator
|
||||
#ifndef CONF_GCLK_GEN_0_SOURCE
|
||||
#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_0_runstdby
|
||||
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_0_div_sel
|
||||
#ifndef CONF_GCLK_GEN_0_DIVSEL
|
||||
#define CONF_GCLK_GEN_0_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_0_oe
|
||||
#ifndef CONF_GCLK_GEN_0_OE
|
||||
#define CONF_GCLK_GEN_0_OE 1
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_0_oov
|
||||
#ifndef CONF_GCLK_GEN_0_OOV
|
||||
#define CONF_GCLK_GEN_0_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_0_idc
|
||||
#ifndef CONF_GCLK_GEN_0_IDC
|
||||
#define CONF_GCLK_GEN_0_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_0_enable
|
||||
#ifndef CONF_GCLK_GEN_0_GENEN
|
||||
#define CONF_GCLK_GEN_0_GENEN 1
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 0 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_0_div
|
||||
#ifndef CONF_GCLK_GEN_0_DIV
|
||||
#define CONF_GCLK_GEN_0_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 1 configuration
|
||||
// <i> Indicates whether generic clock 1 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_1
|
||||
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_1_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 1 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 1
|
||||
// <id> gclk_gen_1_oscillator
|
||||
#ifndef CONF_GCLK_GEN_1_SOURCE
|
||||
#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_1_runstdby
|
||||
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_1_div_sel
|
||||
#ifndef CONF_GCLK_GEN_1_DIVSEL
|
||||
#define CONF_GCLK_GEN_1_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_1_oe
|
||||
#ifndef CONF_GCLK_GEN_1_OE
|
||||
#define CONF_GCLK_GEN_1_OE 1
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_1_oov
|
||||
#ifndef CONF_GCLK_GEN_1_OOV
|
||||
#define CONF_GCLK_GEN_1_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_1_idc
|
||||
#ifndef CONF_GCLK_GEN_1_IDC
|
||||
#define CONF_GCLK_GEN_1_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_1_enable
|
||||
#ifndef CONF_GCLK_GEN_1_GENEN
|
||||
#define CONF_GCLK_GEN_1_GENEN 1
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 1 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_1_div
|
||||
#ifndef CONF_GCLK_GEN_1_DIV
|
||||
#define CONF_GCLK_GEN_1_DIV 24
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 2 configuration
|
||||
// <i> Indicates whether generic clock 2 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_2
|
||||
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_2_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 2 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 2
|
||||
// <id> gclk_gen_2_oscillator
|
||||
#ifndef CONF_GCLK_GEN_2_SOURCE
|
||||
#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSCULP32K
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_2_runstdby
|
||||
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_2_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_2_div_sel
|
||||
#ifndef CONF_GCLK_GEN_2_DIVSEL
|
||||
#define CONF_GCLK_GEN_2_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_2_oe
|
||||
#ifndef CONF_GCLK_GEN_2_OE
|
||||
#define CONF_GCLK_GEN_2_OE 1
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_2_oov
|
||||
#ifndef CONF_GCLK_GEN_2_OOV
|
||||
#define CONF_GCLK_GEN_2_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_2_idc
|
||||
#ifndef CONF_GCLK_GEN_2_IDC
|
||||
#define CONF_GCLK_GEN_2_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_2_enable
|
||||
#ifndef CONF_GCLK_GEN_2_GENEN
|
||||
#define CONF_GCLK_GEN_2_GENEN 1
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 2 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_2_div
|
||||
#ifndef CONF_GCLK_GEN_2_DIV
|
||||
#define CONF_GCLK_GEN_2_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 3 configuration
|
||||
// <i> Indicates whether generic clock 3 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_3
|
||||
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_3_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 3 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 3
|
||||
// <id> gclk_gen_3_oscillator
|
||||
#ifndef CONF_GCLK_GEN_3_SOURCE
|
||||
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_3_runstdby
|
||||
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_3_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_3_div_sel
|
||||
#ifndef CONF_GCLK_GEN_3_DIVSEL
|
||||
#define CONF_GCLK_GEN_3_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_3_oe
|
||||
#ifndef CONF_GCLK_GEN_3_OE
|
||||
#define CONF_GCLK_GEN_3_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_3_oov
|
||||
#ifndef CONF_GCLK_GEN_3_OOV
|
||||
#define CONF_GCLK_GEN_3_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_3_idc
|
||||
#ifndef CONF_GCLK_GEN_3_IDC
|
||||
#define CONF_GCLK_GEN_3_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_3_enable
|
||||
#ifndef CONF_GCLK_GEN_3_GENEN
|
||||
#define CONF_GCLK_GEN_3_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 3 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_3_div
|
||||
#ifndef CONF_GCLK_GEN_3_DIV
|
||||
#define CONF_GCLK_GEN_3_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 4 configuration
|
||||
// <i> Indicates whether generic clock 4 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_4
|
||||
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_4_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 4 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 4
|
||||
// <id> gclk_gen_4_oscillator
|
||||
#ifndef CONF_GCLK_GEN_4_SOURCE
|
||||
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_4_runstdby
|
||||
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_4_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_4_div_sel
|
||||
#ifndef CONF_GCLK_GEN_4_DIVSEL
|
||||
#define CONF_GCLK_GEN_4_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_4_oe
|
||||
#ifndef CONF_GCLK_GEN_4_OE
|
||||
#define CONF_GCLK_GEN_4_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_4_oov
|
||||
#ifndef CONF_GCLK_GEN_4_OOV
|
||||
#define CONF_GCLK_GEN_4_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_4_idc
|
||||
#ifndef CONF_GCLK_GEN_4_IDC
|
||||
#define CONF_GCLK_GEN_4_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_4_enable
|
||||
#ifndef CONF_GCLK_GEN_4_GENEN
|
||||
#define CONF_GCLK_GEN_4_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_4_div
|
||||
#ifndef CONF_GCLK_GEN_4_DIV
|
||||
#define CONF_GCLK_GEN_4_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 5 configuration
|
||||
// <i> Indicates whether generic clock 5 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_5
|
||||
#ifndef CONF_GCLK_GENERATOR_5_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_5_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 5 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 5
|
||||
// <id> gclk_gen_5_oscillator
|
||||
#ifndef CONF_GCLK_GEN_5_SOURCE
|
||||
#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_5_runstdby
|
||||
#ifndef CONF_GCLK_GEN_5_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_5_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_5_div_sel
|
||||
#ifndef CONF_GCLK_GEN_5_DIVSEL
|
||||
#define CONF_GCLK_GEN_5_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_5_oe
|
||||
#ifndef CONF_GCLK_GEN_5_OE
|
||||
#define CONF_GCLK_GEN_5_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_5_oov
|
||||
#ifndef CONF_GCLK_GEN_5_OOV
|
||||
#define CONF_GCLK_GEN_5_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_5_idc
|
||||
#ifndef CONF_GCLK_GEN_5_IDC
|
||||
#define CONF_GCLK_GEN_5_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_5_enable
|
||||
#ifndef CONF_GCLK_GEN_5_GENEN
|
||||
#define CONF_GCLK_GEN_5_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 5 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_5_div
|
||||
#ifndef CONF_GCLK_GEN_5_DIV
|
||||
#define CONF_GCLK_GEN_5_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 6 configuration
|
||||
// <i> Indicates whether generic clock 6 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_6
|
||||
#ifndef CONF_GCLK_GENERATOR_6_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_6_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 6 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 6
|
||||
// <id> gclk_gen_6_oscillator
|
||||
#ifndef CONF_GCLK_GEN_6_SOURCE
|
||||
#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_6_runstdby
|
||||
#ifndef CONF_GCLK_GEN_6_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_6_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_6_div_sel
|
||||
#ifndef CONF_GCLK_GEN_6_DIVSEL
|
||||
#define CONF_GCLK_GEN_6_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_6_oe
|
||||
#ifndef CONF_GCLK_GEN_6_OE
|
||||
#define CONF_GCLK_GEN_6_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_6_oov
|
||||
#ifndef CONF_GCLK_GEN_6_OOV
|
||||
#define CONF_GCLK_GEN_6_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_6_idc
|
||||
#ifndef CONF_GCLK_GEN_6_IDC
|
||||
#define CONF_GCLK_GEN_6_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_6_enable
|
||||
#ifndef CONF_GCLK_GEN_6_GENEN
|
||||
#define CONF_GCLK_GEN_6_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 6 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_6_div
|
||||
#ifndef CONF_GCLK_GEN_6_DIV
|
||||
#define CONF_GCLK_GEN_6_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 7 configuration
|
||||
// <i> Indicates whether generic clock 7 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_7
|
||||
#ifndef CONF_GCLK_GENERATOR_7_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_7_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 7 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 7
|
||||
// <id> gclk_gen_7_oscillator
|
||||
#ifndef CONF_GCLK_GEN_7_SOURCE
|
||||
#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_7_runstdby
|
||||
#ifndef CONF_GCLK_GEN_7_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_7_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_7_div_sel
|
||||
#ifndef CONF_GCLK_GEN_7_DIVSEL
|
||||
#define CONF_GCLK_GEN_7_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_7_oe
|
||||
#ifndef CONF_GCLK_GEN_7_OE
|
||||
#define CONF_GCLK_GEN_7_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_7_oov
|
||||
#ifndef CONF_GCLK_GEN_7_OOV
|
||||
#define CONF_GCLK_GEN_7_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_7_idc
|
||||
#ifndef CONF_GCLK_GEN_7_IDC
|
||||
#define CONF_GCLK_GEN_7_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_7_enable
|
||||
#ifndef CONF_GCLK_GEN_7_GENEN
|
||||
#define CONF_GCLK_GEN_7_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 7 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_7_div
|
||||
#ifndef CONF_GCLK_GEN_7_DIV
|
||||
#define CONF_GCLK_GEN_7_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 8 configuration
|
||||
// <i> Indicates whether generic clock 8 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_8
|
||||
#ifndef CONF_GCLK_GENERATOR_8_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_8_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 8 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 8
|
||||
// <id> gclk_gen_8_oscillator
|
||||
#ifndef CONF_GCLK_GEN_8_SOURCE
|
||||
#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_8_runstdby
|
||||
#ifndef CONF_GCLK_GEN_8_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_8_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_8_div_sel
|
||||
#ifndef CONF_GCLK_GEN_8_DIVSEL
|
||||
#define CONF_GCLK_GEN_8_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_8_oe
|
||||
#ifndef CONF_GCLK_GEN_8_OE
|
||||
#define CONF_GCLK_GEN_8_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_8_oov
|
||||
#ifndef CONF_GCLK_GEN_8_OOV
|
||||
#define CONF_GCLK_GEN_8_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_8_idc
|
||||
#ifndef CONF_GCLK_GEN_8_IDC
|
||||
#define CONF_GCLK_GEN_8_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_8_enable
|
||||
#ifndef CONF_GCLK_GEN_8_GENEN
|
||||
#define CONF_GCLK_GEN_8_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 8 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_8_div
|
||||
#ifndef CONF_GCLK_GEN_8_DIV
|
||||
#define CONF_GCLK_GEN_8_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 9 configuration
|
||||
// <i> Indicates whether generic clock 9 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_9
|
||||
#ifndef CONF_GCLK_GENERATOR_9_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_9_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 9 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 9
|
||||
// <id> gclk_gen_9_oscillator
|
||||
#ifndef CONF_GCLK_GEN_9_SOURCE
|
||||
#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_9_runstdby
|
||||
#ifndef CONF_GCLK_GEN_9_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_9_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_9_div_sel
|
||||
#ifndef CONF_GCLK_GEN_9_DIVSEL
|
||||
#define CONF_GCLK_GEN_9_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_9_oe
|
||||
#ifndef CONF_GCLK_GEN_9_OE
|
||||
#define CONF_GCLK_GEN_9_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_9_oov
|
||||
#ifndef CONF_GCLK_GEN_9_OOV
|
||||
#define CONF_GCLK_GEN_9_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_9_idc
|
||||
#ifndef CONF_GCLK_GEN_9_IDC
|
||||
#define CONF_GCLK_GEN_9_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_9_enable
|
||||
#ifndef CONF_GCLK_GEN_9_GENEN
|
||||
#define CONF_GCLK_GEN_9_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 9 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_9_div
|
||||
#ifndef CONF_GCLK_GEN_9_DIV
|
||||
#define CONF_GCLK_GEN_9_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 10 configuration
|
||||
// <i> Indicates whether generic clock 10 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_10
|
||||
#ifndef CONF_GCLK_GENERATOR_10_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_10_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 10 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 10
|
||||
// <id> gclk_gen_10_oscillator
|
||||
#ifndef CONF_GCLK_GEN_10_SOURCE
|
||||
#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_10_runstdby
|
||||
#ifndef CONF_GCLK_GEN_10_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_10_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_10_div_sel
|
||||
#ifndef CONF_GCLK_GEN_10_DIVSEL
|
||||
#define CONF_GCLK_GEN_10_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_10_oe
|
||||
#ifndef CONF_GCLK_GEN_10_OE
|
||||
#define CONF_GCLK_GEN_10_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_10_oov
|
||||
#ifndef CONF_GCLK_GEN_10_OOV
|
||||
#define CONF_GCLK_GEN_10_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_10_idc
|
||||
#ifndef CONF_GCLK_GEN_10_IDC
|
||||
#define CONF_GCLK_GEN_10_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_10_enable
|
||||
#ifndef CONF_GCLK_GEN_10_GENEN
|
||||
#define CONF_GCLK_GEN_10_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 10 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_10_div
|
||||
#ifndef CONF_GCLK_GEN_10_DIV
|
||||
#define CONF_GCLK_GEN_10_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 11 configuration
|
||||
// <i> Indicates whether generic clock 11 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_11
|
||||
#ifndef CONF_GCLK_GENERATOR_11_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_11_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 11 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 11
|
||||
// <id> gclk_gen_11_oscillator
|
||||
#ifndef CONF_GCLK_GEN_11_SOURCE
|
||||
#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_11_runstdby
|
||||
#ifndef CONF_GCLK_GEN_11_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_11_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_11_div_sel
|
||||
#ifndef CONF_GCLK_GEN_11_DIVSEL
|
||||
#define CONF_GCLK_GEN_11_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_11_oe
|
||||
#ifndef CONF_GCLK_GEN_11_OE
|
||||
#define CONF_GCLK_GEN_11_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_11_oov
|
||||
#ifndef CONF_GCLK_GEN_11_OOV
|
||||
#define CONF_GCLK_GEN_11_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_11_idc
|
||||
#ifndef CONF_GCLK_GEN_11_IDC
|
||||
#define CONF_GCLK_GEN_11_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_11_enable
|
||||
#ifndef CONF_GCLK_GEN_11_GENEN
|
||||
#define CONF_GCLK_GEN_11_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 11 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_11_div
|
||||
#ifndef CONF_GCLK_GEN_11_DIV
|
||||
#define CONF_GCLK_GEN_11_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_GCLK_CONFIG_H
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/* Auto-generated config file hpl_mclk_config.h */
|
||||
#ifndef HPL_MCLK_CONFIG_H
|
||||
#define HPL_MCLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// <e> System Configuration
|
||||
// <i> Indicates whether configuration for system is enabled or not
|
||||
// <id> enable_cpu_clock
|
||||
#ifndef CONF_SYSTEM_CONFIG
|
||||
#define CONF_SYSTEM_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Basic settings
|
||||
// <y> CPU Clock source
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <i> This defines the clock source for the CPU
|
||||
// <id> cpu_clock_source
|
||||
#ifndef CONF_CPU_SRC
|
||||
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> CPU Clock Division Factor
|
||||
// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
|
||||
// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
|
||||
// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
|
||||
// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
|
||||
// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
|
||||
// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
|
||||
// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
|
||||
// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
|
||||
// <i> Prescalar for CPU clock
|
||||
// <id> cpu_div
|
||||
#ifndef CONF_MCLK_CPUDIV
|
||||
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
|
||||
#endif
|
||||
// <y> Low Power Clock Division
|
||||
// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
|
||||
// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
|
||||
// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
|
||||
// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
|
||||
// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
|
||||
// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
|
||||
// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
|
||||
// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
|
||||
// <id> mclk_arch_lpdiv
|
||||
#ifndef CONF_MCLK_LPDIV
|
||||
#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
|
||||
#endif
|
||||
|
||||
// <y> Backup Clock Division
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
|
||||
// <id> mclk_arch_bupdiv
|
||||
#ifndef CONF_MCLK_BUPDIV
|
||||
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
|
||||
#endif
|
||||
// <y> High-Speed Clock Division
|
||||
// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
|
||||
// <id> mclk_arch_hsdiv
|
||||
#ifndef CONF_MCLK_HSDIV
|
||||
#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <h> NVM Settings
|
||||
// <o> NVM Wait States
|
||||
// <i> These bits select the number of wait states for a read operation.
|
||||
// <0=> 0
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
// <10=> 10
|
||||
// <11=> 11
|
||||
// <12=> 12
|
||||
// <13=> 13
|
||||
// <14=> 14
|
||||
// <15=> 15
|
||||
// <id> nvm_wait_states
|
||||
#ifndef CONF_NVM_WAIT_STATE
|
||||
#define CONF_NVM_WAIT_STATE 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_MCLK_CONFIG_H
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
/* Auto-generated config file hpl_osc32kctrl_config.h */
|
||||
#ifndef HPL_OSC32KCTRL_CONFIG_H
|
||||
#define HPL_OSC32KCTRL_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> RTC Source configuration
|
||||
// <id> enable_rtc_source
|
||||
#ifndef CONF_RTCCTRL_CONFIG
|
||||
#define CONF_RTCCTRL_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> RTC source control
|
||||
// <y> RTC Clock Source Selection
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <i> This defines the clock source for RTC
|
||||
// <id> rtc_source_oscillator
|
||||
#ifndef CONF_RTCCTRL_SRC
|
||||
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
|
||||
#endif
|
||||
|
||||
// <q> Use 1 kHz output
|
||||
// <id> rtc_1khz_selection
|
||||
#ifndef CONF_RTCCTRL_1KHZ
|
||||
|
||||
#define CONF_RTCCTRL_1KHZ 0
|
||||
|
||||
#endif
|
||||
|
||||
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
|
||||
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
|
||||
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
|
||||
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
|
||||
#else
|
||||
#error unexpected CONF_RTCCTRL_SRC
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> 32kHz External Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for External 32K Osc is enabled or not
|
||||
// <id> enable_xosc32k
|
||||
#ifndef CONF_XOSC32K_CONFIG
|
||||
#define CONF_XOSC32K_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> 32kHz External Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
|
||||
// <id> xosc32k_arch_enable
|
||||
#ifndef CONF_XOSC32K_ENABLE
|
||||
#define CONF_XOSC32K_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>62592us
|
||||
// <0x1=>125092us
|
||||
// <0x2=>500092us
|
||||
// <0x3=>1000092us
|
||||
// <0x4=>2000092us
|
||||
// <0x5=>4000092us
|
||||
// <0x6=>8000092us
|
||||
// <id> xosc32k_arch_startup
|
||||
#ifndef CONF_XOSC32K_STARTUP
|
||||
#define CONF_XOSC32K_STARTUP 0x0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc32k_arch_ondemand
|
||||
#ifndef CONF_XOSC32K_ONDEMAND
|
||||
#define CONF_XOSC32K_ONDEMAND 1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc32k_arch_runstdby
|
||||
#ifndef CONF_XOSC32K_RUNSTDBY
|
||||
#define CONF_XOSC32K_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> 1kHz Output Enable
|
||||
// <i> Indicates whether 1kHz Output is enabled or not
|
||||
// <id> xosc32k_arch_en1k
|
||||
#ifndef CONF_XOSC32K_EN1K
|
||||
#define CONF_XOSC32K_EN1K 0
|
||||
#endif
|
||||
|
||||
// <q> 32kHz Output Enable
|
||||
// <i> Indicates whether 32kHz Output is enabled or not
|
||||
// <id> xosc32k_arch_en32k
|
||||
#ifndef CONF_XOSC32K_EN32K
|
||||
#define CONF_XOSC32K_EN32K 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc32k_arch_swben
|
||||
#ifndef CONF_XOSC32K_SWBEN
|
||||
#define CONF_XOSC32K_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc32k_arch_cfden
|
||||
#ifndef CONF_XOSC32K_CFDEN
|
||||
#define CONF_XOSC32K_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector Event Out
|
||||
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
|
||||
// <id> xosc32k_arch_cfdeo
|
||||
#ifndef CONF_XOSC32K_CFDEO
|
||||
#define CONF_XOSC32K_CFDEO 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN32/XOUT32 Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc32k_arch_xtalen
|
||||
#ifndef CONF_XOSC32K_XTALEN
|
||||
#define CONF_XOSC32K_XTALEN 1
|
||||
#endif
|
||||
|
||||
// <o> Control Gain Mode
|
||||
// <0x0=>Low Power mode
|
||||
// <0x1=>Standard mode
|
||||
// <0x2=>High Speed mode
|
||||
// <id> xosc32k_arch_cgm
|
||||
#ifndef CONF_XOSC32K_CGM
|
||||
#define CONF_XOSC32K_CGM 0x1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for OSCULP32K is enabled or not
|
||||
// <id> enable_osculp32k
|
||||
#ifndef CONF_OSCULP32K_CONFIG
|
||||
#define CONF_OSCULP32K_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> 32kHz Ultra Low Power Internal Oscillator Control
|
||||
|
||||
// <q> Oscillator Calibration Control
|
||||
// <i> Indicates whether Oscillator Calibration is enabled or not
|
||||
// <id> osculp32k_calib_enable
|
||||
#ifndef CONF_OSCULP32K_CALIB_ENABLE
|
||||
#define CONF_OSCULP32K_CALIB_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Oscillator Calibration <0x0-0x3F>
|
||||
// <id> osculp32k_calib
|
||||
#ifndef CONF_OSCULP32K_CALIB
|
||||
#define CONF_OSCULP32K_CALIB 0x0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_OSC32KCTRL_CONFIG_H
|
||||
|
|
@ -0,0 +1,640 @@
|
|||
/* Auto-generated config file hpl_oscctrl_config.h */
|
||||
#ifndef HPL_OSCCTRL_CONFIG_H
|
||||
#define HPL_OSCCTRL_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> External Multipurpose Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for XOSC0 is enabled or not
|
||||
// <id> enable_xosc0
|
||||
#ifndef CONF_XOSC0_CONFIG
|
||||
#define CONF_XOSC0_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <o> Frequency <8000000-48000000>
|
||||
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
|
||||
// <id> xosc0_frequency
|
||||
#ifndef CONF_XOSC_FREQUENCY
|
||||
#define CONF_XOSC0_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
// <h> External Multipurpose Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
|
||||
// <id> xosc0_arch_enable
|
||||
#ifndef CONF_XOSC0_ENABLE
|
||||
#define CONF_XOSC0_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>31us
|
||||
// <0x1=>61us
|
||||
// <0x2=>122us
|
||||
// <0x3=>244us
|
||||
// <0x4=>488us
|
||||
// <0x5=>977us
|
||||
// <0x6=>1953us
|
||||
// <0x7=>3906us
|
||||
// <0x8=>7813us
|
||||
// <0x9=>15625us
|
||||
// <0xA=>31250us
|
||||
// <0xB=>62500us
|
||||
// <0xC=>125000us
|
||||
// <0xD=>250000us
|
||||
// <0xE=>500000us
|
||||
// <0xF=>1000000us
|
||||
// <id> xosc0_arch_startup
|
||||
#ifndef CONF_XOSC0_STARTUP
|
||||
#define CONF_XOSC0_STARTUP 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc0_arch_swben
|
||||
#ifndef CONF_XOSC0_SWBEN
|
||||
#define CONF_XOSC0_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc0_arch_cfden
|
||||
#ifndef CONF_XOSC0_CFDEN
|
||||
#define CONF_XOSC0_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Automatic Loop Control Enable
|
||||
// <i> Indicates whether Automatic Loop Control is enabled or not
|
||||
// <id> xosc0_arch_enalc
|
||||
#ifndef CONF_XOSC0_ENALC
|
||||
#define CONF_XOSC0_ENALC 0
|
||||
#endif
|
||||
|
||||
// <q> Low Buffer Gain Enable
|
||||
// <i> Indicates whether Low Buffer Gain is enabled or not
|
||||
// <id> xosc0_arch_lowbufgain
|
||||
#ifndef CONF_XOSC0_LOWBUFGAIN
|
||||
#define CONF_XOSC0_LOWBUFGAIN 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc0_arch_ondemand
|
||||
#ifndef CONF_XOSC0_ONDEMAND
|
||||
#define CONF_XOSC0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc0_arch_runstdby
|
||||
#ifndef CONF_XOSC0_RUNSTDBY
|
||||
#define CONF_XOSC0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN/XOUT Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc0_arch_xtalen
|
||||
#ifndef CONF_XOSC0_XTALEN
|
||||
#define CONF_XOSC0_XTALEN 0
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
#if CONF_XOSC0_FREQUENCY >= 32000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x0
|
||||
#define CONF_XOSC0_IMULT 0x7
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 24000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x1
|
||||
#define CONF_XOSC0_IMULT 0x6
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 16000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x2
|
||||
#define CONF_XOSC0_IMULT 0x5
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 8000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x3
|
||||
#define CONF_XOSC0_IMULT 0x4
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#endif
|
||||
|
||||
// <e> External Multipurpose Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for XOSC1 is enabled or not
|
||||
// <id> enable_xosc1
|
||||
#ifndef CONF_XOSC1_CONFIG
|
||||
#define CONF_XOSC1_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <o> Frequency <8000000-48000000>
|
||||
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
|
||||
// <id> xosc1_frequency
|
||||
#ifndef CONF_XOSC_FREQUENCY
|
||||
#define CONF_XOSC1_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
// <h> External Multipurpose Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
|
||||
// <id> xosc1_arch_enable
|
||||
#ifndef CONF_XOSC1_ENABLE
|
||||
#define CONF_XOSC1_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>31us
|
||||
// <0x1=>61us
|
||||
// <0x2=>122us
|
||||
// <0x3=>244us
|
||||
// <0x4=>488us
|
||||
// <0x5=>977us
|
||||
// <0x6=>1953us
|
||||
// <0x7=>3906us
|
||||
// <0x8=>7813us
|
||||
// <0x9=>15625us
|
||||
// <0xA=>31250us
|
||||
// <0xB=>62500us
|
||||
// <0xC=>125000us
|
||||
// <0xD=>250000us
|
||||
// <0xE=>500000us
|
||||
// <0xF=>1000000us
|
||||
// <id> xosc1_arch_startup
|
||||
#ifndef CONF_XOSC1_STARTUP
|
||||
#define CONF_XOSC1_STARTUP 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc1_arch_swben
|
||||
#ifndef CONF_XOSC1_SWBEN
|
||||
#define CONF_XOSC1_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc1_arch_cfden
|
||||
#ifndef CONF_XOSC1_CFDEN
|
||||
#define CONF_XOSC1_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Automatic Loop Control Enable
|
||||
// <i> Indicates whether Automatic Loop Control is enabled or not
|
||||
// <id> xosc1_arch_enalc
|
||||
#ifndef CONF_XOSC1_ENALC
|
||||
#define CONF_XOSC1_ENALC 0
|
||||
#endif
|
||||
|
||||
// <q> Low Buffer Gain Enable
|
||||
// <i> Indicates whether Low Buffer Gain is enabled or not
|
||||
// <id> xosc1_arch_lowbufgain
|
||||
#ifndef CONF_XOSC1_LOWBUFGAIN
|
||||
#define CONF_XOSC1_LOWBUFGAIN 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc1_arch_ondemand
|
||||
#ifndef CONF_XOSC1_ONDEMAND
|
||||
#define CONF_XOSC1_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc1_arch_runstdby
|
||||
#ifndef CONF_XOSC1_RUNSTDBY
|
||||
#define CONF_XOSC1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN/XOUT Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc1_arch_xtalen
|
||||
#ifndef CONF_XOSC1_XTALEN
|
||||
#define CONF_XOSC1_XTALEN 1
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
#if CONF_XOSC1_FREQUENCY >= 32000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x0
|
||||
#define CONF_XOSC1_IMULT 0x7
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 24000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x1
|
||||
#define CONF_XOSC1_IMULT 0x6
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 16000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x2
|
||||
#define CONF_XOSC1_IMULT 0x5
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 8000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x3
|
||||
#define CONF_XOSC1_IMULT 0x4
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#endif
|
||||
|
||||
// <e> DFLL Configuration
|
||||
// <i> Indicates whether configuration for DFLL is enabled or not
|
||||
// <id> enable_dfll
|
||||
#ifndef CONF_DFLL_CONFIG
|
||||
#define CONF_DFLL_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source
|
||||
// <id> dfll_ref_clock
|
||||
#ifndef CONF_DFLL_GCLK
|
||||
#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK2_Val
|
||||
#endif
|
||||
|
||||
// <h> Digital Frequency Locked Loop Control
|
||||
// <q> DFLL Enable
|
||||
// <i> Indicates whether DFLL is enabled or not
|
||||
// <id> dfll_arch_enable
|
||||
#ifndef CONF_DFLL_ENABLE
|
||||
#define CONF_DFLL_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> dfll_arch_ondemand
|
||||
#ifndef CONF_DFLL_ONDEMAND
|
||||
#define CONF_DFLL_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> dfll_arch_runstdby
|
||||
#ifndef CONF_DFLL_RUNSTDBY
|
||||
#define CONF_DFLL_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> USB Clock Recovery Mode
|
||||
// <i> Indicates whether USB Clock Recovery Mode is enabled or not
|
||||
// <id> dfll_arch_usbcrm
|
||||
#ifndef CONF_DFLL_USBCRM
|
||||
#define CONF_DFLL_USBCRM 0
|
||||
#endif
|
||||
|
||||
// <q> Wait Lock
|
||||
// <i> Indicates whether Wait Lock is enabled or not
|
||||
// <id> dfll_arch_waitlock
|
||||
#ifndef CONF_DFLL_WAITLOCK
|
||||
#define CONF_DFLL_WAITLOCK 1
|
||||
#endif
|
||||
|
||||
// <q> Bypass Coarse Lock
|
||||
// <i> Indicates whether Bypass Coarse Lock is enabled or not
|
||||
// <id> dfll_arch_bplckc
|
||||
#ifndef CONF_DFLL_BPLCKC
|
||||
#define CONF_DFLL_BPLCKC 0
|
||||
#endif
|
||||
|
||||
// <q> Quick Lock Disable
|
||||
// <i> Indicates whether Quick Lock Disable is enabled or not
|
||||
// <id> dfll_arch_qldis
|
||||
#ifndef CONF_DFLL_QLDIS
|
||||
#define CONF_DFLL_QLDIS 0
|
||||
#endif
|
||||
|
||||
// <q> Chill Cycle Disable
|
||||
// <i> Indicates whether Chill Cycle Disable is enabled or not
|
||||
// <id> dfll_arch_ccdis
|
||||
#ifndef CONF_DFLL_CCDIS
|
||||
#define CONF_DFLL_CCDIS 0
|
||||
#endif
|
||||
|
||||
// <q> Lose Lock After Wake
|
||||
// <i> Indicates whether Lose Lock After Wake is enabled or not
|
||||
// <id> dfll_arch_llaw
|
||||
#ifndef CONF_DFLL_LLAW
|
||||
#define CONF_DFLL_LLAW 0
|
||||
#endif
|
||||
|
||||
// <q> Stable DFLL Frequency
|
||||
// <i> Indicates whether Stable DFLL Frequency is enabled or not
|
||||
// <id> dfll_arch_stable
|
||||
#ifndef CONF_DFLL_STABLE
|
||||
#define CONF_DFLL_STABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Operating Mode Selection
|
||||
// <0=>Open Loop Mode
|
||||
// <1=>Closed Loop Mode
|
||||
// <id> dfll_mode
|
||||
#ifndef CONF_DFLL_MODE
|
||||
#define CONF_DFLL_MODE 0x0
|
||||
#endif
|
||||
|
||||
// <o> Coarse Maximum Step <0x0-0x1F>
|
||||
// <id> dfll_arch_cstep
|
||||
#ifndef CONF_DFLL_CSTEP
|
||||
#define CONF_DFLL_CSTEP 0x1
|
||||
#endif
|
||||
|
||||
// <o> Fine Maximum Step <0x0-0xFF>
|
||||
// <id> dfll_arch_fstep
|
||||
#ifndef CONF_DFLL_FSTEP
|
||||
#define CONF_DFLL_FSTEP 0x1
|
||||
#endif
|
||||
|
||||
// <o> DFLL Multiply Factor <0x0-0xFFFF>
|
||||
// <id> dfll_mul
|
||||
#ifndef CONF_DFLL_MUL
|
||||
#define CONF_DFLL_MUL 0x0
|
||||
#endif
|
||||
|
||||
// <e> DFLL Calibration Overwrite
|
||||
// <i> Indicates whether Overwrite Calibration value of DFLL
|
||||
// <id> dfll_arch_calibration
|
||||
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
|
||||
#define CONF_DFLL_OVERWRITE_CALIBRATION 0
|
||||
#endif
|
||||
|
||||
// <o> Coarse Value <0x0-0x3F>
|
||||
// <id> dfll_arch_coarse
|
||||
#ifndef CONF_DFLL_COARSE
|
||||
#define CONF_DFLL_COARSE (0x1f / 4)
|
||||
#endif
|
||||
|
||||
// <o> Fine Value <0x0-0xFF>
|
||||
// <id> dfll_arch_fine
|
||||
#ifndef CONF_DFLL_FINE
|
||||
#define CONF_DFLL_FINE (0x80)
|
||||
#endif
|
||||
|
||||
//</e>
|
||||
|
||||
//</h>
|
||||
|
||||
//</e>
|
||||
|
||||
// <e> FDPLL0 Configuration
|
||||
// <i> Indicates whether configuration for FDPLL0 is enabled or not
|
||||
// <id> enable_fdpll0
|
||||
#ifndef CONF_FDPLL0_CONFIG
|
||||
#define CONF_FDPLL0_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source.
|
||||
// <id> fdpll0_ref_clock
|
||||
#ifndef CONF_FDPLL0_GCLK
|
||||
#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <h> Digital Phase Locked Loop Control
|
||||
// <q> Enable
|
||||
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
|
||||
// <id> fdpll0_arch_enable
|
||||
#ifndef CONF_FDPLL0_ENABLE
|
||||
#define CONF_FDPLL0_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> fdpll0_arch_ondemand
|
||||
#ifndef CONF_FDPLL0_ONDEMAND
|
||||
#define CONF_FDPLL0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> fdpll0_arch_runstdby
|
||||
#ifndef CONF_FDPLL0_RUNSTDBY
|
||||
#define CONF_FDPLL0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
|
||||
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll0_ldrfrac
|
||||
#ifndef CONF_FDPLL0_LDRFRAC
|
||||
#define CONF_FDPLL0_LDRFRAC 0xd
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
|
||||
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll0_ldr
|
||||
#ifndef CONF_FDPLL0_LDR
|
||||
#define CONF_FDPLL0_LDR 0x5b7
|
||||
#endif
|
||||
|
||||
// <o> Clock Divider <0x0-0x7FF>
|
||||
// <i> This Clock divider is only for XOSC clock input to DPLL
|
||||
// <id> fdpll0_clock_div
|
||||
#ifndef CONF_FDPLL0_DIV
|
||||
#define CONF_FDPLL0_DIV 0x0
|
||||
#endif
|
||||
|
||||
// <q> DCO Filter Enable
|
||||
// <i> Indicates whether DCO Filter Enable is enabled or not
|
||||
// <id> fdpll0_arch_dcoen
|
||||
#ifndef CONF_FDPLL0_DCOEN
|
||||
#define CONF_FDPLL0_DCOEN 0
|
||||
#endif
|
||||
|
||||
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
|
||||
// <id> fdpll0_clock_dcofilter
|
||||
#ifndef CONF_FDPLL0_DCOFILTER
|
||||
#define CONF_FDPLL0_DCOFILTER 0x0
|
||||
#endif
|
||||
|
||||
// <q> Lock Bypass
|
||||
// <i> Indicates whether Lock Bypass is enabled or not
|
||||
// <id> fdpll0_arch_lbypass
|
||||
#ifndef CONF_FDPLL0_LBYPASS
|
||||
#define CONF_FDPLL0_LBYPASS 0
|
||||
#endif
|
||||
|
||||
// <o> Lock Time
|
||||
// <0x0=>No time-out, automatic lock
|
||||
// <0x4=>The Time-out if no lock within 800 us
|
||||
// <0x5=>The Time-out if no lock within 900 us
|
||||
// <0x6=>The Time-out if no lock within 1 ms
|
||||
// <0x7=>The Time-out if no lock within 11 ms
|
||||
// <id> fdpll0_arch_ltime
|
||||
#ifndef CONF_FDPLL0_LTIME
|
||||
#define CONF_FDPLL0_LTIME 0x0
|
||||
#endif
|
||||
|
||||
// <o> Reference Clock Selection
|
||||
// <0x0=>GCLK clock reference
|
||||
// <0x1=>XOSC32K clock reference
|
||||
// <0x2=>XOSC0 clock reference
|
||||
// <0x3=>XOSC1 clock reference
|
||||
// <id> fdpll0_arch_refclk
|
||||
#ifndef CONF_FDPLL0_REFCLK
|
||||
#define CONF_FDPLL0_REFCLK 0x1
|
||||
#endif
|
||||
|
||||
// <q> Wake Up Fast
|
||||
// <i> Indicates whether Wake Up Fast is enabled or not
|
||||
// <id> fdpll0_arch_wuf
|
||||
#ifndef CONF_FDPLL0_WUF
|
||||
#define CONF_FDPLL0_WUF 0
|
||||
#endif
|
||||
|
||||
// <o> Proportional Integral Filter Selection <0x0-0xF>
|
||||
// <id> fdpll0_arch_filter
|
||||
#ifndef CONF_FDPLL0_FILTER
|
||||
#define CONF_FDPLL0_FILTER 0x0
|
||||
#endif
|
||||
|
||||
//</h>
|
||||
//</e>
|
||||
// <e> FDPLL1 Configuration
|
||||
// <i> Indicates whether configuration for FDPLL1 is enabled or not
|
||||
// <id> enable_fdpll1
|
||||
#ifndef CONF_FDPLL1_CONFIG
|
||||
#define CONF_FDPLL1_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source.
|
||||
// <id> fdpll1_ref_clock
|
||||
#ifndef CONF_FDPLL1_GCLK
|
||||
#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK1_Val
|
||||
#endif
|
||||
|
||||
// <h> Digital Phase Locked Loop Control
|
||||
// <q> Enable
|
||||
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
|
||||
// <id> fdpll1_arch_enable
|
||||
#ifndef CONF_FDPLL1_ENABLE
|
||||
#define CONF_FDPLL1_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> fdpll1_arch_ondemand
|
||||
#ifndef CONF_FDPLL1_ONDEMAND
|
||||
#define CONF_FDPLL1_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> fdpll1_arch_runstdby
|
||||
#ifndef CONF_FDPLL1_RUNSTDBY
|
||||
#define CONF_FDPLL1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
|
||||
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll1_ldrfrac
|
||||
#ifndef CONF_FDPLL1_LDRFRAC
|
||||
#define CONF_FDPLL1_LDRFRAC 0x0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
|
||||
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll1_ldr
|
||||
#ifndef CONF_FDPLL1_LDR
|
||||
#define CONF_FDPLL1_LDR 0x3b
|
||||
#endif
|
||||
|
||||
// <o> Clock Divider <0x0-0x7FF>
|
||||
// <i> This Clock divider is only for XOSC clock input to DPLL
|
||||
// <id> fdpll1_clock_div
|
||||
#ifndef CONF_FDPLL1_DIV
|
||||
#define CONF_FDPLL1_DIV 0x0
|
||||
#endif
|
||||
|
||||
// <q> DCO Filter Enable
|
||||
// <i> Indicates whether DCO Filter Enable is enabled or not
|
||||
// <id> fdpll1_arch_dcoen
|
||||
#ifndef CONF_FDPLL1_DCOEN
|
||||
#define CONF_FDPLL1_DCOEN 0
|
||||
#endif
|
||||
|
||||
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
|
||||
// <id> fdpll1_clock_dcofilter
|
||||
#ifndef CONF_FDPLL1_DCOFILTER
|
||||
#define CONF_FDPLL1_DCOFILTER 0x0
|
||||
#endif
|
||||
|
||||
// <q> Lock Bypass
|
||||
// <i> Indicates whether Lock Bypass is enabled or not
|
||||
// <id> fdpll1_arch_lbypass
|
||||
#ifndef CONF_FDPLL1_LBYPASS
|
||||
#define CONF_FDPLL1_LBYPASS 0
|
||||
#endif
|
||||
|
||||
// <o> Lock Time
|
||||
// <0x0=>No time-out, automatic lock
|
||||
// <0x4=>The Time-out if no lock within 800 us
|
||||
// <0x5=>The Time-out if no lock within 900 us
|
||||
// <0x6=>The Time-out if no lock within 1 ms
|
||||
// <0x7=>The Time-out if no lock within 11 ms
|
||||
// <id> fdpll1_arch_ltime
|
||||
#ifndef CONF_FDPLL1_LTIME
|
||||
#define CONF_FDPLL1_LTIME 0x0
|
||||
#endif
|
||||
|
||||
// <o> Reference Clock Selection
|
||||
// <0x0=>GCLK clock reference
|
||||
// <0x1=>XOSC32K clock reference
|
||||
// <0x2=>XOSC0 clock reference
|
||||
// <0x3=>XOSC1 clock reference
|
||||
// <id> fdpll1_arch_refclk
|
||||
#ifndef CONF_FDPLL1_REFCLK
|
||||
#define CONF_FDPLL1_REFCLK 0x0
|
||||
#endif
|
||||
|
||||
// <q> Wake Up Fast
|
||||
// <i> Indicates whether Wake Up Fast is enabled or not
|
||||
// <id> fdpll1_arch_wuf
|
||||
#ifndef CONF_FDPLL1_WUF
|
||||
#define CONF_FDPLL1_WUF 0
|
||||
#endif
|
||||
|
||||
// <o> Proportional Integral Filter Selection <0x0-0xF>
|
||||
// <id> fdpll1_arch_filter
|
||||
#ifndef CONF_FDPLL1_FILTER
|
||||
#define CONF_FDPLL1_FILTER 0x0
|
||||
#endif
|
||||
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_OSCCTRL_CONFIG_H
|
||||
|
|
@ -0,0 +1,522 @@
|
|||
/* Auto-generated config file hpl_port_config.h */
|
||||
#ifndef HPL_PORT_CONFIG_H
|
||||
#define HPL_PORT_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> PORT Input Event 0 configuration
|
||||
// <id> enable_port_input_event_0
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_0
|
||||
#define CONF_PORT_EVCTRL_PORT_0 1
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 0 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
|
||||
// <id> porta_input_event_enable_0
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_0
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_0
|
||||
#define CONF_PORTA_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 0
|
||||
// <id> porta_event_action_0
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_0
|
||||
#define CONF_PORTA_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
|
||||
// <id> portb_input_event_enable_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_0
|
||||
#define CONF_PORTB_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 0
|
||||
// <id> portb_event_action_0
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_0
|
||||
#define CONF_PORTB_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled
|
||||
// <id> portc_input_event_enable_0
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_0
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_0
|
||||
#define CONF_PORTC_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 0
|
||||
// <id> portc_event_action_0
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_0
|
||||
#define CONF_PORTC_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 0 configuration is enabled
|
||||
// <id> portd_input_event_enable_0
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_0 0x1
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_0
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_0
|
||||
#define CONF_PORTD_EVCTRL_PID_0 0xb
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 0
|
||||
// <id> portd_event_action_0
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_0
|
||||
#define CONF_PORTD_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 1 configuration
|
||||
// <id> enable_port_input_event_1
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_1
|
||||
#define CONF_PORT_EVCTRL_PORT_1 1
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 1 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
|
||||
// <id> porta_input_event_enable_1
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_1
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_1
|
||||
#define CONF_PORTA_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 1
|
||||
// <id> porta_event_action_1
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_1
|
||||
#define CONF_PORTA_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
|
||||
// <id> portb_input_event_enable_1
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_1
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_1
|
||||
#define CONF_PORTB_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 1
|
||||
// <id> portb_event_action_1
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_1
|
||||
#define CONF_PORTB_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled
|
||||
// <id> portc_input_event_enable_1
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_1 0x1
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_1
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_1
|
||||
#define CONF_PORTC_EVCTRL_PID_1 0x1
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 1
|
||||
// <id> portc_event_action_1
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_1
|
||||
#define CONF_PORTC_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 1 configuration is enabled
|
||||
// <id> portd_input_event_enable_1
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_1
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_1
|
||||
#define CONF_PORTD_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 1
|
||||
// <id> portd_event_action_1
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_1
|
||||
#define CONF_PORTD_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 2 configuration
|
||||
// <id> enable_port_input_event_2
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_2
|
||||
#define CONF_PORT_EVCTRL_PORT_2 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 2 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
|
||||
// <id> porta_input_event_enable_2
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_2
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_2
|
||||
#define CONF_PORTA_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 2
|
||||
// <id> porta_event_action_2
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_2
|
||||
#define CONF_PORTA_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
|
||||
// <id> portb_input_event_enable_2
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_2
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_2
|
||||
#define CONF_PORTB_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 2
|
||||
// <id> portb_event_action_2
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_2
|
||||
#define CONF_PORTB_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled
|
||||
// <id> portc_input_event_enable_2
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_2
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_2
|
||||
#define CONF_PORTC_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 2
|
||||
// <id> portc_event_action_2
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_2
|
||||
#define CONF_PORTC_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 2 configuration is enabled
|
||||
// <id> portd_input_event_enable_2
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_2
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_2
|
||||
#define CONF_PORTD_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 2
|
||||
// <id> portd_event_action_2
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_2
|
||||
#define CONF_PORTD_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 3 configuration
|
||||
// <id> enable_port_input_event_3
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_3
|
||||
#define CONF_PORT_EVCTRL_PORT_3 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 3 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
|
||||
// <id> porta_input_event_enable_3
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_3
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_3
|
||||
#define CONF_PORTA_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 3
|
||||
// <id> porta_event_action_3
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_3
|
||||
#define CONF_PORTA_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
|
||||
// <id> portb_input_event_enable_3
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_3
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_3
|
||||
#define CONF_PORTB_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 3
|
||||
// <id> portb_event_action_3
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_3
|
||||
#define CONF_PORTB_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled
|
||||
// <id> portc_input_event_enable_3
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_3
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_3
|
||||
#define CONF_PORTC_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 3
|
||||
// <id> portc_event_action_3
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_3
|
||||
#define CONF_PORTC_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 3 configuration is enabled
|
||||
// <id> portd_input_event_enable_3
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_3
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_3
|
||||
#define CONF_PORTD_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 3
|
||||
// <id> portd_event_action_3
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_3
|
||||
#define CONF_PORTD_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
#define CONF_PORTA_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
|
||||
#define CONF_PORTB_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
|
||||
#define CONF_PORTC_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3))
|
||||
#define CONF_PORTD_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTD_EVCTRL_EVACT_0) | CONF_PORTD_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTD_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTD_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTD_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTD_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTD_EVCTRL_EVACT_2) | CONF_PORTD_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTD_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTD_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTD_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTD_EVCTRL_PID_3))
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_PORT_CONFIG_H
|
||||
|
|
@ -0,0 +1,371 @@
|
|||
/* Auto-generated config file hpl_sercom_config.h */
|
||||
#ifndef HPL_SERCOM_CONFIG_H
|
||||
#define HPL_SERCOM_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// Enable configuration of module
|
||||
#ifndef CONF_SERCOM_4_SPI_ENABLE
|
||||
#define CONF_SERCOM_4_SPI_ENABLE 1
|
||||
#endif
|
||||
|
||||
//<o> SPI DMA TX Channel <0-32>
|
||||
//<i> This defines DMA channel to be used
|
||||
//<id> spi_master_dma_tx_channel
|
||||
#ifndef CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL
|
||||
#define CONF_SERCOM_4_SPI_M_DMA_TX_CHANNEL 2
|
||||
#endif
|
||||
|
||||
// <e> SPI RX Channel Enable
|
||||
// <id> spi_master_rx_channel
|
||||
#ifndef CONF_SERCOM_4_SPI_RX_CHANNEL
|
||||
#define CONF_SERCOM_4_SPI_RX_CHANNEL 1
|
||||
#endif
|
||||
|
||||
//<o> DMA Channel <0-32>
|
||||
//<i> This defines DMA channel to be used
|
||||
//<id> spi_master_dma_rx_channel
|
||||
#ifndef CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL
|
||||
#define CONF_SERCOM_4_SPI_M_DMA_RX_CHANNEL 3
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// Set module in SPI Master mode
|
||||
#ifndef CONF_SERCOM_4_SPI_MODE
|
||||
#define CONF_SERCOM_4_SPI_MODE 0x03
|
||||
#endif
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <q> Receive buffer enable
|
||||
// <i> Enable receive buffer to receive data from slave (RXEN)
|
||||
// <id> spi_master_rx_enable
|
||||
#ifndef CONF_SERCOM_4_SPI_RXEN
|
||||
#define CONF_SERCOM_4_SPI_RXEN 0x1
|
||||
#endif
|
||||
|
||||
// <o> Character Size
|
||||
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
|
||||
// <0x0=>8 bits
|
||||
// <0x1=>9 bits
|
||||
// <id> spi_master_character_size
|
||||
#ifndef CONF_SERCOM_4_SPI_CHSIZE
|
||||
#define CONF_SERCOM_4_SPI_CHSIZE 0x0
|
||||
#endif
|
||||
// <o> Baud rate <1-18000000>
|
||||
// <i> The SPI data transfer rate
|
||||
// <id> spi_master_baud_rate
|
||||
#ifndef CONF_SERCOM_4_SPI_BAUD
|
||||
#define CONF_SERCOM_4_SPI_BAUD 1000000
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> spi_master_advanced
|
||||
#ifndef CONF_SERCOM_4_SPI_ADVANCED
|
||||
#define CONF_SERCOM_4_SPI_ADVANCED 0
|
||||
#endif
|
||||
|
||||
// <o> Dummy byte <0x00-0x1ff>
|
||||
// <id> spi_master_dummybyte
|
||||
// <i> Dummy byte used when reading data from the slave without sending any data
|
||||
#ifndef CONF_SERCOM_4_SPI_DUMMYBYTE
|
||||
#define CONF_SERCOM_4_SPI_DUMMYBYTE 0x1ff
|
||||
#endif
|
||||
|
||||
// <o> Data Order
|
||||
// <0=>MSB first
|
||||
// <1=>LSB first
|
||||
// <i> I least significant or most significant bit is shifted out first (DORD)
|
||||
// <id> spi_master_arch_dord
|
||||
#ifndef CONF_SERCOM_4_SPI_DORD
|
||||
#define CONF_SERCOM_4_SPI_DORD 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Polarity
|
||||
// <0=>SCK is low when idle
|
||||
// <1=>SCK is high when idle
|
||||
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
|
||||
// <id> spi_master_arch_cpol
|
||||
#ifndef CONF_SERCOM_4_SPI_CPOL
|
||||
#define CONF_SERCOM_4_SPI_CPOL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Phase
|
||||
// <0x0=>Sample input on leading edge
|
||||
// <0x1=>Sample input on trailing edge
|
||||
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
|
||||
// <id> spi_master_arch_cpha
|
||||
#ifndef CONF_SERCOM_4_SPI_CPHA
|
||||
#define CONF_SERCOM_4_SPI_CPHA 0x0
|
||||
#endif
|
||||
|
||||
// <o> Immediate Buffer Overflow Notification
|
||||
// <i> Controls when OVF is asserted (IBON)
|
||||
// <0x0=>In data stream
|
||||
// <0x1=>On buffer overflow
|
||||
// <id> spi_master_arch_ibon
|
||||
#ifndef CONF_SERCOM_4_SPI_IBON
|
||||
#define CONF_SERCOM_4_SPI_IBON 0x0
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
|
||||
// <id> spi_master_arch_runstdby
|
||||
#ifndef CONF_SERCOM_4_SPI_RUNSTDBY
|
||||
#define CONF_SERCOM_4_SPI_RUNSTDBY 0x0
|
||||
#endif
|
||||
|
||||
// <o> Debug Stop Mode
|
||||
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
|
||||
// <0=>Keep running
|
||||
// <1=>Halt
|
||||
// <id> spi_master_arch_dbgstop
|
||||
#ifndef CONF_SERCOM_4_SPI_DBGSTOP
|
||||
#define CONF_SERCOM_4_SPI_DBGSTOP 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// Address mode disabled in master mode
|
||||
#ifndef CONF_SERCOM_4_SPI_AMODE_EN
|
||||
#define CONF_SERCOM_4_SPI_AMODE_EN 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_4_SPI_AMODE
|
||||
#define CONF_SERCOM_4_SPI_AMODE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_4_SPI_ADDR
|
||||
#define CONF_SERCOM_4_SPI_ADDR 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_4_SPI_ADDRMASK
|
||||
#define CONF_SERCOM_4_SPI_ADDRMASK 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_4_SPI_SSDE
|
||||
#define CONF_SERCOM_4_SPI_SSDE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_4_SPI_MSSEN
|
||||
#define CONF_SERCOM_4_SPI_MSSEN 0x0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_4_SPI_PLOADEN
|
||||
#define CONF_SERCOM_4_SPI_PLOADEN 0
|
||||
#endif
|
||||
|
||||
// <o> Receive Data Pinout
|
||||
// <0x0=>PAD[0]
|
||||
// <0x1=>PAD[1]
|
||||
// <0x2=>PAD[2]
|
||||
// <0x3=>PAD[3]
|
||||
// <id> spi_master_rxpo
|
||||
#ifndef CONF_SERCOM_4_SPI_RXPO
|
||||
#define CONF_SERCOM_4_SPI_RXPO 3
|
||||
#endif
|
||||
|
||||
// <o> Transmit Data Pinout
|
||||
// <0x0=>PAD[0,1]_DO_SCK
|
||||
// <0x1=>PAD[2,3]_DO_SCK
|
||||
// <0x2=>PAD[3,1]_DO_SCK
|
||||
// <0x3=>PAD[0,3]_DO_SCK
|
||||
// <id> spi_master_txpo
|
||||
#ifndef CONF_SERCOM_4_SPI_TXPO
|
||||
#define CONF_SERCOM_4_SPI_TXPO 0
|
||||
#endif
|
||||
|
||||
// Calculate baud register value from requested baudrate value
|
||||
#ifndef CONF_SERCOM_4_SPI_BAUD_RATE
|
||||
#define CONF_SERCOM_4_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM4_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_4_SPI_BAUD)) - 1
|
||||
#endif
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// Enable configuration of module
|
||||
#ifndef CONF_SERCOM_5_SPI_ENABLE
|
||||
#define CONF_SERCOM_5_SPI_ENABLE 1
|
||||
#endif
|
||||
|
||||
//<o> SPI DMA TX Channel <0-32>
|
||||
//<i> This defines DMA channel to be used
|
||||
//<id> spi_master_dma_tx_channel
|
||||
#ifndef CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL
|
||||
#define CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL 1
|
||||
#endif
|
||||
|
||||
// <e> SPI RX Channel Enable
|
||||
// <id> spi_master_rx_channel
|
||||
#ifndef CONF_SERCOM_5_SPI_RX_CHANNEL
|
||||
#define CONF_SERCOM_5_SPI_RX_CHANNEL 1
|
||||
#endif
|
||||
|
||||
//<o> DMA Channel <0-32>
|
||||
//<i> This defines DMA channel to be used
|
||||
//<id> spi_master_dma_rx_channel
|
||||
#ifndef CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL
|
||||
#define CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// Set module in SPI Master mode
|
||||
#ifndef CONF_SERCOM_5_SPI_MODE
|
||||
#define CONF_SERCOM_5_SPI_MODE 0x03
|
||||
#endif
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <q> Receive buffer enable
|
||||
// <i> Enable receive buffer to receive data from slave (RXEN)
|
||||
// <id> spi_master_rx_enable
|
||||
#ifndef CONF_SERCOM_5_SPI_RXEN
|
||||
#define CONF_SERCOM_5_SPI_RXEN 0x1
|
||||
#endif
|
||||
|
||||
// <o> Character Size
|
||||
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
|
||||
// <0x0=>8 bits
|
||||
// <0x1=>9 bits
|
||||
// <id> spi_master_character_size
|
||||
#ifndef CONF_SERCOM_5_SPI_CHSIZE
|
||||
#define CONF_SERCOM_5_SPI_CHSIZE 0x0
|
||||
#endif
|
||||
// <o> Baud rate <1-18000000>
|
||||
// <i> The SPI data transfer rate
|
||||
// <id> spi_master_baud_rate
|
||||
#ifndef CONF_SERCOM_5_SPI_BAUD
|
||||
#define CONF_SERCOM_5_SPI_BAUD 12000000
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> spi_master_advanced
|
||||
#ifndef CONF_SERCOM_5_SPI_ADVANCED
|
||||
#define CONF_SERCOM_5_SPI_ADVANCED 1
|
||||
#endif
|
||||
|
||||
// <o> Dummy byte <0x00-0x1ff>
|
||||
// <id> spi_master_dummybyte
|
||||
// <i> Dummy byte used when reading data from the slave without sending any data
|
||||
#ifndef CONF_SERCOM_5_SPI_DUMMYBYTE
|
||||
#define CONF_SERCOM_5_SPI_DUMMYBYTE 0x1ff
|
||||
#endif
|
||||
|
||||
// <o> Data Order
|
||||
// <0=>MSB first
|
||||
// <1=>LSB first
|
||||
// <i> I least significant or most significant bit is shifted out first (DORD)
|
||||
// <id> spi_master_arch_dord
|
||||
#ifndef CONF_SERCOM_5_SPI_DORD
|
||||
#define CONF_SERCOM_5_SPI_DORD 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Polarity
|
||||
// <0=>SCK is low when idle
|
||||
// <1=>SCK is high when idle
|
||||
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
|
||||
// <id> spi_master_arch_cpol
|
||||
#ifndef CONF_SERCOM_5_SPI_CPOL
|
||||
#define CONF_SERCOM_5_SPI_CPOL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Phase
|
||||
// <0x0=>Sample input on leading edge
|
||||
// <0x1=>Sample input on trailing edge
|
||||
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
|
||||
// <id> spi_master_arch_cpha
|
||||
#ifndef CONF_SERCOM_5_SPI_CPHA
|
||||
#define CONF_SERCOM_5_SPI_CPHA 0x0
|
||||
#endif
|
||||
|
||||
// <o> Immediate Buffer Overflow Notification
|
||||
// <i> Controls when OVF is asserted (IBON)
|
||||
// <0x0=>In data stream
|
||||
// <0x1=>On buffer overflow
|
||||
// <id> spi_master_arch_ibon
|
||||
#ifndef CONF_SERCOM_5_SPI_IBON
|
||||
#define CONF_SERCOM_5_SPI_IBON 0x0
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
|
||||
// <id> spi_master_arch_runstdby
|
||||
#ifndef CONF_SERCOM_5_SPI_RUNSTDBY
|
||||
#define CONF_SERCOM_5_SPI_RUNSTDBY 0x0
|
||||
#endif
|
||||
|
||||
// <o> Debug Stop Mode
|
||||
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
|
||||
// <0=>Keep running
|
||||
// <1=>Halt
|
||||
// <id> spi_master_arch_dbgstop
|
||||
#ifndef CONF_SERCOM_5_SPI_DBGSTOP
|
||||
#define CONF_SERCOM_5_SPI_DBGSTOP 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// Address mode disabled in master mode
|
||||
#ifndef CONF_SERCOM_5_SPI_AMODE_EN
|
||||
#define CONF_SERCOM_5_SPI_AMODE_EN 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_5_SPI_AMODE
|
||||
#define CONF_SERCOM_5_SPI_AMODE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_5_SPI_ADDR
|
||||
#define CONF_SERCOM_5_SPI_ADDR 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_5_SPI_ADDRMASK
|
||||
#define CONF_SERCOM_5_SPI_ADDRMASK 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_5_SPI_SSDE
|
||||
#define CONF_SERCOM_5_SPI_SSDE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_5_SPI_MSSEN
|
||||
#define CONF_SERCOM_5_SPI_MSSEN 0x0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_5_SPI_PLOADEN
|
||||
#define CONF_SERCOM_5_SPI_PLOADEN 0
|
||||
#endif
|
||||
|
||||
// <o> Receive Data Pinout
|
||||
// <0x0=>PAD[0]
|
||||
// <0x1=>PAD[1]
|
||||
// <0x2=>PAD[2]
|
||||
// <0x3=>PAD[3]
|
||||
// <id> spi_master_rxpo
|
||||
#ifndef CONF_SERCOM_5_SPI_RXPO
|
||||
#define CONF_SERCOM_5_SPI_RXPO 3
|
||||
#endif
|
||||
|
||||
// <o> Transmit Data Pinout
|
||||
// <0x0=>PAD[0,1]_DO_SCK
|
||||
// <0x1=>PAD[2,3]_DO_SCK
|
||||
// <0x2=>PAD[3,1]_DO_SCK
|
||||
// <0x3=>PAD[0,3]_DO_SCK
|
||||
// <id> spi_master_txpo
|
||||
#ifndef CONF_SERCOM_5_SPI_TXPO
|
||||
#define CONF_SERCOM_5_SPI_TXPO 0
|
||||
#endif
|
||||
|
||||
// Calculate baud register value from requested baudrate value
|
||||
#ifndef CONF_SERCOM_5_SPI_BAUD_RATE
|
||||
#define CONF_SERCOM_5_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM5_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_5_SPI_BAUD)) - 1
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_SERCOM_CONFIG_H
|
||||
|
|
@ -0,0 +1,709 @@
|
|||
/* Auto-generated config file peripheral_clk_config.h */
|
||||
#ifndef PERIPHERAL_CLK_CONFIG_H
|
||||
#define PERIPHERAL_CLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <y> EVSYS Channel 0 Clock Source
|
||||
// <id> evsys_clk_selection_0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 0.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 1 Clock Source
|
||||
// <id> evsys_clk_selection_1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 1.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 2 Clock Source
|
||||
// <id> evsys_clk_selection_2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 2.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 3 Clock Source
|
||||
// <id> evsys_clk_selection_3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 3.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 4 Clock Source
|
||||
// <id> evsys_clk_selection_4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 4.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 5 Clock Source
|
||||
// <id> evsys_clk_selection_5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 5.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 6 Clock Source
|
||||
// <id> evsys_clk_selection_6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 6.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 7 Clock Source
|
||||
// <id> evsys_clk_selection_7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 7.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 8 Clock Source
|
||||
// <id> evsys_clk_selection_8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 8.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 9 Clock Source
|
||||
// <id> evsys_clk_selection_9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 9.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 10 Clock Source
|
||||
// <id> evsys_clk_selection_10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 10.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 11 Clock Source
|
||||
// <id> evsys_clk_selection_11
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 11.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_CPU_FREQUENCY
|
||||
* \brief CPU's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_CPU_FREQUENCY
|
||||
#define CONF_CPU_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> Core Clock Source
|
||||
// <id> core_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM4_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> Slow Clock Source
|
||||
// <id> slow_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the slow clock source.
|
||||
#ifndef CONF_GCLK_SERCOM4_SLOW_SRC
|
||||
#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM4_CORE_FREQUENCY
|
||||
* \brief SERCOM4's Core Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY
|
||||
* \brief SERCOM4's Slow Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768
|
||||
#endif
|
||||
|
||||
// <y> Core Clock Source
|
||||
// <id> core_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM5_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> Slow Clock Source
|
||||
// <id> slow_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the slow clock source.
|
||||
#ifndef CONF_GCLK_SERCOM5_SLOW_SRC
|
||||
#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM5_CORE_FREQUENCY
|
||||
* \brief SERCOM5's Core Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM5_SLOW_FREQUENCY
|
||||
* \brief SERCOM5's Slow Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM5_SLOW_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768
|
||||
#endif
|
||||
|
||||
// <y> TC Clock Source
|
||||
// <id> tc_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for TC.
|
||||
#ifndef CONF_GCLK_TC7_SRC
|
||||
#define CONF_GCLK_TC7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_TC7_FREQUENCY
|
||||
* \brief TC7's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_TC7_FREQUENCY
|
||||
#define CONF_GCLK_TC7_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // PERIPHERAL_CLK_CONFIG_H
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Application implement
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef SPI_SLAVE_DMA_CONFIG_H
|
||||
#define SPI_SLAVE_DMA_CONFIG_H
|
||||
|
||||
// <o> Delay in Micro Seconds <1-1000>
|
||||
// <i> Delay in microseconds to hold CS low after data transfer completion by DMA
|
||||
// <id> delay_in_us_cs_low
|
||||
#ifndef CONF_DELAY_US
|
||||
#define CONF_DELAY_US 20
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,475 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Configurations xmlns:i="http://www.w3.org/2001/XMLSchema-instance" z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/" xmlns="DefaultValues">
|
||||
<Configurations>
|
||||
<Configuration z:Id="i2">
|
||||
<Compiler_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>DebugLevel</d4p1:Key>
|
||||
<d4p1:Value>None</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>IncludePaths</d4p1:Key>
|
||||
<d4p1:Value>NDEBUG</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>MiscellaneousSettings</d4p1:Key>
|
||||
<d4p1:Value>-std=gnu99</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>OptimizationLevel</d4p1:Key>
|
||||
<d4p1:Value>Optimize for size (-Os)</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>SymbolDefines</d4p1:Key>
|
||||
<d4p1:Value>NDEBUG</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>SymbolUndefines</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>Verbose</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>WarningsAsErrors</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.CheckSyntaxOnly</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.Pedantic</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.PedanticWarningsAsErrors</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.InhibitAllWarnings</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.miscellaneous.Device</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.miscellaneous.CompileOnly</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.miscellaneous.SupportAnsiPrograms</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.miscellaneous.MakeFileDependent</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
</Compiler_dictionary>
|
||||
<Linker_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>Libraries</d4p1:Key>
|
||||
<d4p1:Value>libm</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>LibrarySearchPath</d4p1:Key>
|
||||
<d4p1:Value>$(ProjectDir)\Device_Startup</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>MiscellaneousSettings</d4p1:Key>
|
||||
<d4p1:Value>-Tsame54p20a_flash.ld</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.DoNotUseStandardStartFiles</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.DoNotUseDefaultLibraries</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.NoStartupOrDefaultLibs</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.OmitAllSymbolInformation</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.NoSharedLibraries</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.GenerateMAPFile</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.UseNewlibNano</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.AdditionalSpecs</d4p1:Key>
|
||||
<d4p1:Value>None</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.optimization.GarbageCollectUnusedSections</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.optimization.EnableFastMath</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.optimization.GeneratePositionIndependentCode</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.memorysettings.Flash</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.memorysettings.Sram</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.memorysettings.ExternalRAM</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.miscellaneous.OtherOptions</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.miscellaneous.OtherObjects</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
</Linker_dictionary>
|
||||
<Name>Debug</Name>
|
||||
</Configuration>
|
||||
</Configurations>
|
||||
</Configurations>
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME54P20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME54P20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
|
|
@ -0,0 +1,546 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief gcc starttup file for SAME54
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same54.h"
|
||||
|
||||
/* Initialize segments */
|
||||
extern uint32_t _sfixed;
|
||||
extern uint32_t _efixed;
|
||||
extern uint32_t _etext;
|
||||
extern uint32_t _srelocate;
|
||||
extern uint32_t _erelocate;
|
||||
extern uint32_t _szero;
|
||||
extern uint32_t _ezero;
|
||||
extern uint32_t _sstack;
|
||||
extern uint32_t _estack;
|
||||
|
||||
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
|
||||
int main(void);
|
||||
/** \endcond */
|
||||
|
||||
void __libc_init_array(void);
|
||||
|
||||
/* Default empty handler */
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M4 core handlers */
|
||||
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MemManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void OSCCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
|
||||
void OSCCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
|
||||
void OSCCTRL_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
|
||||
void OSCCTRL_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
|
||||
void OSCCTRL_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
|
||||
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SUPC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
|
||||
void SUPC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
|
||||
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EIC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
|
||||
void EIC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
|
||||
void EIC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
|
||||
void EIC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
|
||||
void EIC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
|
||||
void EIC_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
|
||||
void EIC_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
|
||||
void EIC_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
|
||||
void EIC_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
|
||||
void EIC_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
|
||||
void EIC_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
|
||||
void EIC_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
|
||||
void EIC_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
|
||||
void EIC_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
|
||||
void EIC_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
|
||||
void EIC_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
|
||||
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
|
||||
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
|
||||
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
|
||||
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
|
||||
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
|
||||
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
|
||||
void DMAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
|
||||
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
|
||||
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
|
||||
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
|
||||
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
|
||||
void EVSYS_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
|
||||
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
|
||||
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
|
||||
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
|
||||
void SERCOM0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
|
||||
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
|
||||
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
|
||||
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
|
||||
void SERCOM1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
|
||||
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
|
||||
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
|
||||
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
|
||||
void SERCOM2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
|
||||
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
|
||||
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
|
||||
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
|
||||
void SERCOM3_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
|
||||
#ifdef ID_SERCOM4
|
||||
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
|
||||
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
|
||||
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
|
||||
void SERCOM4_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
|
||||
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
|
||||
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
|
||||
void SERCOM5_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM6
|
||||
void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
|
||||
void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
|
||||
void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
|
||||
void SERCOM6_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM7
|
||||
void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
|
||||
void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
|
||||
void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
|
||||
void SERCOM7_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
|
||||
#endif
|
||||
#ifdef ID_CAN0
|
||||
void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_CAN1
|
||||
void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_USB
|
||||
void USB_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
|
||||
void USB_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
|
||||
void USB_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
|
||||
void USB_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
|
||||
#endif
|
||||
#ifdef ID_GMAC
|
||||
void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void TCC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
|
||||
void TCC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
|
||||
void TCC0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
|
||||
void TCC0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
|
||||
void TCC0_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
|
||||
void TCC0_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
|
||||
void TCC0_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
|
||||
void TCC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
|
||||
void TCC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
|
||||
void TCC1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
|
||||
void TCC1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
|
||||
void TCC1_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
|
||||
void TCC2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
|
||||
void TCC2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
|
||||
void TCC2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
|
||||
void TCC2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
|
||||
#ifdef ID_TCC3
|
||||
void TCC3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
|
||||
void TCC3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
|
||||
void TCC3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
|
||||
#endif
|
||||
#ifdef ID_TCC4
|
||||
void TCC4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
|
||||
void TCC4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
|
||||
void TCC4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
|
||||
#endif
|
||||
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_TC4
|
||||
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC5
|
||||
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC6
|
||||
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC7
|
||||
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void PDEC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
|
||||
void PDEC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
|
||||
void PDEC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
|
||||
void ADC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
|
||||
void ADC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
|
||||
void ADC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
|
||||
void ADC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
|
||||
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
|
||||
void DAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
|
||||
void DAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
|
||||
void DAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
|
||||
void DAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
|
||||
#ifdef ID_I2S
|
||||
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_ICM
|
||||
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_PUKCC
|
||||
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_SDHC0
|
||||
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_SDHC1
|
||||
void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
|
||||
/* Exception Table */
|
||||
__attribute__ ((section(".vectors")))
|
||||
const DeviceVectors exception_table = {
|
||||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
.pvStack = (void*) (&_estack),
|
||||
|
||||
.pfnReset_Handler = (void*) Reset_Handler,
|
||||
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
|
||||
.pfnHardFault_Handler = (void*) HardFault_Handler,
|
||||
.pfnMemManagement_Handler = (void*) MemManagement_Handler,
|
||||
.pfnBusFault_Handler = (void*) BusFault_Handler,
|
||||
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
|
||||
.pvReservedM9 = (void*) (0UL), /* Reserved */
|
||||
.pvReservedM8 = (void*) (0UL), /* Reserved */
|
||||
.pvReservedM7 = (void*) (0UL), /* Reserved */
|
||||
.pvReservedM6 = (void*) (0UL), /* Reserved */
|
||||
.pfnSVCall_Handler = (void*) SVCall_Handler,
|
||||
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
|
||||
.pvReservedM3 = (void*) (0UL), /* Reserved */
|
||||
.pfnPendSV_Handler = (void*) PendSV_Handler,
|
||||
.pfnSysTick_Handler = (void*) SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
|
||||
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
|
||||
.pfnOSCCTRL_0_Handler = (void*) OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
|
||||
.pfnOSCCTRL_1_Handler = (void*) OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
|
||||
.pfnOSCCTRL_2_Handler = (void*) OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
|
||||
.pfnOSCCTRL_3_Handler = (void*) OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
|
||||
.pfnOSCCTRL_4_Handler = (void*) OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
|
||||
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
|
||||
.pfnSUPC_0_Handler = (void*) SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
|
||||
.pfnSUPC_1_Handler = (void*) SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */
|
||||
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
|
||||
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
|
||||
.pfnEIC_0_Handler = (void*) EIC_0_Handler, /* 12 EIC_EXTINT_0 */
|
||||
.pfnEIC_1_Handler = (void*) EIC_1_Handler, /* 13 EIC_EXTINT_1 */
|
||||
.pfnEIC_2_Handler = (void*) EIC_2_Handler, /* 14 EIC_EXTINT_2 */
|
||||
.pfnEIC_3_Handler = (void*) EIC_3_Handler, /* 15 EIC_EXTINT_3 */
|
||||
.pfnEIC_4_Handler = (void*) EIC_4_Handler, /* 16 EIC_EXTINT_4 */
|
||||
.pfnEIC_5_Handler = (void*) EIC_5_Handler, /* 17 EIC_EXTINT_5 */
|
||||
.pfnEIC_6_Handler = (void*) EIC_6_Handler, /* 18 EIC_EXTINT_6 */
|
||||
.pfnEIC_7_Handler = (void*) EIC_7_Handler, /* 19 EIC_EXTINT_7 */
|
||||
.pfnEIC_8_Handler = (void*) EIC_8_Handler, /* 20 EIC_EXTINT_8 */
|
||||
.pfnEIC_9_Handler = (void*) EIC_9_Handler, /* 21 EIC_EXTINT_9 */
|
||||
.pfnEIC_10_Handler = (void*) EIC_10_Handler, /* 22 EIC_EXTINT_10 */
|
||||
.pfnEIC_11_Handler = (void*) EIC_11_Handler, /* 23 EIC_EXTINT_11 */
|
||||
.pfnEIC_12_Handler = (void*) EIC_12_Handler, /* 24 EIC_EXTINT_12 */
|
||||
.pfnEIC_13_Handler = (void*) EIC_13_Handler, /* 25 EIC_EXTINT_13 */
|
||||
.pfnEIC_14_Handler = (void*) EIC_14_Handler, /* 26 EIC_EXTINT_14 */
|
||||
.pfnEIC_15_Handler = (void*) EIC_15_Handler, /* 27 EIC_EXTINT_15 */
|
||||
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
|
||||
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
|
||||
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
|
||||
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
|
||||
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
|
||||
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
|
||||
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
|
||||
.pfnDMAC_4_Handler = (void*) DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
|
||||
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
|
||||
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
|
||||
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
|
||||
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
|
||||
.pfnEVSYS_4_Handler = (void*) EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
|
||||
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
|
||||
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
|
||||
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
|
||||
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
|
||||
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
|
||||
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 SERCOM0_0 */
|
||||
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 SERCOM0_1 */
|
||||
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 SERCOM0_2 */
|
||||
.pfnSERCOM0_3_Handler = (void*) SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
|
||||
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 SERCOM1_0 */
|
||||
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 SERCOM1_1 */
|
||||
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 SERCOM1_2 */
|
||||
.pfnSERCOM1_3_Handler = (void*) SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
|
||||
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 SERCOM2_0 */
|
||||
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 SERCOM2_1 */
|
||||
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 SERCOM2_2 */
|
||||
.pfnSERCOM2_3_Handler = (void*) SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
|
||||
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 SERCOM3_0 */
|
||||
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 SERCOM3_1 */
|
||||
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 SERCOM3_2 */
|
||||
.pfnSERCOM3_3_Handler = (void*) SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
|
||||
#ifdef ID_SERCOM4
|
||||
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 SERCOM4_0 */
|
||||
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 SERCOM4_1 */
|
||||
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 SERCOM4_2 */
|
||||
.pfnSERCOM4_3_Handler = (void*) SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
|
||||
#else
|
||||
.pvReserved62 = (void*) (0UL), /* 62 Reserved */
|
||||
.pvReserved63 = (void*) (0UL), /* 63 Reserved */
|
||||
.pvReserved64 = (void*) (0UL), /* 64 Reserved */
|
||||
.pvReserved65 = (void*) (0UL), /* 65 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 SERCOM5_0 */
|
||||
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 SERCOM5_1 */
|
||||
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 SERCOM5_2 */
|
||||
.pfnSERCOM5_3_Handler = (void*) SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
|
||||
#else
|
||||
.pvReserved66 = (void*) (0UL), /* 66 Reserved */
|
||||
.pvReserved67 = (void*) (0UL), /* 67 Reserved */
|
||||
.pvReserved68 = (void*) (0UL), /* 68 Reserved */
|
||||
.pvReserved69 = (void*) (0UL), /* 69 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM6
|
||||
.pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 SERCOM6_0 */
|
||||
.pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 SERCOM6_1 */
|
||||
.pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 SERCOM6_2 */
|
||||
.pfnSERCOM6_3_Handler = (void*) SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
|
||||
#else
|
||||
.pvReserved70 = (void*) (0UL), /* 70 Reserved */
|
||||
.pvReserved71 = (void*) (0UL), /* 71 Reserved */
|
||||
.pvReserved72 = (void*) (0UL), /* 72 Reserved */
|
||||
.pvReserved73 = (void*) (0UL), /* 73 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM7
|
||||
.pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 SERCOM7_0 */
|
||||
.pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 SERCOM7_1 */
|
||||
.pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 SERCOM7_2 */
|
||||
.pfnSERCOM7_3_Handler = (void*) SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
|
||||
#else
|
||||
.pvReserved74 = (void*) (0UL), /* 74 Reserved */
|
||||
.pvReserved75 = (void*) (0UL), /* 75 Reserved */
|
||||
.pvReserved76 = (void*) (0UL), /* 76 Reserved */
|
||||
.pvReserved77 = (void*) (0UL), /* 77 Reserved */
|
||||
#endif
|
||||
#ifdef ID_CAN0
|
||||
.pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network 0 */
|
||||
#else
|
||||
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
|
||||
#endif
|
||||
#ifdef ID_CAN1
|
||||
.pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network 1 */
|
||||
#else
|
||||
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
|
||||
#endif
|
||||
#ifdef ID_USB
|
||||
.pfnUSB_0_Handler = (void*) USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
|
||||
.pfnUSB_1_Handler = (void*) USB_1_Handler, /* 81 USB_SOF_HSOF */
|
||||
.pfnUSB_2_Handler = (void*) USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
|
||||
.pfnUSB_3_Handler = (void*) USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
|
||||
#else
|
||||
.pvReserved80 = (void*) (0UL), /* 80 Reserved */
|
||||
.pvReserved81 = (void*) (0UL), /* 81 Reserved */
|
||||
.pvReserved82 = (void*) (0UL), /* 82 Reserved */
|
||||
.pvReserved83 = (void*) (0UL), /* 83 Reserved */
|
||||
#endif
|
||||
#ifdef ID_GMAC
|
||||
.pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */
|
||||
#else
|
||||
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
|
||||
#endif
|
||||
.pfnTCC0_0_Handler = (void*) TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
|
||||
.pfnTCC0_1_Handler = (void*) TCC0_1_Handler, /* 86 TCC0_MC_0 */
|
||||
.pfnTCC0_2_Handler = (void*) TCC0_2_Handler, /* 87 TCC0_MC_1 */
|
||||
.pfnTCC0_3_Handler = (void*) TCC0_3_Handler, /* 88 TCC0_MC_2 */
|
||||
.pfnTCC0_4_Handler = (void*) TCC0_4_Handler, /* 89 TCC0_MC_3 */
|
||||
.pfnTCC0_5_Handler = (void*) TCC0_5_Handler, /* 90 TCC0_MC_4 */
|
||||
.pfnTCC0_6_Handler = (void*) TCC0_6_Handler, /* 91 TCC0_MC_5 */
|
||||
.pfnTCC1_0_Handler = (void*) TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
|
||||
.pfnTCC1_1_Handler = (void*) TCC1_1_Handler, /* 93 TCC1_MC_0 */
|
||||
.pfnTCC1_2_Handler = (void*) TCC1_2_Handler, /* 94 TCC1_MC_1 */
|
||||
.pfnTCC1_3_Handler = (void*) TCC1_3_Handler, /* 95 TCC1_MC_2 */
|
||||
.pfnTCC1_4_Handler = (void*) TCC1_4_Handler, /* 96 TCC1_MC_3 */
|
||||
.pfnTCC2_0_Handler = (void*) TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
|
||||
.pfnTCC2_1_Handler = (void*) TCC2_1_Handler, /* 98 TCC2_MC_0 */
|
||||
.pfnTCC2_2_Handler = (void*) TCC2_2_Handler, /* 99 TCC2_MC_1 */
|
||||
.pfnTCC2_3_Handler = (void*) TCC2_3_Handler, /* 100 TCC2_MC_2 */
|
||||
#ifdef ID_TCC3
|
||||
.pfnTCC3_0_Handler = (void*) TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
|
||||
.pfnTCC3_1_Handler = (void*) TCC3_1_Handler, /* 102 TCC3_MC_0 */
|
||||
.pfnTCC3_2_Handler = (void*) TCC3_2_Handler, /* 103 TCC3_MC_1 */
|
||||
#else
|
||||
.pvReserved101 = (void*) (0UL), /* 101 Reserved */
|
||||
.pvReserved102 = (void*) (0UL), /* 102 Reserved */
|
||||
.pvReserved103 = (void*) (0UL), /* 103 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TCC4
|
||||
.pfnTCC4_0_Handler = (void*) TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
|
||||
.pfnTCC4_1_Handler = (void*) TCC4_1_Handler, /* 105 TCC4_MC_0 */
|
||||
.pfnTCC4_2_Handler = (void*) TCC4_2_Handler, /* 106 TCC4_MC_1 */
|
||||
#else
|
||||
.pvReserved104 = (void*) (0UL), /* 104 Reserved */
|
||||
.pvReserved105 = (void*) (0UL), /* 105 Reserved */
|
||||
.pvReserved106 = (void*) (0UL), /* 106 Reserved */
|
||||
#endif
|
||||
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter 0 */
|
||||
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter 1 */
|
||||
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter 2 */
|
||||
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter 3 */
|
||||
#ifdef ID_TC4
|
||||
.pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter 4 */
|
||||
#else
|
||||
.pvReserved111 = (void*) (0UL), /* 111 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC5
|
||||
.pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter 5 */
|
||||
#else
|
||||
.pvReserved112 = (void*) (0UL), /* 112 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC6
|
||||
.pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter 6 */
|
||||
#else
|
||||
.pvReserved113 = (void*) (0UL), /* 113 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC7
|
||||
.pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter 7 */
|
||||
#else
|
||||
.pvReserved114 = (void*) (0UL), /* 114 Reserved */
|
||||
#endif
|
||||
.pfnPDEC_0_Handler = (void*) PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
|
||||
.pfnPDEC_1_Handler = (void*) PDEC_1_Handler, /* 116 PDEC_MC_0 */
|
||||
.pfnPDEC_2_Handler = (void*) PDEC_2_Handler, /* 117 PDEC_MC_1 */
|
||||
.pfnADC0_0_Handler = (void*) ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */
|
||||
.pfnADC0_1_Handler = (void*) ADC0_1_Handler, /* 119 ADC0_RESRDY */
|
||||
.pfnADC1_0_Handler = (void*) ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */
|
||||
.pfnADC1_1_Handler = (void*) ADC1_1_Handler, /* 121 ADC1_RESRDY */
|
||||
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
|
||||
.pfnDAC_0_Handler = (void*) DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
|
||||
.pfnDAC_1_Handler = (void*) DAC_1_Handler, /* 124 DAC_EMPTY_0 */
|
||||
.pfnDAC_2_Handler = (void*) DAC_2_Handler, /* 125 DAC_EMPTY_1 */
|
||||
.pfnDAC_3_Handler = (void*) DAC_3_Handler, /* 126 DAC_RESRDY_0 */
|
||||
.pfnDAC_4_Handler = (void*) DAC_4_Handler, /* 127 DAC_RESRDY_1 */
|
||||
#ifdef ID_I2S
|
||||
.pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
|
||||
#else
|
||||
.pvReserved128 = (void*) (0UL), /* 128 Reserved */
|
||||
#endif
|
||||
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
|
||||
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
|
||||
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
|
||||
#ifdef ID_ICM
|
||||
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
|
||||
#else
|
||||
.pvReserved132 = (void*) (0UL), /* 132 Reserved */
|
||||
#endif
|
||||
#ifdef ID_PUKCC
|
||||
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
|
||||
#else
|
||||
.pvReserved133 = (void*) (0UL), /* 133 Reserved */
|
||||
#endif
|
||||
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
|
||||
#ifdef ID_SDHC0
|
||||
.pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */
|
||||
#else
|
||||
.pvReserved135 = (void*) (0UL), /* 135 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SDHC1
|
||||
.pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller 1 */
|
||||
#else
|
||||
.pvReserved136 = (void*) (0UL) /* 136 Reserved */
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
* To initialize the device, and call the main() routine.
|
||||
*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pSrc, *pDest;
|
||||
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext;
|
||||
pDest = &_srelocate;
|
||||
|
||||
if (pSrc != pDest) {
|
||||
for (; pDest < &_erelocate;) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the zero segment */
|
||||
for (pDest = &_szero; pDest < &_ezero;) {
|
||||
*pDest++ = 0;
|
||||
}
|
||||
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *) & _sfixed;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
#if __FPU_USED
|
||||
/* Enable FPU */
|
||||
SCB->CPACR |= (0xFu << 20);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Initialize the C library */
|
||||
__libc_init_array();
|
||||
|
||||
/* Branch to main function */
|
||||
main();
|
||||
|
||||
/* Infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same54.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (48000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement">
|
||||
<ProjectComponents>
|
||||
<ProjectComponent z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/">
|
||||
<CApiVersion></CApiVersion>
|
||||
<CBundle></CBundle>
|
||||
<CClass>CMSIS</CClass>
|
||||
<CGroup>CORE</CGroup>
|
||||
<CSub></CSub>
|
||||
<CVariant></CVariant>
|
||||
<CVendor>ARM</CVendor>
|
||||
<CVersion>5.1.2</CVersion>
|
||||
<DefaultRepoPath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs</DefaultRepoPath>
|
||||
<DependentComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays" />
|
||||
<Description></Description>
|
||||
<Files xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
|
||||
<d4p1:anyType i:type="FileInfo">
|
||||
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Documentation\Core\html\index.html</AbsolutePath>
|
||||
<Attribute></Attribute>
|
||||
<Category>doc</Category>
|
||||
<Condition></Condition>
|
||||
<FileContentHash i:nil="true" />
|
||||
<FileVersion></FileVersion>
|
||||
<Name>CMSIS/Documentation/Core/html/index.html</Name>
|
||||
<SelectString></SelectString>
|
||||
<SourcePath></SourcePath>
|
||||
</d4p1:anyType>
|
||||
<d4p1:anyType i:type="FileInfo">
|
||||
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include\</AbsolutePath>
|
||||
<Attribute></Attribute>
|
||||
<Category>include</Category>
|
||||
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|
||||
<FileContentHash i:nil="true" />
|
||||
<FileVersion></FileVersion>
|
||||
<Name>CMSIS/Core/Include/</Name>
|
||||
<SelectString></SelectString>
|
||||
<SourcePath></SourcePath>
|
||||
</d4p1:anyType>
|
||||
</Files>
|
||||
<PackName>CMSIS</PackName>
|
||||
<PackPath>C:/Program Files (x86)/Atmel/Studio/7.0/Packs/arm/CMSIS/5.4.0/ARM.CMSIS.pdsc</PackPath>
|
||||
<PackVersion>5.4.0</PackVersion>
|
||||
<PresentInProject>true</PresentInProject>
|
||||
<ReferenceConditionId>ARMv6_7_8-M Device</ReferenceConditionId>
|
||||
<RteComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
|
||||
<d4p1:string></d4p1:string>
|
||||
</RteComponents>
|
||||
<Status>Resolved</Status>
|
||||
<VersionMode>Fixed</VersionMode>
|
||||
<IsComponentInAtProject>true</IsComponentInAtProject>
|
||||
</ProjectComponent>
|
||||
<ProjectComponent z:Id="i2" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/">
|
||||
<CApiVersion></CApiVersion>
|
||||
<CBundle></CBundle>
|
||||
<CClass>Device</CClass>
|
||||
<CGroup>Startup</CGroup>
|
||||
<CSub></CSub>
|
||||
<CVariant></CVariant>
|
||||
<CVendor>Atmel</CVendor>
|
||||
<CVersion>1.1.0</CVersion>
|
||||
<DefaultRepoPath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs</DefaultRepoPath>
|
||||
<DependentComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
|
||||
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|
||||
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|
||||
<Description></Description>
|
||||
<Files xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
|
||||
<d4p1:anyType i:type="FileInfo">
|
||||
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\include</AbsolutePath>
|
||||
<Attribute></Attribute>
|
||||
<Category>include</Category>
|
||||
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|
||||
<FileContentHash i:nil="true" />
|
||||
<FileVersion></FileVersion>
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||||
<Name>include</Name>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
<FileContentHash>8A8bci0EePdi0b+8Lluv4A==</FileContentHash>
|
||||
<FileVersion></FileVersion>
|
||||
<Name>include/sam.h</Name>
|
||||
<SelectString></SelectString>
|
||||
<SourcePath></SourcePath>
|
||||
</d4p1:anyType>
|
||||
<d4p1:anyType i:type="FileInfo">
|
||||
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\templates\main.c</AbsolutePath>
|
||||
<Attribute>template</Attribute>
|
||||
<Category>source</Category>
|
||||
<Condition>C Exe</Condition>
|
||||
<FileContentHash>SJgCZe88oMZvgSxZz+Ly/A==</FileContentHash>
|
||||
<FileVersion></FileVersion>
|
||||
<Name>templates/main.c</Name>
|
||||
<SelectString>Main file (.c)</SelectString>
|
||||
<SourcePath></SourcePath>
|
||||
</d4p1:anyType>
|
||||
<d4p1:anyType i:type="FileInfo">
|
||||
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\templates\main.cpp</AbsolutePath>
|
||||
<Attribute>template</Attribute>
|
||||
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||||
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|
||||
<FileContentHash>Wwcf/gxegRQ10+cCzYcFIw==</FileContentHash>
|
||||
<FileVersion></FileVersion>
|
||||
<Name>templates/main.cpp</Name>
|
||||
<SelectString>Main file (.cpp)</SelectString>
|
||||
<SourcePath></SourcePath>
|
||||
</d4p1:anyType>
|
||||
<d4p1:anyType i:type="FileInfo">
|
||||
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\gcc\system_same54.c</AbsolutePath>
|
||||
<Attribute>config</Attribute>
|
||||
<Category>source</Category>
|
||||
<Condition>GCC Exe</Condition>
|
||||
<FileContentHash>13EKFJ9ZysfwBWEbJglN5Q==</FileContentHash>
|
||||
<FileVersion></FileVersion>
|
||||
<Name>gcc/system_same54.c</Name>
|
||||
<SelectString></SelectString>
|
||||
<SourcePath></SourcePath>
|
||||
</d4p1:anyType>
|
||||
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|
||||
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\gcc\gcc\startup_same54.c</AbsolutePath>
|
||||
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|
||||
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|
||||
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|
||||
<FileContentHash>hvyBThCuEBmDbH8Yhxa2Jw==</FileContentHash>
|
||||
<FileVersion></FileVersion>
|
||||
<Name>gcc/gcc/startup_same54.c</Name>
|
||||
<SelectString></SelectString>
|
||||
<SourcePath></SourcePath>
|
||||
</d4p1:anyType>
|
||||
<d4p1:anyType i:type="FileInfo">
|
||||
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\gcc\gcc\same54p20a_flash.ld</AbsolutePath>
|
||||
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|
||||
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|
||||
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|
||||
<FileContentHash>KxZPrZpayTyit24vDXKm8w==</FileContentHash>
|
||||
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|
||||
<Name>gcc/gcc/same54p20a_flash.ld</Name>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAME54_DFP\1.1.134\gcc\gcc\same54p20a_sram.ld</AbsolutePath>
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||||
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|
||||
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|
||||
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|
||||
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|
||||
<Name>gcc/gcc/same54p20a_sram.ld</Name>
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||||
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|
||||
<Compile Include="hal\include\hal_delay.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hal_evsys.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hal_gpio.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hal_init.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hal_io.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hal_sleep.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hal_spi_m_dma.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_cmcc.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_core.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_delay.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_dma.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_evsys.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_gpio.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_i2c_m_async.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_i2c_m_sync.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_i2c_s_async.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_i2c_s_sync.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_init.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_irq.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_missing_features.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_ramecc.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_reset.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_sleep.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_spi.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_spi_async.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_spi_dma.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_spi_m_async.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_spi_m_dma.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_spi_m_sync.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_spi_sync.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_spi_s_async.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_spi_s_sync.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_usart.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_usart_async.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_usart_sync.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\src\hal_atomic.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\src\hal_cache.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\src\hal_delay.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\src\hal_evsys.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\src\hal_gpio.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\src\hal_init.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\src\hal_io.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\src\hal_sleep.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\src\hal_spi_m_dma.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\include\compiler.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\include\err_codes.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\include\events.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\include\parts.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\include\utils.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\include\utils_assert.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\include\utils_event.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\include\utils_increment_macro.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\include\utils_list.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\include\utils_repeat_macro.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\src\utils_assert.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\src\utils_event.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\src\utils_list.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\src\utils_syscalls.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\cmcc\hpl_cmcc.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\core\hpl_core_m4.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\core\hpl_core_port.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\core\hpl_init.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\dmac\hpl_dmac.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\evsys\hpl_evsys.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\gclk\hpl_gclk.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\gclk\hpl_gclk_base.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\mclk\hpl_mclk.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\osc32kctrl\hpl_osc32kctrl.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\oscctrl\hpl_oscctrl.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\pm\hpl_pm.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\pm\hpl_pm_base.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\port\hpl_gpio_base.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\ramecc\hpl_ramecc.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\sercom\hpl_sercom.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\tc\tc_lite.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\tc\tc_lite.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_ac_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_adc_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_aes_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_can_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_ccl_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_cmcc_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_dac_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_dmac_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_dsu_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_eic_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_evsys_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_freqm_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_gclk_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_gmac_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_hmatrixb_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_i2s_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_icm_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_mclk_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_nvmctrl_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_osc32kctrl_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_oscctrl_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_pac_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_pcc_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_pdec_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_pm_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_port_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_qspi_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_ramecc_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_rstc_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_rtc_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_sdhc_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_sercom_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_supc_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_tcc_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_tc_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_trng_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_usb_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hri\hri_wdt_e54.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="interrupt_handlers.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="main.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="motor_params.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="utilities.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<Folder Include="Config\" />
|
||||
<Folder Include="Device_Startup\" />
|
||||
<Folder Include="examples\" />
|
||||
<Folder Include="hal\" />
|
||||
<Folder Include="hal\documentation\" />
|
||||
<Folder Include="hal\include\" />
|
||||
<Folder Include="hal\src\" />
|
||||
<Folder Include="hal\utils\" />
|
||||
<Folder Include="hal\utils\include\" />
|
||||
<Folder Include="hal\utils\src\" />
|
||||
<Folder Include="hpl\" />
|
||||
<Folder Include="hpl\cmcc\" />
|
||||
<Folder Include="hpl\core\" />
|
||||
<Folder Include="hpl\dmac\" />
|
||||
<Folder Include="hpl\doc_lite\" />
|
||||
<Folder Include="hpl\evsys\" />
|
||||
<Folder Include="hpl\gclk\" />
|
||||
<Folder Include="hpl\mclk\" />
|
||||
<Folder Include="hpl\osc32kctrl\" />
|
||||
<Folder Include="hpl\oscctrl\" />
|
||||
<Folder Include="hpl\pm\" />
|
||||
<Folder Include="hpl\port\" />
|
||||
<Folder Include="hpl\ramecc\" />
|
||||
<Folder Include="hpl\sercom\" />
|
||||
<Folder Include="ethercat" />
|
||||
<Folder Include="hpl\tc\" />
|
||||
<Folder Include="hri\" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<None Include="Device_Startup\same54p20a_flash.ld">
|
||||
<SubType>compile</SubType>
|
||||
</None>
|
||||
<None Include="Device_Startup\same54p20a_sram.ld">
|
||||
<SubType>compile</SubType>
|
||||
</None>
|
||||
<None Include="hal\documentation\evsys.rst">
|
||||
<SubType>compile</SubType>
|
||||
</None>
|
||||
<None Include="hal\documentation\spi_master_dma.rst">
|
||||
<SubType>compile</SubType>
|
||||
</None>
|
||||
<None Include="hpl\doc_lite\tc.rst">
|
||||
<SubType>compile</SubType>
|
||||
</None>
|
||||
</ItemGroup>
|
||||
<Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
|
||||
</Project>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,12 @@
|
|||
#include <atmel_start.h>
|
||||
|
||||
/**
|
||||
* Initializes MCU, drivers and middleware in the project
|
||||
**/
|
||||
void atmel_start_init(void)
|
||||
{
|
||||
system_init();
|
||||
/* Set floating point coprosessor access mode. */
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#ifndef ATMEL_START_H_INCLUDED
|
||||
#define ATMEL_START_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "driver_init.h"
|
||||
|
||||
/**
|
||||
* Initializes MCU, drivers and middleware in the project
|
||||
**/
|
||||
void atmel_start_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef ATMEL_START_PINS_H_INCLUDED
|
||||
#define ATMEL_START_PINS_H_INCLUDED
|
||||
|
||||
#include <hal_gpio.h>
|
||||
|
||||
// SAME54 has 14 pin functions
|
||||
|
||||
#define GPIO_PIN_FUNCTION_A 0
|
||||
#define GPIO_PIN_FUNCTION_B 1
|
||||
#define GPIO_PIN_FUNCTION_C 2
|
||||
#define GPIO_PIN_FUNCTION_D 3
|
||||
#define GPIO_PIN_FUNCTION_E 4
|
||||
#define GPIO_PIN_FUNCTION_F 5
|
||||
#define GPIO_PIN_FUNCTION_G 6
|
||||
#define GPIO_PIN_FUNCTION_H 7
|
||||
#define GPIO_PIN_FUNCTION_I 8
|
||||
#define GPIO_PIN_FUNCTION_J 9
|
||||
#define GPIO_PIN_FUNCTION_K 10
|
||||
#define GPIO_PIN_FUNCTION_L 11
|
||||
#define GPIO_PIN_FUNCTION_M 12
|
||||
#define GPIO_PIN_FUNCTION_N 13
|
||||
|
||||
#define M3_3 GPIO(GPIO_PORTA, 18)
|
||||
#define DRV_RESET GPIO(GPIO_PORTA, 27)
|
||||
#define ECAT_SPI_CS_PIN GPIO(GPIO_PORTB, 0)
|
||||
#define PB01 GPIO(GPIO_PORTB, 1)
|
||||
#define M3_4 GPIO(GPIO_PORTB, 14)
|
||||
#define M3_5 GPIO(GPIO_PORTB, 15)
|
||||
#define PB16 GPIO(GPIO_PORTB, 16)
|
||||
#define PB17 GPIO(GPIO_PORTB, 17)
|
||||
#define DRV_INC GPIO(GPIO_PORTB, 26)
|
||||
#define DRV_INB GPIO(GPIO_PORTB, 27)
|
||||
#define SPI_CS GPIO(GPIO_PORTB, 28)
|
||||
#define DRV_ENC GPIO(GPIO_PORTB, 29)
|
||||
#define SW0 GPIO(GPIO_PORTB, 31)
|
||||
#define DEBUG_1 GPIO(GPIO_PORTC, 1)
|
||||
#define DEBUG_3 GPIO(GPIO_PORTC, 2)
|
||||
#define DEBUG_2 GPIO(GPIO_PORTC, 3)
|
||||
#define LED0 GPIO(GPIO_PORTC, 18)
|
||||
#define DEBUG_4 GPIO(GPIO_PORTC, 30)
|
||||
#define DEBUG_5 GPIO(GPIO_PORTD, 11)
|
||||
|
||||
#endif // ATMEL_START_PINS_H_INCLUDED
|
||||
|
|
@ -0,0 +1,567 @@
|
|||
/*
|
||||
* bldc.c
|
||||
*
|
||||
* Created: 10/03/2021 14:53:19
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
|
||||
#include "bldc.h"
|
||||
#include "utilities.h"
|
||||
// ----------------------------------------------------------------------
|
||||
// header files
|
||||
// ----------------------------------------------------------------------
|
||||
#include "arm_math.h"
|
||||
#include "statemachine.h"
|
||||
#include "utilities.h"
|
||||
|
||||
|
||||
//// ------------------------------------------------------------------------------
|
||||
// Current Selection Based on Hall State
|
||||
// Direction":
|
||||
// CW -> Always positive current
|
||||
// CCW -> Always negative current
|
||||
void select_active_phase(BLDCMotor_t *Motor, const uint8_t hall_state)
|
||||
{
|
||||
volatile float32_t phase_current = 0;
|
||||
switch(hall_state)
|
||||
{
|
||||
case 0b001: case 0b011:
|
||||
phase_current = Motor->Iphase_pu.C;
|
||||
break;
|
||||
|
||||
case 0b010: case 0b110:
|
||||
phase_current = Motor->Iphase_pu.B;
|
||||
break;
|
||||
|
||||
case 0b100: case 0b101:
|
||||
phase_current = Motor->Iphase_pu.A;
|
||||
break;
|
||||
|
||||
default :
|
||||
//phase_current = 0; // Invalid hall code
|
||||
break;
|
||||
}
|
||||
|
||||
Motor->Iphase_pu.Bus = phase_current;
|
||||
}
|
||||
|
||||
void BldcInitStruct(BLDCMotor_t *motor)
|
||||
{
|
||||
// ----------------------------------------------------------------------
|
||||
// Initialize all voltage and current objects, variables and helpers:
|
||||
motor->motor_status.actualDirection = 0;
|
||||
motor->motor_setpoints.desiredDirection = 0;
|
||||
motor->motor_status.duty_cycle = 0;
|
||||
motor->motor_status.calc_rpm = 0;
|
||||
motor->motor_status.Num_Steps = 0;
|
||||
motor->motor_status.cur_comm_step = 0;
|
||||
motor->motor_status.currentHallPattern = 1;
|
||||
motor->motor_status.nextHallPattern = 3;
|
||||
motor->motor_setpoints.directionOffset = 0;
|
||||
|
||||
//motor->hall_state = 1;
|
||||
//motor->dir_hall_code = 1;
|
||||
|
||||
motor->Iphase_pu.A = 0;
|
||||
motor->Iphase_pu.B = 0;
|
||||
motor->Iphase_pu.C = 0;
|
||||
motor->Iphase_pu.Bus = 0;
|
||||
motor->Voffset_lsb.A = 0;
|
||||
motor->Voffset_lsb.B = 0;
|
||||
motor->timerflags.pwm_cycle_tic = false;
|
||||
motor->timerflags.control_loop_tic = false;
|
||||
motor->timerflags.motor_telemetry_flag = false;
|
||||
motor->timerflags.control_loop_tic = false;
|
||||
motor->timerflags.adc_readings_ready_tic = false;
|
||||
|
||||
motor->regulation_loop_count = 0;
|
||||
|
||||
|
||||
motor->VdcBus_pu = DEVICE_DC_VOLTAGE_V;
|
||||
motor->VoneByDcBus_pu = 1.0f/DEVICE_DC_VOLTAGE_V;
|
||||
motor->motor_commutation_Pattern = COMMUTATION_PATTERN_M1;
|
||||
|
||||
|
||||
motor->motor_setpoints.desired_torque = 0.0;
|
||||
motor->motor_setpoints.desired_speed = 0;
|
||||
motor->motor_setpoints.desired_position = 0;
|
||||
motor->motor_setpoints.max_current = 0.0;
|
||||
motor->motor_setpoints.max_torque = 0.0;
|
||||
motor->motor_setpoints.max_velocity = 0;
|
||||
|
||||
// ------------------------------------------------------------------------------
|
||||
// Function
|
||||
// ------------------------------------------------------------------------------
|
||||
//motor->ReadHall = HallFunc;
|
||||
|
||||
//// ------------------------------------------------------------------------------
|
||||
//// pi current control init
|
||||
PI_objectInit(&motor->controllers.Pi_Idc);
|
||||
float32_t motorLs_H = MOTOR_LQ_H * 2.0f;
|
||||
float32_t motorRs_OHM = MOTOR_RS_OHM * 2.0f;
|
||||
motor->controllers.Pi_Idc.Kp = PI_calcKp(motorLs_H, DEVICE_SHUNT_CURRENT_A, DEVICE_DC_VOLTAGE_V, DEVICE_ISR_PERIOD_Sec);
|
||||
//Pi_Idc.Ki = 0;
|
||||
motor->controllers.Pi_Idc.Ki = PI_calcKi(motorRs_OHM, motorLs_H, DEVICE_ISR_PERIOD_Sec);
|
||||
|
||||
//// ------------------------------------------------------------------------------
|
||||
//// pi velocity control init
|
||||
PID_objectInit(&motor->controllers.Pid_Speed);
|
||||
|
||||
/* V only Control Gains */
|
||||
//motor->controllers.Pid_Speed.Kp = 0.005f;
|
||||
//motor->controllers.Pid_Speed.Ki = 0.01f;
|
||||
|
||||
/* VI Control Gains */
|
||||
//motor->controllers.Pid_Speed.Kp = 0.0003f;
|
||||
//motor->controllers.Pid_Speed.Ki = 0.001f;
|
||||
motor->controllers.Pid_Speed.Kp = 0.0005f;
|
||||
motor->controllers.Pid_Speed.Ki = 0.0f;
|
||||
motor->controllers.Pid_Speed.Kd = 0.0001f;
|
||||
|
||||
//motor->controllers.Pid_Speed.Ki = 0.0001f;
|
||||
motor->controllers.Pid_Speed.OutMax_pu = (MOTOR_MAX_CURRENT_IDC_A);
|
||||
motor->controllers.Pid_Speed.OutMin_pu = -(MOTOR_MAX_CURRENT_IDC_A);
|
||||
|
||||
//// ------------------------------------------------------------------------------
|
||||
//// pi position control init
|
||||
PI_objectInit(&motor->controllers.Pi_Pos);
|
||||
motor->controllers.Pi_Pos.Kp = 40.0f;
|
||||
motor->controllers.Pi_Pos.Ki = 0.0f;
|
||||
|
||||
//motor->controllers.Pi_Pos.Ki = 0.00015f;
|
||||
//Pi_Pos.Kp = 500000;
|
||||
//Pi_Pos.Kp = 0;
|
||||
|
||||
motor->controllers.Pi_Pos.OutMax_pu = MOTOR_MAX_SPD_RPM;
|
||||
motor->controllers.Pi_Pos.OutMin_pu = -MOTOR_MAX_SPD_RPM;
|
||||
}
|
||||
|
||||
void BldcInitFunctions()
|
||||
{
|
||||
//Motor1.ReadHall = readM1Hall;
|
||||
//Motor2.ReadHall = readM2Hall;
|
||||
//Motor3.ReadHall = readM3Hall;
|
||||
//Motor1.DisableMotor = DisableM1GateDrivers;
|
||||
//Motor2.DisableMotor = DisableM2GateDrivers;
|
||||
//Motor3.DisableMotor = DisableM3GateDrivers;
|
||||
//Motor1.SetDutyCycle = SetM1DutyCycle;
|
||||
//Motor2.SetDutyCycle = SetM2DutyCycle;
|
||||
//Motor3.SetDutyCycle = SetM3DutyCycle;
|
||||
}
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Hall Reading Functions
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
inline uint8_t readM1Hall(void)
|
||||
{
|
||||
volatile uint8_t motor_read = 0;
|
||||
motor_read = (motor_read & HALL_A_MASK) | (uint8_t)((PORT->Group[HALL_A_GROUP].IN.reg & HALL_A_PORT)>>(HALL_A_LSR));
|
||||
motor_read = (motor_read & HALL_B_MASK) | (uint8_t)((PORT->Group[HALL_B_GROUP].IN.reg & HALL_B_PORT)>>(HALL_B_LSR));
|
||||
motor_read = (motor_read & HALL_C_MASK) | (uint8_t)((PORT->Group[HALL_C_GROUP].IN.reg & HALL_C_PORT)>>(HALL_C_LSR));
|
||||
|
||||
return motor_read;
|
||||
|
||||
//return ((gpio_get_pin_level(HALL_A_PIN) << 2)|
|
||||
//(gpio_get_pin_level(HALL_B_PIN) << 1)|
|
||||
//(gpio_get_pin_level(HALL_C_PIN) << 0));
|
||||
//
|
||||
//volatile uint8_t a = gpio_get_pin_level(HALL_A_PIN);
|
||||
//volatile uint8_t b = gpio_get_pin_level(HALL_B_PIN);
|
||||
//volatile uint8_t c = gpio_get_pin_level(HALL_C_PIN);
|
||||
//
|
||||
//return ((a << 2) |
|
||||
//(b << 1) |
|
||||
//(c << 0));
|
||||
}
|
||||
|
||||
inline uint8_t readM2Hall(void)
|
||||
{
|
||||
volatile uint8_t motor_read = 0;
|
||||
motor_read = (motor_read & HALL_A_MASK) | (uint8_t)((PORT->Group[HALL_A_GROUP].IN.reg & HALL_A_PORT)>>(HALL_A_LSR));
|
||||
motor_read = (motor_read & HALL_B_MASK) | (uint8_t)((PORT->Group[HALL_B_GROUP].IN.reg & HALL_B_PORT)>>(HALL_B_LSR));
|
||||
motor_read = (motor_read & HALL_C_MASK) | (uint8_t)((PORT->Group[HALL_C_GROUP].IN.reg & HALL_C_PORT)>>(HALL_C_LSR));
|
||||
|
||||
return motor_read;
|
||||
//
|
||||
//return ((gpio_get_pin_level(HALL_A_PIN) << 2)|
|
||||
//(gpio_get_pin_level(HALL_B_PIN) << 1)|
|
||||
//(gpio_get_pin_level(HALL_C_PIN) << 0));
|
||||
|
||||
|
||||
//volatile uint8_t a = gpio_get_pin_level(HALL_A_PIN);
|
||||
//volatile uint8_t b = gpio_get_pin_level(HALL_B_PIN);
|
||||
//volatile uint8_t c = gpio_get_pin_level(HALL_C_PIN);
|
||||
//
|
||||
//return ((a << 2) |
|
||||
//(b << 1) |
|
||||
//(c << 0));
|
||||
}
|
||||
|
||||
inline uint8_t readM3Hall(void)
|
||||
{
|
||||
volatile uint8_t motor_read = 0;
|
||||
motor_read = (motor_read & HALL_A_MASK) | (uint8_t)((PORT->Group[HALL_A_GROUP].IN.reg & HALL_A_PORT)>>(HALL_A_LSR));
|
||||
motor_read = (motor_read & HALL_B_MASK) | (uint8_t)((PORT->Group[HALL_B_GROUP].IN.reg & HALL_B_PORT)>>(HALL_B_LSR));
|
||||
motor_read = (motor_read & HALL_C_MASK) | (uint8_t)((PORT->Group[HALL_C_GROUP].IN.reg & HALL_C_PORT)>>(HALL_C_LSR));
|
||||
|
||||
return motor_read;
|
||||
//
|
||||
//return ((gpio_get_pin_level(HALL_A_PIN) << 2)|
|
||||
//(gpio_get_pin_level(HALL_B_PIN) << 1)|
|
||||
//(gpio_get_pin_level(HALL_C_PIN) << 0));
|
||||
|
||||
//volatile uint8_t a = gpio_get_pin_level(HALL_A_PIN);
|
||||
//volatile uint8_t b = gpio_get_pin_level(HALL_B_PIN);
|
||||
//volatile uint8_t c = gpio_get_pin_level(HALL_C_PIN);
|
||||
//
|
||||
//return ((a << 2) |
|
||||
//(b << 1) |
|
||||
//(c << 0));
|
||||
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Disable Functions
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
void DisableM1GateDrivers(BLDCMotor_t *motor)
|
||||
{
|
||||
hri_tcc_write_PATTBUF_reg(motor->hw, motor->motor_commutation_Pattern[0]);
|
||||
}
|
||||
|
||||
void DisableM2GateDrivers(BLDCMotor_t *motor)
|
||||
{
|
||||
hri_tcc_write_PATTBUF_reg(motor->hw, motor->motor_commutation_Pattern[0]);
|
||||
}
|
||||
|
||||
void DisableM3GateDrivers(BLDCMotor_t *motor)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
inline void SetM1DutyCycle(const uint16_t duty)
|
||||
{
|
||||
TCC1->CCBUF[1].reg = duty;
|
||||
}
|
||||
|
||||
inline void SetM2DutyCycle(const uint16_t duty)
|
||||
{
|
||||
TCC0->CCBUF[0].reg = duty;
|
||||
TCC0->CCBUF[1].reg = duty;
|
||||
TCC0->CCBUF[2].reg = duty;
|
||||
TCC0->CCBUF[3].reg = duty;
|
||||
}
|
||||
|
||||
inline void SetM3DutyCycle(const uint16_t duty)
|
||||
{
|
||||
TCC0->CCBUF[4].reg = duty;
|
||||
TCC0->CCBUF[5].reg = duty;
|
||||
TCC1->CCBUF[0].reg = duty;
|
||||
}
|
||||
|
||||
/**
|
||||
** ____|___TCC0_________ ||____TCC1_________|
|
||||
** W0 | M2_0 | CC0 || __M3_2__ | CC0 |
|
||||
** W1 | M2_1 | CC1 || - | CC1 |
|
||||
** W2 | M2_2 | CC2 || M1_0 | CC1 |
|
||||
** W3 | M2_3 | CC3 || M1_1 | CC1 |
|
||||
** W4 | __M3_0__ | CC4 || M1_2 | CC1 |
|
||||
** W5 | __M3_1__ | CC5 || M1_3 | CC1 |
|
||||
** W6 | M2_4 | CC0 || M1_4 | CC1 |
|
||||
** W7 | M2_5 | CC1 || M1_5 | CC1 |
|
||||
*/
|
||||
|
||||
void exec_commutation(void)
|
||||
{
|
||||
// ----------------------------------------------------------------------
|
||||
// Read Motor Hall Sensors
|
||||
// ----------------------------------------------------------------------
|
||||
//tic_port(DEBUG_2_PORT);
|
||||
Motor1.motor_status.currentHallPattern = readM1Hall();
|
||||
Motor2.motor_status.currentHallPattern = readM2Hall();
|
||||
//toc_port(DEBUG_2_PORT);
|
||||
//Motor2.motor_status.currentHallPattern = Motor1.ReadHall();
|
||||
//Motor3.motor_status.currentHallPattern = Motor1.ReadHall();
|
||||
//toc_port(DEBUG_3_PORT);
|
||||
// ----------------------------------------------------------------------
|
||||
// Multi Motor Register Masking
|
||||
// ----------------------------------------------------------------------
|
||||
//tic_port(DEBUG_2_PORT);
|
||||
volatile uint16_t temp_M1 = COMMUTATION_PATTERN_M1[Motor1.motor_status.currentHallPattern + Motor1.motor_setpoints.directionOffset];
|
||||
|
||||
volatile uint16_t temp_M2 = COMMUTATION_PATTERN_M2[Motor2.motor_status.currentHallPattern + Motor2.motor_setpoints.directionOffset];
|
||||
//volatile uint16_t temp_M3_tcc1_des = COMMUTATION_PATTERN_M1[Motor3.motor_status.currentHallPattern + Motor3.motor_setpoints.directionOffset] & m3_TCC1_mask;
|
||||
//volatile uint16_t temp_M3_tcc0_des = COMMUTATION_PATTERN_M2[Motor3.motor_status.currentHallPattern + Motor3.motor_setpoints.directionOffset] & m3_TCC0_mask;
|
||||
/* Zero target bits */
|
||||
//temp_M1 &= m3_TCC1_inv_mask;
|
||||
//temp_M2 &= m3_TCC0_inv_mask;
|
||||
/* Set Desired bits */
|
||||
//temp_M1 |= temp_M3_tcc1_des;
|
||||
//temp_M2 |= temp_M3_tcc0_des;
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Set Pattern Buffers
|
||||
// ----------------------------------------------------------------------
|
||||
TCC0->PATTBUF.reg = (uint16_t)temp_M2;
|
||||
TCC1->PATTBUF.reg = (uint16_t)temp_M1;
|
||||
|
||||
//toc_port(DEBUG_2_PORT);
|
||||
//toc_port(DEBUG_2_PORT);
|
||||
// ----------------------------------------------------------------------
|
||||
// Set Remaining GPIO lines responsible for M3 Commutation
|
||||
// ----------------------------------------------------------------------
|
||||
///* GPIO En Pin Setting for M3 */
|
||||
//switch(Motor3.motor_status.currentHallPattern + Motor3.motor_setpoints.directionOffset)
|
||||
//{
|
||||
//// REG_PORT_OUTSET0 = Port A
|
||||
//// REG_PORT_OUTSET1 = Port B
|
||||
//case 1: case 6: case 9: case 14:
|
||||
//REG_PORT_OUTCLR0 = (1 << GPIO_PIN(M3_3));
|
||||
//REG_PORT_OUTSET1 = (1 << GPIO_PIN(M3_4))|(1 << GPIO_PIN(M3_5));
|
||||
//break;
|
||||
//case 2: case 5: case 10: case 13:
|
||||
//REG_PORT_OUTSET0 = (1 << GPIO_PIN(M3_3));
|
||||
//REG_PORT_OUTSET1 = (1 << GPIO_PIN(M3_4));
|
||||
//REG_PORT_OUTCLR1 = (1 << GPIO_PIN(M3_5));
|
||||
//break;
|
||||
//case 3: case 4: case 11: case 12:
|
||||
//REG_PORT_OUTSET0 = (1 << GPIO_PIN(M3_3));
|
||||
//REG_PORT_OUTCLR1 = (1 << GPIO_PIN(M3_4));
|
||||
//REG_PORT_OUTSET1 = (1 << GPIO_PIN(M3_5));
|
||||
//break;
|
||||
//default:
|
||||
///*hall error - should not get here */
|
||||
//break;
|
||||
//}
|
||||
|
||||
|
||||
// TCC1->PATTBUF.reg = COMMUTATION_PATTERN_M1[(Motor1.motor_status.currentHallPattern +
|
||||
// Motor1.motor_setpoints.directionOffset)];
|
||||
// ----------------------------------------------------------------------
|
||||
// Set Calculated Duty Cycles
|
||||
// ----------------------------------------------------------------------
|
||||
//tic_port(DEBUG_2_PORT);
|
||||
//Motor1.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle);
|
||||
SetM1DutyCycle(Motor1.motor_status.duty_cycle);
|
||||
SetM2DutyCycle(Motor1.motor_status.duty_cycle);
|
||||
//Motor2.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle);
|
||||
//Motor3.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle);
|
||||
//tic_port(DEBUG_2_PORT);
|
||||
//tic_port(DEBUG_2_PORT);
|
||||
Motor1.motor_status.cur_comm_step = MOTOR_COMMUTATION_STEPS[Motor1.motor_status.currentHallPattern];
|
||||
volatile int8_t step_change1 = Motor1.motor_status.cur_comm_step - Motor1.motor_status.prev_comm_step;
|
||||
|
||||
switch(step_change1)
|
||||
{
|
||||
case 1: case -5:
|
||||
Motor1.motor_status.Num_Steps = Motor1.motor_status.Num_Steps+1;
|
||||
Motor1.motor_status.actualDirection = CW;
|
||||
//Motor1.motor_setpoints.directionOffset = DIRECTION_CW_OFFSET;
|
||||
break;
|
||||
case -1: case 5:
|
||||
Motor1.motor_status.Num_Steps = Motor1.motor_status.Num_Steps-1;
|
||||
Motor1.motor_status.actualDirection = CCW;
|
||||
//Motor1.motor_setpoints.directionOffset = DIRECTION_CCW_OFFSET;
|
||||
break;
|
||||
default:
|
||||
// do nothing
|
||||
break;
|
||||
}
|
||||
Motor1.motor_status.prev_comm_step = Motor1.motor_status.cur_comm_step;
|
||||
//toc_port(DEBUG_2_PORT);
|
||||
|
||||
Motor2.motor_status.cur_comm_step = MOTOR_COMMUTATION_STEPS[Motor1.motor_status.currentHallPattern];
|
||||
volatile int8_t step_change2 = Motor2.motor_status.cur_comm_step - Motor2.motor_status.prev_comm_step;
|
||||
|
||||
switch(step_change2)
|
||||
{
|
||||
case 1: case -5:
|
||||
Motor2.motor_status.Num_Steps = Motor2.motor_status.Num_Steps+1;
|
||||
Motor2.motor_status.actualDirection = CW;
|
||||
//Motor2.motor_setpoints.directionOffset = DIRECTION_CW_OFFSET;
|
||||
break;
|
||||
case -1: case 5:
|
||||
Motor2.motor_status.Num_Steps = Motor2.motor_status.Num_Steps-1;
|
||||
Motor2.motor_status.actualDirection = CCW;
|
||||
//Motor1.motor_setpoints.directionOffset = DIRECTION_CCW_OFFSET;
|
||||
break;
|
||||
default:
|
||||
// do nothing
|
||||
break;
|
||||
}
|
||||
|
||||
//toc_port(DEBUG_2_PORT);
|
||||
//
|
||||
//Motor3.motor_status.cur_comm_step = MOTOR_COMMUTATION_STEPS[Motor1.motor_status.currentHallPattern];
|
||||
//volatile int8_t step_change3 = Motor3.motor_status.cur_comm_step - Motor3.motor_status.prev_comm_step;
|
||||
//
|
||||
//switch(step_change3)
|
||||
//{
|
||||
//case 1: case -5:
|
||||
//Motor3.motor_status.Num_Steps = Motor3.motor_status.Num_Steps+1;
|
||||
//Motor3.motor_status.actualDirection = CW;
|
||||
////Motor3.motor_setpoints.directionOffset = DIRECTION_CW_OFFSET;
|
||||
//break;
|
||||
//case -1: case 5:
|
||||
//Motor3.motor_status.Num_Steps = Motor3.motor_status.Num_Steps-1;
|
||||
//Motor3.motor_status.actualDirection = CCW;
|
||||
////Motor1.motor_setpoints.directionOffset = DIRECTION_CCW_OFFSET;
|
||||
//break;
|
||||
//default:
|
||||
//// do nothing
|
||||
//break;
|
||||
//}
|
||||
|
||||
//calculate_motor_speed();
|
||||
//toc(DEBUG_3);
|
||||
//toc(DEBUG_4);
|
||||
//CRITICAL_SECTION_LEAVE();
|
||||
}
|
||||
|
||||
void calculate_motor_speed(void)
|
||||
{
|
||||
//tic_port(DEBUG_2_PORT);
|
||||
volatile uint32_t temp_rpm = 0;
|
||||
hri_tccount32_read_CC_reg(TC0, 0); /* Read CC0 but throw away)*/
|
||||
volatile uint32_t period_after_capture = hri_tccount32_read_CC_reg(TC0, 1);
|
||||
if((period_after_capture > UINT32_MAX)|| (period_after_capture > 10712046)) {
|
||||
Motor1.motor_status.calc_rpm = 0;
|
||||
} else {
|
||||
//uint32_t test = (SPEEDFACTOR, period_after_capture);
|
||||
//temp_rpm = SPEEDFACTOR / period_after_capture;
|
||||
//tic_port(DEBUG_3_PORT);
|
||||
temp_rpm = HZ_TO_RPM / (period_after_capture*MOTOR_COMUTATION_STATES);
|
||||
//temp_rpm = HZ_TO_RPM * period_after_capture;
|
||||
//toc_port(DEBUG_3_PORT);
|
||||
}
|
||||
|
||||
if(Motor1.motor_status.actualDirection == CCW) /* Changed from CCW */
|
||||
{
|
||||
//*motor_speed = -1* Motor1.calc_rpm;
|
||||
temp_rpm = -1 * temp_rpm;
|
||||
} else {
|
||||
//*motor_speed = Motor1.calc_rpm;
|
||||
temp_rpm = temp_rpm;
|
||||
}
|
||||
|
||||
Motor1.motor_status.calc_rpm = (int16_t)temp_rpm;
|
||||
//toc_port(DEBUG_2_PORT);
|
||||
|
||||
//#ifdef AVERAGE_SPEED_MEASURE
|
||||
//// To avoid noise an average is realized on 8 samples
|
||||
//speed_average += temp_rpm;
|
||||
//if(count >= n_SAMPLE)
|
||||
//{
|
||||
//count = 1;
|
||||
//Motor1.motor_status.calc_rpm = (speed_average >> 3); // divide by 32
|
||||
////Motor1.motor_status.calc_rpm = (speed_average); // divide by 32
|
||||
//speed_average = 0;
|
||||
////*Spare_byte1 = motorState.actualDirection;
|
||||
//if(Motor1.motor_status.actualDirection == CCW) /* Changed from CCW */
|
||||
//{
|
||||
////*motor_speed = -1* Motor1.calc_rpm;
|
||||
//Motor1.motor_status.calc_rpm = -1* Motor1.motor_status.calc_rpm;
|
||||
//} else {
|
||||
////*motor_speed = Motor1.calc_rpm;
|
||||
//Motor1.motor_status.calc_rpm = Motor1.motor_status.calc_rpm;
|
||||
//}
|
||||
//return;
|
||||
//}
|
||||
//else count++;
|
||||
//#else
|
||||
//Motor1.motor_status.calc_rpm = (int16_t)temp_rpm;
|
||||
//#endif
|
||||
//toc_port(DEBUG_2_PORT);
|
||||
}
|
||||
|
||||
void DisableMotor(BLDCMotor_t *motor)
|
||||
{
|
||||
hri_tcc_write_PATTBUF_reg(motor->hw, motor->motor_commutation_Pattern[0]);
|
||||
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// pi current control
|
||||
//------------------------------------------------------------------------------
|
||||
void BLDC_runCurrentCntl(BLDCMotor_t *motor, const float32_t curfbk, const float32_t curRef)
|
||||
{
|
||||
|
||||
motor->controllers.Pi_Idc.Fbk_pu = f_clamp(curfbk, -DEVICE_SHUNT_CURRENT_A, DEVICE_SHUNT_CURRENT_A); // Clamped to max current sensor readingspeedfbk;
|
||||
motor->controllers.Pi_Idc.Ref_pu = f_clamp(curRef, -MOTOR_MAX_CURRENT_IDC_A, MOTOR_MAX_CURRENT_IDC_A); // Clamp desired to Motor Max Current i_ref_clamped;
|
||||
|
||||
//*Spare_1 = (int16_t)(motor->controllers.Pi_Idc.Ref_pu * 1000); // Send Req Current to TC
|
||||
|
||||
motor->controllers.Pi_Idc.OutMax_pu = motor->VdcBus_pu;
|
||||
motor->controllers.Pi_Idc.OutMin_pu = -motor->VdcBus_pu;
|
||||
PI_run_series(&motor->controllers.Pi_Idc);
|
||||
|
||||
if(motor->controllers.Pi_Idc.Out_pu > 0) {
|
||||
motor->motor_setpoints.desiredDirection = 0;
|
||||
motor->motor_setpoints.directionOffset = 0;
|
||||
} else {
|
||||
motor->motor_setpoints.desiredDirection = 1;
|
||||
motor->motor_setpoints.directionOffset = 8;
|
||||
}
|
||||
|
||||
volatile float32_t duty_pu = f_abs((motor->controllers.Pi_Idc.Out_pu * motor->VoneByDcBus_pu));
|
||||
motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
|
||||
// Remove Low duty cycle values
|
||||
//if(duty_cycle < 80.0) motor->duty_cycle = (uint16_t)0;
|
||||
//else motor->duty_cycle = (uint16_t)duty_cycle;
|
||||
|
||||
}
|
||||
|
||||
//// ------------------------------------------------------------------------------
|
||||
// Speed Control: Input in RPM units (int16_t)
|
||||
//------------------------------------------------------------------------------
|
||||
void BLDC_runSpeedCntl(BLDCMotor_t *motor, const float32_t speedfbk, const float32_t speedRef)
|
||||
{
|
||||
//tic_port(DEBUG_3_PORT);
|
||||
motor->controllers.Pid_Speed.Fbk_pu = speedfbk;
|
||||
motor->controllers.Pid_Speed.Ref_pu = f_clamp(speedRef, -MOTOR_MAX_SPD_RPM, MOTOR_MAX_SPD_RPM); // Convert Speed Ref to Q16 Format
|
||||
|
||||
if (applicationStatus.currentstate == MOTOR_V_CTRL_STATE)
|
||||
{
|
||||
/* Output Pu in Volts (PWM %) */
|
||||
motor->controllers.Pid_Speed.OutMax_pu = motor->VdcBus_pu;
|
||||
motor->controllers.Pid_Speed.OutMin_pu = -motor->VdcBus_pu;
|
||||
|
||||
PID_run_parallel(&motor->controllers.Pid_Speed);
|
||||
|
||||
if(motor->controllers.Pid_Speed.Out_pu > 0) {
|
||||
motor->motor_setpoints.desiredDirection = 0;
|
||||
motor->motor_setpoints.directionOffset = 0;
|
||||
} else {
|
||||
motor->motor_setpoints.desiredDirection = 1;
|
||||
motor->motor_setpoints.directionOffset = 8;
|
||||
}
|
||||
/* Process unit is Volts */
|
||||
volatile float32_t duty_pu = f_abs((motor->controllers.Pid_Speed.Out_pu * motor->VoneByDcBus_pu));
|
||||
volatile duty_cycle = f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
|
||||
motor->motor_status.duty_cycle = (uint16_t)duty_cycle;
|
||||
} else {
|
||||
/* Pu in Current (Amps) */
|
||||
motor->controllers.Pid_Speed.OutMax_pu = (MOTOR_MAX_CURRENT_IDC_A);
|
||||
motor->controllers.Pid_Speed.OutMin_pu = -(MOTOR_MAX_CURRENT_IDC_A);
|
||||
PID_run_parallel(&motor->controllers.Pid_Speed);
|
||||
motor->controllers.Pi_Idc.Ref_pu = motor->controllers.Pid_Speed.Out_pu;
|
||||
}
|
||||
//toc_port(DEBUG_3_PORT);
|
||||
}
|
||||
|
||||
//// ------------------------------------------------------------------------------
|
||||
// Position Control:Input in Hall step units (int16_t)
|
||||
//------------------------------------------------------------------------------
|
||||
void BLDC_runPosCntl(BLDCMotor_t *motor, const int16_t posfbk, const int16_t posRef)
|
||||
{
|
||||
/* Output Pu in RPM */
|
||||
motor->controllers.Pi_Pos.OutMax_pu = MOTOR_MAX_SPD_RPM;
|
||||
motor->controllers.Pi_Pos.OutMin_pu = -MOTOR_MAX_SPD_RPM;
|
||||
motor->controllers.Pi_Pos.Fbk_pu = posfbk;
|
||||
motor->controllers.Pi_Pos.Ref_pu = posRef;
|
||||
PI_run_series(&motor->controllers.Pi_Pos);
|
||||
motor->controllers.Pid_Speed.Ref_pu = motor->controllers.Pi_Pos.Out_pu;
|
||||
}
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
/*
|
||||
* bldc.h
|
||||
*
|
||||
* Created: 10/03/2021 14:38:14
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
#ifndef BLDC_H_
|
||||
#define BLDC_H_
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// header files
|
||||
// ----------------------------------------------------------------------
|
||||
//#include "arm_math.h"
|
||||
#include "atmel_start.h"
|
||||
#include "control.h"
|
||||
#include "motor_params.h"
|
||||
|
||||
/* if the Hall sensor reads 0x0 or 0x7 that means either one of the hall sensor is damaged or disconnected*/
|
||||
#define INVALID_HALL_0 (0U)
|
||||
#define INVALID_HALL_7 (7U)
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// ADC Parameters
|
||||
// ----------------------------------------------------------------------
|
||||
#define ADC_VOLTAGE_REFERENCE (3.3f)
|
||||
#define ADC_RESOLUTION (12)
|
||||
#define ADC_MAX_COUNTS (1<<ADC_RESOLUTION)
|
||||
#define ADC_LSB_SIZE (ADC_VOLTAGE_REFERENCE/ADC_MAX_COUNTS)
|
||||
#define LSB_TO_PU (ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY)
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Define the control and PWM frequencies:
|
||||
// ----------------------------------------------------------------------
|
||||
// 16kHz is the maximum frequency according to the calculation duration in the mode run and spin.
|
||||
#define DEVICE_MCU_FREQUENCY_Hz (120000000U)
|
||||
#define DEVICE_SPEEDTC_DIV (4U)
|
||||
#define DEVICE_SPEEDTC_FREQUENCY_Hz (DEVICE_MCU_FREQUENCY_Hz/DEVICE_SPEEDTC_DIV)
|
||||
#define DEVICE_PWM_FREQUENCY_kHz (25.0f)
|
||||
#define DEVICE_ISR_FREQUENCY_kHz DEVICE_PWM_FREQUENCY_kHz
|
||||
#define DEVICE_ISR_PERIOD_Sec (0.001f/DEVICE_ISR_FREQUENCY_kHz)
|
||||
#define HZ_TO_RPM (DEVICE_SPEEDTC_FREQUENCY_Hz * 60)
|
||||
//#define HZ_TO_RPM MOTOR_COMUTATION_STATES/(DEVICE_SPEEDTC_FREQUENCY_Hz * 60)
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Define the device quantities (voltage, current, speed)
|
||||
// ----------------------------------------------------------------------
|
||||
#define DEVICE_DC_VOLTAGE_V 24.0f // max. ADC bus voltage(PEAK) [V]
|
||||
#define DEVICE_SHUNT_CURRENT_A 2.5f // phase current(PEAK) [A]
|
||||
#define CURRENT_SENSOR_SENSITIVITY 0.4f //V/A
|
||||
#define ONEON_CURRENT_SENSOR_SENSITIVITY 2.5f //V/A
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Type Definitions
|
||||
// ----------------------------------------------------------------------
|
||||
volatile typedef struct
|
||||
{
|
||||
volatile float32_t A; // Phase A
|
||||
volatile float32_t B; // Phase B
|
||||
volatile float32_t C; // Phase C
|
||||
volatile float32_t Bus; // Currently Active Phase Current
|
||||
} MOTOR_3PHASES_t;
|
||||
|
||||
volatile typedef struct
|
||||
{
|
||||
volatile int16_t A; // Phase A measured offset
|
||||
volatile int16_t B; // Phase B measured offset
|
||||
} MOTOR_phase_offset_t;
|
||||
|
||||
volatile typedef struct timerflags
|
||||
{
|
||||
volatile bool pwm_cycle_tic;
|
||||
volatile bool current_loop_tic;
|
||||
volatile bool control_loop_tic;
|
||||
volatile bool adc_readings_ready_tic;
|
||||
volatile bool motor_telemetry_flag;
|
||||
} TIMERflags_t;
|
||||
|
||||
volatile typedef struct
|
||||
{
|
||||
volatile PI_t Pi_Idc;
|
||||
volatile PID_t Pid_Speed;
|
||||
volatile PI_t Pi_Pos;
|
||||
} MOTOR_Control_Structs;
|
||||
|
||||
volatile typedef struct
|
||||
{
|
||||
volatile uint8_t desiredDirection; //! The desired direction of rotation.
|
||||
volatile uint8_t directionOffset;
|
||||
volatile float32_t desired_torque;
|
||||
volatile int16_t desired_speed;
|
||||
volatile int16_t desired_position;
|
||||
volatile float32_t max_torque;
|
||||
volatile float32_t max_current;
|
||||
volatile int16_t max_velocity;
|
||||
} MOTOR_Setpoints;
|
||||
|
||||
volatile typedef struct
|
||||
{
|
||||
volatile uint8_t actualDirection; //! The actual direction of rotation.
|
||||
volatile uint16_t duty_cycle;
|
||||
volatile float32_t calc_rpm;
|
||||
volatile int32_t Num_Steps;
|
||||
/* Hall States */
|
||||
volatile uint8_t prevHallPattern;
|
||||
volatile uint8_t currentHallPattern;
|
||||
volatile uint8_t nextHallPattern;
|
||||
/* Commutation State */
|
||||
volatile uint8_t cur_comm_step;
|
||||
volatile uint8_t prev_comm_step;
|
||||
} MOTOR_Status;
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Function Pointers
|
||||
// ----------------------------------------------------------------------
|
||||
typedef uint8_t (*ReadHallFunc)(void);
|
||||
typedef void (*DisableMotorFunc)(void);
|
||||
typedef void (*SetMotorDutyCycle)(uint16_t);
|
||||
|
||||
volatile typedef struct BLDCmotor
|
||||
{
|
||||
/* Hardware */
|
||||
const Tcc *hw;
|
||||
const uint16_t *motor_commutation_Pattern;
|
||||
uint32_t current_sensor_channels[2];
|
||||
/* Status */
|
||||
MOTOR_Status motor_status;
|
||||
/* Measured Values */
|
||||
volatile MOTOR_3PHASES_t Iphase_pu;
|
||||
volatile MOTOR_phase_offset_t Voffset_lsb;
|
||||
volatile float32_t VdcBus_pu;
|
||||
volatile float32_t VoneByDcBus_pu;
|
||||
/* Motor Flags */
|
||||
volatile TIMERflags_t timerflags;
|
||||
volatile uint8_t regulation_loop_count;
|
||||
/* Controllers */
|
||||
volatile MOTOR_Control_Structs controllers;
|
||||
/* Setpoints */
|
||||
volatile MOTOR_Setpoints motor_setpoints;
|
||||
/* Functions */
|
||||
ReadHallFunc ReadHall;
|
||||
DisableMotorFunc DisableMotor;
|
||||
SetMotorDutyCycle SetDutyCycle;
|
||||
} BLDCMotor_t;
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// global variables
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
static const uint8_t HALL_PATTERN_ARRAY[16] = {0, 5, 3, 1, 6, 4, 2, 0, 0, 3, 6, 2, 5, 1, 4, 0 };
|
||||
static const uint8_t MOTOR_COMMUTATION_STEPS[8] = {9, 1, 3, 2, 5, 6, 4, 9};
|
||||
|
||||
volatile BLDCMotor_t Motor1;
|
||||
volatile BLDCMotor_t Motor2;
|
||||
volatile BLDCMotor_t Motor3;
|
||||
|
||||
|
||||
//static uint32_t adc_seq_regs[6] = {0x1802, 0x1803, 0x1802, 0x1803, 0x1802, 0x1803};
|
||||
static uint32_t adc_seq_regs[4] = {0x1802, 0x1803, 0x1802, 0x1803};
|
||||
static volatile uint16_t adc_res[4] = {0};
|
||||
static volatile bool adc_dma_done = 0;
|
||||
|
||||
struct _dma_resource *adc_sram_dma_resource;
|
||||
struct _dma_resource *adc_dmac_sequence_resource;
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// functions
|
||||
// ----------------------------------------------------------------------
|
||||
void BldcInitStruct(BLDCMotor_t *motor);
|
||||
void BldcInitFunctions(void);
|
||||
|
||||
|
||||
|
||||
void select_active_phase(BLDCMotor_t *Motor, const uint8_t hall_state);
|
||||
void read_zero_current_offset_value(BLDCMotor_t *Motor);
|
||||
//int32_t adc_sync_read_channel(struct adc_async_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, const uint16_t length);
|
||||
//static uint16_t adc_read(struct adc_async_descriptor *const descr, const uint8_t channel);
|
||||
inline void exec_commutation(void);
|
||||
uint8_t get_dir_hall_code(void);
|
||||
uint8_t get_hall_state(void);
|
||||
|
||||
uint8_t HALLPatternGet(void);
|
||||
uint8_t PDEC_HALLPatternGet(void);
|
||||
void calculate_motor_speed(void);
|
||||
void DisableMotor(BLDCMotor_t *motor);
|
||||
void BLDC_runSpeedCntl(BLDCMotor_t *motor, const float32_t speedfbk, const float32_t speedRef);
|
||||
void BLDC_runCurrentCntl(BLDCMotor_t *motor, const float32_t curfbk, const float32_t curRef);
|
||||
void BLDC_runPosCntl(BLDCMotor_t *motor, int16_t posfbk, int16_t posRef);
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Functions used with function pointers
|
||||
// ----------------------------------------------------------------------
|
||||
uint8_t readM1Hall(void);
|
||||
uint8_t readM2Hall(void);
|
||||
uint8_t readM3Hall(void);
|
||||
void DisableM1GateDrivers(BLDCMotor_t *motor);
|
||||
void DisableM2GateDrivers(BLDCMotor_t *motor);
|
||||
void DisableM3GateDrivers(BLDCMotor_t *motor);
|
||||
void SetM1DutyCycle(const uint16_t duty);
|
||||
void SetM2DutyCycle(const uint16_t duty);
|
||||
void SetM3DutyCycle(const uint16_t duty);
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// all controller objects, variables and helpers:
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
//Motor2.ReadHall = readM2Hall;
|
||||
//Motor3.ReadHall = readM3Hall;
|
||||
|
||||
|
||||
|
||||
#endif /* BLDC_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* communication.h
|
||||
*
|
||||
* Created: 10/03/2021 13:07:51
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
|
||||
#ifndef COMMUNICATION_H_
|
||||
#define COMMUNICATION_H_
|
||||
|
||||
#include "ethercat_e54.h"
|
||||
|
||||
//Write To Ecat Total Bytes (38 bytes)
|
||||
//write (2 Bytes)
|
||||
volatile uint8_t *status =&ram_buffer[ram_wr_start];
|
||||
volatile uint8_t *state =(((uint8_t *)&ram_buffer[ram_wr_start])+1);
|
||||
//Joint (10 Bytes)
|
||||
volatile int16_t *joint_rel_position =&ram_buffer[ram_wr_start+1];
|
||||
volatile int16_t *joint_revolution =&ram_buffer[ram_wr_start+2];
|
||||
volatile int16_t *joint_abs_position =&ram_buffer[ram_wr_start+3];
|
||||
volatile int16_t *joint_speed =&ram_buffer[ram_wr_start+4];
|
||||
volatile int16_t *joint_torque =&ram_buffer[ram_wr_start+5];
|
||||
// Motor (20+1+1+4) = 26
|
||||
volatile int16_t *motor_rel_revolutions=&ram_buffer[ram_wr_start+6];
|
||||
volatile int16_t *motor_rel_position =&ram_buffer[ram_wr_start+7];
|
||||
volatile int16_t *motor_abs_position =&ram_buffer[ram_wr_start+8];
|
||||
volatile int16_t *motor_dutyCycle =&ram_buffer[ram_wr_start+9];
|
||||
volatile int16_t *motor_speed =&ram_buffer[ram_wr_start+10];
|
||||
volatile int16_t *motor_torque =&ram_buffer[ram_wr_start+11];
|
||||
volatile int16_t *motor_currentPHA =&ram_buffer[ram_wr_start+12];
|
||||
volatile int16_t *motor_currentPHB =&ram_buffer[ram_wr_start+13];
|
||||
volatile int16_t *motor_currentPHC =&ram_buffer[ram_wr_start+14];
|
||||
volatile int16_t *motor_currentBUS =&ram_buffer[ram_wr_start+15];
|
||||
volatile uint8_t *hall_state =&ram_buffer[ram_wr_start+16];
|
||||
volatile uint8_t *Spare_byte1 =(((uint8_t *)&ram_buffer[ram_wr_start+16])+1);
|
||||
volatile int16_t *Spare_1 =&ram_buffer[ram_wr_start+17];
|
||||
volatile int16_t *Spare_2 =&ram_buffer[ram_wr_start+18];
|
||||
|
||||
//Read From Ecat Total (35 Bytes)
|
||||
// (1 Byte)
|
||||
volatile uint8_t *control_mode =&ram_buffer[ram_rd_start];
|
||||
volatile uint8_t *control_set =(((uint8_t *)&ram_buffer[ram_rd_start])+1);
|
||||
// (34 Byte)
|
||||
volatile int16_t *desired_position =&ram_buffer[ram_rd_start+1];
|
||||
volatile int16_t *desired_speed =&ram_buffer[ram_rd_start+2];
|
||||
volatile int16_t *desired_torque =&ram_buffer[ram_rd_start+3];
|
||||
volatile int16_t *i_kp =&ram_buffer[ram_rd_start+4];
|
||||
volatile int16_t *i_ki =&ram_buffer[ram_rd_start+5];
|
||||
volatile int16_t *v_kp =&ram_buffer[ram_rd_start+6];
|
||||
volatile int16_t *v_kd =&ram_buffer[ram_rd_start+7];
|
||||
volatile int16_t *p_kp =&ram_buffer[ram_rd_start+8];
|
||||
volatile int16_t *p_ki =&ram_buffer[ram_rd_start+9];
|
||||
volatile uint16_t *ReductionRatio =&ram_buffer[ram_rd_start+10];
|
||||
volatile int16_t *max_torque =&ram_buffer[ram_rd_start+11];
|
||||
volatile int16_t *max_current =&ram_buffer[ram_rd_start+12];
|
||||
volatile int16_t *max_velocity =&ram_buffer[ram_rd_start+13];
|
||||
volatile int16_t *spare1 =&ram_buffer[ram_rd_start+14];
|
||||
volatile int16_t *spare2 =&ram_buffer[ram_rd_start+15];
|
||||
volatile int16_t *spare3 =&ram_buffer[ram_rd_start+16];
|
||||
volatile int16_t *spare4 =&ram_buffer[ram_rd_start+17];
|
||||
|
||||
void comms_check(void)
|
||||
{
|
||||
*status = 1;
|
||||
*state = 0;
|
||||
*joint_rel_position = 3;
|
||||
*joint_revolution = 4;
|
||||
*joint_abs_position = 5;
|
||||
*joint_speed = 6;
|
||||
*joint_torque = 7;
|
||||
*motor_rel_revolutions = 8;
|
||||
*motor_rel_position = 9;
|
||||
*motor_abs_position = 10;
|
||||
*motor_dutyCycle = 11;
|
||||
*motor_speed = 12;
|
||||
*motor_torque = 13;
|
||||
*motor_currentPHA = 14;
|
||||
*motor_currentPHB = 15;
|
||||
*motor_currentPHC = 16;
|
||||
*motor_currentBUS = 17;
|
||||
*hall_state = 18;
|
||||
*Spare_byte1 = 19;
|
||||
*Spare_1 = 20;
|
||||
*Spare_2 = 21;
|
||||
}
|
||||
|
||||
void clear_comms_buffer(void)
|
||||
{
|
||||
memset(ram_buffer, 0, ram_rd_start);
|
||||
}
|
||||
|
||||
|
||||
|
||||
#endif /* COMMUNICATION_H_ */
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* configuration.h
|
||||
*
|
||||
* Created: 03/03/2021 08:38:13
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
|
||||
#ifndef CONFIGURATION_H_
|
||||
#define CONFIGURATION_H_
|
||||
#include <atmel_start.h>
|
||||
//#include <tc_lite.h>
|
||||
|
||||
|
||||
|
||||
#include "pins.h"
|
||||
#include "bldc.h"
|
||||
|
||||
#define DMAC_CHANNEL_ADC_SEQ 2U
|
||||
#define DMAC_CHANNEL_ADC_SRAM 3U
|
||||
|
||||
|
||||
//void dummy2 (void){
|
||||
//while(1);
|
||||
//}
|
||||
//
|
||||
//void dummy3 (void){
|
||||
//while(1);
|
||||
//}
|
||||
//
|
||||
//void dummy4 (void){
|
||||
//while(1);
|
||||
//}
|
||||
//void dummy5 (void){
|
||||
//while(1);
|
||||
//}
|
||||
//
|
||||
//void dummy6 (void){
|
||||
//while(1);
|
||||
//}
|
||||
|
||||
inline static void configure_tcc_pwm(void)
|
||||
{
|
||||
|
||||
/* TCC0 */
|
||||
hri_tcc_set_WEXCTRL_OTMX_bf(TCC0, 0);
|
||||
hri_tcc_write_PER_reg(TCC0,1200);
|
||||
|
||||
hri_tcc_set_WAVE_POL0_bit(TCC0);
|
||||
hri_tcc_set_WAVE_POL1_bit(TCC0);
|
||||
hri_tcc_set_WAVE_POL2_bit(TCC0);
|
||||
hri_tcc_set_WAVE_POL3_bit(TCC0);
|
||||
hri_tcc_set_WAVE_POL4_bit(TCC0);
|
||||
hri_tcc_set_WAVE_POL5_bit(TCC0);
|
||||
hri_tcc_write_CC_CC_bf(TCC0, 0, 0);
|
||||
hri_tcc_write_CC_CC_bf(TCC0, 1, 0);
|
||||
hri_tcc_write_CC_CC_bf(TCC0, 2, 0);
|
||||
hri_tcc_write_CC_CC_bf(TCC0, 3, 0);
|
||||
hri_tcc_write_CC_CC_bf(TCC0, 4, 0);
|
||||
hri_tcc_write_CC_CC_bf(TCC0, 5, 0);
|
||||
|
||||
hri_tcc_write_CTRLA_ENABLE_bit(TCC0, 1 << TCC_CTRLA_ENABLE_Pos);
|
||||
|
||||
|
||||
/* TCC1 */
|
||||
hri_tcc_set_WEXCTRL_OTMX_bf(TCC1, 3);
|
||||
hri_tcc_write_CC_CC_bf(TCC1, 0, 0);
|
||||
hri_tcc_write_CC_CC_bf(TCC1, 1, 0);
|
||||
hri_tcc_write_CC_CC_bf(TCC1, 2, 0);
|
||||
hri_tcc_write_CC_CC_bf(TCC1, 3, 0);
|
||||
//hri_tcc_write_CC_CC_bf(TCC1, 0, 0);
|
||||
hri_tcc_write_PER_reg(TCC1,1200);
|
||||
//pwm_set_parameters(&TCC_PWM, 1000, 250);
|
||||
|
||||
hri_tcc_set_WAVE_POL0_bit(TCC1);
|
||||
hri_tcc_set_WAVE_POL1_bit(TCC1);
|
||||
hri_tcc_set_WAVE_POL2_bit(TCC1);
|
||||
hri_tcc_set_WAVE_POL3_bit(TCC1);
|
||||
hri_tcc_set_WAVE_POL4_bit(TCC1);
|
||||
hri_tcc_set_WAVE_POL5_bit(TCC1);
|
||||
|
||||
hri_tcc_clear_CTRLA_ENABLE_bit(TCC1);
|
||||
hri_tcc_write_CTRLA_MSYNC_bit(TCC1, true);
|
||||
//hri_tcc_write_CTRLA_ENABLE_bit(TCC1, 1 << TCC_CTRLA_ENABLE_Pos); /* Enable: enabled */
|
||||
|
||||
pwm_register_callback(&TCC_PWM, PWM_PERIOD_CB, pwm_cb);
|
||||
pwm_enable(&TCC_PWM);
|
||||
|
||||
}
|
||||
|
||||
inline void configure_adc(void)
|
||||
{
|
||||
adc_sync_enable_channel(&ADC_0, 0);
|
||||
//adc_sync_enable_channel(&ADC_1, 0);
|
||||
|
||||
//adc_async_register_callback(&ADC_0, 0, ADC_ASYNC_CONVERT_CB, adc_cb);
|
||||
//adc_async_register_callback(&ADC_1, 0, ADC_ASYNC_CONVERT_CB, convert_cb_ADC_1);
|
||||
//adc_async_start_conversion(&ADC_0);
|
||||
//adc_async_start_conversion(&ADC_1);
|
||||
}
|
||||
|
||||
void config_pins(void)
|
||||
{
|
||||
//gpio_set_pin_direction(DBG_PIN1, GPIO_DIRECTION_OUT);
|
||||
//gpio_set_pin_function(DBG_PIN1, GPIO_PIN_FUNCTION_OFF);
|
||||
}
|
||||
|
||||
|
||||
inline void configure_TC_CCL_SPEED(void)
|
||||
{
|
||||
/* Enable TC1 Clock for 32-bit timer. Linked to TC0 in driver_init.c
|
||||
Could also add a hri_gclk_write_PCHCTRL_reg call for TC1 but it is redundant (for SAME54) since TC0 and TC1 share the GCLK index.*/
|
||||
//hri_gclk_write_PCHCTRL_reg(GCLK, TC1_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
//event_system_enable_generator(
|
||||
|
||||
}
|
||||
|
||||
inline static void adc_init_dma(void)
|
||||
{
|
||||
adc_sram_dmac_init();
|
||||
adc_dmac_sequence_init();
|
||||
hri_adc_set_DSEQCTRL_INPUTCTRL_bit(ADC0);
|
||||
hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC0);
|
||||
}
|
||||
|
||||
inline void adc_dmac_sequence_init()
|
||||
{
|
||||
/* Configure the DMAC source address, destination address,
|
||||
* next descriptor address, data count and Enable the DMAC Channel */
|
||||
_dma_set_source_address(DMAC_CHANNEL_ADC_SEQ, (const void *)adc_seq_regs);
|
||||
_dma_set_destination_address(DMAC_CHANNEL_ADC_SEQ, (const void *)&ADC0->DSEQDATA.reg);
|
||||
_dma_set_data_amount(DMAC_CHANNEL_ADC_SEQ, 4);
|
||||
_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SEQ, DMAC_CHANNEL_ADC_SEQ);
|
||||
_dma_enable_transaction(DMAC_CHANNEL_ADC_SEQ, false);
|
||||
//_dma_get_channel_resource(&adc_dmac_sequence_resource, DMAC_CHANNEL_ADC_SEQ);
|
||||
//adc_dmac_sequence_resource[0].dma_cb.error = dummy2;
|
||||
//adc_dmac_sequence_resource[0].dma_cb.suspend = dummy3;
|
||||
//adc_dmac_sequence_resource[0].dma_cb.transfer_done = dummy4;
|
||||
|
||||
|
||||
hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[2], 0x01); //Suspend
|
||||
}
|
||||
|
||||
inline void adc_sram_dmac_init()
|
||||
{
|
||||
/* Configure the DMAC source address, destination address,
|
||||
* next descriptor address, data count and Enable the DMAC Channel */
|
||||
_dma_set_source_address(DMAC_CHANNEL_ADC_SRAM, (const void *)&ADC0->RESULT.reg);
|
||||
_dma_set_destination_address(DMAC_CHANNEL_ADC_SRAM, (const void *)adc_res);
|
||||
_dma_set_data_amount(DMAC_CHANNEL_ADC_SRAM, 4);
|
||||
_dma_set_irq_state(DMAC_CHANNEL_ADC_SRAM, DMA_TRANSFER_COMPLETE_CB, true);
|
||||
_dma_get_channel_resource(&adc_sram_dma_resource, DMAC_CHANNEL_ADC_SRAM);
|
||||
adc_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback;
|
||||
//adc_sram_dma_resource[0].dma_cb.error = dummy6;
|
||||
//adc_sram_dma_resource[0].dma_cb.suspend = dummy5;
|
||||
_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SRAM, DMAC_CHANNEL_ADC_SRAM);
|
||||
_dma_enable_transaction(DMAC_CHANNEL_ADC_SRAM, false);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /* CONFIGURATION_H_ */
|
||||
|
|
@ -0,0 +1,260 @@
|
|||
/*
|
||||
* pi.h
|
||||
*
|
||||
* Created: 01/02/2021 21:36:11
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
#ifndef CONTROL_H_
|
||||
#define CONTROL_H_
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// history
|
||||
// ----------------------------------------------------------------------
|
||||
// 01.02.2021 - initial Revision
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// header files
|
||||
// ----------------------------------------------------------------------
|
||||
#include "arm_math.h"
|
||||
#include "atmel_start.h"
|
||||
#include "utilities.h"
|
||||
// ----------------------------------------------------------------------
|
||||
// #defines
|
||||
// ----------------------------------------------------------------------
|
||||
// ----------------------------------------------------------------------
|
||||
// global variables
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* PI Structure */
|
||||
typedef volatile struct
|
||||
{
|
||||
volatile float32_t Kp; // the proportional gain for the PI controller
|
||||
volatile float32_t Ki; // the integral gain for the PI controller
|
||||
|
||||
volatile float32_t Ref_pu; // the reference value [pu]
|
||||
volatile float32_t Fbk_pu; // the feedback value [pu]
|
||||
volatile float32_t Ff_pu; // the feedForward value [pu]
|
||||
|
||||
volatile float32_t OutMin_pu; // the saturation low limit for the controller output [pu]
|
||||
volatile float32_t OutMax_pu; // the saturation high limit for the controller output [pu]
|
||||
volatile float32_t Out_pu; // the controller output [pu]
|
||||
|
||||
volatile float32_t Ui; // the integrator value for the PI controller
|
||||
volatile float32_t error; // the integrator value for the PI controller
|
||||
volatile bool SatFlag; // flag to signal controller saturation
|
||||
} PI_t;
|
||||
|
||||
/* PID Structure */
|
||||
typedef volatile struct
|
||||
{
|
||||
volatile float32_t Kp; //!< the proportional gain for the PID controller
|
||||
volatile float32_t Ki; //!< the integral gain for the PID controller
|
||||
volatile float32_t Kd; //!< the derivative gain for the PID controller
|
||||
|
||||
volatile float32_t Ref_pu; //!< the reference input value
|
||||
volatile float32_t Fbk_pu; //!< the feedback input value
|
||||
volatile float32_t Ff_pu; //!< the feedforward input value
|
||||
|
||||
volatile float32_t OutMin_pu; //!< the minimum output value allowed for the PID controller
|
||||
volatile float32_t OutMax_pu; //!< the maximum output value allowed for the PID controller
|
||||
volatile float32_t Out_pu; // the controller output [pu]
|
||||
|
||||
volatile float32_t Ui; //!< the integrator start value for the PID controller
|
||||
volatile float32_t Ud;
|
||||
volatile float32_t error; // the integrator value for the PI controller
|
||||
|
||||
//FILTER_FO_Handle derFilterHandle; //!< the derivative filter handle
|
||||
//FILTER_FO_Obj derFilter; //!< the derivative filter object
|
||||
} PID_t;
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// functions
|
||||
// ----------------------------------------------------------------------
|
||||
// function to set default values for the object
|
||||
|
||||
//inline float32_t clamp(const float32_t d, const float32_t min, const float32_t max) {
|
||||
//const float32_t t = d < min ? min : d;
|
||||
//return t > max ? max : t;
|
||||
//}
|
||||
|
||||
|
||||
inline void PI_objectInit(volatile PI_t *pPi_obj)
|
||||
{
|
||||
PI_t *obj = (PI_t *)pPi_obj;
|
||||
|
||||
// Function initializes the object with default values
|
||||
//fix16_t Kp = fix16_from_float32_t(1.0);
|
||||
obj->Kp = 0.0f;
|
||||
obj->Ki = 0.0f;
|
||||
obj->Fbk_pu = 0.0f;
|
||||
obj->Ref_pu = 0.0f;
|
||||
obj->Ff_pu = 0.0f;
|
||||
obj->Out_pu = 0.0f;
|
||||
obj->OutMax_pu = 0.0f;
|
||||
obj->OutMin_pu = 0.0f;
|
||||
obj->Ui = 0.0f;
|
||||
obj->SatFlag = false;
|
||||
}
|
||||
|
||||
inline void PID_objectInit(volatile PID_t *pPiD_obj)
|
||||
{
|
||||
PID_t *obj = (PID_t *)pPiD_obj;
|
||||
|
||||
// Function initializes the object with default values
|
||||
//fix16_t Kp = fix16_from_float32_t(1.0);
|
||||
obj->Kp = 0.0f;
|
||||
obj->Ki = 0.0f;
|
||||
obj->Kd = 0.0f;
|
||||
obj->Fbk_pu = 0.0f;
|
||||
obj->Ref_pu = 0.0f;
|
||||
obj->Ff_pu = 0.0f;
|
||||
obj->Out_pu = 0.0f;
|
||||
obj->OutMax_pu = 0.0f;
|
||||
obj->OutMin_pu = 0.0f;
|
||||
obj->Ui = 0.0f;
|
||||
obj->Ud = 0.0f;
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// PI Calculation
|
||||
// ----------------------------------------------------------------------
|
||||
static inline void PI_run_series(volatile PI_t *pPi_obj)
|
||||
{
|
||||
PI_t *obj = (PI_t *)pPi_obj;
|
||||
volatile float32_t Up;
|
||||
|
||||
// Compute the controller error
|
||||
obj->error = obj->Ref_pu - obj->Fbk_pu;
|
||||
|
||||
// Compute the proportional term
|
||||
Up = obj->Kp *obj->error;
|
||||
|
||||
// Compute the integral term in series form and saturate
|
||||
obj->Ui = f_clamp((obj->Ui + (obj->Ki * Up)), obj->OutMin_pu, obj->OutMax_pu);
|
||||
|
||||
// Saturate the output
|
||||
obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);
|
||||
}
|
||||
|
||||
static inline void PI_run_parallel(volatile PI_t *pPi_obj)
|
||||
{
|
||||
PI_t *obj = (PI_t *)pPi_obj;
|
||||
volatile float32_t Up;
|
||||
|
||||
// Compute the controller error
|
||||
obj->error = obj->Ref_pu - obj->Fbk_pu;
|
||||
|
||||
// Compute the proportional term
|
||||
Up = obj->Kp * obj->error;
|
||||
|
||||
// Compute the integral term in parallel form and saturate
|
||||
obj->Ui = f_clamp((obj->Ui + (obj->Ki * obj->error)), obj->OutMin_pu, obj->OutMax_pu);
|
||||
|
||||
obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu); // Saturate the output
|
||||
} // end of PI_run_parallel() function
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// PID Calculation
|
||||
// ----------------------------------------------------------------------
|
||||
static inline void PID_run_series(volatile PID_t *pPid_obj)
|
||||
{
|
||||
PID_t *obj = (PID_t *)pPid_obj;
|
||||
volatile float32_t Up, Ud_tmp;
|
||||
|
||||
// Compute the controller error
|
||||
obj->error = obj->Ref_pu - obj->Fbk_pu;
|
||||
|
||||
// Compute the proportional term
|
||||
Up = obj->Kp * obj->error;
|
||||
|
||||
if(obj->Ki>0.0f){
|
||||
// Compute the integral term in parallel form and saturate
|
||||
obj->Ui = f_clamp((obj->Ui + (obj->Ki * Up)), obj->OutMin_pu, obj->OutMax_pu);
|
||||
}
|
||||
|
||||
Ud_tmp = obj->Kd * obj->Ui; // Compute the derivative term
|
||||
|
||||
obj->Ud = Ud_tmp; // Replace with filter
|
||||
|
||||
obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ud + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu); // Saturate the output
|
||||
|
||||
}
|
||||
|
||||
static inline void PID_run_parallel(volatile PID_t *pPid_obj)
|
||||
{
|
||||
PID_t *obj = (PID_t *)pPid_obj;
|
||||
volatile float32_t Up, Ud_tmp;
|
||||
|
||||
|
||||
// Compute the controller error
|
||||
obj->error = obj->Ref_pu - obj->Fbk_pu;
|
||||
|
||||
// Compute the proportional term
|
||||
Up = obj->Kp * obj->error;
|
||||
|
||||
if(obj->Ki>0.0f){
|
||||
// Compute the integral term in parallel form and saturate
|
||||
obj->Ui = f_clamp((obj->Ui + (obj->Ki * obj->error)), obj->OutMin_pu, obj->OutMax_pu);
|
||||
}
|
||||
|
||||
Ud_tmp = obj->Kd * obj->error; // Compute the derivative term
|
||||
|
||||
obj->Ud = Ud_tmp; // Replace with filter
|
||||
|
||||
obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ud + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu); // Saturate the output
|
||||
}
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Calculate Current Parameters
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
static inline float32_t PI_calcKp(const float32_t Ls_H, const float32_t deviceCurrent_A, const float32_t deviceVoltage_V,
|
||||
const float32_t deviceCtrlPeriode_Sec)
|
||||
{
|
||||
// calculation is based on "Betragsoptimum"
|
||||
// Kp = Ls/(2*tau)
|
||||
float32_t x1;
|
||||
float32_t y1;
|
||||
float32_t Kp;
|
||||
|
||||
// multiplication with deviceCurrent_A is to get per unit values
|
||||
x1 = (float32_t)(Ls_H * deviceCurrent_A);
|
||||
|
||||
y1 = (float32_t)(2.0f * deviceCtrlPeriode_Sec);
|
||||
|
||||
// multiplication with deviceVoltage_V is to get per unit values
|
||||
y1 = (float32_t)(y1 * deviceVoltage_V);
|
||||
|
||||
Kp = (x1 / y1);
|
||||
return Kp;
|
||||
}
|
||||
|
||||
static inline float32_t PI_calcKi(const float32_t Rs_Ohm, const float32_t Ls_H, const float32_t deviceCtrlPeriode_Sec)
|
||||
{
|
||||
// calculation is based on "TI - MotorWare's documentation"
|
||||
float32_t RsByLs = (float32_t)(Rs_Ohm / Ls_H);
|
||||
float32_t Ki = RsByLs * deviceCtrlPeriode_Sec;
|
||||
//fix16_t Ki = 0;
|
||||
return Ki;
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// something...
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// end of file
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
#endif /* BLDC_PI_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,343 @@
|
|||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
|
||||
#include "driver_init.h"
|
||||
#include <peripheral_clk_config.h>
|
||||
#include <utils.h>
|
||||
#include <hal_init.h>
|
||||
|
||||
struct spi_m_dma_descriptor SPI_MS_IF;
|
||||
|
||||
struct spi_m_dma_descriptor SPI_0;
|
||||
|
||||
void EVENT_SYSTEM_0_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_1, CONF_GCLK_EVSYS_CHANNEL_1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_2, CONF_GCLK_EVSYS_CHANNEL_2_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);
|
||||
|
||||
event_system_init();
|
||||
}
|
||||
|
||||
void SPI_MS_IF_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_level(DRV_INB,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(DRV_INB, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(DRV_INB, PINMUX_PB27D_SERCOM4_PAD0);
|
||||
|
||||
gpio_set_pin_level(DRV_INC,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(DRV_INC, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(DRV_INC, PINMUX_PB26D_SERCOM4_PAD1);
|
||||
|
||||
// Set pin direction to input
|
||||
gpio_set_pin_direction(DRV_ENC, GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_pull_mode(DRV_ENC,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(DRV_ENC, PINMUX_PB29D_SERCOM4_PAD3);
|
||||
}
|
||||
|
||||
void SPI_MS_IF_CLOCK_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
hri_mclk_set_APBDMASK_SERCOM4_bit(MCLK);
|
||||
}
|
||||
|
||||
void SPI_MS_IF_init(void)
|
||||
{
|
||||
SPI_MS_IF_CLOCK_init();
|
||||
spi_m_dma_init(&SPI_MS_IF, SERCOM4);
|
||||
SPI_MS_IF_PORT_init();
|
||||
}
|
||||
|
||||
void SPI_0_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_level(PB16,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(PB16, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(PB16, PINMUX_PB16C_SERCOM5_PAD0);
|
||||
|
||||
gpio_set_pin_level(PB17,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(PB17, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(PB17, PINMUX_PB17C_SERCOM5_PAD1);
|
||||
|
||||
// Set pin direction to input
|
||||
gpio_set_pin_direction(PB01, GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_pull_mode(PB01,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(PB01, PINMUX_PB01D_SERCOM5_PAD3);
|
||||
}
|
||||
|
||||
void SPI_0_CLOCK_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_CORE, CONF_GCLK_SERCOM5_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_SLOW, CONF_GCLK_SERCOM5_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
hri_mclk_set_APBDMASK_SERCOM5_bit(MCLK);
|
||||
}
|
||||
|
||||
void SPI_0_init(void)
|
||||
{
|
||||
SPI_0_CLOCK_init();
|
||||
spi_m_dma_init(&SPI_0, SERCOM5);
|
||||
SPI_0_PORT_init();
|
||||
}
|
||||
|
||||
void TC_ECAT_CLOCK_init(void)
|
||||
{
|
||||
hri_mclk_set_APBDMASK_TC7_bit(MCLK);
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, TC7_GCLK_ID, CONF_GCLK_TC7_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
}
|
||||
|
||||
void system_init(void)
|
||||
{
|
||||
init_mcu();
|
||||
|
||||
// GPIO on PA18
|
||||
|
||||
gpio_set_pin_level(M3_3,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(M3_3, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(M3_3, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PA27
|
||||
|
||||
gpio_set_pin_level(DRV_RESET,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(DRV_RESET, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(DRV_RESET, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PB00
|
||||
|
||||
gpio_set_pin_level(ECAT_SPI_CS_PIN,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(ECAT_SPI_CS_PIN, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(ECAT_SPI_CS_PIN, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PB14
|
||||
|
||||
gpio_set_pin_level(M3_4,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(M3_4, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(M3_4, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PB15
|
||||
|
||||
gpio_set_pin_level(M3_5,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(M3_5, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(M3_5, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PB28
|
||||
|
||||
gpio_set_pin_level(SPI_CS,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(SPI_CS, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(SPI_CS, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PB31
|
||||
|
||||
// Set pin direction to input
|
||||
gpio_set_pin_direction(SW0, GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_pull_mode(SW0,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_UP);
|
||||
|
||||
gpio_set_pin_function(SW0, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PC01
|
||||
|
||||
gpio_set_pin_level(DEBUG_1,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(DEBUG_1, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(DEBUG_1, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PC02
|
||||
|
||||
gpio_set_pin_level(DEBUG_3,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(DEBUG_3, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(DEBUG_3, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PC03
|
||||
|
||||
gpio_set_pin_level(DEBUG_2,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(DEBUG_2, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(DEBUG_2, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PC18
|
||||
|
||||
gpio_set_pin_level(LED0,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(LED0, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(LED0, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PC30
|
||||
|
||||
gpio_set_pin_level(DEBUG_4,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(DEBUG_4, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(DEBUG_4, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PD11
|
||||
|
||||
gpio_set_pin_level(DEBUG_5,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(DEBUG_5, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(DEBUG_5, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
EVENT_SYSTEM_0_init();
|
||||
|
||||
SPI_MS_IF_init();
|
||||
|
||||
SPI_0_init();
|
||||
|
||||
TC_ECAT_CLOCK_init();
|
||||
|
||||
TC_ECAT_init();
|
||||
}
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef DRIVER_INIT_INCLUDED
|
||||
#define DRIVER_INIT_INCLUDED
|
||||
|
||||
#include "atmel_start_pins.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <hal_atomic.h>
|
||||
#include <hal_delay.h>
|
||||
#include <hal_gpio.h>
|
||||
#include <hal_init.h>
|
||||
#include <hal_io.h>
|
||||
#include <hal_sleep.h>
|
||||
|
||||
#include <hal_evsys.h>
|
||||
|
||||
#include <hal_spi_m_dma.h>
|
||||
|
||||
#include <hal_spi_m_dma.h>
|
||||
#include <tc_lite.h>
|
||||
|
||||
extern struct spi_m_dma_descriptor SPI_MS_IF;
|
||||
|
||||
extern struct spi_m_dma_descriptor SPI_0;
|
||||
|
||||
void SPI_MS_IF_PORT_init(void);
|
||||
void SPI_MS_IF_CLOCK_init(void);
|
||||
void SPI_MS_IF_init(void);
|
||||
|
||||
void SPI_0_PORT_init(void);
|
||||
void SPI_0_CLOCK_init(void);
|
||||
void SPI_0_init(void);
|
||||
|
||||
void TC_ECAT_CLOCK_init(void);
|
||||
|
||||
int8_t TC_ECAT_init(void);
|
||||
|
||||
/**
|
||||
* \brief Perform system initialization, initialize pins and clocks for
|
||||
* peripherals
|
||||
*/
|
||||
void system_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif // DRIVER_INIT_INCLUDED
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* communication.h
|
||||
*
|
||||
* Created: 10/03/2021 13:07:51
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
|
||||
#ifndef COMMUNICATION_H_
|
||||
#define COMMUNICATION_H_
|
||||
|
||||
#include "ethercat_e54.h"
|
||||
|
||||
//Write To Ecat Total Bytes (38 bytes)
|
||||
//write (2 Bytes)
|
||||
volatile uint8_t *status =&ram_buffer[ram_wr_start];
|
||||
volatile uint8_t *state =(((uint8_t *)&ram_buffer[ram_wr_start])+1);
|
||||
//Joint (10 Bytes)
|
||||
volatile int16_t *joint_rel_position =&ram_buffer[ram_wr_start+1];
|
||||
volatile int16_t *joint_revolution =&ram_buffer[ram_wr_start+2];
|
||||
volatile int16_t *joint_abs_position =&ram_buffer[ram_wr_start+3];
|
||||
volatile int16_t *joint_speed =&ram_buffer[ram_wr_start+4];
|
||||
volatile int16_t *joint_torque =&ram_buffer[ram_wr_start+5];
|
||||
// Motor (20+1+1+4) = 26
|
||||
volatile int16_t *motor_rel_revolutions=&ram_buffer[ram_wr_start+6];
|
||||
volatile int16_t *motor_rel_position =&ram_buffer[ram_wr_start+7];
|
||||
volatile int16_t *motor_abs_position =&ram_buffer[ram_wr_start+8];
|
||||
volatile int16_t *motor_dutyCycle =&ram_buffer[ram_wr_start+9];
|
||||
volatile int16_t *motor_speed =&ram_buffer[ram_wr_start+10];
|
||||
volatile int16_t *motor_torque =&ram_buffer[ram_wr_start+11];
|
||||
volatile int16_t *motor_currentPHA =&ram_buffer[ram_wr_start+12];
|
||||
volatile int16_t *motor_currentPHB =&ram_buffer[ram_wr_start+13];
|
||||
volatile int16_t *motor_currentPHC =&ram_buffer[ram_wr_start+14];
|
||||
volatile int16_t *motor_currentBUS =&ram_buffer[ram_wr_start+15];
|
||||
volatile uint8_t *hall_state =&ram_buffer[ram_wr_start+16];
|
||||
volatile uint8_t *Spare_byte1 =(((uint8_t *)&ram_buffer[ram_wr_start+16])+1);
|
||||
volatile int16_t *Spare_1 =&ram_buffer[ram_wr_start+17];
|
||||
volatile int16_t *Spare_2 =&ram_buffer[ram_wr_start+18];
|
||||
|
||||
//Read From Ecat Total (35 Bytes)
|
||||
// (1 Byte)
|
||||
volatile uint8_t *control_mode =&ram_buffer[ram_rd_start];
|
||||
volatile uint8_t *control_set =(((uint8_t *)&ram_buffer[ram_rd_start])+1);
|
||||
// (34 Byte)
|
||||
volatile int16_t *desired_position =&ram_buffer[ram_rd_start+1];
|
||||
volatile int16_t *desired_speed =&ram_buffer[ram_rd_start+2];
|
||||
volatile int16_t *desired_torque =&ram_buffer[ram_rd_start+3];
|
||||
volatile int16_t *i_kp =&ram_buffer[ram_rd_start+4];
|
||||
volatile int16_t *i_ki =&ram_buffer[ram_rd_start+5];
|
||||
volatile int16_t *v_kp =&ram_buffer[ram_rd_start+6];
|
||||
volatile int16_t *v_kd =&ram_buffer[ram_rd_start+7];
|
||||
volatile int16_t *p_kp =&ram_buffer[ram_rd_start+8];
|
||||
volatile int16_t *p_ki =&ram_buffer[ram_rd_start+9];
|
||||
volatile uint16_t *ReductionRatio =&ram_buffer[ram_rd_start+10];
|
||||
volatile int16_t *max_torque =&ram_buffer[ram_rd_start+11];
|
||||
volatile int16_t *max_current =&ram_buffer[ram_rd_start+12];
|
||||
volatile int16_t *max_velocity =&ram_buffer[ram_rd_start+13];
|
||||
volatile int16_t *spare1 =&ram_buffer[ram_rd_start+14];
|
||||
volatile int16_t *spare2 =&ram_buffer[ram_rd_start+15];
|
||||
volatile int16_t *spare3 =&ram_buffer[ram_rd_start+16];
|
||||
volatile int16_t *spare4 =&ram_buffer[ram_rd_start+17];
|
||||
|
||||
void comms_check(void)
|
||||
{
|
||||
*status = 1;
|
||||
*state = 0;
|
||||
*joint_rel_position = 3;
|
||||
*joint_revolution = 4;
|
||||
*joint_abs_position = 5;
|
||||
*joint_speed = 6;
|
||||
*joint_torque = 7;
|
||||
*motor_rel_revolutions = 8;
|
||||
*motor_rel_position = 9;
|
||||
*motor_abs_position = 10;
|
||||
*motor_dutyCycle = 11;
|
||||
*motor_speed = 12;
|
||||
*motor_torque = 13;
|
||||
*motor_currentPHA = 14;
|
||||
*motor_currentPHB = 15;
|
||||
*motor_currentPHC = 16;
|
||||
*motor_currentBUS = 17;
|
||||
*hall_state = 18;
|
||||
*Spare_byte1 = 19;
|
||||
*Spare_1 = 20;
|
||||
*Spare_2 = 21;
|
||||
}
|
||||
|
||||
void clear_comms_buffer(void)
|
||||
{
|
||||
memset(ram_buffer, 0, ram_rd_start);
|
||||
}
|
||||
|
||||
|
||||
|
||||
#endif /* COMMUNICATION_H_ */
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
/*
|
||||
* ethercat_e54.c
|
||||
*
|
||||
* Created: 02/03/2021 10:49:41
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Header Files
|
||||
// ----------------------------------------------------------------------
|
||||
#include "atmel_start.h"
|
||||
#include "pins.h"
|
||||
#include "driver_init.h"
|
||||
|
||||
#include "ethercat_e54.h"
|
||||
#include "ethercat_slave_def.h"
|
||||
#include "bldc.h"
|
||||
#include "statemachine.h"
|
||||
#include <string.h>
|
||||
|
||||
|
||||
|
||||
extern void One_ms_cycle_callback(void)
|
||||
{
|
||||
tx_ethercat = true;
|
||||
if(tx_ethercat_done){
|
||||
volatile int i=0;
|
||||
//tic_port(DEBUG_3_PORT);
|
||||
//toc_port(DEBUG_3_PORT);
|
||||
|
||||
//memcpy();
|
||||
memcpy(&ram_buffer[ram_real_wr_start], &ram_buffer[ram_wr_start], ram_rd_start);
|
||||
|
||||
//for (i=0;i<ram_rd_start;i++){
|
||||
//ram_buffer[ram_real_wr_start+i] = ram_buffer[ram_wr_start+i];
|
||||
//}
|
||||
//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_rx.channel_id);
|
||||
//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||||
//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_tx.channel_id);
|
||||
//spi_m_dma_transfer(&SPI_0, )
|
||||
//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[1], DMAC_CHCTRLB_CMD_RESUME_Val); //RX Channel
|
||||
//_dma_enable_transaction(1,true);
|
||||
|
||||
gpio_set_pin_level(ECAT_SPI_CS_PIN, false); // SPI_Slave Select LOW
|
||||
DMAC->Channel[0].CHCTRLB.reg = 0x2; // Resume
|
||||
//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||||
/*hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[0], DMAC_CHCTRLB_CMD_RESUME_Val)*/; //TX Channel
DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
tx_ethercat_done = false;
}
else {
gpio_set_pin_level(ECAT_SPI_CS_PIN, true); // SPI_Slave Select HIGH
|
||||
tx_ethercat_done = false;
//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_rx.channel_id);
|
||||
//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||||
//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_tx.channel_id);
//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[1], DMAC_CHCTRLB_CMD_RESUME_Val); //RX Channel
gpio_set_pin_level(ECAT_SPI_CS_PIN, false); // SPI_Slave Select LOW
_dma_enable_transaction(0,false);
//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||||
//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[0], DMAC_CHCTRLB_CMD_RESUME_Val); //TX Channel
_dma_enable_transaction(1,false);
tx_ethercat_done = false;
}
|
||||
|
||||
//toc_port(DEBUG_3_PORT);
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Callbacks
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
static void transfer_error(struct _dma_resource *resource)
|
||||
{
|
||||
uint8_t error = 1;
|
||||
// spi_select_slave(&spi_master_instance, &slave, false);
|
||||
//DMAC->CHID.reg = resource->channel_id;
|
||||
//DMAC->CHCTRLB.bit.CMD = 0x02;
|
||||
//DMAC->CHINTFLAG.bit.SUSP = 1;
|
||||
//responde_spi_master = true;
|
||||
//com_state = com_error;
|
||||
}
|
||||
|
||||
static void LAN9252_rx_done(struct _dma_resource *resource)
|
||||
{
|
||||
gpio_set_pin_level(ECAT_SPI_CS_PIN, true);
|
||||
|
||||
//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_rx.channel_id);
|
||||
//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||||
//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_tx.channel_id);
|
||||
//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[1], DMAC_CHCTRLB_CMD_RESUME_Val); //RX Channel
|
||||
gpio_set_pin_level(ECAT_SPI_CS_PIN, false);
|
||||
//_dma_enable_transaction(0,false);
|
||||
DMAC->Channel[0].CHCTRLB.reg = 0x2; // Resume
|
||||
|
||||
//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||||
//_dma_enable_transaction(1,false); //TX Channel
DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[0], DMAC_CHCTRLB_CMD_RESUME_Val); //TX Channel
tx_ethercat_done = false;
|
||||
//responde_spi_master = true;
|
||||
}
|
||||
|
||||
|
||||
static void LAN9252_rx_susp(struct _dma_resource *resource)
|
||||
{
|
||||
gpio_set_pin_level(ECAT_SPI_CS_PIN, true);
//volatile uint32_t *pointer = ((DMAC->WRBADDR.reg)+0x10*resource->channel_id+12);
volatile uint32_t *pointer = ((DMAC->WRBADDR.reg)+12);
if (*pointer != &spi_rx_write_fifo_dma_descriptor){
//_dma_enable_transaction(0,false);
DMAC->Channel[0].CHCTRLB.reg = 0x2; // Resume
gpio_set_pin_level(ECAT_SPI_CS_PIN, false);
//_dma_enable_transaction(1,false); //TX Channel
DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
tx_ethercat_done = false;
}
else{
tx_ethercat_done = true;
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
void ethercat_update(void)
|
||||
{
|
||||
if (tx_ethercat){
|
||||
tx_ethercat = false;
|
||||
}
|
||||
}
|
||||
|
||||
//void TC7_Handler(void)
|
||||
//{
|
||||
//if (TC7->COUNT16.INTFLAG.bit.OVF == 0x01) {
|
||||
//TC7->COUNT16.INTFLAG.bit.OVF = 0x01;
|
||||
////One_ms_cycle_callback();
|
||||
//
|
||||
//}
|
||||
//}
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// functions
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
void config_ethercat_tc(void)
|
||||
{
|
||||
//tc_syncro_task.interval = 100;
|
||||
//tc_syncro_task.cb = One_ms_cycle_callback;
|
||||
//tc_syncro_task.mode = TIMER_TASK_REPEAT;
|
||||
//timer_add_task(&TC_ECAT, &tc_syncro_task);
|
||||
//timer_start(&TC_ECAT);
|
||||
}
|
||||
|
||||
void config_ethercat_sercom()
|
||||
{
|
||||
|
||||
|
||||
}
|
||||
|
||||
void configure_dma_resource()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
|
||||
void configure_ethercat_dma_descriptors(void)
|
||||
{
|
||||
TC_ECAT_init();
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// DMAC Descriptors
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
// Args = dma_transfer_descriptor_type type, *descriptor, start, lenght, next_descriptor, block_action
|
||||
|
||||
//abort actual_fifo
|
||||
//setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_abort_fifo_dma_descriptor,abort_fifo_start,abort_fifo_length,&spi_config_fifo_dma_descriptor,&spi_LAN9252_instance,DMA_BLOCK_ACTION_SUSPEND);
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX, &spi_abort_fifo_dma_descriptor, abort_fifo_start, abort_fifo_length, &spi_clear_rd_fifo_dma_descriptor, DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
|
||||
//clear initial read data from LAN9252 to avoid errors.
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_clear_rd_fifo_dma_descriptor,wr_pdram_start,wr_pdram_lenght+2*write_var_num,&spi_write_cl_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_write_cl_fifo_dma_descriptor,cl_pdram_start,cl_pdram_lenght,&spi_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
|
||||
// write fifo registers
|
||||
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_write_fifo_dma_descriptor,wr_pdram_start,wr_pdram_lenght,&spi_write2ram_dma_descriptor,DMAC_BTCTRL_BLOCKACT_NOACT_Val); //DMA_BLOCK_ACTION_NOACT
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_write2ram_dma_descriptor,&ram_buffer[ram_real_wr_start],2*write_var_num,&spi_config_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
// write fifo configuration
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_config_fifo_dma_descriptor,cf_pdram_start,cf_pdram_lenght,&spi_read_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
// read fifo registers
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_read_fifo_dma_descriptor,rd_pdram_start,rd_pdram_lenght,&spi_read2ram_dma_descriptor,DMAC_BTCTRL_BLOCKACT_NOACT_Val); //DMA_BLOCK_ACTION_NOACT
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX_DUMMY,&spi_read2ram_dma_descriptor,0,2*read_var_num,&spi_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
//// RX DESCRIPTORS
|
||||
|
||||
// abort fifo
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_abort_fifo_dma_descriptor,0,cf_pdram_lenght,&spi_rx_clear_rd_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
//clear initial read data from LAN9252 to avoid errors.
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_clear_rd_fifo_dma_descriptor,0,wr_pdram_lenght+2*write_var_num,&spi_rx_write_cl_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_write_cl_fifo_dma_descriptor,0,cl_pdram_lenght,&spi_rx_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
// write fifo registers , dummy receive
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_write_fifo_dma_descriptor,0,spi_head+2*write_var_num,&spi_rx_config_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
// write fifo config. dummy receive
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_config_fifo_dma_descriptor,0,cf_pdram_lenght,&spi_rx_read_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
// read fifo registers
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_read_fifo_dma_descriptor,0,spi_head,&spi_rx_read2ram_dma_descriptor,DMAC_BTCTRL_BLOCKACT_NOACT_Val); //DMA_BLOCK_ACTION_NOACT
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX,&spi_rx_read2ram_dma_descriptor,&ram_buffer[ram_rd_start],2*read_var_num,&spi_rx_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Register Callbacks
|
||||
// ----------------------------------------------------------------------
|
||||
//spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_RX_DONE, LAN9252_rx_done);
|
||||
//spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_ERROR, transfer_error);
|
||||
spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_SUSPEND, LAN9252_rx_susp);
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Link Descriptors
|
||||
// ----------------------------------------------------------------------
|
||||
_dma_set_descriptor(0, spi_rx_abort_fifo_dma_descriptor);
|
||||
_dma_set_descriptor(1, spi_abort_fifo_dma_descriptor);
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Enable SPI DMA
|
||||
// ----------------------------------------------------------------------
|
||||
spi_m_dma_enable(&SPI_0);
|
||||
// _dma_enable_transaction(&DMAC->Channel[1],true);
|
||||
// _dma_enable_transaction(&DMAC->Channel[0],true);
|
||||
//DMAC->Channel[0].CHCTRLA.bit.ENABLE = true;
|
||||
//DMAC->Channel[1].CHCTRLA.bit.ENABLE = true;
|
||||
|
||||
}
|
||||
|
||||
static void setup_transfer_descriptor(enum dma_transfer_descriptor_type type, DmacDescriptor *descriptor, const uint32_t start,
|
||||
const uint32_t lenght, const uint32_t next_descriptor, uint16_t block_action)
|
||||
{
|
||||
|
||||
/*** DMA RX Descriptor Initialization step by step
|
||||
*** 1- Validate the Descriptor
|
||||
*** 2- Event Output = DMA_EVENT_OUTPUT_BEAT
|
||||
*** 3- block_action = DMA_BLOCK_ACTION_NOACT;
|
||||
*** 4- beat_size = DMA_BEAT_SIZE_BYTE;
|
||||
*** 5- src_increment_enable = false;
|
||||
*** 6- dst_increment_enable = false;
|
||||
*** 7- step_selection = DMA_STEPSEL_DST;
|
||||
*** 8- step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
|
||||
*** 9- block_transfer_count;
|
||||
*** 10- source_address = (uint32_t)NULL;
|
||||
*** 11- destination_address = (uint32_t)NULL;
|
||||
*** 12- next_descriptor_address = 0;
|
||||
***/
|
||||
|
||||
hri_dmacdescriptor_set_BTCTRL_VALID_bit(descriptor); // 1.Validate the Descriptor
|
||||
hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(descriptor, DMAC_BTCTRL_EVOSEL_BURST_Val); // 2. Define mentions 0x3 as Burst, but 0x3 = BEAT (Event strobe when beat transfer complete)
|
||||
hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(descriptor, block_action); // 3. block_action
|
||||
hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(descriptor, DMAC_BTCTRL_BEATSIZE_BYTE_Val); // 4. beat_size
|
||||
|
||||
switch (type){
|
||||
case DMA_TRANSFER_DESCRIPTOR_TX:
|
||||
hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(descriptor, true); // 5. src_increment_enable = true
|
||||
hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(descriptor, false); // 6. dst_increment_enable = false
|
||||
hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(descriptor, start+lenght); // 10. source_address
|
||||
hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(descriptor, (uint32_t)(&SPI_LAN9252->SPI.DATA.reg)); // 11. destination_address
|
||||
break;
|
||||
case DMA_TRANSFER_DESCRIPTOR_TX_DUMMY:
|
||||
hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(descriptor, false); // 5. src_increment_enable = false
|
||||
hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(descriptor, false); // 6. dst_increment_enable = false
|
||||
hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(descriptor, dummy_register); // 10. source_address
|
||||
hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(descriptor, (uint32_t)(&SPI_LAN9252->SPI.DATA.reg)); // 11. destination_address
|
||||
break;
|
||||
case DMA_TRANSFER_DESCRIPTOR_RX:
|
||||
hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(descriptor, false); // 5. src_increment_enable = false
|
||||
hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(descriptor, true); // 6. dst_increment_enable = true
|
||||
hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(descriptor, (uint32_t)(&SPI_LAN9252->SPI.DATA.reg)); // 10. source_address
|
||||
hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(descriptor, start+lenght); // 11. destination_address
|
||||
break;
|
||||
case DMA_TRANSFER_DESCRIPTOR_RX_DUMMY:
|
||||
hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(descriptor, false); // 5. src_increment_enable
|
||||
hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(descriptor, false); // 6. dst_increment_enable = false;
|
||||
hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(descriptor, (uint32_t)(&SPI_LAN9252->SPI.DATA.reg)); // 10. source_address
|
||||
hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(descriptor, &spi_rx_buffer[0]); // 11. destination_address
|
||||
break;
|
||||
}
|
||||
|
||||
hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(descriptor, false); // 7. step_selection = DMA_STEPSEL_DST
|
||||
hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(descriptor, DMAC_BTCTRL_STEPSIZE_X1_Val); // 8. step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1
|
||||
hri_dmacdescriptor_write_BTCNT_BTCNT_bf(descriptor, lenght); // 9. block_transfer_count;
|
||||
hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(descriptor, next_descriptor); // 12. next_descriptor_address = 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
/*
|
||||
* ethercat_e54.h
|
||||
*
|
||||
* Created: 02/03/2021 10:49:33
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
#ifndef ETHERCAT_E54_H_
|
||||
#define ETHERCAT_E54_H_
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Header Files
|
||||
// ----------------------------------------------------------------------
|
||||
// ----------------------------------------------------------------------
|
||||
// Defines
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Types
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
enum dma_transfer_descriptor_type {
|
||||
DMA_TRANSFER_DESCRIPTOR_TX,
|
||||
DMA_TRANSFER_DESCRIPTOR_RX,
|
||||
DMA_TRANSFER_DESCRIPTOR_TX_DUMMY,
|
||||
DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,
|
||||
};
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Register Addresses
|
||||
// ----------------------------------------------------------------------
|
||||
#define read_var_num 32U //to change to 16bits need to change ecat spi lenght.
|
||||
#define write_var_num 32U //max 20
|
||||
|
||||
// #define read_var_num 2 //to change to 16bits need to change ecat spi lenght.
|
||||
// #define write_var_num 2 //max 20
|
||||
|
||||
#define ram_wr_start 0U
|
||||
#define ram_rd_start write_var_num //write_var_num
|
||||
#define ram_real_wr_start ram_rd_start + read_var_num
|
||||
|
||||
#define SPI_READ 0x03U
|
||||
#define SPI_WRITE 0x02U
|
||||
#define SPI_INC 0x40U
|
||||
#define SPI_DEC 0x80U
|
||||
#define TEST_VAL 0x87654321U
|
||||
#define CSR_BUSY 0x80000000U
|
||||
#define ADDR_BYTES 2
|
||||
#define CSR_READ 1<<30
|
||||
#define CSR_WRITE 0<<30
|
||||
#define CSR_SIZE 4<<16
|
||||
#define CSR_HW_RD 1<<27
|
||||
|
||||
#define ECAT_PRAM_RD_DATA 0x0000U
|
||||
#define ECAT_PRAM_WR_DATA 0x2000U
|
||||
#define ID_REV 0x5000U
|
||||
#define IRQ_CFG 0x5400U
|
||||
#define INT_STS 0x5800U
|
||||
#define INT_EN 0x5C00U
|
||||
#define BYTE_TEST 0x6400U
|
||||
#define HW_CFG 0x7400U
|
||||
#define PMT_CTRL 0x8400U
|
||||
#define GPT_CFG 0x8C00U
|
||||
#define GPT_CNT 0x9000U
|
||||
#define FREE_RUN 0x9C00U
|
||||
#define RESET_CTL 0xF801U
|
||||
#define ECAT_CSR_DATA 0x0003U
|
||||
#define ECAT_CSR_CMD 0x0403U
|
||||
#define ECAT_PRAM_RD_ADDR_LEN 0x0803U
|
||||
#define ECAT_PRAM_RD_CMD 0x0C03U
|
||||
#define ECAT_PRAM_WR_ADDR_LEN 0x1003U
|
||||
#define ECAT_PRAM_WR_CMD 0x1403U
|
||||
|
||||
#define PDRAM_RD_ADDRESS 0x1100U
|
||||
#define PDRAM_WR_ADDRESS 0x1800U
|
||||
|
||||
//#define PDRAM_RD_LENGTH 2*read_var_num
|
||||
//#define PDRAM_WR_LENGTH 2*write_var_num
|
||||
|
||||
#define PDRAM_RD_LENGTH 120
|
||||
#define PDRAM_WR_LENGTH 56
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// SPI
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
#define spi_head 3
|
||||
#define hw_tst_length spi_head +4
|
||||
#define by_tst_length spi_head +4
|
||||
#define rd_status_length spi_head +4*4
|
||||
#define abort_fifo_length spi_head +4*4
|
||||
#define cf_pdram_lenght spi_head +4*4
|
||||
#define rd_pdram_lenght spi_head
|
||||
#define wr_pdram_lenght spi_head
|
||||
#define cl_pdram_lenght spi_head +4*2
|
||||
|
||||
#define rd_fifo_lenght
|
||||
#define wr_fifo_lenght
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Flags
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
volatile bool tx_ethercat;
|
||||
volatile bool tx_ethercat_done;
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// DMA descriptors
|
||||
// ----------------------------------------------------------------------
|
||||
COMPILER_ALIGNED(16)
|
||||
DmacDescriptor spi_config_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_read_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_write_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_read2ram_dma_descriptor;
|
||||
DmacDescriptor spi_write2ram_dma_descriptor;
|
||||
DmacDescriptor spi_abort_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_clear_rd_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_write_cl_fifo_dma_descriptor;
|
||||
|
||||
DmacDescriptor spi_rx_config_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_rx_read_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_rx_write_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_rx_read2ram_dma_descriptor;
|
||||
DmacDescriptor spi_rx_abort_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_rx_clear_rd_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_rx_write_cl_fifo_dma_descriptor;
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Global Variables
|
||||
// ----------------------------------------------------------------------
|
||||
volatile uint16_t ram_buffer[(read_var_num+2*write_var_num)];
|
||||
//volatile uint16_t ram_buffer[(read_var_num+2*write_var_num)] = {1,2,3,4,5,6,7,8, 9,10,11,12,13,14,15,16, 17,18,19,20,21,22,23,23, 24,25,26,27,28,29,30,31, 32,33,34,35,36,37,38,39, 40,41,42,43,44,45,46,47,
|
||||
//1,2,3,4,5,6,7,8, 9,10,11,12,13,14,15,16, 17,18,19,20,21,22,23,23, 24,25,26,27,28,29,30,31, 32,33,34,35,36,37,38,39, 40,41,42,43,44,45,46,47};
|
||||
//volatile uint16_t ram_buffer[(read_var_num+2*write_var_num)] = {1,2,3,4,5,6,7,8, 9,10,11,12,13,14,15,16, 17,18,19,20,21,22,23,24 };
|
||||
//1,2,3,4,5,6,7,8, 9,10,11,12,13,14,15,16, 17,18,19,20,21,22,23,23, 24,25,26,27,28,29,30,31, 32,33,34,35,36,37,38,39, 40,41,42,43,44,45,46,47};
|
||||
|
||||
volatile uint8_t spi_rx_buffer[30];
|
||||
|
||||
static uint8_t spi_tx_buffer[110] = {
|
||||
SPI_READ,HW_CFG,HW_CFG>>8,0xFF,0xFF,0xFF,0xFF,
|
||||
SPI_READ,BYTE_TEST,BYTE_TEST>>8,0xFF,0xFF,0xFF,0xFF,
|
||||
SPI_WRITE,ECAT_PRAM_RD_ADDR_LEN | SPI_INC, (ECAT_PRAM_RD_ADDR_LEN | SPI_INC)>>8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,
|
||||
SPI_READ, ECAT_PRAM_RD_ADDR_LEN | SPI_INC, (ECAT_PRAM_RD_ADDR_LEN | SPI_INC)>>8,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
|
||||
SPI_WRITE,ECAT_PRAM_RD_ADDR_LEN | SPI_INC, (ECAT_PRAM_RD_ADDR_LEN | SPI_INC)>>8,PDRAM_RD_ADDRESS,(PDRAM_RD_ADDRESS>>8),PDRAM_RD_LENGTH,PDRAM_RD_LENGTH>>8,0x00,0x00,0x00,CSR_BUSY>>24,PDRAM_WR_ADDRESS,PDRAM_WR_ADDRESS>>8,PDRAM_WR_LENGTH,PDRAM_WR_LENGTH>>8,0x00,0x00,0x00,CSR_BUSY>>24,
|
||||
SPI_READ,ECAT_PRAM_RD_DATA,(ECAT_PRAM_RD_DATA)>>8, //modification for FIFO FIXED
|
||||
SPI_WRITE,ECAT_PRAM_WR_DATA,(ECAT_PRAM_WR_DATA)>>8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
SPI_WRITE,ECAT_PRAM_WR_ADDR_LEN | SPI_INC, (ECAT_PRAM_WR_ADDR_LEN | SPI_INC)>>8,PDRAM_RD_ADDRESS,(PDRAM_RD_ADDRESS>>8),PDRAM_RD_LENGTH,PDRAM_RD_LENGTH>>8,0x00,0x00,0x00,CSR_BUSY>>24};
|
||||
|
||||
|
||||
const static uint32_t dummy_register = &spi_tx_buffer[4];
|
||||
const static uint32_t hw_tst_start = &spi_tx_buffer[0];
|
||||
const static uint32_t by_tst_start = &spi_tx_buffer[0+hw_tst_length];
|
||||
const static uint32_t abort_fifo_start=&spi_tx_buffer[0+hw_tst_length+by_tst_length];
|
||||
const static uint32_t rd_status_start= &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length];
|
||||
const static uint32_t cf_pdram_start = &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length+rd_status_length];
|
||||
const static uint32_t rd_pdram_start = &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length+rd_status_length+cf_pdram_lenght];
|
||||
const static uint32_t wr_pdram_start = &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length+rd_status_length+cf_pdram_lenght+rd_pdram_lenght];
|
||||
volatile static uint32_t cl_pdram_start = &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length+rd_status_length+cf_pdram_lenght+rd_pdram_lenght+wr_pdram_lenght+write_var_num];
|
||||
//
|
||||
//
|
||||
const static uint32_t *spi_rx_reg = &spi_rx_buffer[0];
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Driver Instances
|
||||
// ----------------------------------------------------------------------
|
||||
//static struct timer_task tc_syncro_task;
|
||||
#define SYNC_1kHz_MODULE TC7
|
||||
#define SPI_LAN9252 SERCOM5
|
||||
// ----------------------------------------------------------------------
|
||||
// Callbacks
|
||||
// ----------------------------------------------------------------------
|
||||
// External
|
||||
extern void One_ms_cycle_callback(void);
|
||||
|
||||
// Internal
|
||||
static void transfer_error(struct _dma_resource *resource);
|
||||
static void LAN9252_rx_done(struct _dma_resource *resource);
|
||||
static void LAN9252_rx_susp(struct _dma_resource *resource);
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Interrupt Handlers
|
||||
// ----------------------------------------------------------------------
|
||||
//extern void TC7_Handler(void);
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// functions
|
||||
// ----------------------------------------------------------------------
|
||||
void ethercat_update(void);
|
||||
void config_ethercat_tc(void);
|
||||
void config_ethercat_sercom(void);
|
||||
void configure_dma_resource(void);
|
||||
void configure_ethercat_dma_descriptors(void);
|
||||
static void setup_transfer_descriptor(enum dma_transfer_descriptor_type type, DmacDescriptor *descriptor,
|
||||
const uint32_t start, const uint32_t lenght, const uint32_t next_descriptor, uint16_t block_action);
|
||||
|
||||
|
||||
#endif /* ETHERCAT_E54_H_ */
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* ethercat_slave_buffer.h
|
||||
*
|
||||
* Created: 10/03/2021 13:10:51
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
|
||||
#ifndef ETHERCAT_SLAVE_DEF_H_
|
||||
#define ETHERCAT_SLAVE_DEF_H_
|
||||
|
||||
#include "ethercat_e54.h"
|
||||
|
||||
//Write To Ecat Total Bytes (38 bytes)
|
||||
//write (2 Bytes)
|
||||
static volatile uint8_t *status =&ram_buffer[ram_wr_start];
|
||||
static volatile uint8_t *state =(((uint8_t *)&ram_buffer[ram_wr_start])+1);
|
||||
//Joint (10 Bytes)
|
||||
static volatile int16_t *joint_rel_position =&ram_buffer[ram_wr_start+1];
|
||||
static volatile int16_t *joint_revolution =&ram_buffer[ram_wr_start+2];
|
||||
static volatile int16_t *joint_abs_position =&ram_buffer[ram_wr_start+3];
|
||||
static volatile int16_t *joint_speed =&ram_buffer[ram_wr_start+4];
|
||||
static volatile int16_t *joint_torque =&ram_buffer[ram_wr_start+5];
|
||||
// Motor (24+1+1) = 26
|
||||
static volatile int16_t *motor_rel_revolutions=&ram_buffer[ram_wr_start+6];
|
||||
static volatile int16_t *motor_rel_position =&ram_buffer[ram_wr_start+7];
|
||||
static volatile int16_t *motor_abs_position =&ram_buffer[ram_wr_start+8];
|
||||
static volatile int16_t *motor_dutyCycle =&ram_buffer[ram_wr_start+9];
|
||||
static volatile int16_t *motor_speed =&ram_buffer[ram_wr_start+10];
|
||||
static volatile int16_t *motor_torque =&ram_buffer[ram_wr_start+11];
|
||||
static volatile int16_t *motor_currentPHA =&ram_buffer[ram_wr_start+12];
|
||||
static volatile int16_t *motor_currentPHB =&ram_buffer[ram_wr_start+13];
|
||||
static volatile int16_t *motor_currentPHC =&ram_buffer[ram_wr_start+14];
|
||||
static volatile int16_t *motor_currentBUS =&ram_buffer[ram_wr_start+15];
|
||||
static volatile uint8_t *hall_state =&ram_buffer[ram_wr_start+16];
|
||||
static volatile uint8_t *Spare_byte1 =(((uint8_t *)&ram_buffer[ram_wr_start+16])+1);
|
||||
static volatile int16_t *Spare_1 =&ram_buffer[ram_wr_start+17];
|
||||
static volatile int16_t *Spare_2 =&ram_buffer[ram_wr_start+18];
|
||||
|
||||
//Read From Ecat Total (35 Bytes)
|
||||
// (1 Byte)
|
||||
static volatile uint8_t *control_mode =&ram_buffer[ram_rd_start];
|
||||
static volatile uint8_t *control_set =(((uint8_t *)&ram_buffer[ram_rd_start])+1);
|
||||
// (34 Byte)
|
||||
static volatile int16_t *desired_position =&ram_buffer[ram_rd_start+1];
|
||||
static volatile int16_t *desired_speed =&ram_buffer[ram_rd_start+2];
|
||||
static volatile int16_t *desired_torque =&ram_buffer[ram_rd_start+3];
|
||||
static volatile int16_t *i_kp =&ram_buffer[ram_rd_start+4];
|
||||
static volatile int16_t *i_ki =&ram_buffer[ram_rd_start+5];
|
||||
static volatile int16_t *v_kp =&ram_buffer[ram_rd_start+6];
|
||||
static volatile int16_t *v_kd =&ram_buffer[ram_rd_start+7];
|
||||
static volatile int16_t *p_kp =&ram_buffer[ram_rd_start+8];
|
||||
static volatile int16_t *p_ki =&ram_buffer[ram_rd_start+9];
|
||||
static volatile uint16_t *ReductionRatio =&ram_buffer[ram_rd_start+10];
|
||||
static volatile int16_t *max_torque =&ram_buffer[ram_rd_start+11];
|
||||
static volatile int16_t *max_current =&ram_buffer[ram_rd_start+12];
|
||||
static volatile int16_t *max_velocity =&ram_buffer[ram_rd_start+13];
|
||||
static volatile int16_t *spare1 =&ram_buffer[ram_rd_start+14];
|
||||
static volatile int16_t *spare2 =&ram_buffer[ram_rd_start+15];
|
||||
static volatile int16_t *spare3 =&ram_buffer[ram_rd_start+16];
|
||||
static volatile int16_t *spare4 =&ram_buffer[ram_rd_start+17];
|
||||
|
||||
inline void comms_check(void)
|
||||
{
|
||||
*status = 1;
|
||||
*state = 0;
|
||||
*joint_rel_position = 3;
|
||||
*joint_revolution = 4;
|
||||
*joint_abs_position = 5;
|
||||
*joint_speed = 6;
|
||||
*joint_torque = 7;
|
||||
*motor_rel_revolutions = 8;
|
||||
*motor_rel_position = 9;
|
||||
*motor_abs_position = 10;
|
||||
*motor_dutyCycle = 11;
|
||||
*motor_speed = 12;
|
||||
*motor_torque = 13;
|
||||
*motor_currentPHA = 14;
|
||||
*motor_currentPHB = 15;
|
||||
*motor_currentPHC = 16;
|
||||
*motor_currentBUS = 17;
|
||||
*hall_state = 18;
|
||||
*Spare_byte1 = 19;
|
||||
*Spare_1 = 20;
|
||||
*Spare_2 = 21;
|
||||
}
|
||||
|
||||
inline void clear_comms_buffer(void)
|
||||
{
|
||||
memset(ram_buffer, 0, ram_rd_start);
|
||||
}
|
||||
|
||||
#endif /* ETHERCAT_SLAVE_DEF_H_ */
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
/*
|
||||
* ethercat_e54.c
|
||||
*
|
||||
* Created: 02/03/2021 10:49:41
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Header Files
|
||||
// ----------------------------------------------------------------------
|
||||
#include "atmel_start.h"
|
||||
#include "pins.h"
|
||||
#include "driver_init.h"
|
||||
|
||||
#include "ethercat_e54.h"
|
||||
#include "ethercat_slave_def.h"
|
||||
#include "bldc.h"
|
||||
#include "statemachine.h"
|
||||
#include <string.h>
|
||||
|
||||
|
||||
#define DEBUG_1_PORT PORT_PC01
|
||||
#define DEBUG_2_PORT PORT_PC03
|
||||
#define DEBUG_3_PORT PORT_PC02
|
||||
#define DEBUG_4_PORT PORT_PC30
|
||||
|
||||
|
||||
|
||||
void update_telemetry(void)
|
||||
{
|
||||
inline int16_t convert_to_mA(volatile float32_t current_PU)
|
||||
{
|
||||
return (int16_t)(current_PU*1000);
|
||||
}
|
||||
|
||||
*state = applicationStatus.currentstate;
|
||||
*status = applicationStatus.fault;
|
||||
*motor_rel_position = Motor1.motor_status.Num_Steps;
|
||||
*motor_abs_position = 0;
|
||||
*motor_dutyCycle = Motor1.motor_status.duty_cycle;
|
||||
*motor_speed = (int16_t)Motor1.motor_status.calc_rpm;
|
||||
*motor_torque = 0;
|
||||
*motor_currentPHA = convert_to_mA(Motor1.Iphase_pu.A);
|
||||
*motor_currentPHB = convert_to_mA(Motor1.Iphase_pu.B);
|
||||
*motor_currentPHC = convert_to_mA(Motor1.Iphase_pu.C);
|
||||
*motor_currentBUS = convert_to_mA(Motor1.Iphase_pu.Bus);
|
||||
*hall_state = Motor1.motor_status.currentHallPattern;
|
||||
*Spare_byte1 = Motor1.motor_setpoints.directionOffset;
|
||||
*Spare_1 = Motor1.motor_status.actualDirection;
|
||||
//*Spare_2 = 0;
|
||||
}
|
||||
|
||||
void update_setpoints(void)
|
||||
{
|
||||
inline float32_t convert_int_to_PU(volatile int16_t input)
|
||||
{
|
||||
return ((float32_t)input/1000.0f);
|
||||
}
|
||||
//Motor1.des_mode = 0;
|
||||
//Motor1.set = 0;
|
||||
Motor1.motor_setpoints.desired_position = *desired_position;
|
||||
Motor1.motor_setpoints.desired_speed = *desired_speed;
|
||||
//Motor1.desired_speed = 1500;
|
||||
Motor1.motor_setpoints.desired_torque = convert_int_to_PU(*desired_torque);
|
||||
//Motor1.controllerParam.I_kp = 0;
|
||||
//Motor1.controllerParam.I_ki = 0;
|
||||
//Motor1.controllerParam.V_kp = 0;
|
||||
//Motor1.controllerParam.V_kd = 0;
|
||||
//Motor1.controllerParam.V_kd = 0;
|
||||
//Motor1.controllerParam.P_kp = 0;
|
||||
//Motor1.controllerParam.P_ki = 0;
|
||||
//Motor1.reductionRatio = 0;
|
||||
Motor1.motor_setpoints.max_velocity = *max_velocity;
|
||||
Motor1.motor_setpoints.max_current = convert_int_to_PU(*max_current);
|
||||
Motor1.motor_setpoints.max_torque = convert_int_to_PU(*max_torque);
|
||||
//Motor1.Spare1 = 0;
|
||||
//Motor1.Spare2 = 0;
|
||||
//Motor1.Spare3 = 0;
|
||||
//Motor1.Spare4 = 0;
|
||||
}
|
||||
|
||||
|
||||
extern void One_ms_cycle_callback(void)
|
||||
{
|
||||
tx_ethercat = true;
|
||||
if(tx_ethercat_done){
|
||||
volatile int i=0;
|
||||
//tic_port(DEBUG_3_PORT);
|
||||
//toc_port(DEBUG_3_PORT);
|
||||
|
||||
//memcpy();
|
||||
memcpy(&ram_buffer[ram_real_wr_start], &ram_buffer[ram_wr_start], ram_rd_start);
|
||||
|
||||
//for (i=0;i<ram_rd_start;i++){
|
||||
//ram_buffer[ram_real_wr_start+i] = ram_buffer[ram_wr_start+i];
|
||||
//}
|
||||
//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_rx.channel_id);
|
||||
//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||||
//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_tx.channel_id);
|
||||
//spi_m_dma_transfer(&SPI_0, )
|
||||
//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[1], DMAC_CHCTRLB_CMD_RESUME_Val); //RX Channel
|
||||
//_dma_enable_transaction(1,true);
|
||||
|
||||
gpio_set_pin_level(ECAT_SPI_CS_PIN, false); // SPI_Slave Select LOW
|
||||
DMAC->Channel[0].CHCTRLB.reg = 0x2; // Resume
|
||||
//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||||
/*hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[0], DMAC_CHCTRLB_CMD_RESUME_Val)*/; //TX Channel
DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
tx_ethercat_done = false;
}
else {
gpio_set_pin_level(ECAT_SPI_CS_PIN, true); // SPI_Slave Select HIGH
|
||||
tx_ethercat_done = false;
//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_rx.channel_id);
|
||||
//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||||
//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_tx.channel_id);
//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[1], DMAC_CHCTRLB_CMD_RESUME_Val); //RX Channel
gpio_set_pin_level(ECAT_SPI_CS_PIN, false); // SPI_Slave Select LOW
_dma_enable_transaction(0,false);
//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||||
//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[0], DMAC_CHCTRLB_CMD_RESUME_Val); //TX Channel
_dma_enable_transaction(1,false);
tx_ethercat_done = false;
}
|
||||
|
||||
//toc_port(DEBUG_3_PORT);
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Callbacks
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
static void transfer_error(struct _dma_resource *resource)
|
||||
{
|
||||
uint8_t error = 1;
|
||||
// spi_select_slave(&spi_master_instance, &slave, false);
|
||||
//DMAC->CHID.reg = resource->channel_id;
|
||||
//DMAC->CHCTRLB.bit.CMD = 0x02;
|
||||
//DMAC->CHINTFLAG.bit.SUSP = 1;
|
||||
//responde_spi_master = true;
|
||||
//com_state = com_error;
|
||||
}
|
||||
|
||||
static void LAN9252_rx_done(struct _dma_resource *resource)
|
||||
{
|
||||
gpio_set_pin_level(ECAT_SPI_CS_PIN, true);
|
||||
|
||||
//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_rx.channel_id);
|
||||
//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||||
//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_tx.channel_id);
|
||||
//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[1], DMAC_CHCTRLB_CMD_RESUME_Val); //RX Channel
|
||||
gpio_set_pin_level(ECAT_SPI_CS_PIN, false);
|
||||
//_dma_enable_transaction(0,false);
|
||||
DMAC->Channel[0].CHCTRLB.reg = 0x2; // Resume
|
||||
|
||||
//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||||
//_dma_enable_transaction(1,false); //TX Channel
DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[0], DMAC_CHCTRLB_CMD_RESUME_Val); //TX Channel
tx_ethercat_done = false;
|
||||
//responde_spi_master = true;
|
||||
}
|
||||
|
||||
|
||||
static void LAN9252_rx_susp(struct _dma_resource *resource)
|
||||
{
|
||||
gpio_set_pin_level(ECAT_SPI_CS_PIN, true);
//volatile uint32_t *pointer = ((DMAC->WRBADDR.reg)+0x10*resource->channel_id+12);
volatile uint32_t *pointer = ((DMAC->WRBADDR.reg)+12);
if (*pointer != &spi_rx_write_fifo_dma_descriptor){
//_dma_enable_transaction(0,false);
DMAC->Channel[0].CHCTRLB.reg = 0x2; // Resume
gpio_set_pin_level(ECAT_SPI_CS_PIN, false);
//_dma_enable_transaction(1,false); //TX Channel
DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
tx_ethercat_done = false;
}
else{
tx_ethercat_done = true;
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
void ethercat_update(void)
|
||||
{
|
||||
if (tx_ethercat){
|
||||
tx_ethercat = false;
|
||||
}
|
||||
}
|
||||
|
||||
//void TC7_Handler(void)
|
||||
//{
|
||||
//if (TC7->COUNT16.INTFLAG.bit.OVF == 0x01) {
|
||||
//TC7->COUNT16.INTFLAG.bit.OVF = 0x01;
|
||||
////One_ms_cycle_callback();
|
||||
//
|
||||
//}
|
||||
//}
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// functions
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
void config_ethercat_tc(void)
|
||||
{
|
||||
//tc_syncro_task.interval = 100;
|
||||
//tc_syncro_task.cb = One_ms_cycle_callback;
|
||||
//tc_syncro_task.mode = TIMER_TASK_REPEAT;
|
||||
//timer_add_task(&TC_ECAT, &tc_syncro_task);
|
||||
//timer_start(&TC_ECAT);
|
||||
}
|
||||
|
||||
void config_ethercat_sercom()
|
||||
{
|
||||
|
||||
|
||||
}
|
||||
|
||||
void configure_dma_resource()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
|
||||
void configure_ethercat_dma_descriptors(void)
|
||||
{
|
||||
TC_ECAT_init();
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// DMAC Descriptors
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
// Args = dma_transfer_descriptor_type type, *descriptor, start, lenght, next_descriptor, block_action
|
||||
|
||||
//abort actual_fifo
|
||||
//setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_abort_fifo_dma_descriptor,abort_fifo_start,abort_fifo_length,&spi_config_fifo_dma_descriptor,&spi_LAN9252_instance,DMA_BLOCK_ACTION_SUSPEND);
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX, &spi_abort_fifo_dma_descriptor, abort_fifo_start, abort_fifo_length, &spi_clear_rd_fifo_dma_descriptor, DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
|
||||
//clear initial read data from LAN9252 to avoid errors.
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_clear_rd_fifo_dma_descriptor,wr_pdram_start,wr_pdram_lenght+2*write_var_num,&spi_write_cl_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_write_cl_fifo_dma_descriptor,cl_pdram_start,cl_pdram_lenght,&spi_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
|
||||
// write fifo registers
|
||||
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_write_fifo_dma_descriptor,wr_pdram_start,wr_pdram_lenght,&spi_write2ram_dma_descriptor,DMAC_BTCTRL_BLOCKACT_NOACT_Val); //DMA_BLOCK_ACTION_NOACT
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_write2ram_dma_descriptor,&ram_buffer[ram_real_wr_start],2*write_var_num,&spi_config_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
// write fifo configuration
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_config_fifo_dma_descriptor,cf_pdram_start,cf_pdram_lenght,&spi_read_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
// read fifo registers
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_read_fifo_dma_descriptor,rd_pdram_start,rd_pdram_lenght,&spi_read2ram_dma_descriptor,DMAC_BTCTRL_BLOCKACT_NOACT_Val); //DMA_BLOCK_ACTION_NOACT
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX_DUMMY,&spi_read2ram_dma_descriptor,0,2*read_var_num,&spi_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
//// RX DESCRIPTORS
|
||||
|
||||
// abort fifo
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_abort_fifo_dma_descriptor,0,cf_pdram_lenght,&spi_rx_clear_rd_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
//clear initial read data from LAN9252 to avoid errors.
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_clear_rd_fifo_dma_descriptor,0,wr_pdram_lenght+2*write_var_num,&spi_rx_write_cl_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_write_cl_fifo_dma_descriptor,0,cl_pdram_lenght,&spi_rx_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
// write fifo registers , dummy receive
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_write_fifo_dma_descriptor,0,spi_head+2*write_var_num,&spi_rx_config_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
// write fifo config. dummy receive
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_config_fifo_dma_descriptor,0,cf_pdram_lenght,&spi_rx_read_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
// read fifo registers
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_read_fifo_dma_descriptor,0,spi_head,&spi_rx_read2ram_dma_descriptor,DMAC_BTCTRL_BLOCKACT_NOACT_Val); //DMA_BLOCK_ACTION_NOACT
|
||||
setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX,&spi_rx_read2ram_dma_descriptor,&ram_buffer[ram_rd_start],2*read_var_num,&spi_rx_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val); //DMA_BLOCK_ACTION_SUSPEND
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Register Callbacks
|
||||
// ----------------------------------------------------------------------
|
||||
//spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_RX_DONE, LAN9252_rx_done);
|
||||
//spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_ERROR, transfer_error);
|
||||
spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_SUSPEND, LAN9252_rx_susp);
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Link Descriptors
|
||||
// ----------------------------------------------------------------------
|
||||
_dma_set_descriptor(0, spi_rx_abort_fifo_dma_descriptor);
|
||||
_dma_set_descriptor(1, spi_abort_fifo_dma_descriptor);
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Enable SPI DMA
|
||||
// ----------------------------------------------------------------------
|
||||
spi_m_dma_enable(&SPI_0);
|
||||
// _dma_enable_transaction(&DMAC->Channel[1],true);
|
||||
// _dma_enable_transaction(&DMAC->Channel[0],true);
|
||||
//DMAC->Channel[0].CHCTRLA.bit.ENABLE = true;
|
||||
//DMAC->Channel[1].CHCTRLA.bit.ENABLE = true;
|
||||
|
||||
}
|
||||
|
||||
static void setup_transfer_descriptor(enum dma_transfer_descriptor_type type, DmacDescriptor *descriptor, const uint32_t start,
|
||||
const uint32_t lenght, const uint32_t next_descriptor, uint16_t block_action)
|
||||
{
|
||||
|
||||
/*** DMA RX Descriptor Initialization step by step
|
||||
*** 1- Validate the Descriptor
|
||||
*** 2- Event Output = DMA_EVENT_OUTPUT_BEAT
|
||||
*** 3- block_action = DMA_BLOCK_ACTION_NOACT;
|
||||
*** 4- beat_size = DMA_BEAT_SIZE_BYTE;
|
||||
*** 5- src_increment_enable = false;
|
||||
*** 6- dst_increment_enable = false;
|
||||
*** 7- step_selection = DMA_STEPSEL_DST;
|
||||
*** 8- step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
|
||||
*** 9- block_transfer_count;
|
||||
*** 10- source_address = (uint32_t)NULL;
|
||||
*** 11- destination_address = (uint32_t)NULL;
|
||||
*** 12- next_descriptor_address = 0;
|
||||
***/
|
||||
|
||||
hri_dmacdescriptor_set_BTCTRL_VALID_bit(descriptor); // 1.Validate the Descriptor
|
||||
hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(descriptor, DMAC_BTCTRL_EVOSEL_BURST_Val); // 2. Define mentions 0x3 as Burst, but 0x3 = BEAT (Event strobe when beat transfer complete)
|
||||
hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(descriptor, block_action); // 3. block_action
|
||||
hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(descriptor, DMAC_BTCTRL_BEATSIZE_BYTE_Val); // 4. beat_size
|
||||
|
||||
switch (type){
|
||||
case DMA_TRANSFER_DESCRIPTOR_TX:
|
||||
hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(descriptor, true); // 5. src_increment_enable = true
|
||||
hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(descriptor, false); // 6. dst_increment_enable = false
|
||||
hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(descriptor, start+lenght); // 10. source_address
|
||||
hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(descriptor, (uint32_t)(&SPI_LAN9252->SPI.DATA.reg)); // 11. destination_address
|
||||
break;
|
||||
case DMA_TRANSFER_DESCRIPTOR_TX_DUMMY:
|
||||
hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(descriptor, false); // 5. src_increment_enable = false
|
||||
hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(descriptor, false); // 6. dst_increment_enable = false
|
||||
hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(descriptor, dummy_register); // 10. source_address
|
||||
hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(descriptor, (uint32_t)(&SPI_LAN9252->SPI.DATA.reg)); // 11. destination_address
|
||||
break;
|
||||
case DMA_TRANSFER_DESCRIPTOR_RX:
|
||||
hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(descriptor, false); // 5. src_increment_enable = false
|
||||
hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(descriptor, true); // 6. dst_increment_enable = true
|
||||
hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(descriptor, (uint32_t)(&SPI_LAN9252->SPI.DATA.reg)); // 10. source_address
|
||||
hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(descriptor, start+lenght); // 11. destination_address
|
||||
break;
|
||||
case DMA_TRANSFER_DESCRIPTOR_RX_DUMMY:
|
||||
hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(descriptor, false); // 5. src_increment_enable
|
||||
hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(descriptor, false); // 6. dst_increment_enable = false;
|
||||
hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(descriptor, (uint32_t)(&SPI_LAN9252->SPI.DATA.reg)); // 10. source_address
|
||||
hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(descriptor, &spi_rx_buffer[0]); // 11. destination_address
|
||||
break;
|
||||
}
|
||||
|
||||
hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(descriptor, false); // 7. step_selection = DMA_STEPSEL_DST
|
||||
hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(descriptor, DMAC_BTCTRL_STEPSIZE_X1_Val); // 8. step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1
|
||||
hri_dmacdescriptor_write_BTCNT_BTCNT_bf(descriptor, lenght); // 9. block_transfer_count;
|
||||
hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(descriptor, next_descriptor); // 12. next_descriptor_address = 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,196 @@
|
|||
/*
|
||||
* ethercat_e54.h
|
||||
*
|
||||
* Created: 02/03/2021 10:49:33
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
#ifndef ETHERCAT_E54_H_
|
||||
#define ETHERCAT_E54_H_
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Header Files
|
||||
// ----------------------------------------------------------------------
|
||||
// ----------------------------------------------------------------------
|
||||
// Defines
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Types
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
enum dma_transfer_descriptor_type {
|
||||
DMA_TRANSFER_DESCRIPTOR_TX,
|
||||
DMA_TRANSFER_DESCRIPTOR_RX,
|
||||
DMA_TRANSFER_DESCRIPTOR_TX_DUMMY,
|
||||
DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,
|
||||
};
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Register Addresses
|
||||
// ----------------------------------------------------------------------
|
||||
#define read_var_num 32 //to change to 16bits need to change ecat spi lenght.
|
||||
#define write_var_num 32 //max 20
|
||||
// #define read_var_num 2 //to change to 16bits need to change ecat spi lenght.
|
||||
// #define write_var_num 2 //max 20
|
||||
|
||||
#define ram_wr_start 0
|
||||
#define ram_rd_start write_var_num //write_var_num
|
||||
#define ram_real_wr_start ram_rd_start + read_var_num
|
||||
|
||||
#define SPI_READ 0x03
|
||||
#define SPI_WRITE 0x02
|
||||
#define SPI_INC 0x40
|
||||
#define SPI_DEC 0x80
|
||||
#define TEST_VAL 0x87654321
|
||||
#define CSR_BUSY 0x80000000
|
||||
#define ADDR_BYTES 2
|
||||
#define CSR_READ 1<<30
|
||||
#define CSR_WRITE 0<<30
|
||||
#define CSR_SIZE 4<<16
|
||||
#define CSR_HW_RD 1<<27
|
||||
|
||||
#define ECAT_PRAM_RD_DATA 0x0000
|
||||
#define ECAT_PRAM_WR_DATA 0x2000
|
||||
#define ID_REV 0x5000
|
||||
#define IRQ_CFG 0x5400
|
||||
#define INT_STS 0x5800
|
||||
#define INT_EN 0x5C00
|
||||
#define BYTE_TEST 0x6400
|
||||
#define HW_CFG 0x7400
|
||||
#define PMT_CTRL 0x8400
|
||||
#define GPT_CFG 0x8C00
|
||||
#define GPT_CNT 0x9000
|
||||
#define FREE_RUN 0x9C00
|
||||
#define RESET_CTL 0xF801
|
||||
#define ECAT_CSR_DATA 0x0003
|
||||
#define ECAT_CSR_CMD 0x0403
|
||||
#define ECAT_PRAM_RD_ADDR_LEN 0x0803
|
||||
#define ECAT_PRAM_RD_CMD 0x0C03
|
||||
#define ECAT_PRAM_WR_ADDR_LEN 0x1003
|
||||
#define ECAT_PRAM_WR_CMD 0x1403
|
||||
|
||||
#define PDRAM_RD_ADDRESS 0x1100
|
||||
#define PDRAM_WR_ADDRESS 0x1800
|
||||
|
||||
#define PDRAM_RD_LENGTH 2*read_var_num
|
||||
#define PDRAM_WR_LENGTH 2*write_var_num
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// SPI
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
#define spi_head 3
|
||||
#define hw_tst_length spi_head +4
|
||||
#define by_tst_length spi_head +4
|
||||
#define rd_status_length spi_head +4*4
|
||||
#define abort_fifo_length spi_head +4*4
|
||||
#define cf_pdram_lenght spi_head +4*4
|
||||
#define rd_pdram_lenght spi_head
|
||||
#define wr_pdram_lenght spi_head
|
||||
#define cl_pdram_lenght spi_head +4*2
|
||||
|
||||
#define rd_fifo_lenght
|
||||
#define wr_fifo_lenght
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Flags
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
volatile bool tx_ethercat;
|
||||
volatile bool tx_ethercat_done;
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// DMA descriptors
|
||||
// ----------------------------------------------------------------------
|
||||
COMPILER_ALIGNED(16)
|
||||
DmacDescriptor spi_config_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_read_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_write_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_read2ram_dma_descriptor;
|
||||
DmacDescriptor spi_write2ram_dma_descriptor;
|
||||
DmacDescriptor spi_abort_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_clear_rd_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_write_cl_fifo_dma_descriptor;
|
||||
|
||||
DmacDescriptor spi_rx_config_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_rx_read_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_rx_write_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_rx_read2ram_dma_descriptor;
|
||||
DmacDescriptor spi_rx_abort_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_rx_clear_rd_fifo_dma_descriptor;
|
||||
DmacDescriptor spi_rx_write_cl_fifo_dma_descriptor;
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Global Variables
|
||||
// ----------------------------------------------------------------------
|
||||
volatile uint16_t ram_buffer[(read_var_num+2*write_var_num)];
|
||||
//volatile uint16_t ram_buffer[(read_var_num+2*write_var_num)] = {1,2,3,4,5,6,7,8, 9,10,11,12,13,14,15,16, 17,18,19,20,21,22,23,23, 24,25,26,27,28,29,30,31, 32,33,34,35,36,37,38,39, 40,41,42,43,44,45,46,47,
|
||||
//1,2,3,4,5,6,7,8, 9,10,11,12,13,14,15,16, 17,18,19,20,21,22,23,23, 24,25,26,27,28,29,30,31, 32,33,34,35,36,37,38,39, 40,41,42,43,44,45,46,47};
|
||||
//volatile uint16_t ram_buffer[(read_var_num+2*write_var_num)] = {1,2,3,4,5,6,7,8, 9,10,11,12,13,14,15,16, 17,18,19,20,21,22,23,24 };
|
||||
//1,2,3,4,5,6,7,8, 9,10,11,12,13,14,15,16, 17,18,19,20,21,22,23,23, 24,25,26,27,28,29,30,31, 32,33,34,35,36,37,38,39, 40,41,42,43,44,45,46,47};
|
||||
|
||||
volatile uint8_t spi_rx_buffer[30];
|
||||
|
||||
static uint8_t spi_tx_buffer[110] = {
|
||||
SPI_READ,HW_CFG,HW_CFG>>8,0xFF,0xFF,0xFF,0xFF,
|
||||
SPI_READ,BYTE_TEST,BYTE_TEST>>8,0xFF,0xFF,0xFF,0xFF,
|
||||
SPI_WRITE,ECAT_PRAM_RD_ADDR_LEN | SPI_INC, (ECAT_PRAM_RD_ADDR_LEN | SPI_INC)>>8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,
|
||||
SPI_READ, ECAT_PRAM_RD_ADDR_LEN | SPI_INC, (ECAT_PRAM_RD_ADDR_LEN | SPI_INC)>>8,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
|
||||
SPI_WRITE,ECAT_PRAM_RD_ADDR_LEN | SPI_INC, (ECAT_PRAM_RD_ADDR_LEN | SPI_INC)>>8,PDRAM_RD_ADDRESS,(PDRAM_RD_ADDRESS>>8),PDRAM_RD_LENGTH,PDRAM_RD_LENGTH>>8,0x00,0x00,0x00,CSR_BUSY>>24,PDRAM_WR_ADDRESS,PDRAM_WR_ADDRESS>>8,PDRAM_WR_LENGTH,PDRAM_WR_LENGTH>>8,0x00,0x00,0x00,CSR_BUSY>>24,
|
||||
SPI_READ,ECAT_PRAM_RD_DATA,(ECAT_PRAM_RD_DATA)>>8, //modification for FIFO FIXED
|
||||
SPI_WRITE,ECAT_PRAM_WR_DATA,(ECAT_PRAM_WR_DATA)>>8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
SPI_WRITE,ECAT_PRAM_WR_ADDR_LEN | SPI_INC, (ECAT_PRAM_WR_ADDR_LEN | SPI_INC)>>8,PDRAM_RD_ADDRESS,(PDRAM_RD_ADDRESS>>8),PDRAM_RD_LENGTH,PDRAM_RD_LENGTH>>8,0x00,0x00,0x00,CSR_BUSY>>24};
|
||||
|
||||
|
||||
const static uint32_t dummy_register = &spi_tx_buffer[4];
|
||||
const static uint32_t hw_tst_start = &spi_tx_buffer[0];
|
||||
const static uint32_t by_tst_start = &spi_tx_buffer[0+hw_tst_length];
|
||||
const static uint32_t abort_fifo_start=&spi_tx_buffer[0+hw_tst_length+by_tst_length];
|
||||
const static uint32_t rd_status_start= &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length];
|
||||
const static uint32_t cf_pdram_start = &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length+rd_status_length];
|
||||
const static uint32_t rd_pdram_start = &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length+rd_status_length+cf_pdram_lenght];
|
||||
const static uint32_t wr_pdram_start = &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length+rd_status_length+cf_pdram_lenght+rd_pdram_lenght];
|
||||
volatile static uint32_t cl_pdram_start = &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length+rd_status_length+cf_pdram_lenght+rd_pdram_lenght+wr_pdram_lenght+write_var_num];
|
||||
//
|
||||
//
|
||||
const static uint32_t *spi_rx_reg = &spi_rx_buffer[0];
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Driver Instances
|
||||
// ----------------------------------------------------------------------
|
||||
//static struct timer_task tc_syncro_task;
|
||||
#define SYNC_1kHz_MODULE TC7
|
||||
#define SPI_LAN9252 SERCOM5
|
||||
// ----------------------------------------------------------------------
|
||||
// Callbacks
|
||||
// ----------------------------------------------------------------------
|
||||
// External
|
||||
extern void One_ms_cycle_callback(void);
|
||||
|
||||
// Internal
|
||||
static void transfer_error(struct _dma_resource *resource);
|
||||
static void LAN9252_rx_done(struct _dma_resource *resource);
|
||||
static void LAN9252_rx_susp(struct _dma_resource *resource);
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Interrupt Handlers
|
||||
// ----------------------------------------------------------------------
|
||||
//extern void TC7_Handler(void);
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// functions
|
||||
// ----------------------------------------------------------------------
|
||||
void ethercat_update(void);
|
||||
void config_ethercat_tc(void);
|
||||
void config_ethercat_sercom(void);
|
||||
void configure_dma_resource(void);
|
||||
void configure_ethercat_dma_descriptors(void);
|
||||
static void setup_transfer_descriptor(enum dma_transfer_descriptor_type type, DmacDescriptor *descriptor,
|
||||
const uint32_t start, const uint32_t lenght, const uint32_t next_descriptor, uint16_t block_action);
|
||||
|
||||
|
||||
#endif /* ETHERCAT_E54_H_ */
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* ethercat_slave_buffer.h
|
||||
*
|
||||
* Created: 10/03/2021 13:10:51
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
|
||||
#ifndef ETHERCAT_SLAVE_DEF_H_
|
||||
#define ETHERCAT_SLAVE_DEF_H_
|
||||
|
||||
#include "ethercat_e54.h"
|
||||
|
||||
//Write To Ecat Total Bytes (38 bytes)
|
||||
//write (2 Bytes)
|
||||
static volatile uint8_t *status =&ram_buffer[ram_wr_start];
|
||||
static volatile uint8_t *state =(((uint8_t *)&ram_buffer[ram_wr_start])+1);
|
||||
//Joint (10 Bytes)
|
||||
static volatile int16_t *joint_rel_position =&ram_buffer[ram_wr_start+1];
|
||||
static volatile int16_t *joint_revolution =&ram_buffer[ram_wr_start+2];
|
||||
static volatile int16_t *joint_abs_position =&ram_buffer[ram_wr_start+3];
|
||||
static volatile int16_t *joint_speed =&ram_buffer[ram_wr_start+4];
|
||||
static volatile int16_t *joint_torque =&ram_buffer[ram_wr_start+5];
|
||||
// Motor (24+1+1) = 26
|
||||
static volatile int16_t *motor_rel_revolutions=&ram_buffer[ram_wr_start+6];
|
||||
static volatile int16_t *motor_rel_position =&ram_buffer[ram_wr_start+7];
|
||||
static volatile int16_t *motor_abs_position =&ram_buffer[ram_wr_start+8];
|
||||
static volatile int16_t *motor_dutyCycle =&ram_buffer[ram_wr_start+9];
|
||||
static volatile int16_t *motor_speed =&ram_buffer[ram_wr_start+10];
|
||||
static volatile int16_t *motor_torque =&ram_buffer[ram_wr_start+11];
|
||||
static volatile int16_t *motor_currentPHA =&ram_buffer[ram_wr_start+12];
|
||||
static volatile int16_t *motor_currentPHB =&ram_buffer[ram_wr_start+13];
|
||||
static volatile int16_t *motor_currentPHC =&ram_buffer[ram_wr_start+14];
|
||||
static volatile int16_t *motor_currentBUS =&ram_buffer[ram_wr_start+15];
|
||||
static volatile uint8_t *hall_state =&ram_buffer[ram_wr_start+16];
|
||||
static volatile uint8_t *Spare_byte1 =(((uint8_t *)&ram_buffer[ram_wr_start+16])+1);
|
||||
static volatile int16_t *Spare_1 =&ram_buffer[ram_wr_start+17];
|
||||
static volatile int16_t *Spare_2 =&ram_buffer[ram_wr_start+18];
|
||||
|
||||
//Read From Ecat Total (35 Bytes)
|
||||
// (1 Byte)
|
||||
static volatile uint8_t *control_mode =&ram_buffer[ram_rd_start];
|
||||
static volatile uint8_t *control_set =(((uint8_t *)&ram_buffer[ram_rd_start])+1);
|
||||
// (34 Byte)
|
||||
static volatile int16_t *desired_position =&ram_buffer[ram_rd_start+1];
|
||||
static volatile int16_t *desired_speed =&ram_buffer[ram_rd_start+2];
|
||||
static volatile int16_t *desired_torque =&ram_buffer[ram_rd_start+3];
|
||||
static volatile int16_t *i_kp =&ram_buffer[ram_rd_start+4];
|
||||
static volatile int16_t *i_ki =&ram_buffer[ram_rd_start+5];
|
||||
static volatile int16_t *v_kp =&ram_buffer[ram_rd_start+6];
|
||||
static volatile int16_t *v_kd =&ram_buffer[ram_rd_start+7];
|
||||
static volatile int16_t *p_kp =&ram_buffer[ram_rd_start+8];
|
||||
static volatile int16_t *p_ki =&ram_buffer[ram_rd_start+9];
|
||||
static volatile uint16_t *ReductionRatio =&ram_buffer[ram_rd_start+10];
|
||||
static volatile int16_t *max_torque =&ram_buffer[ram_rd_start+11];
|
||||
static volatile int16_t *max_current =&ram_buffer[ram_rd_start+12];
|
||||
static volatile int16_t *max_velocity =&ram_buffer[ram_rd_start+13];
|
||||
static volatile int16_t *spare1 =&ram_buffer[ram_rd_start+14];
|
||||
static volatile int16_t *spare2 =&ram_buffer[ram_rd_start+15];
|
||||
static volatile int16_t *spare3 =&ram_buffer[ram_rd_start+16];
|
||||
static volatile int16_t *spare4 =&ram_buffer[ram_rd_start+17];
|
||||
|
||||
inline void comms_check(void)
|
||||
{
|
||||
*status = 1;
|
||||
*state = 0;
|
||||
*joint_rel_position = 3;
|
||||
*joint_revolution = 4;
|
||||
*joint_abs_position = 5;
|
||||
*joint_speed = 6;
|
||||
*joint_torque = 7;
|
||||
*motor_rel_revolutions = 8;
|
||||
*motor_rel_position = 9;
|
||||
*motor_abs_position = 10;
|
||||
*motor_dutyCycle = 11;
|
||||
*motor_speed = 12;
|
||||
*motor_torque = 13;
|
||||
*motor_currentPHA = 14;
|
||||
*motor_currentPHB = 15;
|
||||
*motor_currentPHC = 16;
|
||||
*motor_currentBUS = 17;
|
||||
*hall_state = 18;
|
||||
*Spare_byte1 = 19;
|
||||
*Spare_1 = 20;
|
||||
*Spare_2 = 21;
|
||||
}
|
||||
|
||||
inline void clear_comms_buffer(void)
|
||||
{
|
||||
memset(ram_buffer, 0, ram_rd_start);
|
||||
}
|
||||
|
||||
#endif /* ETHERCAT_SLAVE_DEF_H_ */
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
|
||||
#include "driver_examples.h"
|
||||
#include "driver_init.h"
|
||||
#include "utils.h"
|
||||
|
||||
/**
|
||||
* Example of using SPI_MS_IF to write "Hello World" using the IO abstraction.
|
||||
*
|
||||
* Since the driver is asynchronous we need to use statically allocated memory for string
|
||||
* because driver initiates transfer and then returns before the transmission is completed.
|
||||
*
|
||||
* Once transfer has been completed the tx_cb function will be called.
|
||||
*/
|
||||
|
||||
static uint8_t example_SPI_MS_IF[12] = "Hello World!";
|
||||
|
||||
static void tx_complete_cb_SPI_MS_IF(struct _dma_resource *resource)
|
||||
{
|
||||
/* Transfer completed */
|
||||
}
|
||||
|
||||
void SPI_MS_IF_example(void)
|
||||
{
|
||||
struct io_descriptor *io;
|
||||
spi_m_dma_get_io_descriptor(&SPI_MS_IF, &io);
|
||||
|
||||
spi_m_dma_register_callback(&SPI_MS_IF, SPI_M_DMA_CB_TX_DONE, tx_complete_cb_SPI_MS_IF);
|
||||
spi_m_dma_enable(&SPI_MS_IF);
|
||||
io_write(io, example_SPI_MS_IF, 12);
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using SPI_0 to write "Hello World" using the IO abstraction.
|
||||
*
|
||||
* Since the driver is asynchronous we need to use statically allocated memory for string
|
||||
* because driver initiates transfer and then returns before the transmission is completed.
|
||||
*
|
||||
* Once transfer has been completed the tx_cb function will be called.
|
||||
*/
|
||||
|
||||
static uint8_t example_SPI_0[12] = "Hello World!";
|
||||
|
||||
static void tx_complete_cb_SPI_0(struct _dma_resource *resource)
|
||||
{
|
||||
/* Transfer completed */
|
||||
}
|
||||
|
||||
void SPI_0_example(void)
|
||||
{
|
||||
struct io_descriptor *io;
|
||||
spi_m_dma_get_io_descriptor(&SPI_0, &io);
|
||||
|
||||
spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_TX_DONE, tx_complete_cb_SPI_0);
|
||||
spi_m_dma_enable(&SPI_0);
|
||||
io_write(io, example_SPI_0, 12);
|
||||
}
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef DRIVER_EXAMPLES_H_INCLUDED
|
||||
#define DRIVER_EXAMPLES_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void SPI_MS_IF_example(void);
|
||||
|
||||
void SPI_0_example(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif // DRIVER_EXAMPLES_H_INCLUDED
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
===================
|
||||
Event system driver
|
||||
===================
|
||||
|
||||
Event system allows autonomous, low-latency and configurable communication between peripherals.
|
||||
|
||||
Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition
|
||||
to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that
|
||||
respond to events are event users, peripherals that generate events are called event generators. A peripheral can have
|
||||
one or more event generators and can have one or more event users.
|
||||
|
||||
Communication is made without CPU intervention and without consuming system resources such as bus or RAM bandwidth. This
|
||||
reduces the load on the CPU and system resources, compared to a traditional interrupt-based system.
|
||||
|
||||
The Event System consists of several channels which route the internal events from generators
|
||||
to users. Each event generator can be selected as source for multiple channels, but a channel cannot
|
||||
be set to use multiple event generators at the same time.
|
||||
|
||||
Event system driver allows to configure event system of an MCU.
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
- Event channel configuration is static
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
The SPI Master DMA Driver
|
||||
==================================
|
||||
|
||||
The serial peripheral interface (SPI) is a DMA serial communication
|
||||
interface.
|
||||
|
||||
The SPI Master DMA driver uses DMA system to transfer data from
|
||||
a memory buffer to SPI (Memory to Peripheral), and receive data
|
||||
from SPI to a memory buffer (Peripheral to Memory).User must configure
|
||||
DMA system driver accordingly. A callback is called when all the data
|
||||
is transfered or all the data is received, if it is registered via
|
||||
spi_m_dma_register_callback function.
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
* Initialization/de-initialization
|
||||
* Enabling/disabling
|
||||
* Control of the following settings:
|
||||
|
||||
* Baudrate
|
||||
* SPI mode
|
||||
* Character size
|
||||
* Data order
|
||||
* Data transfer: transmission, reception and full-duplex
|
||||
* Notifications about transfer completion and errors via callbacks
|
||||
|
||||
Applications
|
||||
------------
|
||||
|
||||
Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card,
|
||||
LCD controller, etc.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
SPI master capable hardware and DMA hardware, with data sent/received.
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
When only uses DMA channel to receive data, the transfer channel must enable to
|
||||
send dummy data to the slave.
|
||||
|
||||
While read/write/transfer is in progress, the data buffer used must be kept
|
||||
unchanged.
|
||||
|
||||
Known issues and workarounds
|
||||
----------------------------
|
||||
|
||||
N/A
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Critical sections related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_ATOMIC_H_INCLUDED
|
||||
#define _HAL_ATOMIC_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_helper_atomic
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Type for the register holding global interrupt enable flag
|
||||
*/
|
||||
typedef uint32_t hal_atomic_t;
|
||||
|
||||
/**
|
||||
* \brief Helper macro for entering critical sections
|
||||
*
|
||||
* This macro is recommended to be used instead of a direct call
|
||||
* hal_enterCritical() function to enter critical
|
||||
* sections. No semicolon is required after the macro.
|
||||
*
|
||||
* \section atomic_usage Usage Example
|
||||
* \code
|
||||
* CRITICAL_SECTION_ENTER()
|
||||
* Critical code
|
||||
* CRITICAL_SECTION_LEAVE()
|
||||
* \endcode
|
||||
*/
|
||||
#define CRITICAL_SECTION_ENTER() \
|
||||
{ \
|
||||
volatile hal_atomic_t __atomic; \
|
||||
atomic_enter_critical(&__atomic);
|
||||
|
||||
/**
|
||||
* \brief Helper macro for leaving critical sections
|
||||
*
|
||||
* This macro is recommended to be used instead of a direct call
|
||||
* hal_leaveCritical() function to leave critical
|
||||
* sections. No semicolon is required after the macro.
|
||||
*/
|
||||
#define CRITICAL_SECTION_LEAVE() \
|
||||
atomic_leave_critical(&__atomic); \
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable interrupts, enter critical section
|
||||
*
|
||||
* Disables global interrupts. Supports nested critical sections,
|
||||
* so that global interrupts are only re-enabled
|
||||
* upon leaving the outermost nested critical section.
|
||||
*
|
||||
* \param[out] atomic The pointer to a variable to store the value of global
|
||||
* interrupt enable flag
|
||||
*/
|
||||
void atomic_enter_critical(hal_atomic_t volatile *atomic);
|
||||
|
||||
/**
|
||||
* \brief Exit atomic section
|
||||
*
|
||||
* Enables global interrupts. Supports nested critical sections,
|
||||
* so that global interrupts are only re-enabled
|
||||
* upon leaving the outermost nested critical section.
|
||||
*
|
||||
* \param[in] atomic The pointer to a variable, which stores the latest stored
|
||||
* value of the global interrupt enable flag
|
||||
*/
|
||||
void atomic_leave_critical(hal_atomic_t volatile *atomic);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t atomic_get_version(void);
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_ATOMIC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL cache functionality implementation.
|
||||
*
|
||||
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef HAL_CACHE_H_
|
||||
#define HAL_CACHE_H_
|
||||
|
||||
#include <hpl_cmcc.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Enable cache module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of cache module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_enable(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Disable cache module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of cache module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_disable(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Initialize cache module
|
||||
*
|
||||
* This function initialize cache module configuration.
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_init(void);
|
||||
|
||||
/**
|
||||
* \brief Configure cache module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of cache module
|
||||
* \param[in] cache configuration structure pointer
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
|
||||
|
||||
/**
|
||||
* \brief Invalidate entire cache entries
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of cache module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_invalidate_all(const void *hw);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_CACHE_H_ */
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL delay related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include <hpl_irq.h>
|
||||
#include <hpl_reset.h>
|
||||
#include <hpl_sleep.h>
|
||||
|
||||
#ifndef _HAL_DELAY_H_INCLUDED
|
||||
#define _HAL_DELAY_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_delay Delay Driver
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize Delay driver
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*/
|
||||
void delay_init(void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Perform delay in us
|
||||
*
|
||||
* This function performs delay for the given amount of microseconds.
|
||||
*
|
||||
* \param[in] us The amount delay in us
|
||||
*/
|
||||
void delay_us(const uint16_t us);
|
||||
|
||||
/**
|
||||
* \brief Perform delay in ms
|
||||
*
|
||||
* This function performs delay for the given amount of milliseconds.
|
||||
*
|
||||
* \param[in] ms The amount delay in ms
|
||||
*/
|
||||
void delay_ms(const uint16_t ms);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t delay_get_version(void);
|
||||
|
||||
/**@}*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HAL_DELAY_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL event system related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include <hpl_evsys.h>
|
||||
|
||||
#ifndef _HAL_EVSYS_H_INCLUDED
|
||||
#define _HAL_EVSYS_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_evsys
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize event system.
|
||||
*
|
||||
* \return Initialization status.
|
||||
*/
|
||||
int32_t event_system_init(void);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize event system.
|
||||
*
|
||||
* \return De-initialization status.
|
||||
*/
|
||||
int32_t event_system_deinit(void);
|
||||
|
||||
/**
|
||||
* \brief Enable event reception by the given user from the given channel
|
||||
*
|
||||
* \param[in] user A user to enable
|
||||
* \param[in] channel A channel the user is assigned to
|
||||
*
|
||||
* \return Status of operation.
|
||||
*/
|
||||
int32_t event_system_enable_user(const uint16_t user, const uint16_t channel);
|
||||
|
||||
/**
|
||||
* \brief Disable event reception by the given user from the given channel
|
||||
*
|
||||
* \param[in] user A user to disable
|
||||
* \param[in] channel A channel the user is assigned to
|
||||
*
|
||||
* \return Status of operation.
|
||||
*/
|
||||
int32_t event_system_disable_user(const uint16_t user, const uint16_t channel);
|
||||
|
||||
/**
|
||||
* \brief Enable event generation by the given generator for the given channel
|
||||
*
|
||||
* \param[in] generator A generator to disable
|
||||
* \param[in] channel A channel the generator is assigned to
|
||||
*
|
||||
* \return Status of operation.
|
||||
*/
|
||||
int32_t event_system_enable_generator(const uint16_t generator, const uint16_t channel);
|
||||
|
||||
/**
|
||||
* \brief Disable event generation by the given generator for the given channel
|
||||
*
|
||||
* \param[in] generator A generator to disable
|
||||
* \param[in] channel A channel the generator is assigned to
|
||||
*
|
||||
* \return Status of operation.
|
||||
*/
|
||||
int32_t event_system_disable_generator(const uint16_t generator, const uint16_t channel);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t event_system_get_version(void);
|
||||
|
||||
/**@}*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HAL_EVSYS_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,201 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Port
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*/
|
||||
#ifndef _HAL_GPIO_INCLUDED_
|
||||
#define _HAL_GPIO_INCLUDED_
|
||||
|
||||
#include <hpl_gpio.h>
|
||||
#include <utils_assert.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Set gpio pull mode
|
||||
*
|
||||
* Set pin pull mode, non existing pull modes throws an fatal assert
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
* \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor
|
||||
* GPIO_PULL_UP = Pull pin high with internal resistor
|
||||
* GPIO_PULL_OFF = Disable pin pull mode
|
||||
*/
|
||||
static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode)
|
||||
{
|
||||
_gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set pin function
|
||||
*
|
||||
* Select which function a pin will be used for
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
* \param[in] function The pin function is given by a 32-bit wide bitfield
|
||||
* found in the header files for the device
|
||||
*
|
||||
*/
|
||||
static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
|
||||
{
|
||||
_gpio_set_pin_function(pin, function);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set port data direction
|
||||
*
|
||||
* Select if the pin data direction is input, output or disabled.
|
||||
* If disabled state is not possible, this function throws an assert.
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply direction setting to the
|
||||
* corresponding pin
|
||||
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
|
||||
* GPIO_DIRECTION_OUT = Data direction out
|
||||
* GPIO_DIRECTION_OFF = Disables the pin
|
||||
* (low power state)
|
||||
*/
|
||||
static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask,
|
||||
const enum gpio_direction direction)
|
||||
{
|
||||
_gpio_set_direction(port, mask, direction);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set gpio data direction
|
||||
*
|
||||
* Select if the pin data direction is input, output or disabled.
|
||||
* If disabled state is not possible, this function throws an assert.
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
|
||||
* GPIO_DIRECTION_OUT = Data direction out
|
||||
* GPIO_DIRECTION_OFF = Disables the pin
|
||||
* (low power state)
|
||||
*/
|
||||
static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
|
||||
{
|
||||
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set port level
|
||||
*
|
||||
* Sets output level on the pins defined by the bit mask
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply port level to the corresponding
|
||||
* pin
|
||||
* \param[in] level true = Pin levels set to "high" state
|
||||
* false = Pin levels set to "low" state
|
||||
*/
|
||||
static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level)
|
||||
{
|
||||
_gpio_set_level(port, mask, level);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set gpio level
|
||||
*
|
||||
* Sets output level on a pin
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
* \param[in] level true = Pin level set to "high" state
|
||||
* false = Pin level set to "low" state
|
||||
*/
|
||||
static inline void gpio_set_pin_level(const uint8_t pin, const bool level)
|
||||
{
|
||||
_gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Toggle out level on pins
|
||||
*
|
||||
* Toggle the pin levels on pins defined by bit mask
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means toggle pin level to the corresponding
|
||||
* pin
|
||||
*/
|
||||
static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask)
|
||||
{
|
||||
_gpio_toggle_level(port, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Toggle output level on pin
|
||||
*
|
||||
* Toggle the pin levels on pins defined by bit mask
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
*/
|
||||
static inline void gpio_toggle_pin_level(const uint8_t pin)
|
||||
{
|
||||
_gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get input level on pins
|
||||
*
|
||||
* Read the input level on pins connected to a port
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
*/
|
||||
static inline uint32_t gpio_get_port_level(const enum gpio_port port)
|
||||
{
|
||||
return _gpio_get_level(port);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get level on pin
|
||||
*
|
||||
* Reads the level on pins connected to a port
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
*/
|
||||
static inline bool gpio_get_pin_level(const uint8_t pin)
|
||||
{
|
||||
return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
|
||||
}
|
||||
/**
|
||||
* \brief Get current driver version
|
||||
*/
|
||||
uint32_t gpio_get_version(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL initialization related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_INIT_H_INCLUDED
|
||||
#define _HAL_INIT_H_INCLUDED
|
||||
|
||||
#include <hpl_init.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_helper_init Init Driver
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize the hardware abstraction layer
|
||||
*
|
||||
* This function calls the various initialization functions.
|
||||
* Currently the following initialization functions are supported:
|
||||
* - System clock initialization
|
||||
*/
|
||||
static inline void init_mcu(void)
|
||||
{
|
||||
_init_chip();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t init_get_version(void);
|
||||
|
||||
/**@}*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HAL_INIT_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I/O related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_IO_INCLUDED
|
||||
#define _HAL_IO_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_helper_io I/O Driver
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief I/O descriptor
|
||||
*
|
||||
* The I/O descriptor forward declaration.
|
||||
*/
|
||||
struct io_descriptor;
|
||||
|
||||
/**
|
||||
* \brief I/O write function pointer type
|
||||
*/
|
||||
typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief I/O read function pointer type
|
||||
*/
|
||||
typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief I/O descriptor
|
||||
*/
|
||||
struct io_descriptor {
|
||||
io_write_t write; /*! The write function pointer. */
|
||||
io_read_t read; /*! The read function pointer. */
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief I/O write interface
|
||||
*
|
||||
* This function writes up to \p length of bytes to a given I/O descriptor.
|
||||
* It returns the number of bytes actually write.
|
||||
*
|
||||
* \param[in] descr An I/O descriptor to write
|
||||
* \param[in] buf The buffer pointer to story the write data
|
||||
* \param[in] length The number of bytes to write
|
||||
*
|
||||
* \return The number of bytes written
|
||||
*/
|
||||
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief I/O read interface
|
||||
*
|
||||
* This function reads up to \p length bytes from a given I/O descriptor, and
|
||||
* stores it in the buffer pointed to by \p buf. It returns the number of bytes
|
||||
* actually read.
|
||||
*
|
||||
* \param[in] descr An I/O descriptor to read
|
||||
* \param[in] buf The buffer pointer to story the read data
|
||||
* \param[in] length The number of bytes to read
|
||||
*
|
||||
* \return The number of bytes actually read. This number can be less than the
|
||||
* requested length. E.g., in a driver that uses ring buffer for
|
||||
* reception, it may depend on the availability of data in the
|
||||
* ring buffer.
|
||||
*/
|
||||
int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HAL_IO_INCLUDED */
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Sleep related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_SLEEP_H_INCLUDED
|
||||
#define _HAL_SLEEP_H_INCLUDED
|
||||
|
||||
#include <hpl_sleep.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_helper_sleep
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Set the sleep mode of the device and put the MCU to sleep
|
||||
*
|
||||
* For an overview of which systems are disabled in sleep for the different
|
||||
* sleep modes, see the data sheet.
|
||||
*
|
||||
* \param[in] mode Sleep mode to use
|
||||
*
|
||||
* \return The status of a sleep request
|
||||
* \retval -1 The requested sleep mode was invalid or not available
|
||||
* \retval 0 The operation completed successfully, returned after leaving the
|
||||
* sleep
|
||||
*/
|
||||
int sleep(const uint8_t mode);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t sleep_get_version(void);
|
||||
/**@}*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HAL_SLEEP_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SPI DMA related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_SPI_M_DMA_H_INCLUDED
|
||||
#define _HAL_SPI_M_DMA_H_INCLUDED
|
||||
|
||||
#include <hal_io.h>
|
||||
#include <hpl_spi_m_dma.h>
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_spi_master_dma
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Forward declaration of spi_descriptor. */
|
||||
struct spi_m_dma_descriptor;
|
||||
|
||||
/** The callback types */
|
||||
enum spi_m_dma_cb_type {
|
||||
/** Callback type for DMA transfer buffer done */
|
||||
SPI_M_DMA_CB_TX_DONE,
|
||||
/** Callback type for DMA receive buffer done */
|
||||
SPI_M_DMA_CB_RX_DONE,
|
||||
/** Callback type for DMA errors */
|
||||
SPI_M_DMA_CB_ERROR,
|
||||
SPI_M_DMA_CB_N,
|
||||
SPI_M_DMA_CB_SUSPEND
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief SPI Master DMA callback type
|
||||
*/
|
||||
typedef void (*spi_m_dma_cb_t)(struct _dma_resource *resource);
|
||||
|
||||
/** \brief SPI HAL driver struct for DMA access
|
||||
*/
|
||||
struct spi_m_dma_descriptor {
|
||||
struct _spi_m_dma_hpl_interface *func;
|
||||
/** Pointer to SPI device instance */
|
||||
struct _spi_m_dma_dev dev;
|
||||
/** I/O read/write */
|
||||
struct io_descriptor io;
|
||||
/** DMA resource */
|
||||
struct _dma_resource *resource;
|
||||
};
|
||||
|
||||
/** \brief Set the SPI HAL instance function pointer for HPL APIs.
|
||||
*
|
||||
* Set SPI HAL instance function pointer for HPL APIs.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] func Pointer to the HPL api structure.
|
||||
*
|
||||
*/
|
||||
void spi_m_dma_set_func_ptr(struct spi_m_dma_descriptor *spi, void *const func);
|
||||
|
||||
/** \brief Initialize the SPI HAL instance and hardware for DMA mode
|
||||
*
|
||||
* Initialize SPI HAL with dma mode.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] hw Pointer to the hardware base.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_INVALID_DATA Error, initialized.
|
||||
*/
|
||||
int32_t spi_m_dma_init(struct spi_m_dma_descriptor *spi, void *const hw);
|
||||
|
||||
/** \brief Deinitialize the SPI HAL instance
|
||||
*
|
||||
* Abort transfer, disable and reset SPI, de-init software.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval <0 Error code.
|
||||
*/
|
||||
void spi_m_dma_deinit(struct spi_m_dma_descriptor *spi);
|
||||
|
||||
/** \brief Enable SPI
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval <0 Error code.
|
||||
*/
|
||||
void spi_m_dma_enable(struct spi_m_dma_descriptor *spi);
|
||||
|
||||
/** \brief Disable SPI
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval <0 Error code.
|
||||
*/
|
||||
void spi_m_dma_disable(struct spi_m_dma_descriptor *spi);
|
||||
|
||||
/** \brief Set SPI baudrate
|
||||
*
|
||||
* Works if SPI is initialized as master.
|
||||
* In the function a sanity check is used to confirm it's called in the correct mode.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] baud_val The target baudrate value
|
||||
* (See "baudrate calculation" for calculating the value).
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy.
|
||||
*
|
||||
* note: This api should be used to write the baudrate register with the given baud_val
|
||||
* paramter, the user has to calculate the baud_val for required baud rate and pass it as
|
||||
* argument(baud_val) to this api
|
||||
*/
|
||||
int32_t spi_m_dma_set_baudrate(struct spi_m_dma_descriptor *spi, const uint32_t baud_val);
|
||||
|
||||
/** \brief Set SPI mode
|
||||
*
|
||||
* Set SPI transfer mode (\ref spi_transfer_mode),
|
||||
* which controls clock polarity and clock phase:
|
||||
* - Mode 0: leading edge is rising edge, data sample on leading edge.
|
||||
* - Mode 1: leading edge is rising edge, data sample on trailing edge.
|
||||
* - Mode 2: leading edge is falling edge, data sample on leading edge.
|
||||
* - Mode 3: leading edge is falling edge, data sample on trailing edge.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] mode The mode (\ref spi_transfer_mode).
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy, CS activated.
|
||||
*/
|
||||
int32_t spi_m_dma_set_mode(struct spi_m_dma_descriptor *spi, const enum spi_transfer_mode mode);
|
||||
|
||||
/** \brief Set the SPI transfer character size in number of bits
|
||||
*
|
||||
* The character size (\ref spi_char_size) influence the way the data is
|
||||
* sent/received.
|
||||
* For char size <= 8-bit, data is stored byte by byte.
|
||||
* For char size between 9-bit ~ 16-bit, data is stored in 2-byte length.
|
||||
* Note that the default and recommended char size is 8-bit since it's
|
||||
* supported by all system.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] char_size The char size (\ref spi_char_size).
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy, CS activated.
|
||||
* \retval ERR_INVALID_ARG The char size is not supported.
|
||||
*/
|
||||
int32_t spi_m_dma_set_char_size(struct spi_m_dma_descriptor *spi, const enum spi_char_size char_size);
|
||||
|
||||
/** \brief Set SPI transfer data order
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] dord The data order: send LSB/MSB first.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy, CS activated.
|
||||
* \retval ERR_INVALID The data order is not supported.
|
||||
*/
|
||||
int32_t spi_m_dma_set_data_order(struct spi_m_dma_descriptor *spi, const enum spi_data_order dord);
|
||||
|
||||
/** \brief Perform the SPI data transfer (TX and RX) with the DMA
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] txbuf Pointer to the transfer information.
|
||||
* \param[out] rxbuf Pointer to the receiver information.
|
||||
* \param[in] length SPI transfer data length.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy.
|
||||
*/
|
||||
int32_t spi_m_dma_transfer(struct spi_m_dma_descriptor *spi, uint8_t const *txbuf, uint8_t *const rxbuf,
|
||||
const uint16_t length);
|
||||
|
||||
/** \brief Register a function as an SPI transfer completion callback
|
||||
*
|
||||
* Register a callback function specified by its \c type.
|
||||
* - SPI_CB_COMPLETE: set the function that will be called on the SPI transfer
|
||||
* completion including deactivating the CS.
|
||||
* - SPI_CB_XFER: set the function that will be called on the SPI buffer transfer
|
||||
* completion.
|
||||
* Register a NULL function to not use the callback.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] type Callback type (\ref spi_m_dma_cb_type).
|
||||
* \param[in] func Pointer to callback function.
|
||||
*/
|
||||
void spi_m_dma_register_callback(struct spi_m_dma_descriptor *spi, const enum spi_m_dma_cb_type type,
|
||||
spi_m_dma_cb_t func);
|
||||
|
||||
/**
|
||||
* \brief Return I/O descriptor for this SPI instance
|
||||
*
|
||||
* This function will return an I/O instance for this SPI driver instance
|
||||
*
|
||||
* \param[in] spi An SPI master descriptor, which is used to communicate through
|
||||
* SPI
|
||||
* \param[in, out] io A pointer to an I/O descriptor pointer type
|
||||
*
|
||||
* \retval ERR_NONE
|
||||
*/
|
||||
int32_t spi_m_dma_get_io_descriptor(struct spi_m_dma_descriptor *const spi, struct io_descriptor **io);
|
||||
|
||||
/** \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t spi_m_dma_get_version(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* ifndef _HAL_SPI_M_DMA_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,277 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Generic CMCC(Cortex M Cache Controller) related functionality.
|
||||
*
|
||||
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef HPL_CMCC_H_
|
||||
#define HPL_CMCC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/**
|
||||
* \Cache driver MACROS
|
||||
*/
|
||||
#define CMCC_DISABLE 0U
|
||||
#define CMCC_ENABLE 1U
|
||||
#define IS_CMCC_DISABLED 0U
|
||||
#define IS_CMCC_ENABLED 1U
|
||||
#define CMCC_WAY_NOS 4U
|
||||
#define CMCC_LINE_NOS 64U
|
||||
#define CMCC_MONITOR_DISABLE 0U
|
||||
|
||||
/**
|
||||
* \brief Cache size configurations
|
||||
*/
|
||||
enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB };
|
||||
|
||||
/**
|
||||
* \brief Way Numbers
|
||||
*/
|
||||
enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 };
|
||||
|
||||
/**
|
||||
* \brief Cache monitor configurations
|
||||
*/
|
||||
enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT };
|
||||
|
||||
/**
|
||||
* \brief Cache configuration structure
|
||||
*/
|
||||
struct _cache_cfg {
|
||||
enum conf_cache_size cache_size;
|
||||
bool data_cache_disable;
|
||||
bool inst_cache_disable;
|
||||
bool gclk_gate_disable;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Cache enable status
|
||||
*/
|
||||
static inline bool _is_cache_enabled(const void *hw)
|
||||
{
|
||||
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Cache disable status
|
||||
*/
|
||||
static inline bool _is_cache_disabled(const void *hw)
|
||||
{
|
||||
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Cache enable
|
||||
*/
|
||||
static inline int32_t _cmcc_enable(const void *hw)
|
||||
{
|
||||
int32_t return_value;
|
||||
|
||||
if (_is_cache_disabled(hw)) {
|
||||
hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN);
|
||||
return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE;
|
||||
} else {
|
||||
return_value = ERR_NO_CHANGE;
|
||||
}
|
||||
|
||||
return return_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Cache disable
|
||||
*/
|
||||
static inline int32_t _cmcc_disable(const void *hw)
|
||||
{
|
||||
hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos));
|
||||
while (!(_is_cache_disabled(hw)))
|
||||
;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Initialize Cache Module
|
||||
*
|
||||
* This function initialize low level cmcc module configuration.
|
||||
*
|
||||
* \return initialize status
|
||||
*/
|
||||
int32_t _cmcc_init(void);
|
||||
|
||||
/**
|
||||
* \brief Configure CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] cache configuration structure pointer
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl);
|
||||
|
||||
/**
|
||||
* \brief Enable data cache in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_enable_data_cache(const void *hw, bool value);
|
||||
|
||||
/**
|
||||
* \brief Enable instruction cache in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_enable_inst_cache(const void *hw, bool value);
|
||||
|
||||
/**
|
||||
* \brief Enable clock gating in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_enable_clock_gating(const void *hw, bool value);
|
||||
|
||||
/**
|
||||
* \brief Configure the cache size in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from cache size configuration enumerator
|
||||
* 0->1K, 1->2K, 2->4K(default)
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size);
|
||||
|
||||
/**
|
||||
* \brief Lock the mentioned WAY in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from "way_num_index" enumerator
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_lock_way(const void *hw, enum way_num_index);
|
||||
|
||||
/**
|
||||
* \brief Unlock the mentioned WAY in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from "way_num_index" enumerator
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_unlock_way(const void *hw, enum way_num_index);
|
||||
|
||||
/**
|
||||
* \brief Invalidate the mentioned cache line in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from "way_num" enumerator (valid arg is 0-3)
|
||||
* \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num);
|
||||
|
||||
/**
|
||||
* \brief Invalidate entire cache entries in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_invalidate_all(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Configure cache monitor in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from cache monitor configurations enumerator
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg);
|
||||
|
||||
/**
|
||||
* \brief Enable cache monitor in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_enable_monitor(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Disable cache monitor in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_disable_monitor(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Reset cache monitor in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_reset_monitor(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Get cache monitor event counter value from CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return event counter value
|
||||
*/
|
||||
uint32_t _cmcc_get_monitor_event_count(const void *hw);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HPL_CMCC_H_ */
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief CPU core related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_CORE_H_INCLUDED
|
||||
#define _HPL_CORE_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Core
|
||||
*
|
||||
* \section hpl_core_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include "hpl_core_port.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_CORE_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Delay related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_DELAY_H_INCLUDED
|
||||
#define _HPL_DELAY_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Delay
|
||||
*
|
||||
* \section hpl_delay_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifndef _UNIT_TEST_
|
||||
#include <compiler.h>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
|
||||
/**
|
||||
* \brief Initialize delay functionality
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*/
|
||||
void _delay_init(void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the amount of cycles to delay for the given amount of us
|
||||
*
|
||||
* \param[in] us The amount of us to delay for
|
||||
*
|
||||
* \return The amount of cycles
|
||||
*/
|
||||
uint32_t _get_cycles_for_us(const uint16_t us);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the amount of cycles to delay for the given amount of ms
|
||||
*
|
||||
* \param[in] ms The amount of ms to delay for
|
||||
*
|
||||
* \return The amount of cycles
|
||||
*/
|
||||
uint32_t _get_cycles_for_ms(const uint16_t ms);
|
||||
|
||||
/**
|
||||
* \brief Delay loop to delay n number of cycles
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
* \param[in] cycles The amount of cycles to delay for
|
||||
*/
|
||||
void _delay_cycles(void *const hw, uint32_t cycles);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_DELAY_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,182 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief DMA related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_DMA_H_INCLUDED
|
||||
#define _HPL_DMA_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL DMA
|
||||
*
|
||||
* \section hpl_dma_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include <hpl_irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct _dma_resource;
|
||||
|
||||
/**
|
||||
* \brief DMA callback types
|
||||
*/
|
||||
|
||||
enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB, DMA_SUSPEND_CB };
|
||||
|
||||
/**
|
||||
* \brief DMA interrupt callbacks
|
||||
*/
|
||||
struct _dma_callbacks {
|
||||
void (*transfer_done)(struct _dma_resource *resource);
|
||||
void (*error)(struct _dma_resource *resource);
|
||||
void (*suspend)(struct _dma_resource *resource);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief DMA resource structure
|
||||
*/
|
||||
struct _dma_resource {
|
||||
struct _dma_callbacks dma_cb;
|
||||
void * back;
|
||||
};
|
||||
|
||||
/** ADDED */
|
||||
int32_t _dma_set_descriptor(const uint8_t channel, const DmacDescriptor descriptor);
|
||||
|
||||
|
||||
/**
|
||||
* \brief Initialize DMA
|
||||
*
|
||||
* This function does low level DMA configuration.
|
||||
*
|
||||
* \return initialize status
|
||||
*/
|
||||
int32_t _dma_init(void);
|
||||
|
||||
/**
|
||||
* \brief Set destination address
|
||||
*
|
||||
* \param[in] channel DMA channel to set destination address for
|
||||
* \param[in] dst Destination address
|
||||
*
|
||||
* \return setting status
|
||||
*/
|
||||
int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst);
|
||||
|
||||
/**
|
||||
* \brief Set source address
|
||||
*
|
||||
* \param[in] channel DMA channel to set source address for
|
||||
* \param[in] src Source address
|
||||
*
|
||||
* \return setting status
|
||||
*/
|
||||
int32_t _dma_set_source_address(const uint8_t channel, const void *const src);
|
||||
|
||||
/**
|
||||
* \brief Set next descriptor address
|
||||
*
|
||||
* \param[in] current_channel Current DMA channel to set next descriptor address
|
||||
* \param[in] next_channel Next DMA channel used as next descriptor
|
||||
*
|
||||
* \return setting status
|
||||
*/
|
||||
int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable source address incrementation during DMA transaction
|
||||
*
|
||||
* \param[in] channel DMA channel to set source address for
|
||||
* \param[in] enable True to enable, false to disable
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable Destination address incrementation during DMA transaction
|
||||
*
|
||||
* \param[in] channel DMA channel to set destination address for
|
||||
* \param[in] enable True to enable, false to disable
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable);
|
||||
/**
|
||||
* \brief Set the amount of data to be transfered per transaction
|
||||
*
|
||||
* \param[in] channel DMA channel to set data amount for
|
||||
* \param[in] amount Data amount
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount);
|
||||
|
||||
/**
|
||||
* \brief Trigger DMA transaction on the given channel
|
||||
*
|
||||
* \param[in] channel DMA channel to trigger transaction on
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger);
|
||||
|
||||
/**
|
||||
* \brief Retrieves DMA resource structure
|
||||
*
|
||||
* \param[out] resource The resource to be retrieved
|
||||
* \param[in] channel DMA channel to retrieve structure for
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable DMA interrupt
|
||||
*
|
||||
* \param[in] channel DMA channel to enable/disable interrupt for
|
||||
* \param[in] type The type of interrupt to disable/enable if applicable
|
||||
* \param[in] state Enable or disable
|
||||
*/
|
||||
void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HPL_DMA_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Event system related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_EVSYS_H_INCLUDED
|
||||
#define _HPL_EVSYS_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL EVSYS
|
||||
*
|
||||
* \section hpl_eveys_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Initialize event system.
|
||||
*
|
||||
* \return Status of operation.
|
||||
*/
|
||||
int32_t _event_system_init(void);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize event system.
|
||||
*
|
||||
* \return Status of operation.
|
||||
*/
|
||||
int32_t _event_system_deinit(void);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable event reception by the given user from the given
|
||||
* channel
|
||||
*
|
||||
* \param[in] user A user to enable
|
||||
* \param[in] channel A channel the user is assigned to
|
||||
* \param[in] on true to enable, false to disable
|
||||
*
|
||||
* \return Status of operation.
|
||||
*/
|
||||
int32_t _event_system_enable_user(const uint16_t user, const uint16_t channel, const bool on);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable event generation by the given generator for the given
|
||||
* channel
|
||||
*
|
||||
* \param[in] generator A generator to enable
|
||||
* \param[in] channel A channel the user is assigned to
|
||||
* \param[in] on true to enable, false to disable
|
||||
*
|
||||
* \return Status of operation.
|
||||
*/
|
||||
int32_t _event_system_enable_generator(const uint16_t generator, const uint16_t channel, const bool on);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_EVSYS_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Port related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_GPIO_H_INCLUDED
|
||||
#define _HPL_GPIO_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Port
|
||||
*
|
||||
* \section hpl_port_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/**
|
||||
* \brief Macros for the pin and port group, lower 5
|
||||
* bits stands for pin number in the group, higher 3
|
||||
* bits stands for port group
|
||||
*/
|
||||
#define GPIO_PIN(n) (((n)&0x1Fu) << 0)
|
||||
#define GPIO_PORT(n) ((n) >> 5)
|
||||
#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu))
|
||||
#define GPIO_PIN_FUNCTION_OFF 0xffffffff
|
||||
|
||||
/**
|
||||
* \brief PORT pull mode settings
|
||||
*/
|
||||
enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN };
|
||||
|
||||
/**
|
||||
* \brief PORT direction settins
|
||||
*/
|
||||
enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT };
|
||||
|
||||
/**
|
||||
* \brief PORT group abstraction
|
||||
*/
|
||||
|
||||
enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE };
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Port initialization function
|
||||
*
|
||||
* Port initialization function should setup the port module based
|
||||
* on a static configuration file, this function should normally
|
||||
* not be called directly, but is a part of hal_init()
|
||||
*/
|
||||
void _gpio_init(void);
|
||||
|
||||
/**
|
||||
* \brief Set direction on port with mask
|
||||
*
|
||||
* Set data direction for each pin, or disable the pin
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply direction setting to the
|
||||
* corresponding pin
|
||||
* \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input
|
||||
* and disable input buffer to disable the pin
|
||||
* GPIO_DIRECTION_IN = set pin direction to input
|
||||
* and enable input buffer to enable the pin
|
||||
* GPIO_DIRECTION_OUT = set pin direction to output
|
||||
* and disable input buffer
|
||||
*/
|
||||
static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
|
||||
const enum gpio_direction direction);
|
||||
|
||||
/**
|
||||
* \brief Set output level on port with mask
|
||||
*
|
||||
* Sets output state on pin to high or low with pin masking
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply direction setting to
|
||||
* the corresponding pin
|
||||
* \param[in] level true = pin level is set to 1
|
||||
* false = pin level is set to 0
|
||||
*/
|
||||
static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level);
|
||||
|
||||
/**
|
||||
* \brief Change output level to the opposite with mask
|
||||
*
|
||||
* Change pin output level to the opposite with pin masking
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply direction setting to
|
||||
* the corresponding pin
|
||||
*/
|
||||
static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask);
|
||||
|
||||
/**
|
||||
* \brief Get input levels on all port pins
|
||||
*
|
||||
* Get input level on all port pins, will read IN register if configured to
|
||||
* input and OUT register if configured as output
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
*/
|
||||
static inline uint32_t _gpio_get_level(const enum gpio_port port);
|
||||
|
||||
/**
|
||||
* \brief Set pin pull mode
|
||||
*
|
||||
* Set pull mode on a single pin
|
||||
*
|
||||
* \notice This function will automatically change pin direction to input
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] pin The pin in the group that pull mode should be selected
|
||||
* for
|
||||
* \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled
|
||||
* GPIO_PULL_DOWN = pull resistor on pin will pull pin
|
||||
* level to ground level
|
||||
* GPIO_PULL_UP = pull resistor on pin will pull pin
|
||||
* level to VCC
|
||||
*/
|
||||
static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
|
||||
const enum gpio_pull_mode pull_mode);
|
||||
|
||||
/**
|
||||
* \brief Set gpio function
|
||||
*
|
||||
* Select which function a gpio is used for
|
||||
*
|
||||
* \param[in] gpio The gpio to set function for
|
||||
* \param[in] function The gpio function is given by a 32-bit wide bitfield
|
||||
* found in the header files for the device
|
||||
*
|
||||
*/
|
||||
static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function);
|
||||
|
||||
#include <hpl_gpio_base.h>
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_GPIO_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED
|
||||
#define _HPL_I2C_M_ASYNC_H_INCLUDED
|
||||
|
||||
#include "hpl_i2c_m_sync.h"
|
||||
#include "hpl_irq.h"
|
||||
#include "utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief i2c master callback names
|
||||
*/
|
||||
enum _i2c_m_async_callback_type {
|
||||
I2C_M_ASYNC_DEVICE_ERROR,
|
||||
I2C_M_ASYNC_DEVICE_TX_COMPLETE,
|
||||
I2C_M_ASYNC_DEVICE_RX_COMPLETE
|
||||
};
|
||||
|
||||
struct _i2c_m_async_device;
|
||||
|
||||
typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev);
|
||||
typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode);
|
||||
|
||||
/**
|
||||
* \brief i2c callback pointers structure
|
||||
*/
|
||||
struct _i2c_m_async_callback {
|
||||
_i2c_error_cb_t error;
|
||||
_i2c_complete_cb_t tx_complete;
|
||||
_i2c_complete_cb_t rx_complete;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief i2c device structure
|
||||
*/
|
||||
struct _i2c_m_async_device {
|
||||
struct _i2c_m_service service;
|
||||
void * hw;
|
||||
struct _i2c_m_async_callback cb;
|
||||
struct _irq_descriptor irq;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize I2C in interrupt mode
|
||||
*
|
||||
* This function does low level I2C configuration.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c interrupt device structure
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize I2C in interrupt mode
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Enable I2C module
|
||||
*
|
||||
* This function does low level I2C enable.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Disable I2C module
|
||||
*
|
||||
* This function does low level I2C disable.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Transfer data by I2C
|
||||
*
|
||||
* This function does low level I2C data transfer.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] msg The pointer to i2c msg structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg);
|
||||
|
||||
/**
|
||||
* \brief Set baud rate of I2C
|
||||
*
|
||||
* This function does low level I2C set baud rate.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] clkrate The clock rate(KHz) input to i2c module
|
||||
* \param[in] baudrate The demand baud rate(KHz) of i2c module
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
|
||||
|
||||
/**
|
||||
* \brief Register callback to I2C
|
||||
*
|
||||
* This function does low level I2C callback register.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] cb_type The callback type request
|
||||
* \param[in] func The callback function pointer
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type,
|
||||
FUNC_PTR func);
|
||||
|
||||
/**
|
||||
* \brief Generate stop condition on the I2C bus
|
||||
*
|
||||
* This function will generate a stop condition on the I2C bus
|
||||
*
|
||||
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
|
||||
*
|
||||
* \return Operation status
|
||||
* \retval 0 Operation executed successfully
|
||||
* \retval <0 Operation failed
|
||||
*/
|
||||
int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Returns the number of bytes left or not used in the I2C message buffer
|
||||
*
|
||||
* This function will return the number of bytes left (not written to the bus) or still free
|
||||
* (not received from the bus) in the message buffer, depending on direction of transmission.
|
||||
*
|
||||
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
|
||||
*
|
||||
* \return Number of bytes or error code
|
||||
* \retval >0 Positive number indicating bytes left
|
||||
* \retval 0 Buffer is full/empty depending on direction
|
||||
* \retval <0 Error code
|
||||
*/
|
||||
int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable I2C master interrupt
|
||||
*
|
||||
* param[in] device The pointer to I2C master device instance
|
||||
* param[in] type The type of interrupt to disable/enable if applicable
|
||||
* param[in] state Enable or disable
|
||||
*/
|
||||
void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type,
|
||||
const bool state);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_I2C_M_SYNC_H_INCLUDED
|
||||
#define _HPL_I2C_M_SYNC_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief i2c flags
|
||||
*/
|
||||
#define I2C_M_RD 0x0001 /* read data, from slave to master */
|
||||
#define I2C_M_BUSY 0x0100
|
||||
#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */
|
||||
#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */
|
||||
#define I2C_M_FAIL 0x1000
|
||||
#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
|
||||
|
||||
/**
|
||||
* \brief i2c Return codes
|
||||
*/
|
||||
#define I2C_OK 0 /* Operation successful */
|
||||
#define I2C_ACK -1 /* Received ACK from device on I2C bus */
|
||||
#define I2C_NACK -2 /* Received NACK from device on I2C bus */
|
||||
#define I2C_ERR_ARBLOST -3 /* Arbitration lost */
|
||||
#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */
|
||||
#define I2C_ERR_BUS -5 /* Bus error */
|
||||
#define I2C_ERR_BUSY -6 /* Device busy */
|
||||
#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */
|
||||
|
||||
/**
|
||||
* \brief i2c I2C Modes
|
||||
*/
|
||||
#define I2C_STANDARD_MODE 0x00
|
||||
#define I2C_FASTMODE 0x01
|
||||
#define I2C_HIGHSPEED_MODE 0x02
|
||||
|
||||
/**
|
||||
* \brief i2c master message structure
|
||||
*/
|
||||
struct _i2c_m_msg {
|
||||
uint16_t addr;
|
||||
volatile uint16_t flags;
|
||||
int32_t len;
|
||||
uint8_t * buffer;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief i2c master service
|
||||
*/
|
||||
struct _i2c_m_service {
|
||||
struct _i2c_m_msg msg;
|
||||
uint16_t mode;
|
||||
uint16_t trise;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief i2c sync master device structure
|
||||
*/
|
||||
struct _i2c_m_sync_device {
|
||||
struct _i2c_m_service service;
|
||||
void * hw;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize I2C
|
||||
*
|
||||
* This function does low level I2C configuration.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize I2C
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Enable I2C module
|
||||
*
|
||||
* This function does low level I2C enable.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Disable I2C module
|
||||
*
|
||||
* This function does low level I2C disable.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Transfer data by I2C
|
||||
*
|
||||
* This function does low level I2C data transfer.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] msg The pointer to i2c msg structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg);
|
||||
|
||||
/**
|
||||
* \brief Set baud rate of I2C
|
||||
*
|
||||
* This function does low level I2C set baud rate.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] clkrate The clock rate(KHz) input to i2c module
|
||||
* \param[in] baudrate The demand baud rate(KHz) of i2c module
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
|
||||
|
||||
/**
|
||||
* \brief Send send condition on the I2C bus
|
||||
*
|
||||
* This function will generate a stop condition on the I2C bus
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device struct
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED
|
||||
#define _HPL_I2C_S_ASYNC_H_INCLUDED
|
||||
|
||||
#include "hpl_i2c_s_sync.h"
|
||||
#include "hpl_irq.h"
|
||||
#include "utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief i2c callback types
|
||||
*/
|
||||
enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE };
|
||||
|
||||
/**
|
||||
* \brief Forward declaration of I2C Slave device
|
||||
*/
|
||||
struct _i2c_s_async_device;
|
||||
|
||||
/**
|
||||
* \brief i2c slave callback function type
|
||||
*/
|
||||
typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device);
|
||||
|
||||
/**
|
||||
* \brief i2c slave callback pointers structure
|
||||
*/
|
||||
struct _i2c_s_async_callback {
|
||||
void (*error)(struct _i2c_s_async_device *const device);
|
||||
void (*tx)(struct _i2c_s_async_device *const device);
|
||||
void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief i2c slave device structure
|
||||
*/
|
||||
struct _i2c_s_async_device {
|
||||
void * hw;
|
||||
struct _i2c_s_async_callback cb;
|
||||
struct _irq_descriptor irq;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize asynchronous I2C slave
|
||||
*
|
||||
* This function does low level I2C configuration.
|
||||
*
|
||||
* \param[in] device The pointer to i2c interrupt device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize asynchronous I2C in interrupt mode
|
||||
*
|
||||
* \param[in] device The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable I2C module
|
||||
*
|
||||
* This function does low level I2C enable.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Disable I2C module
|
||||
*
|
||||
* This function does low level I2C disable.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if 10-bit addressing mode is on
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Cheking status
|
||||
* \retval 1 10-bit addressing mode is on
|
||||
* \retval 0 10-bit addressing mode is off
|
||||
*/
|
||||
int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set I2C slave address
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
* \param[in] address Address to set
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address);
|
||||
|
||||
/**
|
||||
* \brief Write a byte to the given I2C instance
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
* \param[in] data Data to write
|
||||
*/
|
||||
void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data);
|
||||
|
||||
/**
|
||||
* \brief Retrieve I2C slave status
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
*\return I2C slave status
|
||||
*/
|
||||
i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Abort data transmission
|
||||
*
|
||||
* \param[in] device The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable I2C slave interrupt
|
||||
*
|
||||
* param[in] device The pointer to I2C slave device instance
|
||||
* param[in] type The type of interrupt to disable/enable if applicable
|
||||
* param[in] disable Enable or disable
|
||||
*/
|
||||
int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type,
|
||||
const bool disable);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_I2C_S_SYNC_H_INCLUDED
|
||||
#define _HPL_I2C_S_SYNC_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief I2C Slave status type
|
||||
*/
|
||||
typedef uint32_t i2c_s_status_t;
|
||||
|
||||
/**
|
||||
* \brief i2c slave device structure
|
||||
*/
|
||||
struct _i2c_s_sync_device {
|
||||
void *hw;
|
||||
};
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize synchronous I2C slave
|
||||
*
|
||||
* This function does low level I2C configuration.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize synchronous I2C slave
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable I2C module
|
||||
*
|
||||
* This function does low level I2C enable.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Disable I2C module
|
||||
*
|
||||
* This function does low level I2C disable.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if 10-bit addressing mode is on
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Cheking status
|
||||
* \retval 1 10-bit addressing mode is on
|
||||
* \retval 0 10-bit addressing mode is off
|
||||
*/
|
||||
int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set I2C slave address
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
* \param[in] address Address to set
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address);
|
||||
|
||||
/**
|
||||
* \brief Write a byte to the given I2C instance
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
* \param[in] data Data to write
|
||||
*/
|
||||
void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data);
|
||||
|
||||
/**
|
||||
* \brief Retrieve I2C slave status
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
*\return I2C slave status
|
||||
*/
|
||||
i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Clear the Data Ready interrupt flag
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Read a byte from the given I2C instance
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Data received via I2C interface.
|
||||
*/
|
||||
uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if I2C is ready to send next byte
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Status of the ready check.
|
||||
* \retval true if the I2C is ready to send next byte
|
||||
* \retval false if the I2C is not ready to send next byte
|
||||
*/
|
||||
bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if there is data received by I2C
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Status of the data received check.
|
||||
* \retval true if the I2C has received a byte
|
||||
* \retval false if the I2C has not received a byte
|
||||
*/
|
||||
bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Init related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_INIT_H_INCLUDED
|
||||
#define _HPL_INIT_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Init
|
||||
*
|
||||
* \section hpl_init_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initializes clock sources
|
||||
*/
|
||||
void _sysctrl_init_sources(void);
|
||||
|
||||
/**
|
||||
* \brief Initializes Power Manager
|
||||
*/
|
||||
void _pm_init(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize generators
|
||||
*/
|
||||
void _gclk_init_generators(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize 32 kHz clock sources
|
||||
*/
|
||||
void _osc32kctrl_init_sources(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock sources
|
||||
*/
|
||||
void _oscctrl_init_sources(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock sources that need input reference clocks
|
||||
*/
|
||||
void _sysctrl_init_referenced_generators(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock sources that need input reference clocks
|
||||
*/
|
||||
void _oscctrl_init_referenced_generators(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize master clock generator
|
||||
*/
|
||||
void _mclk_init(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock generator
|
||||
*/
|
||||
void _lpmcu_misc_regs_init(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock generator
|
||||
*/
|
||||
void _pmc_init(void);
|
||||
|
||||
/**
|
||||
* \brief Set performance level
|
||||
*
|
||||
* \param[in] level The performance level to set
|
||||
*/
|
||||
void _set_performance_level(const uint8_t level);
|
||||
|
||||
/**
|
||||
* \brief Initialize the chip
|
||||
*/
|
||||
void _init_chip(void);
|
||||
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_INIT_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief IRQ related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_IRQ_H_INCLUDED
|
||||
#define _HPL_IRQ_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL IRQ
|
||||
*
|
||||
* \section hpl_irq_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief IRQ descriptor
|
||||
*/
|
||||
struct _irq_descriptor {
|
||||
void (*handler)(void *parameter);
|
||||
void *parameter;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Retrieve current IRQ number
|
||||
*
|
||||
* \return The current IRQ number
|
||||
*/
|
||||
uint8_t _irq_get_current(void);
|
||||
|
||||
/**
|
||||
* \brief Disable the given IRQ
|
||||
*
|
||||
* \param[in] n The number of IRQ to disable
|
||||
*/
|
||||
void _irq_disable(uint8_t n);
|
||||
|
||||
/**
|
||||
* \brief Set the given IRQ
|
||||
*
|
||||
* \param[in] n The number of IRQ to set
|
||||
*/
|
||||
void _irq_set(uint8_t n);
|
||||
|
||||
/**
|
||||
* \brief Clear the given IRQ
|
||||
*
|
||||
* \param[in] n The number of IRQ to clear
|
||||
*/
|
||||
void _irq_clear(uint8_t n);
|
||||
|
||||
/**
|
||||
* \brief Enable the given IRQ
|
||||
*
|
||||
* \param[in] n The number of IRQ to enable
|
||||
*/
|
||||
void _irq_enable(uint8_t n);
|
||||
|
||||
/**
|
||||
* \brief Register IRQ handler
|
||||
*
|
||||
* \param[in] number The number registered IRQ
|
||||
* \param[in] irq The pointer to irq handler to register
|
||||
*
|
||||
* \return The status of IRQ handler registering
|
||||
* \retval -1 Passed parameters were invalid
|
||||
* \retval 0 The registering is completed successfully
|
||||
*/
|
||||
void _irq_register(const uint8_t number, struct _irq_descriptor *const irq);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_IRQ_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Family-dependent missing features expected by HAL
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_MISSING_FEATURES
|
||||
#define _HPL_MISSING_FEATURES
|
||||
|
||||
#endif /* _HPL_MISSING_FEATURES */
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief RAMECC related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_RAMECC_H_INCLUDED
|
||||
#define _HPL_RAMECC_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL RAMECC
|
||||
*
|
||||
* \section hpl_ramecc_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include <hpl_irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief RAMECC callback type
|
||||
*/
|
||||
typedef void (*ramecc_cb_t)(const uint32_t data);
|
||||
|
||||
/**
|
||||
* \brief RAMECC callback types
|
||||
*/
|
||||
enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB };
|
||||
|
||||
/**
|
||||
* \brief RAMECC interrupt callbacks
|
||||
*/
|
||||
struct _ramecc_callbacks {
|
||||
ramecc_cb_t dual_bit_err;
|
||||
ramecc_cb_t single_bit_err;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief RAMECC device structure
|
||||
*/
|
||||
struct _ramecc_device {
|
||||
struct _ramecc_callbacks ramecc_cb;
|
||||
struct _irq_descriptor irq;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize RAMECC
|
||||
*
|
||||
* This function does low level RAMECC configuration.
|
||||
*
|
||||
* \return initialize status
|
||||
*/
|
||||
int32_t _ramecc_init(void);
|
||||
|
||||
/**
|
||||
* \brief Register RAMECC callback
|
||||
*
|
||||
* \param[in] type The type of callback
|
||||
* \param[in] cb A callback function
|
||||
*/
|
||||
void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HPL_RAMECC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Reset related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_RESET_H_INCLUDED
|
||||
#define _HPL_RESET_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Reset
|
||||
*
|
||||
* \section hpl_reset_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifndef _UNIT_TEST_
|
||||
#include <compiler.h>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Reset reason enumeration
|
||||
*
|
||||
* The list of possible reset reasons.
|
||||
*/
|
||||
enum reset_reason {
|
||||
RESET_REASON_POR = 1,
|
||||
RESET_REASON_BOD12 = 2,
|
||||
RESET_REASON_BOD33 = 4,
|
||||
RESET_REASON_NVM = 8,
|
||||
RESET_REASON_EXT = 16,
|
||||
RESET_REASON_WDT = 32,
|
||||
RESET_REASON_SYST = 64,
|
||||
RESET_REASON_BACKUP = 128
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Retrieve the reset reason
|
||||
*
|
||||
* Retrieves the reset reason of the last MCU reset.
|
||||
*
|
||||
*\return An enum value indicating the reason of the last reset.
|
||||
*/
|
||||
enum reset_reason _get_reset_reason(void);
|
||||
|
||||
/**
|
||||
* \brief Reset MCU
|
||||
*/
|
||||
void _reset_mcu(void);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_RESET_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Sleep related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_SLEEP_H_INCLUDED
|
||||
#define _HPL_SLEEP_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Sleep
|
||||
*
|
||||
* \section hpl_sleep_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifndef _UNIT_TEST_
|
||||
#include <compiler.h>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Set the sleep mode for the device
|
||||
*
|
||||
* This function sets the sleep mode for the device.
|
||||
* For an overview of which systems are disabled in sleep for the different
|
||||
* sleep modes see datasheet.
|
||||
*
|
||||
* \param[in] mode Sleep mode to use
|
||||
*
|
||||
* \return the status of a sleep request
|
||||
* \retval -1 The requested sleep mode was invalid
|
||||
* \retval 0 The operation completed successfully, sleep mode is set
|
||||
*/
|
||||
int32_t _set_sleep_mode(const uint8_t mode);
|
||||
|
||||
/**
|
||||
* \brief Reset MCU
|
||||
*/
|
||||
void _reset_mcu(void);
|
||||
|
||||
/**
|
||||
* \brief Put MCU to sleep
|
||||
*/
|
||||
void _go_to_sleep(void);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_SLEEP_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SPI related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_SPI_H_INCLUDED
|
||||
#define _HPL_SPI_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
#include <utils.h>
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_spi HPL SPI
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief SPI Dummy char is used when reading data from the SPI slave
|
||||
*/
|
||||
#define SPI_DUMMY_CHAR 0x1ff
|
||||
|
||||
/**
|
||||
* \brief SPI message to let driver to process
|
||||
*/
|
||||
//@{
|
||||
struct spi_msg {
|
||||
/** Pointer to the output data buffer */
|
||||
uint8_t *txbuf;
|
||||
/** Pointer to the input data buffer */
|
||||
uint8_t *rxbuf;
|
||||
/** Size of the message data in SPI characters */
|
||||
uint32_t size;
|
||||
};
|
||||
//@}
|
||||
|
||||
/**
|
||||
* \brief SPI transfer modes
|
||||
* SPI transfer mode controls clock polarity and clock phase.
|
||||
* Mode 0: leading edge is rising edge, data sample on leading edge.
|
||||
* Mode 1: leading edge is rising edge, data sample on trailing edge.
|
||||
* Mode 2: leading edge is falling edge, data sample on leading edge.
|
||||
* Mode 3: leading edge is falling edge, data sample on trailing edge.
|
||||
*/
|
||||
enum spi_transfer_mode {
|
||||
/** Leading edge is rising edge, data sample on leading edge. */
|
||||
SPI_MODE_0,
|
||||
/** Leading edge is rising edge, data sample on trailing edge. */
|
||||
SPI_MODE_1,
|
||||
/** Leading edge is falling edge, data sample on leading edge. */
|
||||
SPI_MODE_2,
|
||||
/** Leading edge is falling edge, data sample on trailing edge. */
|
||||
SPI_MODE_3
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief SPI character sizes
|
||||
* The character size influence the way the data is sent/received.
|
||||
* For char size <= 8 data is stored byte by byte.
|
||||
* For char size between 9 ~ 16 data is stored in 2-byte length.
|
||||
* Note that the default and recommended char size is 8 bit since it's
|
||||
* supported by all system.
|
||||
*/
|
||||
enum spi_char_size {
|
||||
/** Character size is 8 bit. */
|
||||
SPI_CHAR_SIZE_8 = 0,
|
||||
/** Character size is 9 bit. */
|
||||
SPI_CHAR_SIZE_9 = 1,
|
||||
/** Character size is 10 bit. */
|
||||
SPI_CHAR_SIZE_10 = 2,
|
||||
/** Character size is 11 bit. */
|
||||
SPI_CHAR_SIZE_11 = 3,
|
||||
/** Character size is 12 bit. */
|
||||
SPI_CHAR_SIZE_12 = 4,
|
||||
/** Character size is 13 bit. */
|
||||
SPI_CHAR_SIZE_13 = 5,
|
||||
/** Character size is 14 bit. */
|
||||
SPI_CHAR_SIZE_14 = 6,
|
||||
/** Character size is 15 bit. */
|
||||
SPI_CHAR_SIZE_15 = 7,
|
||||
/** Character size is 16 bit. */
|
||||
SPI_CHAR_SIZE_16 = 8
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief SPI data order
|
||||
*/
|
||||
enum spi_data_order {
|
||||
/** MSB goes first. */
|
||||
SPI_DATA_ORDER_MSB_1ST = 0,
|
||||
/** LSB goes first. */
|
||||
SPI_DATA_ORDER_LSB_1ST = 1
|
||||
};
|
||||
|
||||
/** \brief Transfer descriptor for SPI
|
||||
* Transfer descriptor holds TX and RX buffers
|
||||
*/
|
||||
struct spi_xfer {
|
||||
/** Pointer to data buffer to TX */
|
||||
uint8_t *txbuf;
|
||||
/** Pointer to data buffer to RX */
|
||||
uint8_t *rxbuf;
|
||||
/** Size of data characters to TX & RX */
|
||||
uint32_t size;
|
||||
};
|
||||
|
||||
/** SPI generic driver. */
|
||||
struct spi_dev {
|
||||
/** Pointer to the hardware base or private data for special device. */
|
||||
void *prvt;
|
||||
/** Reference start of sync/async variables */
|
||||
uint32_t sync_async_misc[1];
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Calculate the baudrate value for hardware to use to set baudrate
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] clk Clock frequency (Hz) for baudrate generation.
|
||||
* \param[in] baud Target baudrate (bps).
|
||||
* \return Error or baudrate value.
|
||||
* \retval >0 Baudrate value.
|
||||
* \retval ERR_INVALID_ARG Calculation fail.
|
||||
*/
|
||||
int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_SPI_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Common SPI related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_SPI_ASYNC_H_INCLUDED
|
||||
#define _HPL_SPI_ASYNC_H_INCLUDED
|
||||
|
||||
#include <hpl_spi.h>
|
||||
#include <hpl_irq.h>
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_spi HPL SPI
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Callbacks the SPI driver must offer in async mode
|
||||
*/
|
||||
//@{
|
||||
/** The callback types */
|
||||
enum _spi_async_dev_cb_type {
|
||||
/** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */
|
||||
SPI_DEV_CB_TX,
|
||||
/** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */
|
||||
SPI_DEV_CB_RX,
|
||||
/** Callback type for \ref _spi_async_dev_cb_complete_t. */
|
||||
SPI_DEV_CB_COMPLETE,
|
||||
/** Callback type for error */
|
||||
SPI_DEV_CB_ERROR,
|
||||
/** Number of callbacks. */
|
||||
SPI_DEV_CB_N
|
||||
};
|
||||
|
||||
struct _spi_async_dev;
|
||||
|
||||
/** \brief The prototype for callback on SPI transfer error.
|
||||
* If status code is zero, it indicates the normal completion, that is,
|
||||
* SS deactivation.
|
||||
* If status code belows zero, it indicates complete.
|
||||
*/
|
||||
typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status);
|
||||
|
||||
/** \brief The prototype for callback on SPI transmit/receive event
|
||||
* For TX, the callback is invoked when transmit is done or ready to start
|
||||
* transmit.
|
||||
* For RX, the callback is invoked when receive is done or ready to read data,
|
||||
* see \ref _spi_async_dev_read_one_t on data reading.
|
||||
* Without DMA enabled, the callback is invoked on each character event.
|
||||
* With DMA enabled, the callback is invoked on DMA buffer done.
|
||||
*/
|
||||
typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief The callbacks offered by SPI driver
|
||||
*/
|
||||
struct _spi_async_dev_callbacks {
|
||||
/** TX callback, see \ref _spi_async_dev_cb_xfer_t. */
|
||||
_spi_async_dev_cb_xfer_t tx;
|
||||
/** RX callback, see \ref _spi_async_dev_cb_xfer_t. */
|
||||
_spi_async_dev_cb_xfer_t rx;
|
||||
/** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */
|
||||
_spi_async_dev_cb_xfer_t complete;
|
||||
/** Error callback, see \ref */
|
||||
_spi_async_dev_cb_error_t err;
|
||||
};
|
||||
//@}
|
||||
|
||||
/**
|
||||
* \brief SPI async driver
|
||||
*/
|
||||
//@{
|
||||
|
||||
/** SPI driver to support async HAL */
|
||||
struct _spi_async_dev {
|
||||
/** Pointer to the hardware base or private data for special device. */
|
||||
void *prvt;
|
||||
/** Data size, number of bytes for each character */
|
||||
uint8_t char_size;
|
||||
/** Dummy byte used in master mode when reading the slave */
|
||||
uint16_t dummy_byte;
|
||||
|
||||
/** \brief Pointer to callback functions, ignored for polling mode
|
||||
* Pointer to the callback functions so that initialize the driver to
|
||||
* handle interrupts.
|
||||
*/
|
||||
struct _spi_async_dev_callbacks callbacks;
|
||||
/** IRQ instance for SPI device. */
|
||||
struct _irq_descriptor irq;
|
||||
};
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Common SPI DMA related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_SPI_DMA_H_INCLUDED
|
||||
#define _HPL_SPI_DMA_H_INCLUDED
|
||||
|
||||
#include <hpl_irq.h>
|
||||
#include <hpl_dma.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** The callback types */
|
||||
enum _spi_dma_dev_cb_type {
|
||||
/** Callback type for DMA transmit. */
|
||||
SPI_DEV_CB_DMA_TX,
|
||||
/** Callback type for DMA receive. */
|
||||
SPI_DEV_CB_DMA_RX,
|
||||
/** Callback type for DMA error. */
|
||||
SPI_DEV_CB_DMA_ERROR,
|
||||
/** Number of callbacks. */
|
||||
SPI_DEV_CB_DMA_N,
|
||||
SPI_DEV_CB_DMA_SUSPEND
|
||||
};
|
||||
|
||||
struct _spi_dma_dev;
|
||||
|
||||
/**
|
||||
* \brief The prototype for callback on SPI DMA.
|
||||
*/
|
||||
typedef void (*_spi_dma_cb_t)(struct _dma_resource *resource);
|
||||
|
||||
/**
|
||||
* \brief The callbacks offered by SPI driver
|
||||
*/
|
||||
struct _spi_dma_dev_callbacks {
|
||||
_spi_dma_cb_t tx;
|
||||
_spi_dma_cb_t rx;
|
||||
_spi_dma_cb_t error;
|
||||
_spi_dma_cb_t suspend;
|
||||
};
|
||||
|
||||
/** SPI driver to support DMA HAL */
|
||||
struct _spi_dma_dev {
|
||||
/** Pointer to the hardware base or private data for special device. */
|
||||
void *prvt;
|
||||
/** Pointer to callback functions */
|
||||
struct _spi_dma_dev_callbacks callbacks;
|
||||
/** IRQ instance for SPI device. */
|
||||
struct _irq_descriptor irq;
|
||||
/** DMA resource */
|
||||
struct _dma_resource *resource;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _HPL_SPI_DMA_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SPI Slave Async related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED
|
||||
#define _HPL_SPI_M_ASYNC_H_INCLUDED
|
||||
|
||||
#include <hpl_spi.h>
|
||||
#include <hpl_spi_async.h>
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_spi HPL SPI
|
||||
*
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Uses common SPI async device driver. */
|
||||
#define _spi_m_async_dev _spi_async_dev
|
||||
|
||||
#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type
|
||||
|
||||
/** Uses common SPI async device driver complete callback type. */
|
||||
#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
|
||||
|
||||
/** Uses common SPI async device driver transfer callback type. */
|
||||
#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initialize SPI for access with interrupts
|
||||
* It will load default hardware configuration and software struct.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] hw Pointer to the hardware base.
|
||||
* \retval ERR_INVALID_ARG Input parameter problem.
|
||||
* \retval ERR_BUSY SPI hardware not ready (resetting).
|
||||
* \retval ERR_DENIED SPI has been enabled.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Initialize SPI for access with interrupts
|
||||
* Disable, reset the hardware and the software struct.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Enable SPI for access with interrupts
|
||||
* Enable the SPI and enable callback generation of receive and error
|
||||
* interrupts.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG Input parameter problem.
|
||||
* \retval ERR_BUSY SPI hardware not ready (resetting).
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Disable SPI for access without interrupts
|
||||
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Set SPI transfer mode
|
||||
* Set SPI transfer mode (\ref spi_transfer_mode),
|
||||
* which controls clock polarity and clock phase.
|
||||
* Mode 0: leading edge is rising edge, data sample on leading edge.
|
||||
* Mode 1: leading edge is rising edge, data sample on trailing edge.
|
||||
* Mode 2: leading edge is falling edge, data sample on leading edge.
|
||||
* Mode 3: leading edge is falling edge, data sample on trailing edge.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] mode The SPI transfer mode.
|
||||
* \return Operation status.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set SPI baudrate
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
|
||||
* how it's generated.
|
||||
* \return Operation status.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val);
|
||||
|
||||
/**
|
||||
* \brief Set SPI baudrate
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] char_size The character size, see \ref spi_char_size.
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG The character size is not supported.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size);
|
||||
|
||||
/**
|
||||
* \brief Set SPI data order
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] dord SPI data order (LSB/MSB first).
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG The character size is not supported.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord);
|
||||
|
||||
/**
|
||||
* \brief Enable interrupt on character output
|
||||
*
|
||||
* Enable interrupt when a new character can be written
|
||||
* to the SPI device.
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance
|
||||
* \param[in] state true = enable output interrupt
|
||||
* false = disable output interrupt
|
||||
*
|
||||
* \return Status code
|
||||
* \retval 0 Ok status
|
||||
*/
|
||||
int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state);
|
||||
|
||||
/**
|
||||
* \brief Enable interrupt on character input
|
||||
*
|
||||
* Enable interrupt when a new character is ready to be
|
||||
* read from the SPI device.
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance
|
||||
* \param[in] state true = enable input interrupts
|
||||
* false = disable input interrupt
|
||||
*
|
||||
* \return Status code
|
||||
* \retvat 0 OK Status
|
||||
*/
|
||||
int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state);
|
||||
|
||||
/**
|
||||
* \brief Enable interrupt on after data transmission complate
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance
|
||||
* \param[in] state true = enable input interrupts
|
||||
* false = disable input interrupt
|
||||
*
|
||||
* \return Status code
|
||||
* \retvat 0 OK Status
|
||||
*/
|
||||
int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state);
|
||||
|
||||
/**
|
||||
* \brief Read one character to SPI device instance
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
*
|
||||
* \return Character read from SPI module
|
||||
*/
|
||||
uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Write one character to assigned buffer
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] data
|
||||
*
|
||||
* \return Status code of write operation
|
||||
* \retval 0 Write operation OK
|
||||
*/
|
||||
int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data);
|
||||
|
||||
/**
|
||||
* \brief Register the SPI device callback
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] cb_type The callback type.
|
||||
* \param[in] func The callback function to register. NULL to disable callback.
|
||||
* \return Always 0.
|
||||
*/
|
||||
int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type,
|
||||
const FUNC_PTR func);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable SPI master interrupt
|
||||
*
|
||||
* param[in] device The pointer to SPI master device instance
|
||||
* param[in] type The type of interrupt to disable/enable if applicable
|
||||
* param[in] state Enable or disable
|
||||
*/
|
||||
void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type,
|
||||
const bool state);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,182 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SPI Master DMA related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_SPI_M_DMA_H_INCLUDED
|
||||
#define _HPL_SPI_M_DMA_H_INCLUDED
|
||||
|
||||
#include <hpl_spi.h>
|
||||
#include <hpl_spi_dma.h>
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_spi HPL SPI
|
||||
*
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Uses common SPI dma device driver. */
|
||||
#define _spi_m_dma_dev _spi_dma_dev
|
||||
|
||||
#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initialize SPI for access with interrupts
|
||||
* It will load default hardware configuration and software struct.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] hw Pointer to the hardware base.
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG Input parameter problem.
|
||||
* \retval ERR_BUSY SPI hardware not ready (resetting).
|
||||
* \retval ERR_DENIED SPI has been enabled.
|
||||
* \retval 0 ERR_NONE is operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Initialize SPI for access with interrupts
|
||||
* Disable, reset the hardware and the software struct.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval 0 ERR_NONE is operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Enable SPI for access with interrupts
|
||||
* Enable the SPI and enable callback generation of receive and error
|
||||
* interrupts.
|
||||
* \param[in] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG Input parameter problem.
|
||||
* \retval ERR_BUSY SPI hardware not ready (resetting).
|
||||
* \retval 0 ERR_NONE is operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Disable SPI for access without interrupts
|
||||
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
|
||||
* \param[in] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval 0 ERR_NONE is operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Set SPI transfer mode
|
||||
* Set SPI transfer mode (\ref spi_transfer_mode),
|
||||
* which controls clock polarity and clock phase.
|
||||
* Mode 0: leading edge is rising edge, data sample on leading edge.
|
||||
* Mode 1: leading edge is rising edge, data sample on trailing edge.
|
||||
* Mode 2: leading edge is falling edge, data sample on leading edge.
|
||||
* Mode 3: leading edge is falling edge, data sample on trailing edge.
|
||||
* \param[in] dev Pointer to the SPI device instance.
|
||||
* \param[in] mode The SPI transfer mode.
|
||||
* \return Operation status.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 ERR_NONE is operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set SPI baudrate
|
||||
* \param[in] dev Pointer to the SPI device instance.
|
||||
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
|
||||
* how it's generated.
|
||||
* \return Operation status.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val);
|
||||
|
||||
/**
|
||||
* \brief Set SPI baudrate
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] char_size The character size, see \ref spi_char_size.
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG The character size is not supported.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size);
|
||||
|
||||
/**
|
||||
* \brief Set SPI data order
|
||||
* \param[in] dev Pointer to the SPI device instance.
|
||||
* \param[in] dord SPI data order (LSB/MSB first).
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG The character size is not supported.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord);
|
||||
|
||||
/**
|
||||
* \brief Register the SPI device callback
|
||||
* \param[in] dev Pointer to the SPI device instance.
|
||||
* \param[in] cb_type The callback type.
|
||||
* \param[in] func The callback function to register. NULL to disable callback.
|
||||
* \return Always 0.
|
||||
*/
|
||||
void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func);
|
||||
|
||||
/** \brief Do SPI data transfer (TX & RX) with DMA
|
||||
* Log the TX & RX buffers and transfer them in background. It never blocks.
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance.
|
||||
* \param[in] txbuf Pointer to the transfer information (\ref spi_transfer).
|
||||
* \param[out] rxbuf Pointer to the receiver information (\ref spi_receive).
|
||||
* \param[in] length spi transfer data length.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy.
|
||||
*/
|
||||
int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf,
|
||||
const uint16_t length);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,166 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SPI related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_SPI_M_SYNC_H_INCLUDED
|
||||
#define _HPL_SPI_M_SYNC_H_INCLUDED
|
||||
|
||||
#include <hpl_spi.h>
|
||||
#include <hpl_spi_sync.h>
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_spi HPL SPI
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Uses common SPI sync device driver. */
|
||||
#define _spi_m_sync_dev _spi_sync_dev
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initialize SPI for access without interrupts
|
||||
* It will load default hardware configuration and software struct.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] hw Pointer to the hardware base.
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG Input parameter problem.
|
||||
* \retval ERR_BUSY SPI hardware not ready (resetting).
|
||||
* \retval ERR_DENIED SPI has been enabled.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize SPI
|
||||
* Disable, reset the hardware and the software struct.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Enable SPI for access without interrupts
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_BUSY SPI hardware not ready (resetting).
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Disable SPI for access without interrupts
|
||||
* Disable SPI. Deactivate all CS pins if works as master.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Set SPI transfer mode
|
||||
* Set SPI transfer mode (\ref spi_transfer_mode),
|
||||
* which controls clock polarity and clock phase.
|
||||
* Mode 0: leading edge is rising edge, data sample on leading edge.
|
||||
* Mode 1: leading edge is rising edge, data sample on trailing edge.
|
||||
* Mode 2: leading edge is falling edge, data sample on leading edge.
|
||||
* Mode 3: leading edge is falling edge, data sample on trailing edge.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] mode The SPI transfer mode.
|
||||
* \return Operation status.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set SPI baudrate
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
|
||||
* how it's generated.
|
||||
* \return Operation status.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val);
|
||||
|
||||
/**
|
||||
* \brief Set SPI char size
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] char_size The character size, see \ref spi_char_size.
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG The character size is not supported.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size);
|
||||
|
||||
/**
|
||||
* \brief Set SPI data order
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] dord SPI data order (LSB/MSB first).
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG The character size is not supported.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord);
|
||||
|
||||
/**
|
||||
* \brief Transfer the whole message without interrupt
|
||||
* Transfer the message, it will keep waiting until the message finish or
|
||||
* error.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] msg Pointer to the message instance to process.
|
||||
* \return Error or number of characters transferred.
|
||||
* \retval ERR_BUSY SPI hardware is not ready to start transfer (not
|
||||
* enabled, busy applying settings, ...).
|
||||
* \retval SPI_ERR_OVERFLOW Overflow error.
|
||||
* \retval >=0 Number of characters transferred.
|
||||
*/
|
||||
int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,232 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SPI Slave Async related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED
|
||||
#define _HPL_SPI_S_ASYNC_H_INCLUDED
|
||||
|
||||
#include <hpl_spi_async.h>
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_spi HPL SPI
|
||||
*
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Uses common SPI async device driver. */
|
||||
#define _spi_s_async_dev _spi_async_dev
|
||||
|
||||
#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type
|
||||
|
||||
/** Uses common SPI async device driver complete callback type. */
|
||||
#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
|
||||
|
||||
/** Uses common SPI async device driver transfer callback type. */
|
||||
#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initialize SPI for access with interrupts
|
||||
* It will load default hardware configuration and software struct.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] hw Pointer to the hardware base.
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG Input parameter problem.
|
||||
* \retval ERR_BUSY SPI hardware not ready (resetting).
|
||||
* \retval ERR_DENIED SPI has been enabled.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Initialize SPI for access with interrupts
|
||||
* Disable, reset the hardware and the software struct.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Enable SPI for access with interrupts
|
||||
* Enable the SPI and enable callback generation of receive and error
|
||||
* interrupts.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG Input parameter problem.
|
||||
* \retval ERR_BUSY SPI hardware not ready (resetting).
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Disable SPI for access without interrupts
|
||||
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Set SPI transfer mode
|
||||
* Set SPI transfer mode (\ref spi_transfer_mode),
|
||||
* which controls clock polarity and clock phase.
|
||||
* Mode 0: leading edge is rising edge, data sample on leading edge.
|
||||
* Mode 1: leading edge is rising edge, data sample on trailing edge.
|
||||
* Mode 2: leading edge is falling edge, data sample on leading edge.
|
||||
* Mode 3: leading edge is falling edge, data sample on trailing edge.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] mode The SPI transfer mode.
|
||||
* \return Operation status.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set SPI baudrate
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] char_size The character size, see \ref spi_char_size.
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG The character size is not supported.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size);
|
||||
|
||||
/**
|
||||
* \brief Set SPI data order
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] dord SPI data order (LSB/MSB first).
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG The character size is not supported.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord);
|
||||
|
||||
/**
|
||||
* \brief Enable interrupt on character output
|
||||
*
|
||||
* Enable interrupt when a new character can be written
|
||||
* to the SPI device.
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance
|
||||
* \param[in] state true = enable output interrupt
|
||||
* false = disable output interrupt
|
||||
*
|
||||
* \return Status code
|
||||
* \retval 0 Ok status
|
||||
*/
|
||||
int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state);
|
||||
|
||||
/**
|
||||
* \brief Enable interrupt on character input
|
||||
*
|
||||
* Enable interrupt when a new character is ready to be
|
||||
* read from the SPI device.
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance
|
||||
* \param[in] state true = enable input interrupts
|
||||
* false = disable input interrupt
|
||||
*
|
||||
* \return Status code
|
||||
* \retvat 0 OK Status
|
||||
*/
|
||||
int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state);
|
||||
|
||||
/**
|
||||
* \brief Enable interrupt on Slave Select (SS) rising
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance
|
||||
* \param[in] state true = enable input interrupts
|
||||
* false = disable input interrupt
|
||||
*
|
||||
* \return Status code
|
||||
* \retvat 0 OK Status
|
||||
*/
|
||||
int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state);
|
||||
|
||||
/**
|
||||
* \brief Read one character to SPI device instance
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
*
|
||||
* \return Character read from SPI module
|
||||
*/
|
||||
uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Write one character to assigned buffer
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] data
|
||||
*
|
||||
* \return Status code of write operation
|
||||
* \retval 0 Write operation OK
|
||||
*/
|
||||
int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data);
|
||||
|
||||
/**
|
||||
* \brief Register the SPI device callback
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] cb_type The callback type.
|
||||
* \param[in] func The callback function to register. NULL to disable callback.
|
||||
* \return Always 0.
|
||||
*/
|
||||
int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type,
|
||||
const FUNC_PTR func);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable SPI slave interrupt
|
||||
*
|
||||
* param[in] device The pointer to SPI slave device instance
|
||||
* param[in] type The type of interrupt to disable/enable if applicable
|
||||
* param[in] state Enable or disable
|
||||
*/
|
||||
void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type,
|
||||
const bool state);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,232 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SPI related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_SPI_S_SYNC_H_INCLUDED
|
||||
#define _HPL_SPI_S_SYNC_H_INCLUDED
|
||||
|
||||
#include <hpl_spi_sync.h>
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_spi HPL SPI
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Uses common SPI sync device driver. */
|
||||
#define _spi_s_sync_dev _spi_sync_dev
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initialize SPI for access without interrupts
|
||||
* It will load default hardware configuration and software struct.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] hw Pointer to the hardware base.
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG Input parameter problem.
|
||||
* \retval ERR_BUSY SPI hardware not ready (resetting).
|
||||
* \retval ERR_DENIED SPI has been enabled.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Initialize SPI for access with interrupts
|
||||
* Disable, reset the hardware and the software struct.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Enable SPI for access without interrupts
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_BUSY SPI hardware not ready (resetting).
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Disable SPI for access without interrupts
|
||||
* Disable SPI. Deactivate all CS pins if works as master.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Set SPI transfer mode
|
||||
* Set SPI transfer mode (\ref spi_transfer_mode),
|
||||
* which controls clock polarity and clock phase.
|
||||
* Mode 0: leading edge is rising edge, data sample on leading edge.
|
||||
* Mode 1: leading edge is rising edge, data sample on trailing edge.
|
||||
* Mode 2: leading edge is falling edge, data sample on leading edge.
|
||||
* Mode 3: leading edge is falling edge, data sample on trailing edge.
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] mode The SPI transfer mode.
|
||||
* \return Operation status.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set SPI baudrate
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] char_size The character size, see \ref spi_char_size.
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG The character size is not supported.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size);
|
||||
|
||||
/**
|
||||
* \brief Set SPI data order
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] dord SPI data order (LSB/MSB first).
|
||||
* \return Operation status.
|
||||
* \retval ERR_INVALID_ARG The character size is not supported.
|
||||
* \retval ERR_BUSY SPI is not ready to accept new setting.
|
||||
* \retval 0 Operation done successfully.
|
||||
*/
|
||||
int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord);
|
||||
|
||||
/**
|
||||
* \brief Enable interrupt on character output
|
||||
*
|
||||
* Enable interrupt when a new character can be written
|
||||
* to the SPI device.
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance
|
||||
* \param[in] state true = enable output interrupt
|
||||
* false = disable output interrupt
|
||||
*
|
||||
* \return Status code
|
||||
* \retval 0 Ok status
|
||||
*/
|
||||
int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state);
|
||||
|
||||
/**
|
||||
* \brief Enable interrupt on character input
|
||||
*
|
||||
* Enable interrupt when a new character is ready to be
|
||||
* read from the SPI device.
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance
|
||||
* \param[in] state true = enable input interrupts
|
||||
* false = disable input interrupt
|
||||
*
|
||||
* \return Status code
|
||||
* \retval 0 OK Status
|
||||
*/
|
||||
int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state);
|
||||
|
||||
/**
|
||||
* \brief Read one character to SPI device instance
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
*
|
||||
* \return Character read from SPI module
|
||||
*/
|
||||
uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Write one character to assigned buffer
|
||||
* \param[in, out] dev Pointer to the SPI device instance.
|
||||
* \param[in] data
|
||||
*
|
||||
* \return Status code of write operation
|
||||
* \retval 0 Write operation OK
|
||||
*/
|
||||
int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data);
|
||||
|
||||
/**
|
||||
* \brief Check if TX ready
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance
|
||||
*
|
||||
* \return TX ready state
|
||||
* \retval true TX ready
|
||||
* \retval false TX not ready
|
||||
*/
|
||||
bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Check if RX character ready
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance
|
||||
*
|
||||
* \return RX character ready state
|
||||
* \retval true RX character ready
|
||||
* \retval false RX character not ready
|
||||
*/
|
||||
bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Check if SS deactiviation detected
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance
|
||||
*
|
||||
* \return SS deactiviation state
|
||||
* \retval true SS deactiviation detected
|
||||
* \retval false SS deactiviation not detected
|
||||
*/
|
||||
bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Check if error is detected
|
||||
*
|
||||
* \param[in] dev Pointer to the SPI device instance
|
||||
*
|
||||
* \return Error detection state
|
||||
* \retval true Error detected
|
||||
* \retval false Error not detected
|
||||
*/
|
||||
bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Common SPI related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_SPI_SYNC_H_INCLUDED
|
||||
#define _HPL_SPI_SYNC_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
#include <utils.h>
|
||||
|
||||
#include <hpl_spi.h>
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_spi HPL SPI
|
||||
*
|
||||
* \section hpl_spi_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** SPI driver to support sync HAL */
|
||||
struct _spi_sync_dev {
|
||||
/** Pointer to the hardware base or private data for special device. */
|
||||
void *prvt;
|
||||
/** Data size, number of bytes for each character */
|
||||
uint8_t char_size;
|
||||
/** Dummy byte used in master mode when reading the slave */
|
||||
uint16_t dummy_byte;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief USART related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_USART_H_INCLUDED
|
||||
#define _HPL_USART_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL USART SYNC
|
||||
*
|
||||
* \section hpl_usart_sync_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief USART flow control state
|
||||
*/
|
||||
union usart_flow_control_state {
|
||||
struct {
|
||||
uint8_t cts : 1;
|
||||
uint8_t rts : 1;
|
||||
uint8_t unavailable : 1;
|
||||
uint8_t reserved : 5;
|
||||
} bit;
|
||||
uint8_t value;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief USART baud rate mode
|
||||
*/
|
||||
enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH };
|
||||
|
||||
/**
|
||||
* \brief USART data order
|
||||
*/
|
||||
enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 };
|
||||
|
||||
/**
|
||||
* \brief USART mode
|
||||
*/
|
||||
enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 };
|
||||
|
||||
/**
|
||||
* \brief USART parity
|
||||
*/
|
||||
enum usart_parity {
|
||||
USART_PARITY_EVEN = 0,
|
||||
USART_PARITY_ODD = 1,
|
||||
USART_PARITY_NONE = 2,
|
||||
USART_PARITY_SPACE = 3,
|
||||
USART_PARITY_MARK = 4
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief USART stop bits mode
|
||||
*/
|
||||
enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 };
|
||||
|
||||
/**
|
||||
* \brief USART character size
|
||||
*/
|
||||
enum usart_character_size {
|
||||
USART_CHARACTER_SIZE_8BITS = 0,
|
||||
USART_CHARACTER_SIZE_9BITS = 1,
|
||||
USART_CHARACTER_SIZE_5BITS = 5,
|
||||
USART_CHARACTER_SIZE_6BITS = 6,
|
||||
USART_CHARACTER_SIZE_7BITS = 7
|
||||
};
|
||||
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_USART_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief USART related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_USART_ASYNC_H_INCLUDED
|
||||
#define _HPL_USART_ASYNC_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL USART
|
||||
*
|
||||
* \section hpl_usart_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include "hpl_usart.h"
|
||||
#include "hpl_irq.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief USART callback types
|
||||
*/
|
||||
enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR };
|
||||
|
||||
/**
|
||||
* \brief USART device structure
|
||||
*
|
||||
* The USART device structure forward declaration.
|
||||
*/
|
||||
struct _usart_async_device;
|
||||
|
||||
/**
|
||||
* \brief USART interrupt callbacks
|
||||
*/
|
||||
struct _usart_async_callbacks {
|
||||
void (*tx_byte_sent)(struct _usart_async_device *device);
|
||||
void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data);
|
||||
void (*tx_done_cb)(struct _usart_async_device *device);
|
||||
void (*error_cb)(struct _usart_async_device *device);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief USART descriptor device structure
|
||||
*/
|
||||
struct _usart_async_device {
|
||||
struct _usart_async_callbacks usart_cb;
|
||||
struct _irq_descriptor irq;
|
||||
void * hw;
|
||||
};
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initialize asynchronous USART
|
||||
*
|
||||
* This function does low level USART configuration.
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Initialization status
|
||||
*/
|
||||
int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize USART
|
||||
*
|
||||
* This function closes the given USART by disabling its clock.
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*/
|
||||
void _usart_async_deinit(struct _usart_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable usart module
|
||||
*
|
||||
* This function will enable the usart module
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*/
|
||||
void _usart_async_enable(struct _usart_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Disable usart module
|
||||
*
|
||||
* This function will disable the usart module
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*/
|
||||
void _usart_async_disable(struct _usart_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Calculate baud rate register value
|
||||
*
|
||||
* \param[in] baud Required baud rate
|
||||
* \param[in] clock_rate clock frequency
|
||||
* \param[in] samples The number of samples
|
||||
* \param[in] mode USART mode
|
||||
* \param[in] fraction A fraction value
|
||||
*
|
||||
* \return Calculated baud rate register value
|
||||
*/
|
||||
uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
|
||||
const enum usart_baud_rate_mode mode, const uint8_t fraction);
|
||||
|
||||
/**
|
||||
* \brief Set baud rate
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] baud_rate A baud rate to set
|
||||
*/
|
||||
void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate);
|
||||
|
||||
/**
|
||||
* \brief Set data order
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] order A data order to set
|
||||
*/
|
||||
void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order);
|
||||
|
||||
/**
|
||||
* \brief Set mode
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] mode A mode to set
|
||||
*/
|
||||
void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set parity
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] parity A parity to set
|
||||
*/
|
||||
void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity);
|
||||
|
||||
/**
|
||||
* \brief Set stop bits mode
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] stop_bits A stop bits mode to set
|
||||
*/
|
||||
void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits);
|
||||
|
||||
/**
|
||||
* \brief Set character size
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] size A character size to set
|
||||
*/
|
||||
void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size);
|
||||
|
||||
/**
|
||||
* \brief Retrieve usart status
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*/
|
||||
uint32_t _usart_async_get_status(const struct _usart_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Write a byte to the given USART instance
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] data Data to write
|
||||
*/
|
||||
void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data);
|
||||
|
||||
/**
|
||||
* \brief Check if USART is ready to send next byte
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*
|
||||
* \return Status of the ready check.
|
||||
* \retval true if the USART is ready to send next byte
|
||||
* \retval false if the USART is not ready to send next byte
|
||||
*/
|
||||
bool _usart_async_is_byte_sent(const struct _usart_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set the state of flow control pins
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] state - A state of flow control pins to set
|
||||
*/
|
||||
void _usart_async_set_flow_control_state(struct _usart_async_device *const device,
|
||||
const union usart_flow_control_state state);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the state of flow control pins
|
||||
*
|
||||
* This function retrieves the of flow control pins.
|
||||
*
|
||||
* \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
|
||||
*/
|
||||
union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable data register empty interrupt
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*/
|
||||
void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable transmission complete interrupt
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*/
|
||||
void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Retrieve ordinal number of the given USART hardware instance
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*
|
||||
* \return The ordinal number of the given USART hardware instance
|
||||
*/
|
||||
uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable USART interrupt
|
||||
*
|
||||
* param[in] device The pointer to USART device instance
|
||||
* param[in] type The type of interrupt to disable/enable if applicable
|
||||
* param[in] state Enable or disable
|
||||
*/
|
||||
void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type,
|
||||
const bool state);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_USART_ASYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief USART related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_SYNC_USART_H_INCLUDED
|
||||
#define _HPL_SYNC_USART_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL USART SYNC
|
||||
*
|
||||
* \section hpl_usart_sync_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <hpl_usart.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief USART descriptor device structure
|
||||
*/
|
||||
struct _usart_sync_device {
|
||||
void *hw;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initialize synchronous USART
|
||||
*
|
||||
* This function does low level USART configuration.
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Initialization status
|
||||
*/
|
||||
int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize USART
|
||||
*
|
||||
* This function closes the given USART by disabling its clock.
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*/
|
||||
void _usart_sync_deinit(struct _usart_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable usart module
|
||||
*
|
||||
* This function will enable the usart module
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*/
|
||||
void _usart_sync_enable(struct _usart_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Disable usart module
|
||||
*
|
||||
* This function will disable the usart module
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*/
|
||||
void _usart_sync_disable(struct _usart_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Calculate baud rate register value
|
||||
*
|
||||
* \param[in] baud Required baud rate
|
||||
* \param[in] clock_rate clock frequency
|
||||
* \param[in] samples The number of samples
|
||||
* \param[in] mode USART mode
|
||||
* \param[in] fraction A fraction value
|
||||
*
|
||||
* \return Calculated baud rate register value
|
||||
*/
|
||||
uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
|
||||
const enum usart_baud_rate_mode mode, const uint8_t fraction);
|
||||
|
||||
/**
|
||||
* \brief Set baud rate
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] baud_rate A baud rate to set
|
||||
*/
|
||||
void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate);
|
||||
|
||||
/**
|
||||
* \brief Set data order
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] order A data order to set
|
||||
*/
|
||||
void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order);
|
||||
|
||||
/**
|
||||
* \brief Set mode
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] mode A mode to set
|
||||
*/
|
||||
void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set parity
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] parity A parity to set
|
||||
*/
|
||||
void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity);
|
||||
|
||||
/**
|
||||
* \brief Set stop bits mode
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] stop_bits A stop bits mode to set
|
||||
*/
|
||||
void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits);
|
||||
|
||||
/**
|
||||
* \brief Set character size
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] size A character size to set
|
||||
*/
|
||||
void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size);
|
||||
|
||||
/**
|
||||
* \brief Retrieve usart status
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*/
|
||||
uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Write a byte to the given USART instance
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] data Data to write
|
||||
*/
|
||||
void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data);
|
||||
|
||||
/**
|
||||
* \brief Read a byte from the given USART instance
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] data Data to write
|
||||
*
|
||||
* \return Data received via USART interface.
|
||||
*/
|
||||
uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if USART is ready to send next byte
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*
|
||||
* \return Status of the ready check.
|
||||
* \retval true if the USART is ready to send next byte
|
||||
* \retval false if the USART is not ready to send next byte
|
||||
*/
|
||||
bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if USART transmitter has sent the byte
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*
|
||||
* \return Status of the ready check.
|
||||
* \retval true if the USART transmitter has sent the byte
|
||||
* \retval false if the USART transmitter has not send the byte
|
||||
*/
|
||||
bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if there is data received by USART
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*
|
||||
* \return Status of the data received check.
|
||||
* \retval true if the USART has received a byte
|
||||
* \retval false if the USART has not received a byte
|
||||
*/
|
||||
bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set the state of flow control pins
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
* \param[in] state - A state of flow control pins to set
|
||||
*/
|
||||
void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device,
|
||||
const union usart_flow_control_state state);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the state of flow control pins
|
||||
*
|
||||
* This function retrieves the of flow control pins.
|
||||
*
|
||||
* \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
|
||||
*/
|
||||
union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Retrieve ordinal number of the given USART hardware instance
|
||||
*
|
||||
* \param[in] device The pointer to USART device instance
|
||||
*
|
||||
* \return The ordinal number of the given USART hardware instance
|
||||
*/
|
||||
uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_SYNC_USART_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Critical sections related functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hal_atomic.h"
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define DRIVER_VERSION 0x00000001u
|
||||
|
||||
/**
|
||||
* \brief Disable interrupts, enter critical section
|
||||
*/
|
||||
void atomic_enter_critical(hal_atomic_t volatile *atomic)
|
||||
{
|
||||
*atomic = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
__DMB();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Exit atomic section
|
||||
*/
|
||||
void atomic_leave_critical(hal_atomic_t volatile *atomic)
|
||||
{
|
||||
__DMB();
|
||||
__set_PRIMASK(*atomic);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*/
|
||||
uint32_t atomic_get_version(void)
|
||||
{
|
||||
return DRIVER_VERSION;
|
||||
}
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL cache functionality implementation.
|
||||
*
|
||||
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include <hpl_cmcc.h>
|
||||
|
||||
/**
|
||||
* \brief Initialize cache module
|
||||
*/
|
||||
int32_t cache_init(void)
|
||||
{
|
||||
return _cmcc_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable cache module
|
||||
*/
|
||||
int32_t cache_enable(const void *hw)
|
||||
{
|
||||
return _cmcc_enable(hw);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable cache module
|
||||
*/
|
||||
int32_t cache_disable(const void *hw)
|
||||
{
|
||||
return _cmcc_disable(hw);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Configure cache module
|
||||
*/
|
||||
int32_t cache_configure(const void *hw, struct _cache_cfg *cache)
|
||||
{
|
||||
return _cmcc_configure(hw, cache);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Invalidate entire cache entries
|
||||
*/
|
||||
int32_t cache_invalidate_all(const void *hw)
|
||||
{
|
||||
return _cmcc_invalidate_all(hw);
|
||||
}
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL delay related functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include <hpl_irq.h>
|
||||
#include <hpl_reset.h>
|
||||
#include <hpl_sleep.h>
|
||||
#include "hal_delay.h"
|
||||
#include <hpl_delay.h>
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define DRIVER_VERSION 0x00000001u
|
||||
|
||||
/**
|
||||
* \brief The pointer to a hardware instance used by the driver.
|
||||
*/
|
||||
static void *hardware;
|
||||
|
||||
/**
|
||||
* \brief Initialize Delay driver
|
||||
*/
|
||||
void delay_init(void *const hw)
|
||||
{
|
||||
_delay_init(hardware = hw);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Perform delay in us
|
||||
*/
|
||||
void delay_us(const uint16_t us)
|
||||
{
|
||||
_delay_cycles(hardware, _get_cycles_for_us(us));
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Perform delay in ms
|
||||
*/
|
||||
void delay_ms(const uint16_t ms)
|
||||
{
|
||||
_delay_cycles(hardware, _get_cycles_for_ms(ms));
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*/
|
||||
uint32_t delay_get_version(void)
|
||||
{
|
||||
return DRIVER_VERSION;
|
||||
}
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL event system related functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hal_evsys.h"
|
||||
#include <hpl_evsys.h>
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define DRIVER_VERSION 0x00000001u
|
||||
|
||||
/**
|
||||
* \brief Initialize event system.
|
||||
*/
|
||||
int32_t event_system_init(void)
|
||||
{
|
||||
return _event_system_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Deinitialize event system.
|
||||
*/
|
||||
int32_t event_system_deinit(void)
|
||||
{
|
||||
return _event_system_deinit();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable event reception by the given user from the given channel
|
||||
*/
|
||||
int32_t event_system_enable_user(const uint16_t user, const uint16_t channel)
|
||||
{
|
||||
return _event_system_enable_user(user, channel, true);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable event reception by the given user from the given channel
|
||||
*/
|
||||
int32_t event_system_disable_user(const uint16_t user, const uint16_t channel)
|
||||
{
|
||||
return _event_system_enable_user(user, channel, false);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable event generation by the given generator for the given channel
|
||||
*/
|
||||
int32_t event_system_enable_generator(const uint16_t generator, const uint16_t channel)
|
||||
{
|
||||
return _event_system_enable_generator(generator, channel, true);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable event generation by the given generator for the given channel
|
||||
*/
|
||||
int32_t event_system_disable_generator(const uint16_t generator, const uint16_t channel)
|
||||
{
|
||||
return _event_system_enable_generator(generator, channel, false);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version
|
||||
*/
|
||||
uint32_t event_system_get_version(void)
|
||||
{
|
||||
return DRIVER_VERSION;
|
||||
}
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Port
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hal_gpio.h"
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define DRIVER_VERSION 0x00000001u
|
||||
|
||||
uint32_t gpio_get_version(void)
|
||||
{
|
||||
return DRIVER_VERSION;
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL initialization related functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hal_init.h"
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define HAL_INIT_VERSION 0x00000001u
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*/
|
||||
uint32_t init_get_version(void)
|
||||
{
|
||||
return HAL_INIT_VERSION;
|
||||
}
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I/O functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include <hal_io.h>
|
||||
#include <utils_assert.h>
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define DRIVER_VERSION 0x00000001u
|
||||
|
||||
uint32_t io_get_version(void)
|
||||
{
|
||||
return DRIVER_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief I/O write interface
|
||||
*/
|
||||
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
|
||||
{
|
||||
ASSERT(io_descr && buf);
|
||||
return io_descr->write(io_descr, buf, length);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief I/O read interface
|
||||
*/
|
||||
int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
|
||||
{
|
||||
ASSERT(io_descr && buf);
|
||||
return io_descr->read(io_descr, buf, length);
|
||||
}
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Sleep related functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hal_sleep.h"
|
||||
#include <hpl_sleep.h>
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define DRIVER_VERSION 0x00000001u
|
||||
|
||||
/**
|
||||
* \brief Set the sleep mode of the device and put the MCU to sleep
|
||||
*
|
||||
* For an overview of which systems are disabled in sleep for the different
|
||||
* sleep modes, see the data sheet.
|
||||
*
|
||||
* \param[in] mode Sleep mode to use
|
||||
*
|
||||
* \return The status of a sleep request
|
||||
* \retval -1 The requested sleep mode was invalid or not available
|
||||
* \retval 0 The operation completed successfully, returned after leaving the
|
||||
* sleep
|
||||
*/
|
||||
int sleep(const uint8_t mode)
|
||||
{
|
||||
if (ERR_NONE != _set_sleep_mode(mode))
|
||||
return ERR_INVALID_ARG;
|
||||
|
||||
_go_to_sleep();
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version
|
||||
*/
|
||||
uint32_t sleep_get_version(void)
|
||||
{
|
||||
return DRIVER_VERSION;
|
||||
}
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I/O SPI DMA related functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hal_atomic.h"
|
||||
#include "hal_spi_m_dma.h"
|
||||
#include <utils_assert.h>
|
||||
#include <utils.h>
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define SPI_DRIVER_VERSION 0x00000001u
|
||||
|
||||
static int32_t _spi_m_dma_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length);
|
||||
static int32_t _spi_m_dma_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief Initialize the SPI HAL instance function pointer for HPL APIs.
|
||||
*/
|
||||
void spi_m_dma_set_func_ptr(struct spi_m_dma_descriptor *spi, void *const func)
|
||||
{
|
||||
ASSERT(spi);
|
||||
spi->func = (struct _spi_m_dma_hpl_interface *)func;
|
||||
}
|
||||
|
||||
int32_t spi_m_dma_init(struct spi_m_dma_descriptor *spi, void *const hw)
|
||||
{
|
||||
int32_t rc = 0;
|
||||
ASSERT(spi && hw);
|
||||
spi->dev.prvt = (void *)hw;
|
||||
rc = _spi_m_dma_init(&spi->dev, hw);
|
||||
|
||||
if (rc) {
|
||||
return rc;
|
||||
}
|
||||
|
||||
spi->io.read = _spi_m_dma_io_read;
|
||||
spi->io.write = _spi_m_dma_io_write;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
void spi_m_dma_deinit(struct spi_m_dma_descriptor *spi)
|
||||
{
|
||||
ASSERT(spi);
|
||||
_spi_m_dma_deinit(&spi->dev);
|
||||
}
|
||||
|
||||
void spi_m_dma_enable(struct spi_m_dma_descriptor *spi)
|
||||
{
|
||||
ASSERT(spi);
|
||||
_spi_m_dma_enable(&spi->dev);
|
||||
}
|
||||
|
||||
void spi_m_dma_disable(struct spi_m_dma_descriptor *spi)
|
||||
{
|
||||
ASSERT(spi);
|
||||
_spi_m_dma_disable(&spi->dev);
|
||||
}
|
||||
|
||||
int32_t spi_m_dma_set_baudrate(struct spi_m_dma_descriptor *spi, const uint32_t baud_val)
|
||||
{
|
||||
ASSERT(spi);
|
||||
return _spi_m_dma_set_baudrate(&spi->dev, baud_val);
|
||||
}
|
||||
|
||||
int32_t spi_m_dma_set_mode(struct spi_m_dma_descriptor *spi, const enum spi_transfer_mode mode)
|
||||
{
|
||||
ASSERT(spi);
|
||||
return _spi_m_dma_set_mode(&spi->dev, mode);
|
||||
}
|
||||
|
||||
int32_t spi_m_dma_set_char_size(struct spi_m_dma_descriptor *spi, const enum spi_char_size char_size)
|
||||
{
|
||||
ASSERT(spi);
|
||||
return _spi_m_dma_set_char_size(&spi->dev, char_size);
|
||||
}
|
||||
|
||||
int32_t spi_m_dma_set_data_order(struct spi_m_dma_descriptor *spi, const enum spi_data_order dord)
|
||||
{
|
||||
ASSERT(spi);
|
||||
return _spi_m_dma_set_data_order(&spi->dev, dord);
|
||||
}
|
||||
|
||||
/** \brief Do SPI read in background
|
||||
*
|
||||
* It never blocks and return quickly, user check status or set callback to
|
||||
* know when data is ready to process.
|
||||
*
|
||||
* \param[in, out] spi Pointer to the HAL SPI instance.
|
||||
* \param[out] p_buf Pointer to the buffer to store read data.
|
||||
* \param[in] size Size of the data in number of characters.
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
* \retval ERR_NONE Success, transfer started.
|
||||
* \retval ERR_BUSY Busy.
|
||||
*/
|
||||
static int32_t _spi_m_dma_io_read(struct io_descriptor *io, uint8_t *const buf, const uint16_t length)
|
||||
{
|
||||
ASSERT(io);
|
||||
|
||||
struct spi_m_dma_descriptor *spi = CONTAINER_OF(io, struct spi_m_dma_descriptor, io);
|
||||
return _spi_m_dma_transfer(&spi->dev, NULL, buf, length);
|
||||
}
|
||||
|
||||
/** \brief Do SPI data write in background
|
||||
*
|
||||
* The data read back is discarded.
|
||||
*
|
||||
* It never blocks and return quickly, user check status or set callback to
|
||||
* know when data is sent.
|
||||
*
|
||||
* \param[in, out] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] p_buf Pointer to the buffer to store data to write.
|
||||
* \param[in] size Size of the data in number of characters.
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
* \retval ERR_NONE Success, transfer started.
|
||||
* \retval ERR_BUSY Busy.
|
||||
*/
|
||||
static int32_t _spi_m_dma_io_write(struct io_descriptor *io, const uint8_t *const buf, const uint16_t length)
|
||||
{
|
||||
ASSERT(io);
|
||||
|
||||
struct spi_m_dma_descriptor *spi = CONTAINER_OF(io, struct spi_m_dma_descriptor, io);
|
||||
return _spi_m_dma_transfer(&spi->dev, buf, NULL, length);
|
||||
}
|
||||
|
||||
int32_t spi_m_dma_transfer(struct spi_m_dma_descriptor *spi, uint8_t const *txbuf, uint8_t *const rxbuf,
|
||||
const uint16_t length)
|
||||
{
|
||||
ASSERT(spi);
|
||||
return _spi_m_dma_transfer(&spi->dev, txbuf, rxbuf, length);
|
||||
}
|
||||
|
||||
void spi_m_dma_register_callback(struct spi_m_dma_descriptor *spi, const enum spi_m_dma_cb_type type,
|
||||
spi_m_dma_cb_t func)
|
||||
{
|
||||
ASSERT(spi);
|
||||
_spi_m_dma_register_callback(&spi->dev, (enum _spi_dma_dev_cb_type)type, func);
|
||||
}
|
||||
|
||||
int32_t spi_m_dma_get_io_descriptor(struct spi_m_dma_descriptor *const spi, struct io_descriptor **io)
|
||||
{
|
||||
ASSERT(spi && io);
|
||||
*io = &spi->io;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t spi_m_dma_get_version(void)
|
||||
{
|
||||
return SPI_DRIVER_VERSION;
|
||||
}
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Header
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* compiler.h
|
||||
*
|
||||
* Created: 05.05.2014
|
||||
* Author: N. Fomin
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _COMPILER_H
|
||||
#define _COMPILER_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifndef _UNIT_TEST_
|
||||
#include "parts.h"
|
||||
#endif
|
||||
#include "err_codes.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _COMPILER_H */
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Error code definitions.
|
||||
*
|
||||
* This file defines various status codes returned by functions,
|
||||
* indicating success or failure as well as what kind of failure.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef ERROR_CODES_H_INCLUDED
|
||||
#define ERROR_CODES_H_INCLUDED
|
||||
|
||||
#define ERR_NONE 0
|
||||
#define ERR_INVALID_DATA -1
|
||||
#define ERR_NO_CHANGE -2
|
||||
#define ERR_ABORTED -3
|
||||
#define ERR_BUSY -4
|
||||
#define ERR_SUSPEND -5
|
||||
#define ERR_IO -6
|
||||
#define ERR_REQ_FLUSHED -7
|
||||
#define ERR_TIMEOUT -8
|
||||
#define ERR_BAD_DATA -9
|
||||
#define ERR_NOT_FOUND -10
|
||||
#define ERR_UNSUPPORTED_DEV -11
|
||||
#define ERR_NO_MEMORY -12
|
||||
#define ERR_INVALID_ARG -13
|
||||
#define ERR_BAD_ADDRESS -14
|
||||
#define ERR_BAD_FORMAT -15
|
||||
#define ERR_BAD_FRQ -16
|
||||
#define ERR_DENIED -17
|
||||
#define ERR_ALREADY_INITIALIZED -18
|
||||
#define ERR_OVERFLOW -19
|
||||
#define ERR_NOT_INITIALIZED -20
|
||||
#define ERR_SAMPLERATE_UNAVAILABLE -21
|
||||
#define ERR_RESOLUTION_UNAVAILABLE -22
|
||||
#define ERR_BAUDRATE_UNAVAILABLE -23
|
||||
#define ERR_PACKET_COLLISION -24
|
||||
#define ERR_PROTOCOL -25
|
||||
#define ERR_PIN_MUX_INVALID -26
|
||||
#define ERR_UNSUPPORTED_OP -27
|
||||
#define ERR_NO_RESOURCE -28
|
||||
#define ERR_NOT_READY -29
|
||||
#define ERR_FAILURE -30
|
||||
#define ERR_WRONG_LENGTH -31
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Events declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _EVENTS_H_INCLUDED
|
||||
#define _EVENTS_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
/**
|
||||
* \brief List of events. Must start with 0, be unique and follow numerical order.
|
||||
*/
|
||||
#define EVENT_IS_READY_TO_SLEEP_ID 0
|
||||
#define EVENT_PREPARE_TO_SLEEP_ID 1
|
||||
#define EVENT_WOKEN_UP_ID 2
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _EVENTS_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Atmel part identification macros
|
||||
*
|
||||
* Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef ATMEL_PARTS_H
|
||||
#define ATMEL_PARTS_H
|
||||
|
||||
#include "same54.h"
|
||||
|
||||
#include "hri_e54.h"
|
||||
|
||||
#endif /* ATMEL_PARTS_H */
|
||||
|
|
@ -0,0 +1,368 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Different macros.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef UTILS_H_INCLUDED
|
||||
#define UTILS_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_utils_macro
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Retrieve pointer to parent structure
|
||||
*/
|
||||
#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name)))
|
||||
|
||||
/**
|
||||
* \brief Retrieve array size
|
||||
*/
|
||||
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
|
||||
|
||||
/**
|
||||
* \brief Emit the compiler pragma \a arg.
|
||||
*
|
||||
* \param[in] arg The pragma directive as it would appear after \e \#pragma
|
||||
* (i.e. not stringified).
|
||||
*/
|
||||
#define COMPILER_PRAGMA(arg) _Pragma(#arg)
|
||||
|
||||
/**
|
||||
* \def COMPILER_PACK_SET(alignment)
|
||||
* \brief Set maximum alignment for subsequent struct and union definitions to \a alignment.
|
||||
*/
|
||||
#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
|
||||
|
||||
/**
|
||||
* \def COMPILER_PACK_RESET()
|
||||
* \brief Set default alignment for subsequent struct and union definitions.
|
||||
*/
|
||||
#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
|
||||
|
||||
/**
|
||||
* \brief Set aligned boundary.
|
||||
*/
|
||||
#if defined __GNUC__
|
||||
#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
|
||||
#elif defined __ICCARM__
|
||||
#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)
|
||||
#elif defined __CC_ARM
|
||||
#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Flash located data macros
|
||||
*/
|
||||
#if defined __GNUC__
|
||||
#define PROGMEM_DECLARE(type, name) const type name
|
||||
#define PROGMEM_T const
|
||||
#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x))
|
||||
#define PROGMEM_PTR_T const *
|
||||
#define PROGMEM_STRING_T const uint8_t *
|
||||
#elif defined __ICCARM__
|
||||
#define PROGMEM_DECLARE(type, name) const type name
|
||||
#define PROGMEM_T const
|
||||
#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x))
|
||||
#define PROGMEM_PTR_T const *
|
||||
#define PROGMEM_STRING_T const uint8_t *
|
||||
#elif defined __CC_ARM
|
||||
#define PROGMEM_DECLARE(type, name) const type name
|
||||
#define PROGMEM_T const
|
||||
#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x))
|
||||
#define PROGMEM_PTR_T const *
|
||||
#define PROGMEM_STRING_T const uint8_t *
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Optimization
|
||||
*/
|
||||
#if defined __GNUC__
|
||||
#define OPTIMIZE_HIGH __attribute__((optimize(s)))
|
||||
#elif defined __CC_ARM
|
||||
#define OPTIMIZE_HIGH _Pragma("O3")
|
||||
#elif defined __ICCARM__
|
||||
#define OPTIMIZE_HIGH _Pragma("optimize=high")
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief RAM located function attribute
|
||||
*/
|
||||
#if defined(__CC_ARM) /* Keil ?Vision 4 */
|
||||
#define RAMFUNC __attribute__((section(".ramfunc")))
|
||||
#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */
|
||||
#define RAMFUNC __ramfunc
|
||||
#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */
|
||||
#define RAMFUNC __attribute__((section(".ramfunc")))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief No-init section.
|
||||
* Place a data object or a function in a no-init section.
|
||||
*/
|
||||
#if defined(__CC_ARM)
|
||||
#define NO_INIT(a) __attribute__((zero_init))
|
||||
#elif defined(__ICCARM__)
|
||||
#define NO_INIT(a) __no_init
|
||||
#elif defined(__GNUC__)
|
||||
#define NO_INIT(a) __attribute__((section(".no_init")))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Set user-defined section.
|
||||
* Place a data object or a function in a user-defined section.
|
||||
*/
|
||||
#if defined(__CC_ARM)
|
||||
#define COMPILER_SECTION(a) __attribute__((__section__(a)))
|
||||
#elif defined(__ICCARM__)
|
||||
#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a)
|
||||
#elif defined(__GNUC__)
|
||||
#define COMPILER_SECTION(a) __attribute__((__section__(a)))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Define WEAK attribute.
|
||||
*/
|
||||
#if defined(__CC_ARM) /* Keil ?Vision 4 */
|
||||
#define WEAK __attribute__((weak))
|
||||
#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */
|
||||
#define WEAK __weak
|
||||
#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */
|
||||
#define WEAK __attribute__((weak))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Pointer to function
|
||||
*/
|
||||
typedef void (*FUNC_PTR)(void);
|
||||
|
||||
#define LE_BYTE0(a) ((uint8_t)(a))
|
||||
#define LE_BYTE1(a) ((uint8_t)((a) >> 8))
|
||||
#define LE_BYTE2(a) ((uint8_t)((a) >> 16))
|
||||
#define LE_BYTE3(a) ((uint8_t)((a) >> 24))
|
||||
|
||||
#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8))
|
||||
#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24))
|
||||
|
||||
/** \name Zero-Bit Counting
|
||||
*
|
||||
* Under GCC, __builtin_clz and __builtin_ctz behave like macros when
|
||||
* applied to constant expressions (values known at compile time), so they are
|
||||
* more optimized than the use of the corresponding assembly instructions and
|
||||
* they can be used as constant expressions e.g. to initialize objects having
|
||||
* static storage duration, and like the corresponding assembly instructions
|
||||
* when applied to non-constant expressions (values unknown at compile time), so
|
||||
* they are more optimized than an assembly periphrasis. Hence, clz and ctz
|
||||
* ensure a possible and optimized behavior for both constant and non-constant
|
||||
* expressions.
|
||||
*
|
||||
* @{ */
|
||||
|
||||
/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
|
||||
*
|
||||
* \param[in] u Value of which to count the leading zero bits.
|
||||
*
|
||||
* \return The count of leading zero bits in \a u.
|
||||
*/
|
||||
#if (defined __GNUC__) || (defined __CC_ARM)
|
||||
#define clz(u) __builtin_clz(u)
|
||||
#else
|
||||
#define clz(u) \
|
||||
( \
|
||||
((u) == 0) \
|
||||
? 32 \
|
||||
: ((u) & (1ul << 31)) \
|
||||
? 0 \
|
||||
: ((u) & (1ul << 30)) \
|
||||
? 1 \
|
||||
: ((u) & (1ul << 29)) \
|
||||
? 2 \
|
||||
: ((u) & (1ul << 28)) \
|
||||
? 3 \
|
||||
: ((u) & (1ul << 27)) \
|
||||
? 4 \
|
||||
: ((u) & (1ul << 26)) \
|
||||
? 5 \
|
||||
: ((u) & (1ul << 25)) \
|
||||
? 6 \
|
||||
: ((u) & (1ul << 24)) \
|
||||
? 7 \
|
||||
: ((u) & (1ul << 23)) \
|
||||
? 8 \
|
||||
: ((u) & (1ul << 22)) \
|
||||
? 9 \
|
||||
: ((u) & (1ul << 21)) \
|
||||
? 10 \
|
||||
: ((u) & (1ul << 20)) \
|
||||
? 11 \
|
||||
: ((u) & (1ul << 19)) \
|
||||
? 12 \
|
||||
: ((u) & (1ul << 18)) \
|
||||
? 13 \
|
||||
: ((u) & (1ul << 17)) ? 14 \
|
||||
: ((u) & (1ul << 16)) ? 15 \
|
||||
: ((u) & (1ul << 15)) ? 16 \
|
||||
: ((u) & (1ul << 14)) ? 17 \
|
||||
: ((u) & (1ul << 13)) ? 18 \
|
||||
: ((u) & (1ul << 12)) ? 19 \
|
||||
: ((u) \
|
||||
& (1ul \
|
||||
<< 11)) \
|
||||
? 20 \
|
||||
: ((u) \
|
||||
& (1ul \
|
||||
<< 10)) \
|
||||
? 21 \
|
||||
: ((u) \
|
||||
& (1ul \
|
||||
<< 9)) \
|
||||
? 22 \
|
||||
: ((u) \
|
||||
& (1ul \
|
||||
<< 8)) \
|
||||
? 23 \
|
||||
: ((u) & (1ul << 7)) ? 24 \
|
||||
: ((u) & (1ul << 6)) ? 25 \
|
||||
: ((u) \
|
||||
& (1ul \
|
||||
<< 5)) \
|
||||
? 26 \
|
||||
: ((u) & (1ul << 4)) ? 27 \
|
||||
: ((u) & (1ul << 3)) ? 28 \
|
||||
: ((u) & (1ul << 2)) ? 29 \
|
||||
: ( \
|
||||
(u) & (1ul << 1)) \
|
||||
? 30 \
|
||||
: 31)
|
||||
#endif
|
||||
|
||||
/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
|
||||
*
|
||||
* \param[in] u Value of which to count the trailing zero bits.
|
||||
*
|
||||
* \return The count of trailing zero bits in \a u.
|
||||
*/
|
||||
#if (defined __GNUC__) || (defined __CC_ARM)
|
||||
#define ctz(u) __builtin_ctz(u)
|
||||
#else
|
||||
#define ctz(u) \
|
||||
( \
|
||||
(u) & (1ul << 0) \
|
||||
? 0 \
|
||||
: (u) & (1ul << 1) \
|
||||
? 1 \
|
||||
: (u) & (1ul << 2) \
|
||||
? 2 \
|
||||
: (u) & (1ul << 3) \
|
||||
? 3 \
|
||||
: (u) & (1ul << 4) \
|
||||
? 4 \
|
||||
: (u) & (1ul << 5) \
|
||||
? 5 \
|
||||
: (u) & (1ul << 6) \
|
||||
? 6 \
|
||||
: (u) & (1ul << 7) \
|
||||
? 7 \
|
||||
: (u) & (1ul << 8) \
|
||||
? 8 \
|
||||
: (u) & (1ul << 9) \
|
||||
? 9 \
|
||||
: (u) & (1ul << 10) \
|
||||
? 10 \
|
||||
: (u) & (1ul << 11) \
|
||||
? 11 \
|
||||
: (u) & (1ul << 12) \
|
||||
? 12 \
|
||||
: (u) & (1ul << 13) \
|
||||
? 13 \
|
||||
: (u) & (1ul << 14) \
|
||||
? 14 \
|
||||
: (u) & (1ul << 15) \
|
||||
? 15 \
|
||||
: (u) & (1ul << 16) \
|
||||
? 16 \
|
||||
: (u) & (1ul << 17) \
|
||||
? 17 \
|
||||
: (u) & (1ul << 18) \
|
||||
? 18 \
|
||||
: (u) & (1ul << 19) ? 19 \
|
||||
: (u) & (1ul << 20) ? 20 \
|
||||
: (u) & (1ul << 21) ? 21 \
|
||||
: (u) & (1ul << 22) ? 22 \
|
||||
: (u) & (1ul << 23) ? 23 \
|
||||
: (u) & (1ul << 24) ? 24 \
|
||||
: (u) & (1ul << 25) ? 25 \
|
||||
: (u) & (1ul << 26) ? 26 \
|
||||
: (u) & (1ul << 27) ? 27 \
|
||||
: (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32)
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \brief Counts the number of bits in a mask (no more than 32 bits)
|
||||
* \param[in] mask Mask of which to count the bits.
|
||||
*/
|
||||
#define size_of_mask(mask) (32 - clz(mask) - ctz(mask))
|
||||
|
||||
/**
|
||||
* \brief Retrieve the start position of bits mask (no more than 32 bits)
|
||||
* \param[in] mask Mask of which to retrieve the start position.
|
||||
*/
|
||||
#define pos_of_mask(mask) ctz(mask)
|
||||
|
||||
/**
|
||||
* \brief Return division result of a/b and round up the result to the closest
|
||||
* number divisible by "b"
|
||||
*/
|
||||
#define round_up(a, b) (((a)-1) / (b) + 1)
|
||||
|
||||
/**
|
||||
* \brief Get the minimum of x and y
|
||||
*/
|
||||
#define min(x, y) ((x) > (y) ? (y) : (x))
|
||||
|
||||
/**
|
||||
* \brief Get the maximum of x and y
|
||||
*/
|
||||
#define max(x, y) ((x) > (y) ? (x) : (y))
|
||||
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* UTILS_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Asserts related functionality.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _ASSERT_H_INCLUDED
|
||||
#define _ASSERT_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifndef USE_SIMPLE_ASSERT
|
||||
//# define USE_SIMPLE_ASSERT
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Assert macro
|
||||
*
|
||||
* This macro is used to throw asserts. It can be mapped to different function
|
||||
* based on debug level.
|
||||
*
|
||||
* \param[in] condition A condition to be checked;
|
||||
* assert is thrown if the given condition is false
|
||||
*/
|
||||
#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__)
|
||||
|
||||
#ifdef DEBUG
|
||||
|
||||
#ifdef USE_SIMPLE_ASSERT
|
||||
#define ASSERT_IMPL(condition, file, line) \
|
||||
if (!(condition)) \
|
||||
__asm("BKPT #0");
|
||||
#else
|
||||
#define ASSERT_IMPL(condition, file, line) assert((condition), file, line)
|
||||
#endif
|
||||
|
||||
#else /* DEBUG */
|
||||
|
||||
#ifdef USE_SIMPLE_ASSERT
|
||||
#define ASSERT_IMPL(condition, file, line) ((void)0)
|
||||
#else
|
||||
#define ASSERT_IMPL(condition, file, line) ((void)0)
|
||||
#endif
|
||||
|
||||
#endif /* DEBUG */
|
||||
|
||||
/**
|
||||
* \brief Assert function
|
||||
*
|
||||
* This function is used to throw asserts.
|
||||
*
|
||||
* \param[in] condition A condition to be checked; assert is thrown if the given
|
||||
* condition is false
|
||||
* \param[in] file File name
|
||||
* \param[in] line Line number
|
||||
*/
|
||||
void assert(const bool condition, const char *const file, const int line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _ASSERT_H_INCLUDED */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue