commiting examples

2021-07-26 10:32:22 +02:00
parent 76cd702edc
commit 312768d2cf
589 changed files with 464854 additions and 446 deletions
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart
@@ -146,7 +146,7 @@ drivers:
        the transaction
      dmac_blockact_9: Channel will be disabled if it is the last block transfer in
        the transaction
-      dmac_channel_0_settings: false
+      dmac_channel_0_settings: true
      dmac_channel_10_settings: false
      dmac_channel_11_settings: false
      dmac_channel_12_settings: false
@@ -157,7 +157,7 @@ drivers:
      dmac_channel_17_settings: false
      dmac_channel_18_settings: false
      dmac_channel_19_settings: false
-      dmac_channel_1_settings: false
+      dmac_channel_1_settings: true
      dmac_channel_20_settings: false
      dmac_channel_21_settings: false
      dmac_channel_22_settings: false
@@ -179,7 +179,7 @@ drivers:
      dmac_channel_8_settings: false
      dmac_channel_9_settings: false
      dmac_dbgrun: false
-      dmac_dstinc_0: false
+      dmac_dstinc_0: true
      dmac_dstinc_1: false
      dmac_dstinc_10: false
      dmac_dstinc_11: false
@@ -276,8 +276,8 @@ drivers:
      dmac_evie_7: false
      dmac_evie_8: false
      dmac_evie_9: false
-      dmac_evoe_0: false
-      dmac_evoe_1: false
+      dmac_evoe_0: true
+      dmac_evoe_1: true
      dmac_evoe_10: false
      dmac_evoe_11: false
      dmac_evoe_12: false
@@ -308,8 +308,8 @@ drivers:
      dmac_evoe_7: false
      dmac_evoe_8: false
      dmac_evoe_9: false
-      dmac_evosel_0: Event generation disabled
-      dmac_evosel_1: Event generation disabled
+      dmac_evosel_0: Event strobe when beat transfer complete
+      dmac_evosel_1: Event strobe when beat transfer complete
      dmac_evosel_10: Event generation disabled
      dmac_evosel_11: Event generation disabled
      dmac_evosel_12: Event generation disabled
@@ -417,7 +417,7 @@ drivers:
      dmac_runstdby_8: false
      dmac_runstdby_9: false
      dmac_srcinc_0: false
-      dmac_srcinc_1: false
+      dmac_srcinc_1: true
      dmac_srcinc_10: false
      dmac_srcinc_11: false
      dmac_srcinc_12: false
@@ -448,7 +448,7 @@ drivers:
      dmac_srcinc_7: false
      dmac_srcinc_8: false
      dmac_srcinc_9: false
-      dmac_stepsel_0: Step size settings apply to the destination address
+      dmac_stepsel_0: Step size settings apply to the source address
      dmac_stepsel_1: Step size settings apply to the destination address
      dmac_stepsel_10: Step size settings apply to the destination address
      dmac_stepsel_11: Step size settings apply to the destination address
@@ -512,8 +512,8 @@ drivers:
      dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
-      dmac_trifsrc_0: Only software/event triggers
-      dmac_trifsrc_1: Only software/event triggers
+      dmac_trifsrc_0: SERCOM5 RX Trigger
+      dmac_trifsrc_1: SERCOM5 TX Trigger
      dmac_trifsrc_10: Only software/event triggers
      dmac_trifsrc_11: Only software/event triggers
      dmac_trifsrc_12: Only software/event triggers
@@ -544,8 +544,8 @@ drivers:
      dmac_trifsrc_7: Only software/event triggers
      dmac_trifsrc_8: Only software/event triggers
      dmac_trifsrc_9: Only software/event triggers
-      dmac_trigact_0: One trigger required for each block transfer
-      dmac_trigact_1: One trigger required for each block transfer
+      dmac_trigact_0: One trigger required for each beat transfer
+      dmac_trigact_1: One trigger required for each beat transfer
      dmac_trigact_10: One trigger required for each block transfer
      dmac_trigact_11: One trigger required for each block transfer
      dmac_trigact_12: One trigger required for each block transfer
@@ -588,9 +588,9 @@ drivers:
    configuration:
      evsys_channel_0: No channel output selected
      evsys_channel_1: No channel output selected
-      evsys_channel_10: Channel 0
-      evsys_channel_11: Channel 0
-      evsys_channel_12: Channel 0
+      evsys_channel_10: No channel output selected
+      evsys_channel_11: No channel output selected
+      evsys_channel_12: No channel output selected
      evsys_channel_17: No channel output selected
      evsys_channel_18: No channel output selected
      evsys_channel_19: No channel output selected
@@ -627,7 +627,7 @@ drivers:
      evsys_channel_47: No channel output selected
      evsys_channel_48: No channel output selected
      evsys_channel_49: No channel output selected
-      evsys_channel_5: Channel 0
+      evsys_channel_5: No channel output selected
      evsys_channel_50: No channel output selected
      evsys_channel_51: No channel output selected
      evsys_channel_52: No channel output selected
@@ -638,7 +638,7 @@ drivers:
      evsys_channel_57: No channel output selected
      evsys_channel_58: No channel output selected
      evsys_channel_59: No channel output selected
-      evsys_channel_6: Channel 0
+      evsys_channel_6: No channel output selected
      evsys_channel_60: No channel output selected
      evsys_channel_61: No channel output selected
      evsys_channel_62: No channel output selected
@@ -646,10 +646,10 @@ drivers:
      evsys_channel_64: No channel output selected
      evsys_channel_65: No channel output selected
      evsys_channel_66: No channel output selected
-      evsys_channel_7: Channel 0
-      evsys_channel_8: Channel 0
-      evsys_channel_9: Channel 0
-      evsys_channel_setting_0: true
+      evsys_channel_7: No channel output selected
+      evsys_channel_8: No channel output selected
+      evsys_channel_9: No channel output selected
+      evsys_channel_setting_0: false
      evsys_channel_setting_1: false
      evsys_channel_setting_10: false
      evsys_channel_setting_11: false
@@ -1013,11 +1013,11 @@ drivers:
      $input_id: External Crystal Oscillator 8-48MHz (XOSC1)
      RESERVED_InputFreq: 12000000
      RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1)
-      _$freq_output_Generic clock generator 0: 12000000
-      _$freq_output_Generic clock generator 1: 48000000
+      _$freq_output_Generic clock generator 0: 120000000
+      _$freq_output_Generic clock generator 1: 2000000
      _$freq_output_Generic clock generator 10: 12000000
      _$freq_output_Generic clock generator 11: 12000000
-      _$freq_output_Generic clock generator 2: 3000000
+      _$freq_output_Generic clock generator 2: 32768
      _$freq_output_Generic clock generator 3: 32768
      _$freq_output_Generic clock generator 4: 12000000
      _$freq_output_Generic clock generator 5: 12000000
@@ -1027,13 +1027,13 @@ drivers:
      _$freq_output_Generic clock generator 9: 12000000
      enable_gclk_gen_0: true
      enable_gclk_gen_0__externalclock: 1000000
-      enable_gclk_gen_1: false
+      enable_gclk_gen_1: true
      enable_gclk_gen_10: false
      enable_gclk_gen_10__externalclock: 1000000
      enable_gclk_gen_11: false
      enable_gclk_gen_11__externalclock: 1000000
      enable_gclk_gen_1__externalclock: 1000000
-      enable_gclk_gen_2: false
+      enable_gclk_gen_2: true
      enable_gclk_gen_2__externalclock: 1000000
      enable_gclk_gen_3: false
      enable_gclk_gen_3__externalclock: 1000000
@@ -1051,7 +1051,7 @@ drivers:
      enable_gclk_gen_9__externalclock: 1000000
      gclk_arch_gen_0_enable: true
      gclk_arch_gen_0_idc: false
-      gclk_arch_gen_0_oe: false
+      gclk_arch_gen_0_oe: true
      gclk_arch_gen_0_oov: false
      gclk_arch_gen_0_runstdby: false
      gclk_arch_gen_10_enable: false
@@ -1064,14 +1064,14 @@ drivers:
      gclk_arch_gen_11_oe: false
      gclk_arch_gen_11_oov: false
      gclk_arch_gen_11_runstdby: false
-      gclk_arch_gen_1_enable: false
+      gclk_arch_gen_1_enable: true
      gclk_arch_gen_1_idc: false
-      gclk_arch_gen_1_oe: false
+      gclk_arch_gen_1_oe: true
      gclk_arch_gen_1_oov: false
      gclk_arch_gen_1_runstdby: false
-      gclk_arch_gen_2_enable: false
+      gclk_arch_gen_2_enable: true
      gclk_arch_gen_2_idc: false
-      gclk_arch_gen_2_oe: false
+      gclk_arch_gen_2_oe: true
      gclk_arch_gen_2_oov: false
      gclk_arch_gen_2_runstdby: false
      gclk_arch_gen_3_enable: false
@@ -1111,19 +1111,19 @@ drivers:
      gclk_arch_gen_9_runstdby: false
      gclk_gen_0_div: 1
      gclk_gen_0_div_sel: false
-      gclk_gen_0_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+      gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL1)
      gclk_gen_10_div: 1
      gclk_gen_10_div_sel: false
      gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
      gclk_gen_11_div: 1
      gclk_gen_11_div_sel: false
      gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
-      gclk_gen_1_div: 1
+      gclk_gen_1_div: 24
      gclk_gen_1_div_sel: false
      gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M)
      gclk_gen_2_div: 1
-      gclk_gen_2_div_sel: true
-      gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+      gclk_gen_2_div_sel: false
+      gclk_gen_2_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
      gclk_gen_3_div: 1
      gclk_gen_3_div_sel: false
      gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
@@ -1155,11 +1155,11 @@ drivers:
    functionality: System
    api: HAL:HPL:MCLK
    configuration:
-      $input: 12000000
+      $input: 120000000
      $input_id: Generic clock generator 0
-      RESERVED_InputFreq: 12000000
+      RESERVED_InputFreq: 120000000
      RESERVED_InputFreq_id: Generic clock generator 0
-      _$freq_output_CPU: 12000000
+      _$freq_output_CPU: 120000000
      cpu_clock_source: Generic clock generator 0
      cpu_div: '1'
      enable_cpu_clock: true
@@ -1216,13 +1216,13 @@ drivers:
    functionality: System
    api: HAL:HPL:OSCCTRL
    configuration:
-      $input: 32768
-      $input_id: 32kHz External Crystal Oscillator (XOSC32K)
-      RESERVED_InputFreq: 32768
-      RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)
+      $input: 2000000
+      $input_id: Generic clock generator 1
+      RESERVED_InputFreq: 2000000
+      RESERVED_InputFreq_id: Generic clock generator 1
      _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
      _$freq_output_Digital Phase Locked Loop (DPLL0): 47985664
-      _$freq_output_Digital Phase Locked Loop (DPLL1): 47985664
+      _$freq_output_Digital Phase Locked Loop (DPLL1): 120000000
      _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000
      _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000
      dfll_arch_bplckc: false
@@ -1230,7 +1230,7 @@ drivers:
      dfll_arch_ccdis: false
      dfll_arch_coarse: 31
      dfll_arch_cstep: 1
-      dfll_arch_enable: false
+      dfll_arch_enable: true
      dfll_arch_fine: 128
      dfll_arch_fstep: 1
      dfll_arch_llaw: false
@@ -1242,10 +1242,10 @@ drivers:
      dfll_arch_waitlock: true
      dfll_mode: Open Loop Mode
      dfll_mul: 0
-      dfll_ref_clock: Generic clock generator 3
-      enable_dfll: false
+      dfll_ref_clock: Generic clock generator 2
+      enable_dfll: true
      enable_fdpll0: false
-      enable_fdpll1: false
+      enable_fdpll1: true
      enable_xosc0: false
      enable_xosc1: true
      fdpll0_arch_dcoen: false
@@ -1263,19 +1263,19 @@ drivers:
      fdpll0_ldrfrac: 13
      fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
      fdpll1_arch_dcoen: false
-      fdpll1_arch_enable: false
+      fdpll1_arch_enable: true
      fdpll1_arch_filter: 0
      fdpll1_arch_lbypass: false
      fdpll1_arch_ltime: No time-out, automatic lock
      fdpll1_arch_ondemand: false
-      fdpll1_arch_refclk: XOSC32K clock reference
+      fdpll1_arch_refclk: GCLK clock reference
      fdpll1_arch_runstdby: false
      fdpll1_arch_wuf: false
      fdpll1_clock_dcofilter: 0
      fdpll1_clock_div: 0
-      fdpll1_ldr: 1463
-      fdpll1_ldrfrac: 13
-      fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
+      fdpll1_ldr: 59
+      fdpll1_ldrfrac: 0
+      fdpll1_ref_clock: Generic clock generator 1
      xosc0_arch_cfden: false
      xosc0_arch_enable: false
      xosc0_arch_enalc: false
@@ -1527,6 +1527,53 @@ drivers:
        configuration:
          core_gclk_selection: Generic clock generator 0
          slow_gclk_selection: Generic clock generator 3
+  SPI_1:
+    user_label: SPI_1
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM5::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.DMA
+    functionality: SPI
+    api: HAL:Driver:SPI_Master_DMA
+    configuration:
+      spi_master_advanced: true
+      spi_master_arch_cpha: Sample input on leading edge
+      spi_master_arch_cpol: SCK is low when idle
+      spi_master_arch_dbgstop: Keep running
+      spi_master_arch_dord: MSB first
+      spi_master_arch_ibon: In data stream
+      spi_master_arch_runstdby: false
+      spi_master_baud_rate: 10000000
+      spi_master_character_size: 8 bits
+      spi_master_dma_rx_channel: 0
+      spi_master_dma_tx_channel: 1
+      spi_master_dummybyte: 511
+      spi_master_rx_channel: true
+      spi_master_rx_enable: true
+    optional_signals: []
+    variant:
+      specification: TXPO=0, RXPO=3
+      required_signals:
+      - name: SERCOM5/PAD/0
+        pad: PB16
+        label: MOSI
+      - name: SERCOM5/PAD/1
+        pad: PB17
+        label: SCK
+      - name: SERCOM5/PAD/3
+        pad: PB01
+        label: MISO
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Slow
+          input: Generic clock generator 3
+          external: false
+          external_frequency: 0
+        configuration:
+          core_gclk_selection: Generic clock generator 0
+          slow_gclk_selection: Generic clock generator 3
  TIMER_0:
    user_label: TIMER_0
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer
@@ -1587,6 +1634,66 @@ drivers:
          external_frequency: 0
        configuration:
          tc_gclk_selection: Generic clock generator 0
+  TC_ECAT:
+    user_label: TC_ECAT
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC7::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer
+    functionality: Timer
+    api: Lite:TC:Timer
+    configuration:
+      cc_cc0: 30000
+      cc_cc1: 0
+      cc_control: true
+      count_control: false
+      count_count: 0
+      ctrla_alock: false
+      ctrla_capten0: false
+      ctrla_capten1: false
+      ctrla_captmode0: DEFAULT
+      ctrla_captmode1: DEFAULT
+      ctrla_control: true
+      ctrla_copen0: false
+      ctrla_copen1: false
+      ctrla_enable: true
+      ctrla_mode: 0
+      ctrla_ondemand: false
+      ctrla_prescaler: DIV4
+      ctrla_prescsync: GCLK
+      ctrla_runstdby: false
+      ctrlbset_cmd: NONE
+      ctrlbset_control: false
+      ctrlbset_dir: false
+      ctrlbset_lupd: false
+      ctrlbset_oneshot: false
+      ctrlc_inven0: false
+      ctrlc_inven1: false
+      dbgctrl_control: false
+      dbgctrl_dbgrun: false
+      drvctrl_control: false
+      evctrl_control: true
+      evctrl_evact: 'OFF'
+      evctrl_mceo0: true
+      evctrl_mceo1: false
+      evctrl_ovfeo: false
+      evctrl_tcei: false
+      evctrl_tcinv: false
+      intenset_control: true
+      intenset_err: false
+      intenset_mc0: false
+      intenset_mc1: false
+      intenset_ovf: true
+      wave_control: true
+      wave_wavegen: MFRQ
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: TC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          tc_gclk_selection: Generic clock generator 0
 pads:
  PA08:
    name: PA08
@@ -1624,6 +1731,18 @@ pads:
    mode: Digital input
    user_label: PB11
    configuration: null
+  PB16:
+    name: PB16
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB16
+    mode: Digital output
+    user_label: PB16
+    configuration: null
+  PB17:
+    name: PB17
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB17
+    mode: Digital output
+    user_label: PB17
+    configuration: null
  PB24:
    name: PB24
    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24
@@ -1661,5 +1780,17 @@ pads:
    mode: Digital input
    user_label: PB29
    configuration: null
+  ECAT_SPI_CS_PIN:
+    name: PB00
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB00
+    mode: Digital output
+    user_label: ECAT_SPI_CS_PIN
+    configuration: null
+  PB01:
+    name: PB01
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB01
+    mode: Digital input
+    user_label: PB01
+    configuration: null
 toolchain_options: []
 static_files: []
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_dmac_config.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_dmac_config.h
@@ -105,7 +105,7 @@
 // <e> Channel 0 settings
 // <id> dmac_channel_0_settings
 #ifndef CONF_DMAC_CHANNEL_0_SETTINGS
-#define CONF_DMAC_CHANNEL_0_SETTINGS 0
+#define CONF_DMAC_CHANNEL_0_SETTINGS 1
 #endif

 // <q> Channel Run in Standby
@@ -122,7 +122,7 @@
 // <i> Defines the trigger action used for a transfer
 // <id> dmac_trigact_0
 #ifndef CONF_DMAC_TRIGACT_0
-#define CONF_DMAC_TRIGACT_0 0
+#define CONF_DMAC_TRIGACT_0 2
 #endif

 // <o> Trigger source
@@ -214,7 +214,7 @@
 // <i> Defines the peripheral trigger which is source of the transfer
 // <id> dmac_trifsrc_0
 #ifndef CONF_DMAC_TRIGSRC_0
-#define CONF_DMAC_TRIGSRC_0 0
+#define CONF_DMAC_TRIGSRC_0 14
 #endif

 // <o> Channel Arbitration Level
@@ -232,7 +232,7 @@
 // <i> Indicates whether channel event generation is enabled or not
 // <id> dmac_evoe_0
 #ifndef CONF_DMAC_EVOE_0
-#define CONF_DMAC_EVOE_0 0
+#define CONF_DMAC_EVOE_0 1
 #endif

 // <q> Channel Event Input
@@ -277,7 +277,7 @@
 // <i> Defines whether source or destination addresses are using the step size settings
 // <id> dmac_stepsel_0
 #ifndef CONF_DMAC_STEPSEL_0
-#define CONF_DMAC_STEPSEL_0 0
+#define CONF_DMAC_STEPSEL_0 1
 #endif

 // <q> Source Address Increment
@@ -291,7 +291,7 @@
 // <i> Indicates whether the destination address incrementation is enabled or not
 // <id> dmac_dstinc_0
 #ifndef CONF_DMAC_DSTINC_0
-#define CONF_DMAC_DSTINC_0 0
+#define CONF_DMAC_DSTINC_0 1
 #endif

 // <o> Beat Size
@@ -322,14 +322,14 @@
 // <i> Defines the event output selection
 // <id> dmac_evosel_0
 #ifndef CONF_DMAC_EVOSEL_0
-#define CONF_DMAC_EVOSEL_0 0
+#define CONF_DMAC_EVOSEL_0 3
 #endif
 // </e>

 // <e> Channel 1 settings
 // <id> dmac_channel_1_settings
 #ifndef CONF_DMAC_CHANNEL_1_SETTINGS
-#define CONF_DMAC_CHANNEL_1_SETTINGS 0
+#define CONF_DMAC_CHANNEL_1_SETTINGS 1
 #endif

 // <q> Channel Run in Standby
@@ -346,7 +346,7 @@
 // <i> Defines the trigger action used for a transfer
 // <id> dmac_trigact_1
 #ifndef CONF_DMAC_TRIGACT_1
-#define CONF_DMAC_TRIGACT_1 0
+#define CONF_DMAC_TRIGACT_1 2
 #endif

 // <o> Trigger source
@@ -438,7 +438,7 @@
 // <i> Defines the peripheral trigger which is source of the transfer
 // <id> dmac_trifsrc_1
 #ifndef CONF_DMAC_TRIGSRC_1
-#define CONF_DMAC_TRIGSRC_1 0
+#define CONF_DMAC_TRIGSRC_1 15
 #endif

 // <o> Channel Arbitration Level
@@ -456,7 +456,7 @@
 // <i> Indicates whether channel event generation is enabled or not
 // <id> dmac_evoe_1
 #ifndef CONF_DMAC_EVOE_1
-#define CONF_DMAC_EVOE_1 0
+#define CONF_DMAC_EVOE_1 1
 #endif

 // <q> Channel Event Input
@@ -508,7 +508,7 @@
 // <i> Indicates whether the source address incrementation is enabled or not
 // <id> dmac_srcinc_1
 #ifndef CONF_DMAC_SRCINC_1
-#define CONF_DMAC_SRCINC_1 0
+#define CONF_DMAC_SRCINC_1 1
 #endif

 // <q> Destination Address Increment
@@ -546,7 +546,7 @@
 // <i> Defines the event output selection
 // <id> dmac_evosel_1
 #ifndef CONF_DMAC_EVOSEL_1
-#define CONF_DMAC_EVOSEL_1 0
+#define CONF_DMAC_EVOSEL_1 3
 #endif
 // </e>

--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_evsys_config.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_evsys_config.h
@@ -7,7 +7,7 @@
 // <e> Channel 0 settings
 // <id> evsys_channel_setting_0
 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_0
-#define CONF_EVSYS_CHANNEL_SETTINGS_0 1
+#define CONF_EVSYS_CHANNEL_SETTINGS_0 0
 #endif

 // <y> Edge detection
@@ -6042,7 +6042,7 @@
 // <id> evsys_channel_5
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_5
-#define CONF_CHANNEL_5 1
+#define CONF_CHANNEL_5 0
 #endif

 // <o> Channel selection for DMAC channel 1
@@ -6082,7 +6082,7 @@
 // <id> evsys_channel_6
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_6
-#define CONF_CHANNEL_6 1
+#define CONF_CHANNEL_6 0
 #endif

 // <o> Channel selection for DMAC channel 2
@@ -6122,7 +6122,7 @@
 // <id> evsys_channel_7
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_7
-#define CONF_CHANNEL_7 1
+#define CONF_CHANNEL_7 0
 #endif

 // <o> Channel selection for DMAC channel 3
@@ -6162,7 +6162,7 @@
 // <id> evsys_channel_8
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_8
-#define CONF_CHANNEL_8 1
+#define CONF_CHANNEL_8 0
 #endif

 // <o> Channel selection for DMAC channel 4
@@ -6202,7 +6202,7 @@
 // <id> evsys_channel_9
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_9
-#define CONF_CHANNEL_9 1
+#define CONF_CHANNEL_9 0
 #endif

 // <o> Channel selection for DMAC channel 5
@@ -6242,7 +6242,7 @@
 // <id> evsys_channel_10
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_10
-#define CONF_CHANNEL_10 1
+#define CONF_CHANNEL_10 0
 #endif

 // <o> Channel selection for DMAC channel 6
@@ -6282,7 +6282,7 @@
 // <id> evsys_channel_11
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_11
-#define CONF_CHANNEL_11 1
+#define CONF_CHANNEL_11 0
 #endif

 // <o> Channel selection for DMAC channel 7
@@ -6322,7 +6322,7 @@
 // <id> evsys_channel_12
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_12
-#define CONF_CHANNEL_12 1
+#define CONF_CHANNEL_12 0
 #endif
 //</h>

--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_gclk_config.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_gclk_config.h
@@ -25,7 +25,7 @@
 // <i> This defines the clock source for generic clock generator 0
 // <id> gclk_gen_0_oscillator
 #ifndef CONF_GCLK_GEN_0_SOURCE
-#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL1
 #endif

 // <q> Run in Standby
@@ -46,7 +46,7 @@
 // <i> Indicates whether Output Enable is enabled or not
 // <id> gclk_arch_gen_0_oe
 #ifndef CONF_GCLK_GEN_0_OE
-#define CONF_GCLK_GEN_0_OE 0
+#define CONF_GCLK_GEN_0_OE 1
 #endif

 // <q> Output Off Value
@@ -84,7 +84,7 @@
 // <i> Indicates whether generic clock 1 configuration is enabled or not
 // <id> enable_gclk_gen_1
 #ifndef CONF_GCLK_GENERATOR_1_CONFIG
-#define CONF_GCLK_GENERATOR_1_CONFIG 0
+#define CONF_GCLK_GENERATOR_1_CONFIG 1
 #endif

 // <h> Generic Clock Generator Control
@@ -121,7 +121,7 @@
 // <i> Indicates whether Output Enable is enabled or not
 // <id> gclk_arch_gen_1_oe
 #ifndef CONF_GCLK_GEN_1_OE
-#define CONF_GCLK_GEN_1_OE 0
+#define CONF_GCLK_GEN_1_OE 1
 #endif

 // <q> Output Off Value
@@ -142,7 +142,7 @@
 // <i> Indicates whether Generic Clock Generator Enable is enabled or not
 // <id> gclk_arch_gen_1_enable
 #ifndef CONF_GCLK_GEN_1_GENEN
-#define CONF_GCLK_GEN_1_GENEN 0
+#define CONF_GCLK_GEN_1_GENEN 1
 #endif
 // </h>

@@ -150,7 +150,7 @@
 //<o> Generic clock generator 1 division <0x0000-0xFFFF>
 // <id> gclk_gen_1_div
 #ifndef CONF_GCLK_GEN_1_DIV
-#define CONF_GCLK_GEN_1_DIV 1
+#define CONF_GCLK_GEN_1_DIV 24
 #endif
 // </h>
 // </e>
@@ -159,7 +159,7 @@
 // <i> Indicates whether generic clock 2 configuration is enabled or not
 // <id> enable_gclk_gen_2
 #ifndef CONF_GCLK_GENERATOR_2_CONFIG
-#define CONF_GCLK_GENERATOR_2_CONFIG 0
+#define CONF_GCLK_GENERATOR_2_CONFIG 1
 #endif

 // <h> Generic Clock Generator Control
@@ -176,7 +176,7 @@
 // <i> This defines the clock source for generic clock generator 2
 // <id> gclk_gen_2_oscillator
 #ifndef CONF_GCLK_GEN_2_SOURCE
-#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSCULP32K
 #endif

 // <q> Run in Standby
@@ -190,14 +190,14 @@
 // <i> Indicates whether Divide Selection is enabled or not
 //<id> gclk_gen_2_div_sel
 #ifndef CONF_GCLK_GEN_2_DIVSEL
-#define CONF_GCLK_GEN_2_DIVSEL 1
+#define CONF_GCLK_GEN_2_DIVSEL 0
 #endif

 // <q> Output Enable
 // <i> Indicates whether Output Enable is enabled or not
 // <id> gclk_arch_gen_2_oe
 #ifndef CONF_GCLK_GEN_2_OE
-#define CONF_GCLK_GEN_2_OE 0
+#define CONF_GCLK_GEN_2_OE 1
 #endif

 // <q> Output Off Value
@@ -218,7 +218,7 @@
 // <i> Indicates whether Generic Clock Generator Enable is enabled or not
 // <id> gclk_arch_gen_2_enable
 #ifndef CONF_GCLK_GEN_2_GENEN
-#define CONF_GCLK_GEN_2_GENEN 0
+#define CONF_GCLK_GEN_2_GENEN 1
 #endif
 // </h>

--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_oscctrl_config.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_oscctrl_config.h
@@ -234,7 +234,7 @@
 // <i> Indicates whether configuration for DFLL is enabled or not
 // <id> enable_dfll
 #ifndef CONF_DFLL_CONFIG
-#define CONF_DFLL_CONFIG 0
+#define CONF_DFLL_CONFIG 1
 #endif

 // <y> Reference Clock Source
@@ -253,7 +253,7 @@
 // <i> Select the clock source
 // <id> dfll_ref_clock
 #ifndef CONF_DFLL_GCLK
-#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
+#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK2_Val
 #endif

 // <h> Digital Frequency Locked Loop Control
@@ -261,7 +261,7 @@
 // <i> Indicates whether DFLL is enabled or not
 // <id> dfll_arch_enable
 #ifndef CONF_DFLL_ENABLE
-#define CONF_DFLL_ENABLE 0
+#define CONF_DFLL_ENABLE 1
 #endif

 // <q> On Demand Control
@@ -510,7 +510,7 @@
 // <i> Indicates whether configuration for FDPLL1 is enabled or not
 // <id> enable_fdpll1
 #ifndef CONF_FDPLL1_CONFIG
-#define CONF_FDPLL1_CONFIG 0
+#define CONF_FDPLL1_CONFIG 1
 #endif

 // <y> Reference Clock Source
@@ -532,7 +532,7 @@
 // <i> Select the clock source.
 // <id> fdpll1_ref_clock
 #ifndef CONF_FDPLL1_GCLK
-#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K
+#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK1_Val
 #endif

 // <h> Digital Phase Locked Loop Control
@@ -540,7 +540,7 @@
 // <i> Indicates whether Digital Phase Locked Loop is enabled or not
 // <id> fdpll1_arch_enable
 #ifndef CONF_FDPLL1_ENABLE
-#define CONF_FDPLL1_ENABLE 0
+#define CONF_FDPLL1_ENABLE 1
 #endif

 // <q> On Demand Control
@@ -561,14 +561,14 @@
 // <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
 // <id> fdpll1_ldrfrac
 #ifndef CONF_FDPLL1_LDRFRAC
-#define CONF_FDPLL1_LDRFRAC 0xd
+#define CONF_FDPLL1_LDRFRAC 0x0
 #endif

 // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
 // <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
 // <id> fdpll1_ldr
 #ifndef CONF_FDPLL1_LDR
-#define CONF_FDPLL1_LDR 0x5b7
+#define CONF_FDPLL1_LDR 0x3b
 #endif

 // <o> Clock Divider <0x0-0x7FF>
@@ -616,7 +616,7 @@
 // <0x3=>XOSC1 clock reference
 // <id> fdpll1_arch_refclk
 #ifndef CONF_FDPLL1_REFCLK
-#define CONF_FDPLL1_REFCLK 0x1
+#define CONF_FDPLL1_REFCLK 0x0
 #endif

 // <q> Wake Up Fast
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_sercom_config.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_sercom_config.h
@@ -454,6 +454,187 @@
 #define CONF_SERCOM_4_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM4_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_4_SPI_BAUD)) - 1
 #endif

+#include <peripheral_clk_config.h>
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_5_SPI_ENABLE
+#define CONF_SERCOM_5_SPI_ENABLE 1
+#endif
+
+//<o> SPI DMA TX Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> spi_master_dma_tx_channel
+#ifndef CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_5_SPI_M_DMA_TX_CHANNEL 1
+#endif
+
+// <e> SPI RX Channel Enable
+// <id> spi_master_rx_channel
+#ifndef CONF_SERCOM_5_SPI_RX_CHANNEL
+#define CONF_SERCOM_5_SPI_RX_CHANNEL 1
+#endif
+
+//<o> DMA Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> spi_master_dma_rx_channel
+#ifndef CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_5_SPI_M_DMA_RX_CHANNEL 0
+#endif
+
+// </e>
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_5_SPI_MODE
+#define CONF_SERCOM_5_SPI_MODE 0x03
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave (RXEN)
+// <id> spi_master_rx_enable
+#ifndef CONF_SERCOM_5_SPI_RXEN
+#define CONF_SERCOM_5_SPI_RXEN 0x1
+#endif
+
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_master_character_size
+#ifndef CONF_SERCOM_5_SPI_CHSIZE
+#define CONF_SERCOM_5_SPI_CHSIZE 0x0
+#endif
+// <o> Baud rate <1-18000000>
+// <i> The SPI data transfer rate
+// <id> spi_master_baud_rate
+#ifndef CONF_SERCOM_5_SPI_BAUD
+#define CONF_SERCOM_5_SPI_BAUD 10000000
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> spi_master_advanced
+#ifndef CONF_SERCOM_5_SPI_ADVANCED
+#define CONF_SERCOM_5_SPI_ADVANCED 1
+#endif
+
+// <o> Dummy byte <0x00-0x1ff>
+// <id> spi_master_dummybyte
+// <i> Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_5_SPI_DUMMYBYTE
+#define CONF_SERCOM_5_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first (DORD)
+// <id> spi_master_arch_dord
+#ifndef CONF_SERCOM_5_SPI_DORD
+#define CONF_SERCOM_5_SPI_DORD 0x0
+#endif
+
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_master_arch_cpol
+#ifndef CONF_SERCOM_5_SPI_CPOL
+#define CONF_SERCOM_5_SPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_master_arch_cpha
+#ifndef CONF_SERCOM_5_SPI_CPHA
+#define CONF_SERCOM_5_SPI_CPHA 0x0
+#endif
+
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_master_arch_ibon
+#ifndef CONF_SERCOM_5_SPI_IBON
+#define CONF_SERCOM_5_SPI_IBON 0x0
+#endif
+
+// <q> Run in stand-by
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_master_arch_runstdby
+#ifndef CONF_SERCOM_5_SPI_RUNSTDBY
+#define CONF_SERCOM_5_SPI_RUNSTDBY 0x0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// <id> spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_5_SPI_DBGSTOP
+#define CONF_SERCOM_5_SPI_DBGSTOP 0
+#endif
+
+// </e>
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_5_SPI_AMODE_EN
+#define CONF_SERCOM_5_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_AMODE
+#define CONF_SERCOM_5_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_ADDR
+#define CONF_SERCOM_5_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_ADDRMASK
+#define CONF_SERCOM_5_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_SSDE
+#define CONF_SERCOM_5_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_MSSEN
+#define CONF_SERCOM_5_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_PLOADEN
+#define CONF_SERCOM_5_SPI_PLOADEN 0
+#endif
+
+// <o> Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// <id> spi_master_rxpo
+#ifndef CONF_SERCOM_5_SPI_RXPO
+#define CONF_SERCOM_5_SPI_RXPO 3
+#endif
+
+// <o> Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// <id> spi_master_txpo
+#ifndef CONF_SERCOM_5_SPI_TXPO
+#define CONF_SERCOM_5_SPI_TXPO 0
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_5_SPI_BAUD_RATE
+#define CONF_SERCOM_5_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM5_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_5_SPI_BAUD)) - 1
+#endif
+
 // <<< end of configuration section >>>

 #endif // HPL_SERCOM_CONFIG_H
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/peripheral_clk_config.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/peripheral_clk_config.h
@@ -42,7 +42,7 @@
 */

 #ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 12000000
+#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000
 #endif

 // <y> EVSYS Channel 1 Clock Source
@@ -83,7 +83,7 @@
 */

 #ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 12000000
+#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000
 #endif

 // <y> EVSYS Channel 2 Clock Source
@@ -124,7 +124,7 @@
 */

 #ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 12000000
+#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000
 #endif

 // <y> EVSYS Channel 3 Clock Source
@@ -165,7 +165,7 @@
 */

 #ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 12000000
+#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000
 #endif

 // <y> EVSYS Channel 4 Clock Source
@@ -206,7 +206,7 @@
 */

 #ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 12000000
+#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000
 #endif

 // <y> EVSYS Channel 5 Clock Source
@@ -247,7 +247,7 @@
 */

 #ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 12000000
+#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000
 #endif

 // <y> EVSYS Channel 6 Clock Source
@@ -288,7 +288,7 @@
 */

 #ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 12000000
+#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000
 #endif

 // <y> EVSYS Channel 7 Clock Source
@@ -329,7 +329,7 @@
 */

 #ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 12000000
+#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000
 #endif

 // <y> EVSYS Channel 8 Clock Source
@@ -370,7 +370,7 @@
 */

 #ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 12000000
+#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000
 #endif

 // <y> EVSYS Channel 9 Clock Source
@@ -411,7 +411,7 @@
 */

 #ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 12000000
+#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000
 #endif

 // <y> EVSYS Channel 10 Clock Source
@@ -452,7 +452,7 @@
 */

 #ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 12000000
+#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000
 #endif

 // <y> EVSYS Channel 11 Clock Source
@@ -493,7 +493,7 @@
 */

 #ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 12000000
+#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000
 #endif

 /**
@@ -501,7 +501,7 @@
 * \brief CPU's Clock frequency
 */
 #ifndef CONF_CPU_FREQUENCY
-#define CONF_CPU_FREQUENCY 12000000
+#define CONF_CPU_FREQUENCY 120000000
 #endif

 // <y> Core Clock Source
@@ -573,7 +573,7 @@
 * \brief SERCOM2's Core Clock frequency
 */
 #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 12000000
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 120000000
 #endif

 /**
@@ -653,7 +653,7 @@
 * \brief SERCOM4's Core Clock frequency
 */
 #ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 12000000
+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 120000000
 #endif

 /**
@@ -664,6 +664,86 @@
 #define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768
 #endif

+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM5_CORE_SRC
+#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM5_SLOW_SRC
+#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM5_CORE_FREQUENCY
+ * \brief SERCOM5's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 120000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM5_SLOW_FREQUENCY
+ * \brief SERCOM5's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM5_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768
+#endif
+
 // <y> TC Clock Source
 // <id> tc_gclk_selection

@@ -701,7 +781,47 @@
 * \brief TC0's Clock frequency
 */
 #ifndef CONF_GCLK_TC0_FREQUENCY
-#define CONF_GCLK_TC0_FREQUENCY 12000000
+#define CONF_GCLK_TC0_FREQUENCY 120000000
+#endif
+
+// <y> TC Clock Source
+// <id> tc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for TC.
+#ifndef CONF_GCLK_TC7_SRC
+#define CONF_GCLK_TC7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TC7_FREQUENCY
+ * \brief TC7's Clock frequency
+ */
+#ifndef CONF_GCLK_TC7_FREQUENCY
+#define CONF_GCLK_TC7_FREQUENCY 120000000
 #endif

 // <<< end of configuration section >>>
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj
@@ -152,11 +152,11 @@
          <AcmeProjectActionInfo Action="File" Source="stdio_redirect/stdio_io.c" IsConfig="false" Hash="Nx8PfIAymK/f5AjLql/CyQ" />
          <AcmeProjectActionInfo Action="File" Source="stdio_redirect/stdio_io.h" IsConfig="false" Hash="4X02f8UL8cjBHeGJM3BnHw" />
          <AcmeProjectActionInfo Action="File" Source="main.c" IsConfig="false" Hash="k0AH7j+BrmdFhBPzCCMptA" />
-          <AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="2sHYZTuLryCX1YMXh3fv4g" />
-          <AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="SmSCndG2nTv95r8KyRfSNw" />
-          <AcmeProjectActionInfo Action="File" Source="atmel_start_pins.h" IsConfig="false" Hash="pNsGGmxB0OdQao2WzlXw0w" />
-          <AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="9cKo3Ih/dVXg0EjRkS7NyA" />
-          <AcmeProjectActionInfo Action="File" Source="examples/driver_examples.c" IsConfig="false" Hash="NAOIehpMqYEt9b2+WS7H5A" />
+          <AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="OUxqgieZ3yprCQMwX7dCUw" />
+          <AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="hKDzztU7boK3vG5tv6CbdQ" />
+          <AcmeProjectActionInfo Action="File" Source="atmel_start_pins.h" IsConfig="false" Hash="HkMWJ7XbNEqZ/ndrVHgYXQ" />
+          <AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="U8tDDopMoUk/nawNSg9Vfw" />
+          <AcmeProjectActionInfo Action="File" Source="examples/driver_examples.c" IsConfig="false" Hash="Us2SD8XKf4isA4dLgGu+Mw" />
          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_usart_sync.h" IsConfig="false" Hash="ZzIGSRyjZuxRzFAtNNt7sw" />
          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_missing_features.h" IsConfig="false" Hash="XsAvpgfutzkw0Y5SydYFaw" />
          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_reset.h" IsConfig="false" Hash="WwLFRlBtuZ/qnD1JuDKnRQ" />
@@ -173,7 +173,7 @@
          <AcmeProjectActionInfo Action="File" Source="hpl/cmcc/hpl_cmcc.c" IsConfig="false" Hash="xrdKSj3ppVwQWgZ3zrlaRg" />
          <AcmeProjectActionInfo Action="File" Source="hpl/core/hpl_core_m4.c" IsConfig="false" Hash="VG4QALndju794J3HSKhsEQ" />
          <AcmeProjectActionInfo Action="File" Source="hpl/core/hpl_core_port.h" IsConfig="false" Hash="RXrDMMracCeflR1F9jWiGg" />
-          <AcmeProjectActionInfo Action="File" Source="hpl/core/hpl_init.c" IsConfig="false" Hash="/W7xK3rVKLxPEwN+aiJq8Q" />
+          <AcmeProjectActionInfo Action="File" Source="hpl/core/hpl_init.c" IsConfig="false" Hash="HyXCJRfb4vfXmyMmlE0xcg" />
          <AcmeProjectActionInfo Action="File" Source="hpl/dmac/hpl_dmac.c" IsConfig="false" Hash="hfo1VP6av1KthYmILu3PCg" />
          <AcmeProjectActionInfo Action="File" Source="hpl/evsys/hpl_evsys.c" IsConfig="false" Hash="YFXyIZne7hxDvOF/5YjFTg" />
          <AcmeProjectActionInfo Action="File" Source="hpl/gclk/hpl_gclk.c" IsConfig="false" Hash="5XO/19EedZQ0lq6yB8UTWQ" />
@@ -187,23 +187,23 @@
          <AcmeProjectActionInfo Action="File" Source="hpl/qspi/hpl_qspi.c" IsConfig="false" Hash="kcTOrixin2H2Rt8x9WBNGQ" />
          <AcmeProjectActionInfo Action="File" Source="hpl/ramecc/hpl_ramecc.c" IsConfig="false" Hash="pMdmwVWBg16VG8HOwA3DPw" />
          <AcmeProjectActionInfo Action="File" Source="hpl/sercom/hpl_sercom.c" IsConfig="false" Hash="hcMq5dgdlyb9xXr1YOQnMQ" />
-          <AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.c" IsConfig="false" Hash="h3lF0y7cJM1yyFbWGx7QkQ" />
-          <AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.h" IsConfig="false" Hash="Gzd12xGkTZwkQmCYoTHN6Q" />
+          <AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.c" IsConfig="false" Hash="WBNEJquEzGno+LWdm1O78g" />
+          <AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.h" IsConfig="false" Hash="NziV6LfmD5tWWVxq/41FRA" />
          <AcmeProjectActionInfo Action="File" Source="stdio_start.c" IsConfig="false" Hash="WtwT7ld+0j4cPDj52v3y1A" />
          <AcmeProjectActionInfo Action="File" Source="stdio_start.h" IsConfig="false" Hash="5j2k69zdoQpbzluEyr/rHQ" />
          <AcmeProjectActionInfo Action="File" Source="atmel_start.h" IsConfig="false" Hash="TNU9VszFRFbDuMJ3vToUzg" />
          <AcmeProjectActionInfo Action="File" Source="atmel_start.c" IsConfig="false" Hash="lom1/YOY9m/TDACgnyb3yA" />
          <AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="nSlPPTDdCwyMdzM7qvqVRQ" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="FBwzaeWRR0NEBkjPjrWnqA" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="qFfXbIiu7Skw/l5fYsEt7Q" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="oV+Eeegy2AFPQj9NYqkwTg" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="iaRvD0C0dCTuR2N0zWUDjg" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
          <AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" />
          <AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="uzEpFoaBTLlpyWknL/fmxg" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="CNa1FBn8+CXUBqimcvdq2w" />
          <AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="5iQ/eeupKkHFkYA/g43bXQ" />
          <AcmeProjectActionInfo Action="File" Source="config/hpl_qspi_config.h" IsConfig="true" Hash="+GkCXfQc+hl3IqkWXgjL7A" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="gJ8Gplj+AF/VaB/y7//74w" />
-          <AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="9F6jT6g2yhmqyb5sOdX/8w" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="Zp4Hpseq6iLlDfpu9Sz3Yw" />
+          <AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="xR/UoLBH1WlmT8Yb6KJwgg" />
          <AcmeProjectActionInfo Action="File" Source="config/stdio_redirect_config.h" IsConfig="true" Hash="CKmkBk12sfr7mb+HRQBuzg" />
        </AcmeActionInfos>
        <NonsecureFilesInfo />
@@ -502,10 +502,16 @@
    <Compile Include="driver_init.h">
      <SubType>compile</SubType>
    </Compile>
-    <Compile Include="ethercat\ethercat_qspi.c">
+    <Compile Include="ethercat\communication.h">
      <SubType>compile</SubType>
    </Compile>
-    <Compile Include="ethercat\ethercat_qspi.h">
+    <Compile Include="ethercat\ethercat_e54.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="ethercat\ethercat_e54.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="ethercat\ethercat_slave_def.h">
      <SubType>compile</SubType>
    </Compile>
    <Compile Include="examples\driver_examples.c">
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start_pins.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start_pins.h
@@ -31,8 +31,12 @@
 #define PA09 GPIO(GPIO_PORTA, 9)
 #define PA10 GPIO(GPIO_PORTA, 10)
 #define PA11 GPIO(GPIO_PORTA, 11)
+#define ECAT_SPI_CS_PIN GPIO(GPIO_PORTB, 0)
+#define PB01 GPIO(GPIO_PORTB, 1)
 #define PB10 GPIO(GPIO_PORTB, 10)
 #define PB11 GPIO(GPIO_PORTB, 11)
+#define PB16 GPIO(GPIO_PORTB, 16)
+#define PB17 GPIO(GPIO_PORTB, 17)
 #define PB24 GPIO(GPIO_PORTB, 24)
 #define PB25 GPIO(GPIO_PORTB, 25)
 #define PB26 GPIO(GPIO_PORTB, 26)
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c
@@ -17,6 +17,8 @@ struct usart_sync_descriptor TARGET_IO;

 struct spi_m_dma_descriptor SPI_0;

+struct spi_m_dma_descriptor SPI_1;
+
 void EVENT_SYSTEM_0_init(void)
 {
 	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
@@ -329,6 +331,62 @@ void SPI_0_init(void)
 	SPI_0_PORT_init();
 }

+void SPI_1_PORT_init(void)
+{
+
+	gpio_set_pin_level(PB16,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(PB16, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(PB16, PINMUX_PB16C_SERCOM5_PAD0);
+
+	gpio_set_pin_level(PB17,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(PB17, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(PB17, PINMUX_PB17C_SERCOM5_PAD1);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(PB01, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(PB01,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(PB01, PINMUX_PB01D_SERCOM5_PAD3);
+}
+
+void SPI_1_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_CORE, CONF_GCLK_SERCOM5_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_SLOW, CONF_GCLK_SERCOM5_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBDMASK_SERCOM5_bit(MCLK);
+}
+
+void SPI_1_init(void)
+{
+	SPI_1_CLOCK_init();
+	spi_m_dma_init(&SPI_1, SERCOM5);
+	SPI_1_PORT_init();
+}
+
 void TIMER_0_CLOCK_init(void)
 {
 	hri_mclk_set_APBAMASK_TC0_bit(MCLK);
@@ -337,10 +395,30 @@ void TIMER_0_CLOCK_init(void)
 	hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
 }

+void TC_ECAT_CLOCK_init(void)
+{
+	hri_mclk_set_APBDMASK_TC7_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TC7_GCLK_ID, CONF_GCLK_TC7_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
 void system_init(void)
 {
 	init_mcu();

+	// GPIO on PB00
+
+	gpio_set_pin_level(ECAT_SPI_CS_PIN,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(ECAT_SPI_CS_PIN, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(ECAT_SPI_CS_PIN, GPIO_PIN_FUNCTION_OFF);
+
 	// GPIO on PB28

 	gpio_set_pin_level(SPI_CS,
@@ -363,7 +441,13 @@ void system_init(void)

 	SPI_0_init();

+	SPI_1_init();
+
 	TIMER_0_CLOCK_init();

 	TIMER_0_init();
+
+	TC_ECAT_CLOCK_init();
+
+	TC_ECAT_init();
 }
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.h
@@ -28,6 +28,9 @@ extern "C" {
 #include <hal_usart_sync.h>

 #include <hal_spi_m_dma.h>
+
+#include <hal_spi_m_dma.h>
+#include <tc_lite.h>
 #include <tc_lite.h>

 extern struct qspi_sync_descriptor QUAD_SPI_0;
@@ -36,6 +39,8 @@ extern struct usart_sync_descriptor TARGET_IO;

 extern struct spi_m_dma_descriptor SPI_0;

+extern struct spi_m_dma_descriptor SPI_1;
+
 void QUAD_SPI_0_PORT_init(void);
 void QUAD_SPI_0_CLOCK_init(void);
 void QUAD_SPI_0_init(void);
@@ -48,10 +53,18 @@ void SPI_0_PORT_init(void);
 void SPI_0_CLOCK_init(void);
 void SPI_0_init(void);

+void SPI_1_PORT_init(void);
+void SPI_1_CLOCK_init(void);
+void SPI_1_init(void);
+
 void TIMER_0_CLOCK_init(void);

 int8_t TIMER_0_init(void);

+void TC_ECAT_CLOCK_init(void);
+
+int8_t TC_ECAT_init(void);
+
 /**
 * \brief Perform system initialization, initialize pins and clocks for
 * peripherals
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/communication.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/communication.h
@@ -0,0 +1,95 @@
+/*
+ * communication.h
+ *
+ * Created: 10/03/2021 13:07:51
+ *  Author: Nick-XMG
+ */ 
+
+
+#ifndef COMMUNICATION_H_
+#define COMMUNICATION_H_
+
+#include "ethercat_e54.h"
+
+//Write To Ecat Total Bytes (38 bytes)
+//write (2 Bytes)
+volatile uint8_t  *status				=&ram_buffer[ram_wr_start];
+volatile uint8_t  *state				=(((uint8_t *)&ram_buffer[ram_wr_start])+1);
+//Joint (10 Bytes)
+volatile int16_t  *joint_rel_position	=&ram_buffer[ram_wr_start+1];
+volatile int16_t  *joint_revolution		=&ram_buffer[ram_wr_start+2];
+volatile int16_t  *joint_abs_position	=&ram_buffer[ram_wr_start+3];
+volatile int16_t  *joint_speed			=&ram_buffer[ram_wr_start+4];
+volatile int16_t  *joint_torque			=&ram_buffer[ram_wr_start+5];
+// Motor (20+1+1+4) = 26
+volatile int16_t  *motor_rel_revolutions=&ram_buffer[ram_wr_start+6];
+volatile int16_t  *motor_rel_position	=&ram_buffer[ram_wr_start+7];
+volatile int16_t  *motor_abs_position	=&ram_buffer[ram_wr_start+8];
+volatile int16_t  *motor_dutyCycle		=&ram_buffer[ram_wr_start+9];
+volatile int16_t  *motor_speed			=&ram_buffer[ram_wr_start+10];
+volatile int16_t  *motor_torque			=&ram_buffer[ram_wr_start+11];
+volatile int16_t  *motor_currentPHA		=&ram_buffer[ram_wr_start+12]; 
+volatile int16_t  *motor_currentPHB		=&ram_buffer[ram_wr_start+13]; 
+volatile int16_t  *motor_currentPHC		=&ram_buffer[ram_wr_start+14]; 
+volatile int16_t  *motor_currentBUS		=&ram_buffer[ram_wr_start+15]; 
+volatile uint8_t  *hall_state			=&ram_buffer[ram_wr_start+16];
+volatile uint8_t  *Spare_byte1			=(((uint8_t *)&ram_buffer[ram_wr_start+16])+1);
+volatile int16_t  *Spare_1				=&ram_buffer[ram_wr_start+17];
+volatile int16_t  *Spare_2				=&ram_buffer[ram_wr_start+18];
+
+//Read From Ecat Total (35 Bytes)
+// (1 Byte)
+volatile uint8_t *control_mode			=&ram_buffer[ram_rd_start];
+volatile uint8_t *control_set			=(((uint8_t *)&ram_buffer[ram_rd_start])+1);
+// (34 Byte)
+volatile int16_t *desired_position		=&ram_buffer[ram_rd_start+1];
+volatile int16_t *desired_speed			=&ram_buffer[ram_rd_start+2];
+volatile int16_t *desired_torque		=&ram_buffer[ram_rd_start+3];
+volatile int16_t *i_kp					=&ram_buffer[ram_rd_start+4];
+volatile int16_t *i_ki					=&ram_buffer[ram_rd_start+5];
+volatile int16_t *v_kp					=&ram_buffer[ram_rd_start+6];
+volatile int16_t *v_kd					=&ram_buffer[ram_rd_start+7];
+volatile int16_t *p_kp					=&ram_buffer[ram_rd_start+8];
+volatile int16_t *p_ki					=&ram_buffer[ram_rd_start+9];
+volatile uint16_t *ReductionRatio		=&ram_buffer[ram_rd_start+10];
+volatile int16_t *max_torque			=&ram_buffer[ram_rd_start+11];
+volatile int16_t *max_current			=&ram_buffer[ram_rd_start+12];
+volatile int16_t *max_velocity			=&ram_buffer[ram_rd_start+13];
+volatile int16_t *spare1				=&ram_buffer[ram_rd_start+14];
+volatile int16_t *spare2				=&ram_buffer[ram_rd_start+15];
+volatile int16_t *spare3				=&ram_buffer[ram_rd_start+16];
+volatile int16_t *spare4				=&ram_buffer[ram_rd_start+17];
+
+void comms_check(void)
+{
+	*status					= 1;
+	*state					= 0;
+	*joint_rel_position		= 3;
+	*joint_revolution	    = 4;
+	*joint_abs_position		= 5;
+	*joint_speed			= 6;
+	*joint_torque			= 7;
+	*motor_rel_revolutions	= 8;
+	*motor_rel_position		= 9;
+	*motor_abs_position		= 10;
+	*motor_dutyCycle		= 11;
+	*motor_speed			= 12;
+	*motor_torque			= 13;
+	*motor_currentPHA		= 14;
+	*motor_currentPHB		= 15;
+	*motor_currentPHC		= 16;
+	*motor_currentBUS		= 17;
+	*hall_state				= 18;
+	*Spare_byte1			= 19;
+	*Spare_1				= 20;
+	*Spare_2				= 21;
+}
+
+void clear_comms_buffer(void)
+{
+	memset(ram_buffer, 0, ram_rd_start);
+}
+
+
+
+#endif /* COMMUNICATION_H_ */
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/ethercat_e54.c
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/ethercat_e54.c
@@ -0,0 +1,223 @@
+/*
+ * ethercat_e54.c
+ *
+ * Created: 02/03/2021 10:49:41
+ *  Author: Nick-XMG
+ */ 
+
+// ----------------------------------------------------------------------
+// Header Files
+// ----------------------------------------------------------------------
+#include "atmel_start.h"
+#include "driver_init.h"
+
+#include "ethercat_e54.h"
+#include "ethercat_slave_def.h"
+#include <string.h>
+
+
+extern void One_ms_cycle_callback(void)
+{
+	tx_ethercat = true;
+	if(tx_ethercat_done){
+		volatile int i=0;
+		//tic_port(DEBUG_3_PORT);
+		//toc_port(DEBUG_3_PORT);
+		
+		//memcpy();
+		memcpy(&ram_buffer[ram_real_wr_start], &ram_buffer[ram_wr_start], ram_rd_start);
+		
+		//for (i=0;i<ram_rd_start;i++){
+			//ram_buffer[ram_real_wr_start+i] = ram_buffer[ram_wr_start+i];
+		//}
+		//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_rx.channel_id);
+		//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
+		//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_tx.channel_id);
+		//spi_m_dma_transfer(&SPI_0, )		
+		//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[1], DMAC_CHCTRLB_CMD_RESUME_Val);	//RX Channel	
+		//_dma_enable_transaction(1,true);
+		
+		gpio_set_pin_level(ECAT_SPI_CS_PIN, false);  // SPI_Slave Select LOW
+		DMAC->Channel[0].CHCTRLB.reg = 0x2; // Resume		
+		//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
+		/*hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[0], DMAC_CHCTRLB_CMD_RESUME_Val)*/;	//TX Channel	
+		
+		DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
+		tx_ethercat_done = false;
+	}
+	else {
+		
+		gpio_set_pin_level(ECAT_SPI_CS_PIN, true);			// SPI_Slave Select HIGH
+		tx_ethercat_done = false;
+		
+		//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_rx.channel_id);
+		//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
+		//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_tx.channel_id);
+		//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[1], DMAC_CHCTRLB_CMD_RESUME_Val);	//RX Channel
+		gpio_set_pin_level(ECAT_SPI_CS_PIN, false); // SPI_Slave Select LOW
+		_dma_enable_transaction(0,false);
+		//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
+		//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[0], DMAC_CHCTRLB_CMD_RESUME_Val);	//TX Channel
+		_dma_enable_transaction(1,false);
+		tx_ethercat_done = false;
+	}
+	
+	//toc_port(DEBUG_3_PORT);
+}
+
+// ----------------------------------------------------------------------
+// Callbacks
+// ----------------------------------------------------------------------
+
+static void transfer_error(struct _dma_resource *resource)
+{
+	uint8_t error = 1;
+	//	spi_select_slave(&spi_master_instance, &slave, false);
+	//DMAC->CHID.reg = resource->channel_id;
+	//DMAC->CHCTRLB.bit.CMD = 0x02;
+	//DMAC->CHINTFLAG.bit.SUSP = 1;
+	//responde_spi_master = true;
+	//com_state = com_error;
+}
+
+static void LAN9252_rx_done(struct _dma_resource *resource)
+{
+	gpio_set_pin_level(ECAT_SPI_CS_PIN, true);
+	
+	//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_rx.channel_id);
+	//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
+	//DMAC->CHID.reg = DMAC_CHID_ID(dma_LAN9252_tx.channel_id);
+	//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[1], DMAC_CHCTRLB_CMD_RESUME_Val);	//RX Channel
+	gpio_set_pin_level(ECAT_SPI_CS_PIN, false);
+	//_dma_enable_transaction(0,false);
+	DMAC->Channel[0].CHCTRLB.reg = 0x2; // Resume
+	
+	//DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
+	//_dma_enable_transaction(1,false); //TX Channel
+	DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
+	//hri_dmacchannel_write_CHCTRLB_CMD_bf(&DMAC->Channel[0], DMAC_CHCTRLB_CMD_RESUME_Val);	//TX Channel
+	tx_ethercat_done = false;
+	//responde_spi_master = true;
+}
+
+
+static void LAN9252_rx_susp(struct _dma_resource *resource)
+{
+	gpio_set_pin_level(ECAT_SPI_CS_PIN, true);
+	
+	//volatile uint32_t *pointer = ((DMAC->WRBADDR.reg)+0x10*resource->channel_id+12);
+	volatile uint32_t *pointer = ((DMAC->WRBADDR.reg)+12);
+
+	if (*pointer != &spi_rx_write_fifo_dma_descriptor){
+		//_dma_enable_transaction(0,false);
+		DMAC->Channel[0].CHCTRLB.reg = 0x2; // Resume
+		gpio_set_pin_level(ECAT_SPI_CS_PIN, false);
+		//_dma_enable_transaction(1,false); //TX Channel
+		DMAC->Channel[1].CHCTRLB.reg = 0x2; // Resume
+		tx_ethercat_done = false;
+	}
+	else{
+		tx_ethercat_done = true;
+	}
+
+
+}
+
+void configure_ethercat_dma_descriptors(void)
+{
+	TC_ECAT_init();
+	
+	// ----------------------------------------------------------------------
+	// DMAC Descriptors
+	// ----------------------------------------------------------------------
+	
+	// Args = dma_transfer_descriptor_type type, *descriptor, start, lenght, next_descriptor, block_action
+		
+	//abort actual_fifo
+	//setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_abort_fifo_dma_descriptor,abort_fifo_start,abort_fifo_length,&spi_config_fifo_dma_descriptor,&spi_LAN9252_instance,DMA_BLOCK_ACTION_SUSPEND);
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX, &spi_abort_fifo_dma_descriptor, abort_fifo_start, abort_fifo_length, &spi_clear_rd_fifo_dma_descriptor, DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);			//DMA_BLOCK_ACTION_SUSPEND
+	
+	
+	//clear initial read data from LAN9252 to avoid errors.
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_clear_rd_fifo_dma_descriptor,wr_pdram_start,wr_pdram_lenght+2*write_var_num,&spi_write_cl_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);	//DMA_BLOCK_ACTION_SUSPEND
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_write_cl_fifo_dma_descriptor,cl_pdram_start,cl_pdram_lenght,&spi_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);						//DMA_BLOCK_ACTION_SUSPEND
+	
+	
+	// write fifo registers
+
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_write_fifo_dma_descriptor,wr_pdram_start,wr_pdram_lenght,&spi_write2ram_dma_descriptor,DMAC_BTCTRL_BLOCKACT_NOACT_Val);							//DMA_BLOCK_ACTION_NOACT
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_write2ram_dma_descriptor,&ram_buffer[ram_real_wr_start],2*write_var_num,&spi_config_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);		//DMA_BLOCK_ACTION_SUSPEND
+	
+	// write fifo configuration
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_config_fifo_dma_descriptor,cf_pdram_start,cf_pdram_lenght,&spi_read_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);						//DMA_BLOCK_ACTION_SUSPEND		
+	
+	// read fifo registers
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX,&spi_read_fifo_dma_descriptor,rd_pdram_start,rd_pdram_lenght,&spi_read2ram_dma_descriptor,DMAC_BTCTRL_BLOCKACT_NOACT_Val);								//DMA_BLOCK_ACTION_NOACT
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_TX_DUMMY,&spi_read2ram_dma_descriptor,0,2*read_var_num,&spi_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);									//DMA_BLOCK_ACTION_SUSPEND
+	
+	//// RX DESCRIPTORS
+	
+	// abort fifo
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_abort_fifo_dma_descriptor,0,cf_pdram_lenght,&spi_rx_clear_rd_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);						//DMA_BLOCK_ACTION_SUSPEND
+	
+	//clear initial read data from LAN9252 to avoid errors.
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_clear_rd_fifo_dma_descriptor,0,wr_pdram_lenght+2*write_var_num,&spi_rx_write_cl_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);	//DMA_BLOCK_ACTION_SUSPEND
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_write_cl_fifo_dma_descriptor,0,cl_pdram_lenght,&spi_rx_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);						//DMA_BLOCK_ACTION_SUSPEND
+	
+	// write fifo registers , dummy receive
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_write_fifo_dma_descriptor,0,spi_head+2*write_var_num,&spi_rx_config_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);				//DMA_BLOCK_ACTION_SUSPEND
+	
+	// write fifo config. dummy receive
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_config_fifo_dma_descriptor,0,cf_pdram_lenght,&spi_rx_read_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);							//DMA_BLOCK_ACTION_SUSPEND
+	
+	// read fifo registers
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,&spi_rx_read_fifo_dma_descriptor,0,spi_head,&spi_rx_read2ram_dma_descriptor,DMAC_BTCTRL_BLOCKACT_NOACT_Val);										//DMA_BLOCK_ACTION_NOACT
+	setup_transfer_descriptor(DMA_TRANSFER_DESCRIPTOR_RX,&spi_rx_read2ram_dma_descriptor,&ram_buffer[ram_rd_start],2*read_var_num,&spi_rx_write_fifo_dma_descriptor,DMAC_BTCTRL_BLOCKACT_SUSPEND_Val);			//DMA_BLOCK_ACTION_SUSPEND
+
+	// ----------------------------------------------------------------------
+	// Register Callbacks
+	// ---------------------------------------------------------------------- 
+	//spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_RX_DONE, LAN9252_rx_done);
+	//spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_ERROR, transfer_error);
+	spi_m_dma_register_callback(&SPI_1, SPI_M_DMA_CB_SUSPEND, LAN9252_rx_susp);
+	
+	// ----------------------------------------------------------------------
+	// Link Descriptors
+	// ----------------------------------------------------------------------
+	_dma_set_descriptor(0, spi_rx_abort_fifo_dma_descriptor);
+	_dma_set_descriptor(1, spi_abort_fifo_dma_descriptor);
+	
+
+	// ----------------------------------------------------------------------
+	// Enable SPI DMA
+	// ----------------------------------------------------------------------
+	spi_m_dma_enable(&SPI_1);
+	//	_dma_enable_transaction(&DMAC->Channel[1],true);
+	// 	_dma_enable_transaction(&DMAC->Channel[0],true);
+	//DMAC->Channel[0].CHCTRLA.bit.ENABLE = true;
+	//DMAC->Channel[1].CHCTRLA.bit.ENABLE = true;
+	
+}
+
+static void setup_transfer_descriptor(enum dma_transfer_descriptor_type type, DmacDescriptor *descriptor, const uint32_t start, 
+										const uint32_t lenght, const uint32_t next_descriptor, uint16_t block_action)
+{
+		
+	/*** DMA RX Descriptor Initialization step by step
+	 *** 1- Validate the Descriptor
+	 *** 2- Event Output = DMA_EVENT_OUTPUT_BEAT
+	 *** 3- block_action = DMA_BLOCK_ACTION_NOACT;
+	 *** 4- beat_size = DMA_BEAT_SIZE_BYTE;
+	 *** 5- src_increment_enable = false;
+	 *** 6- dst_increment_enable = false;
+	 *** 7- step_selection = DMA_STEPSEL_DST;
+	 *** 8- step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
+	 *** 9- block_transfer_count;
+	 *** 10- source_address = (uint32_t)NULL;
+	 *** 11- destination_address = (uint32_t)NULL;
+	 *** 12- next_descriptor_address = 0;
+	 ***/
+		
+	hri_dmacdescriptor_set_BTCTRL_VALID_bit(descriptor);										// 1.Validate the Descriptor
+	hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(descriptor, DMAC_BTCTRL_EVOSEL_BURST_Val);		// 2. Define mentions 0x3 as Burst, but 0x3 = BEAT (Event strobe when beat transfer complete)
+	hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(descriptor, block_action);						// 3. block_action
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/ethercat_e54.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/ethercat_e54.h
@@ -0,0 +1,196 @@
+/*
+ * ethercat_e54.h
+ *
+ * Created: 02/03/2021 10:49:33
+ *  Author: Nick-XMG
+ */ 
+
+#ifndef ETHERCAT_E54_H_
+#define ETHERCAT_E54_H_
+
+// ----------------------------------------------------------------------
+// Header Files
+// ----------------------------------------------------------------------
+// ----------------------------------------------------------------------
+// Defines
+// ----------------------------------------------------------------------
+
+
+// ----------------------------------------------------------------------
+// Types
+// ----------------------------------------------------------------------
+
+enum dma_transfer_descriptor_type {
+	DMA_TRANSFER_DESCRIPTOR_TX,
+	DMA_TRANSFER_DESCRIPTOR_RX,
+	DMA_TRANSFER_DESCRIPTOR_TX_DUMMY,
+	DMA_TRANSFER_DESCRIPTOR_RX_DUMMY,
+};
+
+
+// ----------------------------------------------------------------------
+// Register Addresses
+// ----------------------------------------------------------------------
+#define read_var_num 32U  //to change to 16bits need to change ecat spi lenght.
+#define write_var_num 32U //max 20
+// #define read_var_num 2  //to change to 16bits need to change ecat spi lenght.
+// #define write_var_num 2 //max 20
+
+#define ram_wr_start 0U
+#define ram_rd_start write_var_num //write_var_num
+#define ram_real_wr_start  ram_rd_start + read_var_num
+
+#define SPI_READ   0x03U
+#define SPI_WRITE  0x02U
+#define SPI_INC    0x40U
+#define SPI_DEC	   0x80U
+#define TEST_VAL   0x87654321U
+#define CSR_BUSY   0x80000000U
+#define ADDR_BYTES 2
+#define CSR_READ   1<<30
+#define CSR_WRITE  0<<30
+#define CSR_SIZE   4<<16
+#define CSR_HW_RD  1<<27
+
+#define ECAT_PRAM_RD_DATA		0x0000U
+#define ECAT_PRAM_WR_DATA		0x2000U
+#define ID_REV					0x5000U
+#define IRQ_CFG					0x5400U
+#define INT_STS					0x5800U
+#define INT_EN					0x5C00U
+#define BYTE_TEST				0x6400U
+#define HW_CFG					0x7400U
+#define PMT_CTRL				0x8400U
+#define GPT_CFG					0x8C00U
+#define GPT_CNT					0x9000U
+#define FREE_RUN				0x9C00U
+#define RESET_CTL				0xF801U
+#define ECAT_CSR_DATA			0x0003U
+#define ECAT_CSR_CMD			0x0403U
+#define ECAT_PRAM_RD_ADDR_LEN	0x0803U
+#define ECAT_PRAM_RD_CMD		0x0C03U
+#define ECAT_PRAM_WR_ADDR_LEN	0x1003U
+#define ECAT_PRAM_WR_CMD		0x1403U
+
+#define PDRAM_RD_ADDRESS		0x1100U
+#define PDRAM_WR_ADDRESS		0x1800U
+
+#define PDRAM_RD_LENGTH			2*read_var_num
+#define PDRAM_WR_LENGTH			2*write_var_num
+
+// ----------------------------------------------------------------------
+// SPI 
+// ----------------------------------------------------------------------
+
+#define spi_head 3
+#define hw_tst_length			spi_head +4
+#define by_tst_length			spi_head +4
+#define rd_status_length		spi_head +4*4
+#define abort_fifo_length		spi_head +4*4
+#define cf_pdram_lenght			spi_head +4*4
+#define rd_pdram_lenght			spi_head
+#define wr_pdram_lenght			spi_head
+#define cl_pdram_lenght			spi_head +4*2
+
+#define rd_fifo_lenght
+#define wr_fifo_lenght
+
+
+// ----------------------------------------------------------------------
+// Flags
+// ----------------------------------------------------------------------
+
+volatile bool tx_ethercat;
+volatile bool tx_ethercat_done;
+
+// ----------------------------------------------------------------------
+// DMA descriptors
+// ----------------------------------------------------------------------
+COMPILER_ALIGNED(16)
+DmacDescriptor spi_config_fifo_dma_descriptor;
+DmacDescriptor spi_read_fifo_dma_descriptor;
+DmacDescriptor spi_write_fifo_dma_descriptor;
+DmacDescriptor spi_read2ram_dma_descriptor;
+DmacDescriptor spi_write2ram_dma_descriptor;
+DmacDescriptor spi_abort_fifo_dma_descriptor;
+DmacDescriptor spi_clear_rd_fifo_dma_descriptor;
+DmacDescriptor spi_write_cl_fifo_dma_descriptor;
+
+DmacDescriptor spi_rx_config_fifo_dma_descriptor;
+DmacDescriptor spi_rx_read_fifo_dma_descriptor;
+DmacDescriptor spi_rx_write_fifo_dma_descriptor;
+DmacDescriptor spi_rx_read2ram_dma_descriptor;
+DmacDescriptor spi_rx_abort_fifo_dma_descriptor;
+DmacDescriptor spi_rx_clear_rd_fifo_dma_descriptor;
+DmacDescriptor spi_rx_write_cl_fifo_dma_descriptor;
+
+// ----------------------------------------------------------------------
+// Global Variables
+// ----------------------------------------------------------------------
+volatile uint16_t ram_buffer[(read_var_num+2*write_var_num)];
+//volatile uint16_t ram_buffer[(read_var_num+2*write_var_num)] = {1,2,3,4,5,6,7,8,  9,10,11,12,13,14,15,16,  17,18,19,20,21,22,23,23, 24,25,26,27,28,29,30,31, 32,33,34,35,36,37,38,39, 40,41,42,43,44,45,46,47,
+																//1,2,3,4,5,6,7,8,  9,10,11,12,13,14,15,16,  17,18,19,20,21,22,23,23, 24,25,26,27,28,29,30,31, 32,33,34,35,36,37,38,39, 40,41,42,43,44,45,46,47};
+//volatile uint16_t ram_buffer[(read_var_num+2*write_var_num)] = {1,2,3,4,5,6,7,8,  9,10,11,12,13,14,15,16,  17,18,19,20,21,22,23,24 };
+																//1,2,3,4,5,6,7,8,  9,10,11,12,13,14,15,16,  17,18,19,20,21,22,23,23, 24,25,26,27,28,29,30,31, 32,33,34,35,36,37,38,39, 40,41,42,43,44,45,46,47};
+
+volatile  uint8_t spi_rx_buffer[30];							
+
+static uint8_t spi_tx_buffer[110] = {
+	SPI_READ,HW_CFG,HW_CFG>>8,0xFF,0xFF,0xFF,0xFF,
+	SPI_READ,BYTE_TEST,BYTE_TEST>>8,0xFF,0xFF,0xFF,0xFF,
+	SPI_WRITE,ECAT_PRAM_RD_ADDR_LEN | SPI_INC, (ECAT_PRAM_RD_ADDR_LEN | SPI_INC)>>8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,
+	SPI_READ, ECAT_PRAM_RD_ADDR_LEN | SPI_INC, (ECAT_PRAM_RD_ADDR_LEN | SPI_INC)>>8,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+	SPI_WRITE,ECAT_PRAM_RD_ADDR_LEN | SPI_INC, (ECAT_PRAM_RD_ADDR_LEN | SPI_INC)>>8,PDRAM_RD_ADDRESS,(PDRAM_RD_ADDRESS>>8),PDRAM_RD_LENGTH,PDRAM_RD_LENGTH>>8,0x00,0x00,0x00,CSR_BUSY>>24,PDRAM_WR_ADDRESS,PDRAM_WR_ADDRESS>>8,PDRAM_WR_LENGTH,PDRAM_WR_LENGTH>>8,0x00,0x00,0x00,CSR_BUSY>>24,
+	SPI_READ,ECAT_PRAM_RD_DATA,(ECAT_PRAM_RD_DATA)>>8, //modification for FIFO FIXED
+	SPI_WRITE,ECAT_PRAM_WR_DATA,(ECAT_PRAM_WR_DATA)>>8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	SPI_WRITE,ECAT_PRAM_WR_ADDR_LEN | SPI_INC, (ECAT_PRAM_WR_ADDR_LEN | SPI_INC)>>8,PDRAM_RD_ADDRESS,(PDRAM_RD_ADDRESS>>8),PDRAM_RD_LENGTH,PDRAM_RD_LENGTH>>8,0x00,0x00,0x00,CSR_BUSY>>24};
+
+
+const static uint32_t dummy_register = &spi_tx_buffer[4];
+const static uint32_t hw_tst_start =   &spi_tx_buffer[0];
+const static uint32_t by_tst_start =   &spi_tx_buffer[0+hw_tst_length];
+const static uint32_t abort_fifo_start=&spi_tx_buffer[0+hw_tst_length+by_tst_length];
+const static uint32_t rd_status_start= &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length];
+const static uint32_t cf_pdram_start = &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length+rd_status_length];
+const static uint32_t rd_pdram_start = &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length+rd_status_length+cf_pdram_lenght];
+const static uint32_t wr_pdram_start = &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length+rd_status_length+cf_pdram_lenght+rd_pdram_lenght];
+volatile static uint32_t cl_pdram_start = &spi_tx_buffer[0+hw_tst_length+by_tst_length+abort_fifo_length+rd_status_length+cf_pdram_lenght+rd_pdram_lenght+wr_pdram_lenght+write_var_num];
+//
+//
+const static uint32_t *spi_rx_reg   = &spi_rx_buffer[0];
+
+// ----------------------------------------------------------------------
+// 	Driver Instances
+// ----------------------------------------------------------------------
+//static struct timer_task tc_syncro_task;
+#define SYNC_1kHz_MODULE	TC7 
+#define SPI_LAN9252			SERCOM5
+// ----------------------------------------------------------------------
+// 	Callbacks
+// ----------------------------------------------------------------------
+// 	External
+extern void One_ms_cycle_callback(void);
+
+// 	Internal
+static void transfer_error(struct _dma_resource *resource);
+static void LAN9252_rx_done(struct _dma_resource *resource);
+static void LAN9252_rx_susp(struct _dma_resource *resource);
+
+// ----------------------------------------------------------------------
+// 	Interrupt Handlers
+// ----------------------------------------------------------------------
+//extern void TC7_Handler(void);
+
+// ----------------------------------------------------------------------
+// 	functions
+// ----------------------------------------------------------------------
+void ethercat_update(void);
+void config_ethercat_tc(void);
+void config_ethercat_sercom(void);
+void configure_dma_resource(void);
+void configure_ethercat_dma_descriptors(void);
+static void setup_transfer_descriptor(enum dma_transfer_descriptor_type type, DmacDescriptor *descriptor,
+								 const uint32_t start, const uint32_t lenght, const uint32_t next_descriptor, uint16_t block_action);
+	
+
+#endif /* ETHERCAT_E54_H_ */
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/ethercat_slave_def.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/ethercat/ethercat_slave_def.h
@@ -0,0 +1,93 @@
+/*
+ * ethercat_slave_buffer.h
+ *
+ * Created: 10/03/2021 13:10:51
+ *  Author: Nick-XMG
+ */ 
+
+
+#ifndef ETHERCAT_SLAVE_DEF_H_
+#define ETHERCAT_SLAVE_DEF_H_
+
+#include "ethercat_e54.h"
+
+//Write To Ecat Total Bytes (38 bytes)
+//write (2 Bytes)
+static volatile uint8_t  *status				=&ram_buffer[ram_wr_start];
+static volatile uint8_t  *state					=(((uint8_t *)&ram_buffer[ram_wr_start])+1);
+//Joint (10 Bytes)
+static volatile int16_t  *joint_rel_position	=&ram_buffer[ram_wr_start+1];
+static volatile int16_t  *joint_revolution		=&ram_buffer[ram_wr_start+2];
+static volatile int16_t  *joint_abs_position	=&ram_buffer[ram_wr_start+3];
+static volatile int16_t  *joint_speed			=&ram_buffer[ram_wr_start+4];
+static volatile int16_t  *joint_torque			=&ram_buffer[ram_wr_start+5];
+// Motor (24+1+1) = 26
+static volatile int16_t  *motor_rel_revolutions=&ram_buffer[ram_wr_start+6];
+static volatile int16_t  *motor_rel_position	=&ram_buffer[ram_wr_start+7];
+static volatile int16_t  *motor_abs_position	=&ram_buffer[ram_wr_start+8];
+static volatile int16_t  *motor_dutyCycle		=&ram_buffer[ram_wr_start+9];
+static volatile int16_t  *motor_speed			=&ram_buffer[ram_wr_start+10];
+static volatile int16_t  *motor_torque			=&ram_buffer[ram_wr_start+11];
+static volatile int16_t  *motor_currentPHA		=&ram_buffer[ram_wr_start+12]; 
+static volatile int16_t  *motor_currentPHB		=&ram_buffer[ram_wr_start+13]; 
+static volatile int16_t  *motor_currentPHC		=&ram_buffer[ram_wr_start+14]; 
+static volatile int16_t  *motor_currentBUS		=&ram_buffer[ram_wr_start+15]; 
+static volatile uint8_t  *hall_state			=&ram_buffer[ram_wr_start+16];
+static volatile uint8_t  *Spare_byte1			=(((uint8_t *)&ram_buffer[ram_wr_start+16])+1);
+static volatile int16_t  *Spare_1				=&ram_buffer[ram_wr_start+17];
+static volatile int16_t  *Spare_2				=&ram_buffer[ram_wr_start+18];
+
+//Read From Ecat Total (35 Bytes)
+// (1 Byte)
+static volatile uint8_t *control_mode			=&ram_buffer[ram_rd_start];
+static volatile uint8_t *control_set			=(((uint8_t *)&ram_buffer[ram_rd_start])+1);
+// (34 Byte)
+static volatile int16_t *desired_position		=&ram_buffer[ram_rd_start+1];
+static volatile int16_t *desired_speed			=&ram_buffer[ram_rd_start+2];
+static volatile int16_t *desired_torque			=&ram_buffer[ram_rd_start+3];
+static volatile int16_t *i_kp					=&ram_buffer[ram_rd_start+4];
+static volatile int16_t *i_ki					=&ram_buffer[ram_rd_start+5];
+static volatile int16_t *v_kp					=&ram_buffer[ram_rd_start+6];
+static volatile int16_t *v_kd					=&ram_buffer[ram_rd_start+7];
+static volatile int16_t *p_kp					=&ram_buffer[ram_rd_start+8];
+static volatile int16_t *p_ki					=&ram_buffer[ram_rd_start+9];
+static volatile uint16_t *ReductionRatio		=&ram_buffer[ram_rd_start+10];
+static volatile int16_t *max_torque			=&ram_buffer[ram_rd_start+11];
+static volatile int16_t *max_current			=&ram_buffer[ram_rd_start+12];
+static volatile int16_t *max_velocity			=&ram_buffer[ram_rd_start+13];
+static volatile int16_t *spare1				=&ram_buffer[ram_rd_start+14];
+static volatile int16_t *spare2				=&ram_buffer[ram_rd_start+15];
+static volatile int16_t *spare3				=&ram_buffer[ram_rd_start+16];
+static volatile int16_t *spare4				=&ram_buffer[ram_rd_start+17];
+
+inline void comms_check(void)
+{
+	*status					= 1;
+	*state					= 0;
+	*joint_rel_position		= 3;
+	*joint_revolution	    = 4;
+	*joint_abs_position		= 5;
+	*joint_speed			= 6;
+	*joint_torque			= 7;
+	*motor_rel_revolutions	= 8;
+	*motor_rel_position		= 9;
+	*motor_abs_position		= 10;
+	*motor_dutyCycle		= 11;
+	*motor_speed			= 12;
+	*motor_torque			= 13;
+	*motor_currentPHA		= 14;
+	*motor_currentPHB		= 15;
+	*motor_currentPHC		= 16;
+	*motor_currentBUS		= 17;
+	*hall_state				= 18;
+	*Spare_byte1			= 19;
+	*Spare_1				= 20;
+	*Spare_2				= 21;
+}
+
+inline void clear_comms_buffer(void)
+{
+	memset(ram_buffer, 0, ram_rd_start);
+}
+
+#endif /* ETHERCAT_SLAVE_DEF_H_ */
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.c
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.c
@@ -70,3 +70,29 @@ void SPI_0_example(void)
 	spi_m_dma_enable(&SPI_0);
 	io_write(io, example_SPI_0, 12);
 }
+
+/**
+ * Example of using SPI_1 to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
+ */
+
+static uint8_t example_SPI_1[12] = "Hello World!";
+
+static void tx_complete_cb_SPI_1(struct _dma_resource *resource)
+{
+	/* Transfer completed */
+}
+
+void SPI_1_example(void)
+{
+	struct io_descriptor *io;
+	spi_m_dma_get_io_descriptor(&SPI_1, &io);
+
+	spi_m_dma_register_callback(&SPI_1, SPI_M_DMA_CB_TX_DONE, tx_complete_cb_SPI_1);
+	spi_m_dma_enable(&SPI_1);
+	io_write(io, example_SPI_1, 12);
+}
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/examples/driver_examples.h
@@ -18,6 +18,8 @@ void TARGET_IO_example(void);

 void SPI_0_example(void);

+void SPI_1_example(void);
+
 #ifdef __cplusplus
 }
 #endif
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_dma.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_dma.h
@@ -58,7 +58,9 @@ enum spi_m_dma_cb_type {
 	SPI_M_DMA_CB_RX_DONE,
 	/** Callback type for DMA errors */
 	SPI_M_DMA_CB_ERROR,
-	SPI_M_DMA_CB_N
+	SPI_M_DMA_CB_N,
+	SPI_M_DMA_CB_SUSPEND
+	
 };

 /**
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_dma.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_dma.h
@@ -55,7 +55,7 @@ struct _dma_resource;
 /**
 * \brief DMA callback types
 */
-enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB };
+enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB, DMA_SUSPEND_CB };

 /**
 * \brief DMA interrupt callbacks
@@ -63,6 +63,7 @@ enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB };
 struct _dma_callbacks {
 	void (*transfer_done)(struct _dma_resource *resource);
 	void (*error)(struct _dma_resource *resource);
+	void (*suspend)(struct _dma_resource *resource);
 };

 /**
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_dma.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_dma.h
@@ -50,7 +50,8 @@ enum _spi_dma_dev_cb_type {
 	/** Callback type for DMA error. */
 	SPI_DEV_CB_DMA_ERROR,
 	/** Number of callbacks. */
-	SPI_DEV_CB_DMA_N
+	SPI_DEV_CB_DMA_N,
+	SPI_DEV_CB_DMA_SUSPEND
 };

 struct _spi_dma_dev;
@@ -67,6 +68,7 @@ struct _spi_dma_dev_callbacks {
 	_spi_dma_cb_t tx;
 	_spi_dma_cb_t rx;
 	_spi_dma_cb_t error;
+	_spi_dma_cb_t suspend;
 };

 /** SPI driver to support DMA HAL */
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_init.c
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/core/hpl_init.c
@@ -42,10 +42,12 @@
 #include <hal_cache.h>

 /* Referenced GCLKs (out of 0~11), should be initialized firstly
+ * - GCLK 2 for DFLL
+ * - GCLK 1 for FDPLL1
 */
-#define _GCLK_INIT_1ST 0x00000000
+#define _GCLK_INIT_1ST 0x00000006
 /* Not referenced GCLKs, initialized last */
-#define _GCLK_INIT_LAST 0x00000FFF
+#define _GCLK_INIT_LAST 0x00000FF9

 /**
 * \brief Initialize the hardware abstraction layer
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/dmac/hpl_dmac.c
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/dmac/hpl_dmac.c
@@ -49,7 +49,7 @@ DmacDescriptor _write_back_section[DMAC_CH_NUM];
 static struct _dma_resource _resources[DMAC_CH_NUM];

 /* DMAC interrupt handler */
-static void _dmac_handler(void);
+static void _dmac_handler(uint8_t);

 /* This macro DMAC configuration */
 #define DMAC_CHANNEL_CFG(i, n)                                                                                         \
@@ -130,6 +130,8 @@ void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type typ
 		hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, channel, state);
 	} else if (DMA_TRANSFER_ERROR_CB == type) {
 		hri_dmac_write_CHINTEN_TERR_bit(DMAC, channel, state);
+	} else if (DMA_SUSPEND_CB == type) {
+		hri_dmac_write_CHINTEN_SUSP_bit(DMAC, channel, state);
 	}
 }

@@ -194,6 +196,14 @@ int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigg
 	return ERR_NONE;
 }

+// ADDED
+int32_t _dma_set_descriptor(const uint8_t channel, const DmacDescriptor descriptor)
+{
+	_descriptor_section[channel] = descriptor;
+	
+	return ERR_NONE;
+}
+
 int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel)
 {
 	*resource = &_resources[channel];
@@ -210,9 +220,9 @@ int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable)
 /**
 * \internal DMAC interrupt handler
 */
-static void _dmac_handler(void)
+static void _dmac_handler(uint8_t channel)
 {
-	uint8_t               channel      = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk);
+	//uint8_t               channel      = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk);
 	struct _dma_resource *tmp_resource = &_resources[channel];

 	if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) {
@@ -221,6 +231,10 @@ static void _dmac_handler(void)
 	} else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)) {
 		hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel);
 		tmp_resource->dma_cb.transfer_done(tmp_resource);
+	} else if  (hri_dmac_get_INTPEND_SUSP_bit(DMAC)|hri_dmac_get_CHINTEN_SUSP_bit(DMAC,channel)) {	//added
+		hri_dmac_clear_CHINTFLAG_SUSP_bit(DMAC, channel);											//added
+		tmp_resource->dma_cb.suspend(tmp_resource);
+		
 	}
 }
 /**
@@ -228,33 +242,33 @@ static void _dmac_handler(void)
 */
 void DMAC_0_Handler(void)
 {
-	_dmac_handler();
+	_dmac_handler(0);
 }
 /**
 * \brief DMAC interrupt handler
 */
 void DMAC_1_Handler(void)
 {
-	_dmac_handler();
+	_dmac_handler(1);
 }
 /**
 * \brief DMAC interrupt handler
 */
 void DMAC_2_Handler(void)
 {
-	_dmac_handler();
+	_dmac_handler(2);
 }
 /**
 * \brief DMAC interrupt handler
 */
 void DMAC_3_Handler(void)
 {
-	_dmac_handler();
+	_dmac_handler(3);
 }
 /**
 * \brief DMAC interrupt handler
 */
 void DMAC_4_Handler(void)
 {
-	_dmac_handler();
+	_dmac_handler(4);
 }
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/sercom/hpl_sercom.c
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/sercom/hpl_sercom.c
@@ -3223,6 +3223,20 @@ static void _spi_dma_tx_complete(struct _dma_resource *resource)
 	}
 }

+/** ADDED
+ *  \brief Callback for suspend
+ *  \param[in, out] dev Pointer to the DMA resource.
+ */
+
+static void _spi_dma_tx_suspend(struct _dma_resource *resource)
+{
+	struct _spi_m_dma_dev *dev = (struct _spi_m_dma_dev *)resource->back;
+
+	if (dev->callbacks.suspend) {
+		dev->callbacks.suspend(resource);
+	}
+}
+
 /**
 *  \brief Callback for ERROR
 *  \param[in, out] dev Pointer to the DMA resource.
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.c
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.c
@@ -99,3 +99,71 @@ int8_t TIMER_0_init()

 	return 0;
 }
+
+/**
+ * \brief Initialize TC interface
+ */
+int8_t TC_ECAT_init()
+{
+
+	if (!hri_tc_is_syncing(TC7, TC_SYNCBUSY_SWRST)) {
+		if (hri_tc_get_CTRLA_reg(TC7, TC_CTRLA_ENABLE)) {
+			hri_tc_clear_CTRLA_ENABLE_bit(TC7);
+			hri_tc_wait_for_sync(TC7, TC_SYNCBUSY_ENABLE);
+		}
+		hri_tc_write_CTRLA_reg(TC7, TC_CTRLA_SWRST);
+	}
+	hri_tc_wait_for_sync(TC7, TC_SYNCBUSY_SWRST);
+
+	hri_tc_write_CTRLA_reg(TC7,
+	                       0 << TC_CTRLA_CAPTMODE0_Pos       /* Capture mode Channel 0: 0 */
+	                           | 0 << TC_CTRLA_CAPTMODE1_Pos /* Capture mode Channel 1: 0 */
+	                           | 0 << TC_CTRLA_COPEN0_Pos    /* Capture Pin 0 Enable: disabled */
+	                           | 0 << TC_CTRLA_COPEN1_Pos    /* Capture Pin 1 Enable: disabled */
+	                           | 0 << TC_CTRLA_CAPTEN0_Pos   /* Capture Channel 0 Enable: disabled */
+	                           | 0 << TC_CTRLA_CAPTEN1_Pos   /* Capture Channel 1 Enable: disabled */
+	                           | 0 << TC_CTRLA_ALOCK_Pos     /* Auto Lock: disabled */
+	                           | 0 << TC_CTRLA_PRESCSYNC_Pos /* Prescaler and Counter Synchronization: 0 */
+	                           | 0 << TC_CTRLA_ONDEMAND_Pos  /* Clock On Demand: disabled */
+	                           | 0 << TC_CTRLA_RUNSTDBY_Pos  /* Run in Standby: disabled */
+	                           | 2 << TC_CTRLA_PRESCALER_Pos /* Setting: 2 */
+	                           | 0x0 << TC_CTRLA_MODE_Pos);  /* Operating Mode: 0x0 */
+
+	hri_tc_write_CTRLB_reg(TC7,
+	                       0 << TC_CTRLBSET_CMD_Pos           /* Command: 0 */
+	                           | 0 << TC_CTRLBSET_ONESHOT_Pos /* One-Shot: disabled */
+	                           | 0 << TC_CTRLBCLR_LUPD_Pos    /* Setting: disabled */
+	                           | 0 << TC_CTRLBSET_DIR_Pos);   /* Counter Direction: disabled */
+
+	hri_tc_write_WAVE_reg(TC7, 1); /* Waveform Generation Mode: 1 */
+
+	// hri_tc_write_DRVCTRL_reg(TC7,0 << TC_DRVCTRL_INVEN1_Pos /* Output Waveform 1 Invert Enable: disabled */
+	//		 | 0 << TC_DRVCTRL_INVEN0_Pos); /* Output Waveform 0 Invert Enable: disabled */
+
+	// hri_tc_write_DBGCTRL_reg(TC7,0); /* Run in debug: 0 */
+
+	hri_tccount32_write_CC_reg(TC7, 0, 0x7530); /* Compare/Capture Value: 0x7530 */
+
+	// hri_tccount32_write_CC_reg(TC7, 1 ,0x0); /* Compare/Capture Value: 0x0 */
+
+	// hri_tccount32_write_COUNT_reg(TC7,0x0); /* Counter Value: 0x0 */
+
+	hri_tc_write_EVCTRL_reg(
+	    TC7,
+	    1 << TC_EVCTRL_MCEO0_Pos       /* Match or Capture Channel 0 Event Output Enable: enabled */
+	        | 0 << TC_EVCTRL_MCEO1_Pos /* Match or Capture Channel 1 Event Output Enable: disabled */
+	        | 0 << TC_EVCTRL_OVFEO_Pos /* Overflow/Underflow Event Output Enable: disabled */
+	        | 0 << TC_EVCTRL_TCEI_Pos  /* TC Event Input: disabled */
+	        | 0 << TC_EVCTRL_TCINV_Pos /* TC Inverted Event Input: disabled */
+	        | 0);                      /* Event Action: 0 */
+
+	hri_tc_write_INTEN_reg(TC7,
+	                       0 << TC_INTENSET_MC0_Pos         /* Match or Capture Channel 0 Interrupt Enable: disabled */
+	                           | 0 << TC_INTENSET_MC1_Pos   /* Match or Capture Channel 1 Interrupt Enable: disabled */
+	                           | 0 << TC_INTENSET_ERR_Pos   /* Error Interrupt Enable: disabled */
+	                           | 1 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: enabled */
+
+	hri_tc_write_CTRLA_ENABLE_bit(TC7, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */
+
+	return 0;
+}
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.h
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hpl/tc/tc_lite.h
@@ -57,6 +57,12 @@ extern "C" {
 */
 int8_t TIMER_0_init();

+/**
+ * \brief Initialize tc interface
+ * \return Initialization status.
+ */
+int8_t TC_ECAT_init();
+
 #ifdef __cplusplus
 }
 #endif
--- a/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c
+++ b/Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/main.c
@@ -1,5 +1,7 @@
 #include <atmel_start.h>
 #include "spi_slave_dma_config.h"
+#include "ethercat/ethercat_e54.h"
+#include "ethercat/ethercat_slave_def.h"

 /* Buffer length to transfer/receive */
 #define BUFFER_LEN (6)
@@ -73,6 +75,29 @@ void spi_master_init(void)
 	spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_RX_DONE, spi_master_rx_complete_cb);
 }

+// ----------------------------------------------------------------------
+// 	EtherCAT Cycle Timer - 1kHz
+// ----------------------------------------------------------------------
+void TC7_Handler(void)
+{
+	if (TC7->COUNT16.INTFLAG.bit.OVF == 0x01) {
+		TC7->COUNT16.INTFLAG.bit.OVF = 0x01;
+		//One_ms_cycle_callback();
+		//gpio_toggle_pin_level(DEBUG_1);
+		//tic_port(DEBUG_3_PORT);
+		//tic_port(DEBUG_2_PORT);
+		One_ms_cycle_callback();
+		//toc_port(DEBUG_2_PORT);
+		//Motor1.timerflags.motor_telemetry_flag = true;
+		
+	}
+}
+
+
+void enable_NVIC_IRQ(void)
+{
+	NVIC_EnableIRQ(TC7_IRQn);	 // TC7: TC_ECAT
+}

 int main(void)
 {
@@ -81,40 +106,42 @@ int main(void)
 	/* Initialize SPI master IO and Callback  */
 	spi_master_init();
 	spi_m_dma_enable(&SPI_0);
+	configure_ethercat_dma_descriptors();
+	enable_NVIC_IRQ();
 	
 	/* Start SPI Master data transfer using DMA */
 	//spi_master_rx(rx_buffer, BUFFER_LEN);
-	spi_master_tx(tx_buffer, SLAVE_BUFFER_SIZE);
+	//spi_master_tx(tx_buffer, SLAVE_BUFFER_SIZE);
 	/* Start SPI Master data reception using DMA */
 	//spi_master_rx(tx_buffer, BUFFER_LEN);
 	printf("Init Complete\n\r");
 	/* Replace with your application code */
 	while (1) {
-		delay_ms(500);
-		//tx_buffer[4] = tx_buffer[4]+1;
-		//spi_master_rx(rx_buffer, BUFFER_LEN);
-		tx_buffer[63] += 1; 
-		spi_master_tx(tx_buffer, SLAVE_BUFFER_SIZE);
-		
-		if (spi_master_tx_complete) {
-			spi_master_rx_complete = false;
-			printf("Master Sent DATA = ");
-			/* Print Received data by SPI Master from SPI Slave on Console */
-			for (int i = 0; i < SLAVE_BUFFER_SIZE; i++) {
-				printf("%u, ", tx_buffer[i]);
-			}
-			printf("\n\r");
-				
-		}
-		/* Check for SPI Master is received data from SPI Slave */
-		if (spi_master_rx_complete) {
-			spi_master_rx_complete = false;
-			printf("Master Recieved DATA = ");
-			/* Print Received data by SPI Master from SPI Slave on Console */
-			for (int i = 0; i < SLAVE_BUFFER_SIZE; i++) {
-				printf("%u, ", rx_buffer[i]);
-			}
-			printf("\n\r");
-		}		
+		//delay_ms(500);
+		////tx_buffer[4] = tx_buffer[4]+1;
+		////spi_master_rx(rx_buffer, BUFFER_LEN);
+		//tx_buffer[63] += 1; 
+		//spi_master_tx(tx_buffer, SLAVE_BUFFER_SIZE);
+		//
+		//if (spi_master_tx_complete) {
+			//spi_master_rx_complete = false;
+			//printf("Master Sent DATA = ");
+			///* Print Received data by SPI Master from SPI Slave on Console */
+			//for (int i = 0; i < SLAVE_BUFFER_SIZE; i++) {
+				//printf("%u, ", tx_buffer[i]);
+			//}
+			//printf("\n\r");
+				//
+		//}
+		///* Check for SPI Master is received data from SPI Slave */
+		//if (spi_master_rx_complete) {
+			//spi_master_rx_complete = false;
+			//printf("Master Recieved DATA = ");
+			///* Print Received data by SPI Master from SPI Slave on Console */
+			//for (int i = 0; i < SLAVE_BUFFER_SIZE; i++) {
+				//printf("%u, ", rx_buffer[i]);
+			//}
+			//printf("\n\r");
+		//}		
 	}
 }
--- a/Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/main.c
+++ b/Example/Master_Slave_IF_Test_Slave/Master_Slave_IF_Test_Slave/main.c
@@ -10,7 +10,7 @@
 extern DmacDescriptor _descriptor_section[DMAC_CH_NUM];
 extern DmacDescriptor _write_back_section[DMAC_CH_NUM];

-#define SLAVE_BUFFER_SIZE	64
+#define SLAVE_BUFFER_SIZE	32

 /* DATA transfer/reception completion flags  */
 volatile uint8_t spi_slave_tx_complete  = 0;
@@ -21,9 +21,7 @@ volatile uint8_t received_data_len      = 0;

 static uint8_t rx_buffer[SLAVE_BUFFER_SIZE] = {0};
 static uint8_t tx_buffer[SLAVE_BUFFER_SIZE] =  {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,
-												19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,
-												35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,
-												51,52,53,54,55,56,57,58,59,60,61,62,63};
+												19,20,21,22,23,24,25,26,27,28,29,30,31};

 /* Register SPI Slave DMA channel callbacks */
 void register_dma_spi_slave_callback(uint16_t channel, void *cb)
@@ -60,7 +58,7 @@ static void spi_slave_rx_complete_cb(struct _dma_resource *const resource)
 /* DMA Transfer complete callback for SPI Slave TX */
 static void spi_slave_tx_complete_cb(struct _dma_resource *const resource)
 {
-	tx_buffer[63] += 1;
+	tx_buffer[SLAVE_BUFFER_SIZE] += 1;
 	//hri_sercomspi_clear_INTEN_TXC_bit((SercomSpi *)(SPI_0.dev.prvt));
 	_dma_enable_transaction(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, false);
 	_dma_enable_transaction(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, false);
@@ -90,12 +88,12 @@ void spi_slave_init()
 {
 	_dma_set_source_address(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL,
 	(uint32_t *)&(((SercomSpi *)(SPI_0.dev.prvt))->DATA.reg));
-	_dma_set_destination_address(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, rx_buffer);
+	_dma_set_destination_address(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, rx_buffer+SLAVE_BUFFER_SIZE);
 	_dma_set_data_amount(CONF_SERCOM_5_RECEIVE_DMA_CHANNEL, SLAVE_BUFFER_SIZE);
 	
 	_dma_set_destination_address(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL,
 	(uint32_t *)&(((SercomSpi *)(SPI_0.dev.prvt))->DATA.reg));
-	_dma_set_source_address(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, tx_buffer);
+	_dma_set_source_address(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, tx_buffer+SLAVE_BUFFER_SIZE);
 	_dma_set_data_amount(CONF_SERCOM_5_TRANSMIT_DMA_CHANNEL, SLAVE_BUFFER_SIZE);
 	
 	/* callback */