Got Ecat Working
This commit is contained in:
Nicolas Trimborn
parent
2f5a303a0a
commit
7576bf10e9
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Microsoft Visual Studio Solution File, Format Version 12.00
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# Atmel Studio Solution File, Format Version 11.00
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VisualStudioVersion = 14.0.23107.0
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MinimumVisualStudioVersion = 10.0.40219.1
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Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "2_Motor_Master", "2_Motor_Master\2_Motor_Master.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
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EndProject
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Global
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GlobalSection(SolutionConfigurationPlatforms) = preSolution
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Debug|ARM = Debug|ARM
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Release|ARM = Release|ARM
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EndGlobalSection
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GlobalSection(ProjectConfigurationPlatforms) = postSolution
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{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
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{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
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{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
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{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
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EndGlobalSection
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GlobalSection(SolutionProperties) = preSolution
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HideSolutionNode = FALSE
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EndGlobalSection
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EndGlobal
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@ -0,0 +1,6 @@
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<environment>
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<configurations/>
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<device-packs>
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<device-pack device="ATSAME51J19A" name="SAME51_DFP" vendor="Atmel" version="1.1.139"/>
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</device-packs>
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</environment>
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@ -0,0 +1,245 @@
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<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
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<vendor>Atmel</vendor>
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<name>Motor_Master</name>
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<description>Project generated by Atmel Start</description>
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<url>http://start.atmel.com/</url>
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<releases>
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<release version="1.0.1">Initial version</release>
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</releases>
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<taxonomy>
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<description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
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</taxonomy>
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<generators>
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<generator id="AtmelStart">
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<description>Atmel Start</description>
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<select Dname="ATSAME51J19A" Dvendor="Atmel:3"/>
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<command>http://start.atmel.com/</command>
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<files>
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<file category="generator" name="atmel_start_config.atstart"/>
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<file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
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</files>
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</generator>
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</generators>
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<conditions>
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<condition id="CMSIS Device Startup">
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<description>Dependency on CMSIS core and Device Startup components</description>
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<require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
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<require Cclass="Device" Cgroup="Startup" Cversion="1.1.0"/>
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</condition>
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<condition id="ARMCC, GCC, IAR">
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<require Dname="ATSAME51J19A"/>
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<accept Tcompiler="ARMCC"/>
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<accept Tcompiler="GCC"/>
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<accept Tcompiler="IAR"/>
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</condition>
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<condition id="GCC">
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||||
<require Dname="ATSAME51J19A"/>
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<accept Tcompiler="GCC"/>
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</condition>
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||||
</conditions>
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||||
<components generator="AtmelStart">
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<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
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<description>Atmel Start Framework</description>
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<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
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<files>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
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||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/custom_logic.rst"/>
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||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/evsys.rst"/>
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<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/ext_irq.rst"/>
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<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/pwm.rst"/>
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<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/quad_spi_sync.rst"/>
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<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_async.rst"/>
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||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_sync.rst"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_custom_logic.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_evsys.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_ext_irq.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_qspi_sync.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_async.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_sync.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_dma.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_cmcc.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_custom_logic.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_evsys.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ext_irq.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
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<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_dma.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_sync.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_dma.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_cache.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_evsys.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_qspi_sync.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
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||||
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e51.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_can_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_cmcc_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dac_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hmatrixb_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_i2s_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_icm_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pcc_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pdec_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_qspi_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ramecc_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sdhc_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_e51.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e51.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_pwm.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_pwm.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_timer.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_ext_irq.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_pwm.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_async.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_sync.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ccl/hpl_ccl.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/cmcc/hpl_cmcc.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m4.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/eic/hpl_eic.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/evsys/hpl_evsys.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/qspi/hpl_qspi.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_adc_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_ccl_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_eic_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_evsys_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,169 @@
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|||
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File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,54 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
|
||||
*
|
||||
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \acme_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \acme_license_stop
|
||||
*
|
||||
* Project: 2_Motor_Master
|
||||
* Target: ATSAME51J19A
|
||||
*
|
||||
**/
|
||||
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
#define ATMEL_START
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
|
|
@ -0,0 +1,595 @@
|
|||
/* Auto-generated config file hpl_adc_config.h */
|
||||
#ifndef HPL_ADC_CONFIG_H
|
||||
#define HPL_ADC_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#ifndef CONF_ADC_0_ENABLE
|
||||
#define CONF_ADC_0_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <o> Conversion Result Resolution
|
||||
// <0x0=>12-bit
|
||||
// <0x1=>16-bit (averaging must be enabled)
|
||||
// <0x2=>10-bit
|
||||
// <0x3=>8-bit
|
||||
// <i> Defines the bit resolution for the ADC sample values (RESSEL)
|
||||
// <id> adc_resolution
|
||||
#ifndef CONF_ADC_0_RESSEL
|
||||
#define CONF_ADC_0_RESSEL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Reference Selection
|
||||
// <0x0=>Internal bandgap reference
|
||||
// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
|
||||
// <0x3=>VDDANA
|
||||
// <0x4=>External reference A
|
||||
// <0x5=>External reference B
|
||||
// <0x6=>External reference C
|
||||
// <i> Select the reference for the ADC (REFSEL)
|
||||
// <id> adc_reference
|
||||
#ifndef CONF_ADC_0_REFSEL
|
||||
#define CONF_ADC_0_REFSEL 0x4
|
||||
#endif
|
||||
|
||||
// <o> Prescaler configuration
|
||||
// <0x0=>Peripheral clock divided by 2
|
||||
// <0x1=>Peripheral clock divided by 4
|
||||
// <0x2=>Peripheral clock divided by 8
|
||||
// <0x3=>Peripheral clock divided by 16
|
||||
// <0x4=>Peripheral clock divided by 32
|
||||
// <0x5=>Peripheral clock divided by 64
|
||||
// <0x6=>Peripheral clock divided by 128
|
||||
// <0x7=>Peripheral clock divided by 256
|
||||
// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
|
||||
// <id> adc_prescaler
|
||||
#ifndef CONF_ADC_0_PRESCALER
|
||||
#define CONF_ADC_0_PRESCALER 0x0
|
||||
#endif
|
||||
|
||||
// <q> Free Running Mode
|
||||
// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
|
||||
// <id> adc_freerunning_mode
|
||||
#ifndef CONF_ADC_0_FREERUN
|
||||
#define CONF_ADC_0_FREERUN 0
|
||||
#endif
|
||||
|
||||
// <q> Differential Mode
|
||||
// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
|
||||
// <id> adc_differential_mode
|
||||
#ifndef CONF_ADC_0_DIFFMODE
|
||||
#define CONF_ADC_0_DIFFMODE 1
|
||||
#endif
|
||||
|
||||
// <o> Positive Mux Input Selection
|
||||
// <0x00=>ADC AIN0 pin
|
||||
// <0x01=>ADC AIN1 pin
|
||||
// <0x02=>ADC AIN2 pin
|
||||
// <0x03=>ADC AIN3 pin
|
||||
// <0x04=>ADC AIN4 pin
|
||||
// <0x05=>ADC AIN5 pin
|
||||
// <0x06=>ADC AIN6 pin
|
||||
// <0x07=>ADC AIN7 pin
|
||||
// <0x08=>ADC AIN8 pin
|
||||
// <0x09=>ADC AIN9 pin
|
||||
// <0x0A=>ADC AIN10 pin
|
||||
// <0x0B=>ADC AIN11 pin
|
||||
// <0x0C=>ADC AIN12 pin
|
||||
// <0x0D=>ADC AIN13 pin
|
||||
// <0x0E=>ADC AIN14 pin
|
||||
// <0x0F=>ADC AIN15 pin
|
||||
// <0x18=>1/4 scaled core supply
|
||||
// <0x19=>1/4 Scaled VBAT Supply
|
||||
// <0x1A=>1/4 scaled I/O supply
|
||||
// <0x1B=>Bandgap voltage
|
||||
// <0x1C=>Temperature reference (PTAT)
|
||||
// <0x1D=>Temperature reference (CTAT)
|
||||
// <0x1E=>DAC Output
|
||||
// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
|
||||
// <id> adc_pinmux_positive
|
||||
#ifndef CONF_ADC_0_MUXPOS
|
||||
#define CONF_ADC_0_MUXPOS 0x0
|
||||
#endif
|
||||
|
||||
// <o> Negative Mux Input Selection
|
||||
// <0x00=>ADC AIN0 pin
|
||||
// <0x01=>ADC AIN1 pin
|
||||
// <0x02=>ADC AIN2 pin
|
||||
// <0x03=>ADC AIN3 pin
|
||||
// <0x04=>ADC AIN4 pin
|
||||
// <0x05=>ADC AIN5 pin
|
||||
// <0x06=>ADC AIN6 pin
|
||||
// <0x07=>ADC AIN7 pin
|
||||
// <0x18=>Internal ground
|
||||
// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
|
||||
// <id> adc_pinmux_negative
|
||||
#ifndef CONF_ADC_0_MUXNEG
|
||||
#define CONF_ADC_0_MUXNEG 0x2
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> adc_advanced_settings
|
||||
#ifndef CONF_ADC_0_ADVANCED
|
||||
#define CONF_ADC_0_ADVANCED 0
|
||||
#endif
|
||||
|
||||
// <q> Run in standby
|
||||
// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
|
||||
// <id> adc_arch_runstdby
|
||||
#ifndef CONF_ADC_0_RUNSTDBY
|
||||
#define CONF_ADC_0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q>Debug Run
|
||||
// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
|
||||
// <id> adc_arch_dbgrun
|
||||
#ifndef CONF_ADC_0_DBGRUN
|
||||
#define CONF_ADC_0_DBGRUN 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
|
||||
// <id> adc_arch_ondemand
|
||||
#ifndef CONF_ADC_0_ONDEMAND
|
||||
#define CONF_ADC_0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Left-Adjusted Result
|
||||
// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
|
||||
// <id> adc_arch_leftadj
|
||||
#ifndef CONF_ADC_0_LEFTADJ
|
||||
#define CONF_ADC_0_LEFTADJ 0
|
||||
#endif
|
||||
|
||||
// <q> Reference Buffer Offset Compensation Enable
|
||||
// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
|
||||
// <id> adc_arch_refcomp
|
||||
#ifndef CONF_ADC_0_REFCOMP
|
||||
#define CONF_ADC_0_REFCOMP 0
|
||||
#endif
|
||||
|
||||
// <q>Comparator Offset Compensation Enable
|
||||
// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
|
||||
// <id> adc_arch_offcomp
|
||||
#ifndef CONF_ADC_0_OFFCOMP
|
||||
#define CONF_ADC_0_OFFCOMP 0
|
||||
#endif
|
||||
|
||||
// <q> Digital Correction Logic Enabled
|
||||
// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
|
||||
// <id> adc_arch_corren
|
||||
#ifndef CONF_ADC_0_CORREN
|
||||
#define CONF_ADC_0_CORREN 0
|
||||
#endif
|
||||
|
||||
// <o> Offset Correction Value <0-4095>
|
||||
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
|
||||
// <id> adc_arch_offsetcorr
|
||||
#ifndef CONF_ADC_0_OFFSETCORR
|
||||
#define CONF_ADC_0_OFFSETCORR 0
|
||||
#endif
|
||||
|
||||
// <o> Gain Correction Value <0-4095>
|
||||
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
|
||||
// <id> adc_arch_gaincorr
|
||||
#ifndef CONF_ADC_0_GAINCORR
|
||||
#define CONF_ADC_0_GAINCORR 0
|
||||
#endif
|
||||
|
||||
// <o> Adjusting Result / Division Coefficient <0-7>
|
||||
// <i> These bits define the division coefficient in 2n steps. (ADJRES)
|
||||
// <id> adc_arch_adjres
|
||||
#ifndef CONF_ADC_0_ADJRES
|
||||
#define CONF_ADC_0_ADJRES 0x0
|
||||
#endif
|
||||
|
||||
// <o.0..10> Number of Samples to be Collected
|
||||
// <0x0=>1 sample
|
||||
// <0x1=>2 samples
|
||||
// <0x2=>4 samples
|
||||
// <0x3=>8 samples
|
||||
// <0x4=>16 samples
|
||||
// <0x5=>32 samples
|
||||
// <0x6=>64 samples
|
||||
// <0x7=>128 samples
|
||||
// <0x8=>256 samples
|
||||
// <0x9=>512 samples
|
||||
// <0xA=>1024 samples
|
||||
// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
|
||||
// <id> adc_arch_samplenum
|
||||
#ifndef CONF_ADC_0_SAMPLENUM
|
||||
#define CONF_ADC_0_SAMPLENUM 0x0
|
||||
#endif
|
||||
|
||||
// <o> Sampling Time Length <0-63>
|
||||
// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
|
||||
// <id> adc_arch_samplen
|
||||
#ifndef CONF_ADC_0_SAMPLEN
|
||||
#define CONF_ADC_0_SAMPLEN 0
|
||||
#endif
|
||||
|
||||
// <o> Window Monitor Mode
|
||||
// <0x0=>No window mode
|
||||
// <0x1=>Mode 1: RESULT above lower threshold
|
||||
// <0x2=>Mode 2: RESULT beneath upper threshold
|
||||
// <0x3=>Mode 3: RESULT inside lower and upper threshold
|
||||
// <0x4=>Mode 4: RESULT outside lower and upper threshold
|
||||
// <i> These bits enable and define the window monitor mode. (WINMODE)
|
||||
// <id> adc_arch_winmode
|
||||
#ifndef CONF_ADC_0_WINMODE
|
||||
#define CONF_ADC_0_WINMODE 0x0
|
||||
#endif
|
||||
|
||||
// <o> Window Monitor Lower Threshold <0-65535>
|
||||
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
|
||||
// <id> adc_arch_winlt
|
||||
#ifndef CONF_ADC_0_WINLT
|
||||
#define CONF_ADC_0_WINLT 0
|
||||
#endif
|
||||
|
||||
// <o> Window Monitor Upper Threshold <0-65535>
|
||||
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
|
||||
// <id> adc_arch_winut
|
||||
#ifndef CONF_ADC_0_WINUT
|
||||
#define CONF_ADC_0_WINUT 0
|
||||
#endif
|
||||
|
||||
// <o> Bitmask for positive input sequence <0-4294967295>
|
||||
// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
|
||||
// <id> adc_arch_seqen
|
||||
#ifndef CONF_ADC_0_SEQEN
|
||||
#define CONF_ADC_0_SEQEN 0x0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Event Control
|
||||
// <id> adc_arch_event_settings
|
||||
#ifndef CONF_ADC_0_EVENT_CONTROL
|
||||
#define CONF_ADC_0_EVENT_CONTROL 0
|
||||
#endif
|
||||
|
||||
// <q> Window Monitor Event Out
|
||||
// <i> Enables event output on window event (WINMONEO)
|
||||
// <id> adc_arch_winmoneo
|
||||
#ifndef CONF_ADC_0_WINMONEO
|
||||
#define CONF_ADC_0_WINMONEO 0
|
||||
#endif
|
||||
|
||||
// <q> Result Ready Event Out
|
||||
// <i> Enables event output on result ready event (RESRDEO)
|
||||
// <id> adc_arch_resrdyeo
|
||||
#ifndef CONF_ADC_0_RESRDYEO
|
||||
#define CONF_ADC_0_RESRDYEO 0
|
||||
#endif
|
||||
|
||||
// <q> Invert flush Event Signal
|
||||
// <i> Invert the flush event input signal (FLUSHINV)
|
||||
// <id> adc_arch_flushinv
|
||||
#ifndef CONF_ADC_0_FLUSHINV
|
||||
#define CONF_ADC_0_FLUSHINV 0
|
||||
#endif
|
||||
|
||||
// <q> Trigger Flush On Event
|
||||
// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
|
||||
// <id> adc_arch_flushei
|
||||
#ifndef CONF_ADC_0_FLUSHEI
|
||||
#define CONF_ADC_0_FLUSHEI 0
|
||||
#endif
|
||||
|
||||
// <q> Invert Start Conversion Event Signal
|
||||
// <i> Invert the start conversion event input signal (STARTINV)
|
||||
// <id> adc_arch_startinv
|
||||
#ifndef CONF_ADC_0_STARTINV
|
||||
#define CONF_ADC_0_STARTINV 0
|
||||
#endif
|
||||
|
||||
// <q> Trigger Conversion On Event
|
||||
// <i> Trigger a conversion on event. (STARTEI)
|
||||
// <id> adc_arch_startei
|
||||
#ifndef CONF_ADC_0_STARTEI
|
||||
#define CONF_ADC_0_STARTEI 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
#ifndef CONF_ADC_1_ENABLE
|
||||
#define CONF_ADC_1_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <o> Conversion Result Resolution
|
||||
// <0x0=>12-bit
|
||||
// <0x1=>16-bit (averaging must be enabled)
|
||||
// <0x2=>10-bit
|
||||
// <0x3=>8-bit
|
||||
// <i> Defines the bit resolution for the ADC sample values (RESSEL)
|
||||
// <id> adc_resolution
|
||||
#ifndef CONF_ADC_1_RESSEL
|
||||
#define CONF_ADC_1_RESSEL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Reference Selection
|
||||
// <0x0=>Internal bandgap reference
|
||||
// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
|
||||
// <0x3=>VDDANA
|
||||
// <0x4=>External reference A
|
||||
// <0x5=>External reference B
|
||||
// <0x6=>External reference C
|
||||
// <i> Select the reference for the ADC (REFSEL)
|
||||
// <id> adc_reference
|
||||
#ifndef CONF_ADC_1_REFSEL
|
||||
#define CONF_ADC_1_REFSEL 0x4
|
||||
#endif
|
||||
|
||||
// <o> Prescaler configuration
|
||||
// <0x0=>Peripheral clock divided by 2
|
||||
// <0x1=>Peripheral clock divided by 4
|
||||
// <0x2=>Peripheral clock divided by 8
|
||||
// <0x3=>Peripheral clock divided by 16
|
||||
// <0x4=>Peripheral clock divided by 32
|
||||
// <0x5=>Peripheral clock divided by 64
|
||||
// <0x6=>Peripheral clock divided by 128
|
||||
// <0x7=>Peripheral clock divided by 256
|
||||
// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
|
||||
// <id> adc_prescaler
|
||||
#ifndef CONF_ADC_1_PRESCALER
|
||||
#define CONF_ADC_1_PRESCALER 0x0
|
||||
#endif
|
||||
|
||||
// <q> Free Running Mode
|
||||
// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
|
||||
// <id> adc_freerunning_mode
|
||||
#ifndef CONF_ADC_1_FREERUN
|
||||
#define CONF_ADC_1_FREERUN 0
|
||||
#endif
|
||||
|
||||
// <q> Differential Mode
|
||||
// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
|
||||
// <id> adc_differential_mode
|
||||
#ifndef CONF_ADC_1_DIFFMODE
|
||||
#define CONF_ADC_1_DIFFMODE 1
|
||||
#endif
|
||||
|
||||
// <o> Positive Mux Input Selection
|
||||
// <0x00=>ADC AIN0 pin
|
||||
// <0x01=>ADC AIN1 pin
|
||||
// <0x02=>ADC AIN2 pin
|
||||
// <0x03=>ADC AIN3 pin
|
||||
// <0x04=>ADC AIN4 pin
|
||||
// <0x05=>ADC AIN5 pin
|
||||
// <0x06=>ADC AIN6 pin
|
||||
// <0x07=>ADC AIN7 pin
|
||||
// <0x08=>ADC AIN8 pin
|
||||
// <0x09=>ADC AIN9 pin
|
||||
// <0x0A=>ADC AIN10 pin
|
||||
// <0x0B=>ADC AIN11 pin
|
||||
// <0x0C=>ADC AIN12 pin
|
||||
// <0x0D=>ADC AIN13 pin
|
||||
// <0x0E=>ADC AIN14 pin
|
||||
// <0x0F=>ADC AIN15 pin
|
||||
// <0x18=>1/4 scaled core supply
|
||||
// <0x19=>1/4 Scaled VBAT Supply
|
||||
// <0x1A=>1/4 scaled I/O supply
|
||||
// <0x1B=>Bandgap voltage
|
||||
// <0x1C=>Temperature reference (PTAT)
|
||||
// <0x1D=>Temperature reference (CTAT)
|
||||
// <0x1E=>DAC Output
|
||||
// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
|
||||
// <id> adc_pinmux_positive
|
||||
#ifndef CONF_ADC_1_MUXPOS
|
||||
#define CONF_ADC_1_MUXPOS 0x1
|
||||
#endif
|
||||
|
||||
// <o> Negative Mux Input Selection
|
||||
// <0x00=>ADC AIN0 pin
|
||||
// <0x01=>ADC AIN1 pin
|
||||
// <0x02=>ADC AIN2 pin
|
||||
// <0x03=>ADC AIN3 pin
|
||||
// <0x04=>ADC AIN4 pin
|
||||
// <0x05=>ADC AIN5 pin
|
||||
// <0x06=>ADC AIN6 pin
|
||||
// <0x07=>ADC AIN7 pin
|
||||
// <0x18=>Internal ground
|
||||
// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
|
||||
// <id> adc_pinmux_negative
|
||||
#ifndef CONF_ADC_1_MUXNEG
|
||||
#define CONF_ADC_1_MUXNEG 0x0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> adc_advanced_settings
|
||||
#ifndef CONF_ADC_1_ADVANCED
|
||||
#define CONF_ADC_1_ADVANCED 0
|
||||
#endif
|
||||
|
||||
// <q> Run in standby
|
||||
// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
|
||||
// <id> adc_arch_runstdby
|
||||
#ifndef CONF_ADC_1_RUNSTDBY
|
||||
#define CONF_ADC_1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q>Debug Run
|
||||
// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
|
||||
// <id> adc_arch_dbgrun
|
||||
#ifndef CONF_ADC_1_DBGRUN
|
||||
#define CONF_ADC_1_DBGRUN 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
|
||||
// <id> adc_arch_ondemand
|
||||
#ifndef CONF_ADC_1_ONDEMAND
|
||||
#define CONF_ADC_1_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Left-Adjusted Result
|
||||
// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
|
||||
// <id> adc_arch_leftadj
|
||||
#ifndef CONF_ADC_1_LEFTADJ
|
||||
#define CONF_ADC_1_LEFTADJ 0
|
||||
#endif
|
||||
|
||||
// <q> Reference Buffer Offset Compensation Enable
|
||||
// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
|
||||
// <id> adc_arch_refcomp
|
||||
#ifndef CONF_ADC_1_REFCOMP
|
||||
#define CONF_ADC_1_REFCOMP 0
|
||||
#endif
|
||||
|
||||
// <q>Comparator Offset Compensation Enable
|
||||
// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
|
||||
// <id> adc_arch_offcomp
|
||||
#ifndef CONF_ADC_1_OFFCOMP
|
||||
#define CONF_ADC_1_OFFCOMP 0
|
||||
#endif
|
||||
|
||||
// <q> Digital Correction Logic Enabled
|
||||
// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
|
||||
// <id> adc_arch_corren
|
||||
#ifndef CONF_ADC_1_CORREN
|
||||
#define CONF_ADC_1_CORREN 0
|
||||
#endif
|
||||
|
||||
// <o> Offset Correction Value <0-4095>
|
||||
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
|
||||
// <id> adc_arch_offsetcorr
|
||||
#ifndef CONF_ADC_1_OFFSETCORR
|
||||
#define CONF_ADC_1_OFFSETCORR 0
|
||||
#endif
|
||||
|
||||
// <o> Gain Correction Value <0-4095>
|
||||
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
|
||||
// <id> adc_arch_gaincorr
|
||||
#ifndef CONF_ADC_1_GAINCORR
|
||||
#define CONF_ADC_1_GAINCORR 0
|
||||
#endif
|
||||
|
||||
// <o> Adjusting Result / Division Coefficient <0-7>
|
||||
// <i> These bits define the division coefficient in 2n steps. (ADJRES)
|
||||
// <id> adc_arch_adjres
|
||||
#ifndef CONF_ADC_1_ADJRES
|
||||
#define CONF_ADC_1_ADJRES 0x0
|
||||
#endif
|
||||
|
||||
// <o.0..10> Number of Samples to be Collected
|
||||
// <0x0=>1 sample
|
||||
// <0x1=>2 samples
|
||||
// <0x2=>4 samples
|
||||
// <0x3=>8 samples
|
||||
// <0x4=>16 samples
|
||||
// <0x5=>32 samples
|
||||
// <0x6=>64 samples
|
||||
// <0x7=>128 samples
|
||||
// <0x8=>256 samples
|
||||
// <0x9=>512 samples
|
||||
// <0xA=>1024 samples
|
||||
// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
|
||||
// <id> adc_arch_samplenum
|
||||
#ifndef CONF_ADC_1_SAMPLENUM
|
||||
#define CONF_ADC_1_SAMPLENUM 0x0
|
||||
#endif
|
||||
|
||||
// <o> Sampling Time Length <0-63>
|
||||
// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
|
||||
// <id> adc_arch_samplen
|
||||
#ifndef CONF_ADC_1_SAMPLEN
|
||||
#define CONF_ADC_1_SAMPLEN 0
|
||||
#endif
|
||||
|
||||
// <o> Window Monitor Mode
|
||||
// <0x0=>No window mode
|
||||
// <0x1=>Mode 1: RESULT above lower threshold
|
||||
// <0x2=>Mode 2: RESULT beneath upper threshold
|
||||
// <0x3=>Mode 3: RESULT inside lower and upper threshold
|
||||
// <0x4=>Mode 4: RESULT outside lower and upper threshold
|
||||
// <i> These bits enable and define the window monitor mode. (WINMODE)
|
||||
// <id> adc_arch_winmode
|
||||
#ifndef CONF_ADC_1_WINMODE
|
||||
#define CONF_ADC_1_WINMODE 0x0
|
||||
#endif
|
||||
|
||||
// <o> Window Monitor Lower Threshold <0-65535>
|
||||
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
|
||||
// <id> adc_arch_winlt
|
||||
#ifndef CONF_ADC_1_WINLT
|
||||
#define CONF_ADC_1_WINLT 0
|
||||
#endif
|
||||
|
||||
// <o> Window Monitor Upper Threshold <0-65535>
|
||||
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
|
||||
// <id> adc_arch_winut
|
||||
#ifndef CONF_ADC_1_WINUT
|
||||
#define CONF_ADC_1_WINUT 0
|
||||
#endif
|
||||
|
||||
// <o> Bitmask for positive input sequence <0-4294967295>
|
||||
// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
|
||||
// <id> adc_arch_seqen
|
||||
#ifndef CONF_ADC_1_SEQEN
|
||||
#define CONF_ADC_1_SEQEN 0x0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Event Control
|
||||
// <id> adc_arch_event_settings
|
||||
#ifndef CONF_ADC_1_EVENT_CONTROL
|
||||
#define CONF_ADC_1_EVENT_CONTROL 0
|
||||
#endif
|
||||
|
||||
// <q> Window Monitor Event Out
|
||||
// <i> Enables event output on window event (WINMONEO)
|
||||
// <id> adc_arch_winmoneo
|
||||
#ifndef CONF_ADC_1_WINMONEO
|
||||
#define CONF_ADC_1_WINMONEO 0
|
||||
#endif
|
||||
|
||||
// <q> Result Ready Event Out
|
||||
// <i> Enables event output on result ready event (RESRDEO)
|
||||
// <id> adc_arch_resrdyeo
|
||||
#ifndef CONF_ADC_1_RESRDYEO
|
||||
#define CONF_ADC_1_RESRDYEO 0
|
||||
#endif
|
||||
|
||||
// <q> Invert flush Event Signal
|
||||
// <i> Invert the flush event input signal (FLUSHINV)
|
||||
// <id> adc_arch_flushinv
|
||||
#ifndef CONF_ADC_1_FLUSHINV
|
||||
#define CONF_ADC_1_FLUSHINV 0
|
||||
#endif
|
||||
|
||||
// <q> Trigger Flush On Event
|
||||
// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
|
||||
// <id> adc_arch_flushei
|
||||
#ifndef CONF_ADC_1_FLUSHEI
|
||||
#define CONF_ADC_1_FLUSHEI 0
|
||||
#endif
|
||||
|
||||
// <q> Invert Start Conversion Event Signal
|
||||
// <i> Invert the start conversion event input signal (STARTINV)
|
||||
// <id> adc_arch_startinv
|
||||
#ifndef CONF_ADC_1_STARTINV
|
||||
#define CONF_ADC_1_STARTINV 0
|
||||
#endif
|
||||
|
||||
// <q> Trigger Conversion On Event
|
||||
// <i> Trigger a conversion on event. (STARTEI)
|
||||
// <id> adc_arch_startei
|
||||
#ifndef CONF_ADC_1_STARTEI
|
||||
#define CONF_ADC_1_STARTEI 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_ADC_CONFIG_H
|
||||
|
|
@ -0,0 +1,499 @@
|
|||
/* Auto-generated config file hpl_ccl_config.h */
|
||||
#ifndef HPL_CCL_CONFIG_H
|
||||
#define HPL_CCL_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <o> Sequential Control Logic 0
|
||||
// <0x0=> Sequential logic is disabled
|
||||
// <0x1=> D flip flop
|
||||
// <0x2=> JK flip flop
|
||||
// <0x3=> D latch
|
||||
// <0x4=> RS latch
|
||||
// <i> Selects mode for sequential module 0
|
||||
// <id> ccl_arch_seqsel_0
|
||||
#ifndef CONF_CCL_SEQSEL_0
|
||||
#define CONF_CCL_SEQSEL_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> Sequential Control Logic 1
|
||||
// <0x0=> Sequential logic is disabled
|
||||
// <0x1=> D flip flop
|
||||
// <0x2=> JK flip flop
|
||||
// <0x3=> D latch
|
||||
// <0x4=> RS latch
|
||||
// <i> Selects mode for sequential module 1
|
||||
// <id> ccl_arch_seqsel_1
|
||||
#ifndef CONF_CCL_SEQSEL_1
|
||||
#define CONF_CCL_SEQSEL_1 0x0
|
||||
#endif
|
||||
|
||||
// <e> Lookup Table Control 0
|
||||
// <i> Enable and setup the lookup table module 0
|
||||
// <id> ccl_arch_lutctrl0
|
||||
#ifndef CONF_CCL_LUTCTRL_EN_0
|
||||
#define CONF_CCL_LUTCTRL_EN_0 0
|
||||
#endif
|
||||
|
||||
// <o> Truth Table <0x00-0xFF>
|
||||
// <i> Define the value of truth logic according to inputs IN[2:0]
|
||||
// <id> ccl_arch_truth_0
|
||||
#ifndef CONF_CCL_TRUTH_0
|
||||
#define CONF_CCL_TRUTH_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> Input Source Selection 0
|
||||
// <0x0=> Masked input
|
||||
// <0x1=> Feedback input source
|
||||
// <0x2=> Linked LookUpTable input source
|
||||
// <0x3=> Event input source
|
||||
// <0x4=> IO pin input source
|
||||
// <0x5=> AC input source
|
||||
// <0x6=> TC input source
|
||||
// <0x7=> Alternative TC input source
|
||||
// <0x8=> TCC input source
|
||||
// <0x9=> SERCOM input source
|
||||
// <id> ccl_arch_insel0_0
|
||||
#ifndef CONF_CCL_INSEL0_0
|
||||
#define CONF_CCL_INSEL0_0 0x4
|
||||
#endif
|
||||
|
||||
// <o> Input Source Selection 1
|
||||
// <0x0=> Masked input
|
||||
// <0x1=> Feedback input source
|
||||
// <0x2=> Linked LookUpTable input source
|
||||
// <0x3=> Event input source
|
||||
// <0x4=> IO pin input source
|
||||
// <0x5=> AC input source
|
||||
// <0x6=> TC input source
|
||||
// <0x7=> Alternative TC input source
|
||||
// <0x8=> TCC input source
|
||||
// <0x9=> SERCOM input source
|
||||
// <id> ccl_arch_insel1_0
|
||||
#ifndef CONF_CCL_INSEL1_0
|
||||
#define CONF_CCL_INSEL1_0 0x4
|
||||
#endif
|
||||
|
||||
// <o> Input Source Selection 2
|
||||
// <0x0=> Masked input
|
||||
// <0x1=> Feedback input source
|
||||
// <0x2=> Linked LookUpTable input source
|
||||
// <0x3=> Event input source
|
||||
// <0x4=> IO pin input source
|
||||
// <0x5=> AC input source
|
||||
// <0x6=> TC input source
|
||||
// <0x7=> Alternative TC input source
|
||||
// <0x8=> TCC input source
|
||||
// <0x9=> SERCOM input source
|
||||
// <id> ccl_arch_insel2_0
|
||||
#ifndef CONF_CCL_INSEL2_0
|
||||
#define CONF_CCL_INSEL2_0 0x4
|
||||
#endif
|
||||
|
||||
// <q> Edge detector enable
|
||||
// <id> ccl_arch_edgesel_0
|
||||
#ifndef CONF_CCL_EDGESEL_0
|
||||
#define CONF_CCL_EDGESEL_0 0
|
||||
#endif
|
||||
|
||||
// <o> Output Filter
|
||||
// <0x0=> Disabled
|
||||
// <0x1=> Synchronizer Enabled
|
||||
// <0x2=> Filter Enabled
|
||||
// <id> ccl_arch_filtsel_0
|
||||
#ifndef CONF_CCL_FILTSEL_0
|
||||
#define CONF_CCL_FILTSEL_0 0x0
|
||||
#endif
|
||||
|
||||
// <h> Event settings 0
|
||||
|
||||
// <q> Event output enable
|
||||
// <id> ccl_arch_luteo_0
|
||||
#ifndef CONF_CCL_LUTEO_0
|
||||
#define CONF_CCL_LUTEO_0 0
|
||||
#endif
|
||||
|
||||
// <q> Event input enable
|
||||
// <id> ccl_arch_lutei_0
|
||||
#ifndef CONF_CCL_LUTEI_0
|
||||
#define CONF_CCL_LUTEI_0 0
|
||||
#endif
|
||||
|
||||
// <q> Event input invert
|
||||
// <id> ccl_arch_invei_0
|
||||
#ifndef CONF_CCL_INVEI_0
|
||||
#define CONF_CCL_INVEI_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <hidden> Persistance settings 0
|
||||
|
||||
// <s> Expression Persistance
|
||||
// <id> ccl_e_persistance_0
|
||||
#define EXPRESSION_PERSISTANCE_0 ""
|
||||
|
||||
// <s> Logic Persistance
|
||||
// <id> ccl_l_persistance_0
|
||||
#define LOGIC_PERSISTANCE_0 ""
|
||||
|
||||
// </hidden>
|
||||
|
||||
// <e> Lookup Table Control 1
|
||||
// <i> Enable and setup the lookup table module 1
|
||||
// <id> ccl_arch_lutctrl1
|
||||
#ifndef CONF_CCL_LUTCTRL_EN_1
|
||||
#define CONF_CCL_LUTCTRL_EN_1 0
|
||||
#endif
|
||||
|
||||
// <o> Truth Table <0x00-0xFF>
|
||||
// <i> Define the value of truth logic according to inputs IN[2:0]
|
||||
// <id> ccl_arch_truth_1
|
||||
#ifndef CONF_CCL_TRUTH_1
|
||||
#define CONF_CCL_TRUTH_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> Input Source Selection 0
|
||||
// <0x0=> Masked input
|
||||
// <0x1=> Feedback input source
|
||||
// <0x2=> Linked LookUpTable input source
|
||||
// <0x3=> Event input source
|
||||
// <0x4=> IO pin input source
|
||||
// <0x5=> AC input source
|
||||
// <0x6=> TC input source
|
||||
// <0x7=> Alternative TC input source
|
||||
// <0x8=> TCC input source
|
||||
// <0x9=> SERCOM input source
|
||||
// <id> ccl_arch_insel0_1
|
||||
#ifndef CONF_CCL_INSEL0_1
|
||||
#define CONF_CCL_INSEL0_1 0x4
|
||||
#endif
|
||||
|
||||
// <o> Input Source Selection 1
|
||||
// <0x0=> Masked input
|
||||
// <0x1=> Feedback input source
|
||||
// <0x2=> Linked LookUpTable input source
|
||||
// <0x3=> Event input source
|
||||
// <0x4=> IO pin input source
|
||||
// <0x5=> AC input source
|
||||
// <0x6=> TC input source
|
||||
// <0x7=> Alternative TC input source
|
||||
// <0x8=> TCC input source
|
||||
// <0x9=> SERCOM input source
|
||||
// <id> ccl_arch_insel1_1
|
||||
#ifndef CONF_CCL_INSEL1_1
|
||||
#define CONF_CCL_INSEL1_1 0x4
|
||||
#endif
|
||||
|
||||
// <o> Input Source Selection 2
|
||||
// <0x0=> Masked input
|
||||
// <0x1=> Feedback input source
|
||||
// <0x2=> Linked LookUpTable input source
|
||||
// <0x3=> Event input source
|
||||
// <0x4=> IO pin input source
|
||||
// <0x5=> AC input source
|
||||
// <0x6=> TC input source
|
||||
// <0x7=> Alternative TC input source
|
||||
// <0x8=> TCC input source
|
||||
// <0x9=> SERCOM input source
|
||||
// <id> ccl_arch_insel2_1
|
||||
#ifndef CONF_CCL_INSEL2_1
|
||||
#define CONF_CCL_INSEL2_1 0x4
|
||||
#endif
|
||||
|
||||
// <q> Edge detector enable
|
||||
// <id> ccl_arch_edgesel_1
|
||||
#ifndef CONF_CCL_EDGESEL_1
|
||||
#define CONF_CCL_EDGESEL_1 0
|
||||
#endif
|
||||
|
||||
// <o> Output Filter
|
||||
// <0x0=> Disabled
|
||||
// <0x1=> Synchronizer Enabled
|
||||
// <0x2=> Filter Enabled
|
||||
// <id> ccl_arch_filtsel_1
|
||||
#ifndef CONF_CCL_FILTSEL_1
|
||||
#define CONF_CCL_FILTSEL_1 0x0
|
||||
#endif
|
||||
|
||||
// <h> Event settings 1
|
||||
|
||||
// <q> Event output enable
|
||||
// <id> ccl_arch_luteo_1
|
||||
#ifndef CONF_CCL_LUTEO_1
|
||||
#define CONF_CCL_LUTEO_1 0
|
||||
#endif
|
||||
|
||||
// <q> Event input enable
|
||||
// <id> ccl_arch_lutei_1
|
||||
#ifndef CONF_CCL_LUTEI_1
|
||||
#define CONF_CCL_LUTEI_1 0
|
||||
#endif
|
||||
|
||||
// <q> Event input invert
|
||||
// <id> ccl_arch_invei_1
|
||||
#ifndef CONF_CCL_INVEI_1
|
||||
#define CONF_CCL_INVEI_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <hidden> Persistance settings 1
|
||||
|
||||
// <s> Expression Persistance
|
||||
// <id> ccl_e_persistance_1
|
||||
#define EXPRESSION_PERSISTANCE_1 ""
|
||||
|
||||
// <s> Logic Persistance
|
||||
// <id> ccl_l_persistance_1
|
||||
#define LOGIC_PERSISTANCE_1 ""
|
||||
|
||||
// </hidden>
|
||||
|
||||
// <e> Lookup Table Control 2
|
||||
// <i> Enable and setup the lookup table module 2
|
||||
// <id> ccl_arch_lutctrl2
|
||||
#ifndef CONF_CCL_LUTCTRL_EN_2
|
||||
#define CONF_CCL_LUTCTRL_EN_2 0
|
||||
#endif
|
||||
|
||||
// <o> Truth Table <0x00-0xFF>
|
||||
// <i> Define the value of truth logic according to inputs IN[2:0]
|
||||
// <id> ccl_arch_truth_2
|
||||
#ifndef CONF_CCL_TRUTH_2
|
||||
#define CONF_CCL_TRUTH_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> Input Source Selection 0
|
||||
// <0x0=> Masked input
|
||||
// <0x1=> Feedback input source
|
||||
// <0x2=> Linked LookUpTable input source
|
||||
// <0x3=> Event input source
|
||||
// <0x4=> IO pin input source
|
||||
// <0x5=> AC input source
|
||||
// <0x6=> TC input source
|
||||
// <0x7=> Alternative TC input source
|
||||
// <0x8=> TCC input source
|
||||
// <0x9=> SERCOM input source
|
||||
// <id> ccl_arch_insel0_2
|
||||
#ifndef CONF_CCL_INSEL0_2
|
||||
#define CONF_CCL_INSEL0_2 0x4
|
||||
#endif
|
||||
|
||||
// <o> Input Source Selection 1
|
||||
// <0x0=> Masked input
|
||||
// <0x1=> Feedback input source
|
||||
// <0x2=> Linked LookUpTable input source
|
||||
// <0x3=> Event input source
|
||||
// <0x4=> IO pin input source
|
||||
// <0x5=> AC input source
|
||||
// <0x6=> TC input source
|
||||
// <0x7=> Alternative TC input source
|
||||
// <0x8=> TCC input source
|
||||
// <0x9=> SERCOM input source
|
||||
// <id> ccl_arch_insel1_2
|
||||
#ifndef CONF_CCL_INSEL1_2
|
||||
#define CONF_CCL_INSEL1_2 0x4
|
||||
#endif
|
||||
|
||||
// <o> Input Source Selection 2
|
||||
// <0x0=> Masked input
|
||||
// <0x1=> Feedback input source
|
||||
// <0x2=> Linked LookUpTable input source
|
||||
// <0x3=> Event input source
|
||||
// <0x4=> IO pin input source
|
||||
// <0x5=> AC input source
|
||||
// <0x6=> TC input source
|
||||
// <0x7=> Alternative TC input source
|
||||
// <0x8=> TCC input source
|
||||
// <0x9=> SERCOM input source
|
||||
// <id> ccl_arch_insel2_2
|
||||
#ifndef CONF_CCL_INSEL2_2
|
||||
#define CONF_CCL_INSEL2_2 0x4
|
||||
#endif
|
||||
|
||||
// <q> Edge detector enable
|
||||
// <id> ccl_arch_edgesel_2
|
||||
#ifndef CONF_CCL_EDGESEL_2
|
||||
#define CONF_CCL_EDGESEL_2 0
|
||||
#endif
|
||||
|
||||
// <o> Output Filter
|
||||
// <0x0=> Disabled
|
||||
// <0x1=> Synchronizer Enabled
|
||||
// <0x2=> Filter Enabled
|
||||
// <id> ccl_arch_filtsel_2
|
||||
#ifndef CONF_CCL_FILTSEL_2
|
||||
#define CONF_CCL_FILTSEL_2 0x0
|
||||
#endif
|
||||
|
||||
// <h> Event settings 2
|
||||
|
||||
// <q> Event output enable
|
||||
// <id> ccl_arch_luteo_2
|
||||
#ifndef CONF_CCL_LUTEO_2
|
||||
#define CONF_CCL_LUTEO_2 0
|
||||
#endif
|
||||
|
||||
// <q> Event input enable
|
||||
// <id> ccl_arch_lutei_2
|
||||
#ifndef CONF_CCL_LUTEI_2
|
||||
#define CONF_CCL_LUTEI_2 0
|
||||
#endif
|
||||
|
||||
// <q> Event input invert
|
||||
// <id> ccl_arch_invei_2
|
||||
#ifndef CONF_CCL_INVEI_2
|
||||
#define CONF_CCL_INVEI_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <hidden> Persistance settings 2
|
||||
|
||||
// <s> Expression Persistance
|
||||
// <id> ccl_e_persistance_2
|
||||
#define EXPRESSION_PERSISTANCE_2 ""
|
||||
|
||||
// <s> Logic Persistance
|
||||
// <id> ccl_l_persistance_2
|
||||
#define LOGIC_PERSISTANCE_2 ""
|
||||
|
||||
// </hidden>
|
||||
|
||||
// <e> Lookup Table Control 3
|
||||
// <i> Enable and setup the lookup table module 3
|
||||
// <id> ccl_arch_lutctrl3
|
||||
#ifndef CONF_CCL_LUTCTRL_EN_3
|
||||
#define CONF_CCL_LUTCTRL_EN_3 0
|
||||
#endif
|
||||
|
||||
// <o> Truth Table <0x00-0xFF>
|
||||
// <i> Define the value of truth logic according to inputs IN[2:0]
|
||||
// <id> ccl_arch_truth_3
|
||||
#ifndef CONF_CCL_TRUTH_3
|
||||
#define CONF_CCL_TRUTH_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> Input Source Selection 0
|
||||
// <0x0=> Masked input
|
||||
// <0x1=> Feedback input source
|
||||
// <0x2=> Linked LookUpTable input source
|
||||
// <0x3=> Event input source
|
||||
// <0x4=> IO pin input source
|
||||
// <0x5=> AC input source
|
||||
// <0x6=> TC input source
|
||||
// <0x7=> Alternative TC input source
|
||||
// <0x8=> TCC input source
|
||||
// <0x9=> SERCOM input source
|
||||
// <id> ccl_arch_insel0_3
|
||||
#ifndef CONF_CCL_INSEL0_3
|
||||
#define CONF_CCL_INSEL0_3 0x4
|
||||
#endif
|
||||
|
||||
// <o> Input Source Selection 1
|
||||
// <0x0=> Masked input
|
||||
// <0x1=> Feedback input source
|
||||
// <0x2=> Linked LookUpTable input source
|
||||
// <0x3=> Event input source
|
||||
// <0x4=> IO pin input source
|
||||
// <0x5=> AC input source
|
||||
// <0x6=> TC input source
|
||||
// <0x7=> Alternative TC input source
|
||||
// <0x8=> TCC input source
|
||||
// <0x9=> SERCOM input source
|
||||
// <id> ccl_arch_insel1_3
|
||||
#ifndef CONF_CCL_INSEL1_3
|
||||
#define CONF_CCL_INSEL1_3 0x4
|
||||
#endif
|
||||
|
||||
// <o> Input Source Selection 2
|
||||
// <0x0=> Masked input
|
||||
// <0x1=> Feedback input source
|
||||
// <0x2=> Linked LookUpTable input source
|
||||
// <0x3=> Event input source
|
||||
// <0x4=> IO pin input source
|
||||
// <0x5=> AC input source
|
||||
// <0x6=> TC input source
|
||||
// <0x7=> Alternative TC input source
|
||||
// <0x8=> TCC input source
|
||||
// <0x9=> SERCOM input source
|
||||
// <id> ccl_arch_insel2_3
|
||||
#ifndef CONF_CCL_INSEL2_3
|
||||
#define CONF_CCL_INSEL2_3 0x4
|
||||
#endif
|
||||
|
||||
// <q> Edge detector enable
|
||||
// <id> ccl_arch_edgesel_3
|
||||
#ifndef CONF_CCL_EDGESEL_3
|
||||
#define CONF_CCL_EDGESEL_3 0
|
||||
#endif
|
||||
|
||||
// <o> Output Filter
|
||||
// <0x0=> Disabled
|
||||
// <0x1=> Synchronizer Enabled
|
||||
// <0x2=> Filter Enabled
|
||||
// <id> ccl_arch_filtsel_3
|
||||
#ifndef CONF_CCL_FILTSEL_3
|
||||
#define CONF_CCL_FILTSEL_3 0x0
|
||||
#endif
|
||||
|
||||
// <h> Event settings 3
|
||||
|
||||
// <q> Event output enable
|
||||
// <id> ccl_arch_luteo_3
|
||||
#ifndef CONF_CCL_LUTEO_3
|
||||
#define CONF_CCL_LUTEO_3 0
|
||||
#endif
|
||||
|
||||
// <q> Event input enable
|
||||
// <id> ccl_arch_lutei_3
|
||||
#ifndef CONF_CCL_LUTEI_3
|
||||
#define CONF_CCL_LUTEI_3 0
|
||||
#endif
|
||||
|
||||
// <q> Event input invert
|
||||
// <id> ccl_arch_invei_3
|
||||
#ifndef CONF_CCL_INVEI_3
|
||||
#define CONF_CCL_INVEI_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <hidden> Persistance settings 3
|
||||
|
||||
// <s> Expression Persistance
|
||||
// <id> ccl_e_persistance_3
|
||||
#define EXPRESSION_PERSISTANCE_3 ""
|
||||
|
||||
// <s> Logic Persistance
|
||||
// <id> ccl_l_persistance_3
|
||||
#define LOGIC_PERSISTANCE_3 ""
|
||||
|
||||
// </hidden>
|
||||
|
||||
// <e> Advanced configurations
|
||||
// <id> ccl_arch_advanced_settings
|
||||
#ifndef CONF_CCL_ADVANCED
|
||||
#define CONF_CCL_ADVANCED 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <id> ccl_arch_runstdby
|
||||
#ifndef CONF_CCL_RUNSTDBY
|
||||
#define CONF_CCL_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_CCL_CONFIG_H
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,913 @@
|
|||
/* Auto-generated config file hpl_eic_config.h */
|
||||
#ifndef HPL_EIC_CONFIG_H
|
||||
#define HPL_EIC_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Basic Settings
|
||||
// <o> Clock Selection
|
||||
// <i> Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or
|
||||
// <i> either by CLK_ULP32K when power consumption is the priority.
|
||||
// <0x0=> Clocked by GCLK
|
||||
// <0x1=> Clocked by ULPOSC32K
|
||||
// <id> eic_arch_cksel
|
||||
#ifndef CONF_EIC_CKSEL
|
||||
#define CONF_EIC_CKSEL 0
|
||||
#endif
|
||||
|
||||
// <o> Pin Sampler frequency selection
|
||||
// <i> Indicates the sampling rate of the EXTINT pin.
|
||||
// <0x0=> The sampling rate is EIC clock
|
||||
// <0x1=> The sampling rate is the prescaled clock
|
||||
// <id> eic_arch_tickon
|
||||
#ifndef CONF_EIC_TICKON
|
||||
#define CONF_EIC_TICKON 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Non-Maskable Interrupt Control
|
||||
// <id> eic_arch_nmi_ctrl
|
||||
#ifndef CONF_EIC_ENABLE_NMI_CTRL
|
||||
#define CONF_EIC_ENABLE_NMI_CTRL 0
|
||||
#endif
|
||||
|
||||
// <q> Non-Maskable Interrupt Filter Enable
|
||||
// <i> Indicates whether the mon-maskable interrupt filter is enabled or not
|
||||
// <id> eic_arch_nmifilten
|
||||
#ifndef CONF_EIC_NMIFILTEN
|
||||
#define CONF_EIC_NMIFILTEN 0
|
||||
#endif
|
||||
|
||||
// <y> Non-Maskable Interrupt Sense
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines non-maskable interrupt sense
|
||||
// <id> eic_arch_nmisense
|
||||
#ifndef CONF_EIC_NMISENSE
|
||||
#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the interrupt detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_nmiasynch
|
||||
#ifndef CONF_EIC_NMIASYNCH
|
||||
#define CONF_EIC_NMIASYNCH 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 0 Settings
|
||||
// <id> eic_arch_enable_irq_setting0
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING0
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING0 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 0 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 0 filter is enabled or not
|
||||
// <id> eic_arch_filten0
|
||||
#ifndef CONF_EIC_FILTEN0
|
||||
#define CONF_EIC_FILTEN0 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 0 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 0 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable0
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE0
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE0 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 0 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 0 event output is enabled or not
|
||||
// <id> eic_arch_extinteo0
|
||||
#ifndef CONF_EIC_EXTINTEO0
|
||||
#define CONF_EIC_EXTINTEO0 0
|
||||
#endif
|
||||
|
||||
// <y> Input 0 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense0
|
||||
#ifndef CONF_EIC_SENSE0
|
||||
#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 0 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch0
|
||||
#ifndef CONF_EIC_ASYNCH0
|
||||
#define CONF_EIC_ASYNCH0 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 1 Settings
|
||||
// <id> eic_arch_enable_irq_setting1
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING1
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING1 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 1 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 1 filter is enabled or not
|
||||
// <id> eic_arch_filten1
|
||||
#ifndef CONF_EIC_FILTEN1
|
||||
#define CONF_EIC_FILTEN1 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 1 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 1 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable1
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE1
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE1 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 1 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 1 event output is enabled or not
|
||||
// <id> eic_arch_extinteo1
|
||||
#ifndef CONF_EIC_EXTINTEO1
|
||||
#define CONF_EIC_EXTINTEO1 0
|
||||
#endif
|
||||
|
||||
// <y> Input 1 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense1
|
||||
#ifndef CONF_EIC_SENSE1
|
||||
#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 1 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch1
|
||||
#ifndef CONF_EIC_ASYNCH1
|
||||
#define CONF_EIC_ASYNCH1 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 2 Settings
|
||||
// <id> eic_arch_enable_irq_setting2
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING2
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING2 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 2 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 2 filter is enabled or not
|
||||
// <id> eic_arch_filten2
|
||||
#ifndef CONF_EIC_FILTEN2
|
||||
#define CONF_EIC_FILTEN2 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 2 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 2 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable2
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE2
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE2 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 2 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 2 event output is enabled or not
|
||||
// <id> eic_arch_extinteo2
|
||||
#ifndef CONF_EIC_EXTINTEO2
|
||||
#define CONF_EIC_EXTINTEO2 0
|
||||
#endif
|
||||
|
||||
// <y> Input 2 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense2
|
||||
#ifndef CONF_EIC_SENSE2
|
||||
#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 2 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch2
|
||||
#ifndef CONF_EIC_ASYNCH2
|
||||
#define CONF_EIC_ASYNCH2 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 3 Settings
|
||||
// <id> eic_arch_enable_irq_setting3
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING3
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING3 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 3 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 3 filter is enabled or not
|
||||
// <id> eic_arch_filten3
|
||||
#ifndef CONF_EIC_FILTEN3
|
||||
#define CONF_EIC_FILTEN3 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 3 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 3 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable3
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE3
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE3 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 3 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 3 event output is enabled or not
|
||||
// <id> eic_arch_extinteo3
|
||||
#ifndef CONF_EIC_EXTINTEO3
|
||||
#define CONF_EIC_EXTINTEO3 0
|
||||
#endif
|
||||
|
||||
// <y> Input 3 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense3
|
||||
#ifndef CONF_EIC_SENSE3
|
||||
#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 3 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch3
|
||||
#ifndef CONF_EIC_ASYNCH3
|
||||
#define CONF_EIC_ASYNCH3 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 4 Settings
|
||||
// <id> eic_arch_enable_irq_setting4
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING4
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING4 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 4 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 4 filter is enabled or not
|
||||
// <id> eic_arch_filten4
|
||||
#ifndef CONF_EIC_FILTEN4
|
||||
#define CONF_EIC_FILTEN4 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 4 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 4 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable4
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE4
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE4 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 4 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 4 event output is enabled or not
|
||||
// <id> eic_arch_extinteo4
|
||||
#ifndef CONF_EIC_EXTINTEO4
|
||||
#define CONF_EIC_EXTINTEO4 0
|
||||
#endif
|
||||
|
||||
// <y> Input 4 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense4
|
||||
#ifndef CONF_EIC_SENSE4
|
||||
#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 4 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch4
|
||||
#ifndef CONF_EIC_ASYNCH4
|
||||
#define CONF_EIC_ASYNCH4 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 5 Settings
|
||||
// <id> eic_arch_enable_irq_setting5
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING5
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING5 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 5 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 5 filter is enabled or not
|
||||
// <id> eic_arch_filten5
|
||||
#ifndef CONF_EIC_FILTEN5
|
||||
#define CONF_EIC_FILTEN5 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 5 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 5 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable5
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE5
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE5 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 5 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 5 event output is enabled or not
|
||||
// <id> eic_arch_extinteo5
|
||||
#ifndef CONF_EIC_EXTINTEO5
|
||||
#define CONF_EIC_EXTINTEO5 0
|
||||
#endif
|
||||
|
||||
// <y> Input 5 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense5
|
||||
#ifndef CONF_EIC_SENSE5
|
||||
#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 5 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch5
|
||||
#ifndef CONF_EIC_ASYNCH5
|
||||
#define CONF_EIC_ASYNCH5 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 6 Settings
|
||||
// <id> eic_arch_enable_irq_setting6
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING6
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING6 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 6 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 6 filter is enabled or not
|
||||
// <id> eic_arch_filten6
|
||||
#ifndef CONF_EIC_FILTEN6
|
||||
#define CONF_EIC_FILTEN6 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 6 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 6 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable6
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE6
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE6 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 6 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 6 event output is enabled or not
|
||||
// <id> eic_arch_extinteo6
|
||||
#ifndef CONF_EIC_EXTINTEO6
|
||||
#define CONF_EIC_EXTINTEO6 0
|
||||
#endif
|
||||
|
||||
// <y> Input 6 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense6
|
||||
#ifndef CONF_EIC_SENSE6
|
||||
#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 6 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch6
|
||||
#ifndef CONF_EIC_ASYNCH6
|
||||
#define CONF_EIC_ASYNCH6 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 7 Settings
|
||||
// <id> eic_arch_enable_irq_setting7
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING7
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING7 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 7 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 7 filter is enabled or not
|
||||
// <id> eic_arch_filten7
|
||||
#ifndef CONF_EIC_FILTEN7
|
||||
#define CONF_EIC_FILTEN7 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 7 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 7 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable7
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE7
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE7 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 7 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 7 event output is enabled or not
|
||||
// <id> eic_arch_extinteo7
|
||||
#ifndef CONF_EIC_EXTINTEO7
|
||||
#define CONF_EIC_EXTINTEO7 0
|
||||
#endif
|
||||
|
||||
// <y> Input 7 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense7
|
||||
#ifndef CONF_EIC_SENSE7
|
||||
#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 7 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch7
|
||||
#ifndef CONF_EIC_ASYNCH7
|
||||
#define CONF_EIC_ASYNCH7 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 8 Settings
|
||||
// <id> eic_arch_enable_irq_setting8
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING8
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING8 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 8 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 8 filter is enabled or not
|
||||
// <id> eic_arch_filten8
|
||||
#ifndef CONF_EIC_FILTEN8
|
||||
#define CONF_EIC_FILTEN8 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 8 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 8 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable8
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE8
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE8 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 8 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 8 event output is enabled or not
|
||||
// <id> eic_arch_extinteo8
|
||||
#ifndef CONF_EIC_EXTINTEO8
|
||||
#define CONF_EIC_EXTINTEO8 0
|
||||
#endif
|
||||
|
||||
// <y> Input 8 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense8
|
||||
#ifndef CONF_EIC_SENSE8
|
||||
#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 8 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch8
|
||||
#ifndef CONF_EIC_ASYNCH8
|
||||
#define CONF_EIC_ASYNCH8 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 9 Settings
|
||||
// <id> eic_arch_enable_irq_setting9
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING9
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING9 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 9 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 9 filter is enabled or not
|
||||
// <id> eic_arch_filten9
|
||||
#ifndef CONF_EIC_FILTEN9
|
||||
#define CONF_EIC_FILTEN9 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 9 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 9 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable9
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE9
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE9 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 9 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 9 event output is enabled or not
|
||||
// <id> eic_arch_extinteo9
|
||||
#ifndef CONF_EIC_EXTINTEO9
|
||||
#define CONF_EIC_EXTINTEO9 0
|
||||
#endif
|
||||
|
||||
// <y> Input 9 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense9
|
||||
#ifndef CONF_EIC_SENSE9
|
||||
#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 9 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch9
|
||||
#ifndef CONF_EIC_ASYNCH9
|
||||
#define CONF_EIC_ASYNCH9 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 10 Settings
|
||||
// <id> eic_arch_enable_irq_setting10
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING10
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING10 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 10 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 10 filter is enabled or not
|
||||
// <id> eic_arch_filten10
|
||||
#ifndef CONF_EIC_FILTEN10
|
||||
#define CONF_EIC_FILTEN10 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 10 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 10 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable10
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE10
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE10 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 10 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 10 event output is enabled or not
|
||||
// <id> eic_arch_extinteo10
|
||||
#ifndef CONF_EIC_EXTINTEO10
|
||||
#define CONF_EIC_EXTINTEO10 0
|
||||
#endif
|
||||
|
||||
// <y> Input 10 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense10
|
||||
#ifndef CONF_EIC_SENSE10
|
||||
#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 10 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch10
|
||||
#ifndef CONF_EIC_ASYNCH10
|
||||
#define CONF_EIC_ASYNCH10 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 11 Settings
|
||||
// <id> eic_arch_enable_irq_setting11
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING11
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING11 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 11 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 11 filter is enabled or not
|
||||
// <id> eic_arch_filten11
|
||||
#ifndef CONF_EIC_FILTEN11
|
||||
#define CONF_EIC_FILTEN11 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 11 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 11 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable11
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE11
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE11 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 11 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 11 event output is enabled or not
|
||||
// <id> eic_arch_extinteo11
|
||||
#ifndef CONF_EIC_EXTINTEO11
|
||||
#define CONF_EIC_EXTINTEO11 0
|
||||
#endif
|
||||
|
||||
// <y> Input 11 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense11
|
||||
#ifndef CONF_EIC_SENSE11
|
||||
#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 11 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch11
|
||||
#ifndef CONF_EIC_ASYNCH11
|
||||
#define CONF_EIC_ASYNCH11 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 12 Settings
|
||||
// <id> eic_arch_enable_irq_setting12
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING12
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING12 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 12 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 12 filter is enabled or not
|
||||
// <id> eic_arch_filten12
|
||||
#ifndef CONF_EIC_FILTEN12
|
||||
#define CONF_EIC_FILTEN12 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 12 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 12 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable12
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE12
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE12 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 12 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 12 event output is enabled or not
|
||||
// <id> eic_arch_extinteo12
|
||||
#ifndef CONF_EIC_EXTINTEO12
|
||||
#define CONF_EIC_EXTINTEO12 0
|
||||
#endif
|
||||
|
||||
// <y> Input 12 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense12
|
||||
#ifndef CONF_EIC_SENSE12
|
||||
#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 12 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch12
|
||||
#ifndef CONF_EIC_ASYNCH12
|
||||
#define CONF_EIC_ASYNCH12 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 13 Settings
|
||||
// <id> eic_arch_enable_irq_setting13
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING13
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING13 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 13 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 13 filter is enabled or not
|
||||
// <id> eic_arch_filten13
|
||||
#ifndef CONF_EIC_FILTEN13
|
||||
#define CONF_EIC_FILTEN13 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 13 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 13 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable13
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE13
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE13 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 13 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 13 event output is enabled or not
|
||||
// <id> eic_arch_extinteo13
|
||||
#ifndef CONF_EIC_EXTINTEO13
|
||||
#define CONF_EIC_EXTINTEO13 0
|
||||
#endif
|
||||
|
||||
// <y> Input 13 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense13
|
||||
#ifndef CONF_EIC_SENSE13
|
||||
#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 13 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch13
|
||||
#ifndef CONF_EIC_ASYNCH13
|
||||
#define CONF_EIC_ASYNCH13 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 14 Settings
|
||||
// <id> eic_arch_enable_irq_setting14
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING14
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING14 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 14 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 14 filter is enabled or not
|
||||
// <id> eic_arch_filten14
|
||||
#ifndef CONF_EIC_FILTEN14
|
||||
#define CONF_EIC_FILTEN14 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 14 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 14 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable14
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE14
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE14 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 14 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 14 event output is enabled or not
|
||||
// <id> eic_arch_extinteo14
|
||||
#ifndef CONF_EIC_EXTINTEO14
|
||||
#define CONF_EIC_EXTINTEO14 0
|
||||
#endif
|
||||
|
||||
// <y> Input 14 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense14
|
||||
#ifndef CONF_EIC_SENSE14
|
||||
#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 14 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch14
|
||||
#ifndef CONF_EIC_ASYNCH14
|
||||
#define CONF_EIC_ASYNCH14 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 15 Settings
|
||||
// <id> eic_arch_enable_irq_setting15
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING15
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING15 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 15 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 15 filter is enabled or not
|
||||
// <id> eic_arch_filten15
|
||||
#ifndef CONF_EIC_FILTEN15
|
||||
#define CONF_EIC_FILTEN15 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 15 Debounce Enable
|
||||
// <i> Indicates whether the external interrupt 15 debounce is enabled or not
|
||||
// <id> eic_arch_debounce_enable15
|
||||
#ifndef CONF_EIC_DEBOUNCE_ENABLE15
|
||||
#define CONF_EIC_DEBOUNCE_ENABLE15 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 15 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 15 event output is enabled or not
|
||||
// <id> eic_arch_extinteo15
|
||||
#ifndef CONF_EIC_EXTINTEO15
|
||||
#define CONF_EIC_EXTINTEO15 0
|
||||
#endif
|
||||
|
||||
// <y> Input 15 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense15
|
||||
#ifndef CONF_EIC_SENSE15
|
||||
#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 15 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch15
|
||||
#ifndef CONF_EIC_ASYNCH15
|
||||
#define CONF_EIC_ASYNCH15 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <h> Debouncer 0 Settings
|
||||
// <o> Debouncer Frequency Selection
|
||||
// <0x0=>Divided by 2
|
||||
// <0x1=>Divided by 4
|
||||
// <0x2=>Divided by 8
|
||||
// <0x3=>Divided by 16
|
||||
// <0x4=>Divided by 32
|
||||
// <0x5=>Divided by 64
|
||||
// <0x6=>Divided by 128
|
||||
// <0x7=>Divided by 256
|
||||
// <i> Select the debouncer low frequency clock for pins
|
||||
|
||||
// <i> EXTINT[7:0].
|
||||
|
||||
// <id> eic_arch_prescaler0
|
||||
#ifndef CONF_EIC_DPRESCALER0
|
||||
#define CONF_EIC_DPRESCALER0 EIC_DPRESCALER_PRESCALER0(0x0)
|
||||
#endif
|
||||
|
||||
// <o> Low frequency samples
|
||||
// <0x0=>3
|
||||
// <0x1=>7
|
||||
// <i> Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from
|
||||
// <i> current pin state to next pin state in synchronous debouncing mode.
|
||||
// <id> eic_arch_states0
|
||||
#ifndef CONF_EIC_STATES0
|
||||
#define CONF_EIC_STATES0 0x0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h> Debouncer 1 Settings
|
||||
// <o> Debouncer Frequency Selection
|
||||
// <0x0=>Divided by 2
|
||||
// <0x1=>Divided by 4
|
||||
// <0x2=>Divided by 8
|
||||
// <0x3=>Divided by 16
|
||||
// <0x4=>Divided by 32
|
||||
// <0x5=>Divided by 64
|
||||
// <0x6=>Divided by 128
|
||||
// <0x7=>Divided by 256
|
||||
// <i> Select the debouncer low frequency clock for pins
|
||||
|
||||
// <i> EXTINT[15:8].
|
||||
|
||||
// <id> eic_arch_prescaler1
|
||||
#ifndef CONF_EIC_DPRESCALER1
|
||||
#define CONF_EIC_DPRESCALER1 EIC_DPRESCALER_PRESCALER1(0x0)
|
||||
#endif
|
||||
|
||||
// <o> Low frequency samples
|
||||
// <0x0=>3
|
||||
// <0x1=>7
|
||||
// <i> Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from
|
||||
// <i> current pin state to next pin state in synchronous debouncing mode.
|
||||
// <id> eic_arch_states1
|
||||
#ifndef CONF_EIC_STATES1
|
||||
#define CONF_EIC_STATES1 0x0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
#define CONFIG_EIC_EXTINT_MAP {7, PIN_PA07}, {14, PIN_PB30}, {15, PIN_PB31},
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_EIC_CONFIG_H
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,640 @@
|
|||
/* Auto-generated config file hpl_oscctrl_config.h */
|
||||
#ifndef HPL_OSCCTRL_CONFIG_H
|
||||
#define HPL_OSCCTRL_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> External Multipurpose Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for XOSC0 is enabled or not
|
||||
// <id> enable_xosc0
|
||||
#ifndef CONF_XOSC0_CONFIG
|
||||
#define CONF_XOSC0_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <o> Frequency <8000000-48000000>
|
||||
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
|
||||
// <id> xosc0_frequency
|
||||
#ifndef CONF_XOSC_FREQUENCY
|
||||
#define CONF_XOSC0_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
// <h> External Multipurpose Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
|
||||
// <id> xosc0_arch_enable
|
||||
#ifndef CONF_XOSC0_ENABLE
|
||||
#define CONF_XOSC0_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>31us
|
||||
// <0x1=>61us
|
||||
// <0x2=>122us
|
||||
// <0x3=>244us
|
||||
// <0x4=>488us
|
||||
// <0x5=>977us
|
||||
// <0x6=>1953us
|
||||
// <0x7=>3906us
|
||||
// <0x8=>7813us
|
||||
// <0x9=>15625us
|
||||
// <0xA=>31250us
|
||||
// <0xB=>62500us
|
||||
// <0xC=>125000us
|
||||
// <0xD=>250000us
|
||||
// <0xE=>500000us
|
||||
// <0xF=>1000000us
|
||||
// <id> xosc0_arch_startup
|
||||
#ifndef CONF_XOSC0_STARTUP
|
||||
#define CONF_XOSC0_STARTUP 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc0_arch_swben
|
||||
#ifndef CONF_XOSC0_SWBEN
|
||||
#define CONF_XOSC0_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc0_arch_cfden
|
||||
#ifndef CONF_XOSC0_CFDEN
|
||||
#define CONF_XOSC0_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Automatic Loop Control Enable
|
||||
// <i> Indicates whether Automatic Loop Control is enabled or not
|
||||
// <id> xosc0_arch_enalc
|
||||
#ifndef CONF_XOSC0_ENALC
|
||||
#define CONF_XOSC0_ENALC 0
|
||||
#endif
|
||||
|
||||
// <q> Low Buffer Gain Enable
|
||||
// <i> Indicates whether Low Buffer Gain is enabled or not
|
||||
// <id> xosc0_arch_lowbufgain
|
||||
#ifndef CONF_XOSC0_LOWBUFGAIN
|
||||
#define CONF_XOSC0_LOWBUFGAIN 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc0_arch_ondemand
|
||||
#ifndef CONF_XOSC0_ONDEMAND
|
||||
#define CONF_XOSC0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc0_arch_runstdby
|
||||
#ifndef CONF_XOSC0_RUNSTDBY
|
||||
#define CONF_XOSC0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN/XOUT Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc0_arch_xtalen
|
||||
#ifndef CONF_XOSC0_XTALEN
|
||||
#define CONF_XOSC0_XTALEN 0
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
#if CONF_XOSC0_FREQUENCY >= 32000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x0
|
||||
#define CONF_XOSC0_IMULT 0x7
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 24000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x1
|
||||
#define CONF_XOSC0_IMULT 0x6
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 16000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x2
|
||||
#define CONF_XOSC0_IMULT 0x5
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 8000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x3
|
||||
#define CONF_XOSC0_IMULT 0x4
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#endif
|
||||
|
||||
// <e> External Multipurpose Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for XOSC1 is enabled or not
|
||||
// <id> enable_xosc1
|
||||
#ifndef CONF_XOSC1_CONFIG
|
||||
#define CONF_XOSC1_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <o> Frequency <8000000-48000000>
|
||||
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
|
||||
// <id> xosc1_frequency
|
||||
#ifndef CONF_XOSC_FREQUENCY
|
||||
#define CONF_XOSC1_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
// <h> External Multipurpose Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
|
||||
// <id> xosc1_arch_enable
|
||||
#ifndef CONF_XOSC1_ENABLE
|
||||
#define CONF_XOSC1_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>31us
|
||||
// <0x1=>61us
|
||||
// <0x2=>122us
|
||||
// <0x3=>244us
|
||||
// <0x4=>488us
|
||||
// <0x5=>977us
|
||||
// <0x6=>1953us
|
||||
// <0x7=>3906us
|
||||
// <0x8=>7813us
|
||||
// <0x9=>15625us
|
||||
// <0xA=>31250us
|
||||
// <0xB=>62500us
|
||||
// <0xC=>125000us
|
||||
// <0xD=>250000us
|
||||
// <0xE=>500000us
|
||||
// <0xF=>1000000us
|
||||
// <id> xosc1_arch_startup
|
||||
#ifndef CONF_XOSC1_STARTUP
|
||||
#define CONF_XOSC1_STARTUP 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc1_arch_swben
|
||||
#ifndef CONF_XOSC1_SWBEN
|
||||
#define CONF_XOSC1_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc1_arch_cfden
|
||||
#ifndef CONF_XOSC1_CFDEN
|
||||
#define CONF_XOSC1_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Automatic Loop Control Enable
|
||||
// <i> Indicates whether Automatic Loop Control is enabled or not
|
||||
// <id> xosc1_arch_enalc
|
||||
#ifndef CONF_XOSC1_ENALC
|
||||
#define CONF_XOSC1_ENALC 0
|
||||
#endif
|
||||
|
||||
// <q> Low Buffer Gain Enable
|
||||
// <i> Indicates whether Low Buffer Gain is enabled or not
|
||||
// <id> xosc1_arch_lowbufgain
|
||||
#ifndef CONF_XOSC1_LOWBUFGAIN
|
||||
#define CONF_XOSC1_LOWBUFGAIN 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc1_arch_ondemand
|
||||
#ifndef CONF_XOSC1_ONDEMAND
|
||||
#define CONF_XOSC1_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc1_arch_runstdby
|
||||
#ifndef CONF_XOSC1_RUNSTDBY
|
||||
#define CONF_XOSC1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN/XOUT Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc1_arch_xtalen
|
||||
#ifndef CONF_XOSC1_XTALEN
|
||||
#define CONF_XOSC1_XTALEN 1
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
#if CONF_XOSC1_FREQUENCY >= 32000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x0
|
||||
#define CONF_XOSC1_IMULT 0x7
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 24000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x1
|
||||
#define CONF_XOSC1_IMULT 0x6
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 16000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x2
|
||||
#define CONF_XOSC1_IMULT 0x5
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 8000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x3
|
||||
#define CONF_XOSC1_IMULT 0x4
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#endif
|
||||
|
||||
// <e> DFLL Configuration
|
||||
// <i> Indicates whether configuration for DFLL is enabled or not
|
||||
// <id> enable_dfll
|
||||
#ifndef CONF_DFLL_CONFIG
|
||||
#define CONF_DFLL_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source
|
||||
// <id> dfll_ref_clock
|
||||
#ifndef CONF_DFLL_GCLK
|
||||
#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK2_Val
|
||||
#endif
|
||||
|
||||
// <h> Digital Frequency Locked Loop Control
|
||||
// <q> DFLL Enable
|
||||
// <i> Indicates whether DFLL is enabled or not
|
||||
// <id> dfll_arch_enable
|
||||
#ifndef CONF_DFLL_ENABLE
|
||||
#define CONF_DFLL_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> dfll_arch_ondemand
|
||||
#ifndef CONF_DFLL_ONDEMAND
|
||||
#define CONF_DFLL_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> dfll_arch_runstdby
|
||||
#ifndef CONF_DFLL_RUNSTDBY
|
||||
#define CONF_DFLL_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> USB Clock Recovery Mode
|
||||
// <i> Indicates whether USB Clock Recovery Mode is enabled or not
|
||||
// <id> dfll_arch_usbcrm
|
||||
#ifndef CONF_DFLL_USBCRM
|
||||
#define CONF_DFLL_USBCRM 0
|
||||
#endif
|
||||
|
||||
// <q> Wait Lock
|
||||
// <i> Indicates whether Wait Lock is enabled or not
|
||||
// <id> dfll_arch_waitlock
|
||||
#ifndef CONF_DFLL_WAITLOCK
|
||||
#define CONF_DFLL_WAITLOCK 1
|
||||
#endif
|
||||
|
||||
// <q> Bypass Coarse Lock
|
||||
// <i> Indicates whether Bypass Coarse Lock is enabled or not
|
||||
// <id> dfll_arch_bplckc
|
||||
#ifndef CONF_DFLL_BPLCKC
|
||||
#define CONF_DFLL_BPLCKC 0
|
||||
#endif
|
||||
|
||||
// <q> Quick Lock Disable
|
||||
// <i> Indicates whether Quick Lock Disable is enabled or not
|
||||
// <id> dfll_arch_qldis
|
||||
#ifndef CONF_DFLL_QLDIS
|
||||
#define CONF_DFLL_QLDIS 0
|
||||
#endif
|
||||
|
||||
// <q> Chill Cycle Disable
|
||||
// <i> Indicates whether Chill Cycle Disable is enabled or not
|
||||
// <id> dfll_arch_ccdis
|
||||
#ifndef CONF_DFLL_CCDIS
|
||||
#define CONF_DFLL_CCDIS 0
|
||||
#endif
|
||||
|
||||
// <q> Lose Lock After Wake
|
||||
// <i> Indicates whether Lose Lock After Wake is enabled or not
|
||||
// <id> dfll_arch_llaw
|
||||
#ifndef CONF_DFLL_LLAW
|
||||
#define CONF_DFLL_LLAW 0
|
||||
#endif
|
||||
|
||||
// <q> Stable DFLL Frequency
|
||||
// <i> Indicates whether Stable DFLL Frequency is enabled or not
|
||||
// <id> dfll_arch_stable
|
||||
#ifndef CONF_DFLL_STABLE
|
||||
#define CONF_DFLL_STABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Operating Mode Selection
|
||||
// <0=>Open Loop Mode
|
||||
// <1=>Closed Loop Mode
|
||||
// <id> dfll_mode
|
||||
#ifndef CONF_DFLL_MODE
|
||||
#define CONF_DFLL_MODE 0x0
|
||||
#endif
|
||||
|
||||
// <o> Coarse Maximum Step <0x0-0x1F>
|
||||
// <id> dfll_arch_cstep
|
||||
#ifndef CONF_DFLL_CSTEP
|
||||
#define CONF_DFLL_CSTEP 0x1
|
||||
#endif
|
||||
|
||||
// <o> Fine Maximum Step <0x0-0xFF>
|
||||
// <id> dfll_arch_fstep
|
||||
#ifndef CONF_DFLL_FSTEP
|
||||
#define CONF_DFLL_FSTEP 0x1
|
||||
#endif
|
||||
|
||||
// <o> DFLL Multiply Factor <0x0-0xFFFF>
|
||||
// <id> dfll_mul
|
||||
#ifndef CONF_DFLL_MUL
|
||||
#define CONF_DFLL_MUL 0x0
|
||||
#endif
|
||||
|
||||
// <e> DFLL Calibration Overwrite
|
||||
// <i> Indicates whether Overwrite Calibration value of DFLL
|
||||
// <id> dfll_arch_calibration
|
||||
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
|
||||
#define CONF_DFLL_OVERWRITE_CALIBRATION 0
|
||||
#endif
|
||||
|
||||
// <o> Coarse Value <0x0-0x3F>
|
||||
// <id> dfll_arch_coarse
|
||||
#ifndef CONF_DFLL_COARSE
|
||||
#define CONF_DFLL_COARSE (0x1f / 4)
|
||||
#endif
|
||||
|
||||
// <o> Fine Value <0x0-0xFF>
|
||||
// <id> dfll_arch_fine
|
||||
#ifndef CONF_DFLL_FINE
|
||||
#define CONF_DFLL_FINE (0x80)
|
||||
#endif
|
||||
|
||||
//</e>
|
||||
|
||||
//</h>
|
||||
|
||||
//</e>
|
||||
|
||||
// <e> FDPLL0 Configuration
|
||||
// <i> Indicates whether configuration for FDPLL0 is enabled or not
|
||||
// <id> enable_fdpll0
|
||||
#ifndef CONF_FDPLL0_CONFIG
|
||||
#define CONF_FDPLL0_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source.
|
||||
// <id> fdpll0_ref_clock
|
||||
#ifndef CONF_FDPLL0_GCLK
|
||||
#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <h> Digital Phase Locked Loop Control
|
||||
// <q> Enable
|
||||
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
|
||||
// <id> fdpll0_arch_enable
|
||||
#ifndef CONF_FDPLL0_ENABLE
|
||||
#define CONF_FDPLL0_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> fdpll0_arch_ondemand
|
||||
#ifndef CONF_FDPLL0_ONDEMAND
|
||||
#define CONF_FDPLL0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> fdpll0_arch_runstdby
|
||||
#ifndef CONF_FDPLL0_RUNSTDBY
|
||||
#define CONF_FDPLL0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
|
||||
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll0_ldrfrac
|
||||
#ifndef CONF_FDPLL0_LDRFRAC
|
||||
#define CONF_FDPLL0_LDRFRAC 0xd
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
|
||||
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll0_ldr
|
||||
#ifndef CONF_FDPLL0_LDR
|
||||
#define CONF_FDPLL0_LDR 0x5b7
|
||||
#endif
|
||||
|
||||
// <o> Clock Divider <0x0-0x7FF>
|
||||
// <i> This Clock divider is only for XOSC clock input to DPLL
|
||||
// <id> fdpll0_clock_div
|
||||
#ifndef CONF_FDPLL0_DIV
|
||||
#define CONF_FDPLL0_DIV 0x0
|
||||
#endif
|
||||
|
||||
// <q> DCO Filter Enable
|
||||
// <i> Indicates whether DCO Filter Enable is enabled or not
|
||||
// <id> fdpll0_arch_dcoen
|
||||
#ifndef CONF_FDPLL0_DCOEN
|
||||
#define CONF_FDPLL0_DCOEN 0
|
||||
#endif
|
||||
|
||||
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
|
||||
// <id> fdpll0_clock_dcofilter
|
||||
#ifndef CONF_FDPLL0_DCOFILTER
|
||||
#define CONF_FDPLL0_DCOFILTER 0x0
|
||||
#endif
|
||||
|
||||
// <q> Lock Bypass
|
||||
// <i> Indicates whether Lock Bypass is enabled or not
|
||||
// <id> fdpll0_arch_lbypass
|
||||
#ifndef CONF_FDPLL0_LBYPASS
|
||||
#define CONF_FDPLL0_LBYPASS 0
|
||||
#endif
|
||||
|
||||
// <o> Lock Time
|
||||
// <0x0=>No time-out, automatic lock
|
||||
// <0x4=>The Time-out if no lock within 800 us
|
||||
// <0x5=>The Time-out if no lock within 900 us
|
||||
// <0x6=>The Time-out if no lock within 1 ms
|
||||
// <0x7=>The Time-out if no lock within 11 ms
|
||||
// <id> fdpll0_arch_ltime
|
||||
#ifndef CONF_FDPLL0_LTIME
|
||||
#define CONF_FDPLL0_LTIME 0x0
|
||||
#endif
|
||||
|
||||
// <o> Reference Clock Selection
|
||||
// <0x0=>GCLK clock reference
|
||||
// <0x1=>XOSC32K clock reference
|
||||
// <0x2=>XOSC0 clock reference
|
||||
// <0x3=>XOSC1 clock reference
|
||||
// <id> fdpll0_arch_refclk
|
||||
#ifndef CONF_FDPLL0_REFCLK
|
||||
#define CONF_FDPLL0_REFCLK 0x1
|
||||
#endif
|
||||
|
||||
// <q> Wake Up Fast
|
||||
// <i> Indicates whether Wake Up Fast is enabled or not
|
||||
// <id> fdpll0_arch_wuf
|
||||
#ifndef CONF_FDPLL0_WUF
|
||||
#define CONF_FDPLL0_WUF 0
|
||||
#endif
|
||||
|
||||
// <o> Proportional Integral Filter Selection <0x0-0xF>
|
||||
// <id> fdpll0_arch_filter
|
||||
#ifndef CONF_FDPLL0_FILTER
|
||||
#define CONF_FDPLL0_FILTER 0x0
|
||||
#endif
|
||||
|
||||
//</h>
|
||||
//</e>
|
||||
// <e> FDPLL1 Configuration
|
||||
// <i> Indicates whether configuration for FDPLL1 is enabled or not
|
||||
// <id> enable_fdpll1
|
||||
#ifndef CONF_FDPLL1_CONFIG
|
||||
#define CONF_FDPLL1_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source.
|
||||
// <id> fdpll1_ref_clock
|
||||
#ifndef CONF_FDPLL1_GCLK
|
||||
#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK1_Val
|
||||
#endif
|
||||
|
||||
// <h> Digital Phase Locked Loop Control
|
||||
// <q> Enable
|
||||
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
|
||||
// <id> fdpll1_arch_enable
|
||||
#ifndef CONF_FDPLL1_ENABLE
|
||||
#define CONF_FDPLL1_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> fdpll1_arch_ondemand
|
||||
#ifndef CONF_FDPLL1_ONDEMAND
|
||||
#define CONF_FDPLL1_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> fdpll1_arch_runstdby
|
||||
#ifndef CONF_FDPLL1_RUNSTDBY
|
||||
#define CONF_FDPLL1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
|
||||
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll1_ldrfrac
|
||||
#ifndef CONF_FDPLL1_LDRFRAC
|
||||
#define CONF_FDPLL1_LDRFRAC 0x0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
|
||||
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll1_ldr
|
||||
#ifndef CONF_FDPLL1_LDR
|
||||
#define CONF_FDPLL1_LDR 0x3b
|
||||
#endif
|
||||
|
||||
// <o> Clock Divider <0x0-0x7FF>
|
||||
// <i> This Clock divider is only for XOSC clock input to DPLL
|
||||
// <id> fdpll1_clock_div
|
||||
#ifndef CONF_FDPLL1_DIV
|
||||
#define CONF_FDPLL1_DIV 0x0
|
||||
#endif
|
||||
|
||||
// <q> DCO Filter Enable
|
||||
// <i> Indicates whether DCO Filter Enable is enabled or not
|
||||
// <id> fdpll1_arch_dcoen
|
||||
#ifndef CONF_FDPLL1_DCOEN
|
||||
#define CONF_FDPLL1_DCOEN 0
|
||||
#endif
|
||||
|
||||
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
|
||||
// <id> fdpll1_clock_dcofilter
|
||||
#ifndef CONF_FDPLL1_DCOFILTER
|
||||
#define CONF_FDPLL1_DCOFILTER 0x0
|
||||
#endif
|
||||
|
||||
// <q> Lock Bypass
|
||||
// <i> Indicates whether Lock Bypass is enabled or not
|
||||
// <id> fdpll1_arch_lbypass
|
||||
#ifndef CONF_FDPLL1_LBYPASS
|
||||
#define CONF_FDPLL1_LBYPASS 0
|
||||
#endif
|
||||
|
||||
// <o> Lock Time
|
||||
// <0x0=>No time-out, automatic lock
|
||||
// <0x4=>The Time-out if no lock within 800 us
|
||||
// <0x5=>The Time-out if no lock within 900 us
|
||||
// <0x6=>The Time-out if no lock within 1 ms
|
||||
// <0x7=>The Time-out if no lock within 11 ms
|
||||
// <id> fdpll1_arch_ltime
|
||||
#ifndef CONF_FDPLL1_LTIME
|
||||
#define CONF_FDPLL1_LTIME 0x0
|
||||
#endif
|
||||
|
||||
// <o> Reference Clock Selection
|
||||
// <0x0=>GCLK clock reference
|
||||
// <0x1=>XOSC32K clock reference
|
||||
// <0x2=>XOSC0 clock reference
|
||||
// <0x3=>XOSC1 clock reference
|
||||
// <id> fdpll1_arch_refclk
|
||||
#ifndef CONF_FDPLL1_REFCLK
|
||||
#define CONF_FDPLL1_REFCLK 0x0
|
||||
#endif
|
||||
|
||||
// <q> Wake Up Fast
|
||||
// <i> Indicates whether Wake Up Fast is enabled or not
|
||||
// <id> fdpll1_arch_wuf
|
||||
#ifndef CONF_FDPLL1_WUF
|
||||
#define CONF_FDPLL1_WUF 0
|
||||
#endif
|
||||
|
||||
// <o> Proportional Integral Filter Selection <0x0-0xF>
|
||||
// <id> fdpll1_arch_filter
|
||||
#ifndef CONF_FDPLL1_FILTER
|
||||
#define CONF_FDPLL1_FILTER 0x0
|
||||
#endif
|
||||
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_OSCCTRL_CONFIG_H
|
||||
|
|
@ -0,0 +1,284 @@
|
|||
/* Auto-generated config file hpl_port_config.h */
|
||||
#ifndef HPL_PORT_CONFIG_H
|
||||
#define HPL_PORT_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> PORT Input Event 0 configuration
|
||||
// <id> enable_port_input_event_0
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_0
|
||||
#define CONF_PORT_EVCTRL_PORT_0 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 0 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
|
||||
// <id> porta_input_event_enable_0
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_0
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_0
|
||||
#define CONF_PORTA_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 0
|
||||
// <id> porta_event_action_0
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_0
|
||||
#define CONF_PORTA_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
|
||||
// <id> portb_input_event_enable_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_0
|
||||
#define CONF_PORTB_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 0
|
||||
// <id> portb_event_action_0
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_0
|
||||
#define CONF_PORTB_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 1 configuration
|
||||
// <id> enable_port_input_event_1
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_1
|
||||
#define CONF_PORT_EVCTRL_PORT_1 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 1 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
|
||||
// <id> porta_input_event_enable_1
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_1
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_1
|
||||
#define CONF_PORTA_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 1
|
||||
// <id> porta_event_action_1
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_1
|
||||
#define CONF_PORTA_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
|
||||
// <id> portb_input_event_enable_1
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_1
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_1
|
||||
#define CONF_PORTB_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 1
|
||||
// <id> portb_event_action_1
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_1
|
||||
#define CONF_PORTB_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 2 configuration
|
||||
// <id> enable_port_input_event_2
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_2
|
||||
#define CONF_PORT_EVCTRL_PORT_2 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 2 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
|
||||
// <id> porta_input_event_enable_2
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_2
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_2
|
||||
#define CONF_PORTA_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 2
|
||||
// <id> porta_event_action_2
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_2
|
||||
#define CONF_PORTA_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
|
||||
// <id> portb_input_event_enable_2
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_2
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_2
|
||||
#define CONF_PORTB_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 2
|
||||
// <id> portb_event_action_2
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_2
|
||||
#define CONF_PORTB_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 3 configuration
|
||||
// <id> enable_port_input_event_3
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_3
|
||||
#define CONF_PORT_EVCTRL_PORT_3 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 3 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
|
||||
// <id> porta_input_event_enable_3
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_3
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_3
|
||||
#define CONF_PORTA_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 3
|
||||
// <id> porta_event_action_3
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_3
|
||||
#define CONF_PORTA_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
|
||||
// <id> portb_input_event_enable_3
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_3
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_3
|
||||
#define CONF_PORTB_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 3
|
||||
// <id> portb_event_action_3
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_3
|
||||
#define CONF_PORTB_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
#define CONF_PORTA_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
|
||||
#define CONF_PORTB_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_PORT_CONFIG_H
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/* Auto-generated config file hpl_qspi_config.h */
|
||||
#ifndef HPL_QSPI_CONFIG_H
|
||||
#define HPL_QSPI_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// <h> Basic settings
|
||||
|
||||
#ifndef CONF_CONF_QSPI_ENABLE
|
||||
#define CONF_CONF_QSPI_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o> Baud rate <1-150000000>
|
||||
// <i> The SPI data transfer rate. Note: (fqspi_clock / baudrate) < 255
|
||||
// <id> qspi_baud_rate
|
||||
#ifndef CONF_QSPI_BAUD
|
||||
#define CONF_QSPI_BAUD 6000000
|
||||
#endif
|
||||
|
||||
// <o> Clock Polarity
|
||||
// <0x0=>The inactive state value of SPCK is logic level zero.
|
||||
// <0x1=>The inactive state value of SPCK is logic level one.
|
||||
// <i> Determines the inactive state value of the serial clock (SPCK).
|
||||
// <id> qspi_cpol
|
||||
#ifndef CONF_QSPI_CPOL
|
||||
#define CONF_QSPI_CPOL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Phase
|
||||
// <0x0=>Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
|
||||
// <0x1=>Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
|
||||
// <i> Determines which edge of SPCK causes data to change and which edge causes data to be captured.
|
||||
// <id> qspi_cpha
|
||||
#ifndef CONF_QSPI_CPHA
|
||||
#define CONF_QSPI_CPHA 0x0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> qspi_advanced
|
||||
#ifndef CONF_QSPI_ADVANCED
|
||||
#define CONF_QSPI_ADVANCED 0
|
||||
#endif
|
||||
|
||||
// <o> Delay Before QSCK (ns) <0-255000>
|
||||
// <i> This field defines the delay from QCS falling edge (activation) to the first valid QSCK transition (in ns).
|
||||
// <id> qspi_dlybs
|
||||
#ifndef CONF_QSPI_DLY_BS
|
||||
#define CONF_QSPI_DLY_BS 0
|
||||
#endif
|
||||
|
||||
// <o> Minimum Inactive QCS Delay (ns) <0-8160000>
|
||||
// <i> This field defines the minimum delay between the deactivation and the activation of QCS (in ns).
|
||||
// <id> qspi_dlycs
|
||||
#ifndef CONF_QSPI_DLY_CS
|
||||
#define CONF_QSPI_DLY_CS 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
/* Calculate baud register value from requested baudrate value */
|
||||
#ifndef CONF_QSPI_BAUD_RATE
|
||||
#define CONF_QSPI_BAUD_RATE ((CONF_CPU_FREQUENCY / CONF_QSPI_BAUD) - 1)
|
||||
#if CONF_QSPI_BAUD > CONF_CPU_FREQUENCY || CONF_QSPI_BAUD_RATE > 255
|
||||
#warning Invalid baudrate, please check.
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Calculates the value of the CSR DLYCS field given the desired delay (in ns) */
|
||||
#ifndef CONF_QSPI_DLYCS
|
||||
#define CONF_QSPI_DLYCS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_CS) / 1000)
|
||||
#endif
|
||||
|
||||
/* Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
|
||||
#ifndef CONF_QSPI_DLYBS
|
||||
#define CONF_QSPI_DLYBS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_BS) / 1000)
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_QSPI_CONFIG_H
|
||||
|
|
@ -0,0 +1,486 @@
|
|||
/* Auto-generated config file hpl_sercom_config.h */
|
||||
#ifndef HPL_SERCOM_CONFIG_H
|
||||
#define HPL_SERCOM_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// Enable configuration of module
|
||||
#ifndef CONF_SERCOM_1_SPI_ENABLE
|
||||
#define CONF_SERCOM_1_SPI_ENABLE 1
|
||||
#endif
|
||||
|
||||
// Set module in SPI Master mode
|
||||
#ifndef CONF_SERCOM_1_SPI_MODE
|
||||
#define CONF_SERCOM_1_SPI_MODE 0x03
|
||||
#endif
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <q> Receive buffer enable
|
||||
// <i> Enable receive buffer to receive data from slave (RXEN)
|
||||
// <id> spi_master_rx_enable
|
||||
#ifndef CONF_SERCOM_1_SPI_RXEN
|
||||
#define CONF_SERCOM_1_SPI_RXEN 0x1
|
||||
#endif
|
||||
|
||||
// <o> Character Size
|
||||
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
|
||||
// <0x0=>8 bits
|
||||
// <0x1=>9 bits
|
||||
// <id> spi_master_character_size
|
||||
#ifndef CONF_SERCOM_1_SPI_CHSIZE
|
||||
#define CONF_SERCOM_1_SPI_CHSIZE 0x0
|
||||
#endif
|
||||
// <o> Baud rate <1-18000000>
|
||||
// <i> The SPI data transfer rate
|
||||
// <id> spi_master_baud_rate
|
||||
#ifndef CONF_SERCOM_1_SPI_BAUD
|
||||
#define CONF_SERCOM_1_SPI_BAUD 50000
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> spi_master_advanced
|
||||
#ifndef CONF_SERCOM_1_SPI_ADVANCED
|
||||
#define CONF_SERCOM_1_SPI_ADVANCED 0
|
||||
#endif
|
||||
|
||||
// <o> Dummy byte <0x00-0x1ff>
|
||||
// <id> spi_master_dummybyte
|
||||
// <i> Dummy byte used when reading data from the slave without sending any data
|
||||
#ifndef CONF_SERCOM_1_SPI_DUMMYBYTE
|
||||
#define CONF_SERCOM_1_SPI_DUMMYBYTE 0x1ff
|
||||
#endif
|
||||
|
||||
// <o> Data Order
|
||||
// <0=>MSB first
|
||||
// <1=>LSB first
|
||||
// <i> I least significant or most significant bit is shifted out first (DORD)
|
||||
// <id> spi_master_arch_dord
|
||||
#ifndef CONF_SERCOM_1_SPI_DORD
|
||||
#define CONF_SERCOM_1_SPI_DORD 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Polarity
|
||||
// <0=>SCK is low when idle
|
||||
// <1=>SCK is high when idle
|
||||
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
|
||||
// <id> spi_master_arch_cpol
|
||||
#ifndef CONF_SERCOM_1_SPI_CPOL
|
||||
#define CONF_SERCOM_1_SPI_CPOL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Phase
|
||||
// <0x0=>Sample input on leading edge
|
||||
// <0x1=>Sample input on trailing edge
|
||||
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
|
||||
// <id> spi_master_arch_cpha
|
||||
#ifndef CONF_SERCOM_1_SPI_CPHA
|
||||
#define CONF_SERCOM_1_SPI_CPHA 0x0
|
||||
#endif
|
||||
|
||||
// <o> Immediate Buffer Overflow Notification
|
||||
// <i> Controls when OVF is asserted (IBON)
|
||||
// <0x0=>In data stream
|
||||
// <0x1=>On buffer overflow
|
||||
// <id> spi_master_arch_ibon
|
||||
#ifndef CONF_SERCOM_1_SPI_IBON
|
||||
#define CONF_SERCOM_1_SPI_IBON 0x0
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
|
||||
// <id> spi_master_arch_runstdby
|
||||
#ifndef CONF_SERCOM_1_SPI_RUNSTDBY
|
||||
#define CONF_SERCOM_1_SPI_RUNSTDBY 0x0
|
||||
#endif
|
||||
|
||||
// <o> Debug Stop Mode
|
||||
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
|
||||
// <0=>Keep running
|
||||
// <1=>Halt
|
||||
// <id> spi_master_arch_dbgstop
|
||||
#ifndef CONF_SERCOM_1_SPI_DBGSTOP
|
||||
#define CONF_SERCOM_1_SPI_DBGSTOP 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// Address mode disabled in master mode
|
||||
#ifndef CONF_SERCOM_1_SPI_AMODE_EN
|
||||
#define CONF_SERCOM_1_SPI_AMODE_EN 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_1_SPI_AMODE
|
||||
#define CONF_SERCOM_1_SPI_AMODE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_1_SPI_ADDR
|
||||
#define CONF_SERCOM_1_SPI_ADDR 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_1_SPI_ADDRMASK
|
||||
#define CONF_SERCOM_1_SPI_ADDRMASK 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_1_SPI_SSDE
|
||||
#define CONF_SERCOM_1_SPI_SSDE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_1_SPI_MSSEN
|
||||
#define CONF_SERCOM_1_SPI_MSSEN 0x0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_1_SPI_PLOADEN
|
||||
#define CONF_SERCOM_1_SPI_PLOADEN 0
|
||||
#endif
|
||||
|
||||
// <o> Receive Data Pinout
|
||||
// <0x0=>PAD[0]
|
||||
// <0x1=>PAD[1]
|
||||
// <0x2=>PAD[2]
|
||||
// <0x3=>PAD[3]
|
||||
// <id> spi_master_rxpo
|
||||
#ifndef CONF_SERCOM_1_SPI_RXPO
|
||||
#define CONF_SERCOM_1_SPI_RXPO 3
|
||||
#endif
|
||||
|
||||
// <o> Transmit Data Pinout
|
||||
// <0x0=>PAD[0,1]_DO_SCK
|
||||
// <0x1=>PAD[2,3]_DO_SCK
|
||||
// <0x2=>PAD[3,1]_DO_SCK
|
||||
// <0x3=>PAD[0,3]_DO_SCK
|
||||
// <id> spi_master_txpo
|
||||
#ifndef CONF_SERCOM_1_SPI_TXPO
|
||||
#define CONF_SERCOM_1_SPI_TXPO 0
|
||||
#endif
|
||||
|
||||
// Calculate baud register value from requested baudrate value
|
||||
#ifndef CONF_SERCOM_1_SPI_BAUD_RATE
|
||||
#define CONF_SERCOM_1_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM1_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_1_SPI_BAUD)) - 1
|
||||
#endif
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// Enable configuration of module
|
||||
#ifndef CONF_SERCOM_2_SPI_ENABLE
|
||||
#define CONF_SERCOM_2_SPI_ENABLE 1
|
||||
#endif
|
||||
|
||||
// Set module in SPI Master mode
|
||||
#ifndef CONF_SERCOM_2_SPI_MODE
|
||||
#define CONF_SERCOM_2_SPI_MODE 0x03
|
||||
#endif
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <q> Receive buffer enable
|
||||
// <i> Enable receive buffer to receive data from slave (RXEN)
|
||||
// <id> spi_master_rx_enable
|
||||
#ifndef CONF_SERCOM_2_SPI_RXEN
|
||||
#define CONF_SERCOM_2_SPI_RXEN 0x1
|
||||
#endif
|
||||
|
||||
// <o> Character Size
|
||||
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
|
||||
// <0x0=>8 bits
|
||||
// <0x1=>9 bits
|
||||
// <id> spi_master_character_size
|
||||
#ifndef CONF_SERCOM_2_SPI_CHSIZE
|
||||
#define CONF_SERCOM_2_SPI_CHSIZE 0x0
|
||||
#endif
|
||||
// <o> Baud rate <1-18000000>
|
||||
// <i> The SPI data transfer rate
|
||||
// <id> spi_master_baud_rate
|
||||
#ifndef CONF_SERCOM_2_SPI_BAUD
|
||||
#define CONF_SERCOM_2_SPI_BAUD 50000
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> spi_master_advanced
|
||||
#ifndef CONF_SERCOM_2_SPI_ADVANCED
|
||||
#define CONF_SERCOM_2_SPI_ADVANCED 0
|
||||
#endif
|
||||
|
||||
// <o> Dummy byte <0x00-0x1ff>
|
||||
// <id> spi_master_dummybyte
|
||||
// <i> Dummy byte used when reading data from the slave without sending any data
|
||||
#ifndef CONF_SERCOM_2_SPI_DUMMYBYTE
|
||||
#define CONF_SERCOM_2_SPI_DUMMYBYTE 0x1ff
|
||||
#endif
|
||||
|
||||
// <o> Data Order
|
||||
// <0=>MSB first
|
||||
// <1=>LSB first
|
||||
// <i> I least significant or most significant bit is shifted out first (DORD)
|
||||
// <id> spi_master_arch_dord
|
||||
#ifndef CONF_SERCOM_2_SPI_DORD
|
||||
#define CONF_SERCOM_2_SPI_DORD 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Polarity
|
||||
// <0=>SCK is low when idle
|
||||
// <1=>SCK is high when idle
|
||||
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
|
||||
// <id> spi_master_arch_cpol
|
||||
#ifndef CONF_SERCOM_2_SPI_CPOL
|
||||
#define CONF_SERCOM_2_SPI_CPOL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Phase
|
||||
// <0x0=>Sample input on leading edge
|
||||
// <0x1=>Sample input on trailing edge
|
||||
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
|
||||
// <id> spi_master_arch_cpha
|
||||
#ifndef CONF_SERCOM_2_SPI_CPHA
|
||||
#define CONF_SERCOM_2_SPI_CPHA 0x0
|
||||
#endif
|
||||
|
||||
// <o> Immediate Buffer Overflow Notification
|
||||
// <i> Controls when OVF is asserted (IBON)
|
||||
// <0x0=>In data stream
|
||||
// <0x1=>On buffer overflow
|
||||
// <id> spi_master_arch_ibon
|
||||
#ifndef CONF_SERCOM_2_SPI_IBON
|
||||
#define CONF_SERCOM_2_SPI_IBON 0x0
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
|
||||
// <id> spi_master_arch_runstdby
|
||||
#ifndef CONF_SERCOM_2_SPI_RUNSTDBY
|
||||
#define CONF_SERCOM_2_SPI_RUNSTDBY 0x0
|
||||
#endif
|
||||
|
||||
// <o> Debug Stop Mode
|
||||
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
|
||||
// <0=>Keep running
|
||||
// <1=>Halt
|
||||
// <id> spi_master_arch_dbgstop
|
||||
#ifndef CONF_SERCOM_2_SPI_DBGSTOP
|
||||
#define CONF_SERCOM_2_SPI_DBGSTOP 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// Address mode disabled in master mode
|
||||
#ifndef CONF_SERCOM_2_SPI_AMODE_EN
|
||||
#define CONF_SERCOM_2_SPI_AMODE_EN 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_2_SPI_AMODE
|
||||
#define CONF_SERCOM_2_SPI_AMODE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_2_SPI_ADDR
|
||||
#define CONF_SERCOM_2_SPI_ADDR 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_2_SPI_ADDRMASK
|
||||
#define CONF_SERCOM_2_SPI_ADDRMASK 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_2_SPI_SSDE
|
||||
#define CONF_SERCOM_2_SPI_SSDE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_2_SPI_MSSEN
|
||||
#define CONF_SERCOM_2_SPI_MSSEN 0x0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_2_SPI_PLOADEN
|
||||
#define CONF_SERCOM_2_SPI_PLOADEN 0
|
||||
#endif
|
||||
|
||||
// <o> Receive Data Pinout
|
||||
// <0x0=>PAD[0]
|
||||
// <0x1=>PAD[1]
|
||||
// <0x2=>PAD[2]
|
||||
// <0x3=>PAD[3]
|
||||
// <id> spi_master_rxpo
|
||||
#ifndef CONF_SERCOM_2_SPI_RXPO
|
||||
#define CONF_SERCOM_2_SPI_RXPO 3
|
||||
#endif
|
||||
|
||||
// <o> Transmit Data Pinout
|
||||
// <0x0=>PAD[0,1]_DO_SCK
|
||||
// <0x1=>PAD[2,3]_DO_SCK
|
||||
// <0x2=>PAD[3,1]_DO_SCK
|
||||
// <0x3=>PAD[0,3]_DO_SCK
|
||||
// <id> spi_master_txpo
|
||||
#ifndef CONF_SERCOM_2_SPI_TXPO
|
||||
#define CONF_SERCOM_2_SPI_TXPO 0
|
||||
#endif
|
||||
|
||||
// Calculate baud register value from requested baudrate value
|
||||
#ifndef CONF_SERCOM_2_SPI_BAUD_RATE
|
||||
#define CONF_SERCOM_2_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM2_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_2_SPI_BAUD)) - 1
|
||||
#endif
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// Enable configuration of module
|
||||
#ifndef CONF_SERCOM_5_SPI_ENABLE
|
||||
#define CONF_SERCOM_5_SPI_ENABLE 1
|
||||
#endif
|
||||
|
||||
// Set module in SPI Master mode
|
||||
#ifndef CONF_SERCOM_5_SPI_MODE
|
||||
#define CONF_SERCOM_5_SPI_MODE 0x03
|
||||
#endif
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <q> Receive buffer enable
|
||||
// <i> Enable receive buffer to receive data from slave (RXEN)
|
||||
// <id> spi_master_rx_enable
|
||||
#ifndef CONF_SERCOM_5_SPI_RXEN
|
||||
#define CONF_SERCOM_5_SPI_RXEN 0x1
|
||||
#endif
|
||||
|
||||
// <o> Character Size
|
||||
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
|
||||
// <0x0=>8 bits
|
||||
// <0x1=>9 bits
|
||||
// <id> spi_master_character_size
|
||||
#ifndef CONF_SERCOM_5_SPI_CHSIZE
|
||||
#define CONF_SERCOM_5_SPI_CHSIZE 0x0
|
||||
#endif
|
||||
// <o> Baud rate <1-18000000>
|
||||
// <i> The SPI data transfer rate
|
||||
// <id> spi_master_baud_rate
|
||||
#ifndef CONF_SERCOM_5_SPI_BAUD
|
||||
#define CONF_SERCOM_5_SPI_BAUD 50000
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> spi_master_advanced
|
||||
#ifndef CONF_SERCOM_5_SPI_ADVANCED
|
||||
#define CONF_SERCOM_5_SPI_ADVANCED 0
|
||||
#endif
|
||||
|
||||
// <o> Dummy byte <0x00-0x1ff>
|
||||
// <id> spi_master_dummybyte
|
||||
// <i> Dummy byte used when reading data from the slave without sending any data
|
||||
#ifndef CONF_SERCOM_5_SPI_DUMMYBYTE
|
||||
#define CONF_SERCOM_5_SPI_DUMMYBYTE 0x1ff
|
||||
#endif
|
||||
|
||||
// <o> Data Order
|
||||
// <0=>MSB first
|
||||
// <1=>LSB first
|
||||
// <i> I least significant or most significant bit is shifted out first (DORD)
|
||||
// <id> spi_master_arch_dord
|
||||
#ifndef CONF_SERCOM_5_SPI_DORD
|
||||
#define CONF_SERCOM_5_SPI_DORD 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Polarity
|
||||
// <0=>SCK is low when idle
|
||||
// <1=>SCK is high when idle
|
||||
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
|
||||
// <id> spi_master_arch_cpol
|
||||
#ifndef CONF_SERCOM_5_SPI_CPOL
|
||||
#define CONF_SERCOM_5_SPI_CPOL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Phase
|
||||
// <0x0=>Sample input on leading edge
|
||||
// <0x1=>Sample input on trailing edge
|
||||
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
|
||||
// <id> spi_master_arch_cpha
|
||||
#ifndef CONF_SERCOM_5_SPI_CPHA
|
||||
#define CONF_SERCOM_5_SPI_CPHA 0x0
|
||||
#endif
|
||||
|
||||
// <o> Immediate Buffer Overflow Notification
|
||||
// <i> Controls when OVF is asserted (IBON)
|
||||
// <0x0=>In data stream
|
||||
// <0x1=>On buffer overflow
|
||||
// <id> spi_master_arch_ibon
|
||||
#ifndef CONF_SERCOM_5_SPI_IBON
|
||||
#define CONF_SERCOM_5_SPI_IBON 0x0
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
|
||||
// <id> spi_master_arch_runstdby
|
||||
#ifndef CONF_SERCOM_5_SPI_RUNSTDBY
|
||||
#define CONF_SERCOM_5_SPI_RUNSTDBY 0x0
|
||||
#endif
|
||||
|
||||
// <o> Debug Stop Mode
|
||||
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
|
||||
// <0=>Keep running
|
||||
// <1=>Halt
|
||||
// <id> spi_master_arch_dbgstop
|
||||
#ifndef CONF_SERCOM_5_SPI_DBGSTOP
|
||||
#define CONF_SERCOM_5_SPI_DBGSTOP 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// Address mode disabled in master mode
|
||||
#ifndef CONF_SERCOM_5_SPI_AMODE_EN
|
||||
#define CONF_SERCOM_5_SPI_AMODE_EN 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_5_SPI_AMODE
|
||||
#define CONF_SERCOM_5_SPI_AMODE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_5_SPI_ADDR
|
||||
#define CONF_SERCOM_5_SPI_ADDR 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_5_SPI_ADDRMASK
|
||||
#define CONF_SERCOM_5_SPI_ADDRMASK 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_5_SPI_SSDE
|
||||
#define CONF_SERCOM_5_SPI_SSDE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_5_SPI_MSSEN
|
||||
#define CONF_SERCOM_5_SPI_MSSEN 0x0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_5_SPI_PLOADEN
|
||||
#define CONF_SERCOM_5_SPI_PLOADEN 0
|
||||
#endif
|
||||
|
||||
// <o> Receive Data Pinout
|
||||
// <0x0=>PAD[0]
|
||||
// <0x1=>PAD[1]
|
||||
// <0x2=>PAD[2]
|
||||
// <0x3=>PAD[3]
|
||||
// <id> spi_master_rxpo
|
||||
#ifndef CONF_SERCOM_5_SPI_RXPO
|
||||
#define CONF_SERCOM_5_SPI_RXPO 3
|
||||
#endif
|
||||
|
||||
// <o> Transmit Data Pinout
|
||||
// <0x0=>PAD[0,1]_DO_SCK
|
||||
// <0x1=>PAD[2,3]_DO_SCK
|
||||
// <0x2=>PAD[3,1]_DO_SCK
|
||||
// <0x3=>PAD[0,3]_DO_SCK
|
||||
// <id> spi_master_txpo
|
||||
#ifndef CONF_SERCOM_5_SPI_TXPO
|
||||
#define CONF_SERCOM_5_SPI_TXPO 0
|
||||
#endif
|
||||
|
||||
// Calculate baud register value from requested baudrate value
|
||||
#ifndef CONF_SERCOM_5_SPI_BAUD_RATE
|
||||
#define CONF_SERCOM_5_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM5_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_5_SPI_BAUD)) - 1
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_SERCOM_CONFIG_H
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,989 @@
|
|||
/* Auto-generated config file peripheral_clk_config.h */
|
||||
#ifndef PERIPHERAL_CLK_CONFIG_H
|
||||
#define PERIPHERAL_CLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <y> ADC Clock Source
|
||||
// <id> adc_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for ADC.
|
||||
#ifndef CONF_GCLK_ADC0_SRC
|
||||
#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_ADC0_FREQUENCY
|
||||
* \brief ADC0's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_ADC0_FREQUENCY
|
||||
#define CONF_GCLK_ADC0_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> ADC Clock Source
|
||||
// <id> adc_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for ADC.
|
||||
#ifndef CONF_GCLK_ADC1_SRC
|
||||
#define CONF_GCLK_ADC1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_ADC1_FREQUENCY
|
||||
* \brief ADC1's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_ADC1_FREQUENCY
|
||||
#define CONF_GCLK_ADC1_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> CCL Clock Source
|
||||
// <id> ccl_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for CCL.
|
||||
#ifndef CONF_GCLK_CCL_SRC
|
||||
#define CONF_GCLK_CCL_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_CCL_FREQUENCY
|
||||
* \brief CCL's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_CCL_FREQUENCY
|
||||
#define CONF_GCLK_CCL_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EIC Clock Source
|
||||
// <id> eic_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for EIC.
|
||||
#ifndef CONF_GCLK_EIC_SRC
|
||||
#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EIC_FREQUENCY
|
||||
* \brief EIC's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_EIC_FREQUENCY
|
||||
#define CONF_GCLK_EIC_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 0 Clock Source
|
||||
// <id> evsys_clk_selection_0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 0.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 1 Clock Source
|
||||
// <id> evsys_clk_selection_1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 1.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 2 Clock Source
|
||||
// <id> evsys_clk_selection_2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 2.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 3 Clock Source
|
||||
// <id> evsys_clk_selection_3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 3.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 4 Clock Source
|
||||
// <id> evsys_clk_selection_4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 4.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 5 Clock Source
|
||||
// <id> evsys_clk_selection_5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 5.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 6 Clock Source
|
||||
// <id> evsys_clk_selection_6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 6.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 7 Clock Source
|
||||
// <id> evsys_clk_selection_7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 7.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 8 Clock Source
|
||||
// <id> evsys_clk_selection_8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 8.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 9 Clock Source
|
||||
// <id> evsys_clk_selection_9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 9.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 10 Clock Source
|
||||
// <id> evsys_clk_selection_10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 10.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 11 Clock Source
|
||||
// <id> evsys_clk_selection_11
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 11.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_CPU_FREQUENCY
|
||||
* \brief CPU's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_CPU_FREQUENCY
|
||||
#define CONF_CPU_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> Core Clock Source
|
||||
// <id> core_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM1_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> Slow Clock Source
|
||||
// <id> slow_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the slow clock source.
|
||||
#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
|
||||
#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
|
||||
* \brief SERCOM1's Core Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
|
||||
* \brief SERCOM1's Slow Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
|
||||
#endif
|
||||
|
||||
// <y> Core Clock Source
|
||||
// <id> core_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM2_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> Slow Clock Source
|
||||
// <id> slow_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the slow clock source.
|
||||
#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
|
||||
#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
|
||||
* \brief SERCOM2's Core Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
|
||||
* \brief SERCOM2's Slow Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
|
||||
#endif
|
||||
|
||||
// <y> Core Clock Source
|
||||
// <id> core_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM5_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> Slow Clock Source
|
||||
// <id> slow_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the slow clock source.
|
||||
#ifndef CONF_GCLK_SERCOM5_SLOW_SRC
|
||||
#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM5_CORE_FREQUENCY
|
||||
* \brief SERCOM5's Core Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM5_SLOW_FREQUENCY
|
||||
* \brief SERCOM5's Slow Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM5_SLOW_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768
|
||||
#endif
|
||||
|
||||
// <y> TCC Clock Source
|
||||
// <id> tcc_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for TCC.
|
||||
#ifndef CONF_GCLK_TCC0_SRC
|
||||
#define CONF_GCLK_TCC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_TCC0_FREQUENCY
|
||||
* \brief TCC0's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_TCC0_FREQUENCY
|
||||
#define CONF_GCLK_TCC0_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <y> TCC Clock Source
|
||||
// <id> tcc_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for TCC.
|
||||
#ifndef CONF_GCLK_TCC1_SRC
|
||||
#define CONF_GCLK_TCC1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_TCC1_FREQUENCY
|
||||
* \brief TCC1's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_TCC1_FREQUENCY
|
||||
#define CONF_GCLK_TCC1_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // PERIPHERAL_CLK_CONFIG_H
|
||||
|
|
@ -0,0 +1,475 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Configurations xmlns:i="http://www.w3.org/2001/XMLSchema-instance" z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/" xmlns="DefaultValues">
|
||||
<Configurations>
|
||||
<Configuration z:Id="i2">
|
||||
<Compiler_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>DebugLevel</d4p1:Key>
|
||||
<d4p1:Value>None</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>IncludePaths</d4p1:Key>
|
||||
<d4p1:Value>NDEBUG</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>MiscellaneousSettings</d4p1:Key>
|
||||
<d4p1:Value>-std=gnu99</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>OptimizationLevel</d4p1:Key>
|
||||
<d4p1:Value>Optimize for size (-Os)</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>SymbolDefines</d4p1:Key>
|
||||
<d4p1:Value>NDEBUG</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>SymbolUndefines</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>Verbose</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>WarningsAsErrors</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.general.CLanguageExp</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.general.ChangeDefaultCharTypeUnsigned</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.general.ChangeDefaultBitFieldUnsigned</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.general.processormode</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.preprocessor.DoNotSearchSystemDirectories</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.preprocessor.PreprocessOnly</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.symbols.Default</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.directories.DefaultIncludePath</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.OtherFlags</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.PrepareDataForGarbageCollection</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.EnableFastMath</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.GeneratePositionIndependentCode</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.EnableLongCalls</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.OtherDebuggingFlags</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.GenerateGprofInformation</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.GenerateProfInformation</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.AllWarnings</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.ExtraWarnings</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.Undefined</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.CheckSyntaxOnly</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.Pedantic</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.PedanticWarningsAsErrors</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.InhibitAllWarnings</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.miscellaneous.Device</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.miscellaneous.CompileOnly</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.miscellaneous.SupportAnsiPrograms</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.miscellaneous.MakeFileDependent</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
</Compiler_dictionary>
|
||||
<Linker_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>Libraries</d4p1:Key>
|
||||
<d4p1:Value>libm</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>LibrarySearchPath</d4p1:Key>
|
||||
<d4p1:Value>$(ProjectDir)\Device_Startup</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>MiscellaneousSettings</d4p1:Key>
|
||||
<d4p1:Value>-Tsame51j19a_flash.ld</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.DoNotUseStandardStartFiles</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.DoNotUseDefaultLibraries</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.NoStartupOrDefaultLibs</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.OmitAllSymbolInformation</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.NoSharedLibraries</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.GenerateMAPFile</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.UseNewlibNano</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.AdditionalSpecs</d4p1:Key>
|
||||
<d4p1:Value>None</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.optimization.GarbageCollectUnusedSections</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.optimization.EnableFastMath</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.optimization.GeneratePositionIndependentCode</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.memorysettings.Flash</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.memorysettings.Sram</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.memorysettings.ExternalRAM</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.miscellaneous.OtherOptions</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.miscellaneous.OtherObjects</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
</Linker_dictionary>
|
||||
<Name>Release</Name>
|
||||
</Configuration>
|
||||
<Configuration z:Id="i3">
|
||||
<Compiler_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>DebugLevel</d4p1:Key>
|
||||
<d4p1:Value>Maximum (-g3)</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>IncludePaths</d4p1:Key>
|
||||
<d4p1:Value>DEBUG</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>MiscellaneousSettings</d4p1:Key>
|
||||
<d4p1:Value>-std=gnu99</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>OptimizationLevel</d4p1:Key>
|
||||
<d4p1:Value>Optimize debugging experience (-Og)</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>SymbolDefines</d4p1:Key>
|
||||
<d4p1:Value>DEBUG</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>SymbolUndefines</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>Verbose</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>WarningsAsErrors</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.general.CLanguageExp</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.general.ChangeDefaultCharTypeUnsigned</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.general.ChangeDefaultBitFieldUnsigned</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.general.processormode</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.preprocessor.DoNotSearchSystemDirectories</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.preprocessor.PreprocessOnly</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.symbols.Default</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.directories.DefaultIncludePath</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.OtherFlags</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.PrepareDataForGarbageCollection</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.EnableFastMath</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.GeneratePositionIndependentCode</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.EnableLongCalls</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.OtherDebuggingFlags</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.GenerateGprofInformation</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.optimization.GenerateProfInformation</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.AllWarnings</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.ExtraWarnings</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.Undefined</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.CheckSyntaxOnly</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.Pedantic</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.PedanticWarningsAsErrors</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.warnings.InhibitAllWarnings</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.miscellaneous.Device</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.miscellaneous.CompileOnly</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.miscellaneous.SupportAnsiPrograms</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.compiler.miscellaneous.MakeFileDependent</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
</Compiler_dictionary>
|
||||
<Linker_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>Libraries</d4p1:Key>
|
||||
<d4p1:Value>libm</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>LibrarySearchPath</d4p1:Key>
|
||||
<d4p1:Value>$(ProjectDir)\Device_Startup</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>MiscellaneousSettings</d4p1:Key>
|
||||
<d4p1:Value>-Tsame51j19a_flash.ld</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.DoNotUseStandardStartFiles</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.DoNotUseDefaultLibraries</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.NoStartupOrDefaultLibs</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.OmitAllSymbolInformation</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.NoSharedLibraries</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.GenerateMAPFile</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.UseNewlibNano</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.general.AdditionalSpecs</d4p1:Key>
|
||||
<d4p1:Value>None</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.optimization.GarbageCollectUnusedSections</d4p1:Key>
|
||||
<d4p1:Value>True</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.optimization.EnableFastMath</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.optimization.GeneratePositionIndependentCode</d4p1:Key>
|
||||
<d4p1:Value>False</d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.memorysettings.Flash</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.memorysettings.Sram</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.memorysettings.ExternalRAM</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.miscellaneous.OtherOptions</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
<d4p1:KeyValueOfstringstring>
|
||||
<d4p1:Key>armgcc.linker.miscellaneous.OtherObjects</d4p1:Key>
|
||||
<d4p1:Value></d4p1:Value>
|
||||
</d4p1:KeyValueOfstringstring>
|
||||
</Linker_dictionary>
|
||||
<Name>Debug</Name>
|
||||
</Configuration>
|
||||
</Configurations>
|
||||
</Configurations>
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51J19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51J19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
|
|
@ -0,0 +1,546 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief gcc starttup file for SAME51
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same51.h"
|
||||
|
||||
/* Initialize segments */
|
||||
extern uint32_t _sfixed;
|
||||
extern uint32_t _efixed;
|
||||
extern uint32_t _etext;
|
||||
extern uint32_t _srelocate;
|
||||
extern uint32_t _erelocate;
|
||||
extern uint32_t _szero;
|
||||
extern uint32_t _ezero;
|
||||
extern uint32_t _sstack;
|
||||
extern uint32_t _estack;
|
||||
|
||||
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
|
||||
int main(void);
|
||||
/** \endcond */
|
||||
|
||||
void __libc_init_array(void);
|
||||
|
||||
/* Default empty handler */
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M4 core handlers */
|
||||
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MemManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void OSCCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
|
||||
void OSCCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
|
||||
void OSCCTRL_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
|
||||
void OSCCTRL_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
|
||||
void OSCCTRL_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
|
||||
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SUPC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
|
||||
void SUPC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
|
||||
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EIC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
|
||||
void EIC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
|
||||
void EIC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
|
||||
void EIC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
|
||||
void EIC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
|
||||
void EIC_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
|
||||
void EIC_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
|
||||
void EIC_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
|
||||
void EIC_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
|
||||
void EIC_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
|
||||
void EIC_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
|
||||
void EIC_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
|
||||
void EIC_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
|
||||
void EIC_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
|
||||
void EIC_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
|
||||
void EIC_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
|
||||
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
|
||||
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
|
||||
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
|
||||
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
|
||||
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
|
||||
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
|
||||
void DMAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
|
||||
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
|
||||
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
|
||||
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
|
||||
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
|
||||
void EVSYS_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
|
||||
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
|
||||
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
|
||||
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
|
||||
void SERCOM0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
|
||||
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
|
||||
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
|
||||
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
|
||||
void SERCOM1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
|
||||
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
|
||||
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
|
||||
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
|
||||
void SERCOM2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
|
||||
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
|
||||
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
|
||||
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
|
||||
void SERCOM3_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
|
||||
#ifdef ID_SERCOM4
|
||||
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
|
||||
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
|
||||
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
|
||||
void SERCOM4_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
|
||||
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
|
||||
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
|
||||
void SERCOM5_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM6
|
||||
void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
|
||||
void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
|
||||
void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
|
||||
void SERCOM6_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM7
|
||||
void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
|
||||
void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
|
||||
void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
|
||||
void SERCOM7_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
|
||||
#endif
|
||||
#ifdef ID_CAN0
|
||||
void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_CAN1
|
||||
void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_USB
|
||||
void USB_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
|
||||
void USB_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
|
||||
void USB_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
|
||||
void USB_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
|
||||
#endif
|
||||
#ifdef ID_GMAC
|
||||
void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void TCC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
|
||||
void TCC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
|
||||
void TCC0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
|
||||
void TCC0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
|
||||
void TCC0_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
|
||||
void TCC0_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
|
||||
void TCC0_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
|
||||
void TCC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
|
||||
void TCC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
|
||||
void TCC1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
|
||||
void TCC1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
|
||||
void TCC1_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
|
||||
void TCC2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
|
||||
void TCC2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
|
||||
void TCC2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
|
||||
void TCC2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
|
||||
#ifdef ID_TCC3
|
||||
void TCC3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
|
||||
void TCC3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
|
||||
void TCC3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
|
||||
#endif
|
||||
#ifdef ID_TCC4
|
||||
void TCC4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
|
||||
void TCC4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
|
||||
void TCC4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
|
||||
#endif
|
||||
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_TC4
|
||||
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC5
|
||||
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC6
|
||||
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC7
|
||||
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void PDEC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
|
||||
void PDEC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
|
||||
void PDEC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
|
||||
void ADC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
|
||||
void ADC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
|
||||
void ADC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
|
||||
void ADC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
|
||||
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
|
||||
void DAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
|
||||
void DAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
|
||||
void DAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
|
||||
void DAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
|
||||
#ifdef ID_I2S
|
||||
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_ICM
|
||||
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_PUKCC
|
||||
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_SDHC0
|
||||
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_SDHC1
|
||||
void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
|
||||
/* Exception Table */
|
||||
__attribute__ ((section(".vectors")))
|
||||
const DeviceVectors exception_table = {
|
||||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
.pvStack = (void*) (&_estack),
|
||||
|
||||
.pfnReset_Handler = (void*) Reset_Handler,
|
||||
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
|
||||
.pfnHardFault_Handler = (void*) HardFault_Handler,
|
||||
.pfnMemManagement_Handler = (void*) MemManagement_Handler,
|
||||
.pfnBusFault_Handler = (void*) BusFault_Handler,
|
||||
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
|
||||
.pvReservedM9 = (void*) (0UL), /* Reserved */
|
||||
.pvReservedM8 = (void*) (0UL), /* Reserved */
|
||||
.pvReservedM7 = (void*) (0UL), /* Reserved */
|
||||
.pvReservedM6 = (void*) (0UL), /* Reserved */
|
||||
.pfnSVCall_Handler = (void*) SVCall_Handler,
|
||||
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
|
||||
.pvReservedM3 = (void*) (0UL), /* Reserved */
|
||||
.pfnPendSV_Handler = (void*) PendSV_Handler,
|
||||
.pfnSysTick_Handler = (void*) SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
|
||||
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
|
||||
.pfnOSCCTRL_0_Handler = (void*) OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
|
||||
.pfnOSCCTRL_1_Handler = (void*) OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
|
||||
.pfnOSCCTRL_2_Handler = (void*) OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
|
||||
.pfnOSCCTRL_3_Handler = (void*) OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
|
||||
.pfnOSCCTRL_4_Handler = (void*) OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
|
||||
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
|
||||
.pfnSUPC_0_Handler = (void*) SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
|
||||
.pfnSUPC_1_Handler = (void*) SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */
|
||||
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
|
||||
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
|
||||
.pfnEIC_0_Handler = (void*) EIC_0_Handler, /* 12 EIC_EXTINT_0 */
|
||||
.pfnEIC_1_Handler = (void*) EIC_1_Handler, /* 13 EIC_EXTINT_1 */
|
||||
.pfnEIC_2_Handler = (void*) EIC_2_Handler, /* 14 EIC_EXTINT_2 */
|
||||
.pfnEIC_3_Handler = (void*) EIC_3_Handler, /* 15 EIC_EXTINT_3 */
|
||||
.pfnEIC_4_Handler = (void*) EIC_4_Handler, /* 16 EIC_EXTINT_4 */
|
||||
.pfnEIC_5_Handler = (void*) EIC_5_Handler, /* 17 EIC_EXTINT_5 */
|
||||
.pfnEIC_6_Handler = (void*) EIC_6_Handler, /* 18 EIC_EXTINT_6 */
|
||||
.pfnEIC_7_Handler = (void*) EIC_7_Handler, /* 19 EIC_EXTINT_7 */
|
||||
.pfnEIC_8_Handler = (void*) EIC_8_Handler, /* 20 EIC_EXTINT_8 */
|
||||
.pfnEIC_9_Handler = (void*) EIC_9_Handler, /* 21 EIC_EXTINT_9 */
|
||||
.pfnEIC_10_Handler = (void*) EIC_10_Handler, /* 22 EIC_EXTINT_10 */
|
||||
.pfnEIC_11_Handler = (void*) EIC_11_Handler, /* 23 EIC_EXTINT_11 */
|
||||
.pfnEIC_12_Handler = (void*) EIC_12_Handler, /* 24 EIC_EXTINT_12 */
|
||||
.pfnEIC_13_Handler = (void*) EIC_13_Handler, /* 25 EIC_EXTINT_13 */
|
||||
.pfnEIC_14_Handler = (void*) EIC_14_Handler, /* 26 EIC_EXTINT_14 */
|
||||
.pfnEIC_15_Handler = (void*) EIC_15_Handler, /* 27 EIC_EXTINT_15 */
|
||||
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
|
||||
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
|
||||
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
|
||||
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
|
||||
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
|
||||
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
|
||||
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
|
||||
.pfnDMAC_4_Handler = (void*) DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
|
||||
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
|
||||
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
|
||||
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
|
||||
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
|
||||
.pfnEVSYS_4_Handler = (void*) EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
|
||||
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
|
||||
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
|
||||
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
|
||||
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
|
||||
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
|
||||
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 SERCOM0_0 */
|
||||
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 SERCOM0_1 */
|
||||
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 SERCOM0_2 */
|
||||
.pfnSERCOM0_3_Handler = (void*) SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
|
||||
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 SERCOM1_0 */
|
||||
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 SERCOM1_1 */
|
||||
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 SERCOM1_2 */
|
||||
.pfnSERCOM1_3_Handler = (void*) SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
|
||||
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 SERCOM2_0 */
|
||||
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 SERCOM2_1 */
|
||||
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 SERCOM2_2 */
|
||||
.pfnSERCOM2_3_Handler = (void*) SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
|
||||
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 SERCOM3_0 */
|
||||
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 SERCOM3_1 */
|
||||
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 SERCOM3_2 */
|
||||
.pfnSERCOM3_3_Handler = (void*) SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
|
||||
#ifdef ID_SERCOM4
|
||||
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 SERCOM4_0 */
|
||||
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 SERCOM4_1 */
|
||||
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 SERCOM4_2 */
|
||||
.pfnSERCOM4_3_Handler = (void*) SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
|
||||
#else
|
||||
.pvReserved62 = (void*) (0UL), /* 62 Reserved */
|
||||
.pvReserved63 = (void*) (0UL), /* 63 Reserved */
|
||||
.pvReserved64 = (void*) (0UL), /* 64 Reserved */
|
||||
.pvReserved65 = (void*) (0UL), /* 65 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 SERCOM5_0 */
|
||||
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 SERCOM5_1 */
|
||||
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 SERCOM5_2 */
|
||||
.pfnSERCOM5_3_Handler = (void*) SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
|
||||
#else
|
||||
.pvReserved66 = (void*) (0UL), /* 66 Reserved */
|
||||
.pvReserved67 = (void*) (0UL), /* 67 Reserved */
|
||||
.pvReserved68 = (void*) (0UL), /* 68 Reserved */
|
||||
.pvReserved69 = (void*) (0UL), /* 69 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM6
|
||||
.pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 SERCOM6_0 */
|
||||
.pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 SERCOM6_1 */
|
||||
.pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 SERCOM6_2 */
|
||||
.pfnSERCOM6_3_Handler = (void*) SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
|
||||
#else
|
||||
.pvReserved70 = (void*) (0UL), /* 70 Reserved */
|
||||
.pvReserved71 = (void*) (0UL), /* 71 Reserved */
|
||||
.pvReserved72 = (void*) (0UL), /* 72 Reserved */
|
||||
.pvReserved73 = (void*) (0UL), /* 73 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM7
|
||||
.pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 SERCOM7_0 */
|
||||
.pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 SERCOM7_1 */
|
||||
.pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 SERCOM7_2 */
|
||||
.pfnSERCOM7_3_Handler = (void*) SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
|
||||
#else
|
||||
.pvReserved74 = (void*) (0UL), /* 74 Reserved */
|
||||
.pvReserved75 = (void*) (0UL), /* 75 Reserved */
|
||||
.pvReserved76 = (void*) (0UL), /* 76 Reserved */
|
||||
.pvReserved77 = (void*) (0UL), /* 77 Reserved */
|
||||
#endif
|
||||
#ifdef ID_CAN0
|
||||
.pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network 0 */
|
||||
#else
|
||||
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
|
||||
#endif
|
||||
#ifdef ID_CAN1
|
||||
.pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network 1 */
|
||||
#else
|
||||
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
|
||||
#endif
|
||||
#ifdef ID_USB
|
||||
.pfnUSB_0_Handler = (void*) USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
|
||||
.pfnUSB_1_Handler = (void*) USB_1_Handler, /* 81 USB_SOF_HSOF */
|
||||
.pfnUSB_2_Handler = (void*) USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
|
||||
.pfnUSB_3_Handler = (void*) USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
|
||||
#else
|
||||
.pvReserved80 = (void*) (0UL), /* 80 Reserved */
|
||||
.pvReserved81 = (void*) (0UL), /* 81 Reserved */
|
||||
.pvReserved82 = (void*) (0UL), /* 82 Reserved */
|
||||
.pvReserved83 = (void*) (0UL), /* 83 Reserved */
|
||||
#endif
|
||||
#ifdef ID_GMAC
|
||||
.pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */
|
||||
#else
|
||||
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
|
||||
#endif
|
||||
.pfnTCC0_0_Handler = (void*) TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
|
||||
.pfnTCC0_1_Handler = (void*) TCC0_1_Handler, /* 86 TCC0_MC_0 */
|
||||
.pfnTCC0_2_Handler = (void*) TCC0_2_Handler, /* 87 TCC0_MC_1 */
|
||||
.pfnTCC0_3_Handler = (void*) TCC0_3_Handler, /* 88 TCC0_MC_2 */
|
||||
.pfnTCC0_4_Handler = (void*) TCC0_4_Handler, /* 89 TCC0_MC_3 */
|
||||
.pfnTCC0_5_Handler = (void*) TCC0_5_Handler, /* 90 TCC0_MC_4 */
|
||||
.pfnTCC0_6_Handler = (void*) TCC0_6_Handler, /* 91 TCC0_MC_5 */
|
||||
.pfnTCC1_0_Handler = (void*) TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
|
||||
.pfnTCC1_1_Handler = (void*) TCC1_1_Handler, /* 93 TCC1_MC_0 */
|
||||
.pfnTCC1_2_Handler = (void*) TCC1_2_Handler, /* 94 TCC1_MC_1 */
|
||||
.pfnTCC1_3_Handler = (void*) TCC1_3_Handler, /* 95 TCC1_MC_2 */
|
||||
.pfnTCC1_4_Handler = (void*) TCC1_4_Handler, /* 96 TCC1_MC_3 */
|
||||
.pfnTCC2_0_Handler = (void*) TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
|
||||
.pfnTCC2_1_Handler = (void*) TCC2_1_Handler, /* 98 TCC2_MC_0 */
|
||||
.pfnTCC2_2_Handler = (void*) TCC2_2_Handler, /* 99 TCC2_MC_1 */
|
||||
.pfnTCC2_3_Handler = (void*) TCC2_3_Handler, /* 100 TCC2_MC_2 */
|
||||
#ifdef ID_TCC3
|
||||
.pfnTCC3_0_Handler = (void*) TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
|
||||
.pfnTCC3_1_Handler = (void*) TCC3_1_Handler, /* 102 TCC3_MC_0 */
|
||||
.pfnTCC3_2_Handler = (void*) TCC3_2_Handler, /* 103 TCC3_MC_1 */
|
||||
#else
|
||||
.pvReserved101 = (void*) (0UL), /* 101 Reserved */
|
||||
.pvReserved102 = (void*) (0UL), /* 102 Reserved */
|
||||
.pvReserved103 = (void*) (0UL), /* 103 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TCC4
|
||||
.pfnTCC4_0_Handler = (void*) TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
|
||||
.pfnTCC4_1_Handler = (void*) TCC4_1_Handler, /* 105 TCC4_MC_0 */
|
||||
.pfnTCC4_2_Handler = (void*) TCC4_2_Handler, /* 106 TCC4_MC_1 */
|
||||
#else
|
||||
.pvReserved104 = (void*) (0UL), /* 104 Reserved */
|
||||
.pvReserved105 = (void*) (0UL), /* 105 Reserved */
|
||||
.pvReserved106 = (void*) (0UL), /* 106 Reserved */
|
||||
#endif
|
||||
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter 0 */
|
||||
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter 1 */
|
||||
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter 2 */
|
||||
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter 3 */
|
||||
#ifdef ID_TC4
|
||||
.pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter 4 */
|
||||
#else
|
||||
.pvReserved111 = (void*) (0UL), /* 111 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC5
|
||||
.pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter 5 */
|
||||
#else
|
||||
.pvReserved112 = (void*) (0UL), /* 112 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC6
|
||||
.pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter 6 */
|
||||
#else
|
||||
.pvReserved113 = (void*) (0UL), /* 113 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC7
|
||||
.pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter 7 */
|
||||
#else
|
||||
.pvReserved114 = (void*) (0UL), /* 114 Reserved */
|
||||
#endif
|
||||
.pfnPDEC_0_Handler = (void*) PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
|
||||
.pfnPDEC_1_Handler = (void*) PDEC_1_Handler, /* 116 PDEC_MC_0 */
|
||||
.pfnPDEC_2_Handler = (void*) PDEC_2_Handler, /* 117 PDEC_MC_1 */
|
||||
.pfnADC0_0_Handler = (void*) ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */
|
||||
.pfnADC0_1_Handler = (void*) ADC0_1_Handler, /* 119 ADC0_RESRDY */
|
||||
.pfnADC1_0_Handler = (void*) ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */
|
||||
.pfnADC1_1_Handler = (void*) ADC1_1_Handler, /* 121 ADC1_RESRDY */
|
||||
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
|
||||
.pfnDAC_0_Handler = (void*) DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
|
||||
.pfnDAC_1_Handler = (void*) DAC_1_Handler, /* 124 DAC_EMPTY_0 */
|
||||
.pfnDAC_2_Handler = (void*) DAC_2_Handler, /* 125 DAC_EMPTY_1 */
|
||||
.pfnDAC_3_Handler = (void*) DAC_3_Handler, /* 126 DAC_RESRDY_0 */
|
||||
.pfnDAC_4_Handler = (void*) DAC_4_Handler, /* 127 DAC_RESRDY_1 */
|
||||
#ifdef ID_I2S
|
||||
.pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
|
||||
#else
|
||||
.pvReserved128 = (void*) (0UL), /* 128 Reserved */
|
||||
#endif
|
||||
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
|
||||
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
|
||||
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
|
||||
#ifdef ID_ICM
|
||||
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
|
||||
#else
|
||||
.pvReserved132 = (void*) (0UL), /* 132 Reserved */
|
||||
#endif
|
||||
#ifdef ID_PUKCC
|
||||
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
|
||||
#else
|
||||
.pvReserved133 = (void*) (0UL), /* 133 Reserved */
|
||||
#endif
|
||||
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
|
||||
#ifdef ID_SDHC0
|
||||
.pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */
|
||||
#else
|
||||
.pvReserved135 = (void*) (0UL), /* 135 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SDHC1
|
||||
.pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller 1 */
|
||||
#else
|
||||
.pvReserved136 = (void*) (0UL) /* 136 Reserved */
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
* To initialize the device, and call the main() routine.
|
||||
*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pSrc, *pDest;
|
||||
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext;
|
||||
pDest = &_srelocate;
|
||||
|
||||
if (pSrc != pDest) {
|
||||
for (; pDest < &_erelocate;) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the zero segment */
|
||||
for (pDest = &_szero; pDest < &_ezero;) {
|
||||
*pDest++ = 0;
|
||||
}
|
||||
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *) & _sfixed;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
#if __FPU_USED
|
||||
/* Enable FPU */
|
||||
SCB->CPACR |= (0xFu << 20);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Initialize the C library */
|
||||
__libc_init_array();
|
||||
|
||||
/* Branch to main function */
|
||||
main();
|
||||
|
||||
/* Infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same51.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (48000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
#include <atmel_start.h>
|
||||
|
||||
/**
|
||||
* Initializes MCU, drivers and middleware in the project
|
||||
**/
|
||||
void atmel_start_init(void)
|
||||
{
|
||||
system_init();
|
||||
}
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef ATMEL_START_PINS_H_INCLUDED
|
||||
#define ATMEL_START_PINS_H_INCLUDED
|
||||
|
||||
#include <hal_gpio.h>
|
||||
|
||||
// SAME51 has 14 pin functions
|
||||
|
||||
#define GPIO_PIN_FUNCTION_A 0
|
||||
#define GPIO_PIN_FUNCTION_B 1
|
||||
#define GPIO_PIN_FUNCTION_C 2
|
||||
#define GPIO_PIN_FUNCTION_D 3
|
||||
#define GPIO_PIN_FUNCTION_E 4
|
||||
#define GPIO_PIN_FUNCTION_F 5
|
||||
#define GPIO_PIN_FUNCTION_G 6
|
||||
#define GPIO_PIN_FUNCTION_H 7
|
||||
#define GPIO_PIN_FUNCTION_I 8
|
||||
#define GPIO_PIN_FUNCTION_J 9
|
||||
#define GPIO_PIN_FUNCTION_K 10
|
||||
#define GPIO_PIN_FUNCTION_L 11
|
||||
#define GPIO_PIN_FUNCTION_M 12
|
||||
#define GPIO_PIN_FUNCTION_N 13
|
||||
|
||||
#define SPI1_MOSI GPIO(GPIO_PORTA, 0)
|
||||
#define SPI1_SCK GPIO(GPIO_PORTA, 1)
|
||||
#define ALOG_0 GPIO(GPIO_PORTA, 2)
|
||||
#define ANAREF_2V48 GPIO(GPIO_PORTA, 3)
|
||||
#define M1_HALLA GPIO(GPIO_PORTA, 4)
|
||||
#define M1_HALLB GPIO(GPIO_PORTA, 5)
|
||||
#define M1_HALLC GPIO(GPIO_PORTA, 6)
|
||||
#define ECAT_SYNC GPIO(GPIO_PORTA, 7)
|
||||
#define ECAT_QSPI_MOSI GPIO(GPIO_PORTA, 8)
|
||||
#define ECAT_QSPI_MISO GPIO(GPIO_PORTA, 9)
|
||||
#define ECAT_QSPI_DATA2 GPIO(GPIO_PORTA, 10)
|
||||
#define ECAT_QSPI_DATA3 GPIO(GPIO_PORTA, 11)
|
||||
#define SPI2_MOSI GPIO(GPIO_PORTA, 12)
|
||||
#define SPI2_SCK GPIO(GPIO_PORTA, 13)
|
||||
#define SPI2_SS GPIO(GPIO_PORTA, 14)
|
||||
#define SPI2_MISO GPIO(GPIO_PORTA, 15)
|
||||
#define M2_PWMA GPIO(GPIO_PORTA, 16)
|
||||
#define M2_PWMB GPIO(GPIO_PORTA, 17)
|
||||
#define M2_PWMC GPIO(GPIO_PORTA, 18)
|
||||
#define M2_ENA GPIO(GPIO_PORTA, 19)
|
||||
#define M2_ENB GPIO(GPIO_PORTA, 20)
|
||||
#define M2_ENC GPIO(GPIO_PORTA, 21)
|
||||
#define M2_HALLA GPIO(GPIO_PORTA, 22)
|
||||
#define M2_HALLB GPIO(GPIO_PORTA, 23)
|
||||
#define M2_HALLC GPIO(GPIO_PORTA, 24)
|
||||
#define M1_RST GPIO(GPIO_PORTA, 25)
|
||||
#define M2_RST GPIO(GPIO_PORTA, 27)
|
||||
#define SPI3_SS GPIO(GPIO_PORTB, 0)
|
||||
#define SPI3_MISO GPIO(GPIO_PORTB, 1)
|
||||
#define SPI3_MOSI GPIO(GPIO_PORTB, 2)
|
||||
#define SPI3_SCK GPIO(GPIO_PORTB, 3)
|
||||
#define M1_IA GPIO(GPIO_PORTB, 4)
|
||||
#define M1_IB GPIO(GPIO_PORTB, 5)
|
||||
#define M2_IA GPIO(GPIO_PORTB, 6)
|
||||
#define M2_IB GPIO(GPIO_PORTB, 7)
|
||||
#define half_VREF GPIO(GPIO_PORTB, 8)
|
||||
#define ALOG_2 GPIO(GPIO_PORTB, 9)
|
||||
#define ECAT_QSPI_SCK GPIO(GPIO_PORTB, 10)
|
||||
#define ECAT_QSPI_CS GPIO(GPIO_PORTB, 11)
|
||||
#define M1_PWMA GPIO(GPIO_PORTB, 12)
|
||||
#define M1_PWMB GPIO(GPIO_PORTB, 13)
|
||||
#define M1_PWMC GPIO(GPIO_PORTB, 14)
|
||||
#define M1_ENA GPIO(GPIO_PORTB, 15)
|
||||
#define M1_ENB GPIO(GPIO_PORTB, 16)
|
||||
#define M1_ENC GPIO(GPIO_PORTB, 17)
|
||||
#define SPI1_CS GPIO(GPIO_PORTB, 22)
|
||||
#define SPI1_MISO GPIO(GPIO_PORTB, 23)
|
||||
#define M1_RST_Bar GPIO(GPIO_PORTB, 30)
|
||||
#define M2_RST_Bar GPIO(GPIO_PORTB, 31)
|
||||
|
||||
#endif // ATMEL_START_PINS_H_INCLUDED
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/*
|
||||
* bldc.c
|
||||
*
|
||||
* Created: 31/07/2021 14:56:17
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* bldc.h
|
||||
*
|
||||
* Created: 31/07/2021 14:56:02
|
||||
* Author: Nick-XMG
|
||||
*/
|
||||
|
||||
|
||||
#ifndef BLDC_H_
|
||||
#define BLDC_H_
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// M1 Hall Parameters
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
#define M1_HALL_A_PIN GPIO(GPIO_PORTA, 22)
|
||||
#define M1_HALL_A_PORT PORT_PA22
|
||||
#define M1_HALL_A_MASK ~(1<<0)
|
||||
#define M1_HALL_A_LSR M1_HALL_A_PIN - M1_HALL_A_GROUP*32 -0
|
||||
#define M1_HALL_A_GROUP M1_HALL_A_PIN/32
|
||||
|
||||
#define M1_HALL_B_PIN GPIO(GPIO_PORTA, 23)
|
||||
#define M1_HALL_B_PORT PORT_PA23
|
||||
#define M1_HALL_B_MASK ~(1<<1)
|
||||
#define M1_HALL_B_LSR M1_HALL_B_PIN - M1_HALL_B_GROUP*32 -1
|
||||
#define M1_HALL_B_GROUP M1_HALL_B_PIN/32
|
||||
|
||||
#define M1_HALL_C_PIN GPIO(GPIO_PORTA, 24)
|
||||
#define M1_HALL_C_PORT PORT_PA24
|
||||
#define M1_HALL_C_MASK ~(1<<2)
|
||||
#define M1_HALL_C_LSR M1_HALL_C_PIN - M1_HALL_C_GROUP*32 -2
|
||||
#define M1_HALL_C_GROUP M1_HALL_C_PIN/32
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// M2 Hall Parameters
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
#define M2_HALL_A_PIN GPIO(GPIO_PORTA, 4)
|
||||
#define M2_HALL_A_PORT PORT_PA04
|
||||
#define M2_HALL_A_MASK ~(1<<0)
|
||||
#define M2_HALL_A_LSR M2_HALL_A_PIN - M2_HALL_A_GROUP*32 -0
|
||||
#define M2_HALL_A_GROUP M2_HALL_A_PIN/32
|
||||
|
||||
#define M2_HALL_B_PIN GPIO(GPIO_PORTA, 5)
|
||||
#define M2_HALL_B_PORT PORT_PA05
|
||||
#define M2_HALL_B_MASK ~(1<<1)
|
||||
#define M2_HALL_B_LSR M2_HALL_B_PIN - M2_HALL_B_GROUP*32 -1
|
||||
#define M2_HALL_B_GROUP M2_HALL_B_PIN/32
|
||||
|
||||
#define M2_HALL_C_PIN GPIO(GPIO_PORTA, 6)
|
||||
#define M2_HALL_C_PORT PORT_PA06
|
||||
#define M2_HALL_C_MASK ~(1<<2)
|
||||
#define M2_HALL_C_LSR M2_HALL_C_PIN - M2_HALL_C_GROUP*32 -2
|
||||
#define M2_HALL_C_GROUP M2_HALL_C_PIN/32
|
||||
|
||||
|
||||
static inline uint8_t readM1Hall(void)
|
||||
{
|
||||
//volatile uint8_t motor_read = 0;
|
||||
//motor_read = (motor_read & M1_HALL_A_MASK) | (uint8_t)((PORT->Group[M1_HALL_A_GROUP].IN.reg & M1_HALL_A_PORT)>>(M1_HALL_A_LSR));
|
||||
//motor_read = (motor_read & M1_HALL_B_MASK) | (uint8_t)((PORT->Group[M1_HALL_B_GROUP].IN.reg & M1_HALL_B_PORT)>>(M1_HALL_B_LSR));
|
||||
//motor_read = (motor_read & M1_HALL_C_MASK) | (uint8_t)((PORT->Group[M1_HALL_C_GROUP].IN.reg & M1_HALL_C_PORT)>>(M1_HALL_C_LSR));
|
||||
//
|
||||
//return motor_read;
|
||||
volatile uint8_t a = gpio_get_pin_level(M1_HALL_A_PIN);
|
||||
volatile uint8_t b = gpio_get_pin_level(M1_HALL_B_PIN);
|
||||
volatile uint8_t c = gpio_get_pin_level(M1_HALL_C_PIN);
|
||||
|
||||
return ((a << 2) |
|
||||
(b << 1) |
|
||||
(c << 0));
|
||||
|
||||
}
|
||||
|
||||
static inline uint8_t readM2Hall(void)
|
||||
{
|
||||
//volatile uint8_t motor_read = 0;
|
||||
//motor_read = (motor_read & M2_HALL_A_MASK) | (uint8_t)((PORT->Group[M2_HALL_A_GROUP].IN.reg & M2_HALL_A_PORT)>>(M2_HALL_A_LSR));
|
||||
//motor_read = (motor_read & M2_HALL_B_MASK) | (uint8_t)((PORT->Group[M2_HALL_B_GROUP].IN.reg & M2_HALL_B_PORT)>>(M2_HALL_B_LSR));
|
||||
//motor_read = (motor_read & M2_HALL_C_MASK) | (uint8_t)((PORT->Group[M2_HALL_C_GROUP].IN.reg & M2_HALL_C_PORT)>>(M2_HALL_C_LSR));
|
||||
//
|
||||
//return motor_read;
|
||||
|
||||
|
||||
volatile uint8_t a = gpio_get_pin_level(M2_HALL_A_PIN);
|
||||
volatile uint8_t b = gpio_get_pin_level(M2_HALL_B_PIN);
|
||||
volatile uint8_t c = gpio_get_pin_level(M2_HALL_C_PIN);
|
||||
|
||||
return ((a << 2) |
|
||||
(b << 1) |
|
||||
(c << 0));
|
||||
}
|
||||
|
||||
|
||||
#endif /* BLDC_H_ */
|
||||
|
|
@ -0,0 +1,969 @@
|
|||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
|
||||
#include "driver_init.h"
|
||||
#include <peripheral_clk_config.h>
|
||||
#include <utils.h>
|
||||
#include <hal_init.h>
|
||||
|
||||
#include <hpl_adc_base.h>
|
||||
#include <hpl_adc_base.h>
|
||||
|
||||
struct spi_m_sync_descriptor SPI_1;
|
||||
struct spi_m_sync_descriptor SPI_3;
|
||||
|
||||
struct adc_sync_descriptor ADC_0;
|
||||
|
||||
struct adc_sync_descriptor ADC_1;
|
||||
|
||||
struct qspi_sync_descriptor QUAD_SPI_0;
|
||||
|
||||
struct spi_m_async_descriptor SPI_2;
|
||||
|
||||
struct pwm_descriptor PWM_0;
|
||||
|
||||
struct pwm_descriptor PWM_1;
|
||||
|
||||
void ADC_0_PORT_init(void)
|
||||
{
|
||||
|
||||
// Disable digital pin circuitry
|
||||
gpio_set_pin_direction(ALOG_0, GPIO_DIRECTION_OFF);
|
||||
|
||||
gpio_set_pin_function(ALOG_0, PINMUX_PA02B_ADC0_AIN0);
|
||||
|
||||
// Disable digital pin circuitry
|
||||
gpio_set_pin_direction(ALOG_2, GPIO_DIRECTION_OFF);
|
||||
|
||||
gpio_set_pin_function(ALOG_2, PINMUX_PB09B_ADC0_AIN3);
|
||||
}
|
||||
|
||||
void ADC_0_CLOCK_init(void)
|
||||
{
|
||||
hri_mclk_set_APBDMASK_ADC0_bit(MCLK);
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
}
|
||||
|
||||
void ADC_0_init(void)
|
||||
{
|
||||
ADC_0_CLOCK_init();
|
||||
ADC_0_PORT_init();
|
||||
adc_sync_init(&ADC_0, ADC0, (void *)NULL);
|
||||
}
|
||||
|
||||
void ADC_1_PORT_init(void)
|
||||
{
|
||||
|
||||
// Disable digital pin circuitry
|
||||
gpio_set_pin_direction(M1_IA, GPIO_DIRECTION_OFF);
|
||||
|
||||
gpio_set_pin_function(M1_IA, PINMUX_PB04B_ADC1_AIN6);
|
||||
|
||||
// Disable digital pin circuitry
|
||||
gpio_set_pin_direction(M1_IB, GPIO_DIRECTION_OFF);
|
||||
|
||||
gpio_set_pin_function(M1_IB, PINMUX_PB05B_ADC1_AIN7);
|
||||
|
||||
// Disable digital pin circuitry
|
||||
gpio_set_pin_direction(M2_IA, GPIO_DIRECTION_OFF);
|
||||
|
||||
gpio_set_pin_function(M2_IA, PINMUX_PB06B_ADC1_AIN8);
|
||||
|
||||
// Disable digital pin circuitry
|
||||
gpio_set_pin_direction(M2_IB, GPIO_DIRECTION_OFF);
|
||||
|
||||
gpio_set_pin_function(M2_IB, PINMUX_PB07B_ADC1_AIN9);
|
||||
}
|
||||
|
||||
void ADC_1_CLOCK_init(void)
|
||||
{
|
||||
hri_mclk_set_APBDMASK_ADC1_bit(MCLK);
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, ADC1_GCLK_ID, CONF_GCLK_ADC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
}
|
||||
|
||||
void ADC_1_init(void)
|
||||
{
|
||||
ADC_1_CLOCK_init();
|
||||
ADC_1_PORT_init();
|
||||
adc_sync_init(&ADC_1, ADC1, (void *)NULL);
|
||||
}
|
||||
|
||||
void DIGITAL_GLUE_LOGIC_0_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_direction(M1_HALLA,
|
||||
// <y> Pin direction
|
||||
// <id> pad_direction
|
||||
// <GPIO_DIRECTION_OFF"> Off
|
||||
// <GPIO_DIRECTION_IN"> In
|
||||
// <GPIO_DIRECTION_OUT"> Out
|
||||
GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_level(M1_HALLA,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
gpio_set_pin_pull_mode(M1_HALLA,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_UP);
|
||||
|
||||
gpio_set_pin_function(M1_HALLA,
|
||||
// <y> Pin function
|
||||
// <id> pad_function
|
||||
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
|
||||
// <PINMUX_PA04N_CCL_IN0"> Auto
|
||||
// <GPIO_PIN_FUNCTION_OFF"> Off
|
||||
// <GPIO_PIN_FUNCTION_A"> A
|
||||
// <GPIO_PIN_FUNCTION_B"> B
|
||||
// <GPIO_PIN_FUNCTION_C"> C
|
||||
// <GPIO_PIN_FUNCTION_D"> D
|
||||
// <GPIO_PIN_FUNCTION_E"> E
|
||||
// <GPIO_PIN_FUNCTION_F"> F
|
||||
// <GPIO_PIN_FUNCTION_G"> G
|
||||
// <GPIO_PIN_FUNCTION_H"> H
|
||||
// <GPIO_PIN_FUNCTION_I"> I
|
||||
// <GPIO_PIN_FUNCTION_J"> J
|
||||
// <GPIO_PIN_FUNCTION_K"> K
|
||||
// <GPIO_PIN_FUNCTION_L"> L
|
||||
// <GPIO_PIN_FUNCTION_M"> M
|
||||
// <GPIO_PIN_FUNCTION_N"> N
|
||||
GPIO_PIN_FUNCTION_N);
|
||||
|
||||
gpio_set_pin_direction(M1_HALLB,
|
||||
// <y> Pin direction
|
||||
// <id> pad_direction
|
||||
// <GPIO_DIRECTION_OFF"> Off
|
||||
// <GPIO_DIRECTION_IN"> In
|
||||
// <GPIO_DIRECTION_OUT"> Out
|
||||
GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_level(M1_HALLB,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
gpio_set_pin_pull_mode(M1_HALLB,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_UP);
|
||||
|
||||
gpio_set_pin_function(M1_HALLB,
|
||||
// <y> Pin function
|
||||
// <id> pad_function
|
||||
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
|
||||
// <PINMUX_PA05N_CCL_IN1"> Auto
|
||||
// <GPIO_PIN_FUNCTION_OFF"> Off
|
||||
// <GPIO_PIN_FUNCTION_A"> A
|
||||
// <GPIO_PIN_FUNCTION_B"> B
|
||||
// <GPIO_PIN_FUNCTION_C"> C
|
||||
// <GPIO_PIN_FUNCTION_D"> D
|
||||
// <GPIO_PIN_FUNCTION_E"> E
|
||||
// <GPIO_PIN_FUNCTION_F"> F
|
||||
// <GPIO_PIN_FUNCTION_G"> G
|
||||
// <GPIO_PIN_FUNCTION_H"> H
|
||||
// <GPIO_PIN_FUNCTION_I"> I
|
||||
// <GPIO_PIN_FUNCTION_J"> J
|
||||
// <GPIO_PIN_FUNCTION_K"> K
|
||||
// <GPIO_PIN_FUNCTION_L"> L
|
||||
// <GPIO_PIN_FUNCTION_M"> M
|
||||
// <GPIO_PIN_FUNCTION_N"> N
|
||||
GPIO_PIN_FUNCTION_N);
|
||||
|
||||
gpio_set_pin_direction(M1_HALLC,
|
||||
// <y> Pin direction
|
||||
// <id> pad_direction
|
||||
// <GPIO_DIRECTION_OFF"> Off
|
||||
// <GPIO_DIRECTION_IN"> In
|
||||
// <GPIO_DIRECTION_OUT"> Out
|
||||
GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_level(M1_HALLC,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
gpio_set_pin_pull_mode(M1_HALLC,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_UP);
|
||||
|
||||
gpio_set_pin_function(M1_HALLC,
|
||||
// <y> Pin function
|
||||
// <id> pad_function
|
||||
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
|
||||
// <PINMUX_PA06N_CCL_IN2"> Auto
|
||||
// <GPIO_PIN_FUNCTION_OFF"> Off
|
||||
// <GPIO_PIN_FUNCTION_A"> A
|
||||
// <GPIO_PIN_FUNCTION_B"> B
|
||||
// <GPIO_PIN_FUNCTION_C"> C
|
||||
// <GPIO_PIN_FUNCTION_D"> D
|
||||
// <GPIO_PIN_FUNCTION_E"> E
|
||||
// <GPIO_PIN_FUNCTION_F"> F
|
||||
// <GPIO_PIN_FUNCTION_G"> G
|
||||
// <GPIO_PIN_FUNCTION_H"> H
|
||||
// <GPIO_PIN_FUNCTION_I"> I
|
||||
// <GPIO_PIN_FUNCTION_J"> J
|
||||
// <GPIO_PIN_FUNCTION_K"> K
|
||||
// <GPIO_PIN_FUNCTION_L"> L
|
||||
// <GPIO_PIN_FUNCTION_M"> M
|
||||
// <GPIO_PIN_FUNCTION_N"> N
|
||||
GPIO_PIN_FUNCTION_N);
|
||||
|
||||
gpio_set_pin_direction(M2_HALLA,
|
||||
// <y> Pin direction
|
||||
// <id> pad_direction
|
||||
// <GPIO_DIRECTION_OFF"> Off
|
||||
// <GPIO_DIRECTION_IN"> In
|
||||
// <GPIO_DIRECTION_OUT"> Out
|
||||
GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_level(M2_HALLA,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
gpio_set_pin_pull_mode(M2_HALLA,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_UP);
|
||||
|
||||
gpio_set_pin_function(M2_HALLA,
|
||||
// <y> Pin function
|
||||
// <id> pad_function
|
||||
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
|
||||
// <PINMUX_PA22N_CCL_IN6"> Auto
|
||||
// <GPIO_PIN_FUNCTION_OFF"> Off
|
||||
// <GPIO_PIN_FUNCTION_A"> A
|
||||
// <GPIO_PIN_FUNCTION_B"> B
|
||||
// <GPIO_PIN_FUNCTION_C"> C
|
||||
// <GPIO_PIN_FUNCTION_D"> D
|
||||
// <GPIO_PIN_FUNCTION_E"> E
|
||||
// <GPIO_PIN_FUNCTION_F"> F
|
||||
// <GPIO_PIN_FUNCTION_G"> G
|
||||
// <GPIO_PIN_FUNCTION_H"> H
|
||||
// <GPIO_PIN_FUNCTION_I"> I
|
||||
// <GPIO_PIN_FUNCTION_J"> J
|
||||
// <GPIO_PIN_FUNCTION_K"> K
|
||||
// <GPIO_PIN_FUNCTION_L"> L
|
||||
// <GPIO_PIN_FUNCTION_M"> M
|
||||
// <GPIO_PIN_FUNCTION_N"> N
|
||||
GPIO_PIN_FUNCTION_N);
|
||||
|
||||
gpio_set_pin_direction(M2_HALLB,
|
||||
// <y> Pin direction
|
||||
// <id> pad_direction
|
||||
// <GPIO_DIRECTION_OFF"> Off
|
||||
// <GPIO_DIRECTION_IN"> In
|
||||
// <GPIO_DIRECTION_OUT"> Out
|
||||
GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_level(M2_HALLB,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
gpio_set_pin_pull_mode(M2_HALLB,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_UP);
|
||||
|
||||
gpio_set_pin_function(M2_HALLB,
|
||||
// <y> Pin function
|
||||
// <id> pad_function
|
||||
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
|
||||
// <PINMUX_PA23N_CCL_IN7"> Auto
|
||||
// <GPIO_PIN_FUNCTION_OFF"> Off
|
||||
// <GPIO_PIN_FUNCTION_A"> A
|
||||
// <GPIO_PIN_FUNCTION_B"> B
|
||||
// <GPIO_PIN_FUNCTION_C"> C
|
||||
// <GPIO_PIN_FUNCTION_D"> D
|
||||
// <GPIO_PIN_FUNCTION_E"> E
|
||||
// <GPIO_PIN_FUNCTION_F"> F
|
||||
// <GPIO_PIN_FUNCTION_G"> G
|
||||
// <GPIO_PIN_FUNCTION_H"> H
|
||||
// <GPIO_PIN_FUNCTION_I"> I
|
||||
// <GPIO_PIN_FUNCTION_J"> J
|
||||
// <GPIO_PIN_FUNCTION_K"> K
|
||||
// <GPIO_PIN_FUNCTION_L"> L
|
||||
// <GPIO_PIN_FUNCTION_M"> M
|
||||
// <GPIO_PIN_FUNCTION_N"> N
|
||||
GPIO_PIN_FUNCTION_N);
|
||||
|
||||
gpio_set_pin_direction(M2_HALLC,
|
||||
// <y> Pin direction
|
||||
// <id> pad_direction
|
||||
// <GPIO_DIRECTION_OFF"> Off
|
||||
// <GPIO_DIRECTION_IN"> In
|
||||
// <GPIO_DIRECTION_OUT"> Out
|
||||
GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_level(M2_HALLC,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
gpio_set_pin_pull_mode(M2_HALLC,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_UP);
|
||||
|
||||
gpio_set_pin_function(M2_HALLC,
|
||||
// <y> Pin function
|
||||
// <id> pad_function
|
||||
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
|
||||
// <PINMUX_PA24N_CCL_IN8"> Auto
|
||||
// <GPIO_PIN_FUNCTION_OFF"> Off
|
||||
// <GPIO_PIN_FUNCTION_A"> A
|
||||
// <GPIO_PIN_FUNCTION_B"> B
|
||||
// <GPIO_PIN_FUNCTION_C"> C
|
||||
// <GPIO_PIN_FUNCTION_D"> D
|
||||
// <GPIO_PIN_FUNCTION_E"> E
|
||||
// <GPIO_PIN_FUNCTION_F"> F
|
||||
// <GPIO_PIN_FUNCTION_G"> G
|
||||
// <GPIO_PIN_FUNCTION_H"> H
|
||||
// <GPIO_PIN_FUNCTION_I"> I
|
||||
// <GPIO_PIN_FUNCTION_J"> J
|
||||
// <GPIO_PIN_FUNCTION_K"> K
|
||||
// <GPIO_PIN_FUNCTION_L"> L
|
||||
// <GPIO_PIN_FUNCTION_M"> M
|
||||
// <GPIO_PIN_FUNCTION_N"> N
|
||||
GPIO_PIN_FUNCTION_N);
|
||||
}
|
||||
|
||||
void DIGITAL_GLUE_LOGIC_0_CLOCK_init(void)
|
||||
{
|
||||
hri_mclk_set_APBCMASK_CCL_bit(MCLK);
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, CCL_GCLK_ID, CONF_GCLK_CCL_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
}
|
||||
|
||||
void DIGITAL_GLUE_LOGIC_0_init(void)
|
||||
{
|
||||
DIGITAL_GLUE_LOGIC_0_CLOCK_init();
|
||||
custom_logic_init();
|
||||
DIGITAL_GLUE_LOGIC_0_PORT_init();
|
||||
}
|
||||
|
||||
void EXTERNAL_IRQ_0_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_mclk_set_APBAMASK_EIC_bit(MCLK);
|
||||
|
||||
// Set pin direction to input
|
||||
gpio_set_pin_direction(ECAT_SYNC, GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_pull_mode(ECAT_SYNC,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(ECAT_SYNC, PINMUX_PA07A_EIC_EXTINT7);
|
||||
|
||||
// Set pin direction to input
|
||||
gpio_set_pin_direction(M1_RST_Bar, GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_pull_mode(M1_RST_Bar,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(M1_RST_Bar, PINMUX_PB30A_EIC_EXTINT14);
|
||||
|
||||
// Set pin direction to input
|
||||
gpio_set_pin_direction(M2_RST_Bar, GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_pull_mode(M2_RST_Bar,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(M2_RST_Bar, PINMUX_PB31A_EIC_EXTINT15);
|
||||
|
||||
ext_irq_init();
|
||||
}
|
||||
|
||||
void EVENT_SYSTEM_0_init(void)
|
||||
{
|
||||
|
||||
hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);
|
||||
|
||||
event_system_init();
|
||||
}
|
||||
|
||||
void QUAD_SPI_0_PORT_init(void)
|
||||
{
|
||||
|
||||
// Set pin direction to input
|
||||
gpio_set_pin_direction(ECAT_QSPI_CS, GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_pull_mode(ECAT_QSPI_CS,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(ECAT_QSPI_CS, PINMUX_PB11H_QSPI_CS);
|
||||
|
||||
gpio_set_pin_direction(ECAT_QSPI_MOSI,
|
||||
// <y> Pin direction
|
||||
// <id> pad_direction
|
||||
// <GPIO_DIRECTION_OFF"> Off
|
||||
// <GPIO_DIRECTION_IN"> In
|
||||
// <GPIO_DIRECTION_OUT"> Out
|
||||
GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_level(ECAT_QSPI_MOSI,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
gpio_set_pin_pull_mode(ECAT_QSPI_MOSI,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(ECAT_QSPI_MOSI,
|
||||
// <y> Pin function
|
||||
// <id> pad_function
|
||||
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
|
||||
// <PINMUX_PA08H_QSPI_DATA0"> Auto
|
||||
// <GPIO_PIN_FUNCTION_OFF"> Off
|
||||
// <GPIO_PIN_FUNCTION_A"> A
|
||||
// <GPIO_PIN_FUNCTION_B"> B
|
||||
// <GPIO_PIN_FUNCTION_C"> C
|
||||
// <GPIO_PIN_FUNCTION_D"> D
|
||||
// <GPIO_PIN_FUNCTION_E"> E
|
||||
// <GPIO_PIN_FUNCTION_F"> F
|
||||
// <GPIO_PIN_FUNCTION_G"> G
|
||||
// <GPIO_PIN_FUNCTION_H"> H
|
||||
// <GPIO_PIN_FUNCTION_I"> I
|
||||
// <GPIO_PIN_FUNCTION_J"> J
|
||||
// <GPIO_PIN_FUNCTION_K"> K
|
||||
// <GPIO_PIN_FUNCTION_L"> L
|
||||
// <GPIO_PIN_FUNCTION_M"> M
|
||||
// <GPIO_PIN_FUNCTION_N"> N
|
||||
PINMUX_PA08H_QSPI_DATA0);
|
||||
|
||||
gpio_set_pin_direction(ECAT_QSPI_MISO,
|
||||
// <y> Pin direction
|
||||
// <id> pad_direction
|
||||
// <GPIO_DIRECTION_OFF"> Off
|
||||
// <GPIO_DIRECTION_IN"> In
|
||||
// <GPIO_DIRECTION_OUT"> Out
|
||||
GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_level(ECAT_QSPI_MISO,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
gpio_set_pin_pull_mode(ECAT_QSPI_MISO,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(ECAT_QSPI_MISO,
|
||||
// <y> Pin function
|
||||
// <id> pad_function
|
||||
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
|
||||
// <PINMUX_PA09H_QSPI_DATA1"> Auto
|
||||
// <GPIO_PIN_FUNCTION_OFF"> Off
|
||||
// <GPIO_PIN_FUNCTION_A"> A
|
||||
// <GPIO_PIN_FUNCTION_B"> B
|
||||
// <GPIO_PIN_FUNCTION_C"> C
|
||||
// <GPIO_PIN_FUNCTION_D"> D
|
||||
// <GPIO_PIN_FUNCTION_E"> E
|
||||
// <GPIO_PIN_FUNCTION_F"> F
|
||||
// <GPIO_PIN_FUNCTION_G"> G
|
||||
// <GPIO_PIN_FUNCTION_H"> H
|
||||
// <GPIO_PIN_FUNCTION_I"> I
|
||||
// <GPIO_PIN_FUNCTION_J"> J
|
||||
// <GPIO_PIN_FUNCTION_K"> K
|
||||
// <GPIO_PIN_FUNCTION_L"> L
|
||||
// <GPIO_PIN_FUNCTION_M"> M
|
||||
// <GPIO_PIN_FUNCTION_N"> N
|
||||
PINMUX_PA09H_QSPI_DATA1);
|
||||
|
||||
gpio_set_pin_direction(ECAT_QSPI_DATA2,
|
||||
// <y> Pin direction
|
||||
// <id> pad_direction
|
||||
// <GPIO_DIRECTION_OFF"> Off
|
||||
// <GPIO_DIRECTION_IN"> In
|
||||
// <GPIO_DIRECTION_OUT"> Out
|
||||
GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_level(ECAT_QSPI_DATA2,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
gpio_set_pin_pull_mode(ECAT_QSPI_DATA2,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(ECAT_QSPI_DATA2,
|
||||
// <y> Pin function
|
||||
// <id> pad_function
|
||||
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
|
||||
// <PINMUX_PA10H_QSPI_DATA2"> Auto
|
||||
// <GPIO_PIN_FUNCTION_OFF"> Off
|
||||
// <GPIO_PIN_FUNCTION_A"> A
|
||||
// <GPIO_PIN_FUNCTION_B"> B
|
||||
// <GPIO_PIN_FUNCTION_C"> C
|
||||
// <GPIO_PIN_FUNCTION_D"> D
|
||||
// <GPIO_PIN_FUNCTION_E"> E
|
||||
// <GPIO_PIN_FUNCTION_F"> F
|
||||
// <GPIO_PIN_FUNCTION_G"> G
|
||||
// <GPIO_PIN_FUNCTION_H"> H
|
||||
// <GPIO_PIN_FUNCTION_I"> I
|
||||
// <GPIO_PIN_FUNCTION_J"> J
|
||||
// <GPIO_PIN_FUNCTION_K"> K
|
||||
// <GPIO_PIN_FUNCTION_L"> L
|
||||
// <GPIO_PIN_FUNCTION_M"> M
|
||||
// <GPIO_PIN_FUNCTION_N"> N
|
||||
PINMUX_PA10H_QSPI_DATA2);
|
||||
|
||||
gpio_set_pin_direction(ECAT_QSPI_DATA3,
|
||||
// <y> Pin direction
|
||||
// <id> pad_direction
|
||||
// <GPIO_DIRECTION_OFF"> Off
|
||||
// <GPIO_DIRECTION_IN"> In
|
||||
// <GPIO_DIRECTION_OUT"> Out
|
||||
GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_level(ECAT_QSPI_DATA3,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
gpio_set_pin_pull_mode(ECAT_QSPI_DATA3,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(ECAT_QSPI_DATA3,
|
||||
// <y> Pin function
|
||||
// <id> pad_function
|
||||
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
|
||||
// <PINMUX_PA11H_QSPI_DATA3"> Auto
|
||||
// <GPIO_PIN_FUNCTION_OFF"> Off
|
||||
// <GPIO_PIN_FUNCTION_A"> A
|
||||
// <GPIO_PIN_FUNCTION_B"> B
|
||||
// <GPIO_PIN_FUNCTION_C"> C
|
||||
// <GPIO_PIN_FUNCTION_D"> D
|
||||
// <GPIO_PIN_FUNCTION_E"> E
|
||||
// <GPIO_PIN_FUNCTION_F"> F
|
||||
// <GPIO_PIN_FUNCTION_G"> G
|
||||
// <GPIO_PIN_FUNCTION_H"> H
|
||||
// <GPIO_PIN_FUNCTION_I"> I
|
||||
// <GPIO_PIN_FUNCTION_J"> J
|
||||
// <GPIO_PIN_FUNCTION_K"> K
|
||||
// <GPIO_PIN_FUNCTION_L"> L
|
||||
// <GPIO_PIN_FUNCTION_M"> M
|
||||
// <GPIO_PIN_FUNCTION_N"> N
|
||||
PINMUX_PA11H_QSPI_DATA3);
|
||||
|
||||
// Set pin direction to input
|
||||
gpio_set_pin_direction(ECAT_QSPI_SCK, GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_pull_mode(ECAT_QSPI_SCK,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(ECAT_QSPI_SCK, PINMUX_PB10H_QSPI_SCK);
|
||||
}
|
||||
|
||||
void QUAD_SPI_0_CLOCK_init(void)
|
||||
{
|
||||
hri_mclk_set_AHBMASK_QSPI_bit(MCLK);
|
||||
hri_mclk_set_AHBMASK_QSPI_2X_bit(MCLK);
|
||||
hri_mclk_set_APBCMASK_QSPI_bit(MCLK);
|
||||
}
|
||||
|
||||
void QUAD_SPI_0_init(void)
|
||||
{
|
||||
QUAD_SPI_0_CLOCK_init();
|
||||
qspi_sync_init(&QUAD_SPI_0, QSPI);
|
||||
QUAD_SPI_0_PORT_init();
|
||||
}
|
||||
|
||||
void SPI_1_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_level(SPI1_MOSI,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(SPI1_MOSI, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(SPI1_MOSI, PINMUX_PA00D_SERCOM1_PAD0);
|
||||
|
||||
gpio_set_pin_level(SPI1_SCK,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(SPI1_SCK, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(SPI1_SCK, PINMUX_PA01D_SERCOM1_PAD1);
|
||||
|
||||
// Set pin direction to input
|
||||
gpio_set_pin_direction(SPI1_MISO, GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_pull_mode(SPI1_MISO,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(SPI1_MISO, PINMUX_PB23C_SERCOM1_PAD3);
|
||||
}
|
||||
|
||||
void SPI_1_CLOCK_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
hri_mclk_set_APBAMASK_SERCOM1_bit(MCLK);
|
||||
}
|
||||
|
||||
void SPI_1_init(void)
|
||||
{
|
||||
SPI_1_CLOCK_init();
|
||||
spi_m_sync_init(&SPI_1, SERCOM1);
|
||||
SPI_1_PORT_init();
|
||||
}
|
||||
|
||||
void SPI_2_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_level(SPI2_MOSI,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(SPI2_MOSI, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(SPI2_MOSI, PINMUX_PA12C_SERCOM2_PAD0);
|
||||
|
||||
gpio_set_pin_level(SPI2_SCK,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(SPI2_SCK, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(SPI2_SCK, PINMUX_PA13C_SERCOM2_PAD1);
|
||||
|
||||
// Set pin direction to input
|
||||
gpio_set_pin_direction(SPI2_MISO, GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_pull_mode(SPI2_MISO,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(SPI2_MISO, PINMUX_PA15C_SERCOM2_PAD3);
|
||||
}
|
||||
|
||||
void SPI_2_CLOCK_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
|
||||
}
|
||||
|
||||
void SPI_2_init(void)
|
||||
{
|
||||
SPI_2_CLOCK_init();
|
||||
spi_m_async_init(&SPI_2, SERCOM2);
|
||||
SPI_2_PORT_init();
|
||||
}
|
||||
|
||||
void SPI_3_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_level(SPI3_MOSI,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(SPI3_MOSI, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(SPI3_MOSI, PINMUX_PB02D_SERCOM5_PAD0);
|
||||
|
||||
gpio_set_pin_level(SPI3_SCK,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(SPI3_SCK, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(SPI3_SCK, PINMUX_PB03D_SERCOM5_PAD1);
|
||||
|
||||
// Set pin direction to input
|
||||
gpio_set_pin_direction(SPI3_MISO, GPIO_DIRECTION_IN);
|
||||
|
||||
gpio_set_pin_pull_mode(SPI3_MISO,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(SPI3_MISO, PINMUX_PB01D_SERCOM5_PAD3);
|
||||
}
|
||||
|
||||
void SPI_3_CLOCK_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_CORE, CONF_GCLK_SERCOM5_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_SLOW, CONF_GCLK_SERCOM5_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
hri_mclk_set_APBDMASK_SERCOM5_bit(MCLK);
|
||||
}
|
||||
|
||||
void SPI_3_init(void)
|
||||
{
|
||||
SPI_3_CLOCK_init();
|
||||
spi_m_sync_init(&SPI_3, SERCOM5);
|
||||
SPI_3_PORT_init();
|
||||
}
|
||||
|
||||
void PWM_0_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_function(M1_PWMA, PINMUX_PB12G_TCC0_WO0);
|
||||
|
||||
gpio_set_pin_function(M1_PWMB, PINMUX_PB13G_TCC0_WO1);
|
||||
|
||||
gpio_set_pin_function(M1_PWMC, PINMUX_PB14G_TCC0_WO2);
|
||||
|
||||
gpio_set_pin_function(M1_ENA, PINMUX_PB15G_TCC0_WO3);
|
||||
|
||||
gpio_set_pin_function(M1_ENB, PINMUX_PB16G_TCC0_WO4);
|
||||
|
||||
gpio_set_pin_function(M1_ENC, PINMUX_PB17G_TCC0_WO5);
|
||||
}
|
||||
|
||||
void PWM_0_CLOCK_init(void)
|
||||
{
|
||||
|
||||
hri_mclk_set_APBBMASK_TCC0_bit(MCLK);
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, CONF_GCLK_TCC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
}
|
||||
|
||||
void PWM_0_init(void)
|
||||
{
|
||||
PWM_0_CLOCK_init();
|
||||
PWM_0_PORT_init();
|
||||
pwm_init(&PWM_0, TCC0, _tcc_get_pwm());
|
||||
}
|
||||
|
||||
void PWM_1_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_function(M2_PWMA, PINMUX_PA16F_TCC1_WO0);
|
||||
|
||||
gpio_set_pin_function(M2_PWMB, PINMUX_PA17F_TCC1_WO1);
|
||||
|
||||
gpio_set_pin_function(M2_PWMC, PINMUX_PA18F_TCC1_WO2);
|
||||
|
||||
gpio_set_pin_function(M2_ENA, PINMUX_PA19F_TCC1_WO3);
|
||||
|
||||
gpio_set_pin_function(M2_ENB, PINMUX_PA20F_TCC1_WO4);
|
||||
|
||||
gpio_set_pin_function(M2_ENC, PINMUX_PA21F_TCC1_WO5);
|
||||
}
|
||||
|
||||
void PWM_1_CLOCK_init(void)
|
||||
{
|
||||
|
||||
hri_mclk_set_APBBMASK_TCC1_bit(MCLK);
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, TCC1_GCLK_ID, CONF_GCLK_TCC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
}
|
||||
|
||||
void PWM_1_init(void)
|
||||
{
|
||||
PWM_1_CLOCK_init();
|
||||
PWM_1_PORT_init();
|
||||
pwm_init(&PWM_1, TCC1, _tcc_get_pwm());
|
||||
}
|
||||
|
||||
void system_init(void)
|
||||
{
|
||||
init_mcu();
|
||||
|
||||
// GPIO on PA03
|
||||
|
||||
// Disable digital pin circuitry
|
||||
gpio_set_pin_direction(ANAREF_2V48, GPIO_DIRECTION_OFF);
|
||||
|
||||
gpio_set_pin_function(ANAREF_2V48, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PA14
|
||||
|
||||
gpio_set_pin_function(SPI2_SS, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PA25
|
||||
|
||||
gpio_set_pin_level(M1_RST,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(M1_RST, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(M1_RST, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PA27
|
||||
|
||||
gpio_set_pin_level(M2_RST,
|
||||
// <y> Initial level
|
||||
// <id> pad_initial_level
|
||||
// <false"> Low
|
||||
// <true"> High
|
||||
false);
|
||||
|
||||
// Set pin direction to output
|
||||
gpio_set_pin_direction(M2_RST, GPIO_DIRECTION_OUT);
|
||||
|
||||
gpio_set_pin_function(M2_RST, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PB00
|
||||
|
||||
gpio_set_pin_function(SPI3_SS, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PB08
|
||||
|
||||
// Disable digital pin circuitry
|
||||
gpio_set_pin_direction(half_VREF, GPIO_DIRECTION_OFF);
|
||||
|
||||
gpio_set_pin_function(half_VREF, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// GPIO on PB22
|
||||
|
||||
gpio_set_pin_function(SPI1_CS, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
ADC_0_init();
|
||||
|
||||
ADC_1_init();
|
||||
|
||||
DIGITAL_GLUE_LOGIC_0_init();
|
||||
|
||||
EXTERNAL_IRQ_0_init();
|
||||
|
||||
EVENT_SYSTEM_0_init();
|
||||
|
||||
QUAD_SPI_0_init();
|
||||
|
||||
SPI_1_init();
|
||||
|
||||
SPI_2_init();
|
||||
|
||||
SPI_3_init();
|
||||
|
||||
PWM_0_init();
|
||||
|
||||
PWM_1_init();
|
||||
}
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef DRIVER_INIT_INCLUDED
|
||||
#define DRIVER_INIT_INCLUDED
|
||||
|
||||
#include "atmel_start_pins.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <hal_atomic.h>
|
||||
#include <hal_delay.h>
|
||||
#include <hal_gpio.h>
|
||||
#include <hal_init.h>
|
||||
#include <hal_io.h>
|
||||
#include <hal_sleep.h>
|
||||
|
||||
#include <hal_adc_sync.h>
|
||||
|
||||
#include <hal_adc_sync.h>
|
||||
|
||||
#include <hal_custom_logic.h>
|
||||
|
||||
#include <hal_ext_irq.h>
|
||||
|
||||
#include <hal_evsys.h>
|
||||
|
||||
#include <hal_qspi_sync.h>
|
||||
|
||||
#include <hal_spi_m_sync.h>
|
||||
|
||||
#include <hal_spi_m_async.h>
|
||||
#include <hal_spi_m_sync.h>
|
||||
|
||||
#include <hal_pwm.h>
|
||||
#include <hpl_tcc.h>
|
||||
|
||||
#include <hal_pwm.h>
|
||||
#include <hpl_tcc.h>
|
||||
|
||||
extern struct adc_sync_descriptor ADC_0;
|
||||
|
||||
extern struct adc_sync_descriptor ADC_1;
|
||||
|
||||
extern struct qspi_sync_descriptor QUAD_SPI_0;
|
||||
extern struct spi_m_sync_descriptor SPI_1;
|
||||
|
||||
extern struct spi_m_async_descriptor SPI_2;
|
||||
extern struct spi_m_sync_descriptor SPI_3;
|
||||
|
||||
extern struct pwm_descriptor PWM_0;
|
||||
|
||||
extern struct pwm_descriptor PWM_1;
|
||||
|
||||
void ADC_0_PORT_init(void);
|
||||
void ADC_0_CLOCK_init(void);
|
||||
void ADC_0_init(void);
|
||||
|
||||
void ADC_1_PORT_init(void);
|
||||
void ADC_1_CLOCK_init(void);
|
||||
void ADC_1_init(void);
|
||||
|
||||
void DIGITAL_GLUE_LOGIC_0_PORT_init(void);
|
||||
void DIGITAL_GLUE_LOGIC_0_CLOCK_init(void);
|
||||
void DIGITAL_GLUE_LOGIC_0_init(void);
|
||||
|
||||
void QUAD_SPI_0_PORT_init(void);
|
||||
void QUAD_SPI_0_CLOCK_init(void);
|
||||
void QUAD_SPI_0_init(void);
|
||||
|
||||
void SPI_1_PORT_init(void);
|
||||
void SPI_1_CLOCK_init(void);
|
||||
void SPI_1_init(void);
|
||||
|
||||
void SPI_2_PORT_init(void);
|
||||
void SPI_2_CLOCK_init(void);
|
||||
void SPI_2_init(void);
|
||||
|
||||
void SPI_3_PORT_init(void);
|
||||
void SPI_3_CLOCK_init(void);
|
||||
void SPI_3_init(void);
|
||||
|
||||
void PWM_0_PORT_init(void);
|
||||
void PWM_0_CLOCK_init(void);
|
||||
void PWM_0_init(void);
|
||||
|
||||
void PWM_1_PORT_init(void);
|
||||
void PWM_1_CLOCK_init(void);
|
||||
void PWM_1_init(void);
|
||||
|
||||
/**
|
||||
* \brief Perform system initialization, initialize pins and clocks for
|
||||
* peripherals
|
||||
*/
|
||||
void system_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif // DRIVER_INIT_INCLUDED
|
||||
|
|
@ -0,0 +1,166 @@
|
|||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
|
||||
#include "driver_examples.h"
|
||||
#include "driver_init.h"
|
||||
#include "utils.h"
|
||||
|
||||
/**
|
||||
* Example of using ADC_0 to generate waveform.
|
||||
*/
|
||||
void ADC_0_example(void)
|
||||
{
|
||||
uint8_t buffer[2];
|
||||
|
||||
adc_sync_enable_channel(&ADC_0, 0);
|
||||
|
||||
while (1) {
|
||||
adc_sync_read_channel(&ADC_0, 0, buffer, 2);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using ADC_1 to generate waveform.
|
||||
*/
|
||||
void ADC_1_example(void)
|
||||
{
|
||||
uint8_t buffer[2];
|
||||
|
||||
adc_sync_enable_channel(&ADC_1, 0);
|
||||
|
||||
while (1) {
|
||||
adc_sync_read_channel(&ADC_1, 0, buffer, 2);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using DIGITAL_GLUE_LOGIC_0.
|
||||
*/
|
||||
void DIGITAL_GLUE_LOGIC_0_example(void)
|
||||
{
|
||||
custom_logic_enable();
|
||||
/* Customer logic now works. */
|
||||
}
|
||||
|
||||
static void button_on_PA07_pressed(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void button_on_PB30_pressed(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void button_on_PB31_pressed(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using EXTERNAL_IRQ_0
|
||||
*/
|
||||
void EXTERNAL_IRQ_0_example(void)
|
||||
{
|
||||
|
||||
ext_irq_register(PIN_PA07, button_on_PA07_pressed);
|
||||
ext_irq_register(PIN_PB30, button_on_PB30_pressed);
|
||||
ext_irq_register(PIN_PB31, button_on_PB31_pressed);
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using QUAD_SPI_0 to get N25Q256A status value,
|
||||
* and check bit 0 which indicate embedded operation is busy or not.
|
||||
*/
|
||||
void QUAD_SPI_0_example(void)
|
||||
{
|
||||
uint8_t status = 0xFF;
|
||||
struct _qspi_command cmd = {
|
||||
.inst_frame.bits.inst_en = 1,
|
||||
.inst_frame.bits.data_en = 1,
|
||||
.inst_frame.bits.tfr_type = QSPI_READ_ACCESS,
|
||||
.instruction = 0x05,
|
||||
.buf_len = 1,
|
||||
.rx_buf = &status,
|
||||
};
|
||||
|
||||
qspi_sync_enable(&QUAD_SPI_0);
|
||||
while (status & (1 << 0)) {
|
||||
qspi_sync_serial_run_command(&QUAD_SPI_0, &cmd);
|
||||
}
|
||||
qspi_sync_deinit(&QUAD_SPI_0);
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using SPI_1 to write "Hello World" using the IO abstraction.
|
||||
*/
|
||||
static uint8_t example_SPI_1[12] = "Hello World!";
|
||||
|
||||
void SPI_1_example(void)
|
||||
{
|
||||
struct io_descriptor *io;
|
||||
spi_m_sync_get_io_descriptor(&SPI_1, &io);
|
||||
|
||||
spi_m_sync_enable(&SPI_1);
|
||||
io_write(io, example_SPI_1, 12);
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using SPI_2 to write "Hello World" using the IO abstraction.
|
||||
*
|
||||
* Since the driver is asynchronous we need to use statically allocated memory for string
|
||||
* because driver initiates transfer and then returns before the transmission is completed.
|
||||
*
|
||||
* Once transfer has been completed the tx_cb function will be called.
|
||||
*/
|
||||
|
||||
static uint8_t example_SPI_2[12] = "Hello World!";
|
||||
|
||||
static void complete_cb_SPI_2(const struct spi_m_async_descriptor *const io_descr)
|
||||
{
|
||||
/* Transfer completed */
|
||||
}
|
||||
|
||||
void SPI_2_example(void)
|
||||
{
|
||||
struct io_descriptor *io;
|
||||
spi_m_async_get_io_descriptor(&SPI_2, &io);
|
||||
|
||||
spi_m_async_register_callback(&SPI_2, SPI_M_ASYNC_CB_XFER, (FUNC_PTR)complete_cb_SPI_2);
|
||||
spi_m_async_enable(&SPI_2);
|
||||
io_write(io, example_SPI_2, 12);
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using SPI_3 to write "Hello World" using the IO abstraction.
|
||||
*/
|
||||
static uint8_t example_SPI_3[12] = "Hello World!";
|
||||
|
||||
void SPI_3_example(void)
|
||||
{
|
||||
struct io_descriptor *io;
|
||||
spi_m_sync_get_io_descriptor(&SPI_3, &io);
|
||||
|
||||
spi_m_sync_enable(&SPI_3);
|
||||
io_write(io, example_SPI_3, 12);
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using PWM_0.
|
||||
*/
|
||||
void PWM_0_example(void)
|
||||
{
|
||||
pwm_set_parameters(&PWM_0, 10000, 5000);
|
||||
pwm_enable(&PWM_0);
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using PWM_1.
|
||||
*/
|
||||
void PWM_1_example(void)
|
||||
{
|
||||
pwm_set_parameters(&PWM_1, 10000, 5000);
|
||||
pwm_enable(&PWM_1);
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef DRIVER_EXAMPLES_H_INCLUDED
|
||||
#define DRIVER_EXAMPLES_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void ADC_0_example(void);
|
||||
|
||||
void ADC_1_example(void);
|
||||
|
||||
void DIGITAL_GLUE_LOGIC_0_example(void);
|
||||
|
||||
void EXTERNAL_IRQ_0_example(void);
|
||||
|
||||
void QUAD_SPI_0_example(void);
|
||||
|
||||
void SPI_2_example(void);
|
||||
|
||||
void PWM_0_example(void);
|
||||
|
||||
void PWM_1_example(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif // DRIVER_EXAMPLES_H_INCLUDED
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
======================
|
||||
ADC Synchronous driver
|
||||
======================
|
||||
|
||||
An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
|
||||
A reference signal with a known voltage level is quantified into equally
|
||||
sized chunks, each representing a digital value from 0 to the highest number
|
||||
possible with the bit resolution supported by the ADC. The input voltage
|
||||
measured by the ADC is compared against these chunks and the chunk with the
|
||||
closest voltage level defines the digital value that can be used to represent
|
||||
the analog input voltage level.
|
||||
|
||||
Usually an ADC can operate in either differential or single-ended mode.
|
||||
In differential mode two signals (V+ and V-) are compared against each other
|
||||
and the resulting digital value represents the relative voltage level between
|
||||
V+ and V-. This means that if the input voltage level on V+ is lower than on
|
||||
V- the digital value is negative, which also means that in differential
|
||||
mode one bit is lost to the sign. In single-ended mode only V+ is compared
|
||||
against the reference voltage, and the resulting digital value can only be
|
||||
positive, but the full bit-range of the ADC can be used.
|
||||
|
||||
Usually multiple resolutions are supported by the ADC, lower resolution can
|
||||
reduce the conversion time, but lose accuracy.
|
||||
|
||||
Some ADCs has a gain stage on the input lines which can be used to increase the
|
||||
dynamic range. The default gain value is usually x1, which means that the
|
||||
conversion range is from 0V to the reference voltage.
|
||||
Applications can change the gain stage, to increase or reduce the conversion
|
||||
range.
|
||||
|
||||
The window mode allows the conversion result to be compared to a set of
|
||||
predefined threshold values. Applications can use callback function to monitor
|
||||
if the conversion result exceeds predefined threshold value.
|
||||
|
||||
Usually multiple reference voltages are supported by the ADC, both internal and
|
||||
external with difference voltage levels. The reference voltage have an impact
|
||||
on the accuracy, and should be selected to cover the full range of the analog
|
||||
input signal and never less than the expected maximum input voltage.
|
||||
|
||||
There are two conversion modes supported by ADC, single shot and free running.
|
||||
In single shot mode the ADC only make one conversion when triggered by the
|
||||
application, in free running mode it continues to make conversion from it
|
||||
is triggered until it is stopped by the application. When window monitoring,
|
||||
the ADC should be set to free running mode.
|
||||
|
||||
Features
|
||||
--------
|
||||
* Initialization and de-initialization
|
||||
* Support multiple Conversion Mode, Single or Free run
|
||||
* Start ADC Conversion
|
||||
* Read Conversion Result
|
||||
|
||||
Applications
|
||||
------------
|
||||
* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
|
||||
* Measurement of external sensor. E.g., Temperature, humidity sensor value.
|
||||
* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
* ADC hardware
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
N/A
|
||||
|
||||
Knows issues and workarounds
|
||||
----------------------------
|
||||
N/A
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
===========================================================
|
||||
Digital Glue Logic based on Configurable Custom Logic (CCL)
|
||||
===========================================================
|
||||
|
||||
Custom logic driver offers a way to initialize on-chip programmable logic
|
||||
units, so that a specific logic box is built. Then this "box" can be connected
|
||||
to internal or external circuit to perform the logic operations.
|
||||
|
||||
Features
|
||||
--------
|
||||
* Initialization and de-initialization
|
||||
* Enabling and disabling
|
||||
|
||||
Applications
|
||||
------------
|
||||
* Connected to external circuit, as a logic operation box, e.g., as adder.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
* Programmable logic control units
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
N/A
|
||||
|
||||
Knows issues and workarounds
|
||||
----------------------------
|
||||
N/A
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
==============
|
||||
EXT IRQ driver
|
||||
==============
|
||||
|
||||
The External Interrupt driver allows external pins to be
|
||||
configured as interrupt lines. Each interrupt line can be
|
||||
individually masked and can generate an interrupt on rising,
|
||||
falling or both edges, or on high or low levels. Some of
|
||||
external pin can also be configured to wake up the device
|
||||
from sleep modes where all clocks have been disabled.
|
||||
External pins can also generate an event.
|
||||
|
||||
Features
|
||||
--------
|
||||
* Initialization and de-initialization
|
||||
* Enabling and disabling
|
||||
* Detect external pins interrupt
|
||||
|
||||
Applications
|
||||
------------
|
||||
* Generate an interrupt on rising, falling or both edges,
|
||||
or on high or low levels.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
* GPIO hardware
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
N/A
|
||||
|
||||
Knows issues and workarounds
|
||||
----------------------------
|
||||
N/A
|
||||
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
The PWM Driver(bare-bone)
|
||||
=========================
|
||||
|
||||
Pulse-width modulation (PWM) is used to create an analog behavior
|
||||
digitally by controlling the amount of power transferred to the
|
||||
connected peripheral. This is achieved by controlling the high period
|
||||
(duty-cycle) of a periodic signal.
|
||||
|
||||
User can change the period or duty cycle whenever PWM is running. The
|
||||
function pwm_set_parameters is used to configure these two parameters.
|
||||
Note these are raw register values and the parameter duty_cycle means
|
||||
the period of first half during one cycle, which should be not beyond
|
||||
total period value.
|
||||
|
||||
In addition, user can also get multi PWM channels output from different
|
||||
peripherals at the same time, which is implemented more flexible by the
|
||||
function pointers.
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
* Initialization/de-initialization
|
||||
* Enabling/disabling
|
||||
* Run-time control of PWM duty-cycle and period
|
||||
* Notifications about errors and one PWM cycle is done
|
||||
|
||||
Applications
|
||||
------------
|
||||
|
||||
Motor control, ballast, LED, H-bridge, power converters, and
|
||||
other types of power control applications.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
The peripheral which can perform waveform generation like frequency
|
||||
generation and pulse-width modulation, such as Timer/Counter.
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
The current driver doesn't support the features like recoverable,
|
||||
non-recoverable faults, dithering, dead-time insertion.
|
||||
|
||||
Known issues and workarounds
|
||||
----------------------------
|
||||
|
||||
N/A
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
The Quad SPI Synchronous Driver
|
||||
=================================
|
||||
|
||||
The Quad SPI Interface (QSPI) is a synchronous serial data link that provides
|
||||
communication with external devices in master mode.
|
||||
|
||||
The driver can be used for SPI serial memory middleware which support flash
|
||||
earse, program and read.
|
||||
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
* Initialization/de-initialization
|
||||
* Enabling/disabling
|
||||
* Execute command in Serial Memory Mode
|
||||
|
||||
Applications
|
||||
------------
|
||||
|
||||
They are commonly used in an application for using serial flash memory operating
|
||||
in single-bit SPI, Dual SPI and Quad SPI.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
Serial NOR flash with Multiple I/O hardware
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
N.A
|
||||
|
||||
Known issues and workarounds
|
||||
----------------------------
|
||||
|
||||
N/A
|
||||
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
The SPI Master Asynchronous Driver
|
||||
==================================
|
||||
|
||||
The serial peripheral interface (SPI) is a synchronous serial communication
|
||||
interface.
|
||||
|
||||
SPI devices communicate in full duplex mode using a master-slave
|
||||
architecture with a single master. The master device originates the frame for
|
||||
reading and writing. Multiple slave devices are supported through selection
|
||||
with individual slave select (SS) lines.
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
* Initialization/de-initialization
|
||||
* Enabling/disabling
|
||||
* Control of the following settings:
|
||||
|
||||
* Baudrate
|
||||
* SPI mode
|
||||
* Character size
|
||||
* Data order
|
||||
* Data transfer: transmission, reception and full-duplex
|
||||
* Notifications about transfer completion and errors via callbacks
|
||||
* Status information with busy state and transfer count
|
||||
|
||||
Applications
|
||||
------------
|
||||
|
||||
Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card,
|
||||
LCD controller, etc.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
SPI master capable hardware, with interrupt on each character sent/received.
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
The slave select (SS) is not automatically inserted during read/write/transfer,
|
||||
user must use I/O to control the devices' SS.
|
||||
|
||||
While read/write/transfer is in progress, the data buffer used must be kept
|
||||
unchanged.
|
||||
|
||||
Known issues and workarounds
|
||||
----------------------------
|
||||
|
||||
N/A
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
The SPI Master Synchronous Driver
|
||||
=================================
|
||||
|
||||
The serial peripheral interface (SPI) is a synchronous serial communication
|
||||
interface.
|
||||
|
||||
SPI devices communicate in full duplex mode using a master-slave
|
||||
architecture with a single master. The master device originates the frame for
|
||||
reading and writing. Multiple slave devices are supported through selection
|
||||
with individual slave select (SS) lines.
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
* Initialization/de-initialization
|
||||
* Enabling/disabling
|
||||
* Control of the following settings:
|
||||
|
||||
* Baudrate
|
||||
* SPI mode
|
||||
* Character size
|
||||
* Data order
|
||||
* Data transfer: transmission, reception and full-duplex
|
||||
|
||||
Applications
|
||||
------------
|
||||
|
||||
Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card,
|
||||
LCD controller, etc.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
SPI master capable hardware
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
The slave select (SS) is not automatically inserted during read/write/transfer,
|
||||
user must use I/O to control the devices' SS.
|
||||
|
||||
Known issues and workarounds
|
||||
----------------------------
|
||||
|
||||
N/A
|
||||
|
||||
|
|
@ -0,0 +1,277 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief ADC functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_ADC_SYNC_H_INCLUDED
|
||||
#define _HAL_ADC_SYNC_H_INCLUDED
|
||||
|
||||
#include <hpl_adc_sync.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_adc_sync
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief ADC descriptor
|
||||
*
|
||||
* The ADC descriptor forward declaration.
|
||||
*/
|
||||
struct adc_sync_descriptor;
|
||||
|
||||
/**
|
||||
* \brief ADC descriptor
|
||||
*/
|
||||
struct adc_sync_descriptor {
|
||||
/** ADC device */
|
||||
struct _adc_sync_device device;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize ADC
|
||||
*
|
||||
* This function initializes the given ADC descriptor.
|
||||
* It checks if the given hardware is not initialized and if the given hardware
|
||||
* is permitted to be initialized.
|
||||
*
|
||||
* \param[out] descr An ADC descriptor to initialize
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
* \param[in] func The pointer to a set of functions pointers
|
||||
*
|
||||
* \return Initialization status.
|
||||
*/
|
||||
int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize ADC
|
||||
*
|
||||
* This function deinitializes the given ADC descriptor.
|
||||
* It checks if the given hardware is initialized and if the given hardware is
|
||||
* permitted to be deinitialized.
|
||||
*
|
||||
* \param[in] descr An ADC descriptor to deinitialize
|
||||
*
|
||||
* \return De-initialization status.
|
||||
*/
|
||||
int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Enable ADC
|
||||
*
|
||||
* Use this function to set the ADC peripheral to enabled state.
|
||||
*
|
||||
* \param[in] descr Pointer to the ADC descriptor
|
||||
* \param[in] channel Channel number
|
||||
*
|
||||
* \return Operation status
|
||||
*
|
||||
*/
|
||||
int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Disable ADC
|
||||
*
|
||||
* Use this function to set the ADC peripheral to disabled state.
|
||||
*
|
||||
* \param[in] descr Pointer to the ADC descriptor
|
||||
* \param[in] channel Channel number
|
||||
*
|
||||
* \return Operation status
|
||||
*
|
||||
*/
|
||||
int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Read data from ADC
|
||||
*
|
||||
* \param[in] descr The pointer to the ADC descriptor
|
||||
* \param[in] channel Channel number
|
||||
* \param[in] buf A buffer to read data to
|
||||
* \param[in] length The size of a buffer
|
||||
*
|
||||
* \return The number of bytes read.
|
||||
*/
|
||||
int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
|
||||
const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief Set ADC reference source
|
||||
*
|
||||
* This function sets ADC reference source.
|
||||
*
|
||||
* \param[in] descr The pointer to the ADC descriptor
|
||||
* \param[in] reference A reference source to set
|
||||
*
|
||||
* \return Status of the ADC reference source setting.
|
||||
*/
|
||||
int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference);
|
||||
|
||||
/**
|
||||
* \brief Set ADC resolution
|
||||
*
|
||||
* This function sets ADC resolution.
|
||||
*
|
||||
* \param[in] descr The pointer to the ADC descriptor
|
||||
* \param[in] resolution A resolution to set
|
||||
*
|
||||
* \return Status of the ADC resolution setting.
|
||||
*/
|
||||
int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution);
|
||||
|
||||
/**
|
||||
* \brief Set ADC input source of a channel
|
||||
*
|
||||
* This function sets ADC positive and negative input sources.
|
||||
*
|
||||
* \param[in] descr The pointer to the ADC descriptor
|
||||
* \param[in] pos_input A positive input source to set
|
||||
* \param[in] neg_input A negative input source to set
|
||||
* \param[in] channel Channel number
|
||||
*
|
||||
* \return Status of the ADC channels setting.
|
||||
*/
|
||||
int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
|
||||
const adc_neg_input_t neg_input, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Set ADC conversion mode
|
||||
*
|
||||
* This function sets ADC conversion mode.
|
||||
*
|
||||
* \param[in] descr The pointer to the ADC descriptor
|
||||
* \param[in] mode A conversion mode to set
|
||||
*
|
||||
* \return Status of the ADC conversion mode setting.
|
||||
*/
|
||||
int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set ADC differential mode
|
||||
*
|
||||
* This function sets ADC differential mode.
|
||||
*
|
||||
* \param[in] descr The pointer to the ADC descriptor
|
||||
* \param[in] channel Channel number
|
||||
* \param[in] mode A differential mode to set
|
||||
*
|
||||
* \return Status of the ADC differential mode setting.
|
||||
*/
|
||||
int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
|
||||
const enum adc_differential_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set ADC channel gain
|
||||
*
|
||||
* This function sets ADC channel gain.
|
||||
*
|
||||
* \param[in] descr The pointer to the ADC descriptor
|
||||
* \param[in] channel Channel number
|
||||
* \param[in] gain A gain to set
|
||||
*
|
||||
* \return Status of the ADC gain setting.
|
||||
*/
|
||||
int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel,
|
||||
const adc_gain_t gain);
|
||||
|
||||
/**
|
||||
* \brief Set ADC window mode
|
||||
*
|
||||
* This function sets ADC window mode.
|
||||
*
|
||||
* \param[in] descr The pointer to the ADC descriptor
|
||||
* \param[in] mode A window mode to set
|
||||
*
|
||||
* \return Status of the ADC window mode setting.
|
||||
*/
|
||||
int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode);
|
||||
|
||||
/**
|
||||
* \brief Set ADC thresholds
|
||||
*
|
||||
* This function sets ADC positive and negative thresholds.
|
||||
*
|
||||
* \param[in] descr The pointer to the ADC descriptor
|
||||
* \param[in] low_threshold A lower thresholds to set
|
||||
* \param[in] up_threshold An upper thresholds to set
|
||||
*
|
||||
* \return Status of the ADC thresholds setting.
|
||||
*/
|
||||
int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
|
||||
const adc_threshold_t up_threshold);
|
||||
|
||||
/**
|
||||
* \brief Retrieve threshold state
|
||||
*
|
||||
* This function retrieves ADC threshold state.
|
||||
*
|
||||
* \param[in] descr The pointer to the ADC descriptor
|
||||
* \param[out] state The threshold state
|
||||
*
|
||||
* \return The state of ADC thresholds state retrieving.
|
||||
*/
|
||||
int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr,
|
||||
adc_threshold_status_t *const state);
|
||||
|
||||
/**
|
||||
* \brief Check if conversion is complete
|
||||
*
|
||||
* This function checks if the ADC has finished the conversion.
|
||||
*
|
||||
* \param[in] descr The pointer to the ADC descriptor
|
||||
* \param[in] channel Channel number
|
||||
*
|
||||
* \return The status of ADC conversion completion checking.
|
||||
* \retval 1 The conversion is complete
|
||||
* \retval 0 The conversion is not complete
|
||||
*/
|
||||
int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t adc_sync_get_version(void);
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#include <hpl_missing_features.h>
|
||||
|
||||
#endif /* _HAL_ADC_SYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Custom Control Logic functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hpl_custom_logic.h"
|
||||
|
||||
#ifndef _HAL_CUSTOM_LOGIC_H_INCLUDED
|
||||
#define _HAL_CUSTOM_LOGIC_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_custom_logic
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize the custom logic hardware
|
||||
* \return Initialization operation status
|
||||
*/
|
||||
static inline int32_t custom_logic_init(void)
|
||||
{
|
||||
return _custom_logic_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable and reset the custom logic hardware
|
||||
*/
|
||||
static inline void custom_logic_deinit(void)
|
||||
{
|
||||
_custom_logic_deinit();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable the custom logic hardware
|
||||
* \return Initialization operation status
|
||||
*/
|
||||
static inline int32_t custom_logic_enable(void)
|
||||
{
|
||||
return _custom_logic_enable();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable the custom logic hardware
|
||||
*/
|
||||
static inline void custom_logic_disable(void)
|
||||
{
|
||||
_custom_logic_disable();
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_CUSTOM_LOGIC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief External interrupt functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_EXT_IRQ_H_INCLUDED
|
||||
#define _HAL_EXT_IRQ_H_INCLUDED
|
||||
|
||||
#include <hpl_ext_irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_ext_irq
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief External IRQ callback type
|
||||
*/
|
||||
typedef void (*ext_irq_cb_t)(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize external IRQ component, if any
|
||||
*
|
||||
* \return Initialization status.
|
||||
* \retval -1 External IRQ module is already initialized
|
||||
* \retval 0 The initialization is completed successfully
|
||||
*/
|
||||
int32_t ext_irq_init(void);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize external IRQ, if any
|
||||
*
|
||||
* \return De-initialization status.
|
||||
* \retval -1 External IRQ module is already deinitialized
|
||||
* \retval 0 The de-initialization is completed successfully
|
||||
*/
|
||||
int32_t ext_irq_deinit(void);
|
||||
|
||||
/**
|
||||
* \brief Register callback for the given external interrupt
|
||||
*
|
||||
* \param[in] pin Pin to enable external IRQ on
|
||||
* \param[in] cb Callback function
|
||||
*
|
||||
* \return Registration status.
|
||||
* \retval -1 Passed parameters were invalid
|
||||
* \retval 0 The callback registration is completed successfully
|
||||
*/
|
||||
int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb);
|
||||
|
||||
/**
|
||||
* \brief Enable external IRQ
|
||||
*
|
||||
* \param[in] pin Pin to enable external IRQ on
|
||||
*
|
||||
* \return Enabling status.
|
||||
* \retval -1 Passed parameters were invalid
|
||||
* \retval 0 The enabling is completed successfully
|
||||
*/
|
||||
int32_t ext_irq_enable(const uint32_t pin);
|
||||
|
||||
/**
|
||||
* \brief Disable external IRQ
|
||||
*
|
||||
* \param[in] pin Pin to enable external IRQ on
|
||||
*
|
||||
* \return Disabling status.
|
||||
* \retval -1 Passed parameters were invalid
|
||||
* \retval 0 The disabling is completed successfully
|
||||
*/
|
||||
int32_t ext_irq_disable(const uint32_t pin);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t ext_irq_get_version(void);
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_EXT_IRQ_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief PWM functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef HAL_PWM_H_INCLUDED
|
||||
#define HAL_PWM_H_INCLUDED
|
||||
|
||||
#include <hpl_pwm.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_pwm_async
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief PWM descriptor
|
||||
*
|
||||
* The PWM descriptor forward declaration.
|
||||
*/
|
||||
struct pwm_descriptor;
|
||||
|
||||
/**
|
||||
* \brief PWM callback type
|
||||
*/
|
||||
typedef void (*pwm_cb_t)(const struct pwm_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief PWM callback types
|
||||
*/
|
||||
enum pwm_callback_type { PWM_PERIOD_CB, PWM_ERROR_CB };
|
||||
|
||||
/**
|
||||
* \brief PWM callbacks
|
||||
*/
|
||||
struct pwm_callbacks {
|
||||
pwm_cb_t period;
|
||||
pwm_cb_t error;
|
||||
};
|
||||
|
||||
/** \brief PWM descriptor
|
||||
*/
|
||||
struct pwm_descriptor {
|
||||
/** PWM device */
|
||||
struct _pwm_device device;
|
||||
/** PWM callback structure */
|
||||
struct pwm_callbacks pwm_cb;
|
||||
};
|
||||
|
||||
/** \brief Initialize the PWM HAL instance and hardware
|
||||
*
|
||||
* \param[in] descr Pointer to the HAL PWM descriptor
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
* \param[in] func The pointer to a set of functions pointers
|
||||
*
|
||||
* \return Operation status.
|
||||
*/
|
||||
int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func);
|
||||
|
||||
/** \brief Deinitialize the PWM HAL instance and hardware
|
||||
*
|
||||
* \param[in] descr Pointer to the HAL PWM descriptor
|
||||
*
|
||||
* \return Operation status.
|
||||
*/
|
||||
int32_t pwm_deinit(struct pwm_descriptor *const descr);
|
||||
|
||||
/** \brief PWM output start
|
||||
*
|
||||
* \param[in] descr Pointer to the HAL PWM descriptor
|
||||
*
|
||||
* \return Operation status.
|
||||
*/
|
||||
int32_t pwm_enable(struct pwm_descriptor *const descr);
|
||||
|
||||
/** \brief PWM output stop
|
||||
*
|
||||
* \param[in] descr Pointer to the HAL PWM descriptor
|
||||
*
|
||||
* \return Operation status.
|
||||
*/
|
||||
int32_t pwm_disable(struct pwm_descriptor *const descr);
|
||||
|
||||
/** \brief Register PWM callback
|
||||
*
|
||||
* \param[in] descr Pointer to the HAL PWM descriptor
|
||||
* \param[in] type Callback type
|
||||
* \param[in] cb A callback function, passing NULL de-registers callback
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval 0 Success
|
||||
* \retval -1 Error
|
||||
*/
|
||||
int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb);
|
||||
|
||||
/** \brief Change PWM parameter
|
||||
*
|
||||
* \param[in] descr Pointer to the HAL PWM descriptor
|
||||
* \param[in] period Total period of one PWM cycle
|
||||
* \param[in] duty_cycle Period of PWM first half during one cycle
|
||||
*
|
||||
* \return Operation status.
|
||||
*/
|
||||
int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period,
|
||||
const pwm_period_t duty_cycle);
|
||||
|
||||
/** \brief Get PWM driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t pwm_get_version(void);
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_PWM;_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Quad QSPI related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_QSPI_INCLUDED
|
||||
#define _HAL_QSPI_INCLUDED
|
||||
|
||||
#include <hpl_qspi_sync.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_quad_spi_sync
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief QSPI descriptor structure
|
||||
*/
|
||||
struct qspi_sync_descriptor {
|
||||
struct _qspi_sync_dev dev;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize QSPI low level driver.
|
||||
*
|
||||
* \param[in] qspi Pointer to the QSPI device instance
|
||||
* \param[in] hw Pointer to the hardware base
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success
|
||||
*/
|
||||
int32_t qspi_sync_init(struct qspi_sync_descriptor *qspi, void *hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize QSPI low level driver.
|
||||
*
|
||||
* \param[in] qspi Pointer to the QSPI device instance
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success
|
||||
*/
|
||||
int32_t qspi_sync_deinit(struct qspi_sync_descriptor *qspi);
|
||||
|
||||
/**
|
||||
* \brief Enable QSPI for access without interrupts
|
||||
*
|
||||
* \param[in] qspi Pointer to the QSPI device instance
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success
|
||||
*/
|
||||
int32_t qspi_sync_enable(struct qspi_sync_descriptor *qspi);
|
||||
|
||||
/**
|
||||
* \brief Disable QSPI for access without interrupts
|
||||
*
|
||||
* Disable QSPI. Deactivate all CS pins if it works as master.
|
||||
*
|
||||
* \param[in] qspi Pointer to the QSPI device instance
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success
|
||||
*/
|
||||
int32_t qspi_sync_disable(struct qspi_sync_descriptor *qspi);
|
||||
|
||||
/** \brief Execute command in Serial Memory Mode.
|
||||
*
|
||||
* \param[in] qspi Pointer to the HAL QSPI instance
|
||||
* \param[in] cmd Pointer to the command structure
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success
|
||||
*/
|
||||
int32_t qspi_sync_serial_run_command(struct qspi_sync_descriptor *qspi, const struct _qspi_command *cmd);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t qspi_sync_get_version(void);
|
||||
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_QSPI_INCLUDED */
|
||||
|
|
@ -0,0 +1,334 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SPI related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_SPI_M_ASYNC_H_INCLUDED
|
||||
#define _HAL_SPI_M_ASYNC_H_INCLUDED
|
||||
|
||||
#include <hal_io.h>
|
||||
#include <hpl_spi_m_async.h>
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_spi_master_async
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \brief SPI status
|
||||
*
|
||||
* Status descriptor holds the current status of transfer.
|
||||
*
|
||||
* \c txcnt and \c rxcnt are always the status of progress in current TX/RX
|
||||
* transfer buffer.
|
||||
*
|
||||
* For R/W/Transfer, simply check \c SPI_M_ASYNC_STATUS_BUSY to know that the
|
||||
* transfer is in progress, check \c SPI_M_ASYNC_STATUS_TX_DONE and
|
||||
* \c SPI_M_ASYNC_STATUS_RX_DONE to know that TX or RX is completed (since TX
|
||||
* and RX happen in different clock edge the time stamp of completion is
|
||||
* different), check \c SPI_M_ASYNC_STATUS_COMPLETE to confirm that CS has been
|
||||
* deactivate.
|
||||
*/
|
||||
struct spi_m_async_status {
|
||||
/** Status flags */
|
||||
uint32_t flags;
|
||||
/** Number of characters transmitted */
|
||||
uint32_t xfercnt;
|
||||
};
|
||||
/** SPI is busy (read/write/transfer, with CS activated) */
|
||||
#define SPI_M_ASYNC_STATUS_BUSY 0x0010
|
||||
/** SPI finished transmit buffer */
|
||||
#define SPI_M_ASYNC_STATUS_TX_DONE 0x0020
|
||||
/** SPI finished receive buffer */
|
||||
#define SPI_M_ASYNC_STATUS_RX_DONE 0x0040
|
||||
/** SPI finished everything including CS deactivate */
|
||||
#define SPI_M_ASYNC_STATUS_COMPLETE 0x0080
|
||||
#define SPI_M_ASYNC_STATUS_ERR_MASK 0x000F
|
||||
#define SPI_M_ASYNC_STATUS_ERR_POS 0
|
||||
#define SPI_M_ASYNC_STATUS_ERR_OVRF ((-ERR_OVERFLOW) << SPI_M_ASYNC_STATUS_ERR_POS)
|
||||
#define SPI_M_ASYNC_STATUS_ERR_ABORT ((-ERR_ABORTED) << SPI_M_ASYNC_STATUS_ERR_POS)
|
||||
#define SPI_M_ASYNC_STATUS_ERR_EXTRACT(st) (((st) >> SPI_M_ASYNC_STATUS_ERR_POS) & SPI_M_ASYNC_STATUS_ERR_MASK)
|
||||
|
||||
/* Forward declaration of spi_descriptor. */
|
||||
struct spi_m_async_descriptor;
|
||||
|
||||
/** The callback types */
|
||||
enum spi_m_async_cb_type {
|
||||
/** Callback type for read/write/transfer buffer done,
|
||||
* see \ref spi_m_async_cb_xfer_t. */
|
||||
SPI_M_ASYNC_CB_XFER,
|
||||
/** Callback type for CS deactivate, error, or abort,
|
||||
* see \ref spi_m_async_cb_error_t. */
|
||||
SPI_M_ASYNC_CB_ERROR,
|
||||
SPI_M_ASYNC_CB_N
|
||||
};
|
||||
|
||||
/** \brief Prototype of callback on SPI transfer errors
|
||||
*
|
||||
* Invoked on transfer errors
|
||||
* invoke \ref spi_get_status.
|
||||
*/
|
||||
typedef void (*spi_m_async_cb_error_t)(struct spi_m_async_descriptor *, const int32_t status);
|
||||
|
||||
/** \brief Prototype of callback on SPI read/write/transfer buffer completion
|
||||
*
|
||||
* Invoked on transfer completion, which means the transfer buffer has been
|
||||
* completed, including all TX/RX data (TX and RX happen in different clock
|
||||
* edges, but the callback is invoked after all TX and RX have been done).
|
||||
*/
|
||||
typedef void (*spi_m_async_cb_xfer_t)(struct spi_m_async_descriptor *);
|
||||
|
||||
/** \brief SPI HAL callbacks
|
||||
*
|
||||
*/
|
||||
struct spi_m_callbacks {
|
||||
/** Callback invoked when the buffer read/write/transfer done. */
|
||||
spi_m_async_cb_xfer_t cb_xfer;
|
||||
/** Callback invoked when the CS deactivates, goes wrong, or aborts. */
|
||||
spi_m_async_cb_error_t cb_error;
|
||||
};
|
||||
|
||||
/** \brief SPI HAL driver struct for asynchronous access
|
||||
*/
|
||||
struct spi_m_async_descriptor {
|
||||
struct _spi_m_async_hpl_interface *func;
|
||||
/** Pointer to the SPI device instance */
|
||||
struct _spi_m_async_dev dev;
|
||||
/** I/O read/write */
|
||||
struct io_descriptor io;
|
||||
|
||||
/** SPI transfer status */
|
||||
uint8_t stat;
|
||||
|
||||
/** Callbacks for asynchronous transfer */
|
||||
struct spi_m_callbacks callbacks;
|
||||
/** Transfer information copy, for R/W/Transfer */
|
||||
struct spi_xfer xfer;
|
||||
/** Character count in current transfer */
|
||||
uint32_t xfercnt;
|
||||
};
|
||||
|
||||
/** \brief Set the SPI HAL instance function pointer for HPL APIs.
|
||||
*
|
||||
* Set SPI HAL instance function pointer for HPL APIs.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] func Pointer to the HPL api structure.
|
||||
*
|
||||
*/
|
||||
void spi_m_async_set_func_ptr(struct spi_m_async_descriptor *spi, void *const func);
|
||||
|
||||
/** \brief Initialize the SPI HAL instance and hardware for callback mode
|
||||
*
|
||||
* Initialize SPI HAL with interrupt mode (uses callbacks).
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] hw Pointer to the hardware base.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_INVALID_DATA Error, initialized.
|
||||
*/
|
||||
int32_t spi_m_async_init(struct spi_m_async_descriptor *spi, void *const hw);
|
||||
|
||||
/** \brief Deinitialize the SPI HAL instance
|
||||
*
|
||||
* Abort transfer, disable and reset SPI, de-init software.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval <0 Error code.
|
||||
*/
|
||||
void spi_m_async_deinit(struct spi_m_async_descriptor *spi);
|
||||
|
||||
/** \brief Enable SPI
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval <0 Error code.
|
||||
*/
|
||||
void spi_m_async_enable(struct spi_m_async_descriptor *spi);
|
||||
|
||||
/** \brief Disable the SPI and abort any pending transfer in progress
|
||||
*
|
||||
* If there is any pending transfer, the complete callback is invoked
|
||||
* with the \c ERR_ABORTED status.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval <0 Error code.
|
||||
*/
|
||||
void spi_m_async_disable(struct spi_m_async_descriptor *spi);
|
||||
|
||||
/** \brief Set SPI baudrate
|
||||
*
|
||||
* Works if the SPI is initialized as master.
|
||||
* In the function a sanity check is used to confirm it's called in the correct mode.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] baud_val The target baudrate value
|
||||
* (see "baudrate calculation" for calculating the value).
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy.
|
||||
*/
|
||||
int32_t spi_m_async_set_baudrate(struct spi_m_async_descriptor *spi, const uint32_t baud_val);
|
||||
|
||||
/** \brief Set SPI mode
|
||||
*
|
||||
* Set the SPI transfer mode (\ref spi_transfer_mode),
|
||||
* which controls the clock polarity and clock phase:
|
||||
* - Mode 0: leading edge is rising edge, data sample on leading edge.
|
||||
* - Mode 1: leading edge is rising edge, data sample on trailing edge.
|
||||
* - Mode 2: leading edge is falling edge, data sample on leading edge.
|
||||
* - Mode 3: leading edge is falling edge, data sample on trailing edge.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] mode The mode (\ref spi_transfer_mode).
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy, CS activated.
|
||||
*/
|
||||
int32_t spi_m_async_set_mode(struct spi_m_async_descriptor *spi, const enum spi_transfer_mode mode);
|
||||
|
||||
/** \brief Set SPI transfer character size in number of bits
|
||||
*
|
||||
* The character size (\ref spi_char_size) influence the way the data is
|
||||
* sent/received.
|
||||
* For char size <= 8-bit, data is stored byte by byte.
|
||||
* For char size between 9-bit ~ 16-bit, data is stored in 2-byte length.
|
||||
* Note that the default and recommended char size is 8-bit since it's
|
||||
* supported by all system.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] char_size The char size (\ref spi_char_size).
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy, CS activated.
|
||||
* \retval ERR_INVALID_ARG The char size is not supported.
|
||||
*/
|
||||
int32_t spi_m_async_set_char_size(struct spi_m_async_descriptor *spi, const enum spi_char_size char_size);
|
||||
|
||||
/** \brief Set SPI transfer data order
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] dord The data order: send LSB/MSB first.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy, CS activated.
|
||||
* \retval ERR_INVALID The data order is not supported.
|
||||
*/
|
||||
int32_t spi_m_async_set_data_order(struct spi_m_async_descriptor *spi, const enum spi_data_order dord);
|
||||
|
||||
/** \brief Perform the SPI data transfer (TX and RX) asynchronously
|
||||
*
|
||||
* Log the TX and RX buffers and transfer them in the background. It never blocks.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] txbuf Pointer to the transfer information (\ref spi_transfer).
|
||||
* \param[out] rxbuf Pointer to the receiver information (\ref spi_receive).
|
||||
* \param[in] length SPI transfer data length.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy.
|
||||
*/
|
||||
int32_t spi_m_async_transfer(struct spi_m_async_descriptor *spi, uint8_t const *txbuf, uint8_t *const rxbuf,
|
||||
const uint16_t length);
|
||||
|
||||
/** \brief Get the SPI transfer status
|
||||
*
|
||||
* Get transfer status, transfer counts in a structured way.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[out] stat Pointer to the detailed status descriptor, set to NULL
|
||||
* to not return details.
|
||||
*
|
||||
* \return Status.
|
||||
* \retval ERR_NONE Not busy.
|
||||
* \retval ERR_BUSY Busy.
|
||||
*/
|
||||
int32_t spi_m_async_get_status(struct spi_m_async_descriptor *spi, struct spi_m_async_status *stat);
|
||||
|
||||
/** \brief Register a function as SPI transfer completion callback
|
||||
*
|
||||
* Register callback function specified by its \c type.
|
||||
* - SPI_CB_COMPLETE: set the function that will be called on the SPI transfer
|
||||
* completion including deactivating the CS.
|
||||
* - SPI_CB_XFER: set the function that will be called on the SPI buffer transfer
|
||||
* completion.
|
||||
* Register NULL function to not use the callback.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] type Callback type (\ref spi_m_async_cb_type).
|
||||
* \param[in] func Pointer to callback function.
|
||||
*/
|
||||
void spi_m_async_register_callback(struct spi_m_async_descriptor *spi, const enum spi_m_async_cb_type type,
|
||||
FUNC_PTR func);
|
||||
|
||||
/**
|
||||
* \brief Return I/O descriptor for this SPI instance
|
||||
*
|
||||
* This function will return an I/O instance for this SPI driver instance
|
||||
*
|
||||
* \param[in] spi An SPI master descriptor, which is used to communicate through
|
||||
* SPI
|
||||
* \param[in, out] io A pointer to an I/O descriptor pointer type
|
||||
*
|
||||
* \retval ERR_NONE
|
||||
*/
|
||||
int32_t spi_m_async_get_io_descriptor(struct spi_m_async_descriptor *const spi, struct io_descriptor **io);
|
||||
|
||||
/** \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t spi_m_async_get_version(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* ifndef _HAL_SPI_M_ASYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SPI related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_SPI_M_SYNC_H_INCLUDED
|
||||
#define _HAL_SPI_M_SYNC_H_INCLUDED
|
||||
|
||||
#include <hal_io.h>
|
||||
#include <hpl_spi_m_sync.h>
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_spi_master_sync
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \brief SPI HAL driver struct for polling mode
|
||||
*
|
||||
*/
|
||||
struct spi_m_sync_descriptor {
|
||||
struct _spi_m_sync_hpl_interface *func;
|
||||
/** SPI device instance */
|
||||
struct _spi_sync_dev dev;
|
||||
/** I/O read/write */
|
||||
struct io_descriptor io;
|
||||
/** Flags for HAL driver */
|
||||
uint16_t flags;
|
||||
};
|
||||
|
||||
/** \brief Set the SPI HAL instance function pointer for HPL APIs.
|
||||
*
|
||||
* Set SPI HAL instance function pointer for HPL APIs.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] func Pointer to the HPL api structure.
|
||||
*
|
||||
*/
|
||||
void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func);
|
||||
|
||||
/** \brief Initialize SPI HAL instance and hardware for polling mode
|
||||
*
|
||||
* Initialize SPI HAL with polling mode.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] hw Pointer to the hardware base.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_INVALID_DATA Error, initialized.
|
||||
*/
|
||||
int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw);
|
||||
|
||||
/** \brief Deinitialize the SPI HAL instance and hardware
|
||||
*
|
||||
* Abort transfer, disable and reset SPI, deinit software.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval <0 Error code.
|
||||
*/
|
||||
void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi);
|
||||
|
||||
/** \brief Enable SPI
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval <0 Error code.
|
||||
*/
|
||||
void spi_m_sync_enable(struct spi_m_sync_descriptor *spi);
|
||||
|
||||
/** \brief Disable SPI
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval <0 Error code.
|
||||
*/
|
||||
void spi_m_sync_disable(struct spi_m_sync_descriptor *spi);
|
||||
|
||||
/** \brief Set SPI baudrate
|
||||
*
|
||||
* Works if SPI is initialized as master, it sets the baudrate.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] baud_val The target baudrate value
|
||||
* (see "baudrate calculation" for calculating the value).
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy
|
||||
* \retval ERR_INVALID_ARG The baudrate is not supported.
|
||||
*/
|
||||
int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val);
|
||||
|
||||
/** \brief Set SPI mode
|
||||
*
|
||||
* Set the SPI transfer mode (\ref spi_transfer_mode),
|
||||
* which controls the clock polarity and clock phase:
|
||||
* - Mode 0: leading edge is rising edge, data sample on leading edge.
|
||||
* - Mode 1: leading edge is rising edge, data sample on trailing edge.
|
||||
* - Mode 2: leading edge is falling edge, data sample on leading edge.
|
||||
* - Mode 3: leading edge is falling edge, data sample on trailing edge.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] mode The mode (0~3).
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy
|
||||
* \retval ERR_INVALID_ARG The mode is not supported.
|
||||
*/
|
||||
int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode);
|
||||
|
||||
/** \brief Set SPI transfer character size in number of bits
|
||||
*
|
||||
* The character size (\ref spi_char_size) influence the way the data is
|
||||
* sent/received.
|
||||
* For char size <= 8-bit, data is stored byte by byte.
|
||||
* For char size between 9-bit ~ 16-bit, data is stored in 2-byte length.
|
||||
* Note that the default and recommended char size is 8-bit since it's
|
||||
* supported by all system.
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] char_size The char size (~16, recommended 8).
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy
|
||||
* \retval ERR_INVALID_ARG The char size is not supported.
|
||||
*/
|
||||
int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size);
|
||||
|
||||
/** \brief Set SPI transfer data order
|
||||
*
|
||||
* \param[in] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] dord The data order: send LSB/MSB first.
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success.
|
||||
* \retval ERR_BUSY Busy
|
||||
* \retval ERR_INVALID_ARG The data order is not supported.
|
||||
*/
|
||||
int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord);
|
||||
|
||||
/** \brief Perform the SPI data transfer (TX and RX) in polling way
|
||||
*
|
||||
* Activate CS, do TX and RX and deactivate CS. It blocks.
|
||||
*
|
||||
* \param[in, out] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] xfer Pointer to the transfer information (\ref spi_xfer).
|
||||
*
|
||||
* \retval size Success.
|
||||
* \retval >=0 Timeout, with number of characters transferred.
|
||||
* \retval ERR_BUSY SPI is busy
|
||||
*/
|
||||
int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *xfer);
|
||||
|
||||
/**
|
||||
* \brief Return the I/O descriptor for this SPI instance
|
||||
*
|
||||
* This function will return an I/O instance for this SPI driver instance.
|
||||
*
|
||||
* \param[in] spi An SPI master descriptor, which is used to communicate through
|
||||
* SPI
|
||||
* \param[in, out] io A pointer to an I/O descriptor pointer type
|
||||
*
|
||||
* \retval ERR_NONE
|
||||
*/
|
||||
int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io);
|
||||
|
||||
/** \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t spi_m_sync_get_version(void);
|
||||
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _HAL_SPI_M_SYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,264 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief ADC related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_ADC_ASYNC_H_INCLUDED
|
||||
#define _HPL_ADC_ASYNC_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL ADC
|
||||
*
|
||||
* \section hpl_async_adc_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include "hpl_adc_sync.h"
|
||||
#include "hpl_irq.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief ADC device structure
|
||||
*
|
||||
* The ADC device structure forward declaration.
|
||||
*/
|
||||
struct _adc_async_device;
|
||||
|
||||
/**
|
||||
* \brief ADC callback types
|
||||
*/
|
||||
enum _adc_async_callback_type { ADC_ASYNC_DEVICE_CONVERT_CB, ADC_ASYNC_DEVICE_MONITOR_CB, ADC_ASYNC_DEVICE_ERROR_CB };
|
||||
|
||||
/**
|
||||
* \brief ADC interrupt callbacks
|
||||
*/
|
||||
struct _adc_async_callbacks {
|
||||
void (*window_cb)(struct _adc_async_device *device, const uint8_t channel);
|
||||
void (*error_cb)(struct _adc_async_device *device, const uint8_t channel);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC channel interrupt callbacks
|
||||
*/
|
||||
struct _adc_async_ch_callbacks {
|
||||
void (*convert_done)(struct _adc_async_device *device, const uint8_t channel, const uint16_t data);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC descriptor device structure
|
||||
*/
|
||||
struct _adc_async_device {
|
||||
struct _adc_async_callbacks adc_async_cb;
|
||||
struct _adc_async_ch_callbacks adc_async_ch_cb;
|
||||
struct _irq_descriptor irq;
|
||||
void * hw;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initialize synchronous ADC
|
||||
*
|
||||
* This function does low level ADC configuration.
|
||||
*
|
||||
* param[in] device The pointer to ADC device instance
|
||||
* param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Initialization status
|
||||
*/
|
||||
int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize ADC
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
*/
|
||||
void _adc_async_deinit(struct _adc_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable ADC peripheral
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
*/
|
||||
void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Disable ADC peripheral
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
*/
|
||||
void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Retrieve ADC conversion data size
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
*
|
||||
* \return The data size in bytes
|
||||
*/
|
||||
uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if conversion is done
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
*
|
||||
* \return The status of conversion
|
||||
* \retval true The conversion is done
|
||||
* \retval false The conversion is not done
|
||||
*/
|
||||
bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Make conversion
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
*/
|
||||
void _adc_async_convert(struct _adc_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the conversion result
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
*
|
||||
* The result value
|
||||
*/
|
||||
uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Set reference source
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] reference A reference source to set
|
||||
*/
|
||||
void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference);
|
||||
|
||||
/**
|
||||
* \brief Set resolution
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] resolution A resolution to set
|
||||
*/
|
||||
void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution);
|
||||
|
||||
/**
|
||||
* \brief Set ADC input source of a channel
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] pos_input A positive input source to set
|
||||
* \param[in] neg_input A negative input source to set
|
||||
* \param[in] channel Channel number
|
||||
*/
|
||||
void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
|
||||
const adc_neg_input_t neg_input, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Set conversion mode
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] mode A conversion mode to set
|
||||
*/
|
||||
void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set differential mode
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
* \param[in] mode A differential mode to set
|
||||
*/
|
||||
void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
|
||||
const enum adc_differential_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set gain
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
* \param[in] gain A gain to set
|
||||
*/
|
||||
void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain);
|
||||
|
||||
/**
|
||||
* \brief Set window mode
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] mode A mode to set
|
||||
*/
|
||||
void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode);
|
||||
|
||||
/**
|
||||
* \brief Set lower threshold
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] low_threshold A lower threshold to set
|
||||
* \param[in] up_threshold An upper thresholds to set
|
||||
*/
|
||||
void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
|
||||
const adc_threshold_t up_threshold);
|
||||
|
||||
/**
|
||||
* \brief Retrieve threshold state
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[out] state The threshold state
|
||||
*/
|
||||
void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable ADC channel interrupt
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
* \param[in] type The type of interrupt to disable/enable if applicable
|
||||
* \param[in] state Enable or disable
|
||||
*/
|
||||
void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
|
||||
const enum _adc_async_callback_type type, const bool state);
|
||||
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_ADC_ASYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief ADC related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_ADC_DMA_H_INCLUDED
|
||||
#define _HPL_ADC_DMA_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL ADC
|
||||
*
|
||||
* \section hpl_dma_adc_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <hpl_adc_sync.h>
|
||||
#include <hpl_irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief ADC device structure
|
||||
*
|
||||
* The ADC device structure forward declaration.
|
||||
*/
|
||||
struct _adc_dma_device;
|
||||
|
||||
/**
|
||||
* \brief ADC callback types
|
||||
*/
|
||||
enum _adc_dma_callback_type { ADC_DMA_DEVICE_COMPLETE_CB, ADC_DMA_DEVICE_ERROR_CB };
|
||||
|
||||
/**
|
||||
* \brief ADC interrupt callbacks
|
||||
*/
|
||||
struct _adc_dma_callbacks {
|
||||
void (*complete)(struct _adc_dma_device *device, const uint16_t data);
|
||||
void (*error)(struct _adc_dma_device *device);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC descriptor device structure
|
||||
*/
|
||||
struct _adc_dma_device {
|
||||
struct _adc_dma_callbacks adc_dma_cb;
|
||||
struct _irq_descriptor irq;
|
||||
void * hw;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initialize synchronous ADC
|
||||
*
|
||||
* This function does low level ADC configuration.
|
||||
*
|
||||
* param[in] device The pointer to ADC device instance
|
||||
* param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Initialization status
|
||||
*/
|
||||
int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize ADC
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
*/
|
||||
void _adc_dma_deinit(struct _adc_dma_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable ADC peripheral
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
*/
|
||||
void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Disable ADC peripheral
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
*/
|
||||
void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Return address of ADC DMA source
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
*
|
||||
* \return ADC DMA source address
|
||||
*/
|
||||
uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Retrieve ADC conversion data size
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
*
|
||||
* \return The data size in bytes
|
||||
*/
|
||||
uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if conversion is done
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
*
|
||||
* \return The status of conversion
|
||||
* \retval true The conversion is done
|
||||
* \retval false The conversion is not done
|
||||
*/
|
||||
bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Make conversion
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
*/
|
||||
void _adc_dma_convert(struct _adc_dma_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set reference source
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] reference A reference source to set
|
||||
*/
|
||||
void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference);
|
||||
|
||||
/**
|
||||
* \brief Set resolution
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] resolution A resolution to set
|
||||
*/
|
||||
void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution);
|
||||
|
||||
/**
|
||||
* \brief Set ADC input source of a channel
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] pos_input A positive input source to set
|
||||
* \param[in] neg_input A negative input source to set
|
||||
* \param[in] channel Channel number
|
||||
*/
|
||||
void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input,
|
||||
const adc_neg_input_t neg_input, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Set conversion mode
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] mode A conversion mode to set
|
||||
*/
|
||||
void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set differential mode
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
* \param[in] mode A differential mode to set
|
||||
*/
|
||||
void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel,
|
||||
const enum adc_differential_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set gain
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
* \param[in] gain A gain to set
|
||||
*/
|
||||
void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain);
|
||||
|
||||
/**
|
||||
* \brief Set window mode
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] mode A mode to set
|
||||
*/
|
||||
void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode);
|
||||
|
||||
/**
|
||||
* \brief Set thresholds
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] low_threshold A lower thresholds to set
|
||||
* \param[in] up_threshold An upper thresholds to set
|
||||
*/
|
||||
void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold,
|
||||
const adc_threshold_t up_threshold);
|
||||
|
||||
/**
|
||||
* \brief Retrieve threshold state
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[out] state The threshold state
|
||||
*/
|
||||
void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state);
|
||||
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_ADC_DMA_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,271 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief ADC related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_ADC_SYNC_H_INCLUDED
|
||||
#define _HPL_ADC_SYNC_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL ADC
|
||||
*
|
||||
* \section hpl_adc_sync_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include "compiler.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief ADC reference source
|
||||
*/
|
||||
typedef uint8_t adc_reference_t;
|
||||
|
||||
/**
|
||||
* \brief ADC resolution
|
||||
*/
|
||||
typedef uint8_t adc_resolution_t;
|
||||
|
||||
/**
|
||||
* \brief ADC positive input for channel
|
||||
*/
|
||||
typedef uint8_t adc_pos_input_t;
|
||||
|
||||
/**
|
||||
* \brief ADC negative input for channel
|
||||
*/
|
||||
typedef uint8_t adc_neg_input_t;
|
||||
|
||||
/**
|
||||
* \brief ADC threshold
|
||||
*/
|
||||
typedef uint16_t adc_threshold_t;
|
||||
|
||||
/**
|
||||
* \brief ADC gain
|
||||
*/
|
||||
typedef uint8_t adc_gain_t;
|
||||
|
||||
/**
|
||||
* \brief ADC conversion mode
|
||||
*/
|
||||
enum adc_conversion_mode { ADC_CONVERSION_MODE_SINGLE_CONVERSION = 0, ADC_CONVERSION_MODE_FREERUN };
|
||||
|
||||
/**
|
||||
* \brief ADC differential mode
|
||||
*/
|
||||
enum adc_differential_mode { ADC_DIFFERENTIAL_MODE_SINGLE_ENDED = 0, ADC_DIFFERENTIAL_MODE_DIFFERENTIAL };
|
||||
|
||||
/**
|
||||
* \brief ADC window mode
|
||||
*/
|
||||
typedef uint8_t adc_window_mode_t;
|
||||
|
||||
/**
|
||||
* \brief ADC threshold status
|
||||
*/
|
||||
typedef bool adc_threshold_status_t;
|
||||
|
||||
/**
|
||||
* \brief ADC sync descriptor device structure
|
||||
*/
|
||||
struct _adc_sync_device {
|
||||
void *hw;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initialize synchronous ADC
|
||||
*
|
||||
* This function does low level ADC configuration.
|
||||
*
|
||||
* param[in] device The pointer to ADC device instance
|
||||
* param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Initialization status
|
||||
*/
|
||||
int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize ADC
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
*/
|
||||
void _adc_sync_deinit(struct _adc_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable ADC
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
*/
|
||||
void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Disable ADC
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
*/
|
||||
void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Retrieve ADC conversion data size
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
*
|
||||
* \return The data size in bytes
|
||||
*/
|
||||
uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if conversion is done
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
*
|
||||
* \return The status of conversion
|
||||
* \retval true The conversion is done
|
||||
* \retval false The conversion is not done
|
||||
*/
|
||||
bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Make conversion
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
*/
|
||||
void _adc_sync_convert(struct _adc_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the conversion result
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
*
|
||||
* \return The result value of channel
|
||||
*/
|
||||
uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Set reference source
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] reference A reference source to set
|
||||
*/
|
||||
void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference);
|
||||
|
||||
/**
|
||||
* \brief Set resolution
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] resolution A resolution to set
|
||||
*/
|
||||
void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution);
|
||||
|
||||
/**
|
||||
* \brief Set ADC input source of a channel
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] pos_input A positive input source to set
|
||||
* \param[in] neg_input A negative input source to set
|
||||
* \param[in] channel Channel number
|
||||
*/
|
||||
void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
|
||||
const adc_neg_input_t neg_input, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Set conversion mode
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] mode A conversion mode to set
|
||||
*/
|
||||
void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set differential mode
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
* \param[in] mode A differential mode to set
|
||||
*/
|
||||
void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
|
||||
const enum adc_differential_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set gain
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] channel Channel number
|
||||
* \param[in] gain A gain to set
|
||||
*/
|
||||
void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain);
|
||||
|
||||
/**
|
||||
* \brief Set window mode
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] mode A mode to set
|
||||
*/
|
||||
void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode);
|
||||
|
||||
/**
|
||||
* \brief Set threshold
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[in] low_threshold A lower threshold to set
|
||||
* \param[in] up_threshold An upper thresholds to set
|
||||
*/
|
||||
void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
|
||||
const adc_threshold_t up_threshold);
|
||||
|
||||
/**
|
||||
* \brief Retrieve threshold state
|
||||
*
|
||||
* \param[in] device The pointer to ADC device instance
|
||||
* \param[out] state The threshold state
|
||||
*/
|
||||
void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_ADC_SYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Custom Control Logic functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_CUSTOM_LOGIC_H_INCLUDED
|
||||
#define _HPL_CUSTOM_LOGIC_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Initialize the custom logic hardware
|
||||
* \return Initialization operation status
|
||||
*/
|
||||
int32_t _custom_logic_init(void);
|
||||
|
||||
/**
|
||||
* \brief Disable and reset the custom logic hardware
|
||||
*/
|
||||
void _custom_logic_deinit(void);
|
||||
|
||||
/**
|
||||
* \brief Enable the custom logic hardware
|
||||
* \return Initialization operation status
|
||||
*/
|
||||
int32_t _custom_logic_enable(void);
|
||||
|
||||
/**
|
||||
* \brief Disable the custom logic hardware
|
||||
*/
|
||||
void _custom_logic_disable(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HPL_CUSTOM_LOGIC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,176 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief DMA related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_DMA_H_INCLUDED
|
||||
#define _HPL_DMA_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL DMA
|
||||
*
|
||||
* \section hpl_dma_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include <hpl_irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct _dma_resource;
|
||||
|
||||
/**
|
||||
* \brief DMA callback types
|
||||
*/
|
||||
enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB };
|
||||
|
||||
/**
|
||||
* \brief DMA interrupt callbacks
|
||||
*/
|
||||
struct _dma_callbacks {
|
||||
void (*transfer_done)(struct _dma_resource *resource);
|
||||
void (*error)(struct _dma_resource *resource);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief DMA resource structure
|
||||
*/
|
||||
struct _dma_resource {
|
||||
struct _dma_callbacks dma_cb;
|
||||
void * back;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize DMA
|
||||
*
|
||||
* This function does low level DMA configuration.
|
||||
*
|
||||
* \return initialize status
|
||||
*/
|
||||
int32_t _dma_init(void);
|
||||
|
||||
/**
|
||||
* \brief Set destination address
|
||||
*
|
||||
* \param[in] channel DMA channel to set destination address for
|
||||
* \param[in] dst Destination address
|
||||
*
|
||||
* \return setting status
|
||||
*/
|
||||
int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst);
|
||||
|
||||
/**
|
||||
* \brief Set source address
|
||||
*
|
||||
* \param[in] channel DMA channel to set source address for
|
||||
* \param[in] src Source address
|
||||
*
|
||||
* \return setting status
|
||||
*/
|
||||
int32_t _dma_set_source_address(const uint8_t channel, const void *const src);
|
||||
|
||||
/**
|
||||
* \brief Set next descriptor address
|
||||
*
|
||||
* \param[in] current_channel Current DMA channel to set next descriptor address
|
||||
* \param[in] next_channel Next DMA channel used as next descriptor
|
||||
*
|
||||
* \return setting status
|
||||
*/
|
||||
int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable source address incrementation during DMA transaction
|
||||
*
|
||||
* \param[in] channel DMA channel to set source address for
|
||||
* \param[in] enable True to enable, false to disable
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable Destination address incrementation during DMA transaction
|
||||
*
|
||||
* \param[in] channel DMA channel to set destination address for
|
||||
* \param[in] enable True to enable, false to disable
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable);
|
||||
/**
|
||||
* \brief Set the amount of data to be transfered per transaction
|
||||
*
|
||||
* \param[in] channel DMA channel to set data amount for
|
||||
* \param[in] amount Data amount
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount);
|
||||
|
||||
/**
|
||||
* \brief Trigger DMA transaction on the given channel
|
||||
*
|
||||
* \param[in] channel DMA channel to trigger transaction on
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger);
|
||||
|
||||
/**
|
||||
* \brief Retrieves DMA resource structure
|
||||
*
|
||||
* \param[out] resource The resource to be retrieved
|
||||
* \param[in] channel DMA channel to retrieve structure for
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable DMA interrupt
|
||||
*
|
||||
* \param[in] channel DMA channel to enable/disable interrupt for
|
||||
* \param[in] type The type of interrupt to disable/enable if applicable
|
||||
* \param[in] state Enable or disable
|
||||
*/
|
||||
void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HPL_DMA_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief External IRQ related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_EXT_IRQ_H_INCLUDED
|
||||
#define _HPL_EXT_IRQ_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL EXT IRQ
|
||||
*
|
||||
* \section hpl_ext_irq_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initialize external interrupt module
|
||||
*
|
||||
* This function does low level external interrupt configuration.
|
||||
*
|
||||
* \param[in] cb The pointer to callback function from external interrupt
|
||||
*
|
||||
* \return Initialization status.
|
||||
* \retval -1 External irq module is already initialized
|
||||
* \retval 0 The initialization is completed successfully
|
||||
*/
|
||||
int32_t _ext_irq_init(void (*cb)(const uint32_t pin));
|
||||
|
||||
/**
|
||||
* \brief Deinitialize external interrupt module
|
||||
*
|
||||
* \return Initialization status.
|
||||
* \retval -1 External irq module is already deinitialized
|
||||
* \retval 0 The de-initialization is completed successfully
|
||||
*/
|
||||
int32_t _ext_irq_deinit(void);
|
||||
|
||||
/**
|
||||
* \brief Enable / disable external irq
|
||||
*
|
||||
* \param[in] pin Pin to enable external irq on
|
||||
* \param[in] enable True to enable, false to disable
|
||||
*
|
||||
* \return Status of external irq enabling / disabling
|
||||
* \retval -1 External irq module can't be enabled / disabled
|
||||
* \retval 0 External irq module is enabled / disabled successfully
|
||||
*/
|
||||
int32_t _ext_irq_enable(const uint32_t pin, const bool enable);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_EXT_IRQ_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief PWM related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_PWM_H_INCLUDED
|
||||
#define _HPL_PWM_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL PWM
|
||||
*
|
||||
* \section hpl_pwm_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include "hpl_irq.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief PWM callback types
|
||||
*/
|
||||
enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB };
|
||||
|
||||
/**
|
||||
* \brief PWM pulse-width period
|
||||
*/
|
||||
typedef uint32_t pwm_period_t;
|
||||
|
||||
/**
|
||||
* \brief PWM device structure
|
||||
*
|
||||
* The PWM device structure forward declaration.
|
||||
*/
|
||||
struct _pwm_device;
|
||||
|
||||
/**
|
||||
* \brief PWM interrupt callbacks
|
||||
*/
|
||||
struct _pwm_callback {
|
||||
void (*pwm_period_cb)(struct _pwm_device *device);
|
||||
void (*pwm_error_cb)(struct _pwm_device *device);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief PWM descriptor device structure
|
||||
*/
|
||||
struct _pwm_device {
|
||||
struct _pwm_callback callback;
|
||||
struct _irq_descriptor irq;
|
||||
void * hw;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief PWM functions, pointers to low-level functions
|
||||
*/
|
||||
struct _pwm_hpl_interface {
|
||||
int32_t (*init)(struct _pwm_device *const device, void *const hw);
|
||||
void (*deinit)(struct _pwm_device *const device);
|
||||
void (*start_pwm)(struct _pwm_device *const device);
|
||||
void (*stop_pwm)(struct _pwm_device *const device);
|
||||
void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
|
||||
bool (*is_pwm_enabled)(const struct _pwm_device *const device);
|
||||
pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device);
|
||||
uint32_t (*pwm_get_duty)(const struct _pwm_device *const device);
|
||||
void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
|
||||
};
|
||||
/**
|
||||
* \brief Initialize TC
|
||||
*
|
||||
* This function does low level TC configuration.
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Initialization status.
|
||||
*/
|
||||
int32_t _pwm_init(struct _pwm_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize TC
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*/
|
||||
void _pwm_deinit(struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Retrieve offset of the given tc hardware instance
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*
|
||||
* \return The offset of the given tc hardware instance
|
||||
*/
|
||||
uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Start hardware pwm
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*/
|
||||
void _pwm_enable(struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Stop hardware pwm
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*/
|
||||
void _pwm_disable(struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set pwm parameter
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
* \param[in] period Total period of one PWM cycle.
|
||||
* \param[in] duty_cycle Period of PWM first half during one cycle.
|
||||
*/
|
||||
void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
|
||||
|
||||
/**
|
||||
* \brief Check if pwm is working
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*
|
||||
* \return Check status.
|
||||
* \retval true The given pwm is working
|
||||
* \retval false The given pwm is not working
|
||||
*/
|
||||
bool _pwm_is_enabled(const struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Get pwm waveform period value
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*
|
||||
* \return Period value.
|
||||
*/
|
||||
pwm_period_t _pwm_get_period(const struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Get pwm waveform duty cycle value
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*
|
||||
* \return Duty cycle value
|
||||
*/
|
||||
uint32_t _pwm_get_duty(const struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable PWM interrupt
|
||||
*
|
||||
* param[in] device The pointer to PWM device instance
|
||||
* param[in] type The type of interrupt to disable/enable if applicable
|
||||
* param[in] disable Enable or disable
|
||||
*/
|
||||
void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_PWM_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Quad SPI related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_QSPI_H_INCLUDED
|
||||
#define _HPL_QSPI_H_INCLUDED
|
||||
|
||||
#include "compiler.h"
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_qspi HPL QSPI
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Qspi access modes
|
||||
*/
|
||||
enum qspi_access {
|
||||
/* Read access */
|
||||
QSPI_READ_ACCESS = 0,
|
||||
/* Read memory access */
|
||||
QSPI_READMEM_ACCESS,
|
||||
/* Write access */
|
||||
QSPI_WRITE_ACCESS,
|
||||
/* Write memory access */
|
||||
QSPI_WRITEMEM_ACCESS
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief QSPI command instruction/address/data width
|
||||
*/
|
||||
enum qspi_cmd_width {
|
||||
/** Instruction: Single-bit, Address: Single-bit, Data: Single-bit */
|
||||
QSPI_INST1_ADDR1_DATA1,
|
||||
/** Instruction: Single-bit, Address: Single-bit, Data: Dual-bit */
|
||||
QSPI_INST1_ADDR1_DATA2,
|
||||
/** Instruction: Single-bit, Address: Single-bit, Data: Quad-bit */
|
||||
QSPI_INST1_ADDR1_DATA4,
|
||||
/** Instruction: Single-bit, Address: Dual-bit, Data: Dual-bit */
|
||||
QSPI_INST1_ADDR2_DATA2,
|
||||
/** Instruction: Single-bit, Address: Quad-bit, Data: Quad-bit */
|
||||
QSPI_INST1_ADDR4_DATA4,
|
||||
/** Instruction: Dual-bit, Address: Dual-bit, Data: Dual-bit */
|
||||
QSPI_INST2_ADDR2_DATA2,
|
||||
/** Instruction: Quad-bit, Address: Quad-bit, Data: Quad-bit */
|
||||
QSPI_INST4_ADDR4_DATA4
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief QSPI command option code length in bits
|
||||
*/
|
||||
enum qspi_cmd_opt_len {
|
||||
/** The option code is 1 bit long */
|
||||
QSPI_OPT_1BIT,
|
||||
/** The option code is 2 bits long */
|
||||
QSPI_OPT_2BIT,
|
||||
/** The option code is 4 bits long */
|
||||
QSPI_OPT_4BIT,
|
||||
/** The option code is 8 bits long */
|
||||
QSPI_OPT_8BIT
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Qspi command structure
|
||||
*/
|
||||
struct _qspi_command {
|
||||
union {
|
||||
struct {
|
||||
/* Width of QSPI Addr , inst data */
|
||||
uint32_t width : 3;
|
||||
/* Reserved */
|
||||
uint32_t reserved0 : 1;
|
||||
/* Enable Instruction */
|
||||
uint32_t inst_en : 1;
|
||||
/* Enable Address */
|
||||
uint32_t addr_en : 1;
|
||||
/* Enable Option */
|
||||
uint32_t opt_en : 1;
|
||||
/* Enable Data */
|
||||
uint32_t data_en : 1;
|
||||
/* Option Length */
|
||||
uint32_t opt_len : 2;
|
||||
/* Address Length */
|
||||
uint32_t addr_len : 1;
|
||||
/* Option Length */
|
||||
uint32_t reserved1 : 1;
|
||||
/* Transfer type */
|
||||
uint32_t tfr_type : 2;
|
||||
/* Continuous read mode */
|
||||
uint32_t continues_read : 1;
|
||||
/* Enable Double Data Rate */
|
||||
uint32_t ddr_enable : 1;
|
||||
/* Dummy Cycles Length */
|
||||
uint32_t dummy_cycles : 5;
|
||||
/* Reserved */
|
||||
uint32_t reserved3 : 11;
|
||||
} bits;
|
||||
uint32_t word;
|
||||
} inst_frame;
|
||||
|
||||
uint8_t instruction;
|
||||
uint8_t option;
|
||||
uint32_t address;
|
||||
|
||||
size_t buf_len;
|
||||
const void *tx_buf;
|
||||
void * rx_buf;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_QSPI_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Quad SPI dma related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_QSPI_DMA_H_INCLUDED
|
||||
#define _HPL_QSPI_DMA_H_INCLUDED
|
||||
|
||||
#include <hpl_qspi.h>
|
||||
#include "hpl_irq.h"
|
||||
#include "hpl_dma.h"
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_qspi_dma HPL QSPI
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** The callback types */
|
||||
enum _qspi_dma_cb_type {
|
||||
/** Callback type for DMA transfer done */
|
||||
QSPI_DMA_CB_XFER_DONE,
|
||||
/** Callback type for DMA errors */
|
||||
QSPI_DMA_CB_ERROR,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief QSPI DMA callback type
|
||||
*/
|
||||
typedef void (*_qspi_dma_cb_t)(struct _dma_resource *resource);
|
||||
|
||||
/**
|
||||
* \brief The callbacks offered by QSPI driver
|
||||
*/
|
||||
struct _qspi_dma_callbacks {
|
||||
_qspi_dma_cb_t xfer_done;
|
||||
_qspi_dma_cb_t error;
|
||||
};
|
||||
|
||||
/**
|
||||
* QSPI dma driver instance.
|
||||
*/
|
||||
struct _qspi_dma_dev {
|
||||
/** Pointer to private data or hardware base */
|
||||
void *prvt;
|
||||
/**
|
||||
* Pointer to the callback functions so that initialize the driver to
|
||||
* handle interrupts.
|
||||
*/
|
||||
struct _qspi_dma_callbacks cb;
|
||||
/** DMA resource */
|
||||
struct _dma_resource *resource;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize QSPI for access without interrupts
|
||||
* It will load default hardware configuration and software struct.
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \param[in] hw Pointer to the hardware base.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_dma_init(struct _qspi_dma_dev *dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize QSPI
|
||||
* Disable, reset the hardware and the software struct.
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_dma_deinit(struct _qspi_dma_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Enable QSPI for access without interrupts
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_dma_enable(struct _qspi_dma_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Disable QSPI for access without interrupts
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_dma_disable(struct _qspi_dma_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Execute command in Serial Memory Mode.
|
||||
*
|
||||
* \param[in] dev The pointer to QSPI device instance
|
||||
* \param[in] cmd The pointer to the command information
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_dma_serial_run_command(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd);
|
||||
|
||||
/**
|
||||
* \brief Register the QSPI device callback
|
||||
* \param[in] dev Pointer to the SPI device instance.
|
||||
* \param[in] type The callback type.
|
||||
* \param[in] cb The callback function to register. NULL to disable callback.
|
||||
* \return Always 0.
|
||||
*/
|
||||
void _qspi_dma_register_callback(struct _qspi_dma_dev *dev, const enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_QSPI_DMA_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Quad SPI Sync related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_QSPI_SYNC_H_INCLUDED
|
||||
#define _HPL_QSPI_SYNC_H_INCLUDED
|
||||
|
||||
#include <hpl_qspi.h>
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_qspi HPL QSPI
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Quad SPI polling driver instance. */
|
||||
struct _qspi_sync_dev {
|
||||
/** Pointer to private data or hardware base */
|
||||
void *prvt;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize QSPI for access without interrupts
|
||||
* It will load default hardware configuration and software struct.
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \param[in] hw Pointer to the hardware base.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_sync_init(struct _qspi_sync_dev *dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize QSPI
|
||||
* Disable, reset the hardware and the software struct.
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_sync_deinit(struct _qspi_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Enable QSPI for access without interrupts
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_sync_enable(struct _qspi_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Disable QSPI for access without interrupts
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_sync_disable(struct _qspi_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Execute command in Serial Memory Mode.
|
||||
*
|
||||
* \param[in] dev The pointer to QSPI device instance
|
||||
* \param[in] cmd The pointer to the command information
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_sync_serial_run_command(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_QSPI_SYNC_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Common SPI DMA related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_SPI_DMA_H_INCLUDED
|
||||
#define _HPL_SPI_DMA_H_INCLUDED
|
||||
|
||||
#include <hpl_irq.h>
|
||||
#include <hpl_dma.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** The callback types */
|
||||
enum _spi_dma_dev_cb_type {
|
||||
/** Callback type for DMA transmit. */
|
||||
SPI_DEV_CB_DMA_TX,
|
||||
/** Callback type for DMA receive. */
|
||||
SPI_DEV_CB_DMA_RX,
|
||||
/** Callback type for DMA error. */
|
||||
SPI_DEV_CB_DMA_ERROR,
|
||||
/** Number of callbacks. */
|
||||
SPI_DEV_CB_DMA_N
|
||||
};
|
||||
|
||||
struct _spi_dma_dev;
|
||||
|
||||
/**
|
||||
* \brief The prototype for callback on SPI DMA.
|
||||
*/
|
||||
typedef void (*_spi_dma_cb_t)(struct _dma_resource *resource);
|
||||
|
||||
/**
|
||||
* \brief The callbacks offered by SPI driver
|
||||
*/
|
||||
struct _spi_dma_dev_callbacks {
|
||||
_spi_dma_cb_t tx;
|
||||
_spi_dma_cb_t rx;
|
||||
_spi_dma_cb_t error;
|
||||
};
|
||||
|
||||
/** SPI driver to support DMA HAL */
|
||||
struct _spi_dma_dev {
|
||||
/** Pointer to the hardware base or private data for special device. */
|
||||
void *prvt;
|
||||
/** Pointer to callback functions */
|
||||
struct _spi_dma_dev_callbacks callbacks;
|
||||
/** IRQ instance for SPI device. */
|
||||
struct _irq_descriptor irq;
|
||||
/** DMA resource */
|
||||
struct _dma_resource *resource;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _HPL_SPI_DMA_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Timer related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_TIMER_H_INCLUDED
|
||||
#define _HPL_TIMER_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Timer
|
||||
*
|
||||
* \section hpl_timer_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include <hpl_irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Timer device structure
|
||||
*
|
||||
* The Timer device structure forward declaration.
|
||||
*/
|
||||
struct _timer_device;
|
||||
|
||||
/**
|
||||
* \brief Timer interrupt callbacks
|
||||
*/
|
||||
struct _timer_callbacks {
|
||||
void (*period_expired)(struct _timer_device *device);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Timer device structure
|
||||
*/
|
||||
struct _timer_device {
|
||||
struct _timer_callbacks timer_cb;
|
||||
struct _irq_descriptor irq;
|
||||
void * hw;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Timer functions, pointers to low-level functions
|
||||
*/
|
||||
struct _timer_hpl_interface {
|
||||
int32_t (*init)(struct _timer_device *const device, void *const hw);
|
||||
void (*deinit)(struct _timer_device *const device);
|
||||
void (*start_timer)(struct _timer_device *const device);
|
||||
void (*stop_timer)(struct _timer_device *const device);
|
||||
void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles);
|
||||
uint32_t (*get_period)(const struct _timer_device *const device);
|
||||
bool (*is_timer_started)(const struct _timer_device *const device);
|
||||
void (*set_timer_irq)(struct _timer_device *const device);
|
||||
};
|
||||
/**
|
||||
* \brief Initialize TCC
|
||||
*
|
||||
* This function does low level TCC configuration.
|
||||
*
|
||||
* \param[in] device The pointer to timer device instance
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Initialization status.
|
||||
*/
|
||||
int32_t _timer_init(struct _timer_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize TCC
|
||||
*
|
||||
* \param[in] device The pointer to timer device instance
|
||||
*/
|
||||
void _timer_deinit(struct _timer_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Start hardware timer
|
||||
*
|
||||
* \param[in] device The pointer to timer device instance
|
||||
*/
|
||||
void _timer_start(struct _timer_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Stop hardware timer
|
||||
*
|
||||
* \param[in] device The pointer to timer device instance
|
||||
*/
|
||||
void _timer_stop(struct _timer_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set timer period
|
||||
*
|
||||
* \param[in] device The pointer to timer device instance
|
||||
*/
|
||||
void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles);
|
||||
|
||||
/**
|
||||
* \brief Retrieve timer period
|
||||
*
|
||||
* \param[in] device The pointer to timer device instance
|
||||
*
|
||||
* \return Timer period
|
||||
*/
|
||||
uint32_t _timer_get_period(const struct _timer_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if timer is running
|
||||
*
|
||||
* \param[in] device The pointer to timer device instance
|
||||
*
|
||||
* \return Check status.
|
||||
* \retval true The given timer is running
|
||||
* \retval false The given timer is not running
|
||||
*/
|
||||
bool _timer_is_started(const struct _timer_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set timer IRQ
|
||||
*
|
||||
* \param[in] device The pointer to timer device instance
|
||||
*/
|
||||
void _timer_set_irq(struct _timer_device *const device);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_TIMER_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief ADC functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Indicates HAL being compiled. Must be defined before including.
|
||||
*/
|
||||
#define _COMPILING_HAL
|
||||
|
||||
#include "hal_adc_sync.h"
|
||||
#include <utils_assert.h>
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define DRIVER_VERSION 0x00000001u
|
||||
|
||||
/**
|
||||
* \brief Maximum amount of ADC interface instances
|
||||
*/
|
||||
#define MAX_ADC_AMOUNT ADC_INST_NUM
|
||||
|
||||
/**
|
||||
* \brief Initialize ADC
|
||||
*/
|
||||
int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func)
|
||||
{
|
||||
ASSERT(descr && hw);
|
||||
|
||||
return _adc_sync_init(&descr->device, hw);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Deinitialize ADC
|
||||
*/
|
||||
int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_adc_sync_deinit(&descr->device);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable ADC
|
||||
*/
|
||||
int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_adc_sync_enable_channel(&descr->device, channel);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable ADC
|
||||
*/
|
||||
int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_adc_sync_disable_channel(&descr->device, channel);
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/*
|
||||
* \brief Read data from ADC
|
||||
*/
|
||||
int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
|
||||
const uint16_t length)
|
||||
{
|
||||
uint8_t data_size;
|
||||
uint16_t offset = 0;
|
||||
|
||||
ASSERT(descr && buffer && length);
|
||||
data_size = _adc_sync_get_data_size(&descr->device);
|
||||
ASSERT(!(length % data_size));
|
||||
|
||||
do {
|
||||
uint16_t result;
|
||||
_adc_sync_convert(&descr->device);
|
||||
|
||||
while (!_adc_sync_is_channel_conversion_done(&descr->device, channel))
|
||||
;
|
||||
|
||||
result = _adc_sync_read_channel_data(&descr->device, channel);
|
||||
buffer[offset] = result;
|
||||
if (1 < data_size) {
|
||||
buffer[offset + 1] = result >> 8;
|
||||
}
|
||||
offset += data_size;
|
||||
} while (offset < length);
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set ADC reference source
|
||||
*/
|
||||
int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_adc_sync_set_reference_source(&descr->device, reference);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set ADC resolution
|
||||
*/
|
||||
int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_adc_sync_set_resolution(&descr->device, resolution);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set ADC input source of a channel
|
||||
*/
|
||||
int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
|
||||
const adc_neg_input_t neg_input, const uint8_t channel)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_adc_sync_set_inputs(&descr->device, pos_input, neg_input, channel);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set ADC thresholds
|
||||
*/
|
||||
int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
|
||||
const adc_threshold_t up_threshold)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_adc_sync_set_thresholds(&descr->device, low_threshold, up_threshold);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set ADC gain
|
||||
*/
|
||||
int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, const adc_gain_t gain)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_adc_sync_set_channel_gain(&descr->device, channel, gain);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set ADC conversion mode
|
||||
*/
|
||||
int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_adc_sync_set_conversion_mode(&descr->device, mode);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set ADC differential mode
|
||||
*/
|
||||
int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
|
||||
const enum adc_differential_mode mode)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_adc_sync_set_channel_differential_mode(&descr->device, channel, mode);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set ADC window mode
|
||||
*/
|
||||
int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_adc_sync_set_window_mode(&descr->device, mode);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve threshold state
|
||||
*/
|
||||
int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, adc_threshold_status_t *const state)
|
||||
{
|
||||
ASSERT(descr && state);
|
||||
_adc_sync_get_threshold_state(&descr->device, state);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Check if conversion is complete
|
||||
*/
|
||||
int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel)
|
||||
{
|
||||
ASSERT(descr);
|
||||
return _adc_sync_is_channel_conversion_done(&descr->device, channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*/
|
||||
uint32_t adc_sync_get_version(void)
|
||||
{
|
||||
return DRIVER_VERSION;
|
||||
}
|
||||
|
||||
//@}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue