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master/slave dma seems to be working

This commit is contained in:
Nicolas Trimborn 2021-07-16 13:19:00 +02:00
parent 91269173aa
commit 76cd702edc
622 changed files with 263619 additions and 0 deletions
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.env_conf → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/AtmelStart.env_conf
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<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
<vendor>Atmel</vendor>
<name>My Project</name>
<description>Project generated by Atmel Start</description>
<url>http://start.atmel.com/</url>
<releases>
<release version="1.0.1">Initial version</release>
</releases>
<taxonomy>
<description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
</taxonomy>
<generators>
<generator id="AtmelStart">
<description>Atmel Start</description>
<select Dname="ATSAME54P20A" Dvendor="Atmel:3"/>
<command>http://start.atmel.com/</command>
<files>
<file category="generator" name="atmel_start_config.atstart"/>
<file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
</files>
</generator>
</generators>
<conditions>
<condition id="CMSIS Device Startup">
<description>Dependency on CMSIS core and Device Startup components</description>
<require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
<require Cclass="Device" Cgroup="Startup" Cversion="1.1.0"/>
</condition>
<condition id="ARMCC, GCC, IAR">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="ARMCC"/>
<accept Tcompiler="GCC"/>
<accept Tcompiler="IAR"/>
</condition>
<condition id="GCC">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="GCC"/>
</condition>
<condition id="IAR">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="IAR"/>
</condition>
<condition id="ARMCC">
<require Dname="ATSAME54P20A"/>
<accept Tcompiler="ARMCC"/>
</condition>
</conditions>
<components generator="AtmelStart">
<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
<description>Atmel Start Framework</description>
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
<files>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/evsys.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/quad_spi_sync.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_dma.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_sync.rst"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_evsys.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_qspi_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_cmcc.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_evsys.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_cache.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_evsys.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_qspi_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hpl/doc_lite/tc.rst"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_can_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_cmcc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dac_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gmac_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hmatrixb_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_i2s_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_icm_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pcc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pdec_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_qspi_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ramecc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sdhc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_e54.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e54.h"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="documentation/stdio.rst"/>
<file category="source" condition="GCC" name="stdio_redirect/gcc/read.c"/>
<file category="source" condition="GCC" name="stdio_redirect/gcc/write.c"/>
<file category="source" condition="IAR" name="stdio_redirect/iar/read.c"/>
<file category="source" condition="IAR" name="stdio_redirect/iar/write.c"/>
<file category="source" condition="ARMCC" name="stdio_redirect/keil/Retarget.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="stdio_redirect/stdio_io.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="stdio_redirect/stdio_io.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_dma.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_sync.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/cmcc/hpl_cmcc.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m4.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/evsys/hpl_evsys.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/qspi/hpl_qspi.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="stdio_start.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="stdio_start.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_evsys_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_qspi_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/stdio_redirect_config.h"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
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</component>
</components>
</package>

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Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/.atmelstart/atmel_start_config.atstart Normal file
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/RTE_Components.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/RTE_Components.h
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_cmcc_config.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_cmcc_config.h
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_dmac_config.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_dmac_config.h
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_evsys_config.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_evsys_config.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_gclk_config.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_gclk_config.h
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_mclk_config.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_mclk_config.h
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_osc32kctrl_config.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_osc32kctrl_config.h
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_oscctrl_config.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_oscctrl_config.h
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_port_config.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_port_config.h
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Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_qspi_config.h Normal file
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@ -0,0 +1,84 @@
/* Auto-generated config file hpl_qspi_config.h */
#ifndef HPL_QSPI_CONFIG_H
#define HPL_QSPI_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <h> Basic settings
#ifndef CONF_CONF_QSPI_ENABLE
#define CONF_CONF_QSPI_ENABLE 1
#endif
// <o> Baud rate <1-150000000>
// <i> The SPI data transfer rate. Note: (fqspi_clock / baudrate) < 255
// <id> qspi_baud_rate
#ifndef CONF_QSPI_BAUD
#define CONF_QSPI_BAUD 6000000
#endif
// <o> Clock Polarity
// <0x0=>The inactive state value of SPCK is logic level zero.
// <0x1=>The inactive state value of SPCK is logic level one.
// <i> Determines the inactive state value of the serial clock (SPCK).
// <id> qspi_cpol
#ifndef CONF_QSPI_CPOL
#define CONF_QSPI_CPOL 0x0
#endif
// <o> Clock Phase
// <0x0=>Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
// <0x1=>Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
// <i> Determines which edge of SPCK causes data to change and which edge causes data to be captured.
// <id> qspi_cpha
#ifndef CONF_QSPI_CPHA
#define CONF_QSPI_CPHA 0x0
#endif
// </h>
// <e> Advanced Configuration
// <id> qspi_advanced
#ifndef CONF_QSPI_ADVANCED
#define CONF_QSPI_ADVANCED 0
#endif
// <o> Delay Before QSCK (ns) <0-255000>
// <i> This field defines the delay from QCS falling edge (activation) to the first valid QSCK transition (in ns).
// <id> qspi_dlybs
#ifndef CONF_QSPI_DLY_BS
#define CONF_QSPI_DLY_BS 0
#endif
// <o> Minimum Inactive QCS Delay (ns) <0-8160000>
// <i> This field defines the minimum delay between the deactivation and the activation of QCS (in ns).
// <id> qspi_dlycs
#ifndef CONF_QSPI_DLY_CS
#define CONF_QSPI_DLY_CS 0
#endif
// </e>
/* Calculate baud register value from requested baudrate value */
#ifndef CONF_QSPI_BAUD_RATE
#define CONF_QSPI_BAUD_RATE ((CONF_CPU_FREQUENCY / CONF_QSPI_BAUD) - 1)
#if CONF_QSPI_BAUD > CONF_CPU_FREQUENCY || CONF_QSPI_BAUD_RATE > 255
#warning Invalid baudrate, please check.
#endif
#endif
/* Calculates the value of the CSR DLYCS field given the desired delay (in ns) */
#ifndef CONF_QSPI_DLYCS
#define CONF_QSPI_DLYCS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_CS) / 1000)
#endif
/* Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
#ifndef CONF_QSPI_DLYBS
#define CONF_QSPI_DLYBS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_BS) / 1000)
#endif
// <<< end of configuration section >>>
#endif // HPL_QSPI_CONFIG_H

0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_sercom_config.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/hpl_sercom_config.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/peripheral_clk_config.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/peripheral_clk_config.h
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Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/spi_slave_dma_config.h Normal file
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/**
* \file
*
* \brief Application implement
*
* Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef SPI_SLAVE_DMA_CONFIG_H
#define SPI_SLAVE_DMA_CONFIG_H
// <o> Delay in Micro Seconds <1-1000>
// <i> Delay in microseconds to hold CS low after data transfer completion by DMA
// <id> delay_in_us_cs_low
#ifndef CONF_DELAY_US
#define CONF_DELAY_US 10
#endif
#endif

0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/stdio_redirect_config.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Config/stdio_redirect_config.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Default.xml → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Default.xml
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_flash.ld → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_flash.ld
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_sram.ld → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/same54p20a_sram.ld
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/startup_same54.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/startup_same54.c
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/system_same54.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Device_Startup/system_same54.c
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.componentinfo.xml → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.componentinfo.xml
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Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/Master_Slave_IF_TestMaster.cproj Normal file
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<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hpl_spi_s_async.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hpl_spi_s_sync.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hpl_usart.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hpl_usart_async.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\include\hpl_usart_sync.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_atomic.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_cache.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_delay.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_evsys.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_gpio.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_init.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_io.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_qspi_sync.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_sleep.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_spi_m_dma.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\src\hal_usart_sync.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\include\compiler.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\include\err_codes.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\include\events.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\include\parts.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\include\utils.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\include\utils_assert.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\include\utils_event.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\include\utils_increment_macro.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\include\utils_list.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\include\utils_repeat_macro.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\src\utils_assert.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\src\utils_event.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\src\utils_list.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hal\utils\src\utils_syscalls.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\cmcc\hpl_cmcc.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\core\hpl_core_m4.c">
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</Compile>
<Compile Include="hpl\core\hpl_core_port.h">
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</Compile>
<Compile Include="hpl\core\hpl_init.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\dmac\hpl_dmac.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\evsys\hpl_evsys.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\gclk\hpl_gclk.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\gclk\hpl_gclk_base.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\mclk\hpl_mclk.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\osc32kctrl\hpl_osc32kctrl.c">
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</Compile>
<Compile Include="hpl\oscctrl\hpl_oscctrl.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\pm\hpl_pm.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\pm\hpl_pm_base.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\port\hpl_gpio_base.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\qspi\hpl_qspi.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\ramecc\hpl_ramecc.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\sercom\hpl_sercom.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\tc\tc_lite.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="hpl\tc\tc_lite.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_ac_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_adc_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_aes_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_can_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_ccl_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_cmcc_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_dac_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_dmac_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_dsu_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_eic_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_evsys_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_freqm_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_gclk_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_gmac_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_hmatrixb_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_i2s_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_icm_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_mclk_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_nvmctrl_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_osc32kctrl_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_oscctrl_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_pac_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_pcc_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_pdec_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_pm_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_port_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_qspi_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_ramecc_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_rstc_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_rtc_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_sdhc_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_sercom_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_supc_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_tcc_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_tc_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_trng_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_usb_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="hri\hri_wdt_e54.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="main.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="stdio_redirect\gcc\read.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="stdio_redirect\gcc\write.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="stdio_redirect\stdio_io.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="stdio_redirect\stdio_io.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="stdio_start.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="stdio_start.h">
<SubType>compile</SubType>
</Compile>
</ItemGroup>
<ItemGroup>
<Folder Include="Config\" />
<Folder Include="Device_Startup\" />
<Folder Include="documentation\" />
<Folder Include="ethercat" />
<Folder Include="examples\" />
<Folder Include="hal\" />
<Folder Include="hal\documentation\" />
<Folder Include="hal\include\" />
<Folder Include="hal\src\" />
<Folder Include="hal\utils\" />
<Folder Include="hal\utils\include\" />
<Folder Include="hal\utils\src\" />
<Folder Include="hpl\" />
<Folder Include="hpl\cmcc\" />
<Folder Include="hpl\core\" />
<Folder Include="hpl\dmac\" />
<Folder Include="hpl\doc_lite\" />
<Folder Include="hpl\evsys\" />
<Folder Include="hpl\gclk\" />
<Folder Include="hpl\mclk\" />
<Folder Include="hpl\osc32kctrl\" />
<Folder Include="hpl\oscctrl\" />
<Folder Include="hpl\pm\" />
<Folder Include="hpl\port\" />
<Folder Include="hpl\qspi\" />
<Folder Include="hpl\ramecc\" />
<Folder Include="hpl\sercom\" />
<Folder Include="hpl\tc\" />
<Folder Include="hri\" />
<Folder Include="stdio_redirect\" />
<Folder Include="stdio_redirect\gcc\" />
</ItemGroup>
<ItemGroup>
<None Include="Device_Startup\same54p20a_flash.ld">
<SubType>compile</SubType>
</None>
<None Include="Device_Startup\same54p20a_sram.ld">
<SubType>compile</SubType>
</None>
<None Include="documentation\stdio.rst">
<SubType>compile</SubType>
</None>
<None Include="hal\documentation\evsys.rst">
<SubType>compile</SubType>
</None>
<None Include="hal\documentation\quad_spi_sync.rst">
<SubType>compile</SubType>
</None>
<None Include="hal\documentation\spi_master_dma.rst">
<SubType>compile</SubType>
</None>
<None Include="hal\documentation\usart_sync.rst">
<SubType>compile</SubType>
</None>
<None Include="hpl\doc_lite\tc.rst">
<SubType>compile</SubType>
</None>
</ItemGroup>
<Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
</Project>

0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.c
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start.h
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43
Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/atmel_start_pins.h Normal file
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@ -0,0 +1,43 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef ATMEL_START_PINS_H_INCLUDED
#define ATMEL_START_PINS_H_INCLUDED
#include <hal_gpio.h>
// SAME54 has 14 pin functions
#define GPIO_PIN_FUNCTION_A 0
#define GPIO_PIN_FUNCTION_B 1
#define GPIO_PIN_FUNCTION_C 2
#define GPIO_PIN_FUNCTION_D 3
#define GPIO_PIN_FUNCTION_E 4
#define GPIO_PIN_FUNCTION_F 5
#define GPIO_PIN_FUNCTION_G 6
#define GPIO_PIN_FUNCTION_H 7
#define GPIO_PIN_FUNCTION_I 8
#define GPIO_PIN_FUNCTION_J 9
#define GPIO_PIN_FUNCTION_K 10
#define GPIO_PIN_FUNCTION_L 11
#define GPIO_PIN_FUNCTION_M 12
#define GPIO_PIN_FUNCTION_N 13
#define PA08 GPIO(GPIO_PORTA, 8)
#define PA09 GPIO(GPIO_PORTA, 9)
#define PA10 GPIO(GPIO_PORTA, 10)
#define PA11 GPIO(GPIO_PORTA, 11)
#define PB10 GPIO(GPIO_PORTB, 10)
#define PB11 GPIO(GPIO_PORTB, 11)
#define PB24 GPIO(GPIO_PORTB, 24)
#define PB25 GPIO(GPIO_PORTB, 25)
#define PB26 GPIO(GPIO_PORTB, 26)
#define PB27 GPIO(GPIO_PORTB, 27)
#define SPI_CS GPIO(GPIO_PORTB, 28)
#define PB29 GPIO(GPIO_PORTB, 29)
#endif // ATMEL_START_PINS_H_INCLUDED

0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/documentation/stdio.rst → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/documentation/stdio.rst
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369
Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/driver_init.c Normal file
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@ -0,0 +1,369 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_init.h"
#include <peripheral_clk_config.h>
#include <utils.h>
#include <hal_init.h>
struct qspi_sync_descriptor QUAD_SPI_0;
struct usart_sync_descriptor TARGET_IO;
struct spi_m_dma_descriptor SPI_0;
void EVENT_SYSTEM_0_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);
event_system_init();
}
void QUAD_SPI_0_PORT_init(void)
{
// Set pin direction to input
gpio_set_pin_direction(PB11, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PB11,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB11, PINMUX_PB11H_QSPI_CS);
gpio_set_pin_direction(PA08,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(PA08,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(PA08,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA08,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA08H_QSPI_DATA0"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
// <GPIO_PIN_FUNCTION_I"> I
// <GPIO_PIN_FUNCTION_J"> J
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA08H_QSPI_DATA0);
gpio_set_pin_direction(PA09,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(PA09,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(PA09,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA09,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA09H_QSPI_DATA1"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
// <GPIO_PIN_FUNCTION_I"> I
// <GPIO_PIN_FUNCTION_J"> J
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA09H_QSPI_DATA1);
gpio_set_pin_direction(PA10,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(PA10,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(PA10,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA10,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA10H_QSPI_DATA2"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
// <GPIO_PIN_FUNCTION_I"> I
// <GPIO_PIN_FUNCTION_J"> J
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA10H_QSPI_DATA2);
gpio_set_pin_direction(PA11,
// <y> Pin direction
// <id> pad_direction
// <GPIO_DIRECTION_OFF"> Off
// <GPIO_DIRECTION_IN"> In
// <GPIO_DIRECTION_OUT"> Out
GPIO_DIRECTION_OUT);
gpio_set_pin_level(PA11,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
gpio_set_pin_pull_mode(PA11,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PA11,
// <y> Pin function
// <id> pad_function
// <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
// <PINMUX_PA11H_QSPI_DATA3"> Auto
// <GPIO_PIN_FUNCTION_OFF"> Off
// <GPIO_PIN_FUNCTION_A"> A
// <GPIO_PIN_FUNCTION_B"> B
// <GPIO_PIN_FUNCTION_C"> C
// <GPIO_PIN_FUNCTION_D"> D
// <GPIO_PIN_FUNCTION_E"> E
// <GPIO_PIN_FUNCTION_F"> F
// <GPIO_PIN_FUNCTION_G"> G
// <GPIO_PIN_FUNCTION_H"> H
// <GPIO_PIN_FUNCTION_I"> I
// <GPIO_PIN_FUNCTION_J"> J
// <GPIO_PIN_FUNCTION_K"> K
// <GPIO_PIN_FUNCTION_L"> L
// <GPIO_PIN_FUNCTION_M"> M
// <GPIO_PIN_FUNCTION_N"> N
PINMUX_PA11H_QSPI_DATA3);
// Set pin direction to input
gpio_set_pin_direction(PB10, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PB10,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB10, PINMUX_PB10H_QSPI_SCK);
}
void QUAD_SPI_0_CLOCK_init(void)
{
hri_mclk_set_AHBMASK_QSPI_bit(MCLK);
hri_mclk_set_AHBMASK_QSPI_2X_bit(MCLK);
hri_mclk_set_APBCMASK_QSPI_bit(MCLK);
}
void QUAD_SPI_0_init(void)
{
QUAD_SPI_0_CLOCK_init();
qspi_sync_init(&QUAD_SPI_0, QSPI);
QUAD_SPI_0_PORT_init();
}
void TARGET_IO_PORT_init(void)
{
gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0);
gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1);
}
void TARGET_IO_CLOCK_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
}
void TARGET_IO_init(void)
{
TARGET_IO_CLOCK_init();
usart_sync_init(&TARGET_IO, SERCOM2, (void *)NULL);
TARGET_IO_PORT_init();
}
void SPI_0_PORT_init(void)
{
gpio_set_pin_level(PB27,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(PB27, GPIO_DIRECTION_OUT);
gpio_set_pin_function(PB27, PINMUX_PB27D_SERCOM4_PAD0);
gpio_set_pin_level(PB26,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(PB26, GPIO_DIRECTION_OUT);
gpio_set_pin_function(PB26, PINMUX_PB26D_SERCOM4_PAD1);
// Set pin direction to input
gpio_set_pin_direction(PB29, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PB29,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PB29, PINMUX_PB29D_SERCOM4_PAD3);
}
void SPI_0_CLOCK_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBDMASK_SERCOM4_bit(MCLK);
}
void SPI_0_init(void)
{
SPI_0_CLOCK_init();
spi_m_dma_init(&SPI_0, SERCOM4);
SPI_0_PORT_init();
}
void TIMER_0_CLOCK_init(void)
{
hri_mclk_set_APBAMASK_TC0_bit(MCLK);
hri_mclk_set_APBAMASK_TC1_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void system_init(void)
{
init_mcu();
// GPIO on PB28
gpio_set_pin_level(SPI_CS,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
true);
// Set pin direction to output
gpio_set_pin_direction(SPI_CS, GPIO_DIRECTION_OUT);
gpio_set_pin_function(SPI_CS, GPIO_PIN_FUNCTION_OFF);
EVENT_SYSTEM_0_init();
QUAD_SPI_0_init();
TARGET_IO_init();
SPI_0_init();
TIMER_0_CLOCK_init();
TIMER_0_init();
}

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_INIT_INCLUDED
#define DRIVER_INIT_INCLUDED
#include "atmel_start_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <hal_atomic.h>
#include <hal_delay.h>
#include <hal_gpio.h>
#include <hal_init.h>
#include <hal_io.h>
#include <hal_sleep.h>
#include <hal_evsys.h>
#include <hal_qspi_sync.h>
#include <hal_usart_sync.h>
#include <hal_spi_m_dma.h>
#include <tc_lite.h>
extern struct qspi_sync_descriptor QUAD_SPI_0;
extern struct usart_sync_descriptor TARGET_IO;
extern struct spi_m_dma_descriptor SPI_0;
void QUAD_SPI_0_PORT_init(void);
void QUAD_SPI_0_CLOCK_init(void);
void QUAD_SPI_0_init(void);
void TARGET_IO_PORT_init(void);
void TARGET_IO_CLOCK_init(void);
void TARGET_IO_init(void);
void SPI_0_PORT_init(void);
void SPI_0_CLOCK_init(void);
void SPI_0_init(void);
void TIMER_0_CLOCK_init(void);
int8_t TIMER_0_init(void);
/**
* \brief Perform system initialization, initialize pins and clocks for
* peripherals
*/
void system_init(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_INIT_INCLUDED

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/*
* ethercat_qspi.c
*
* Created: 15/07/2021 19:30:41
* Author: Nick-XMG
*/
#include "ethercat_qspi.h"
#define ECAT_SIZE_WR 64 //max fifo size
#define ECAT_SIZE_RD ECAT_SIZE_WR
#define ECAT_SIZE_WR_REG ECAT_SIZE_WR/4
#define ECAT_SIZE_RD_REG ECAT_SIZE_WR/4
#define SQI_READ (0x0B<<16)
#define SQI_WRITE (0x02<<16)
#define SQI_INC (0x40<<8)
#define SQI_DEC (0x80<<8)
#define ECAT_PRAM_RD_DATA 0x0000
#define ECAT_PRAM_WR_DATA 0x0020
#define HW_CFG 0x0074
#define BYTE_TEST 0x0064
#define ECAT_PRAM_RD_ADDR_LEN 0x0308
#define ECAT_PRAM_RD_CMD 0x030C
#define ECAT_PRAM_WR_ADDR_LEN 0x0310
#define ECAT_PRAM_WR_CMD 0x0314
#define LAN9252_RDY (1<<27)
#define PDRAM_RD_ADDRESS 0x1100
#define PDRAM_RD_LENGTH ECAT_SIZE_RD //do the math later to automatize. fixed to 64 for now.
#define PDRAM_WR_ADDRESS 0x1800
#define PDRAM_WR_LENGTH ECAT_SIZE_WR
#define PDRAM_LENGTH_MAX 64
#define PDRAM_LENGTH_SHORT 32
#define FIFO_DEPTH 16
#define PDRAM_REG_MAX PDRAM_LENGTH_SHORT/4
#define PRAM_X_ABORT (1<<30)
#define CSR_BUSY 0x80000000
#define buffer_size 3*ECAT_SIZE_WR_REG //changed to double
#define motor_buffer_size buffer_size/3
uint32_t QSPI_tx_buffer[buffer_size]={0};
uint32_t QSPI_rx_buffer[buffer_size]={0};
struct SPI_Slave S1 = {
.SPI_Sn = &SPI_0,
.state = 0,
.SS_pin = SPI_CS,
.tx_buffer = &QSPI_rx_buffer[0],
.rx_buffer = &QSPI_tx_buffer[0],
};
uint32_t QSPI_cmds[]= {0,PRAM_X_ABORT,0,PRAM_X_ABORT,
((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS,CSR_BUSY,
((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX,CSR_BUSY,
((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX*2, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX*2,CSR_BUSY,
};
uint32_t zero[FIFO_DEPTH]={0};
struct _qspi_command rd_cmd = {
.inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
.inst_frame.bits.inst_en = 0,
.inst_frame.bits.data_en = 1,
.inst_frame.bits.addr_en = 1,
.inst_frame.bits.dummy_cycles = 6,
.inst_frame.bits.tfr_type = QSPI_READMEM_ACCESS,
};
struct _qspi_command wr_cmd = {
.inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
.inst_frame.bits.inst_en = 0,
.inst_frame.bits.data_en = 1,
.inst_frame.bits.addr_en = 1,
.inst_frame.bits.dummy_cycles = 0,
.inst_frame.bits.tfr_type = QSPI_WRITEMEM_ACCESS,
};
struct _qspi_command qspi_cmd = {
.inst_frame.bits.width = QSPI_INST1_ADDR1_DATA1,
.inst_frame.bits.inst_en = 1,
.inst_frame.bits.data_en = 0,
.inst_frame.bits.addr_en = 0,
.inst_frame.bits.dummy_cycles = 0,
.instruction = 0x38,
.inst_frame.bits.tfr_type = QSPI_WRITE_ACCESS,
};
volatile uint8_t SPI_S1_SS_state = 0;
volatile uint8_t* M1_tx_cnt = &QSPI_rx_buffer[0];
volatile uint8_t* M1_rx_cnt = &QSPI_tx_buffer[0];
uint8_t sync_rx_buffer[2*2*buffer_size/3]={0};
uint8_t sync_tx_buffer[2*2*buffer_size/3]={0xED};
volatile uint32_t status = 0;
struct _qspi_command *spi_cmd= &wr_cmd;
volatile uint8_t tx_complete=3;
volatile uint32_t *ECAT_BYTE_TEST = QSPI_AHB+BYTE_TEST+SQI_READ;
volatile uint32_t *ECAT_FIFO_RD_RD = QSPI_AHB+SQI_READ +ECAT_PRAM_RD_DATA;
volatile uint32_t *ECAT_FIFO_WR_WR = QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_DATA;
volatile uint32_t *ECAT_HW_CFG_RD = QSPI_AHB+SQI_READ+HW_CFG;
volatile uint32_t *ECAT_FIFO_RD_ADLEN_WR = QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_RD_ADDR_LEN;
volatile uint32_t *ECAT_FIFO_WR_ADLEN_WR = QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
volatile uint32_t *ECAT_FIFO_WR_ADLEN_RD = QSPI_AHB+SQI_READ+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
volatile uint32_t *ECAT_FIFO_WR_CMD_RD = QSPI_AHB+SQI_READ+ECAT_PRAM_WR_CMD;
volatile uint32_t *ECAT_FIFO_WR_CMD_WR = QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_CMD;
volatile enum ecat_states ecat_state = wait;
volatile enum ecat_states next_ecat_state = wait;

69
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/*
* ethercat_qspi.h
*
* Created: 15/07/2021 19:30:17
* Author: Nick-XMG
*/
#ifndef ETHERCAT_QSPI_H_
#define ETHERCAT_QSPI_H_
#include "atmel_start.h"
#include "math.h"
extern uint32_t QSPI_tx_buffer[];
extern uint32_t QSPI_rx_buffer[];
struct SPI_Slave {
struct spi_m_dma_descriptor *SPI_Sn;
uint8_t state;
uint32_t SS_pin;
uint32_t *tx_buffer;
uint32_t *rx_buffer;
};
COMPILER_ALIGNED(16)
DmacDescriptor dummy_rx_descriptor;
DmacDescriptor dummy_tx_descriptor;
volatile uint8_t SPI_S1_SS_state;
volatile uint8_t *M1_tx_cnt;
volatile uint8_t *M1_rx_cnt;
extern uint8_t sync_rx_buffer[];
extern uint8_t sync_tx_buffer[];
extern uint32_t QSPI_cmds[];
extern uint32_t zero[];
struct _qspi_command *spi_cmd;
volatile uint32_t *INPUT_ADDRESS ;
volatile uint32_t *OUTPUT_ADDRESS;
volatile uint32_t read_buffer =0;
volatile uint8_t ecat_length= 0;
struct io_descriptor *SPI_S1_io;
enum ecat_states {
abort_fifo,
dlt_rdram,
cf_dlt_rdram,
write_fifo,
config_fifo,
read_fifo,
wait,
wait2,
en_SQI,
temp,rd_rdy
};
volatile enum ecat_states ecat_state;
volatile enum ecat_states next_ecat_state;
volatile uint8_t wr_cnt = 0;
volatile uint8_t rd_cnt = 0;
volatile init_timer =0;
volatile bool run_ECAT = false;
#endif /* ETHERCAT_QSPI_H_ */

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_examples.h"
#include "driver_init.h"
#include "utils.h"
/**
* Example of using QUAD_SPI_0 to get N25Q256A status value,
* and check bit 0 which indicate embedded operation is busy or not.
*/
void QUAD_SPI_0_example(void)
{
uint8_t status = 0xFF;
struct _qspi_command cmd = {
.inst_frame.bits.inst_en = 1,
.inst_frame.bits.data_en = 1,
.inst_frame.bits.tfr_type = QSPI_READ_ACCESS,
.instruction = 0x05,
.buf_len = 1,
.rx_buf = &status,
};
qspi_sync_enable(&QUAD_SPI_0);
while (status & (1 << 0)) {
qspi_sync_serial_run_command(&QUAD_SPI_0, &cmd);
}
qspi_sync_deinit(&QUAD_SPI_0);
}
/**
* Example of using TARGET_IO to write "Hello World" using the IO abstraction.
*/
void TARGET_IO_example(void)
{
struct io_descriptor *io;
usart_sync_get_io_descriptor(&TARGET_IO, &io);
usart_sync_enable(&TARGET_IO);
io_write(io, (uint8_t *)"Hello World!", 12);
}
/**
* Example of using SPI_0 to write "Hello World" using the IO abstraction.
*
* Since the driver is asynchronous we need to use statically allocated memory for string
* because driver initiates transfer and then returns before the transmission is completed.
*
* Once transfer has been completed the tx_cb function will be called.
*/
static uint8_t example_SPI_0[12] = "Hello World!";
static void tx_complete_cb_SPI_0(struct _dma_resource *resource)
{
/* Transfer completed */
}
void SPI_0_example(void)
{
struct io_descriptor *io;
spi_m_dma_get_io_descriptor(&SPI_0, &io);
spi_m_dma_register_callback(&SPI_0, SPI_M_DMA_CB_TX_DONE, tx_complete_cb_SPI_0);
spi_m_dma_enable(&SPI_0);
io_write(io, example_SPI_0, 12);
}

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/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_EXAMPLES_H_INCLUDED
#define DRIVER_EXAMPLES_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
void QUAD_SPI_0_example(void);
void TARGET_IO_example(void);
void SPI_0_example(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_EXAMPLES_H_INCLUDED

0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/evsys.rst → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/evsys.rst
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The Quad SPI Synchronous Driver
=================================
The Quad SPI Interface (QSPI) is a synchronous serial data link that provides
communication with external devices in master mode.
The driver can be used for SPI serial memory middleware which support flash
earse, program and read.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Execute command in Serial Memory Mode
Applications
------------
They are commonly used in an application for using serial flash memory operating
in single-bit SPI, Dual SPI and Quad SPI.
Dependencies
------------
Serial NOR flash with Multiple I/O hardware
Concurrency
-----------
N/A
Limitations
-----------
N.A
Known issues and workarounds
----------------------------
N/A

0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/spi_master_dma.rst → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/spi_master_dma.rst
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/usart_sync.rst → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/documentation/usart_sync.rst
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_atomic.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_atomic.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_cache.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_cache.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_delay.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_delay.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_evsys.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_evsys.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_gpio.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_gpio.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_init.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_init.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_io.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_io.h
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/**
* \file
*
* \brief Quad QSPI related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_QSPI_INCLUDED
#define _HAL_QSPI_INCLUDED
#include <hpl_qspi_sync.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_quad_spi_sync
*
*@{
*/
/**
* \brief QSPI descriptor structure
*/
struct qspi_sync_descriptor {
struct _qspi_sync_dev dev;
};
/**
* \brief Initialize QSPI low level driver.
*
* \param[in] qspi Pointer to the QSPI device instance
* \param[in] hw Pointer to the hardware base
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_sync_init(struct qspi_sync_descriptor *qspi, void *hw);
/**
* \brief Deinitialize QSPI low level driver.
*
* \param[in] qspi Pointer to the QSPI device instance
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_sync_deinit(struct qspi_sync_descriptor *qspi);
/**
* \brief Enable QSPI for access without interrupts
*
* \param[in] qspi Pointer to the QSPI device instance
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_sync_enable(struct qspi_sync_descriptor *qspi);
/**
* \brief Disable QSPI for access without interrupts
*
* Disable QSPI. Deactivate all CS pins if it works as master.
*
* \param[in] qspi Pointer to the QSPI device instance
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_sync_disable(struct qspi_sync_descriptor *qspi);
/** \brief Execute command in Serial Memory Mode.
*
* \param[in] qspi Pointer to the HAL QSPI instance
* \param[in] cmd Pointer to the command structure
*
* \return Operation status.
* \retval ERR_NONE Success
*/
int32_t qspi_sync_serial_run_command(struct qspi_sync_descriptor *qspi, const struct _qspi_command *cmd);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t qspi_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_QSPI_INCLUDED */

0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_sleep.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_sleep.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_dma.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_spi_m_dma.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_usart_sync.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hal_usart_sync.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_cmcc.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_cmcc.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_core.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_core.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_delay.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_delay.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_dma.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_dma.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_evsys.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_evsys.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_gpio.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_gpio.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_async.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_async.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_sync.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_m_sync.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_async.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_async.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_sync.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_i2c_s_sync.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_init.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_init.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_irq.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_irq.h
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_missing_features.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_missing_features.h
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/**
* \file
*
* \brief Quad SPI related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_QSPI_H_INCLUDED
#define _HPL_QSPI_H_INCLUDED
#include "compiler.h"
/**
* \addtogroup hpl_qspi HPL QSPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Qspi access modes
*/
enum qspi_access {
/* Read access */
QSPI_READ_ACCESS = 0,
/* Read memory access */
QSPI_READMEM_ACCESS,
/* Write access */
QSPI_WRITE_ACCESS,
/* Write memory access */
QSPI_WRITEMEM_ACCESS
};
/**
* \brief QSPI command instruction/address/data width
*/
enum qspi_cmd_width {
/** Instruction: Single-bit, Address: Single-bit, Data: Single-bit */
QSPI_INST1_ADDR1_DATA1,
/** Instruction: Single-bit, Address: Single-bit, Data: Dual-bit */
QSPI_INST1_ADDR1_DATA2,
/** Instruction: Single-bit, Address: Single-bit, Data: Quad-bit */
QSPI_INST1_ADDR1_DATA4,
/** Instruction: Single-bit, Address: Dual-bit, Data: Dual-bit */
QSPI_INST1_ADDR2_DATA2,
/** Instruction: Single-bit, Address: Quad-bit, Data: Quad-bit */
QSPI_INST1_ADDR4_DATA4,
/** Instruction: Dual-bit, Address: Dual-bit, Data: Dual-bit */
QSPI_INST2_ADDR2_DATA2,
/** Instruction: Quad-bit, Address: Quad-bit, Data: Quad-bit */
QSPI_INST4_ADDR4_DATA4
};
/**
* \brief QSPI command option code length in bits
*/
enum qspi_cmd_opt_len {
/** The option code is 1 bit long */
QSPI_OPT_1BIT,
/** The option code is 2 bits long */
QSPI_OPT_2BIT,
/** The option code is 4 bits long */
QSPI_OPT_4BIT,
/** The option code is 8 bits long */
QSPI_OPT_8BIT
};
/**
* \brief Qspi command structure
*/
struct _qspi_command {
union {
struct {
/* Width of QSPI Addr , inst data */
uint32_t width : 3;
/* Reserved */
uint32_t reserved0 : 1;
/* Enable Instruction */
uint32_t inst_en : 1;
/* Enable Address */
uint32_t addr_en : 1;
/* Enable Option */
uint32_t opt_en : 1;
/* Enable Data */
uint32_t data_en : 1;
/* Option Length */
uint32_t opt_len : 2;
/* Address Length */
uint32_t addr_len : 1;
/* Option Length */
uint32_t reserved1 : 1;
/* Transfer type */
uint32_t tfr_type : 2;
/* Continuous read mode */
uint32_t continues_read : 1;
/* Enable Double Data Rate */
uint32_t ddr_enable : 1;
/* Dummy Cycles Length */
uint32_t dummy_cycles : 5;
/* Reserved */
uint32_t reserved3 : 11;
} bits;
uint32_t word;
} inst_frame;
uint8_t instruction;
uint8_t option;
uint32_t address;
size_t buf_len;
const void *tx_buf;
void * rx_buf;
};
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_QSPI_H_INCLUDED */

146
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/**
* \file
*
* \brief Quad SPI dma related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_QSPI_DMA_H_INCLUDED
#define _HPL_QSPI_DMA_H_INCLUDED
#include <hpl_qspi.h>
#include "hpl_irq.h"
#include "hpl_dma.h"
/**
* \addtogroup hpl_qspi_dma HPL QSPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** The callback types */
enum _qspi_dma_cb_type {
/** Callback type for DMA transfer done */
QSPI_DMA_CB_XFER_DONE,
/** Callback type for DMA errors */
QSPI_DMA_CB_ERROR,
};
/**
* \brief QSPI DMA callback type
*/
typedef void (*_qspi_dma_cb_t)(struct _dma_resource *resource);
/**
* \brief The callbacks offered by QSPI driver
*/
struct _qspi_dma_callbacks {
_qspi_dma_cb_t xfer_done;
_qspi_dma_cb_t error;
};
/**
* QSPI dma driver instance.
*/
struct _qspi_dma_dev {
/** Pointer to private data or hardware base */
void *prvt;
/**
* Pointer to the callback functions so that initialize the driver to
* handle interrupts.
*/
struct _qspi_dma_callbacks cb;
/** DMA resource */
struct _dma_resource *resource;
};
/**
* \brief Initialize QSPI for access without interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the QSPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_dma_init(struct _qspi_dma_dev *dev, void *const hw);
/**
* \brief Deinitialize QSPI
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the QSPI device instance.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_dma_deinit(struct _qspi_dma_dev *dev);
/**
* \brief Enable QSPI for access without interrupts
* \param[in, out] dev Pointer to the QSPI device instance.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_dma_enable(struct _qspi_dma_dev *dev);
/**
* \brief Disable QSPI for access without interrupts
* \param[in, out] dev Pointer to the QSPI device instance.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_dma_disable(struct _qspi_dma_dev *dev);
/**
* \brief Execute command in Serial Memory Mode.
*
* \param[in] dev The pointer to QSPI device instance
* \param[in] cmd The pointer to the command information
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_dma_serial_run_command(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd);
/**
* \brief Register the QSPI device callback
* \param[in] dev Pointer to the SPI device instance.
* \param[in] type The callback type.
* \param[in] cb The callback function to register. NULL to disable callback.
* \return Always 0.
*/
void _qspi_dma_register_callback(struct _qspi_dma_dev *dev, const enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_QSPI_DMA_H_INCLUDED */

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/**
* \file
*
* \brief Quad SPI Sync related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_QSPI_SYNC_H_INCLUDED
#define _HPL_QSPI_SYNC_H_INCLUDED
#include <hpl_qspi.h>
/**
* \addtogroup hpl_qspi HPL QSPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Quad SPI polling driver instance. */
struct _qspi_sync_dev {
/** Pointer to private data or hardware base */
void *prvt;
};
/**
* \brief Initialize QSPI for access without interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the QSPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_sync_init(struct _qspi_sync_dev *dev, void *const hw);
/**
* \brief Deinitialize QSPI
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the QSPI device instance.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_sync_deinit(struct _qspi_sync_dev *dev);
/**
* \brief Enable QSPI for access without interrupts
* \param[in, out] dev Pointer to the QSPI device instance.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_sync_enable(struct _qspi_sync_dev *dev);
/**
* \brief Disable QSPI for access without interrupts
* \param[in, out] dev Pointer to the QSPI device instance.
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_sync_disable(struct _qspi_sync_dev *dev);
/**
* \brief Execute command in Serial Memory Mode.
*
* \param[in] dev The pointer to QSPI device instance
* \param[in] cmd The pointer to the command information
* \return Operation status.
* \retval ERR_NONE Operation done successfully.
*/
int32_t _qspi_sync_serial_run_command(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_QSPI_SYNC_H_INCLUDED */

0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_ramecc.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_ramecc.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_reset.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_reset.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_sleep.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_sleep.h
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi.h
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_async.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_async.h
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_dma.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_dma.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_async.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_async.h
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0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_dma.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_dma.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_sync.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_m_sync.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_async.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_async.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_sync.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_s_sync.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_sync.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_spi_sync.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_async.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_async.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_sync.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/include/hpl_usart_sync.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_atomic.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_atomic.c
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_cache.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_cache.c
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_delay.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_delay.c
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_evsys.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_evsys.c
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_gpio.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_gpio.c
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_init.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_init.c
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_io.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_io.c
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Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_qspi_sync.c Normal file
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/**
* \file
*
* \brief Quad SPI related functionality implementation.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_qspi_sync.h"
#include <utils_assert.h>
#include <utils.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Driver version
*/
#define QSPI_SYNC_DRIVER_VERSION 0x00000001u
int32_t qspi_sync_init(struct qspi_sync_descriptor *qspi, void *const hw)
{
ASSERT(qspi && hw);
return _qspi_sync_init(&qspi->dev, hw);
}
int32_t qspi_sync_deinit(struct qspi_sync_descriptor *qspi)
{
ASSERT(qspi);
return _qspi_sync_deinit(&qspi->dev);
}
int32_t qspi_sync_enable(struct qspi_sync_descriptor *qspi)
{
ASSERT(qspi);
return _qspi_sync_enable(&qspi->dev);
}
int32_t qspi_sync_disable(struct qspi_sync_descriptor *qspi)
{
ASSERT(qspi);
return _qspi_sync_disable(&qspi->dev);
}
int32_t qspi_sync_serial_run_command(struct qspi_sync_descriptor *qspi, const struct _qspi_command *cmd)
{
ASSERT(qspi && cmd);
return _qspi_sync_serial_run_command(&qspi->dev, cmd);
}
uint32_t qspi_sync_get_version(void)
{
return QSPI_SYNC_DRIVER_VERSION;
}
#ifdef __cplusplus
}
#endif

0
Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_sleep.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_sleep.c
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_spi_m_dma.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_spi_m_dma.c
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_usart_sync.c → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/src/hal_usart_sync.c
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/compiler.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/compiler.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/err_codes.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/err_codes.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/events.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/events.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/parts.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/parts.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_assert.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_assert.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_event.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_event.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_increment_macro.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_increment_macro.h
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Examples/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_list.h → Examples/Buffer Transfer Example/Master_Slave_IF_Test_Master/Master_Slave_IF_TestMaster/hal/utils/include/utils_list.h
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