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fixed controller issues

This commit is contained in:
Nicolas Trimborn 2021-05-06 10:36:12 +02:00
parent 014164a82e
commit afde807033
31 changed files with 2976 additions and 112 deletions
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BLDC_E54/.vs/BLDC_E54/v14/.atsuo
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8
BLDC_E54/BLDC_E54/.atmelstart/atmel_start_config.atstart
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@ -894,7 +894,7 @@ drivers:
evsys_channel_41: No channel output selected
evsys_channel_42: No channel output selected
evsys_channel_43: No channel output selected
evsys_channel_44: No channel output selected
evsys_channel_44: Channel 1
evsys_channel_45: No channel output selected
evsys_channel_46: No channel output selected
evsys_channel_47: No channel output selected
@ -923,7 +923,7 @@ drivers:
evsys_channel_8: No channel output selected
evsys_channel_9: No channel output selected
evsys_channel_setting_0: true
evsys_channel_setting_1: false
evsys_channel_setting_1: true
evsys_channel_setting_10: false
evsys_channel_setting_11: false
evsys_channel_setting_12: false
@ -1051,7 +1051,7 @@ drivers:
evsys_evd_8: false
evsys_evd_9: false
evsys_evgen_0: TCC1 overflow
evsys_evgen_1: No event generator
evsys_evgen_1: CCL LUT output 0
evsys_evgen_10: No event generator
evsys_evgen_11: No event generator
evsys_evgen_12: No event generator
@ -1147,7 +1147,7 @@ drivers:
evsys_ovr_8: false
evsys_ovr_9: false
evsys_path_0: Asynchronous path
evsys_path_1: Synchronous path
evsys_path_1: Asynchronous path
evsys_path_10: Synchronous path
evsys_path_11: Synchronous path
evsys_path_12: Synchronous path

4
BLDC_E54/BLDC_E54/BLDC_E54.cproj
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@ -148,7 +148,7 @@
<AcmeProjectActionInfo Action="File" Source="hri/hri_usb_e54.h" IsConfig="false" Hash="I+Mpxa40hh4o1NE68Zi5Gg" />
<AcmeProjectActionInfo Action="File" Source="hri/hri_wdt_e54.h" IsConfig="false" Hash="CfZas1TGXPKWyHJU+xHJ7A" />
<AcmeProjectActionInfo Action="File" Source="main.c" IsConfig="false" Hash="k0AH7j+BrmdFhBPzCCMptA" />
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="mceoTydnA8kDgec50q1/vA" />
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="2PHBzCfeTG/AT1J8zlz6Cg" />
<AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="kvX4HyQhlWgUubWSbqV0nw" />
<AcmeProjectActionInfo Action="File" Source="atmel_start_pins.h" IsConfig="false" Hash="HgMCzaF/v9sYxwI7oBvlfw" />
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="TkkzzVyvo+cx7KsAp9l52Q" />
@ -205,7 +205,7 @@
<AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="Fgy1mDm2BRBY3IBfwL3mfg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="6xqR/FfKqve2wjz45CZHjA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="V00MuwusNA40W3fKunzS/A" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="B4UBkE0dQnjXdD5OC7x3WQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="XcRDNsb7d6ZuAa9h2WTYEw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />

8
BLDC_E54/BLDC_E54/Config/hpl_evsys_config.h
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@ -188,7 +188,7 @@
// <e> Channel 1 settings
// <id> evsys_channel_setting_1
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_1
#define CONF_EVSYS_CHANNEL_SETTINGS_1 0
#define CONF_EVSYS_CHANNEL_SETTINGS_1 1
#endif
// <y> Edge detection
@ -209,7 +209,7 @@
// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
// <id> evsys_path_1
#ifndef CONF_PATH_1
#define CONF_PATH_1 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
#define CONF_PATH_1 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
#endif
// <o> Event generator
@ -333,7 +333,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_1
#ifndef CONF_EVGEN_1
#define CONF_EVGEN_1 0
#define CONF_EVGEN_1 116
#endif
// <q> Overrun channel interrupt
@ -7464,7 +7464,7 @@
// <id> evsys_channel_44
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_44
#define CONF_CHANNEL_44 0
#define CONF_CHANNEL_44 2
#endif
// <o> Channel selection for TC1 event

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BLDC_E54/BLDC_E54/Config/hpl_tcc_config.h Normal file
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BLDC_E54/BLDC_E54/Debug/driver_init.o
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BLDC_E54/BLDC_E54/Debug/ethercat/ethercat_e54.o
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BLDC_E54/BLDC_E54/Debug/hpl/dmac/hpl_dmac.o
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BLDC_E54/BLDC_E54/Debug/hpl/evsys/hpl_evsys.o
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46
BLDC_E54/BLDC_E54/bldc.c
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@ -332,10 +332,10 @@ void exec_commutation(void)
// ----------------------------------------------------------------------
// Multi Motor Register Masking
// ----------------------------------------------------------------------
volatile uint16_t temp_M1 = COMMUTATION_PATTERN_M1[Motor1.motor_status.currentHallPattern];
volatile uint16_t temp_M2 = COMMUTATION_PATTERN_M2[Motor2.motor_status.currentHallPattern];
volatile uint16_t temp_M3_tcc1_des = COMMUTATION_PATTERN_M1[Motor3.motor_status.currentHallPattern] & m3_TCC1_mask;
volatile uint16_t temp_M3_tcc0_des = COMMUTATION_PATTERN_M2[Motor3.motor_status.currentHallPattern] & m3_TCC0_mask;
volatile uint16_t temp_M1 = COMMUTATION_PATTERN_M1[Motor1.motor_status.currentHallPattern + Motor1.motor_setpoints.directionOffset];
volatile uint16_t temp_M2 = COMMUTATION_PATTERN_M2[Motor2.motor_status.currentHallPattern + Motor2.motor_setpoints.directionOffset];
volatile uint16_t temp_M3_tcc1_des = COMMUTATION_PATTERN_M1[Motor3.motor_status.currentHallPattern + Motor3.motor_setpoints.directionOffset] & m3_TCC1_mask;
volatile uint16_t temp_M3_tcc0_des = COMMUTATION_PATTERN_M2[Motor3.motor_status.currentHallPattern + Motor3.motor_setpoints.directionOffset] & m3_TCC0_mask;
/* Zero target bits */
temp_M1 &= m3_TCC1_inv_mask;
temp_M2 &= m3_TCC0_inv_mask;
@ -353,7 +353,7 @@ void exec_commutation(void)
// Set Remaining GPIO lines responsible for M3 Commutation
// ----------------------------------------------------------------------
///* GPIO En Pin Setting for M3 */
switch(Motor3.motor_status.currentHallPattern)
switch(Motor3.motor_status.currentHallPattern + Motor3.motor_setpoints.directionOffset)
{
// REG_PORT_OUTSET0 = Port A
// REG_PORT_OUTSET1 = Port B
@ -383,32 +383,10 @@ void exec_commutation(void)
// Set Calculated Duty Cycles
// ----------------------------------------------------------------------
Motor1.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle);
Motor2.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle+1);
Motor3.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle+2);
//Motor2.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle);
//Motor3.SetDutyCycle((uint16_t)Motor1.motor_status.duty_cycle);
//TCC1->CCBUF->reg = (uint16_t)Motor1.motor_status.duty_cycle;
//hri_tcc_write_PATTBUF_reg(TCC1, (COMMUTATION_PATTERN[(Motor1.currentHallPattern + Motor1.directionOffset)]));
//hri_tcc_write_CCBUF_CCBUF_bf(TCC1, 0, 150);
//hri_tcc_write_CCBUF_CCBUF_bf(TCC1, 0, Motor1.duty_cycle);
//if ((Motor1.currentHallPattern != INVALID_HALL_0) && (Motor1.currentHallPattern != INVALID_HALL_7))
//{
// hri_tcc_write_PATTBUF_reg(TCC1, COMMUTATION_PATTERN[(Motor1.currentHallPattern + Motor1.directionOffset)]);
//} else {
//hall error
// return;
//}
//hri_tcc_write_CCBUF_reg(TCC1, 0, Motor1.duty_cycle);
/* Update the next pattern in the pattern array */
//Motor1.nextHallPattern = HALL_PATTERN_ARRAY[(Motor1.currentHallPattern+Motor1.directionOffset)];
//}
//volatile uint8_t curHallState = hallCode & 0x07; //ABC format
//volatile uint8_t curHallState = get_hall_state(); //ABC format
Motor1.motor_status.cur_comm_step = MOTOR_COMMUTATION_STEPS[Motor1.motor_status.currentHallPattern];
volatile int8_t step_change = Motor1.motor_status.cur_comm_step - Motor1.motor_status.prev_comm_step;
@ -418,13 +396,13 @@ void exec_commutation(void)
case -5:
Motor1.motor_status.Num_Steps = Motor1.motor_status.Num_Steps+1;
Motor1.motor_status.actualDirection = CW;
//Motor1.directionOffset = DIRECTION_CW_OFFSET;
Motor1.motor_setpoints.directionOffset = DIRECTION_CW_OFFSET;
break;
case -1:
case 5:
Motor1.motor_status.Num_Steps = Motor1.motor_status.Num_Steps-1;
Motor1.motor_status.actualDirection = CCW;
//Motor1.directionOffset = DIRECTION_CCW_OFFSET;
//Motor1.motor_setpoints.directionOffset = DIRECTION_CCW_OFFSET;
break;
default:
// do nothing
@ -520,7 +498,7 @@ void BLDC_runSpeedCntl(BLDCMotor_t *motor, volatile float speedfbk, volatile flo
{
motor->controllers.Pid_Speed.Fbk_pu = speedfbk;
motor->controllers.Pid_Speed.Ref_pu = f_clamp(speedRef, -MAX_VEL, MAX_VEL); // Convert Speed Ref to Q16 Format
motor->controllers.Pid_Speed.Ref_pu = f_clamp(speedRef, -MOTOR_MAX_SPD_RPM, MOTOR_MAX_SPD_RPM); // Convert Speed Ref to Q16 Format
if (applicationStatus.currentstate == MOTOR_V_CTRL_STATE)
{
@ -556,8 +534,8 @@ void BLDC_runSpeedCntl(BLDCMotor_t *motor, volatile float speedfbk, volatile flo
void BLDC_runPosCntl(BLDCMotor_t *motor, int16_t posfbk, int16_t posRef)
{
/* Output Pu in RPM */
motor->controllers.Pi_Pos.OutMax_pu = MAX_VEL;
motor->controllers.Pi_Pos.OutMin_pu = -MAX_VEL;
motor->controllers.Pi_Pos.OutMax_pu = MOTOR_MAX_SPD_RPM;
motor->controllers.Pi_Pos.OutMin_pu = -MOTOR_MAX_SPD_RPM;
motor->controllers.Pi_Pos.Fbk_pu = posfbk;
motor->controllers.Pi_Pos.Ref_pu = posRef;
PI_run_series(&motor->controllers.Pi_Pos);

5
BLDC_E54/BLDC_E54/bldc.h
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@ -153,9 +153,8 @@ volatile BLDCMotor_t Motor2;
volatile BLDCMotor_t Motor3;
static uint8_t currentSensorCount = 4;
static uint32_t adc_seq_regs[4] = {0x1802, 0x1803, 0x1802, 0x1803};
static volatile uint16_t adc_res[4] = {0};
static uint32_t adc_seq_regs[6] = {0x1802, 0x1803, 0x1802, 0x1803, 0x1802, 0x1803};
static volatile uint16_t adc_res[6] = {0};
static volatile bool adc_dma_done = 0;
struct _dma_resource *adc_sram_dma_resource;

53
BLDC_E54/BLDC_E54/configuration.h
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@ -20,24 +20,24 @@
#define DMAC_CHANNEL_ADC_SRAM 3U
void dummy2 (void){
while(1);
}
void dummy3 (void){
while(1);
}
void dummy4 (void){
while(1);
}
void dummy5 (void){
while(1);
}
void dummy6 (void){
while(1);
}
//void dummy2 (void){
//while(1);
//}
//
//void dummy3 (void){
//while(1);
//}
//
//void dummy4 (void){
//while(1);
//}
//void dummy5 (void){
//while(1);
//}
//
//void dummy6 (void){
//while(1);
//}
inline void configure_tcc_pwm(void)
{
@ -129,13 +129,13 @@ inline void adc_dmac_sequence_init()
* next descriptor address, data count and Enable the DMAC Channel */
_dma_set_source_address(DMAC_CHANNEL_ADC_SEQ, (const void *)adc_seq_regs);
_dma_set_destination_address(DMAC_CHANNEL_ADC_SEQ, (const void *)&ADC0->DSEQDATA.reg);
_dma_set_data_amount(DMAC_CHANNEL_ADC_SEQ, 4);
_dma_set_data_amount(DMAC_CHANNEL_ADC_SEQ, 6);
_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SEQ, DMAC_CHANNEL_ADC_SEQ);
_dma_enable_transaction(DMAC_CHANNEL_ADC_SEQ, false);
_dma_get_channel_resource(&adc_dmac_sequence_resource, DMAC_CHANNEL_ADC_SEQ);
adc_dmac_sequence_resource[0].dma_cb.error = dummy2;
adc_dmac_sequence_resource[0].dma_cb.suspend = dummy3;
adc_dmac_sequence_resource[0].dma_cb.transfer_done = dummy4;
//_dma_get_channel_resource(&adc_dmac_sequence_resource, DMAC_CHANNEL_ADC_SEQ);
//adc_dmac_sequence_resource[0].dma_cb.error = dummy2;
//adc_dmac_sequence_resource[0].dma_cb.suspend = dummy3;
//adc_dmac_sequence_resource[0].dma_cb.transfer_done = dummy4;
hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[2], 0x01); //Suspend
@ -147,13 +147,12 @@ inline void adc_sram_dmac_init()
* next descriptor address, data count and Enable the DMAC Channel */
_dma_set_source_address(DMAC_CHANNEL_ADC_SRAM, (const void *)&ADC0->RESULT.reg);
_dma_set_destination_address(DMAC_CHANNEL_ADC_SRAM, (const void *)adc_res);
_dma_set_data_amount(DMAC_CHANNEL_ADC_SRAM, 4);
_dma_set_data_amount(DMAC_CHANNEL_ADC_SRAM, 6);
_dma_set_irq_state(DMAC_CHANNEL_ADC_SRAM, DMA_TRANSFER_COMPLETE_CB, true);
_dma_get_channel_resource(&adc_sram_dma_resource, DMAC_CHANNEL_ADC_SRAM);
adc_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback;
adc_sram_dma_resource[0].dma_cb.error = dummy6;
adc_sram_dma_resource[0].dma_cb.suspend = dummy5;
//adc_sram_dma_resource[0].dma_cb.error = dummy6;
//adc_sram_dma_resource[0].dma_cb.suspend = dummy5;
_dma_set_next_descriptor(DMAC_CHANNEL_ADC_SRAM, DMAC_CHANNEL_ADC_SRAM);
_dma_enable_transaction(DMAC_CHANNEL_ADC_SRAM, false);
}

1
BLDC_E54/BLDC_E54/driver_init.c
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@ -97,6 +97,7 @@ void EXTERNAL_IRQ_0_init(void)
void EVENT_SYSTEM_0_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_1, CONF_GCLK_EVSYS_CHANNEL_1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);

4
BLDC_E54/BLDC_E54/ethercat/ethercat_e54.c
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@ -43,8 +43,8 @@ void update_telemetry(void)
*motor_currentPHC = convert_to_mA(Motor1.Iphase_pu.C);
*motor_currentBUS = convert_to_mA(Motor1.Iphase_pu.Bus);
*hall_state = Motor1.motor_status.currentHallPattern;
*Spare_byte1 = Motor1.motor_status.actualDirection;
//*Spare_1 = 0;
*Spare_byte1 = Motor1.motor_setpoints.directionOffset;
*Spare_1 = Motor1.motor_status.actualDirection;
//*Spare_2 = 0;
}

4
BLDC_E54/BLDC_E54/ethercat/ethercat_slave_def.h
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@ -14,7 +14,7 @@
//Write To Ecat Total Bytes (38 bytes)
//write (2 Bytes)
static volatile uint8_t *status =&ram_buffer[ram_wr_start];
static volatile uint8_t *state =(((uint8_t *)&ram_buffer[ram_wr_start])+1);
static volatile uint8_t *state =(((uint8_t *)&ram_buffer[ram_wr_start])+1);
//Joint (10 Bytes)
static volatile int16_t *joint_rel_position =&ram_buffer[ram_wr_start+1];
static volatile int16_t *joint_revolution =&ram_buffer[ram_wr_start+2];
@ -44,7 +44,7 @@ static volatile uint8_t *control_set =(((uint8_t *)&ram_buffer[ram_rd_start])+
// (34 Byte)
static volatile int16_t *desired_position =&ram_buffer[ram_rd_start+1];
static volatile int16_t *desired_speed =&ram_buffer[ram_rd_start+2];
static volatile int16_t *desired_torque =&ram_buffer[ram_rd_start+3];
static volatile int16_t *desired_torque =&ram_buffer[ram_rd_start+3];
static volatile int16_t *i_kp =&ram_buffer[ram_rd_start+4];
static volatile int16_t *i_ki =&ram_buffer[ram_rd_start+5];
static volatile int16_t *v_kp =&ram_buffer[ram_rd_start+6];

74
BLDC_E54/BLDC_E54/hal/documentation/adc_sync.rst Normal file
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@ -0,0 +1,74 @@
======================
ADC Synchronous driver
======================
An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
A reference signal with a known voltage level is quantified into equally
sized chunks, each representing a digital value from 0 to the highest number
possible with the bit resolution supported by the ADC. The input voltage
measured by the ADC is compared against these chunks and the chunk with the
closest voltage level defines the digital value that can be used to represent
the analog input voltage level.
Usually an ADC can operate in either differential or single-ended mode.
In differential mode two signals (V+ and V-) are compared against each other
and the resulting digital value represents the relative voltage level between
V+ and V-. This means that if the input voltage level on V+ is lower than on
V- the digital value is negative, which also means that in differential
mode one bit is lost to the sign. In single-ended mode only V+ is compared
against the reference voltage, and the resulting digital value can only be
positive, but the full bit-range of the ADC can be used.
Usually multiple resolutions are supported by the ADC, lower resolution can
reduce the conversion time, but lose accuracy.
Some ADCs has a gain stage on the input lines which can be used to increase the
dynamic range. The default gain value is usually x1, which means that the
conversion range is from 0V to the reference voltage.
Applications can change the gain stage, to increase or reduce the conversion
range.
The window mode allows the conversion result to be compared to a set of
predefined threshold values. Applications can use callback function to monitor
if the conversion result exceeds predefined threshold value.
Usually multiple reference voltages are supported by the ADC, both internal and
external with difference voltage levels. The reference voltage have an impact
on the accuracy, and should be selected to cover the full range of the analog
input signal and never less than the expected maximum input voltage.
There are two conversion modes supported by ADC, single shot and free running.
In single shot mode the ADC only make one conversion when triggered by the
application, in free running mode it continues to make conversion from it
is triggered until it is stopped by the application. When window monitoring,
the ADC should be set to free running mode.
Features
--------
* Initialization and de-initialization
* Support multiple Conversion Mode, Single or Free run
* Start ADC Conversion
* Read Conversion Result
Applications
------------
* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
* Measurement of external sensor. E.g., Temperature, humidity sensor value.
* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
Dependencies
------------
* ADC hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A

53
BLDC_E54/BLDC_E54/hal/documentation/pwm.rst Normal file
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@ -0,0 +1,53 @@
The PWM Driver(bare-bone)
=========================
Pulse-width modulation (PWM) is used to create an analog behavior
digitally by controlling the amount of power transferred to the
connected peripheral. This is achieved by controlling the high period
(duty-cycle) of a periodic signal.
User can change the period or duty cycle whenever PWM is running. The
function pwm_set_parameters is used to configure these two parameters.
Note these are raw register values and the parameter duty_cycle means
the period of first half during one cycle, which should be not beyond
total period value.
In addition, user can also get multi PWM channels output from different
peripherals at the same time, which is implemented more flexible by the
function pointers.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Run-time control of PWM duty-cycle and period
* Notifications about errors and one PWM cycle is done
Applications
------------
Motor control, ballast, LED, H-bridge, power converters, and
other types of power control applications.
Dependencies
------------
The peripheral which can perform waveform generation like frequency
generation and pulse-width modulation, such as Timer/Counter.
Concurrency
-----------
N/A
Limitations
-----------
The current driver doesn't support the features like recoverable,
non-recoverable faults, dithering, dead-time insertion.
Known issues and workarounds
----------------------------
N/A

277
BLDC_E54/BLDC_E54/hal/include/hal_adc_sync.h Normal file
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@ -0,0 +1,277 @@
/**
* \file
*
* \brief ADC functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ADC_SYNC_H_INCLUDED
#define _HAL_ADC_SYNC_H_INCLUDED
#include <hpl_adc_sync.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_adc_sync
*
* @{
*/
/**
* \brief ADC descriptor
*
* The ADC descriptor forward declaration.
*/
struct adc_sync_descriptor;
/**
* \brief ADC descriptor
*/
struct adc_sync_descriptor {
/** ADC device */
struct _adc_sync_device device;
};
/**
* \brief Initialize ADC
*
* This function initializes the given ADC descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr An ADC descriptor to initialize
* \param[in] hw The pointer to hardware instance
* \param[in] func The pointer to a set of functions pointers
*
* \return Initialization status.
*/
int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func);
/**
* \brief Deinitialize ADC
*
* This function deinitializes the given ADC descriptor.
* It checks if the given hardware is initialized and if the given hardware is
* permitted to be deinitialized.
*
* \param[in] descr An ADC descriptor to deinitialize
*
* \return De-initialization status.
*/
int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr);
/**
* \brief Enable ADC
*
* Use this function to set the ADC peripheral to enabled state.
*
* \param[in] descr Pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return Operation status
*
*/
int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Disable ADC
*
* Use this function to set the ADC peripheral to disabled state.
*
* \param[in] descr Pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return Operation status
*
*/
int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Read data from ADC
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] buf A buffer to read data to
* \param[in] length The size of a buffer
*
* \return The number of bytes read.
*/
int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
const uint16_t length);
/**
* \brief Set ADC reference source
*
* This function sets ADC reference source.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] reference A reference source to set
*
* \return Status of the ADC reference source setting.
*/
int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference);
/**
* \brief Set ADC resolution
*
* This function sets ADC resolution.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] resolution A resolution to set
*
* \return Status of the ADC resolution setting.
*/
int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* This function sets ADC positive and negative input sources.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*
* \return Status of the ADC channels setting.
*/
int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set ADC conversion mode
*
* This function sets ADC conversion mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] mode A conversion mode to set
*
* \return Status of the ADC conversion mode setting.
*/
int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode);
/**
* \brief Set ADC differential mode
*
* This function sets ADC differential mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*
* \return Status of the ADC differential mode setting.
*/
int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set ADC channel gain
*
* This function sets ADC channel gain.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] gain A gain to set
*
* \return Status of the ADC gain setting.
*/
int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel,
const adc_gain_t gain);
/**
* \brief Set ADC window mode
*
* This function sets ADC window mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] mode A window mode to set
*
* \return Status of the ADC window mode setting.
*/
int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode);
/**
* \brief Set ADC thresholds
*
* This function sets ADC positive and negative thresholds.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] low_threshold A lower thresholds to set
* \param[in] up_threshold An upper thresholds to set
*
* \return Status of the ADC thresholds setting.
*/
int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* This function retrieves ADC threshold state.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[out] state The threshold state
*
* \return The state of ADC thresholds state retrieving.
*/
int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr,
adc_threshold_status_t *const state);
/**
* \brief Check if conversion is complete
*
* This function checks if the ADC has finished the conversion.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return The status of ADC conversion completion checking.
* \retval 1 The conversion is complete
* \retval 0 The conversion is not complete
*/
int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t adc_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#include <hpl_missing_features.h>
#endif /* _HAL_ADC_SYNC_H_INCLUDED */

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/**
* \file
*
* \brief PWM functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef HAL_PWM_H_INCLUDED
#define HAL_PWM_H_INCLUDED
#include <hpl_pwm.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_pwm_async
*
*@{
*/
/**
* \brief PWM descriptor
*
* The PWM descriptor forward declaration.
*/
struct pwm_descriptor;
/**
* \brief PWM callback type
*/
typedef void (*pwm_cb_t)(const struct pwm_descriptor *const descr);
/**
* \brief PWM callback types
*/
enum pwm_callback_type { PWM_PERIOD_CB, PWM_ERROR_CB };
/**
* \brief PWM callbacks
*/
struct pwm_callbacks {
pwm_cb_t period;
pwm_cb_t error;
};
/** \brief PWM descriptor
*/
struct pwm_descriptor {
/** PWM device */
struct _pwm_device device;
/** PWM callback structure */
struct pwm_callbacks pwm_cb;
};
/** \brief Initialize the PWM HAL instance and hardware
*
* \param[in] descr Pointer to the HAL PWM descriptor
* \param[in] hw The pointer to hardware instance
* \param[in] func The pointer to a set of functions pointers
*
* \return Operation status.
*/
int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func);
/** \brief Deinitialize the PWM HAL instance and hardware
*
* \param[in] descr Pointer to the HAL PWM descriptor
*
* \return Operation status.
*/
int32_t pwm_deinit(struct pwm_descriptor *const descr);
/** \brief PWM output start
*
* \param[in] descr Pointer to the HAL PWM descriptor
*
* \return Operation status.
*/
int32_t pwm_enable(struct pwm_descriptor *const descr);
/** \brief PWM output stop
*
* \param[in] descr Pointer to the HAL PWM descriptor
*
* \return Operation status.
*/
int32_t pwm_disable(struct pwm_descriptor *const descr);
/** \brief Register PWM callback
*
* \param[in] descr Pointer to the HAL PWM descriptor
* \param[in] type Callback type
* \param[in] cb A callback function, passing NULL de-registers callback
*
* \return Operation status.
* \retval 0 Success
* \retval -1 Error
*/
int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb);
/** \brief Change PWM parameter
*
* \param[in] descr Pointer to the HAL PWM descriptor
* \param[in] period Total period of one PWM cycle
* \param[in] duty_cycle Period of PWM first half during one cycle
*
* \return Operation status.
*/
int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period,
const pwm_period_t duty_cycle);
/** \brief Get PWM driver version
*
* \return Current driver version.
*/
uint32_t pwm_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* HAL_PWM;_H_INCLUDED */

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/**
* \file
*
* \brief PWM related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_PWM_H_INCLUDED
#define _HPL_PWM_H_INCLUDED
/**
* \addtogroup HPL PWM
*
* \section hpl_pwm_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief PWM callback types
*/
enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB };
/**
* \brief PWM pulse-width period
*/
typedef uint32_t pwm_period_t;
/**
* \brief PWM device structure
*
* The PWM device structure forward declaration.
*/
struct _pwm_device;
/**
* \brief PWM interrupt callbacks
*/
struct _pwm_callback {
void (*pwm_period_cb)(struct _pwm_device *device);
void (*pwm_error_cb)(struct _pwm_device *device);
};
/**
* \brief PWM descriptor device structure
*/
struct _pwm_device {
struct _pwm_callback callback;
struct _irq_descriptor irq;
void * hw;
};
/**
* \brief PWM functions, pointers to low-level functions
*/
struct _pwm_hpl_interface {
int32_t (*init)(struct _pwm_device *const device, void *const hw);
void (*deinit)(struct _pwm_device *const device);
void (*start_pwm)(struct _pwm_device *const device);
void (*stop_pwm)(struct _pwm_device *const device);
void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
bool (*is_pwm_enabled)(const struct _pwm_device *const device);
pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device);
uint32_t (*pwm_get_duty)(const struct _pwm_device *const device);
void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
};
/**
* \brief Initialize TC
*
* This function does low level TC configuration.
*
* \param[in] device The pointer to PWM device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
*/
int32_t _pwm_init(struct _pwm_device *const device, void *const hw);
/**
* \brief Deinitialize TC
*
* \param[in] device The pointer to PWM device instance
*/
void _pwm_deinit(struct _pwm_device *const device);
/**
* \brief Retrieve offset of the given tc hardware instance
*
* \param[in] device The pointer to PWM device instance
*
* \return The offset of the given tc hardware instance
*/
uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device);
/**
* \brief Start hardware pwm
*
* \param[in] device The pointer to PWM device instance
*/
void _pwm_enable(struct _pwm_device *const device);
/**
* \brief Stop hardware pwm
*
* \param[in] device The pointer to PWM device instance
*/
void _pwm_disable(struct _pwm_device *const device);
/**
* \brief Set pwm parameter
*
* \param[in] device The pointer to PWM device instance
* \param[in] period Total period of one PWM cycle.
* \param[in] duty_cycle Period of PWM first half during one cycle.
*/
void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
/**
* \brief Check if pwm is working
*
* \param[in] device The pointer to PWM device instance
*
* \return Check status.
* \retval true The given pwm is working
* \retval false The given pwm is not working
*/
bool _pwm_is_enabled(const struct _pwm_device *const device);
/**
* \brief Get pwm waveform period value
*
* \param[in] device The pointer to PWM device instance
*
* \return Period value.
*/
pwm_period_t _pwm_get_period(const struct _pwm_device *const device);
/**
* \brief Get pwm waveform duty cycle value
*
* \param[in] device The pointer to PWM device instance
*
* \return Duty cycle value
*/
uint32_t _pwm_get_duty(const struct _pwm_device *const device);
/**
* \brief Enable/disable PWM interrupt
*
* param[in] device The pointer to PWM device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] disable Enable or disable
*/
void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_PWM_H_INCLUDED */

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/**
* \file
*
* \brief Timer related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_TIMER_H_INCLUDED
#define _HPL_TIMER_H_INCLUDED
/**
* \addtogroup HPL Timer
*
* \section hpl_timer_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Timer device structure
*
* The Timer device structure forward declaration.
*/
struct _timer_device;
/**
* \brief Timer interrupt callbacks
*/
struct _timer_callbacks {
void (*period_expired)(struct _timer_device *device);
};
/**
* \brief Timer device structure
*/
struct _timer_device {
struct _timer_callbacks timer_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \brief Timer functions, pointers to low-level functions
*/
struct _timer_hpl_interface {
int32_t (*init)(struct _timer_device *const device, void *const hw);
void (*deinit)(struct _timer_device *const device);
void (*start_timer)(struct _timer_device *const device);
void (*stop_timer)(struct _timer_device *const device);
void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles);
uint32_t (*get_period)(const struct _timer_device *const device);
bool (*is_timer_started)(const struct _timer_device *const device);
void (*set_timer_irq)(struct _timer_device *const device);
};
/**
* \brief Initialize TCC
*
* This function does low level TCC configuration.
*
* \param[in] device The pointer to timer device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
*/
int32_t _timer_init(struct _timer_device *const device, void *const hw);
/**
* \brief Deinitialize TCC
*
* \param[in] device The pointer to timer device instance
*/
void _timer_deinit(struct _timer_device *const device);
/**
* \brief Start hardware timer
*
* \param[in] device The pointer to timer device instance
*/
void _timer_start(struct _timer_device *const device);
/**
* \brief Stop hardware timer
*
* \param[in] device The pointer to timer device instance
*/
void _timer_stop(struct _timer_device *const device);
/**
* \brief Set timer period
*
* \param[in] device The pointer to timer device instance
*/
void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles);
/**
* \brief Retrieve timer period
*
* \param[in] device The pointer to timer device instance
*
* \return Timer period
*/
uint32_t _timer_get_period(const struct _timer_device *const device);
/**
* \brief Check if timer is running
*
* \param[in] device The pointer to timer device instance
*
* \return Check status.
* \retval true The given timer is running
* \retval false The given timer is not running
*/
bool _timer_is_started(const struct _timer_device *const device);
/**
* \brief Set timer IRQ
*
* \param[in] device The pointer to timer device instance
*/
void _timer_set_irq(struct _timer_device *const device);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_TIMER_H_INCLUDED */

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/**
* \file
*
* \brief ADC functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/**
* \brief Indicates HAL being compiled. Must be defined before including.
*/
#define _COMPILING_HAL
#include "hal_adc_sync.h"
#include <utils_assert.h>
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief Maximum amount of ADC interface instances
*/
#define MAX_ADC_AMOUNT ADC_INST_NUM
/**
* \brief Initialize ADC
*/
int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func)
{
ASSERT(descr && hw);
return _adc_sync_init(&descr->device, hw);
}
/**
* \brief Deinitialize ADC
*/
int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr)
{
ASSERT(descr);
_adc_sync_deinit(&descr->device);
return ERR_NONE;
}
/**
* \brief Enable ADC
*/
int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
{
ASSERT(descr);
_adc_sync_enable_channel(&descr->device, channel);
return ERR_NONE;
}
/**
* \brief Disable ADC
*/
int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
{
ASSERT(descr);
_adc_sync_disable_channel(&descr->device, channel);
return ERR_NONE;
}
/*
* \brief Read data from ADC
*/
int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
const uint16_t length)
{
uint8_t data_size;
uint16_t offset = 0;
ASSERT(descr && buffer && length);
data_size = _adc_sync_get_data_size(&descr->device);
ASSERT(!(length % data_size));
do {
uint16_t result;
_adc_sync_convert(&descr->device);
while (!_adc_sync_is_channel_conversion_done(&descr->device, channel))
;
result = _adc_sync_read_channel_data(&descr->device, channel);
buffer[offset] = result;
if (1 < data_size) {
buffer[offset + 1] = result >> 8;
}
offset += data_size;
} while (offset < length);
return offset;
}
/**
* \brief Set ADC reference source
*/
int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference)
{
ASSERT(descr);
_adc_sync_set_reference_source(&descr->device, reference);
return ERR_NONE;
}
/**
* \brief Set ADC resolution
*/
int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution)
{
ASSERT(descr);
_adc_sync_set_resolution(&descr->device, resolution);
return ERR_NONE;
}
/**
* \brief Set ADC input source of a channel
*/
int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel)
{
ASSERT(descr);
_adc_sync_set_inputs(&descr->device, pos_input, neg_input, channel);
return ERR_NONE;
}
/**
* \brief Set ADC thresholds
*/
int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold)
{
ASSERT(descr);
_adc_sync_set_thresholds(&descr->device, low_threshold, up_threshold);
return ERR_NONE;
}
/**
* \brief Set ADC gain
*/
int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, const adc_gain_t gain)
{
ASSERT(descr);
_adc_sync_set_channel_gain(&descr->device, channel, gain);
return ERR_NONE;
}
/**
* \brief Set ADC conversion mode
*/
int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode)
{
ASSERT(descr);
_adc_sync_set_conversion_mode(&descr->device, mode);
return ERR_NONE;
}
/**
* \brief Set ADC differential mode
*/
int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
const enum adc_differential_mode mode)
{
ASSERT(descr);
_adc_sync_set_channel_differential_mode(&descr->device, channel, mode);
return ERR_NONE;
}
/**
* \brief Set ADC window mode
*/
int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode)
{
ASSERT(descr);
_adc_sync_set_window_mode(&descr->device, mode);
return ERR_NONE;
}
/**
* \brief Retrieve threshold state
*/
int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, adc_threshold_status_t *const state)
{
ASSERT(descr && state);
_adc_sync_get_threshold_state(&descr->device, state);
return ERR_NONE;
}
/**
* \brief Check if conversion is complete
*/
int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel)
{
ASSERT(descr);
return _adc_sync_is_channel_conversion_done(&descr->device, channel);
}
/**
* \brief Retrieve the current driver version
*/
uint32_t adc_sync_get_version(void)
{
return DRIVER_VERSION;
}
//@}

159
BLDC_E54/BLDC_E54/hal/src/hal_pwm.c Normal file
View File

@ -0,0 +1,159 @@
/**
* \file
*
* \brief PWM functionality implementation.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_pwm.h"
#include <utils_assert.h>
#include <utils.h>
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
static void pwm_period_expired(struct _pwm_device *device);
static void pwm_detect_fault(struct _pwm_device *device);
/**
* \brief Initialize pwm
*/
int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func)
{
ASSERT(descr && hw);
_pwm_init(&descr->device, hw);
descr->device.callback.pwm_period_cb = pwm_period_expired;
descr->device.callback.pwm_error_cb = pwm_detect_fault;
return ERR_NONE;
}
/**
* \brief Deinitialize pwm
*/
int32_t pwm_deinit(struct pwm_descriptor *const descr)
{
ASSERT(descr);
_pwm_deinit(&descr->device);
return ERR_NONE;
}
/**
* \brief Start pwm
*/
int32_t pwm_enable(struct pwm_descriptor *const descr)
{
ASSERT(descr);
if (_pwm_is_enabled(&descr->device)) {
return ERR_DENIED;
}
_pwm_enable(&descr->device);
return ERR_NONE;
}
/**
* \brief Stop pwm
*/
int32_t pwm_disable(struct pwm_descriptor *const descr)
{
ASSERT(descr);
if (!_pwm_is_enabled(&descr->device)) {
return ERR_DENIED;
}
_pwm_disable(&descr->device);
return ERR_NONE;
}
/**
* \brief Register PWM callback
*/
int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb)
{
switch (type) {
case PWM_PERIOD_CB:
descr->pwm_cb.period = cb;
break;
case PWM_ERROR_CB:
descr->pwm_cb.error = cb;
break;
default:
return ERR_INVALID_ARG;
}
ASSERT(descr);
_pwm_set_irq_state(&descr->device, (enum _pwm_callback_type)type, NULL != cb);
return ERR_NONE;
}
/**
* \brief Change PWM parameter
*/
int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, const pwm_period_t duty_cycle)
{
ASSERT(descr);
_pwm_set_param(&descr->device, period, duty_cycle);
return ERR_NONE;
}
/**
* \brief Retrieve the current driver version
*/
uint32_t pwm_get_version(void)
{
return DRIVER_VERSION;
}
/**
* \internal Process interrupts caused by period experied
*/
static void pwm_period_expired(struct _pwm_device *device)
{
struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);
if (descr->pwm_cb.period) {
descr->pwm_cb.period(descr);
}
}
/**
* \internal Process interrupts caused by pwm fault
*/
static void pwm_detect_fault(struct _pwm_device *device)
{
struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);
if (descr->pwm_cb.error) {
descr->pwm_cb.error(descr);
}
}

10
BLDC_E54/BLDC_E54/hpl/dmac/hpl_dmac.c
View File

@ -220,7 +220,7 @@ int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable)
/**
* \internal DMAC interrupt handler
*/
static void _dmac_handler(uint8_t channel)
static void _dmac_handler(uint8_t channel) // Added Channel
{
//uint8_t channel = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk);
struct _dma_resource *tmp_resource = &_resources[channel];
@ -231,12 +231,8 @@ static void _dmac_handler(uint8_t channel)
} else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)|hri_dmac_get_CHINTEN_TCMPL_bit(DMAC,channel)) {
hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel);
tmp_resource->dma_cb.transfer_done(tmp_resource);
} else if (hri_dmac_get_INTPEND_SUSP_bit(DMAC)|hri_dmac_get_CHINTEN_SUSP_bit(DMAC,channel)) {
hri_dmac_clear_CHINTFLAG_SUSP_bit(DMAC, channel);
if(channel == 3)
{
volatile int i = 0;
}
} else if (hri_dmac_get_INTPEND_SUSP_bit(DMAC)|hri_dmac_get_CHINTEN_SUSP_bit(DMAC,channel)) { //added
hri_dmac_clear_CHINTFLAG_SUSP_bit(DMAC, channel); //added
tmp_resource->dma_cb.suspend(tmp_resource);
}

394
BLDC_E54/BLDC_E54/hpl/tcc/hpl_tcc.c Normal file
View File

@ -0,0 +1,394 @@
/**
* \file
*
* \brief SAM TCC
*
* Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <compiler.h>
#include <hpl_pwm.h>
#include <hpl_tcc.h>
#include <hpl_tcc_config.h>
#include <hpl_timer.h>
#include <utils.h>
#include <utils_assert.h>
/**
* \brief TCC configuration type
*/
struct tcc_cfg {
void * hw; /*!< instance of TCC */
IRQn_Type irq;
hri_tcc_ctrla_reg_t ctrl_a;
hri_tcc_ctrlbset_reg_t ctrl_b;
hri_tcc_dbgctrl_reg_t dbg_ctrl;
hri_tcc_evctrl_reg_t event_ctrl;
hri_tcc_cc_reg_t cc0;
hri_tcc_cc_reg_t cc1;
hri_tcc_cc_reg_t cc2;
hri_tcc_cc_reg_t cc3;
hri_tcc_cc_reg_t cc4;
hri_tcc_cc_reg_t cc5;
hri_tcc_per_reg_t per;
};
/**
* \brief pwm configuration type
*/
struct tcc_pwm_cfg {
void * hw; /*!< instance of TCC */
IRQn_Type irq;
uint8_t sel_ch;
uint32_t period;
uint32_t duty_cycle;
uint32_t wave;
};
/**
* \internal Retrieve configuration
*
* \param[in] hw The pointer of TCC base address
*
* \return The configuration
*/
static struct tcc_cfg *_get_tcc_cfg(void *hw);
/**
* \brief Array of TCC configurations
*/
static struct tcc_cfg _cfgs[2] = {
{(void *)TCC0,
TCC0_0_IRQn,
CONF_TCC0_CTRLA,
CONF_TCC0_CTRLB,
CONF_TCC0_DBGCTRL,
CONF_TCC0_EVCTRL,
CONF_TCC0_CC0,
CONF_TCC0_CC1,
CONF_TCC0_CC2,
CONF_TCC0_CC3,
CONF_TCC0_CC4,
CONF_TCC0_CC5,
CONF_TCC0_PER},
{(void *)TCC1,
TCC1_0_IRQn,
CONF_TCC1_CTRLA,
CONF_TCC1_CTRLB,
CONF_TCC1_DBGCTRL,
CONF_TCC1_EVCTRL,
CONF_TCC1_CC0,
CONF_TCC1_CC1,
CONF_TCC1_CC2,
CONF_TCC1_CC3,
0,
0,
CONF_TCC1_PER},
};
/**
* \internal Retrieve configuration
*
* \param[in] hw The pointer of TCC base address
*
* \return The configuration
*/
static struct tcc_pwm_cfg *_get_tcc_pwm_cfg(void *hw);
/**
* \brief Array of PWM configurations
*/
static struct tcc_pwm_cfg _cfgs_pwm[2] = {
{(void *)TCC0,
TCC0_0_IRQn,
CONF_TCC0_SEL_CH,
CONF_TCC0_PER_REG,
CONF_TCC0_CCX_REG,
(CONF_TCC0_WAVEGEN << TCC_WAVE_WAVEGEN_Pos)},
{(void *)TCC1,
TCC1_0_IRQn,
CONF_TCC1_SEL_CH,
CONF_TCC1_PER_REG,
CONF_TCC1_CCX_REG,
(CONF_TCC1_WAVEGEN << TCC_WAVE_WAVEGEN_Pos)},
};
/* Renamed access REG name PERB -> PERBUF */
#define hri_tcc_write_PERB_reg hri_tcc_write_PERBUF_reg
#define hri_tcc_read_PERB_reg hri_tcc_read_PERBUF_reg
/** Renamed access REG name CCB -> CCBUF */
#define hri_tcc_write_CCB_reg hri_tcc_write_CCBUF_reg
#define hri_tcc_read_CCB_reg hri_tcc_read_CCBUF_reg
static struct _pwm_device *_tcc0_dev = NULL;
static struct _pwm_device *_tcc1_dev = NULL;
/**
* \brief Init irq param with the given tcc hardware instance
*/
static void _tcc_init_irq_param(const void *const hw, void *dev)
{
if (hw == TCC0) {
_tcc0_dev = (struct _pwm_device *)dev;
}
if (hw == TCC1) {
_tcc1_dev = (struct _pwm_device *)dev;
}
}
/**
* \brief Initialize TCC for PWM mode
*/
int32_t _pwm_init(struct _pwm_device *const device, void *const hw)
{
struct tcc_cfg *cfg = _get_tcc_cfg(hw);
if (cfg == NULL) {
return ERR_NOT_FOUND;
}
struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
if (cfg_pwm == NULL) {
return ERR_NOT_FOUND;
}
device->hw = hw;
if (!hri_tcc_is_syncing(hw, TCC_SYNCBUSY_SWRST)) {
if (hri_tcc_get_CTRLA_reg(hw, TCC_CTRLA_ENABLE)) {
hri_tcc_clear_CTRLA_ENABLE_bit(hw);
hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_ENABLE);
}
hri_tcc_write_CTRLA_reg(hw, TCC_CTRLA_SWRST);
}
hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
hri_tcc_write_CTRLA_reg(hw, cfg->ctrl_a);
hri_tcc_set_CTRLB_reg(hw, cfg->ctrl_b);
hri_tcc_write_DBGCTRL_reg(hw, cfg->dbg_ctrl);
hri_tcc_write_EVCTRL_reg(hw, cfg->event_ctrl);
hri_tcc_write_WAVE_reg(hw, cfg_pwm->wave);
hri_tcc_write_PER_reg(hw, cfg_pwm->period);
cfg->per = cfg_pwm->period;
switch (cfg_pwm->sel_ch) {
case 0:
cfg->cc0 = cfg_pwm->duty_cycle;
hri_tcc_write_CC_reg(hw, 0, cfg->cc0);
break;
case 1:
cfg->cc1 = cfg_pwm->duty_cycle;
hri_tcc_write_CC_reg(hw, 1, cfg->cc1);
break;
case 2:
cfg->cc2 = cfg_pwm->duty_cycle;
hri_tcc_write_CC_reg(hw, 2, cfg->cc2);
break;
case 3:
cfg->cc3 = cfg_pwm->duty_cycle;
hri_tcc_write_CC_reg(hw, 3, cfg->cc3);
break;
case 4:
cfg->cc4 = cfg_pwm->duty_cycle;
hri_tcc_write_CC_reg(hw, 4, cfg->cc4);
break;
case 5:
cfg->cc5 = cfg_pwm->duty_cycle;
hri_tcc_write_CC_reg(hw, 5, cfg->cc5);
break;
default:
return ERR_NO_RESOURCE;
break;
}
hri_tcc_clear_CTRLB_LUPD_bit(hw);
_tcc_init_irq_param(hw, (void *)device);
NVIC_DisableIRQ((IRQn_Type)cfg_pwm->irq);
NVIC_ClearPendingIRQ((IRQn_Type)cfg_pwm->irq);
NVIC_EnableIRQ((IRQn_Type)cfg_pwm->irq);
return ERR_NONE;
}
/**
* \brief De-initialize TCC for PWM mode
*/
void _pwm_deinit(struct _pwm_device *const device)
{
void *const hw = device->hw;
struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
if (cfg_pwm != NULL) {
NVIC_DisableIRQ((IRQn_Type)cfg_pwm->irq);
hri_tcc_clear_CTRLA_ENABLE_bit(hw);
hri_tcc_set_CTRLA_SWRST_bit(hw);
}
}
/**
* \brief Start PWM
*/
void _pwm_enable(struct _pwm_device *const device)
{
hri_tcc_set_CTRLA_ENABLE_bit(device->hw);
}
/**
* \brief Stop PWM
*/
void _pwm_disable(struct _pwm_device *const device)
{
hri_tcc_clear_CTRLA_ENABLE_bit(device->hw);
}
/**
* \brief Set PWM parameter
*/
void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle)
{
void *const hw = device->hw;
struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
if (cfg_pwm != NULL) {
hri_tcc_write_PERB_reg(hw, period);
hri_tcc_write_CCB_reg(hw, cfg_pwm->sel_ch, duty_cycle);
;
}
}
/**
* \brief Get pwm waveform period value
*/
pwm_period_t _pwm_get_period(const struct _pwm_device *const device)
{
return (pwm_period_t)(hri_tcc_read_PERB_reg(device->hw));
}
/**
* \brief Get pwm waveform duty cycle
*/
uint32_t _pwm_get_duty(const struct _pwm_device *const device)
{
void *const hw = device->hw;
struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
if (cfg_pwm == NULL) {
return ERR_NOT_FOUND;
}
uint32_t per = hri_tcc_read_PERB_reg(hw);
uint32_t duty_cycle = hri_tcc_read_CCB_reg(hw, cfg_pwm->sel_ch);
return ((duty_cycle * 1000) / per);
}
/**
* \brief Check if PWM is running
*/
bool _pwm_is_enabled(const struct _pwm_device *const device)
{
return hri_tcc_get_CTRLA_ENABLE_bit(device->hw);
}
/**
* \brief Enable/disable PWM interrupt
*/
void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable)
{
ASSERT(device);
if (PWM_DEVICE_PERIOD_CB == type) {
hri_tcc_write_INTEN_OVF_bit(device->hw, disable);
} else if (PWM_DEVICE_ERROR_CB == type) {
hri_tcc_write_INTEN_ERR_bit(device->hw, disable);
}
}
/**
* \brief Retrieve timer helper functions
*/
struct _timer_hpl_interface *_tcc_get_timer(void)
{
return NULL;
}
/**
* \brief Retrieve pwm helper functions
*/
struct _pwm_hpl_interface *_tcc_get_pwm(void)
{
return NULL;
}
/**
* \internal TC interrupt handler for PWM
*
* \param[in] instance TC instance number
*/
static void tcc_pwm_interrupt_handler(struct _pwm_device *device)
{
void *const hw = device->hw;
if (hri_tcc_get_interrupt_OVF_bit(hw)) {
hri_tcc_clear_interrupt_OVF_bit(hw);
if (NULL != device->callback.pwm_period_cb) {
device->callback.pwm_period_cb(device);
}
}
if (hri_tcc_get_INTEN_ERR_bit(hw)) {
hri_tcc_clear_interrupt_ERR_bit(hw);
if (NULL != device->callback.pwm_error_cb) {
device->callback.pwm_error_cb(device);
}
}
}
/**
* \brief TCC interrupt handler
*/
void TCC0_0_Handler(void)
{
tcc_pwm_interrupt_handler(_tcc0_dev);
}
/**
* \brief TCC interrupt handler
*/
void TCC1_0_Handler(void)
{
tcc_pwm_interrupt_handler(_tcc1_dev);
}
static struct tcc_cfg *_get_tcc_cfg(void *hw)
{
uint8_t i;
for (i = 0; i < ARRAY_SIZE(_cfgs); i++) {
if (_cfgs[i].hw == hw) {
return &(_cfgs[i]);
}
}
return NULL;
}
static struct tcc_pwm_cfg *_get_tcc_pwm_cfg(void *hw)
{
uint8_t i;
for (i = 0; i < ARRAY_SIZE(_cfgs_pwm); i++) {
if (_cfgs_pwm[i].hw == hw) {
return &(_cfgs_pwm[i]);
}
}
return NULL;
}

77
BLDC_E54/BLDC_E54/hpl/tcc/hpl_tcc.h Normal file
View File

@ -0,0 +1,77 @@
/**
* \file
*
* \brief SAM Timer/Counter for Control Applications
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*/
#ifndef _HPL_TCC_V101_BASE_H_INCLUDED
#define _HPL_TCC_V101_BASE_H_INCLUDED
#include <hpl_timer.h>
#include <hpl_pwm.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup tcc_group TCC Low Level Driver Helpers
*
* \section tcc_helpers_rev Revision History
* - v0.0.0.1 Initial Commit
*
*@{
*/
/**
* \name HPL functions
*/
//@{
/**
* \brief Retrieve timer helper functions
*
* \return A pointer to set of timer helper functions
*/
struct _timer_hpl_interface *_tcc_get_timer(void);
/**
* \brief Retrieve pwm helper functions
*
* \return A pointer to set of pwm helper functions
*/
struct _pwm_hpl_interface *_tcc_get_pwm(void);
//@}
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HPL_TCC_V101_BASE_H_INCLUDED */

2
BLDC_E54/BLDC_E54/interrupt_handlers.h
View File

@ -30,7 +30,7 @@ void TC7_Handler(void)
//One_ms_cycle_callback();
//gpio_toggle_pin_level(DEBUG_1);
One_ms_cycle_callback();
Motor1.timerflags.motor_telemetry_flag = true;
//Motor1.timerflags.motor_telemetry_flag = true;
}
}

29
BLDC_E54/BLDC_E54/main.c
View File

@ -50,8 +50,8 @@ inline void CONTROLLER_StateMachine(void)
break;
case MOTOR_IDLE:
applicationStatus.previousstate = applicationStatus.currentstate;
//applicationStatus.currentstate = MOTOR_PVI_CTRL_STATE;
applicationStatus.currentstate = MOTOR_V_CTRL_STATE;
applicationStatus.currentstate = MOTOR_PVI_CTRL_STATE;
//applicationStatus.currentstate = MOTOR_V_CTRL_STATE;
break;
case MOTOR_I_CTRL_STATE:
@ -64,8 +64,8 @@ inline void CONTROLLER_StateMachine(void)
/* Blank */
case 6: /* PWM FREQ / 6.25 - 4kHz */
calculate_motor_speed();
//BLDC_runSpeedCntl(&Motor1, Motor1.motor_status.calc_rpm, Motor1.motor_setpoints.desired_speed);
BLDC_runSpeedCntl(&Motor1, Motor1.motor_status.calc_rpm, 3000);
BLDC_runSpeedCntl(&Motor1, Motor1.motor_status.calc_rpm, Motor1.motor_setpoints.desired_speed);
//BLDC_runSpeedCntl(&Motor1, Motor1.motor_status.calc_rpm, 3000);
default: /* PWM FREQ - 25kHz */
select_active_phase(&Motor1, Motor1.motor_status.currentHallPattern); /* Still measure current */
break;
@ -212,36 +212,19 @@ int main(void)
/* Replace with your application code */
while (1) {
//tic(DEBUG_1);
//tic_port(DEBUG_3_PORT);
//toc(DEBUG_1);
//toc_port(DEBUG_3_PORT);
//tic(DEBUG_1_PORT);
//toc(DEBUG_1_PORT);
if(Motor1.timerflags.motor_telemetry_flag) {
Motor1.timerflags.motor_telemetry_flag = false;
update_setpoints();
update_telemetry();
}
//{
//gpio_set_pin_level(DRV_RST, true);
//Motor1.timerflags.pwm_cycle_tic = false;
//tic(DEBUG_1);
//exec_commutation();
//toc(DEBUG_1);
//}
if(Motor1.timerflags.current_loop_tic) {
Motor1.timerflags.current_loop_tic = false;
//tic_port(DEBUG_1_PORT);
CONTROLLER_StateMachine();
//toc_port(DEBUG_1_PORT);
}
//do {
//delay_ms(10);
//} while (gpio_get_pin_level(SW0));

8
BLDC_E54/BLDC_E54/motor_params.h
View File

@ -44,14 +44,16 @@
#define MOTOR_LD_H (0.001290f)
#define MOTOR_LQ_H (0.001290f)
#define MOTOR_FLUX_WB (0.0063879968f)
#define MOTOR_MAX_SPD_RPM (4200.0f)
//#define MOTOR_MAX_SPD_RPM (3000.0f)
#define MOTOR_MAX_SPD_RPM (500.0f)
#define MOTOR_MAX_SPD_ELEC ((MOTOR_MAX_SPD_RPM/60)*MOTOR_POLEPAIRS)
#define MOTOR_MEASURINGRANGE_RPM (1.2f * MOTOR_MAX_SPD_RPM)f // give 20% headroom
#define MOTOR_MAX_CURRENT_IDC_A (1.2f)
//#define MOTOR_MAX_CURRENT_IDC_A (0.5f)
#define PWM_TOP 1000
#define MAX_PWM 700
#define MAX_VEL 3800
#define MAX_PWM 600
//#define MAX_VEL 3800
#define CW 0 //CBA
#define DIRECTION_CW_OFFSET 0 //CBA