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commit before change to d51

This commit is contained in:
Nicolas Trimborn 2021-09-02 20:49:22 +02:00
parent fc9c6b483c
commit e7815c6dd3
29 changed files with 223 additions and 211 deletions
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162
2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart
View File

@ -259,11 +259,11 @@ drivers:
dmac_beatsize_27: 8-bit bus transfer
dmac_beatsize_28: 8-bit bus transfer
dmac_beatsize_29: 8-bit bus transfer
dmac_beatsize_3: 32-bit bus transfer
dmac_beatsize_3: 16-bit bus transfer
dmac_beatsize_30: 8-bit bus transfer
dmac_beatsize_31: 8-bit bus transfer
dmac_beatsize_4: 16-bit bus transfer
dmac_beatsize_5: 16-bit bus transfer
dmac_beatsize_4: 32-bit bus transfer
dmac_beatsize_5: 32-bit bus transfer
dmac_beatsize_6: 32-bit bus transfer
dmac_beatsize_7: 32-bit bus transfer
dmac_beatsize_8: 32-bit bus transfer
@ -314,21 +314,19 @@ drivers:
dmac_blockact_29: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_3: Channel will be disabled if it is the last block transfer in
the transaction
the transaction and block interrupt
dmac_blockact_30: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_31: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_4: Channel will be disabled if it is the last block transfer in
the transaction and block interrupt
dmac_blockact_5: Channel will be disabled if it is the last block transfer in
the transaction and block interrupt
dmac_blockact_4: Channel suspend operation is complete
dmac_blockact_5: Channel suspend operation is complete
dmac_blockact_6: Channel suspend operation is complete
dmac_blockact_7: Channel suspend operation is complete
dmac_blockact_8: Channel suspend operation is complete
dmac_blockact_9: Channel suspend operation is complete
dmac_channel_0_settings: false
dmac_channel_10_settings: true
dmac_channel_0_settings: true
dmac_channel_10_settings: false
dmac_channel_11_settings: false
dmac_channel_12_settings: false
dmac_channel_13_settings: false
@ -355,10 +353,10 @@ drivers:
dmac_channel_3_settings: true
dmac_channel_4_settings: true
dmac_channel_5_settings: true
dmac_channel_6_settings: false
dmac_channel_6_settings: true
dmac_channel_7_settings: true
dmac_channel_8_settings: true
dmac_channel_9_settings: true
dmac_channel_8_settings: false
dmac_channel_9_settings: false
dmac_dbgrun: false
dmac_dstinc_0: true
dmac_dstinc_1: true
@ -386,8 +384,8 @@ drivers:
dmac_dstinc_3: true
dmac_dstinc_30: false
dmac_dstinc_31: false
dmac_dstinc_4: true
dmac_dstinc_5: true
dmac_dstinc_4: false
dmac_dstinc_5: false
dmac_dstinc_6: false
dmac_dstinc_7: false
dmac_dstinc_8: false
@ -419,8 +417,8 @@ drivers:
dmac_evact_3: No action
dmac_evact_30: No action
dmac_evact_31: No action
dmac_evact_4: No action
dmac_evact_5: No action
dmac_evact_4: Channel resume operation
dmac_evact_5: Channel resume operation
dmac_evact_6: Channel resume operation
dmac_evact_7: Channel resume operation
dmac_evact_8: Channel resume operation
@ -451,13 +449,13 @@ drivers:
dmac_evie_3: false
dmac_evie_30: false
dmac_evie_31: false
dmac_evie_4: false
dmac_evie_5: false
dmac_evie_4: true
dmac_evie_5: true
dmac_evie_6: true
dmac_evie_7: true
dmac_evie_8: true
dmac_evie_9: true
dmac_evoe_0: false
dmac_evoe_0: true
dmac_evoe_1: true
dmac_evoe_10: false
dmac_evoe_11: false
@ -489,7 +487,7 @@ drivers:
dmac_evoe_7: false
dmac_evoe_8: false
dmac_evoe_9: false
dmac_evosel_0: Event generation disabled
dmac_evosel_0: Event strobe when block transfer complete
dmac_evosel_1: Event strobe when block transfer complete
dmac_evosel_10: Event generation disabled
dmac_evosel_11: Event generation disabled
@ -623,8 +621,8 @@ drivers:
dmac_srcinc_3: false
dmac_srcinc_30: false
dmac_srcinc_31: false
dmac_srcinc_4: false
dmac_srcinc_5: false
dmac_srcinc_4: true
dmac_srcinc_5: true
dmac_srcinc_6: true
dmac_srcinc_7: true
dmac_srcinc_8: true
@ -693,8 +691,8 @@ drivers:
dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_trifsrc_0: QSPI Rx Trigger
dmac_trifsrc_1: SERCOM1 RX Trigger
dmac_trifsrc_0: SERCOM1 RX Trigger
dmac_trifsrc_1: SERCOM5 RX Trigger
dmac_trifsrc_10: SERCOM1 TX Trigger
dmac_trifsrc_11: QSPI Tx Trigger
dmac_trifsrc_12: Only software/event triggers
@ -716,13 +714,13 @@ drivers:
dmac_trifsrc_27: Only software/event triggers
dmac_trifsrc_28: Only software/event triggers
dmac_trifsrc_29: Only software/event triggers
dmac_trifsrc_3: SERCOM5 RX Trigger
dmac_trifsrc_3: ADC1 Result Ready Trigger
dmac_trifsrc_30: Only software/event triggers
dmac_trifsrc_31: Only software/event triggers
dmac_trifsrc_4: ADC0 Result Ready Trigger
dmac_trifsrc_5: ADC1 Result Ready Trigger
dmac_trifsrc_6: ADC0 Sequencing Trigger
dmac_trifsrc_7: ADC1 Sequencing Trigger
dmac_trifsrc_4: ADC1 Sequencing Trigger
dmac_trifsrc_5: SERCOM2 TX Trigger
dmac_trifsrc_6: SERCOM5 TX Trigger
dmac_trifsrc_7: SERCOM1 TX Trigger
dmac_trifsrc_8: SERCOM2 TX Trigger
dmac_trifsrc_9: SERCOM5 TX Trigger
dmac_trigact_0: One trigger required for each beat transfer
@ -919,14 +917,14 @@ drivers:
api: HAL:Driver:Event_system
configuration:
evsys_channel_0: No channel output selected
evsys_channel_1: Channel 3
evsys_channel_10: No channel output selected
evsys_channel_11: No channel output selected
evsys_channel_12: Channel 0
evsys_channel_1: Channel 1
evsys_channel_10: Channel 5
evsys_channel_11: Channel 4
evsys_channel_12: Channel 2
evsys_channel_17: No channel output selected
evsys_channel_18: No channel output selected
evsys_channel_19: No channel output selected
evsys_channel_2: Channel 4
evsys_channel_2: Channel 6
evsys_channel_20: No channel output selected
evsys_channel_21: No channel output selected
evsys_channel_22: No channel output selected
@ -948,16 +946,16 @@ drivers:
evsys_channel_37: No channel output selected
evsys_channel_38: No channel output selected
evsys_channel_39: No channel output selected
evsys_channel_4: Channel 6
evsys_channel_4: Channel 8
evsys_channel_40: No channel output selected
evsys_channel_41: No channel output selected
evsys_channel_42: No channel output selected
evsys_channel_43: No channel output selected
evsys_channel_44: No channel output selected
evsys_channel_45: No channel output selected
evsys_channel_46: Channel 1
evsys_channel_46: Channel 11
evsys_channel_47: No channel output selected
evsys_channel_48: Channel 2
evsys_channel_48: Channel 12
evsys_channel_49: No channel output selected
evsys_channel_5: No channel output selected
evsys_channel_50: No channel output selected
@ -980,12 +978,12 @@ drivers:
evsys_channel_66: No channel output selected
evsys_channel_7: No channel output selected
evsys_channel_8: No channel output selected
evsys_channel_9: No channel output selected
evsys_channel_9: Channel 0
evsys_channel_setting_0: true
evsys_channel_setting_1: true
evsys_channel_setting_10: false
evsys_channel_setting_11: false
evsys_channel_setting_12: false
evsys_channel_setting_11: true
evsys_channel_setting_12: true
evsys_channel_setting_13: false
evsys_channel_setting_14: false
evsys_channel_setting_15: false
@ -993,7 +991,7 @@ drivers:
evsys_channel_setting_17: false
evsys_channel_setting_18: false
evsys_channel_setting_19: false
evsys_channel_setting_2: true
evsys_channel_setting_2: false
evsys_channel_setting_20: false
evsys_channel_setting_21: false
evsys_channel_setting_22: false
@ -1004,14 +1002,14 @@ drivers:
evsys_channel_setting_27: false
evsys_channel_setting_28: false
evsys_channel_setting_29: false
evsys_channel_setting_3: true
evsys_channel_setting_3: false
evsys_channel_setting_30: false
evsys_channel_setting_31: false
evsys_channel_setting_4: true
evsys_channel_setting_4: false
evsys_channel_setting_5: true
evsys_channel_setting_6: true
evsys_channel_setting_7: false
evsys_channel_setting_8: false
evsys_channel_setting_7: true
evsys_channel_setting_8: true
evsys_channel_setting_9: false
evsys_edgsel_0: No event output when using the resynchronized or synchronous
path
@ -1019,10 +1017,10 @@ drivers:
generator
evsys_edgsel_10: No event output when using the resynchronized or synchronous
path
evsys_edgsel_11: No event output when using the resynchronized or synchronous
path
evsys_edgsel_12: No event output when using the resynchronized or synchronous
path
evsys_edgsel_11: Event is detected on the rising edge of the signal from event
generator
evsys_edgsel_12: Event is detected on the rising edge of the signal from event
generator
evsys_edgsel_13: No event output when using the resynchronized or synchronous
path
evsys_edgsel_14: No event output when using the resynchronized or synchronous
@ -1073,8 +1071,8 @@ drivers:
generator
evsys_edgsel_7: No event output when using the resynchronized or synchronous
path
evsys_edgsel_8: No event output when using the resynchronized or synchronous
path
evsys_edgsel_8: Event is detected on the rising edge of the signal from event
generator
evsys_edgsel_9: No event output when using the resynchronized or synchronous
path
evsys_evd_0: false
@ -1104,16 +1102,16 @@ drivers:
evsys_evd_30: false
evsys_evd_31: false
evsys_evd_4: true
evsys_evd_5: true
evsys_evd_5: false
evsys_evd_6: true
evsys_evd_7: false
evsys_evd_8: false
evsys_evd_7: true
evsys_evd_8: true
evsys_evd_9: false
evsys_evgen_0: TCC0 overflow
evsys_evgen_1: CCL LUT output 0
evsys_evgen_1: TC0 match/capture 0
evsys_evgen_10: No event generator
evsys_evgen_11: No event generator
evsys_evgen_12: No event generator
evsys_evgen_11: CCL LUT output 0
evsys_evgen_12: CCL LUT output 2
evsys_evgen_13: No event generator
evsys_evgen_14: No event generator
evsys_evgen_15: No event generator
@ -1121,7 +1119,7 @@ drivers:
evsys_evgen_17: No event generator
evsys_evgen_18: No event generator
evsys_evgen_19: No event generator
evsys_evgen_2: CCL LUT output 2
evsys_evgen_2: TC0 match/capture 1
evsys_evgen_20: No event generator
evsys_evgen_21: No event generator
evsys_evgen_22: No event generator
@ -1135,11 +1133,11 @@ drivers:
evsys_evgen_3: TC0 match/capture 0
evsys_evgen_30: No event generator
evsys_evgen_31: No event generator
evsys_evgen_4: DMAC channel 1
evsys_evgen_5: DMAC channel 2
evsys_evgen_6: EIC external interrupt 2
evsys_evgen_7: No event generator
evsys_evgen_8: No event generator
evsys_evgen_4: TC0 match/capture 1
evsys_evgen_5: EIC external interrupt 2
evsys_evgen_6: DMAC channel 0
evsys_evgen_7: DMAC channel 1
evsys_evgen_8: DMAC channel 2
evsys_evgen_9: No event generator
evsys_ondemand_0: false
evsys_ondemand_1: false
@ -1208,8 +1206,8 @@ drivers:
evsys_path_0: Asynchronous path
evsys_path_1: Asynchronous path
evsys_path_10: Synchronous path
evsys_path_11: Synchronous path
evsys_path_12: Synchronous path
evsys_path_11: Asynchronous path
evsys_path_12: Asynchronous path
evsys_path_13: Synchronous path
evsys_path_14: Synchronous path
evsys_path_15: Synchronous path
@ -1231,9 +1229,9 @@ drivers:
evsys_path_3: Asynchronous path
evsys_path_30: Synchronous path
evsys_path_31: Synchronous path
evsys_path_4: Synchronous path
evsys_path_5: Synchronous path
evsys_path_6: Asynchronous path
evsys_path_4: Asynchronous path
evsys_path_5: Asynchronous path
evsys_path_6: Synchronous path
evsys_path_7: Synchronous path
evsys_path_8: Synchronous path
evsys_path_9: Synchronous path
@ -1644,8 +1642,8 @@ drivers:
enable_port_input_event_3: true
porta_event_action_0: Output register of pin will be set to level of event
porta_event_action_1: Output register of pin will be set to level of event
porta_event_action_2: Set output register of pin on event
porta_event_action_3: Clear output register of pin on event
porta_event_action_2: Clear output register of pin on event
porta_event_action_3: Set output register of pin on event
porta_event_pin_identifier_0: 0
porta_event_pin_identifier_1: 0
porta_event_pin_identifier_2: 14
@ -1656,8 +1654,8 @@ drivers:
porta_input_event_enable_3: true
portb_event_action_0: Clear output register of pin on event
portb_event_action_1: Set output register of pin on event
portb_event_action_2: Output register of pin will be set to level of event
portb_event_action_3: Output register of pin will be set to level of event
portb_event_action_2: Clear output register of pin on event
portb_event_action_3: Set output register of pin on event
portb_event_pin_identifier_0: 22
portb_event_pin_identifier_1: 22
portb_event_pin_identifier_2: 0
@ -1756,8 +1754,8 @@ drivers:
spi_master_arch_runstdby: false
spi_master_baud_rate: 2000000
spi_master_character_size: 8 bits
spi_master_dma_rx_channel: 1
spi_master_dma_tx_channel: 10
spi_master_dma_rx_channel: 0
spi_master_dma_tx_channel: 7
spi_master_dummybyte: 511
spi_master_rx_channel: true
spi_master_rx_enable: true
@ -1882,8 +1880,8 @@ drivers:
functionality: Timer
api: Lite:TC:Timer
configuration:
cc_cc0: 117
cc_cc1: 180
cc_cc0: 10
cc_cc1: 60
cc_control: true
count_control: false
count_count: 0
@ -1898,7 +1896,7 @@ drivers:
ctrla_enable: true
ctrla_mode: 1
ctrla_ondemand: false
ctrla_prescaler: DIV1024
ctrla_prescaler: DIV8
ctrla_prescsync: GCLK
ctrla_runstdby: false
ctrlbset_cmd: NONE
@ -1922,9 +1920,9 @@ drivers:
intenset_err: false
intenset_mc0: false
intenset_mc1: true
intenset_ovf: false
intenset_ovf: true
per_control: true
per_per: 255
per_per: 250
wave_control: true
wave_wavegen: NFRQ
optional_signals: []
@ -1933,11 +1931,11 @@ drivers:
domain_group:
nodes:
- name: TC
input: Generic clock generator 0
input: Generic clock generator 1
external: false
external_frequency: 0
configuration:
tc_gclk_selection: Generic clock generator 0
tc_gclk_selection: Generic clock generator 1
TC_SPEED_M1:
user_label: TC_SPEED_M1
definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::TC2::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer

56
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_dmac_config.h
View File

@ -105,7 +105,7 @@
// <e> Channel 0 settings
// <id> dmac_channel_0_settings
#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
#define CONF_DMAC_CHANNEL_0_SETTINGS 0
#define CONF_DMAC_CHANNEL_0_SETTINGS 1
#endif
// <q> Channel Run in Standby
@ -214,7 +214,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_0
#ifndef CONF_DMAC_TRIGSRC_0
#define CONF_DMAC_TRIGSRC_0 83
#define CONF_DMAC_TRIGSRC_0 6
#endif
// <o> Channel Arbitration Level
@ -232,7 +232,7 @@
// <i> Indicates whether channel event generation is enabled or not
// <id> dmac_evoe_0
#ifndef CONF_DMAC_EVOE_0
#define CONF_DMAC_EVOE_0 0
#define CONF_DMAC_EVOE_0 1
#endif
// <q> Channel Event Input
@ -322,7 +322,7 @@
// <i> Defines the event output selection
// <id> dmac_evosel_0
#ifndef CONF_DMAC_EVOSEL_0
#define CONF_DMAC_EVOSEL_0 0
#define CONF_DMAC_EVOSEL_0 1
#endif
// </e>
@ -438,7 +438,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_1
#ifndef CONF_DMAC_TRIGSRC_1
#define CONF_DMAC_TRIGSRC_1 6
#define CONF_DMAC_TRIGSRC_1 14
#endif
// <o> Channel Arbitration Level
@ -886,7 +886,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_3
#ifndef CONF_DMAC_TRIGSRC_3
#define CONF_DMAC_TRIGSRC_3 14
#define CONF_DMAC_TRIGSRC_3 70
#endif
// <o> Channel Arbitration Level
@ -973,7 +973,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_3
#ifndef CONF_DMAC_BEATSIZE_3
#define CONF_DMAC_BEATSIZE_3 2
#define CONF_DMAC_BEATSIZE_3 1
#endif
// <o> Block Action
@ -984,7 +984,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_3
#ifndef CONF_DMAC_BLOCKACT_3
#define CONF_DMAC_BLOCKACT_3 0
#define CONF_DMAC_BLOCKACT_3 1
#endif
// <o> Event Output Selection
@ -1110,7 +1110,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_4
#ifndef CONF_DMAC_TRIGSRC_4
#define CONF_DMAC_TRIGSRC_4 68
#define CONF_DMAC_TRIGSRC_4 71
#endif
// <o> Channel Arbitration Level
@ -1135,7 +1135,7 @@
// <i> Indicates whether channel event reception is enabled or not
// <id> dmac_evie_4
#ifndef CONF_DMAC_EVIE_4
#define CONF_DMAC_EVIE_4 0
#define CONF_DMAC_EVIE_4 1
#endif
// <o> Event Input Action
@ -1149,7 +1149,7 @@
// <i> Defines the event input action
// <id> dmac_evact_4
#ifndef CONF_DMAC_EVACT_4
#define CONF_DMAC_EVACT_4 0
#define CONF_DMAC_EVACT_4 5
#endif
// <o> Address Increment Step Size
@ -1180,14 +1180,14 @@
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_4
#ifndef CONF_DMAC_SRCINC_4
#define CONF_DMAC_SRCINC_4 0
#define CONF_DMAC_SRCINC_4 1
#endif
// <q> Destination Address Increment
// <i> Indicates whether the destination address incrementation is enabled or not
// <id> dmac_dstinc_4
#ifndef CONF_DMAC_DSTINC_4
#define CONF_DMAC_DSTINC_4 1
#define CONF_DMAC_DSTINC_4 0
#endif
// <o> Beat Size
@ -1197,7 +1197,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_4
#ifndef CONF_DMAC_BEATSIZE_4
#define CONF_DMAC_BEATSIZE_4 1
#define CONF_DMAC_BEATSIZE_4 2
#endif
// <o> Block Action
@ -1208,7 +1208,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_4
#ifndef CONF_DMAC_BLOCKACT_4
#define CONF_DMAC_BLOCKACT_4 1
#define CONF_DMAC_BLOCKACT_4 2
#endif
// <o> Event Output Selection
@ -1334,7 +1334,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_5
#ifndef CONF_DMAC_TRIGSRC_5
#define CONF_DMAC_TRIGSRC_5 70
#define CONF_DMAC_TRIGSRC_5 9
#endif
// <o> Channel Arbitration Level
@ -1359,7 +1359,7 @@
// <i> Indicates whether channel event reception is enabled or not
// <id> dmac_evie_5
#ifndef CONF_DMAC_EVIE_5
#define CONF_DMAC_EVIE_5 0
#define CONF_DMAC_EVIE_5 1
#endif
// <o> Event Input Action
@ -1373,7 +1373,7 @@
// <i> Defines the event input action
// <id> dmac_evact_5
#ifndef CONF_DMAC_EVACT_5
#define CONF_DMAC_EVACT_5 0
#define CONF_DMAC_EVACT_5 5
#endif
// <o> Address Increment Step Size
@ -1404,14 +1404,14 @@
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_5
#ifndef CONF_DMAC_SRCINC_5
#define CONF_DMAC_SRCINC_5 0
#define CONF_DMAC_SRCINC_5 1
#endif
// <q> Destination Address Increment
// <i> Indicates whether the destination address incrementation is enabled or not
// <id> dmac_dstinc_5
#ifndef CONF_DMAC_DSTINC_5
#define CONF_DMAC_DSTINC_5 1
#define CONF_DMAC_DSTINC_5 0
#endif
// <o> Beat Size
@ -1421,7 +1421,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_5
#ifndef CONF_DMAC_BEATSIZE_5
#define CONF_DMAC_BEATSIZE_5 1
#define CONF_DMAC_BEATSIZE_5 2
#endif
// <o> Block Action
@ -1432,7 +1432,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_5
#ifndef CONF_DMAC_BLOCKACT_5
#define CONF_DMAC_BLOCKACT_5 1
#define CONF_DMAC_BLOCKACT_5 2
#endif
// <o> Event Output Selection
@ -1449,7 +1449,7 @@
// <e> Channel 6 settings
// <id> dmac_channel_6_settings
#ifndef CONF_DMAC_CHANNEL_6_SETTINGS
#define CONF_DMAC_CHANNEL_6_SETTINGS 0
#define CONF_DMAC_CHANNEL_6_SETTINGS 1
#endif
// <q> Channel Run in Standby
@ -1558,7 +1558,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_6
#ifndef CONF_DMAC_TRIGSRC_6
#define CONF_DMAC_TRIGSRC_6 69
#define CONF_DMAC_TRIGSRC_6 15
#endif
// <o> Channel Arbitration Level
@ -1782,7 +1782,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_7
#ifndef CONF_DMAC_TRIGSRC_7
#define CONF_DMAC_TRIGSRC_7 71
#define CONF_DMAC_TRIGSRC_7 7
#endif
// <o> Channel Arbitration Level
@ -1897,7 +1897,7 @@
// <e> Channel 8 settings
// <id> dmac_channel_8_settings
#ifndef CONF_DMAC_CHANNEL_8_SETTINGS
#define CONF_DMAC_CHANNEL_8_SETTINGS 1
#define CONF_DMAC_CHANNEL_8_SETTINGS 0
#endif
// <q> Channel Run in Standby
@ -2121,7 +2121,7 @@
// <e> Channel 9 settings
// <id> dmac_channel_9_settings
#ifndef CONF_DMAC_CHANNEL_9_SETTINGS
#define CONF_DMAC_CHANNEL_9_SETTINGS 1
#define CONF_DMAC_CHANNEL_9_SETTINGS 0
#endif
// <q> Channel Run in Standby
@ -2345,7 +2345,7 @@
// <e> Channel 10 settings
// <id> dmac_channel_10_settings
#ifndef CONF_DMAC_CHANNEL_10_SETTINGS
#define CONF_DMAC_CHANNEL_10_SETTINGS 1
#define CONF_DMAC_CHANNEL_10_SETTINGS 0
#endif
// <q> Channel Run in Standby

72
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_evsys_config.h
View File

@ -333,7 +333,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_1
#ifndef CONF_EVGEN_1
#define CONF_EVGEN_1 116
#define CONF_EVGEN_1 74
#endif
// <q> Overrun channel interrupt
@ -369,7 +369,7 @@
// <e> Channel 2 settings
// <id> evsys_channel_setting_2
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_2
#define CONF_EVSYS_CHANNEL_SETTINGS_2 1
#define CONF_EVSYS_CHANNEL_SETTINGS_2 0
#endif
// <y> Edge detection
@ -514,7 +514,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_2
#ifndef CONF_EVGEN_2
#define CONF_EVGEN_2 118
#define CONF_EVGEN_2 75
#endif
// <q> Overrun channel interrupt
@ -550,7 +550,7 @@
// <e> Channel 3 settings
// <id> evsys_channel_setting_3
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_3
#define CONF_EVSYS_CHANNEL_SETTINGS_3 1
#define CONF_EVSYS_CHANNEL_SETTINGS_3 0
#endif
// <y> Edge detection
@ -731,7 +731,7 @@
// <e> Channel 4 settings
// <id> evsys_channel_setting_4
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_4
#define CONF_EVSYS_CHANNEL_SETTINGS_4 1
#define CONF_EVSYS_CHANNEL_SETTINGS_4 0
#endif
// <y> Edge detection
@ -752,7 +752,7 @@
// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
// <id> evsys_path_4
#ifndef CONF_PATH_4
#define CONF_PATH_4 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
#define CONF_PATH_4 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
#endif
// <o> Event generator
@ -876,7 +876,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_4
#ifndef CONF_EVGEN_4
#define CONF_EVGEN_4 35
#define CONF_EVGEN_4 75
#endif
// <q> Overrun channel interrupt
@ -933,7 +933,7 @@
// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
// <id> evsys_path_5
#ifndef CONF_PATH_5
#define CONF_PATH_5 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
#define CONF_PATH_5 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
#endif
// <o> Event generator
@ -1057,7 +1057,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_5
#ifndef CONF_EVGEN_5
#define CONF_EVGEN_5 36
#define CONF_EVGEN_5 20
#endif
// <q> Overrun channel interrupt
@ -1071,7 +1071,7 @@
// <i> Indicates whether event detected interrupt is enabled or not
// <id> evsys_evd_5
#ifndef CONF_EVD_5
#define CONF_EVD_5 1
#define CONF_EVD_5 0
#endif
// <q> On demand clock
@ -1114,7 +1114,7 @@
// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
// <id> evsys_path_6
#ifndef CONF_PATH_6
#define CONF_PATH_6 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
#define CONF_PATH_6 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
#endif
// <o> Event generator
@ -1238,7 +1238,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_6
#ifndef CONF_EVGEN_6
#define CONF_EVGEN_6 20
#define CONF_EVGEN_6 34
#endif
// <q> Overrun channel interrupt
@ -1274,7 +1274,7 @@
// <e> Channel 7 settings
// <id> evsys_channel_setting_7
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_7
#define CONF_EVSYS_CHANNEL_SETTINGS_7 0
#define CONF_EVSYS_CHANNEL_SETTINGS_7 1
#endif
// <y> Edge detection
@ -1419,7 +1419,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_7
#ifndef CONF_EVGEN_7
#define CONF_EVGEN_7 0
#define CONF_EVGEN_7 35
#endif
// <q> Overrun channel interrupt
@ -1433,7 +1433,7 @@
// <i> Indicates whether event detected interrupt is enabled or not
// <id> evsys_evd_7
#ifndef CONF_EVD_7
#define CONF_EVD_7 0
#define CONF_EVD_7 1
#endif
// <q> On demand clock
@ -1455,7 +1455,7 @@
// <e> Channel 8 settings
// <id> evsys_channel_setting_8
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_8
#define CONF_EVSYS_CHANNEL_SETTINGS_8 0
#define CONF_EVSYS_CHANNEL_SETTINGS_8 1
#endif
// <y> Edge detection
@ -1466,7 +1466,7 @@
// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
// <id> evsys_edgsel_8
#ifndef CONF_EDGSEL_8
#define CONF_EDGSEL_8 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
#define CONF_EDGSEL_8 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
#endif
// <y> Path selection
@ -1600,7 +1600,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_8
#ifndef CONF_EVGEN_8
#define CONF_EVGEN_8 0
#define CONF_EVGEN_8 36
#endif
// <q> Overrun channel interrupt
@ -1614,7 +1614,7 @@
// <i> Indicates whether event detected interrupt is enabled or not
// <id> evsys_evd_8
#ifndef CONF_EVD_8
#define CONF_EVD_8 0
#define CONF_EVD_8 1
#endif
// <q> On demand clock
@ -1998,7 +1998,7 @@
// <e> Channel 11 settings
// <id> evsys_channel_setting_11
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_11
#define CONF_EVSYS_CHANNEL_SETTINGS_11 0
#define CONF_EVSYS_CHANNEL_SETTINGS_11 1
#endif
// <y> Edge detection
@ -2009,7 +2009,7 @@
// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
// <id> evsys_edgsel_11
#ifndef CONF_EDGSEL_11
#define CONF_EDGSEL_11 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
#define CONF_EDGSEL_11 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
#endif
// <y> Path selection
@ -2019,7 +2019,7 @@
// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
// <id> evsys_path_11
#ifndef CONF_PATH_11
#define CONF_PATH_11 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
#define CONF_PATH_11 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
#endif
// <o> Event generator
@ -2143,7 +2143,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_11
#ifndef CONF_EVGEN_11
#define CONF_EVGEN_11 0
#define CONF_EVGEN_11 116
#endif
// <q> Overrun channel interrupt
@ -2179,7 +2179,7 @@
// <e> Channel 12 settings
// <id> evsys_channel_setting_12
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_12
#define CONF_EVSYS_CHANNEL_SETTINGS_12 0
#define CONF_EVSYS_CHANNEL_SETTINGS_12 1
#endif
// <y> Edge detection
@ -2190,7 +2190,7 @@
// <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
// <id> evsys_edgsel_12
#ifndef CONF_EDGSEL_12
#define CONF_EDGSEL_12 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
#define CONF_EDGSEL_12 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
#endif
// <y> Path selection
@ -2200,7 +2200,7 @@
// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
// <id> evsys_path_12
#ifndef CONF_PATH_12
#define CONF_PATH_12 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
#define CONF_PATH_12 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
#endif
// <o> Event generator
@ -2324,7 +2324,7 @@
// <0x77=>CCL LUT output 3
// <id> evsys_evgen_12
#ifndef CONF_EVGEN_12
#define CONF_EVGEN_12 0
#define CONF_EVGEN_12 118
#endif
// <q> Overrun channel interrupt
@ -5880,7 +5880,7 @@
// <id> evsys_channel_1
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_1
#define CONF_CHANNEL_1 4
#define CONF_CHANNEL_1 2
#endif
// <o> Channel selection for PORT event 1
@ -5920,7 +5920,7 @@
// <id> evsys_channel_2
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_2
#define CONF_CHANNEL_2 5
#define CONF_CHANNEL_2 7
#endif
// <o> Channel selection for PORT event 2
@ -6000,7 +6000,7 @@
// <id> evsys_channel_4
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_4
#define CONF_CHANNEL_4 7
#define CONF_CHANNEL_4 9
#endif
//</h>
@ -6202,7 +6202,7 @@
// <id> evsys_channel_9
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_9
#define CONF_CHANNEL_9 0
#define CONF_CHANNEL_9 1
#endif
// <o> Channel selection for DMAC channel 5
@ -6242,7 +6242,7 @@
// <id> evsys_channel_10
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_10
#define CONF_CHANNEL_10 0
#define CONF_CHANNEL_10 6
#endif
// <o> Channel selection for DMAC channel 6
@ -6282,7 +6282,7 @@
// <id> evsys_channel_11
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_11
#define CONF_CHANNEL_11 0
#define CONF_CHANNEL_11 5
#endif
// <o> Channel selection for DMAC channel 7
@ -6322,7 +6322,7 @@
// <id> evsys_channel_12
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_12
#define CONF_CHANNEL_12 1
#define CONF_CHANNEL_12 3
#endif
//</h>
@ -7544,7 +7544,7 @@
// <id> evsys_channel_46
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_46
#define CONF_CHANNEL_46 2
#define CONF_CHANNEL_46 12
#endif
// <o> Channel selection for TC3 event
@ -7624,7 +7624,7 @@
// <id> evsys_channel_48
// <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_48
#define CONF_CHANNEL_48 3
#define CONF_CHANNEL_48 13
#endif
// <o> Channel selection for TC5 event

8
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_port_config.h
View File

@ -164,7 +164,7 @@
// <i> These bits define the event action the PORT A will perform on event input 2
// <id> porta_event_action_2
#ifndef CONF_PORTA_EVCTRL_EVACT_2
#define CONF_PORTA_EVCTRL_EVACT_2 1
#define CONF_PORTA_EVCTRL_EVACT_2 2
#endif
// </h>
@ -192,7 +192,7 @@
// <i> These bits define the event action the PORT B will perform on event input 2
// <id> portb_event_action_2
#ifndef CONF_PORTB_EVCTRL_EVACT_2
#define CONF_PORTB_EVCTRL_EVACT_2 0
#define CONF_PORTB_EVCTRL_EVACT_2 2
#endif
// </h>
@ -229,7 +229,7 @@
// <i> These bits define the event action the PORT A will perform on event input 3
// <id> porta_event_action_3
#ifndef CONF_PORTA_EVCTRL_EVACT_3
#define CONF_PORTA_EVCTRL_EVACT_3 2
#define CONF_PORTA_EVCTRL_EVACT_3 1
#endif
// </h>
@ -257,7 +257,7 @@
// <i> These bits define the event action the PORT B will perform on event input 3
// <id> portb_event_action_3
#ifndef CONF_PORTB_EVCTRL_EVACT_3
#define CONF_PORTB_EVCTRL_EVACT_3 0
#define CONF_PORTB_EVCTRL_EVACT_3 1
#endif
// </h>

4
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h
View File

@ -15,7 +15,7 @@
//<i> This defines DMA channel to be used
//<id> spi_master_dma_tx_channel
#ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 10
#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 7
#endif
// <e> SPI RX Channel Enable
@ -28,7 +28,7 @@
//<i> This defines DMA channel to be used
//<id> spi_master_dma_rx_channel
#ifndef CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL
#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 1
#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 0
#endif
// </e>

4
2_Motor_Master/Motor_Master/Motor_Master/Config/peripheral_clk_config.h
View File

@ -893,7 +893,7 @@
// <i> Select the clock source for TC.
#ifndef CONF_GCLK_TC0_SRC
#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#endif
/**
@ -901,7 +901,7 @@
* \brief TC0's Clock frequency
*/
#ifndef CONF_GCLK_TC0_FREQUENCY
#define CONF_GCLK_TC0_FREQUENCY 100000000
#define CONF_GCLK_TC0_FREQUENCY 2000000
#endif
// <y> TC Clock Source

2
2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.componentinfo.xml
View File

@ -91,7 +91,7 @@
<Attribute>template</Attribute>
<Category>source</Category>
<Condition>C Exe</Condition>
<FileContentHash>5/u/VzT6YicSrkF/TEhsaQ==</FileContentHash>
<FileContentHash>bVtz6/s2nKLwVTITbJPLlQ==</FileContentHash>
<FileVersion></FileVersion>
<Name>templates/main.c</Name>
<SelectString>Main file (.c)</SelectString>

38
2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj
View File

@ -150,7 +150,7 @@
<AcmeProjectActionInfo Action="File" Source="hri/hri_usb_e51.h" IsConfig="false" Hash="x6M7vYgNCS2oECqykr5+yw" />
<AcmeProjectActionInfo Action="File" Source="hri/hri_wdt_e51.h" IsConfig="false" Hash="o9Rg/hyuMzwOCphVc7uG1w" />
<AcmeProjectActionInfo Action="File" Source="main.c" IsConfig="false" Hash="k0AH7j+BrmdFhBPzCCMptA" />
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="FNBo89HkbG68dEmgi30eyQ" />
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="3OxQAqTAa4rYMj/raXEwmA" />
<AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="NyJtBqCuH2RlTy0iltvcfg" />
<AcmeProjectActionInfo Action="File" Source="atmel_start_pins.h" IsConfig="false" Hash="q332kmNEqTBha3F9F86pCg" />
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="yuNriNBbj5kyY6X2I3Qu+A" />
@ -197,7 +197,7 @@
<AcmeProjectActionInfo Action="File" Source="hpl/qspi/hpl_qspi.c" IsConfig="false" Hash="woXbbCFkSWus6J14PHJlHw" />
<AcmeProjectActionInfo Action="File" Source="hpl/ramecc/hpl_ramecc.c" IsConfig="false" Hash="pMdmwVWBg16VG8HOwA3DPw" />
<AcmeProjectActionInfo Action="File" Source="hpl/sercom/hpl_sercom.c" IsConfig="false" Hash="hcMq5dgdlyb9xXr1YOQnMQ" />
<AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.c" IsConfig="false" Hash="rgTvxuBnL9g4Ehy4toqpuA" />
<AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.c" IsConfig="false" Hash="kz+bp4op9YRjnBul3eSRqA" />
<AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.h" IsConfig="false" Hash="zTBTKMmLh2GsbqmbMsUX8g" />
<AcmeProjectActionInfo Action="File" Source="hpl/tcc/hpl_tcc.c" IsConfig="false" Hash="DC3UZSTUv1CDjekNxClhVg" />
<AcmeProjectActionInfo Action="File" Source="hpl/tcc/hpl_tcc.h" IsConfig="false" Hash="rdWkAK12qkOYV59tWwzy6A" />
@ -206,26 +206,28 @@
<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="IJeJ3sDxG9f3mmsLxoMLlA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="Ugqkh4JI/bavEsL6AOVmkA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="c2mFPMtMeiOShLEVxcw7dA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="Zre11F0UnVVaJqMRScEOwA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="45sXrEEoF/ulrCsrA93KmA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="cB1sDpQYOnu3879R9Q3umQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Xe5v62bijwZLOPLD+rPcrA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="ClWspYc5VwPMxMXzZp6pSw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="6ehr8XBnb+p6XoRmEyYIGw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_qspi_config.h" IsConfig="true" Hash="CwZ360eeEYs7T9SYFSvDug" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="YhOvJRia1eKe9odgdXn9EQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="tTBTi6avaSGiP8DXcNnKeQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" />
<AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="s728fWyHIPUXyuq8+2qWsg" />
<AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="9AMUnzTI9+M2WQoaURqWRA" />
</AcmeActionInfos>
<NonsecureFilesInfo />
</AcmeProjectConfig>
</AcmeProjectConfig>
<avrtool>com.atmel.avrdbg.tool.atmelice</avrtool>
<avrtool>
</avrtool>
<avrtoolserialnumber>J42700013287</avrtoolserialnumber>
<avrdeviceexpectedsignature>0x61810302</avrdeviceexpectedsignature>
<avrtoolinterface>SWD</avrtoolinterface>
<avrtoolinterface>
</avrtoolinterface>
<com_atmel_avrdbg_tool_atmelice>
<ToolOptions>
<InterfaceProperties>
@ -254,7 +256,6 @@
</armgcc.compiler.symbols.DefSymbols>
<armgcc.compiler.directories.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -279,6 +280,7 @@
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.compiler.directories.IncludePaths>
@ -304,7 +306,6 @@
<armgcc.linker.miscellaneous.LinkerFlags>-Tsame51j19a_flash.ld</armgcc.linker.miscellaneous.LinkerFlags>
<armgcc.assembler.general.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -329,12 +330,12 @@
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.assembler.general.IncludePaths>
<armgcc.preprocessingassembler.general.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -359,6 +360,7 @@
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.preprocessingassembler.general.IncludePaths>
@ -381,8 +383,6 @@
</armgcc.compiler.symbols.DefSymbols>
<armgcc.compiler.directories.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -407,6 +407,8 @@
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.compiler.directories.IncludePaths>
<armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
@ -432,8 +434,6 @@
<armgcc.linker.miscellaneous.LinkerFlags>-Tsame51j19a_flash.ld -std=gnu99 -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mfp16-format=ieee</armgcc.linker.miscellaneous.LinkerFlags>
<armgcc.assembler.general.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -458,13 +458,13 @@
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.assembler.general.IncludePaths>
<armgcc.assembler.debugging.DebugLevel>Default (-g)</armgcc.assembler.debugging.DebugLevel>
<armgcc.preprocessingassembler.general.IncludePaths>
<ListValues>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
<Value>../Config</Value>
<Value>../</Value>
<Value>../examples</Value>
@ -489,6 +489,8 @@
<Value>../hpl/tc</Value>
<Value>../hpl/tcc</Value>
<Value>../hri</Value>
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
</ListValues>
</armgcc.preprocessingassembler.general.IncludePaths>
<armgcc.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcc.preprocessingassembler.debugging.DebugLevel>

41
2_Motor_Master/Motor_Master/Motor_Master/configuration.h
View File

@ -18,24 +18,6 @@
#include "hpl_sercom_config.h"
#include "ADS1299.h"
#include "hpl_spi_m_dma.h"
// ----------------------------------------------------------------------
// ADC DMA Initialization
// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
// ----------------------------------------------------------------------
#define CONF_ADC_0_ADC_RES_READY_CHANNEL 4U
#define CONF_ADC_1_ADC_RES_READY_CHANNEL 5U
#define CONF_ADC_0_SEQUENCER_CHANNEL 6U
#define CONF_ADC_1_SEQUENCER_CHANNEL 7U
const uint32_t adc0_seq_regs[4] = {0};
const uint32_t adc1_seq_regs[4] = {0x0089, 0x0088, 0x0087, 0x0086}; /* Differential */
//const uint32_t adc1_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808}; /* Single Ended */
volatile int16_t adc0_res[4] = {0};
volatile int16_t adc1_res[4] = {0};
struct _dma_resource *adc_sram_dma_resource;
struct _dma_resource *adc_dmac_sequence_resource;
// ----------------------------------------------------------------------
// PWM Timer Initialization
@ -90,6 +72,27 @@ static void configure_tcc_pwm(void)
}
// ----------------------------------------------------------------------
// ADC DMA Initialization
// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
// ----------------------------------------------------------------------
//#define CONF_ADC_0_ADC_RES_READY_CHANNEL 4U
#define CONF_ADC_1_ADC_RES_READY_CHANNEL 3U
//#define CONF_ADC_0_SEQUENCER_CHANNEL 6U
#define CONF_ADC_1_SEQUENCER_CHANNEL 4U
const uint32_t adc0_seq_regs[4] = {0};
const uint32_t adc1_seq_regs[4] = {0x0089, 0x0088, 0x0087, 0x0086}; /* Differential */
//const uint32_t adc1_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808}; /* Single Ended */
volatile int16_t adc0_res[4] = {0};
volatile int16_t adc1_res[4] = {0};
struct _dma_resource *adc_sram_dma_resource;
struct _dma_resource *adc_dmac_sequence_resource;
static void adc_dmac_sequence_init()
{
/* Configure the DMAC source address, destination address,
@ -192,7 +195,7 @@ static void spi_master_init_dma_descriptors()
//
#define CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL 2U
#define CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL 8U
#define CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL 5U

3
2_Motor_Master/Motor_Master/Motor_Master/driver_init.c
View File

@ -166,6 +166,9 @@ void EVENT_SYSTEM_0_init(void)
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_4, CONF_GCLK_EVSYS_CHANNEL_4_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_5, CONF_GCLK_EVSYS_CHANNEL_5_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_6, CONF_GCLK_EVSYS_CHANNEL_6_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_7, CONF_GCLK_EVSYS_CHANNEL_7_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_8, CONF_GCLK_EVSYS_CHANNEL_8_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_11, CONF_GCLK_EVSYS_CHANNEL_11_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);

10
2_Motor_Master/Motor_Master/Motor_Master/hpl/tc/tc_lite.c
View File

@ -60,7 +60,7 @@ int8_t TIMER_0_init()
| 0 << TC_CTRLA_PRESCSYNC_Pos /* Prescaler and Counter Synchronization: 0 */
| 0 << TC_CTRLA_ONDEMAND_Pos /* Clock On Demand: disabled */
| 0 << TC_CTRLA_RUNSTDBY_Pos /* Run in Standby: disabled */
| 7 << TC_CTRLA_PRESCALER_Pos /* Setting: 7 */
| 3 << TC_CTRLA_PRESCALER_Pos /* Setting: 3 */
| 0x1 << TC_CTRLA_MODE_Pos); /* Operating Mode: 0x1 */
hri_tc_write_CTRLB_reg(TC0,
@ -76,13 +76,13 @@ int8_t TIMER_0_init()
// hri_tc_write_DBGCTRL_reg(TC0,0); /* Run in debug: 0 */
hri_tccount8_write_CC_reg(TC0, 0, 0x75); /* Compare/Capture Value: 0x75 */
hri_tccount8_write_CC_reg(TC0, 0, 0xa); /* Compare/Capture Value: 0xa */
hri_tccount8_write_CC_reg(TC0, 1, 0xb4); /* Compare/Capture Value: 0xb4 */
hri_tccount8_write_CC_reg(TC0, 1, 0x3c); /* Compare/Capture Value: 0x3c */
// hri_tccount8_write_COUNT_reg(TC0,0x0); /* Counter Value: 0x0 */
hri_tc_write_PER_reg(TC0, 0xff); /* Period Value: 0xff */
hri_tc_write_PER_reg(TC0, 0xfa); /* Period Value: 0xfa */
hri_tc_write_EVCTRL_reg(TC0,
1 << TC_EVCTRL_MCEO0_Pos /* Match or Capture Channel 0 Event Output Enable: enabled */
@ -96,7 +96,7 @@ int8_t TIMER_0_init()
0 << TC_INTENSET_MC0_Pos /* Match or Capture Channel 0 Interrupt Enable: disabled */
| 1 << TC_INTENSET_MC1_Pos /* Match or Capture Channel 1 Interrupt Enable: enabled */
| 0 << TC_INTENSET_ERR_Pos /* Error Interrupt Enable: disabled */
| 0 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: disabled */
| 1 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: enabled */
hri_tc_write_CTRLA_ENABLE_bit(TC0, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */

14
2_Motor_Master/Motor_Master/Motor_Master/interrupts.h
View File

@ -19,6 +19,12 @@ void TC0_Handler( void ){
if (TC0->COUNT8.INTFLAG.bit.OVF && TC0->COUNT8.INTENSET.bit.OVF)
{
TC0->COUNT8.INTFLAG.bit.OVF = 0x01;
if ((ecat_state == wait2)|(ecat_state == wait))
{
ecat_state= write_fifo;
run_ECAT =true;
}
Motor1.timerflags.motor_telemetry_flag = true;
}
if (TC0->COUNT8.INTFLAG.bit.MC0 && TC0->COUNT8.INTENSET.bit.MC0)
{
@ -27,12 +33,8 @@ void TC0_Handler( void ){
if (TC0->COUNT8.INTFLAG.bit.MC1 && TC0->COUNT8.INTENSET.bit.MC1)
{
TC0->COUNT8.INTFLAG.bit.MC1 = 0x01;
if ((ecat_state == wait2)|(ecat_state == wait))
{
ecat_state= write_fifo;
run_ECAT =true;
}
Motor1.timerflags.motor_telemetry_flag = true;
DMAC->Channel[7].CHCTRLB.bit.CMD = 0x02;
}
}

20
2_Motor_Master/Motor_Master/Motor_Master/main.c
View File

@ -183,13 +183,18 @@ int main(void)
__enable_irq();
ADS1299_START();
delay_us(20);
/* ADS Result Ready Interrupt, active low */
/* Enable Reception */
/* Enable Reception
* Enable RX channels at startup, Linked to itself so never ends
*/
_dma_enable_transaction(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, false);
_dma_enable_transaction(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, false);
/* Clear Exint Flag */
EIC->INTFLAG.bit.EXTINT = (1<<2);
ext_irq_register(GPIO_PIN(ADS_DATA_RDY), ADS1299_dataReadyISR);
enable_NVIC_IRQ();
@ -206,7 +211,7 @@ int main(void)
if (DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLA.bit.ENABLE)
{
/* Resume */
DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLB.bit.CMD = 0x02;
//DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLB.bit.CMD = 0x02;
}
else {
/* Enable */
@ -246,16 +251,15 @@ int main(void)
ADS1299.data_ReadyFlag = false;
//PORT->Group[0].OUTCLR.reg = (1<<GPIO_PIN(SPI2_SS));
if (DMAC->Channel[8].CHCTRLA.bit.ENABLE)
if (DMAC->Channel[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL].CHCTRLA.bit.ENABLE)
{
/* Resume */
DMAC->Channel[8].CHCTRLB.bit.CMD = 0x02;
//DMAC->Channel[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL].CHCTRLB.bit.CMD = 0x02;
volatile int x = 0;
}
else {
//DMAC->Channel[2].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
} else {
DMAC->Channel[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
/* Enable */
DMAC->Channel[8].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
//DMAC->Channel[8].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
}

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Twincat/MotorData/.vs/MotorData/v15/.suo
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