changes made with edmundo
This commit is contained in:
Nicolas Trimborn
@@ -50,7 +50,6 @@
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/quad_spi_dma.rst"/>
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||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_dma.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_sync.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/timer.rst"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_custom_logic.h"/>
|
||||
@@ -158,7 +157,6 @@
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_pwm.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_timer.h"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
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||||
@@ -177,7 +175,6 @@
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<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_pwm.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_dma.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_sync.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_timer.c"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc_base.h"/>
|
||||
@@ -200,8 +197,6 @@
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/qspi/hpl_qspi.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc.c"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc_base.h"/>
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||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.c"/>
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||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.h"/>
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<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.c"/>
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@@ -221,7 +216,6 @@
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_qspi_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
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||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tc_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tcc_config.h"/>
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<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
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||||
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
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@@ -236,7 +236,7 @@ drivers:
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functionality: System
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api: HAL:HPL:DMAC
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configuration:
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dmac_beatsize_0: 8-bit bus transfer
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dmac_beatsize_0: 32-bit bus transfer
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dmac_beatsize_1: 16-bit bus transfer
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dmac_beatsize_10: 8-bit bus transfer
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dmac_beatsize_11: 8-bit bus transfer
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@@ -259,7 +259,7 @@ drivers:
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dmac_beatsize_27: 8-bit bus transfer
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dmac_beatsize_28: 8-bit bus transfer
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dmac_beatsize_29: 8-bit bus transfer
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dmac_beatsize_3: 8-bit bus transfer
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dmac_beatsize_3: 32-bit bus transfer
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dmac_beatsize_30: 8-bit bus transfer
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dmac_beatsize_31: 8-bit bus transfer
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dmac_beatsize_4: 8-bit bus transfer
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@@ -558,9 +558,9 @@ drivers:
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dmac_lvl_8: Channel priority 0
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dmac_lvl_9: Channel priority 0
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dmac_lvlen0: true
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dmac_lvlen1: true
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dmac_lvlen2: true
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dmac_lvlen3: true
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dmac_lvlen1: false
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dmac_lvlen2: false
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dmac_lvlen3: false
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dmac_lvlpri0: 0
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dmac_lvlpri1: 0
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dmac_lvlpri2: 0
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@@ -923,7 +923,7 @@ drivers:
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api: HAL:Driver:Event_system
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configuration:
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evsys_channel_0: No channel output selected
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evsys_channel_1: No channel output selected
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evsys_channel_1: Channel 3
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evsys_channel_10: No channel output selected
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evsys_channel_11: No channel output selected
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evsys_channel_12: No channel output selected
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@@ -1008,7 +1008,7 @@ drivers:
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evsys_channel_setting_27: false
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evsys_channel_setting_28: false
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evsys_channel_setting_29: false
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evsys_channel_setting_3: false
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evsys_channel_setting_3: true
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evsys_channel_setting_30: false
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evsys_channel_setting_31: false
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evsys_channel_setting_4: false
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@@ -1136,7 +1136,7 @@ drivers:
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evsys_evgen_27: No event generator
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evsys_evgen_28: No event generator
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evsys_evgen_29: No event generator
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evsys_evgen_3: No event generator
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evsys_evgen_3: TC0 match/capture 0
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evsys_evgen_30: No event generator
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evsys_evgen_31: No event generator
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evsys_evgen_4: No event generator
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@@ -1232,7 +1232,7 @@ drivers:
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evsys_path_27: Synchronous path
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evsys_path_28: Synchronous path
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evsys_path_29: Synchronous path
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evsys_path_3: Synchronous path
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evsys_path_3: Asynchronous path
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evsys_path_30: Synchronous path
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evsys_path_31: Synchronous path
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evsys_path_4: Synchronous path
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@@ -1642,7 +1642,7 @@ drivers:
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functionality: System
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api: HAL:HPL:PORT
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configuration:
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enable_port_input_event_0: false
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enable_port_input_event_0: true
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enable_port_input_event_1: false
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enable_port_input_event_2: false
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enable_port_input_event_3: false
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@@ -1658,15 +1658,15 @@ drivers:
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porta_input_event_enable_1: false
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porta_input_event_enable_2: false
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porta_input_event_enable_3: false
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portb_event_action_0: Output register of pin will be set to level of event
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portb_event_action_0: Clear output register of pin on event
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portb_event_action_1: Output register of pin will be set to level of event
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portb_event_action_2: Output register of pin will be set to level of event
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portb_event_action_3: Output register of pin will be set to level of event
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portb_event_pin_identifier_0: 0
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portb_event_pin_identifier_0: 22
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portb_event_pin_identifier_1: 0
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portb_event_pin_identifier_2: 0
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portb_event_pin_identifier_3: 0
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portb_input_event_enable_0: false
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portb_input_event_enable_0: true
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portb_input_event_enable_1: false
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portb_input_event_enable_2: false
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portb_input_event_enable_3: false
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@@ -1882,24 +1882,53 @@ drivers:
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slow_gclk_selection: Generic clock generator 3
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TIMER_0:
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user_label: TIMER_0
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definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::TC0::driver_config_definition::Timer::HAL:Driver:Timer
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definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::TC0::driver_config_definition::16-bit.Counter.Mode::Lite:TC:Timer
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functionality: Timer
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api: HAL:Driver:Timer
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api: Lite:TC:Timer
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configuration:
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tc_arch_dbgrun: false
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tc_arch_evact: Event action disabled
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tc_arch_mceo0: false
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tc_arch_mceo1: false
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tc_arch_ondemand: false
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tc_arch_ovfeo: false
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tc_arch_presync: Reload or reset counter on next GCLK
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tc_arch_runstdby: false
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tc_arch_tcei: false
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tc_arch_tcinv: false
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timer_advanced_configuration: true
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timer_event_control: false
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timer_prescaler: Divide by 64
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timer_tick: 1000
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cc_cc0: 1874
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cc_cc1: 0
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cc_control: true
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count_control: false
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count_count: 0
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ctrla_alock: false
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ctrla_capten0: false
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ctrla_capten1: false
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ctrla_captmode0: DEFAULT
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ctrla_captmode1: DEFAULT
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ctrla_control: true
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ctrla_copen0: false
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ctrla_copen1: false
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ctrla_enable: true
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ctrla_mode: 0
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ctrla_ondemand: false
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ctrla_prescaler: DIV64
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ctrla_prescsync: GCLK
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ctrla_runstdby: false
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ctrlbset_cmd: NONE
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ctrlbset_control: false
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ctrlbset_dir: false
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ctrlbset_lupd: false
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ctrlbset_oneshot: false
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ctrlc_inven0: false
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ctrlc_inven1: false
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dbgctrl_control: false
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dbgctrl_dbgrun: false
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drvctrl_control: false
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evctrl_control: true
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evctrl_evact: 'OFF'
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evctrl_mceo0: true
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evctrl_mceo1: false
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evctrl_ovfeo: false
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evctrl_tcei: false
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evctrl_tcinv: false
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intenset_control: true
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intenset_err: false
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intenset_mc0: true
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intenset_mc1: false
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intenset_ovf: false
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wave_control: true
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wave_wavegen: MFRQ
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optional_signals: []
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variant: null
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clocks:
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@@ -36,7 +36,7 @@
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// <i> Indicates whether Priority Level 1 is enabled or not
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// <id> dmac_lvlen1
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#ifndef CONF_DMAC_LVLEN1
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#define CONF_DMAC_LVLEN1 1
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#define CONF_DMAC_LVLEN1 0
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#endif
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// <o> Level 1 Round-Robin Arbitration
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@@ -57,7 +57,7 @@
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// <i> Indicates whether Priority Level 2 is enabled or not
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// <id> dmac_lvlen2
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#ifndef CONF_DMAC_LVLEN2
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#define CONF_DMAC_LVLEN2 1
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#define CONF_DMAC_LVLEN2 0
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#endif
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// <o> Level 2 Round-Robin Arbitration
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@@ -78,7 +78,7 @@
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// <i> Indicates whether Priority Level 3 is enabled or not
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// <id> dmac_lvlen3
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#ifndef CONF_DMAC_LVLEN3
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#define CONF_DMAC_LVLEN3 1
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#define CONF_DMAC_LVLEN3 0
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#endif
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// <o> Level 3 Round-Robin Arbitration
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@@ -301,7 +301,7 @@
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// <i> Defines the size of one beat
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// <id> dmac_beatsize_0
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#ifndef CONF_DMAC_BEATSIZE_0
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#define CONF_DMAC_BEATSIZE_0 0
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#define CONF_DMAC_BEATSIZE_0 2
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#endif
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// <o> Block Action
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@@ -973,7 +973,7 @@
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// <i> Defines the size of one beat
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// <id> dmac_beatsize_3
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#ifndef CONF_DMAC_BEATSIZE_3
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#define CONF_DMAC_BEATSIZE_3 0
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#define CONF_DMAC_BEATSIZE_3 2
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#endif
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// <o> Block Action
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@@ -550,7 +550,7 @@
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// <e> Channel 3 settings
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// <id> evsys_channel_setting_3
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#ifndef CONF_EVSYS_CHANNEL_SETTINGS_3
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#define CONF_EVSYS_CHANNEL_SETTINGS_3 0
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#define CONF_EVSYS_CHANNEL_SETTINGS_3 1
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#endif
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// <y> Edge detection
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@@ -571,7 +571,7 @@
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// <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
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// <id> evsys_path_3
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#ifndef CONF_PATH_3
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#define CONF_PATH_3 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
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#define CONF_PATH_3 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
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#endif
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// <o> Event generator
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||||
@@ -695,7 +695,7 @@
|
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// <0x77=>CCL LUT output 3
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// <id> evsys_evgen_3
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||||
#ifndef CONF_EVGEN_3
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#define CONF_EVGEN_3 0
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#define CONF_EVGEN_3 74
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#endif
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||||
// <q> Overrun channel interrupt
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||||
@@ -5880,7 +5880,7 @@
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||||
// <id> evsys_channel_1
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||||
// <i> Indicates which channel is chosen for user
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||||
#ifndef CONF_CHANNEL_1
|
||||
#define CONF_CHANNEL_1 0
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#define CONF_CHANNEL_1 4
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||||
#endif
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||||
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||||
// <o> Channel selection for PORT event 1
|
||||
|
||||
@@ -7,7 +7,7 @@
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||||
// <e> PORT Input Event 0 configuration
|
||||
// <id> enable_port_input_event_0
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_0
|
||||
#define CONF_PORT_EVCTRL_PORT_0 0
|
||||
#define CONF_PORT_EVCTRL_PORT_0 1
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 0 configuration on PORT A
|
||||
@@ -44,14 +44,14 @@
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
|
||||
// <id> portb_input_event_enable_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_0 0x1
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_0
|
||||
#define CONF_PORTB_EVCTRL_PID_0 0x0
|
||||
#define CONF_PORTB_EVCTRL_PID_0 0x16
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Action
|
||||
@@ -62,7 +62,7 @@
|
||||
// <i> These bits define the event action the PORT B will perform on event input 0
|
||||
// <id> portb_event_action_0
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_0
|
||||
#define CONF_PORTB_EVCTRL_EVACT_0 0
|
||||
#define CONF_PORTB_EVCTRL_EVACT_0 2
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
@@ -1,180 +0,0 @@
|
||||
/* Auto-generated config file hpl_tc_config.h */
|
||||
#ifndef HPL_TC_CONFIG_H
|
||||
#define HPL_TC_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#ifndef CONF_TC0_ENABLE
|
||||
#define CONF_TC0_ENABLE 1
|
||||
#endif
|
||||
|
||||
#include "peripheral_clk_config.h"
|
||||
|
||||
// <h> Basic configuration
|
||||
|
||||
// <o> Prescaler
|
||||
// <0x0=> No division
|
||||
// <0x1=> Divide by 2
|
||||
// <0x2=> Divide by 4
|
||||
// <0x3=> Divide by 8
|
||||
// <0x4=> Divide by 16
|
||||
// <0x5=> Divide by 64
|
||||
// <0x6=> Divide by 256
|
||||
// <0x7=> Divide by 1024
|
||||
// <i> This defines the prescaler value
|
||||
// <id> timer_prescaler
|
||||
#ifndef CONF_TC0_PRESCALER
|
||||
#define CONF_TC0_PRESCALER 0x5
|
||||
#endif
|
||||
|
||||
// <o> Length of one timer tick in uS <0-4294967295>
|
||||
// <id> timer_tick
|
||||
#ifndef CONF_TC0_TIMER_TICK
|
||||
#define CONF_TC0_TIMER_TICK 1000
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <e> Advanced configuration
|
||||
// <id> timer_advanced_configuration
|
||||
#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE
|
||||
#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <y> Prescaler and Counter Synchronization Selection
|
||||
// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
|
||||
// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
|
||||
// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
|
||||
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
|
||||
// <id> tc_arch_presync
|
||||
#ifndef CONF_TC0_PRESCSYNC
|
||||
#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
|
||||
#endif
|
||||
|
||||
// <q> Run in standby
|
||||
// <i> Indicates whether the module will continue to run in standby sleep mode
|
||||
// <id> tc_arch_runstdby
|
||||
#ifndef CONF_TC0_RUNSTDBY
|
||||
#define CONF_TC0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Run in debug mode
|
||||
// <i> Indicates whether the module will run in debug mode
|
||||
// <id> tc_arch_dbgrun
|
||||
#ifndef CONF_TC0_DBGRUN
|
||||
#define CONF_TC0_DBGRUN 0
|
||||
#endif
|
||||
|
||||
// <q> Run on demand
|
||||
// <i> Run if requested by some other peripheral in the device
|
||||
// <id> tc_arch_ondemand
|
||||
#ifndef CONF_TC0_ONDEMAND
|
||||
#define CONF_TC0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Event control
|
||||
// <id> timer_event_control
|
||||
#ifndef CONF_TC0_EVENT_CONTROL_ENABLE
|
||||
#define CONF_TC0_EVENT_CONTROL_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Event On Match or Capture on Channel 0
|
||||
// <i> Enable output of event on timer tick
|
||||
// <id> tc_arch_mceo0
|
||||
#ifndef CONF_TC0_MCEO0
|
||||
#define CONF_TC0_MCEO0 0
|
||||
#endif
|
||||
|
||||
// <q> Output Event On Match or Capture on Channel 1
|
||||
// <i> Enable output of event on timer tick
|
||||
// <id> tc_arch_mceo1
|
||||
#ifndef CONF_TC0_MCEO1
|
||||
#define CONF_TC0_MCEO1 0
|
||||
#endif
|
||||
|
||||
// <q> Output Event On Timer Tick
|
||||
// <i> Enable output of event on timer tick
|
||||
// <id> tc_arch_ovfeo
|
||||
#ifndef CONF_TC0_OVFEO
|
||||
#define CONF_TC0_OVFEO 0
|
||||
#endif
|
||||
|
||||
// <q> Event Input
|
||||
// <i> Enable asynchronous input events
|
||||
// <id> tc_arch_tcei
|
||||
#ifndef CONF_TC0_TCEI
|
||||
#define CONF_TC0_TCEI 0
|
||||
#endif
|
||||
|
||||
// <q> Inverted Event Input
|
||||
// <i> Invert the asynchronous input events
|
||||
// <id> tc_arch_tcinv
|
||||
#ifndef CONF_TC0_TCINV
|
||||
#define CONF_TC0_TCINV 0
|
||||
#endif
|
||||
|
||||
// <o> Event action
|
||||
// <0=> Event action disabled
|
||||
// <1=> Start, restart or re-trigger TC on event
|
||||
// <2=> Count on event
|
||||
// <3=> Start on event
|
||||
// <4=> Time stamp capture
|
||||
// <5=> Period captured in CC0, pulse width in CC1
|
||||
// <6=> Period captured in CC1, pulse width in CC0
|
||||
// <7=> Pulse width capture
|
||||
// <i> Event which will be performed on an event
|
||||
//<id> tc_arch_evact
|
||||
#ifndef CONF_TC0_EVACT
|
||||
#define CONF_TC0_EVACT 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// Default values which the driver needs in order to work correctly
|
||||
|
||||
// Mode set to 32-bit
|
||||
#ifndef CONF_TC0_MODE
|
||||
#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val
|
||||
#endif
|
||||
|
||||
// CC 1 register set to 0
|
||||
#ifndef CONF_TC0_CC1
|
||||
#define CONF_TC0_CC1 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_TC0_ALOCK
|
||||
#define CONF_TC0_ALOCK 0
|
||||
#endif
|
||||
|
||||
// Not used in 32-bit mode
|
||||
#define CONF_TC0_PER 0
|
||||
|
||||
// Calculating correct top value based on requested tick interval.
|
||||
#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER)
|
||||
|
||||
// Prescaler set to 64
|
||||
#if CONF_TC0_PRESCALER > 0x4
|
||||
#undef CONF_TC0_PRESCALE
|
||||
#define CONF_TC0_PRESCALE 64
|
||||
#endif
|
||||
|
||||
// Prescaler set to 256
|
||||
#if CONF_TC0_PRESCALER > 0x5
|
||||
#undef CONF_TC0_PRESCALE
|
||||
#define CONF_TC0_PRESCALE 256
|
||||
#endif
|
||||
|
||||
// Prescaler set to 1024
|
||||
#if CONF_TC0_PRESCALER > 0x6
|
||||
#undef CONF_TC0_PRESCALE
|
||||
#define CONF_TC0_PRESCALE 1024
|
||||
#endif
|
||||
|
||||
#ifndef CONF_TC0_CC0
|
||||
#define CONF_TC0_CC0 \
|
||||
(uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE)))
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_TC_CONFIG_H
|
||||
@@ -163,7 +163,8 @@ static void update_telemetry(void)
|
||||
//*M1_Mode = 0;
|
||||
|
||||
/* Motor 1 */
|
||||
*M1_Status = Motor1.motor_state.currentstate;
|
||||
*M1_Status = Motor1.motor_state.fault;
|
||||
*M1_Mode = Motor1.motor_state.currentstate;
|
||||
*M1_Joint_rel_position = Motor1.motor_status.Num_Steps;
|
||||
*M1_Joint_abs_position = Motor1.motor_status.abs_position;
|
||||
//*M1_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1])+1);
|
||||
@@ -176,7 +177,8 @@ static void update_telemetry(void)
|
||||
*M1_Motor_speed = (int16_t)Motor1.motor_status.calc_rpm;
|
||||
//*M1_Joint_abs_position = Motor1.motor_status.actualDirection;
|
||||
/* Motor 2 */
|
||||
*M2_Status = Motor2.motor_state.currentstate;
|
||||
*M2_Status = Motor2.motor_state.fault;
|
||||
*M2_Mode = Motor2.motor_state.currentstate;
|
||||
*M2_Joint_rel_position = Motor2.motor_status.Num_Steps;
|
||||
*M2_Joint_abs_position = Motor2.motor_status.abs_position;
|
||||
//*M1_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1])+1);
|
||||
|
||||
@@ -163,7 +163,8 @@ static void update_telemetry(void)
|
||||
//*M1_Mode = 0;
|
||||
|
||||
/* Motor 1 */
|
||||
*M1_Status = Motor1.motor_state.currentstate;
|
||||
*M1_Status = Motor1.motor_state.fault;
|
||||
*M1_Mode = Motor1.motor_state.currentstate;
|
||||
*M1_Joint_rel_position = Motor1.motor_status.Num_Steps;
|
||||
*M1_Joint_abs_position = Motor1.motor_status.abs_position;
|
||||
//*M1_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1])+1);
|
||||
@@ -176,7 +177,8 @@ static void update_telemetry(void)
|
||||
*M1_Motor_speed = (int16_t)Motor1.motor_status.calc_rpm;
|
||||
//*M1_Joint_abs_position = Motor1.motor_status.actualDirection;
|
||||
/* Motor 2 */
|
||||
*M2_Status = Motor2.motor_state.currentstate;
|
||||
*M2_Status = Motor2.motor_state.fault;
|
||||
*M2_Mode = Motor2.motor_state.currentstate;
|
||||
*M2_Joint_rel_position = Motor2.motor_status.Num_Steps;
|
||||
*M2_Joint_abs_position = Motor2.motor_status.abs_position;
|
||||
//*M1_Motor_speed = (((int16_t *)&QSPI_tx_buffer[1])+1);
|
||||
|
||||
@@ -150,14 +150,13 @@
|
||||
<AcmeProjectActionInfo Action="File" Source="hri/hri_usb_e51.h" IsConfig="false" Hash="x6M7vYgNCS2oECqykr5+yw" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hri/hri_wdt_e51.h" IsConfig="false" Hash="o9Rg/hyuMzwOCphVc7uG1w" />
|
||||
<AcmeProjectActionInfo Action="File" Source="main.c" IsConfig="false" Hash="k0AH7j+BrmdFhBPzCCMptA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="Q3o1x3vWYELO1L6mRVKUIA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="hkPygmC76Qup+RNNN/cLrA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="U0r+mqNyUZcAht0NLNN5yg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="NyJtBqCuH2RlTy0iltvcfg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="atmel_start_pins.h" IsConfig="false" Hash="q332kmNEqTBha3F9F86pCg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="HwCfGc+NYMxlXMiyssgrQQ" />
|
||||
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.c" IsConfig="false" Hash="3GCFvpeDmd50lR4mT9TaMQ" />
|
||||
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="yuNriNBbj5kyY6X2I3Qu+A" />
|
||||
<AcmeProjectActionInfo Action="File" Source="examples/driver_examples.c" IsConfig="false" Hash="oDU1dTFRd5Wh3Z/tIEnuoA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_adc_sync.h" IsConfig="false" Hash="ez1X5T9kpYwT+1+5x4Pxqg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_pwm.h" IsConfig="false" Hash="RXcBZcci/7vXKRJKNIq/Kw" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hal/include/hal_timer.h" IsConfig="false" Hash="5pZVthtMl40VMvofOld2ng" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_adc_async.h" IsConfig="false" Hash="kKbVmqgGDUkuWZYErBwgVA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_adc_sync.h" IsConfig="false" Hash="dCWrizZn0RtcCM73jZ/k6A" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hal/include/hpl_missing_features.h" IsConfig="false" Hash="XsAvpgfutzkw0Y5SydYFaw" />
|
||||
@@ -176,7 +175,6 @@
|
||||
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_pwm.c" IsConfig="false" Hash="ZFJmg7/0rhQ6JMKyxuk9kw" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_spi_m_dma.c" IsConfig="false" Hash="KMrinO/3xx7qWxy2PsJB7g" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_spi_m_sync.c" IsConfig="false" Hash="Q0IudnTEWeoIkfQIoYIqxA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hal/src/hal_timer.c" IsConfig="false" Hash="F2MrEXhHq4umI9xpONnlGg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hal/utils/include/parts.h" IsConfig="false" Hash="zv0TWdxXtsu5Y1B88PQgiA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/adc/hpl_adc.c" IsConfig="false" Hash="zpNRk8aViOSavv+cy054MA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/adc/hpl_adc_base.h" IsConfig="false" Hash="19A6ERNtsVVhqvnpGbR3Lg" />
|
||||
@@ -199,10 +197,8 @@
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/qspi/hpl_qspi.c" IsConfig="false" Hash="woXbbCFkSWus6J14PHJlHw" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/ramecc/hpl_ramecc.c" IsConfig="false" Hash="pMdmwVWBg16VG8HOwA3DPw" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/sercom/hpl_sercom.c" IsConfig="false" Hash="hcMq5dgdlyb9xXr1YOQnMQ" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/tc/hpl_tc.c" IsConfig="false" Hash="CwAdaARrfhpCcFm3bk4PtA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/tc/hpl_tc_base.h" IsConfig="false" Hash="gjj5IyaZPy6sUReifzS1GQ" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.c" IsConfig="false" Hash="035J+hUWZyoUFfzslZgZwg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.h" IsConfig="false" Hash="837i/ZOZgAj+upvb6cSvgg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.c" IsConfig="false" Hash="TvX0gjbe0pQlKc43XVzIRQ" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.h" IsConfig="false" Hash="zTBTKMmLh2GsbqmbMsUX8g" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/tcc/hpl_tcc.c" IsConfig="false" Hash="DC3UZSTUv1CDjekNxClhVg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="hpl/tcc/hpl_tcc.h" IsConfig="false" Hash="rdWkAK12qkOYV59tWwzy6A" />
|
||||
<AcmeProjectActionInfo Action="File" Source="atmel_start.h" IsConfig="false" Hash="9RBG5E2ViQiSP2Gn4/FGpA" />
|
||||
@@ -210,17 +206,16 @@
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="IJeJ3sDxG9f3mmsLxoMLlA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="InEybPQe1lA+oW1HFMWYLg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="ZoER5eKK8H7JWexdQhfwww" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="S8xJxIaG6pS6BEvDgxKh9w" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="/3bNiu/UgpvPbmvfRA+w3g" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="UCqlM36hOu88a+CHb/vycw" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Uje5LXAS+nQpGryt9t0fYA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="rMTNR+5FXtu+wfT1NbfRRA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="hX4+5+KlqrwduLW2+CPKfg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_qspi_config.h" IsConfig="true" Hash="CwZ360eeEYs7T9SYFSvDug" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="NOEuutypdbfpBKOWCPUPuA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_tc_config.h" IsConfig="true" Hash="T93Kr6C+WDuufZob89oPeg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="s/tLl+lpMPQWNUrjuAL0rQ" />
|
||||
</AcmeActionInfos>
|
||||
@@ -579,9 +574,6 @@
|
||||
<Compile Include="Config\hpl_tcc_config.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="Config\hpl_tc_config.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="Config\peripheral_clk_config.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
@@ -663,9 +655,6 @@
|
||||
<Compile Include="hal\include\hal_spi_m_sync.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hal_timer.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\include\hpl_adc_async.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
@@ -822,9 +811,6 @@
|
||||
<Compile Include="hal\src\hal_spi_m_sync.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\src\hal_timer.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hal\utils\include\compiler.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
@@ -936,12 +922,6 @@
|
||||
<Compile Include="hpl\tcc\hpl_tcc.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\tc\hpl_tc.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\tc\hpl_tc_base.h">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
<Compile Include="hpl\tc\tc_lite.c">
|
||||
<SubType>compile</SubType>
|
||||
</Compile>
|
||||
@@ -1142,9 +1122,6 @@
|
||||
<None Include="hal\documentation\spi_master_sync.rst">
|
||||
<SubType>compile</SubType>
|
||||
</None>
|
||||
<None Include="hal\documentation\timer.rst">
|
||||
<SubType>compile</SubType>
|
||||
</None>
|
||||
<None Include="hpl\doc_lite\tc.rst">
|
||||
<SubType>compile</SubType>
|
||||
</None>
|
||||
|
||||
@@ -38,7 +38,7 @@ void motor_StateMachine(BLDCMotor_t* const motor)
|
||||
motor->motor_state.currentstate = MOTOR_PVI_CTRL_STATE;
|
||||
break;
|
||||
case MOTOR_OPEN_LOOP_STATE:
|
||||
BLDC_runOpenLoop(motor, *M1_Desired_dc);
|
||||
BLDC_runOpenLoop(motor, 100);
|
||||
calculate_motor_speed(motor);
|
||||
motor->motor_state.previousstate = motor->motor_state.currentstate;
|
||||
break;
|
||||
@@ -77,6 +77,9 @@ void motor_StateMachine(BLDCMotor_t* const motor)
|
||||
if(motor->regulation_loop_count > 23) motor->regulation_loop_count = 0;
|
||||
else motor->regulation_loop_count++;
|
||||
break;
|
||||
case MOTOR_FAULT:
|
||||
disable_phases(motor);
|
||||
break;
|
||||
} //end switch (motor->motor_state.currentstate)
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
@@ -357,6 +360,12 @@ void calculate_motor_speed(BLDCMotor_t* const motor)
|
||||
}
|
||||
|
||||
|
||||
void disable_phases(BLDCMotor_t* const motor)
|
||||
{
|
||||
Tcc * tmp = (Tcc *)motor->motor_param->pwm_desc->device.hw;
|
||||
tmp->PATTBUF.reg = DISABLE_PATTERN;
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// pi current control
|
||||
//------------------------------------------------------------------------------
|
||||
@@ -509,7 +518,10 @@ void read_zero_current_offset_value(BLDCMotor_t *motor1, BLDCMotor_t *motor2)
|
||||
uint8_t samples = 32;
|
||||
uint8_t i;
|
||||
|
||||
// ------------------------- Motor 1 ---------------------------------
|
||||
// ------------------------------------------------------------------
|
||||
// Motor 1
|
||||
// -------------------------------------------------------------------
|
||||
|
||||
adc_sync_enable_channel(&ADC_1, 9);
|
||||
//adc_sync_enable_channel(&ADC_1, 0);
|
||||
|
||||
@@ -560,6 +572,17 @@ void read_zero_current_offset_value(BLDCMotor_t *motor1, BLDCMotor_t *motor2)
|
||||
adc_sync_enable_channel(&ADC_1, 7);
|
||||
//adc_sync_enable_channel(&ADC_1, 0);
|
||||
|
||||
if ((abs(motor1->Voffset_lsb.A) > MAX_CUR_SENSE_OFFSET) || (abs(motor1->Voffset_lsb.B) > MAX_CUR_SENSE_OFFSET))
|
||||
{
|
||||
motor1->motor_state.currentstate = MOTOR_FAULT;
|
||||
motor1->motor_state.fault = MOTOR_CURRENTS_SENSOR;
|
||||
|
||||
}
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// Motor 2
|
||||
// -------------------------------------------------------------------
|
||||
|
||||
phase_A_zero_current_offset_temp = 0;
|
||||
phase_B_zero_current_offset_temp = 0;
|
||||
|
||||
@@ -607,4 +630,9 @@ void read_zero_current_offset_value(BLDCMotor_t *motor1, BLDCMotor_t *motor2)
|
||||
motor2->Voffset_lsb.B = phase_B_zero_current_offset_temp/samples;
|
||||
adc_sync_disable_channel(&ADC_1, 6);
|
||||
//adc_sync_disable_channel(&ADC_1, 0);
|
||||
if ((abs(motor2->Voffset_lsb.A) > MAX_CUR_SENSE_OFFSET) || (abs(motor2->Voffset_lsb.B) > MAX_CUR_SENSE_OFFSET))
|
||||
{
|
||||
motor2->motor_state.currentstate = MOTOR_FAULT;
|
||||
motor2->motor_state.fault = MOTOR_CURRENTS_SENSOR;
|
||||
}
|
||||
}
|
||||
@@ -35,7 +35,7 @@
|
||||
// ----------------------------------------------------------------------
|
||||
// ADC Parameters
|
||||
// ----------------------------------------------------------------------
|
||||
#define ADC_VOLTAGE_REFERENCE (3.3f)
|
||||
#define ADC_VOLTAGE_REFERENCE (3.0f)
|
||||
#define ADC_RESOLUTION (12)
|
||||
#define ADC_MAX_COUNTS (1<<ADC_RESOLUTION)
|
||||
#define ADC_LSB_SIZE (ADC_VOLTAGE_REFERENCE/ADC_MAX_COUNTS)
|
||||
@@ -61,6 +61,7 @@
|
||||
#define DEVICE_SHUNT_CURRENT_A 2.5f // phase current(PEAK) [A]
|
||||
#define CURRENT_SENSOR_SENSITIVITY 0.4f //V/A
|
||||
#define ONEON_CURRENT_SENSOR_SENSITIVITY 2.5f //V/A
|
||||
#define MAX_CUR_SENSE_OFFSET 100
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// global variables
|
||||
@@ -84,6 +85,7 @@ void BldcInitStruct(BLDCMotor_t* const motor, BLDCMotor_param_t* constmotor_para
|
||||
void exec_commutation(BLDCMotor_t* const motor);
|
||||
void select_active_phase(BLDCMotor_t* const Motor);
|
||||
void calculate_motor_speed(BLDCMotor_t* const motor);
|
||||
void disable_phases(BLDCMotor_t* const motor);
|
||||
// ----------------------------------------------------------------------
|
||||
// Static Functions
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
@@ -146,6 +146,8 @@ inline void adc_sram_dmac_init()
|
||||
// ----------------------------------------------------------------------
|
||||
|
||||
#define MASTER_BUFFER_SIZE 64
|
||||
#define MASTER_BUFFER_SIZE_LONG MASTER_BUFFER_SIZE/4
|
||||
|
||||
/* DMA channel Descriptor */
|
||||
extern DmacDescriptor _descriptor_section[DMAC_CH_NUM];
|
||||
extern DmacDescriptor _write_back_section[DMAC_CH_NUM];
|
||||
@@ -160,6 +162,8 @@ void boardToBoardTransferInit(void)
|
||||
spi_m_dma_get_io_descriptor(&SPI_1_MSIF, &io);
|
||||
spi_m_dma_register_callback(&SPI_1_MSIF, SPI_M_DMA_CB_RX_DONE, b2bTransferComplete_cb);
|
||||
//SERCOM4->SPI.CTRLC.bit.DATA32B = true;
|
||||
SERCOM1->SPI.CTRLC.bit.ICSPACE = 5;
|
||||
SERCOM1->SPI.CTRLC.bit.DATA32B= true;
|
||||
gpio_set_pin_level(SPI1_CS, true);
|
||||
spi_m_dma_enable(&SPI_1_MSIF);
|
||||
}
|
||||
@@ -169,12 +173,12 @@ void init_spi_master_dma_descriptors()
|
||||
_dma_set_source_address(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE,
|
||||
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
|
||||
_dma_set_destination_address(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, &QSPI_tx_buffer[16]);
|
||||
_dma_set_data_amount(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, MASTER_BUFFER_SIZE);
|
||||
_dma_set_data_amount(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, MASTER_BUFFER_SIZE_LONG);
|
||||
|
||||
_dma_set_source_address(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, &QSPI_rx_buffer[16]);
|
||||
_dma_set_destination_address(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT,
|
||||
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
|
||||
_dma_set_data_amount(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, MASTER_BUFFER_SIZE);
|
||||
_dma_set_data_amount(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, MASTER_BUFFER_SIZE_LONG);
|
||||
|
||||
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE]);
|
||||
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT]);
|
||||
@@ -186,7 +190,7 @@ void init_spi_master_dma_descriptors()
|
||||
//resource_tx->dma_cb.transfer_done = b2bTransferComplete_cb;
|
||||
|
||||
/* Enable DMA transfer complete interrupt */
|
||||
//_dma_set_irq_state(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
|
||||
//_dma_set_irq_state(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, DMA_TRANSFER_COMPLETE_CB, true);
|
||||
|
||||
}
|
||||
|
||||
|
||||
@@ -15,7 +15,6 @@
|
||||
|
||||
struct spi_m_sync_descriptor SPI_2;
|
||||
struct spi_m_sync_descriptor SPI_3;
|
||||
struct timer_descriptor TIMER_0;
|
||||
|
||||
struct adc_sync_descriptor ADC_1;
|
||||
|
||||
@@ -163,6 +162,7 @@ void EVENT_SYSTEM_0_init(void)
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_1, CONF_GCLK_EVSYS_CHANNEL_1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_2, CONF_GCLK_EVSYS_CHANNEL_2_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_3, CONF_GCLK_EVSYS_CHANNEL_3_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);
|
||||
|
||||
@@ -561,17 +561,11 @@ void SPI_3_init(void)
|
||||
SPI_3_PORT_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Timer initialization function
|
||||
*
|
||||
* Enables Timer peripheral, clocks and initializes Timer driver
|
||||
*/
|
||||
static void TIMER_0_init(void)
|
||||
void TIMER_0_CLOCK_init(void)
|
||||
{
|
||||
hri_mclk_set_APBAMASK_TC0_bit(MCLK);
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
timer_init(&TIMER_0, TC0, _tc_get_timer());
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
}
|
||||
|
||||
void TC_SPEED_M1_CLOCK_init(void)
|
||||
@@ -761,7 +755,10 @@ void system_init(void)
|
||||
|
||||
SPI_3_init();
|
||||
|
||||
TIMER_0_CLOCK_init();
|
||||
|
||||
TIMER_0_init();
|
||||
|
||||
TC_SPEED_M1_CLOCK_init();
|
||||
|
||||
TC_SPEED_M1_init();
|
||||
|
||||
@@ -34,8 +34,7 @@ extern "C" {
|
||||
#include <hal_spi_m_dma.h>
|
||||
#include <hal_spi_m_sync.h>
|
||||
#include <hal_spi_m_sync.h>
|
||||
#include <hal_timer.h>
|
||||
#include <hpl_tc_base.h>
|
||||
#include <tc_lite.h>
|
||||
#include <tc_lite.h>
|
||||
#include <tc_lite.h>
|
||||
|
||||
@@ -52,7 +51,6 @@ extern struct qspi_dma_descriptor ECAT_QSPI;
|
||||
extern struct spi_m_dma_descriptor SPI_1_MSIF;
|
||||
extern struct spi_m_sync_descriptor SPI_2;
|
||||
extern struct spi_m_sync_descriptor SPI_3;
|
||||
extern struct timer_descriptor TIMER_0;
|
||||
|
||||
extern struct pwm_descriptor PWM_0;
|
||||
|
||||
@@ -82,6 +80,10 @@ void SPI_3_PORT_init(void);
|
||||
void SPI_3_CLOCK_init(void);
|
||||
void SPI_3_init(void);
|
||||
|
||||
void TIMER_0_CLOCK_init(void);
|
||||
|
||||
int8_t TIMER_0_init(void);
|
||||
|
||||
void TC_SPEED_M1_CLOCK_init(void);
|
||||
|
||||
int8_t TC_SPEED_M1_init(void);
|
||||
|
||||
@@ -145,33 +145,6 @@ void SPI_3_example(void)
|
||||
io_write(io, example_SPI_3, 12);
|
||||
}
|
||||
|
||||
static struct timer_task TIMER_0_task1, TIMER_0_task2;
|
||||
|
||||
/**
|
||||
* Example of using TIMER_0.
|
||||
*/
|
||||
static void TIMER_0_task1_cb(const struct timer_task *const timer_task)
|
||||
{
|
||||
}
|
||||
|
||||
static void TIMER_0_task2_cb(const struct timer_task *const timer_task)
|
||||
{
|
||||
}
|
||||
|
||||
void TIMER_0_example(void)
|
||||
{
|
||||
TIMER_0_task1.interval = 100;
|
||||
TIMER_0_task1.cb = TIMER_0_task1_cb;
|
||||
TIMER_0_task1.mode = TIMER_TASK_REPEAT;
|
||||
TIMER_0_task2.interval = 200;
|
||||
TIMER_0_task2.cb = TIMER_0_task2_cb;
|
||||
TIMER_0_task2.mode = TIMER_TASK_REPEAT;
|
||||
|
||||
timer_add_task(&TIMER_0, &TIMER_0_task1);
|
||||
timer_add_task(&TIMER_0, &TIMER_0_task2);
|
||||
timer_start(&TIMER_0);
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using PWM_0.
|
||||
*/
|
||||
|
||||
@@ -22,8 +22,6 @@ void ECAT_QSPI_example(void);
|
||||
|
||||
void SPI_1_MSIF_example(void);
|
||||
|
||||
void TIMER_0_example(void);
|
||||
|
||||
void PWM_0_example(void);
|
||||
|
||||
void PWM_1_example(void);
|
||||
|
||||
@@ -1,52 +0,0 @@
|
||||
============================
|
||||
The Timer driver (bare-bone)
|
||||
============================
|
||||
|
||||
The Timer driver provides means for delayed and periodical function invocation.
|
||||
|
||||
A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has
|
||||
been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a
|
||||
configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically
|
||||
changes execution delays and periods for all tasks in the timers task queue.
|
||||
|
||||
A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue
|
||||
and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on
|
||||
the period set in the task configuration.
|
||||
In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to
|
||||
reuse the memory of expired task in the callback.
|
||||
|
||||
Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available.
|
||||
|
||||
Features
|
||||
--------
|
||||
* Initialization and de-initialization
|
||||
* Starting and stopping
|
||||
* Timer tasks - periodical invocation of functions
|
||||
* Changing and obtaining of the period of a timer
|
||||
|
||||
Applications
|
||||
------------
|
||||
* Delayed and periodical function execution for middle-ware stacks and applications.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt.
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during
|
||||
the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed
|
||||
until the task adding or removing is complete.
|
||||
|
||||
The task queue is not protected from the access by interrupts not used by the driver. Due to this
|
||||
it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes
|
||||
the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver.
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts.
|
||||
* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task.
|
||||
|
||||
Knows issues and workarounds
|
||||
----------------------------
|
||||
Not applicable
|
||||
@@ -1,206 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Timer task functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_TIMER_H_INCLUDED
|
||||
#define _HAL_TIMER_H_INCLUDED
|
||||
|
||||
#include <utils_list.h>
|
||||
#include <hpl_timer.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_timer
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Timer mode type
|
||||
*/
|
||||
enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT };
|
||||
|
||||
/**
|
||||
* \brief Timer task descriptor
|
||||
*
|
||||
* The timer task descriptor forward declaration.
|
||||
*/
|
||||
struct timer_task;
|
||||
|
||||
/**
|
||||
* \brief Timer task callback function type
|
||||
*/
|
||||
typedef void (*timer_cb_t)(const struct timer_task *const timer_task);
|
||||
|
||||
/**
|
||||
* \brief Timer task structure
|
||||
*/
|
||||
struct timer_task {
|
||||
struct list_element elem; /*! List element. */
|
||||
uint32_t time_label; /*! Absolute timer start time. */
|
||||
|
||||
uint32_t interval; /*! Number of timer ticks before calling the task. */
|
||||
timer_cb_t cb; /*! Function pointer to the task. */
|
||||
enum timer_task_mode mode; /*! Task mode: one shot or repeat. */
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Timer structure
|
||||
*/
|
||||
struct timer_descriptor {
|
||||
struct _timer_device device;
|
||||
uint32_t time;
|
||||
struct list_descriptor tasks; /*! Timer tasks list. */
|
||||
volatile uint8_t flags;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize timer
|
||||
*
|
||||
* This function initializes the given timer.
|
||||
* It checks if the given hardware is not initialized and if the given hardware
|
||||
* is permitted to be initialized.
|
||||
*
|
||||
* \param[out] descr A timer descriptor to initialize
|
||||
* \param[in] hw The pointer to the hardware instance
|
||||
* \param[in] func The pointer to a set of function pointers
|
||||
*
|
||||
* \return Initialization status.
|
||||
*/
|
||||
int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize timer
|
||||
*
|
||||
* This function deinitializes the given timer.
|
||||
* It checks if the given hardware is initialized and if the given hardware is
|
||||
* permitted to be deinitialized.
|
||||
*
|
||||
* \param[in] descr A timer descriptor to deinitialize
|
||||
*
|
||||
* \return De-initialization status.
|
||||
*/
|
||||
int32_t timer_deinit(struct timer_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Start timer
|
||||
*
|
||||
* This function starts the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to start
|
||||
*
|
||||
* \return Timer starting status.
|
||||
*/
|
||||
int32_t timer_start(struct timer_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Stop timer
|
||||
*
|
||||
* This function stops the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to stop
|
||||
*
|
||||
* \return Timer stopping status.
|
||||
*/
|
||||
int32_t timer_stop(struct timer_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Set amount of clock cycles per timer tick
|
||||
*
|
||||
* This function sets the amount of clock cycles per timer tick for the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to stop
|
||||
* \param[in] clock_cycles The amount of clock cycles per tick to set
|
||||
*
|
||||
* \return Setting clock cycles amount status.
|
||||
*/
|
||||
int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the amount of clock cycles in a tick
|
||||
*
|
||||
* This function retrieves how many clock cycles there are in a single timer tick.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to convert ticks to
|
||||
* clock cycles
|
||||
* \param[out] cycles The amount of clock cycles
|
||||
*
|
||||
* \return The status of clock cycles retrieving.
|
||||
*/
|
||||
int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles);
|
||||
|
||||
/**
|
||||
* \brief Add timer task
|
||||
*
|
||||
* This function adds the given timer task to the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to add task to
|
||||
* \param[in] task A task to add
|
||||
*
|
||||
* \return Timer's task adding status.
|
||||
*/
|
||||
int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task);
|
||||
|
||||
/**
|
||||
* \brief Remove timer task
|
||||
*
|
||||
* This function removes the given timer task from the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to remove task from
|
||||
* \param[in] task A task to remove
|
||||
*
|
||||
* \return Timer's task removing status.
|
||||
*/
|
||||
int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t timer_get_version(void);
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_TIMER_H_INCLUDED */
|
||||
@@ -1,250 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Timer functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hal_timer.h"
|
||||
#include <utils_assert.h>
|
||||
#include <utils.h>
|
||||
#include <hal_atomic.h>
|
||||
#include <hpl_irq.h>
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define DRIVER_VERSION 0x00000001u
|
||||
|
||||
/**
|
||||
* \brief Timer flags
|
||||
*/
|
||||
#define TIMER_FLAG_QUEUE_IS_TAKEN 1
|
||||
#define TIMER_FLAG_INTERRUPT_TRIGERRED 2
|
||||
|
||||
static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time);
|
||||
static void timer_process_counted(struct _timer_device *device);
|
||||
|
||||
/**
|
||||
* \brief Initialize timer
|
||||
*/
|
||||
int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func)
|
||||
{
|
||||
ASSERT(descr && hw);
|
||||
_timer_init(&descr->device, hw);
|
||||
descr->time = 0;
|
||||
descr->device.timer_cb.period_expired = timer_process_counted;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Deinitialize timer
|
||||
*/
|
||||
int32_t timer_deinit(struct timer_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_timer_deinit(&descr->device);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Start timer
|
||||
*/
|
||||
int32_t timer_start(struct timer_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
if (_timer_is_started(&descr->device)) {
|
||||
return ERR_DENIED;
|
||||
}
|
||||
_timer_start(&descr->device);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Stop timer
|
||||
*/
|
||||
int32_t timer_stop(struct timer_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
if (!_timer_is_started(&descr->device)) {
|
||||
return ERR_DENIED;
|
||||
}
|
||||
_timer_stop(&descr->device);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set amount of clock cycler per timer tick
|
||||
*/
|
||||
int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_timer_set_period(&descr->device, clock_cycles);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Add timer task
|
||||
*/
|
||||
int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task)
|
||||
{
|
||||
ASSERT(descr && task);
|
||||
|
||||
descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN;
|
||||
if (is_list_element(&descr->tasks, task)) {
|
||||
descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN;
|
||||
ASSERT(false);
|
||||
return ERR_ALREADY_INITIALIZED;
|
||||
}
|
||||
task->time_label = descr->time;
|
||||
timer_add_timer_task(&descr->tasks, task, descr->time);
|
||||
|
||||
descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN;
|
||||
if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) {
|
||||
CRITICAL_SECTION_ENTER()
|
||||
descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED;
|
||||
_timer_set_irq(&descr->device);
|
||||
CRITICAL_SECTION_LEAVE()
|
||||
}
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Remove timer task
|
||||
*/
|
||||
int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task)
|
||||
{
|
||||
ASSERT(descr && task);
|
||||
|
||||
descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN;
|
||||
if (!is_list_element(&descr->tasks, task)) {
|
||||
descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN;
|
||||
ASSERT(false);
|
||||
return ERR_NOT_FOUND;
|
||||
}
|
||||
list_delete_element(&descr->tasks, task);
|
||||
|
||||
descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN;
|
||||
if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) {
|
||||
CRITICAL_SECTION_ENTER()
|
||||
descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED;
|
||||
_timer_set_irq(&descr->device);
|
||||
CRITICAL_SECTION_LEAVE()
|
||||
}
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the amount of clock cycles in a tick
|
||||
*/
|
||||
int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles)
|
||||
{
|
||||
ASSERT(descr && cycles);
|
||||
*cycles = _timer_get_period(&descr->device);
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*/
|
||||
uint32_t timer_get_version(void)
|
||||
{
|
||||
return DRIVER_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal Insert a timer task into sorted timer's list
|
||||
*
|
||||
* \param[in] head The pointer to the head of timer task list
|
||||
* \param[in] task The pointer to task to add
|
||||
* \param[in] time Current timer time
|
||||
*/
|
||||
static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time)
|
||||
{
|
||||
struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list);
|
||||
|
||||
if (!head) {
|
||||
list_insert_as_head(list, new_task);
|
||||
return;
|
||||
}
|
||||
|
||||
for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) {
|
||||
uint32_t time_left;
|
||||
|
||||
if (it->time_label <= time) {
|
||||
time_left = it->interval - (time - it->time_label);
|
||||
} else {
|
||||
time_left = it->interval - (0xFFFFFFFF - it->time_label) - time;
|
||||
}
|
||||
if (time_left >= new_task->interval)
|
||||
break;
|
||||
prev = it;
|
||||
}
|
||||
|
||||
if (it == head) {
|
||||
list_insert_as_head(list, new_task);
|
||||
} else {
|
||||
list_insert_after(prev, new_task);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal Process interrupts
|
||||
*/
|
||||
static void timer_process_counted(struct _timer_device *device)
|
||||
{
|
||||
struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device);
|
||||
struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks);
|
||||
uint32_t time = ++timer->time;
|
||||
|
||||
if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) {
|
||||
timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED;
|
||||
return;
|
||||
}
|
||||
|
||||
while (it && ((time - it->time_label) >= it->interval)) {
|
||||
struct timer_task *tmp = it;
|
||||
|
||||
list_remove_head(&timer->tasks);
|
||||
if (TIMER_TASK_REPEAT == tmp->mode) {
|
||||
tmp->time_label = time;
|
||||
timer_add_timer_task(&timer->tasks, tmp, time);
|
||||
}
|
||||
it = (struct timer_task *)list_get_head(&timer->tasks);
|
||||
|
||||
tmp->cb(tmp);
|
||||
}
|
||||
}
|
||||
@@ -215,10 +215,11 @@ static void _dmac_handler(void)
|
||||
uint8_t channel = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk);
|
||||
struct _dma_resource *tmp_resource = &_resources[channel];
|
||||
|
||||
if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) {
|
||||
if (hri_dmac_get_CHINTFLAG_TERR_bit(DMAC, channel)) {
|
||||
hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel);
|
||||
tmp_resource->dma_cb.error(tmp_resource);
|
||||
} else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)) {
|
||||
} else if (hri_dmac_get_CHINTFLAG_TCMPL_bit(DMAC, channel)) {
|
||||
//hri_dmac_get_CHINTFLAG_TCMPL_bit(DMAC, channel); /********* ADDED **************/
|
||||
hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel);
|
||||
tmp_resource->dma_cb.transfer_done(tmp_resource);
|
||||
}
|
||||
|
||||
@@ -1,357 +0,0 @@
|
||||
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM TC
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include <hpl_pwm.h>
|
||||
#include <hpl_tc_config.h>
|
||||
#include <hpl_timer.h>
|
||||
#include <utils.h>
|
||||
#include <utils_assert.h>
|
||||
#include <hpl_tc_base.h>
|
||||
|
||||
#ifndef CONF_TC0_ENABLE
|
||||
#define CONF_TC0_ENABLE 0
|
||||
#endif
|
||||
#ifndef CONF_TC1_ENABLE
|
||||
#define CONF_TC1_ENABLE 0
|
||||
#endif
|
||||
#ifndef CONF_TC2_ENABLE
|
||||
#define CONF_TC2_ENABLE 0
|
||||
#endif
|
||||
#ifndef CONF_TC3_ENABLE
|
||||
#define CONF_TC3_ENABLE 0
|
||||
#endif
|
||||
#ifndef CONF_TC4_ENABLE
|
||||
#define CONF_TC4_ENABLE 0
|
||||
#endif
|
||||
#ifndef CONF_TC5_ENABLE
|
||||
#define CONF_TC5_ENABLE 0
|
||||
#endif
|
||||
#ifndef CONF_TC6_ENABLE
|
||||
#define CONF_TC6_ENABLE 0
|
||||
#endif
|
||||
#ifndef CONF_TC7_ENABLE
|
||||
#define CONF_TC7_ENABLE 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Macro is used to fill usart configuration structure based on its
|
||||
* number
|
||||
*
|
||||
* \param[in] n The number of structures
|
||||
*/
|
||||
#define TC_CONFIGURATION(n) \
|
||||
{ \
|
||||
n, TC##n##_IRQn, \
|
||||
TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC) \
|
||||
| (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos) \
|
||||
| TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos), \
|
||||
(CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \
|
||||
| (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \
|
||||
| (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \
|
||||
(CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1, \
|
||||
}
|
||||
/**
|
||||
* \brief TC configuration type
|
||||
*/
|
||||
struct tc_configuration {
|
||||
uint8_t number;
|
||||
IRQn_Type irq;
|
||||
hri_tc_ctrla_reg_t ctrl_a;
|
||||
hri_tc_evctrl_reg_t event_ctrl;
|
||||
hri_tc_dbgctrl_reg_t dbg_ctrl;
|
||||
hri_tccount8_per_reg_t per;
|
||||
hri_tccount32_cc_reg_t cc0;
|
||||
hri_tccount32_cc_reg_t cc1;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Array of TC configurations
|
||||
*/
|
||||
static struct tc_configuration _tcs[] = {
|
||||
#if CONF_TC0_ENABLE == 1
|
||||
TC_CONFIGURATION(0),
|
||||
#endif
|
||||
#if CONF_TC1_ENABLE == 1
|
||||
TC_CONFIGURATION(1),
|
||||
#endif
|
||||
#if CONF_TC2_ENABLE == 1
|
||||
TC_CONFIGURATION(2),
|
||||
#endif
|
||||
#if CONF_TC3_ENABLE == 1
|
||||
TC_CONFIGURATION(3),
|
||||
#endif
|
||||
#if CONF_TC4_ENABLE == 1
|
||||
TC_CONFIGURATION(4),
|
||||
#endif
|
||||
#if CONF_TC5_ENABLE == 1
|
||||
TC_CONFIGURATION(5),
|
||||
#endif
|
||||
#if CONF_TC6_ENABLE == 1
|
||||
TC_CONFIGURATION(6),
|
||||
#endif
|
||||
#if CONF_TC7_ENABLE == 1
|
||||
TC_CONFIGURATION(7),
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct _timer_device *_tc0_dev = NULL;
|
||||
|
||||
static struct _pwm_device *_tc2_dev = NULL;
|
||||
|
||||
static struct _pwm_device *_tc4_dev = NULL;
|
||||
|
||||
static int8_t get_tc_index(const void *const hw);
|
||||
static void _tc_init_irq_param(const void *const hw, void *dev);
|
||||
static inline uint8_t _get_hardware_offset(const void *const hw);
|
||||
/**
|
||||
* \brief Initialize TC
|
||||
*/
|
||||
int32_t _timer_init(struct _timer_device *const device, void *const hw)
|
||||
{
|
||||
int8_t i = get_tc_index(hw);
|
||||
|
||||
device->hw = hw;
|
||||
ASSERT(ARRAY_SIZE(_tcs));
|
||||
|
||||
if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) {
|
||||
if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) {
|
||||
hri_tc_clear_CTRLA_ENABLE_bit(hw);
|
||||
hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE);
|
||||
}
|
||||
hri_tc_write_CTRLA_reg(hw, TC_CTRLA_SWRST);
|
||||
}
|
||||
hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
|
||||
|
||||
hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a);
|
||||
hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl);
|
||||
hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl);
|
||||
hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MFRQ);
|
||||
|
||||
if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
|
||||
hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0);
|
||||
hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
|
||||
|
||||
} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) {
|
||||
hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0);
|
||||
hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1);
|
||||
|
||||
} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) {
|
||||
hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0);
|
||||
hri_tccount8_write_CC_reg(hw, 1, (uint8_t)_tcs[i].cc1);
|
||||
hri_tccount8_write_PER_reg(hw, _tcs[i].per);
|
||||
}
|
||||
hri_tc_set_INTEN_OVF_bit(hw);
|
||||
|
||||
_tc_init_irq_param(hw, (void *)device);
|
||||
NVIC_DisableIRQ(_tcs[i].irq);
|
||||
NVIC_ClearPendingIRQ(_tcs[i].irq);
|
||||
NVIC_EnableIRQ(_tcs[i].irq);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
/**
|
||||
* \brief De-initialize TC
|
||||
*/
|
||||
void _timer_deinit(struct _timer_device *const device)
|
||||
{
|
||||
void *const hw = device->hw;
|
||||
int8_t i = get_tc_index(hw);
|
||||
ASSERT(ARRAY_SIZE(_tcs));
|
||||
|
||||
NVIC_DisableIRQ(_tcs[i].irq);
|
||||
|
||||
hri_tc_clear_CTRLA_ENABLE_bit(hw);
|
||||
hri_tc_set_CTRLA_SWRST_bit(hw);
|
||||
}
|
||||
/**
|
||||
* \brief Start hardware timer
|
||||
*/
|
||||
void _timer_start(struct _timer_device *const device)
|
||||
{
|
||||
hri_tc_set_CTRLA_ENABLE_bit(device->hw);
|
||||
}
|
||||
/**
|
||||
* \brief Stop hardware timer
|
||||
*/
|
||||
void _timer_stop(struct _timer_device *const device)
|
||||
{
|
||||
hri_tc_clear_CTRLA_ENABLE_bit(device->hw);
|
||||
}
|
||||
/**
|
||||
* \brief Set timer period
|
||||
*/
|
||||
void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles)
|
||||
{
|
||||
void *const hw = device->hw;
|
||||
|
||||
if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
|
||||
hri_tccount32_write_CC_reg(hw, 0, clock_cycles);
|
||||
} else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
|
||||
hri_tccount16_write_CC_reg(hw, 0, (uint16_t)clock_cycles);
|
||||
} else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
|
||||
hri_tccount8_write_PER_reg(hw, clock_cycles);
|
||||
}
|
||||
}
|
||||
/**
|
||||
* \brief Retrieve timer period
|
||||
*/
|
||||
uint32_t _timer_get_period(const struct _timer_device *const device)
|
||||
{
|
||||
void *const hw = device->hw;
|
||||
|
||||
if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
|
||||
return hri_tccount32_read_CC_reg(hw, 0);
|
||||
} else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
|
||||
return hri_tccount16_read_CC_reg(hw, 0);
|
||||
} else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
|
||||
return hri_tccount8_read_PER_reg(hw);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* \brief Check if timer is running
|
||||
*/
|
||||
bool _timer_is_started(const struct _timer_device *const device)
|
||||
{
|
||||
return hri_tc_get_CTRLA_ENABLE_bit(device->hw);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve timer helper functions
|
||||
*/
|
||||
struct _timer_hpl_interface *_tc_get_timer(void)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve pwm helper functions
|
||||
*/
|
||||
struct _pwm_hpl_interface *_tc_get_pwm(void)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
/**
|
||||
* \brief Set timer IRQ
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*/
|
||||
void _timer_set_irq(struct _timer_device *const device)
|
||||
{
|
||||
void *const hw = device->hw;
|
||||
int8_t i = get_tc_index(hw);
|
||||
ASSERT(ARRAY_SIZE(_tcs));
|
||||
|
||||
_irq_set(_tcs[i].irq);
|
||||
}
|
||||
/**
|
||||
* \internal TC interrupt handler for Timer
|
||||
*
|
||||
* \param[in] instance TC instance number
|
||||
*/
|
||||
static void tc_interrupt_handler(struct _timer_device *device)
|
||||
{
|
||||
void *const hw = device->hw;
|
||||
|
||||
if (hri_tc_get_interrupt_OVF_bit(hw)) {
|
||||
hri_tc_clear_interrupt_OVF_bit(hw);
|
||||
device->timer_cb.period_expired(device);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief TC interrupt handler
|
||||
*/
|
||||
void TC0_Handler(void)
|
||||
{
|
||||
tc_interrupt_handler(_tc0_dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal Retrieve TC index
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return The index of TC configuration
|
||||
*/
|
||||
static int8_t get_tc_index(const void *const hw)
|
||||
{
|
||||
uint8_t index = _get_hardware_offset(hw);
|
||||
uint8_t i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(_tcs); i++) {
|
||||
if (_tcs[i].number == index) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
|
||||
ASSERT(false);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Init irq param with the given tc hardware instance
|
||||
*/
|
||||
static void _tc_init_irq_param(const void *const hw, void *dev)
|
||||
{
|
||||
if (hw == TC0) {
|
||||
_tc0_dev = (struct _timer_device *)dev;
|
||||
}
|
||||
if (hw == TC2) {
|
||||
_tc2_dev = (struct _pwm_device *)dev;
|
||||
}
|
||||
if (hw == TC4) {
|
||||
_tc4_dev = (struct _pwm_device *)dev;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal Retrieve TC hardware index
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*/
|
||||
static inline uint8_t _get_hardware_offset(const void *const hw)
|
||||
{
|
||||
/* List of available TC modules. */
|
||||
Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
|
||||
|
||||
/* Find index for TC instance. */
|
||||
for (uint32_t i = 0; i < TC_INST_NUM; i++) {
|
||||
if ((uint32_t)hw == (uint32_t)tc_modules[i]) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@@ -1,77 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Timer/Counter
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*/
|
||||
|
||||
#ifndef _HPL_TC_BASE_H_INCLUDED
|
||||
#define _HPL_TC_BASE_H_INCLUDED
|
||||
|
||||
#include <hpl_timer.h>
|
||||
#include <hpl_pwm.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup tc_group TC Hardware Proxy Layer
|
||||
*
|
||||
* \section tc_hpl_rev Revision History
|
||||
* - v0.0.0.1 Initial Commit
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
|
||||
/**
|
||||
* \brief Retrieve timer helper functions
|
||||
*
|
||||
* \return A pointer to set of timer helper functions
|
||||
*/
|
||||
struct _timer_hpl_interface *_tc_get_timer(void);
|
||||
|
||||
/**
|
||||
* \brief Retrieve pwm helper functions
|
||||
*
|
||||
* \return A pointer to set of pwm helper functions
|
||||
*/
|
||||
struct _pwm_hpl_interface *_tc_get_pwm(void);
|
||||
|
||||
//@}
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HPL_TC_BASE_H_INCLUDED */
|
||||
@@ -34,6 +34,74 @@
|
||||
|
||||
#include "tc_lite.h"
|
||||
|
||||
/**
|
||||
* \brief Initialize TC interface
|
||||
*/
|
||||
int8_t TIMER_0_init()
|
||||
{
|
||||
|
||||
if (!hri_tc_is_syncing(TC0, TC_SYNCBUSY_SWRST)) {
|
||||
if (hri_tc_get_CTRLA_reg(TC0, TC_CTRLA_ENABLE)) {
|
||||
hri_tc_clear_CTRLA_ENABLE_bit(TC0);
|
||||
hri_tc_wait_for_sync(TC0, TC_SYNCBUSY_ENABLE);
|
||||
}
|
||||
hri_tc_write_CTRLA_reg(TC0, TC_CTRLA_SWRST);
|
||||
}
|
||||
hri_tc_wait_for_sync(TC0, TC_SYNCBUSY_SWRST);
|
||||
|
||||
hri_tc_write_CTRLA_reg(TC0,
|
||||
0 << TC_CTRLA_CAPTMODE0_Pos /* Capture mode Channel 0: 0 */
|
||||
| 0 << TC_CTRLA_CAPTMODE1_Pos /* Capture mode Channel 1: 0 */
|
||||
| 0 << TC_CTRLA_COPEN0_Pos /* Capture Pin 0 Enable: disabled */
|
||||
| 0 << TC_CTRLA_COPEN1_Pos /* Capture Pin 1 Enable: disabled */
|
||||
| 0 << TC_CTRLA_CAPTEN0_Pos /* Capture Channel 0 Enable: disabled */
|
||||
| 0 << TC_CTRLA_CAPTEN1_Pos /* Capture Channel 1 Enable: disabled */
|
||||
| 0 << TC_CTRLA_ALOCK_Pos /* Auto Lock: disabled */
|
||||
| 0 << TC_CTRLA_PRESCSYNC_Pos /* Prescaler and Counter Synchronization: 0 */
|
||||
| 0 << TC_CTRLA_ONDEMAND_Pos /* Clock On Demand: disabled */
|
||||
| 0 << TC_CTRLA_RUNSTDBY_Pos /* Run in Standby: disabled */
|
||||
| 5 << TC_CTRLA_PRESCALER_Pos /* Setting: 5 */
|
||||
| 0x0 << TC_CTRLA_MODE_Pos); /* Operating Mode: 0x0 */
|
||||
|
||||
hri_tc_write_CTRLB_reg(TC0,
|
||||
0 << TC_CTRLBSET_CMD_Pos /* Command: 0 */
|
||||
| 0 << TC_CTRLBSET_ONESHOT_Pos /* One-Shot: disabled */
|
||||
| 0 << TC_CTRLBCLR_LUPD_Pos /* Setting: disabled */
|
||||
| 0 << TC_CTRLBSET_DIR_Pos); /* Counter Direction: disabled */
|
||||
|
||||
hri_tc_write_WAVE_reg(TC0,1); /* Waveform Generation Mode: 0 */
|
||||
|
||||
// hri_tc_write_DRVCTRL_reg(TC0,0 << TC_DRVCTRL_INVEN1_Pos /* Output Waveform 1 Invert Enable: disabled */
|
||||
// | 0 << TC_DRVCTRL_INVEN0_Pos); /* Output Waveform 0 Invert Enable: disabled */
|
||||
|
||||
// hri_tc_write_DBGCTRL_reg(TC0,0); /* Run in debug: 0 */
|
||||
|
||||
hri_tccount16_write_CC_reg(TC0, 0, 0x752); /* Compare/Capture Value: 0x752 */
|
||||
|
||||
// hri_tccount16_write_CC_reg(TC0, 1 ,0x0); /* Compare/Capture Value: 0x0 */
|
||||
|
||||
// hri_tccount16_write_COUNT_reg(TC0,0x0); /* Counter Value: 0x0 */
|
||||
|
||||
hri_tc_write_EVCTRL_reg(
|
||||
TC0,
|
||||
1 << TC_EVCTRL_MCEO0_Pos /* Match or Capture Channel 0 Event Output Enable: enabled */
|
||||
| 0 << TC_EVCTRL_MCEO1_Pos /* Match or Capture Channel 1 Event Output Enable: disabled */
|
||||
| 0 << TC_EVCTRL_OVFEO_Pos /* Overflow/Underflow Event Output Enable: disabled */
|
||||
| 0 << TC_EVCTRL_TCEI_Pos /* TC Event Input: disabled */
|
||||
| 0 << TC_EVCTRL_TCINV_Pos /* TC Inverted Event Input: disabled */
|
||||
| 0); /* Event Action: 0 */
|
||||
|
||||
hri_tc_write_INTEN_reg(TC0,
|
||||
1 << TC_INTENSET_MC0_Pos /* Match or Capture Channel 0 Interrupt Enable: enabled */
|
||||
| 0 << TC_INTENSET_MC1_Pos /* Match or Capture Channel 1 Interrupt Enable: disabled */
|
||||
| 0 << TC_INTENSET_ERR_Pos /* Error Interrupt Enable: disabled */
|
||||
| 0 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: disabled */
|
||||
|
||||
hri_tc_write_CTRLA_ENABLE_bit(TC0, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Initialize TC interface
|
||||
*/
|
||||
|
||||
@@ -51,6 +51,12 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Initialize tc interface
|
||||
* \return Initialization status.
|
||||
*/
|
||||
int8_t TIMER_0_init();
|
||||
|
||||
/**
|
||||
* \brief Initialize tc interface
|
||||
* \return Initialization status.
|
||||
|
||||
@@ -37,7 +37,7 @@ static void b2bTransferComplete_cb(struct _dma_resource *resource)
|
||||
{
|
||||
|
||||
PORT->Group[1].OUTSET.reg = (1<<GPIO_PIN(SPI1_CS));
|
||||
//PORT->Group[1].OUTSET.reg = (1<<SPI1_CS);
|
||||
volatile int x = 0;
|
||||
//PORT->Group[GPIO_PORTB].OUTCLR.reg = (1<<Slave_1->SS_pin);
|
||||
//gpio_set_pin_level(SPI1_CS, true);
|
||||
}
|
||||
|
||||
@@ -48,19 +48,13 @@ void process_currents()
|
||||
Motor2.timerflags.current_loop_tic = true;
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using TIMER_0.
|
||||
*/
|
||||
|
||||
static struct timer_task Onems_task;
|
||||
|
||||
void One_ms_timer_init(void)
|
||||
{
|
||||
Onems_task.interval = 1;
|
||||
Onems_task.cb = One_ms_cycle_callback;
|
||||
Onems_task.mode = TIMER_TASK_REPEAT;
|
||||
timer_add_task(&TIMER_0, &Onems_task);
|
||||
timer_start(&TIMER_0);
|
||||
void TC0_Handler( void ){
|
||||
if (TC0->COUNT16.INTFLAG.bit.MC0 == 0x01){
|
||||
TC0->COUNT16.INTFLAG.bit.MC0 = 0x01;
|
||||
Motor1.timerflags.motor_telemetry_flag = true;
|
||||
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void enable_NVIC_IRQ(void)
|
||||
@@ -72,11 +66,15 @@ void enable_NVIC_IRQ(void)
|
||||
//NVIC_EnableIRQ(TC4_IRQn); // TC4: M2_Speed_Timer
|
||||
NVIC_EnableIRQ(DMAC_0_IRQn);
|
||||
NVIC_EnableIRQ(DMAC_1_IRQn);
|
||||
NVIC_SetPriority(DMAC_0_IRQn, 1);
|
||||
NVIC_SetPriority(ADC1_0_IRQn, 2);
|
||||
NVIC_SetPriority(DMAC_0_IRQn, 2);
|
||||
NVIC_SetPriority(ADC1_0_IRQn, 3);
|
||||
NVIC_EnableIRQ(TCC0_0_IRQn);
|
||||
NVIC_EnableIRQ(TCC1_0_IRQn);
|
||||
NVIC_EnableIRQ(EIC_2_IRQn);
|
||||
NVIC_EnableIRQ(SERCOM1_1_IRQn);
|
||||
NVIC_SetPriority(SERCOM1_1_IRQn, 1);
|
||||
NVIC_EnableIRQ(TC0_IRQn);
|
||||
//NVIC_EnableIRQ(TC0_IRQn);
|
||||
//NVIC_SetPriority(EIC_2_IRQn, 3);
|
||||
//NVIC_SetPriority(TCC0_0_IRQn, 3);
|
||||
//NVIC_EnableIRQ(EIC_5_IRQn);
|
||||
@@ -165,26 +163,31 @@ int main(void)
|
||||
adc_init_dma();
|
||||
|
||||
ECAT_STATE_MACHINE();
|
||||
One_ms_timer_init();
|
||||
custom_logic_enable();
|
||||
|
||||
//angle_sensor_init();
|
||||
//initialize_ads();
|
||||
/* External IRQ Config */
|
||||
__enable_irq();
|
||||
enable_NVIC_IRQ();
|
||||
__enable_irq();
|
||||
|
||||
//ext_irq_register(GPIO_PIN(ADS_DATA_RDY), ADS1299_dataReadyISR);
|
||||
//ADS1299_START();
|
||||
|
||||
/* Replace with your application code */
|
||||
while (1) {
|
||||
if (Motor1.timerflags.adc_readings_ready_tic) {process_currents();}
|
||||
//if (Motor1.timerflags.adc_readings_ready_tic) {process_currents();}
|
||||
|
||||
if (Motor1.timerflags.motor_telemetry_flag) {
|
||||
Motor1.timerflags.motor_telemetry_flag = false;
|
||||
update_telemetry();
|
||||
update_setpoints();
|
||||
PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
|
||||
|
||||
if (DMAC->Channel[DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT].CHSTATUS.bit.PEND == true)
|
||||
{
|
||||
volatile int x = 0;
|
||||
}
|
||||
//PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
|
||||
DMAC->Channel[DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
DMAC->Channel[DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
//_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, false);
|
||||
@@ -205,10 +208,11 @@ int main(void)
|
||||
}
|
||||
|
||||
if (Motor1.timerflags.current_loop_tic) {
|
||||
Motor1.timerflags.current_loop_tic = false;
|
||||
APPLICATION_StateMachine();
|
||||
exec_commutation(&Motor1);
|
||||
exec_commutation(&Motor2);
|
||||
|
||||
Motor1.timerflags.current_loop_tic = false;
|
||||
APPLICATION_StateMachine();
|
||||
exec_commutation(&Motor1);
|
||||
exec_commutation(&Motor2);
|
||||
}
|
||||
|
||||
if (ADS1299.data_ReadyFlag){
|
||||
|
||||
@@ -150,12 +150,12 @@ const static BLDCMotor_param_t FH_22mm24BXTR = {
|
||||
.motor_LD_H = 0.003150,
|
||||
.motor_LQ_H = 0.003150,
|
||||
.motor_Flux_WB = 0.001575,
|
||||
.motor_Max_Spd_RPM = 3000,
|
||||
.motor_Max_Spd_RPM = 2000,
|
||||
.motor_MeasureRange_RPM = 3000 * 1.2, //(1.2f * MOTOR_MAX_SPD_RPM)f // give 20% headroom
|
||||
.motor_Max_Spd_ELEC = (3000/60)*7.0, //(MOTOR_MAX_SPD_RPM/60)*MOTOR_POLEPAIRS
|
||||
//.motor_Max_Current_IDC_A = 0.368,
|
||||
.motor_Max_Current_IDC_A = 0.180,
|
||||
.controller_param.Pid_Speed.Kp = 0.00008f,
|
||||
.controller_param.Pid_Speed.Kp = 0.00004f,
|
||||
.controller_param.Pid_Speed.Ki = 0.0000001f,
|
||||
//.controller_param.Pid_Speed.Ki = 0.0000001f,
|
||||
.controller_param.Pi_Pos.Kp = 50.0f,
|
||||
|
||||
@@ -59,9 +59,10 @@ typedef enum
|
||||
|
||||
typedef enum
|
||||
{
|
||||
MOTOR_NOFAULT = 0xE1,
|
||||
MOTOR_HALLSENSORINVALID = 0xE2,
|
||||
MOTOR_DRIVER_OVER_CURRENT = 0xE3,
|
||||
MOTOR_NOFAULT = 0x0E,
|
||||
MOTOR_HALLSENSORINVALID = 0xE1,
|
||||
MOTOR_DRIVER_OVER_CURRENT = 0xE2,
|
||||
MOTOR_CURRENTS_SENSOR = 0xE3,
|
||||
} MOTOR_FAULTS_t;
|
||||
|
||||
typedef struct MOTOR_STATE
|
||||
|
||||
Reference in New Issue
Block a user