fixed the dma issue
This commit is contained in:
Nicolas Trimborn
parent
fadb312ed1
commit
c00c82e6e6
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@ -41,7 +41,7 @@ drivers:
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adc_arch_refcomp: false
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adc_arch_resrdyeo: true
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adc_arch_runstdby: false
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adc_arch_samplen: 3
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adc_arch_samplen: 2
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adc_arch_samplenum: 1 sample
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adc_arch_seqen: 0
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adc_arch_startei: false
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@ -237,7 +237,7 @@ drivers:
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api: HAL:HPL:DMAC
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configuration:
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dmac_beatsize_0: 8-bit bus transfer
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dmac_beatsize_1: 8-bit bus transfer
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dmac_beatsize_1: 16-bit bus transfer
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dmac_beatsize_10: 8-bit bus transfer
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dmac_beatsize_11: 8-bit bus transfer
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dmac_beatsize_12: 8-bit bus transfer
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@ -259,7 +259,7 @@ drivers:
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dmac_beatsize_27: 8-bit bus transfer
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dmac_beatsize_28: 8-bit bus transfer
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dmac_beatsize_29: 8-bit bus transfer
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dmac_beatsize_3: 16-bit bus transfer
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dmac_beatsize_3: 8-bit bus transfer
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dmac_beatsize_30: 8-bit bus transfer
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dmac_beatsize_31: 8-bit bus transfer
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dmac_beatsize_4: 8-bit bus transfer
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@ -271,7 +271,7 @@ drivers:
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dmac_blockact_0: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_1: Channel will be disabled if it is the last block transfer in
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the transaction
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the transaction and block interrupt
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dmac_blockact_10: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_11: Channel will be disabled if it is the last block transfer
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@ -314,7 +314,7 @@ drivers:
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dmac_blockact_29: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_3: Channel will be disabled if it is the last block transfer in
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the transaction and block interrupt
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the transaction
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dmac_blockact_30: Channel will be disabled if it is the last block transfer
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in the transaction
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dmac_blockact_31: Channel will be disabled if it is the last block transfer
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@ -365,7 +365,7 @@ drivers:
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dmac_channel_9_settings: false
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dmac_dbgrun: false
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dmac_dstinc_0: true
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dmac_dstinc_1: false
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dmac_dstinc_1: true
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dmac_dstinc_10: false
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dmac_dstinc_11: false
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dmac_dstinc_12: false
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@ -387,7 +387,7 @@ drivers:
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dmac_dstinc_27: false
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dmac_dstinc_28: false
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dmac_dstinc_29: false
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dmac_dstinc_3: true
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dmac_dstinc_3: false
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dmac_dstinc_30: false
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dmac_dstinc_31: false
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dmac_dstinc_4: false
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@ -537,7 +537,7 @@ drivers:
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dmac_lvl_17: Channel priority 0
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dmac_lvl_18: Channel priority 0
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dmac_lvl_19: Channel priority 0
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dmac_lvl_2: Channel priority 1
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dmac_lvl_2: Channel priority 0
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dmac_lvl_20: Channel priority 0
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dmac_lvl_21: Channel priority 0
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dmac_lvl_22: Channel priority 0
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@ -548,7 +548,7 @@ drivers:
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dmac_lvl_27: Channel priority 0
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dmac_lvl_28: Channel priority 0
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dmac_lvl_29: Channel priority 0
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dmac_lvl_3: Channel priority 1
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dmac_lvl_3: Channel priority 0
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dmac_lvl_30: Channel priority 0
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dmac_lvl_31: Channel priority 0
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dmac_lvl_4: Channel priority 0
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@ -562,15 +562,15 @@ drivers:
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dmac_lvlen2: true
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dmac_lvlen3: true
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dmac_lvlpri0: 0
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dmac_lvlpri1: 1
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dmac_lvlpri1: 0
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dmac_lvlpri2: 0
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dmac_lvlpri3: 0
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dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
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dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
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dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
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dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
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dmac_runstdby_0: false
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dmac_runstdby_1: false
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dmac_runstdby_0: true
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dmac_runstdby_1: true
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dmac_runstdby_10: false
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dmac_runstdby_11: false
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dmac_runstdby_12: false
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@ -581,7 +581,7 @@ drivers:
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dmac_runstdby_17: false
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dmac_runstdby_18: false
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dmac_runstdby_19: false
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dmac_runstdby_2: false
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dmac_runstdby_2: true
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dmac_runstdby_20: false
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dmac_runstdby_21: false
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dmac_runstdby_22: false
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@ -592,7 +592,7 @@ drivers:
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dmac_runstdby_27: false
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dmac_runstdby_28: false
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dmac_runstdby_29: false
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dmac_runstdby_3: false
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dmac_runstdby_3: true
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dmac_runstdby_30: false
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dmac_runstdby_31: false
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dmac_runstdby_4: false
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@ -602,7 +602,7 @@ drivers:
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dmac_runstdby_8: false
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dmac_runstdby_9: false
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dmac_srcinc_0: false
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dmac_srcinc_1: true
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dmac_srcinc_1: false
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dmac_srcinc_10: false
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dmac_srcinc_11: false
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dmac_srcinc_12: false
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@ -624,7 +624,7 @@ drivers:
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dmac_srcinc_27: false
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dmac_srcinc_28: false
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dmac_srcinc_29: false
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dmac_srcinc_3: false
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dmac_srcinc_3: true
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dmac_srcinc_30: false
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dmac_srcinc_31: false
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dmac_srcinc_4: false
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@ -656,7 +656,7 @@ drivers:
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dmac_stepsel_27: Step size settings apply to the destination address
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dmac_stepsel_28: Step size settings apply to the destination address
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dmac_stepsel_29: Step size settings apply to the destination address
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dmac_stepsel_3: Step size settings apply to the destination address
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dmac_stepsel_3: Step size settings apply to the source address
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dmac_stepsel_30: Step size settings apply to the destination address
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dmac_stepsel_31: Step size settings apply to the destination address
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dmac_stepsel_4: Step size settings apply to the destination address
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@ -698,7 +698,7 @@ drivers:
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dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_trifsrc_0: SERCOM1 RX Trigger
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dmac_trifsrc_1: SERCOM1 TX Trigger
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dmac_trifsrc_1: ADC1 Result Ready Trigger
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dmac_trifsrc_10: Only software/event triggers
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dmac_trifsrc_11: Only software/event triggers
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dmac_trifsrc_12: Only software/event triggers
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@ -720,7 +720,7 @@ drivers:
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dmac_trifsrc_27: Only software/event triggers
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dmac_trifsrc_28: Only software/event triggers
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dmac_trifsrc_29: Only software/event triggers
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dmac_trifsrc_3: ADC1 Result Ready Trigger
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dmac_trifsrc_3: SERCOM1 TX Trigger
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dmac_trifsrc_30: Only software/event triggers
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dmac_trifsrc_31: Only software/event triggers
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dmac_trifsrc_4: Only software/event triggers
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@ -1758,10 +1758,10 @@ drivers:
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spi_master_arch_dord: MSB first
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spi_master_arch_ibon: In data stream
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spi_master_arch_runstdby: false
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spi_master_baud_rate: 8000000
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spi_master_baud_rate: 2000000
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spi_master_character_size: 8 bits
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spi_master_dma_rx_channel: 0
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spi_master_dma_tx_channel: 1
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spi_master_dma_tx_channel: 3
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spi_master_dummybyte: 511
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spi_master_rx_channel: true
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spi_master_rx_enable: true
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@ -209,7 +209,7 @@
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// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
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// <id> adc_arch_samplen
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#ifndef CONF_ADC_1_SAMPLEN
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#define CONF_ADC_1_SAMPLEN 3
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#define CONF_ADC_1_SAMPLEN 2
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#endif
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// <o> Window Monitor Mode
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@ -51,7 +51,7 @@
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// <o> Level 1 Channel Priority Number <0x00-0xFF>
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// <id> dmac_lvlpri1
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#ifndef CONF_DMAC_LVLPRI1
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#define CONF_DMAC_LVLPRI1 1
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#define CONF_DMAC_LVLPRI1 0
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#endif
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// <q> Priority Level 2
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// <i> Indicates whether Priority Level 2 is enabled or not
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@ -112,7 +112,7 @@
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// <i> Indicates whether channel 0 is running in standby mode or not
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// <id> dmac_runstdby_0
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#ifndef CONF_DMAC_RUNSTDBY_0
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#define CONF_DMAC_RUNSTDBY_0 0
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#define CONF_DMAC_RUNSTDBY_0 1
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#endif
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// <o> Trigger action
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@ -336,7 +336,7 @@
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// <i> Indicates whether channel 1 is running in standby mode or not
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// <id> dmac_runstdby_1
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#ifndef CONF_DMAC_RUNSTDBY_1
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#define CONF_DMAC_RUNSTDBY_1 0
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#define CONF_DMAC_RUNSTDBY_1 1
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#endif
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// <o> Trigger action
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@ -438,7 +438,7 @@
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// <i> Defines the peripheral trigger which is source of the transfer
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// <id> dmac_trifsrc_1
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#ifndef CONF_DMAC_TRIGSRC_1
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#define CONF_DMAC_TRIGSRC_1 7
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#define CONF_DMAC_TRIGSRC_1 70
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#endif
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// <o> Channel Arbitration Level
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@ -508,14 +508,14 @@
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// <i> Indicates whether the source address incrementation is enabled or not
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// <id> dmac_srcinc_1
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#ifndef CONF_DMAC_SRCINC_1
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#define CONF_DMAC_SRCINC_1 1
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#define CONF_DMAC_SRCINC_1 0
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#endif
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// <q> Destination Address Increment
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// <i> Indicates whether the destination address incrementation is enabled or not
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// <id> dmac_dstinc_1
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#ifndef CONF_DMAC_DSTINC_1
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#define CONF_DMAC_DSTINC_1 0
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#define CONF_DMAC_DSTINC_1 1
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#endif
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// <o> Beat Size
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@ -525,7 +525,7 @@
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// <i> Defines the size of one beat
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// <id> dmac_beatsize_1
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#ifndef CONF_DMAC_BEATSIZE_1
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#define CONF_DMAC_BEATSIZE_1 0
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#define CONF_DMAC_BEATSIZE_1 1
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#endif
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// <o> Block Action
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@ -536,7 +536,7 @@
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// <i> Defines the the DMAC should take after a block transfer has completed
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// <id> dmac_blockact_1
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#ifndef CONF_DMAC_BLOCKACT_1
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#define CONF_DMAC_BLOCKACT_1 0
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#define CONF_DMAC_BLOCKACT_1 1
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#endif
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// <o> Event Output Selection
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@ -560,7 +560,7 @@
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// <i> Indicates whether channel 2 is running in standby mode or not
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// <id> dmac_runstdby_2
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#ifndef CONF_DMAC_RUNSTDBY_2
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#define CONF_DMAC_RUNSTDBY_2 0
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#define CONF_DMAC_RUNSTDBY_2 1
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#endif
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// <o> Trigger action
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@ -673,7 +673,7 @@
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// <i> Defines the arbitration level for this channel
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// <id> dmac_lvl_2
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#ifndef CONF_DMAC_LVL_2
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#define CONF_DMAC_LVL_2 1
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#define CONF_DMAC_LVL_2 0
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#endif
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// <q> Channel Event Output
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@ -784,7 +784,7 @@
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// <i> Indicates whether channel 3 is running in standby mode or not
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// <id> dmac_runstdby_3
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#ifndef CONF_DMAC_RUNSTDBY_3
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#define CONF_DMAC_RUNSTDBY_3 0
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#define CONF_DMAC_RUNSTDBY_3 1
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#endif
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// <o> Trigger action
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@ -886,7 +886,7 @@
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// <i> Defines the peripheral trigger which is source of the transfer
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// <id> dmac_trifsrc_3
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#ifndef CONF_DMAC_TRIGSRC_3
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#define CONF_DMAC_TRIGSRC_3 70
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#define CONF_DMAC_TRIGSRC_3 7
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#endif
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// <o> Channel Arbitration Level
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@ -897,7 +897,7 @@
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// <i> Defines the arbitration level for this channel
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// <id> dmac_lvl_3
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#ifndef CONF_DMAC_LVL_3
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#define CONF_DMAC_LVL_3 1
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#define CONF_DMAC_LVL_3 0
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#endif
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// <q> Channel Event Output
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@ -949,21 +949,21 @@
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// <i> Defines whether source or destination addresses are using the step size settings
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// <id> dmac_stepsel_3
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#ifndef CONF_DMAC_STEPSEL_3
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#define CONF_DMAC_STEPSEL_3 0
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#define CONF_DMAC_STEPSEL_3 1
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#endif
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// <q> Source Address Increment
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// <i> Indicates whether the source address incrementation is enabled or not
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// <id> dmac_srcinc_3
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#ifndef CONF_DMAC_SRCINC_3
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#define CONF_DMAC_SRCINC_3 0
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#define CONF_DMAC_SRCINC_3 1
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#endif
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// <q> Destination Address Increment
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// <i> Indicates whether the destination address incrementation is enabled or not
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// <id> dmac_dstinc_3
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#ifndef CONF_DMAC_DSTINC_3
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#define CONF_DMAC_DSTINC_3 1
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#define CONF_DMAC_DSTINC_3 0
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#endif
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// <o> Beat Size
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@ -973,7 +973,7 @@
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// <i> Defines the size of one beat
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// <id> dmac_beatsize_3
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#ifndef CONF_DMAC_BEATSIZE_3
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#define CONF_DMAC_BEATSIZE_3 1
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#define CONF_DMAC_BEATSIZE_3 0
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#endif
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// <o> Block Action
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@ -984,7 +984,7 @@
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// <i> Defines the the DMAC should take after a block transfer has completed
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// <id> dmac_blockact_3
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#ifndef CONF_DMAC_BLOCKACT_3
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#define CONF_DMAC_BLOCKACT_3 1
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#define CONF_DMAC_BLOCKACT_3 0
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#endif
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// <o> Event Output Selection
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@ -15,7 +15,7 @@
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//<i> This defines DMA channel to be used
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//<id> spi_master_dma_tx_channel
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#ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL
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#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 1
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#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 3
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#endif
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// <e> SPI RX Channel Enable
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@ -59,7 +59,7 @@
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// <i> The SPI data transfer rate
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// <id> spi_master_baud_rate
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#ifndef CONF_SERCOM_1_SPI_BAUD
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#define CONF_SERCOM_1_SPI_BAUD 8000000
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#define CONF_SERCOM_1_SPI_BAUD 2000000
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#endif
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// </h>
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@ -207,10 +207,10 @@
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<AcmeProjectActionInfo Action="File" Source="hpl/tcc/hpl_tcc.h" IsConfig="false" Hash="rdWkAK12qkOYV59tWwzy6A" />
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<AcmeProjectActionInfo Action="File" Source="atmel_start.h" IsConfig="false" Hash="9RBG5E2ViQiSP2Gn4/FGpA" />
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<AcmeProjectActionInfo Action="File" Source="atmel_start.c" IsConfig="false" Hash="1RHIE7zTtYK4DURNPUqF9w" />
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<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="KQS08c8S3nvQhznT02tFlg" />
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<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="IJeJ3sDxG9f3mmsLxoMLlA" />
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<AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" />
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<AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
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<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="JdAljBjm3ndwImqgZ6Oc5w" />
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<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="InEybPQe1lA+oW1HFMWYLg" />
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<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="S8xJxIaG6pS6BEvDgxKh9w" />
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<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="/3bNiu/UgpvPbmvfRA+w3g" />
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<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
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@ -219,7 +219,7 @@
|
|||
<AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Uje5LXAS+nQpGryt9t0fYA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="rMTNR+5FXtu+wfT1NbfRRA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_qspi_config.h" IsConfig="true" Hash="CwZ360eeEYs7T9SYFSvDug" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="RbJ5bUxaEZKAk+siOfnj8g" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="NOEuutypdbfpBKOWCPUPuA" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_tc_config.h" IsConfig="true" Hash="T93Kr6C+WDuufZob89oPeg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="s/tLl+lpMPQWNUrjuAL0rQ" />
|
||||
|
|
@ -417,7 +417,7 @@
|
|||
<armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
|
||||
<armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
|
||||
<armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
|
||||
<armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
|
||||
<armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
|
||||
<armgcc.linker.general.UseNewlibNano>True</armgcc.linker.general.UseNewlibNano>
|
||||
<armgcc.linker.libraries.Libraries>
|
||||
<ListValues>
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
|
||||
// ----------------------------------------------------------------------
|
||||
#define DMAC_CHANNEL_ADC_SEQ 2U
|
||||
#define DMAC_CHANNEL_ADC_SRAM 3U
|
||||
#define DMAC_CHANNEL_ADC_SRAM 1U
|
||||
|
||||
/* Single Ended */
|
||||
//const uint32_t adc_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808};
|
||||
|
|
@ -152,7 +152,7 @@ extern DmacDescriptor _write_back_section[DMAC_CH_NUM];
|
|||
|
||||
|
||||
#define DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE 0u
|
||||
#define DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT 1U
|
||||
#define DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT 3U
|
||||
|
||||
void boardToBoardTransferInit(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -63,14 +63,6 @@ void One_ms_timer_init(void)
|
|||
timer_start(&TIMER_0);
|
||||
}
|
||||
|
||||
//void speed_timer_init(void)
|
||||
//{
|
||||
//hri_tc_write_WAVE_reg(TC_SPEED_M1.device.hw, 0x00);
|
||||
//hri_tc_set_CTRLA_CAPTEN0_bit(TC_SPEED_M1.device.hw);
|
||||
//hri_tc_set_CTRLA_CAPTEN1_bit(TC_SPEED_M1.device.hw);
|
||||
//timer_start(&TC_SPEED_M1);
|
||||
//}
|
||||
|
||||
void enable_NVIC_IRQ(void)
|
||||
{
|
||||
|
||||
|
|
@ -192,9 +184,9 @@ int main(void)
|
|||
Motor1.timerflags.motor_telemetry_flag = false;
|
||||
update_telemetry();
|
||||
update_setpoints();
|
||||
//PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
|
||||
//DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
//DMAC->Channel[1].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
|
||||
DMAC->Channel[DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
DMAC->Channel[DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
//_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, false);
|
||||
//_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, false);
|
||||
|
||||
|
|
|
|||
|
|
@ -113,7 +113,7 @@ drivers:
|
|||
adc_arch_refcomp: false
|
||||
adc_arch_resrdyeo: true
|
||||
adc_arch_runstdby: false
|
||||
adc_arch_samplen: 3
|
||||
adc_arch_samplen: 2
|
||||
adc_arch_samplenum: 1 sample
|
||||
adc_arch_seqen: 0
|
||||
adc_arch_startei: false
|
||||
|
|
@ -309,7 +309,7 @@ drivers:
|
|||
api: HAL:HPL:DMAC
|
||||
configuration:
|
||||
dmac_beatsize_0: 8-bit bus transfer
|
||||
dmac_beatsize_1: 8-bit bus transfer
|
||||
dmac_beatsize_1: 16-bit bus transfer
|
||||
dmac_beatsize_10: 8-bit bus transfer
|
||||
dmac_beatsize_11: 8-bit bus transfer
|
||||
dmac_beatsize_12: 8-bit bus transfer
|
||||
|
|
@ -331,7 +331,7 @@ drivers:
|
|||
dmac_beatsize_27: 8-bit bus transfer
|
||||
dmac_beatsize_28: 8-bit bus transfer
|
||||
dmac_beatsize_29: 8-bit bus transfer
|
||||
dmac_beatsize_3: 16-bit bus transfer
|
||||
dmac_beatsize_3: 8-bit bus transfer
|
||||
dmac_beatsize_30: 8-bit bus transfer
|
||||
dmac_beatsize_31: 8-bit bus transfer
|
||||
dmac_beatsize_4: 8-bit bus transfer
|
||||
|
|
@ -343,7 +343,7 @@ drivers:
|
|||
dmac_blockact_0: Channel will be disabled if it is the last block transfer in
|
||||
the transaction
|
||||
dmac_blockact_1: Channel will be disabled if it is the last block transfer in
|
||||
the transaction
|
||||
the transaction and block interrupt
|
||||
dmac_blockact_10: Channel will be disabled if it is the last block transfer
|
||||
in the transaction
|
||||
dmac_blockact_11: Channel will be disabled if it is the last block transfer
|
||||
|
|
@ -386,7 +386,7 @@ drivers:
|
|||
dmac_blockact_29: Channel will be disabled if it is the last block transfer
|
||||
in the transaction
|
||||
dmac_blockact_3: Channel will be disabled if it is the last block transfer in
|
||||
the transaction and block interrupt
|
||||
the transaction
|
||||
dmac_blockact_30: Channel will be disabled if it is the last block transfer
|
||||
in the transaction
|
||||
dmac_blockact_31: Channel will be disabled if it is the last block transfer
|
||||
|
|
@ -437,7 +437,7 @@ drivers:
|
|||
dmac_channel_9_settings: false
|
||||
dmac_dbgrun: false
|
||||
dmac_dstinc_0: true
|
||||
dmac_dstinc_1: false
|
||||
dmac_dstinc_1: true
|
||||
dmac_dstinc_10: false
|
||||
dmac_dstinc_11: false
|
||||
dmac_dstinc_12: false
|
||||
|
|
@ -459,7 +459,7 @@ drivers:
|
|||
dmac_dstinc_27: false
|
||||
dmac_dstinc_28: false
|
||||
dmac_dstinc_29: false
|
||||
dmac_dstinc_3: true
|
||||
dmac_dstinc_3: false
|
||||
dmac_dstinc_30: false
|
||||
dmac_dstinc_31: false
|
||||
dmac_dstinc_4: false
|
||||
|
|
@ -630,9 +630,9 @@ drivers:
|
|||
dmac_lvl_8: Channel priority 0
|
||||
dmac_lvl_9: Channel priority 0
|
||||
dmac_lvlen0: true
|
||||
dmac_lvlen1: true
|
||||
dmac_lvlen2: true
|
||||
dmac_lvlen3: true
|
||||
dmac_lvlen1: false
|
||||
dmac_lvlen2: false
|
||||
dmac_lvlen3: false
|
||||
dmac_lvlpri0: 0
|
||||
dmac_lvlpri1: 0
|
||||
dmac_lvlpri2: 0
|
||||
|
|
@ -641,8 +641,8 @@ drivers:
|
|||
dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
|
||||
dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
|
||||
dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
|
||||
dmac_runstdby_0: false
|
||||
dmac_runstdby_1: false
|
||||
dmac_runstdby_0: true
|
||||
dmac_runstdby_1: true
|
||||
dmac_runstdby_10: false
|
||||
dmac_runstdby_11: false
|
||||
dmac_runstdby_12: false
|
||||
|
|
@ -653,7 +653,7 @@ drivers:
|
|||
dmac_runstdby_17: false
|
||||
dmac_runstdby_18: false
|
||||
dmac_runstdby_19: false
|
||||
dmac_runstdby_2: false
|
||||
dmac_runstdby_2: true
|
||||
dmac_runstdby_20: false
|
||||
dmac_runstdby_21: false
|
||||
dmac_runstdby_22: false
|
||||
|
|
@ -664,7 +664,7 @@ drivers:
|
|||
dmac_runstdby_27: false
|
||||
dmac_runstdby_28: false
|
||||
dmac_runstdby_29: false
|
||||
dmac_runstdby_3: false
|
||||
dmac_runstdby_3: true
|
||||
dmac_runstdby_30: false
|
||||
dmac_runstdby_31: false
|
||||
dmac_runstdby_4: false
|
||||
|
|
@ -674,7 +674,7 @@ drivers:
|
|||
dmac_runstdby_8: false
|
||||
dmac_runstdby_9: false
|
||||
dmac_srcinc_0: false
|
||||
dmac_srcinc_1: true
|
||||
dmac_srcinc_1: false
|
||||
dmac_srcinc_10: false
|
||||
dmac_srcinc_11: false
|
||||
dmac_srcinc_12: false
|
||||
|
|
@ -696,7 +696,7 @@ drivers:
|
|||
dmac_srcinc_27: false
|
||||
dmac_srcinc_28: false
|
||||
dmac_srcinc_29: false
|
||||
dmac_srcinc_3: false
|
||||
dmac_srcinc_3: true
|
||||
dmac_srcinc_30: false
|
||||
dmac_srcinc_31: false
|
||||
dmac_srcinc_4: false
|
||||
|
|
@ -706,7 +706,7 @@ drivers:
|
|||
dmac_srcinc_8: false
|
||||
dmac_srcinc_9: false
|
||||
dmac_stepsel_0: Step size settings apply to the destination address
|
||||
dmac_stepsel_1: Step size settings apply to the source address
|
||||
dmac_stepsel_1: Step size settings apply to the destination address
|
||||
dmac_stepsel_10: Step size settings apply to the destination address
|
||||
dmac_stepsel_11: Step size settings apply to the destination address
|
||||
dmac_stepsel_12: Step size settings apply to the destination address
|
||||
|
|
@ -728,7 +728,7 @@ drivers:
|
|||
dmac_stepsel_27: Step size settings apply to the destination address
|
||||
dmac_stepsel_28: Step size settings apply to the destination address
|
||||
dmac_stepsel_29: Step size settings apply to the destination address
|
||||
dmac_stepsel_3: Step size settings apply to the destination address
|
||||
dmac_stepsel_3: Step size settings apply to the source address
|
||||
dmac_stepsel_30: Step size settings apply to the destination address
|
||||
dmac_stepsel_31: Step size settings apply to the destination address
|
||||
dmac_stepsel_4: Step size settings apply to the destination address
|
||||
|
|
@ -770,7 +770,7 @@ drivers:
|
|||
dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||
dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
|
||||
dmac_trifsrc_0: SERCOM1 RX Trigger
|
||||
dmac_trifsrc_1: SERCOM1 TX Trigger
|
||||
dmac_trifsrc_1: ADC1 Result Ready Trigger
|
||||
dmac_trifsrc_10: Only software/event triggers
|
||||
dmac_trifsrc_11: Only software/event triggers
|
||||
dmac_trifsrc_12: Only software/event triggers
|
||||
|
|
@ -792,7 +792,7 @@ drivers:
|
|||
dmac_trifsrc_27: Only software/event triggers
|
||||
dmac_trifsrc_28: Only software/event triggers
|
||||
dmac_trifsrc_29: Only software/event triggers
|
||||
dmac_trifsrc_3: ADC1 Result Ready Trigger
|
||||
dmac_trifsrc_3: SERCOM1 TX Trigger
|
||||
dmac_trifsrc_30: Only software/event triggers
|
||||
dmac_trifsrc_31: Only software/event triggers
|
||||
dmac_trifsrc_4: Only software/event triggers
|
||||
|
|
|
|||
|
|
@ -502,7 +502,7 @@
|
|||
// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
|
||||
// <id> adc_arch_samplen
|
||||
#ifndef CONF_ADC_1_SAMPLEN
|
||||
#define CONF_ADC_1_SAMPLEN 3
|
||||
#define CONF_ADC_1_SAMPLEN 2
|
||||
#endif
|
||||
|
||||
// <o> Window Monitor Mode
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@
|
|||
// <i> Indicates whether Priority Level 1 is enabled or not
|
||||
// <id> dmac_lvlen1
|
||||
#ifndef CONF_DMAC_LVLEN1
|
||||
#define CONF_DMAC_LVLEN1 1
|
||||
#define CONF_DMAC_LVLEN1 0
|
||||
#endif
|
||||
|
||||
// <o> Level 1 Round-Robin Arbitration
|
||||
|
|
@ -57,7 +57,7 @@
|
|||
// <i> Indicates whether Priority Level 2 is enabled or not
|
||||
// <id> dmac_lvlen2
|
||||
#ifndef CONF_DMAC_LVLEN2
|
||||
#define CONF_DMAC_LVLEN2 1
|
||||
#define CONF_DMAC_LVLEN2 0
|
||||
#endif
|
||||
|
||||
// <o> Level 2 Round-Robin Arbitration
|
||||
|
|
@ -78,7 +78,7 @@
|
|||
// <i> Indicates whether Priority Level 3 is enabled or not
|
||||
// <id> dmac_lvlen3
|
||||
#ifndef CONF_DMAC_LVLEN3
|
||||
#define CONF_DMAC_LVLEN3 1
|
||||
#define CONF_DMAC_LVLEN3 0
|
||||
#endif
|
||||
|
||||
// <o> Level 3 Round-Robin Arbitration
|
||||
|
|
@ -112,7 +112,7 @@
|
|||
// <i> Indicates whether channel 0 is running in standby mode or not
|
||||
// <id> dmac_runstdby_0
|
||||
#ifndef CONF_DMAC_RUNSTDBY_0
|
||||
#define CONF_DMAC_RUNSTDBY_0 0
|
||||
#define CONF_DMAC_RUNSTDBY_0 1
|
||||
#endif
|
||||
|
||||
// <o> Trigger action
|
||||
|
|
@ -336,7 +336,7 @@
|
|||
// <i> Indicates whether channel 1 is running in standby mode or not
|
||||
// <id> dmac_runstdby_1
|
||||
#ifndef CONF_DMAC_RUNSTDBY_1
|
||||
#define CONF_DMAC_RUNSTDBY_1 0
|
||||
#define CONF_DMAC_RUNSTDBY_1 1
|
||||
#endif
|
||||
|
||||
// <o> Trigger action
|
||||
|
|
@ -438,7 +438,7 @@
|
|||
// <i> Defines the peripheral trigger which is source of the transfer
|
||||
// <id> dmac_trifsrc_1
|
||||
#ifndef CONF_DMAC_TRIGSRC_1
|
||||
#define CONF_DMAC_TRIGSRC_1 7
|
||||
#define CONF_DMAC_TRIGSRC_1 70
|
||||
#endif
|
||||
|
||||
// <o> Channel Arbitration Level
|
||||
|
|
@ -501,21 +501,21 @@
|
|||
// <i> Defines whether source or destination addresses are using the step size settings
|
||||
// <id> dmac_stepsel_1
|
||||
#ifndef CONF_DMAC_STEPSEL_1
|
||||
#define CONF_DMAC_STEPSEL_1 1
|
||||
#define CONF_DMAC_STEPSEL_1 0
|
||||
#endif
|
||||
|
||||
// <q> Source Address Increment
|
||||
// <i> Indicates whether the source address incrementation is enabled or not
|
||||
// <id> dmac_srcinc_1
|
||||
#ifndef CONF_DMAC_SRCINC_1
|
||||
#define CONF_DMAC_SRCINC_1 1
|
||||
#define CONF_DMAC_SRCINC_1 0
|
||||
#endif
|
||||
|
||||
// <q> Destination Address Increment
|
||||
// <i> Indicates whether the destination address incrementation is enabled or not
|
||||
// <id> dmac_dstinc_1
|
||||
#ifndef CONF_DMAC_DSTINC_1
|
||||
#define CONF_DMAC_DSTINC_1 0
|
||||
#define CONF_DMAC_DSTINC_1 1
|
||||
#endif
|
||||
|
||||
// <o> Beat Size
|
||||
|
|
@ -525,7 +525,7 @@
|
|||
// <i> Defines the size of one beat
|
||||
// <id> dmac_beatsize_1
|
||||
#ifndef CONF_DMAC_BEATSIZE_1
|
||||
#define CONF_DMAC_BEATSIZE_1 0
|
||||
#define CONF_DMAC_BEATSIZE_1 1
|
||||
#endif
|
||||
|
||||
// <o> Block Action
|
||||
|
|
@ -536,7 +536,7 @@
|
|||
// <i> Defines the the DMAC should take after a block transfer has completed
|
||||
// <id> dmac_blockact_1
|
||||
#ifndef CONF_DMAC_BLOCKACT_1
|
||||
#define CONF_DMAC_BLOCKACT_1 0
|
||||
#define CONF_DMAC_BLOCKACT_1 1
|
||||
#endif
|
||||
|
||||
// <o> Event Output Selection
|
||||
|
|
@ -560,7 +560,7 @@
|
|||
// <i> Indicates whether channel 2 is running in standby mode or not
|
||||
// <id> dmac_runstdby_2
|
||||
#ifndef CONF_DMAC_RUNSTDBY_2
|
||||
#define CONF_DMAC_RUNSTDBY_2 0
|
||||
#define CONF_DMAC_RUNSTDBY_2 1
|
||||
#endif
|
||||
|
||||
// <o> Trigger action
|
||||
|
|
@ -784,7 +784,7 @@
|
|||
// <i> Indicates whether channel 3 is running in standby mode or not
|
||||
// <id> dmac_runstdby_3
|
||||
#ifndef CONF_DMAC_RUNSTDBY_3
|
||||
#define CONF_DMAC_RUNSTDBY_3 0
|
||||
#define CONF_DMAC_RUNSTDBY_3 1
|
||||
#endif
|
||||
|
||||
// <o> Trigger action
|
||||
|
|
@ -886,7 +886,7 @@
|
|||
// <i> Defines the peripheral trigger which is source of the transfer
|
||||
// <id> dmac_trifsrc_3
|
||||
#ifndef CONF_DMAC_TRIGSRC_3
|
||||
#define CONF_DMAC_TRIGSRC_3 70
|
||||
#define CONF_DMAC_TRIGSRC_3 7
|
||||
#endif
|
||||
|
||||
// <o> Channel Arbitration Level
|
||||
|
|
@ -949,21 +949,21 @@
|
|||
// <i> Defines whether source or destination addresses are using the step size settings
|
||||
// <id> dmac_stepsel_3
|
||||
#ifndef CONF_DMAC_STEPSEL_3
|
||||
#define CONF_DMAC_STEPSEL_3 0
|
||||
#define CONF_DMAC_STEPSEL_3 1
|
||||
#endif
|
||||
|
||||
// <q> Source Address Increment
|
||||
// <i> Indicates whether the source address incrementation is enabled or not
|
||||
// <id> dmac_srcinc_3
|
||||
#ifndef CONF_DMAC_SRCINC_3
|
||||
#define CONF_DMAC_SRCINC_3 0
|
||||
#define CONF_DMAC_SRCINC_3 1
|
||||
#endif
|
||||
|
||||
// <q> Destination Address Increment
|
||||
// <i> Indicates whether the destination address incrementation is enabled or not
|
||||
// <id> dmac_dstinc_3
|
||||
#ifndef CONF_DMAC_DSTINC_3
|
||||
#define CONF_DMAC_DSTINC_3 1
|
||||
#define CONF_DMAC_DSTINC_3 0
|
||||
#endif
|
||||
|
||||
// <o> Beat Size
|
||||
|
|
@ -973,7 +973,7 @@
|
|||
// <i> Defines the size of one beat
|
||||
// <id> dmac_beatsize_3
|
||||
#ifndef CONF_DMAC_BEATSIZE_3
|
||||
#define CONF_DMAC_BEATSIZE_3 1
|
||||
#define CONF_DMAC_BEATSIZE_3 0
|
||||
#endif
|
||||
|
||||
// <o> Block Action
|
||||
|
|
@ -984,7 +984,7 @@
|
|||
// <i> Defines the the DMAC should take after a block transfer has completed
|
||||
// <id> dmac_blockact_3
|
||||
#ifndef CONF_DMAC_BLOCKACT_3
|
||||
#define CONF_DMAC_BLOCKACT_3 1
|
||||
#define CONF_DMAC_BLOCKACT_3 0
|
||||
#endif
|
||||
|
||||
// <o> Event Output Selection
|
||||
|
|
|
|||
|
|
@ -209,10 +209,10 @@
|
|||
<AcmeProjectActionInfo Action="File" Source="bosch_sensor_main.h" IsConfig="false" Hash="riKo9R29boLAR/R3G/0bdw" />
|
||||
<AcmeProjectActionInfo Action="File" Source="atmel_start.h" IsConfig="false" Hash="VZC7DgC4gqnis/WYR1EMzQ" />
|
||||
<AcmeProjectActionInfo Action="File" Source="atmel_start.c" IsConfig="false" Hash="ZSBXIMLBuZ+jGf34dOaZDg" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="XAOTvk5xMalucgzL/ILTWw" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="xpUWpQK+5c6kRc3rDlR+Qw" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="SAFPygs5WrLFsCGH+k+xAQ" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="fD/O4h+JMsc7H2g0bo8JyQ" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="xGTWc3ZL07K/tP/YF7YzPw" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="/3bNiu/UgpvPbmvfRA+w3g" />
|
||||
<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
|
||||
|
|
@ -389,7 +389,6 @@
|
|||
<armgcc.compiler.directories.IncludePaths>
|
||||
<ListValues>
|
||||
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
|
||||
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
|
||||
<Value>../Config</Value>
|
||||
<Value>../</Value>
|
||||
<Value>../examples</Value>
|
||||
|
|
@ -414,12 +413,13 @@
|
|||
<Value>../hpl/tcc</Value>
|
||||
<Value>../hri</Value>
|
||||
<Value>../bosch_sensor</Value>
|
||||
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
|
||||
</ListValues>
|
||||
</armgcc.compiler.directories.IncludePaths>
|
||||
<armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
|
||||
<armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
|
||||
<armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
|
||||
<armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
|
||||
<armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
|
||||
<armgcc.linker.general.UseNewlibNano>True</armgcc.linker.general.UseNewlibNano>
|
||||
<armgcc.linker.libraries.Libraries>
|
||||
<ListValues>
|
||||
|
|
@ -440,7 +440,6 @@
|
|||
<armgcc.assembler.general.IncludePaths>
|
||||
<ListValues>
|
||||
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
|
||||
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
|
||||
<Value>../Config</Value>
|
||||
<Value>../</Value>
|
||||
<Value>../examples</Value>
|
||||
|
|
@ -465,13 +464,13 @@
|
|||
<Value>../hpl/tcc</Value>
|
||||
<Value>../hri</Value>
|
||||
<Value>../bosch_sensor</Value>
|
||||
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
|
||||
</ListValues>
|
||||
</armgcc.assembler.general.IncludePaths>
|
||||
<armgcc.assembler.debugging.DebugLevel>Default (-g)</armgcc.assembler.debugging.DebugLevel>
|
||||
<armgcc.preprocessingassembler.general.IncludePaths>
|
||||
<ListValues>
|
||||
<Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
|
||||
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
|
||||
<Value>../Config</Value>
|
||||
<Value>../</Value>
|
||||
<Value>../examples</Value>
|
||||
|
|
@ -496,6 +495,7 @@
|
|||
<Value>../hpl/tcc</Value>
|
||||
<Value>../hri</Value>
|
||||
<Value>../bosch_sensor</Value>
|
||||
<Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
|
||||
</ListValues>
|
||||
</armgcc.preprocessingassembler.general.IncludePaths>
|
||||
<armgcc.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcc.preprocessingassembler.debugging.DebugLevel>
|
||||
|
|
|
|||
|
|
@ -35,10 +35,10 @@ void motor_StateMachine(BLDCMotor_t* const motor)
|
|||
case MOTOR_IDLE:
|
||||
//hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw, DISABLE_PATTERN);
|
||||
motor->motor_state.previousstate = motor->motor_state.currentstate;
|
||||
//motor->motor_state.currentstate = MOTOR_PVI_CTRL_STATE;
|
||||
motor->motor_state.currentstate = MOTOR_PVI_CTRL_STATE;
|
||||
break;
|
||||
case MOTOR_OPEN_LOOP_STATE:
|
||||
BLDC_runOpenLoop(motor, *M1_Desired_dc);
|
||||
BLDC_runOpenLoop(motor, 0);
|
||||
calculate_motor_speed(motor);
|
||||
motor->motor_state.previousstate = motor->motor_state.currentstate;
|
||||
break;
|
||||
|
|
@ -104,6 +104,7 @@ void BldcInitStruct(BLDCMotor_t* const motor, BLDCMotor_param_t * const motor_pa
|
|||
motor->motor_status.actualDirection = 0;
|
||||
motor->motor_status.duty_cycle = 0;
|
||||
motor->motor_status.calc_rpm = 0;
|
||||
//motor->motor_status.abs_position = 0;
|
||||
motor->motor_status.Num_Steps = 0;
|
||||
motor->motor_status.cur_comm_step = 0;
|
||||
motor->motor_status.currentHallPattern = 1;
|
||||
|
|
@ -238,7 +239,8 @@ void exec_commutation(BLDCMotor_t* const motor)
|
|||
// ----------------------------------------------------------------------
|
||||
//hri_tcc_write_CCBUF_CCBUF_bf(motor->motor_param->pwm_desc->device.hw, 0, motor->motor_status.duty_cycle);
|
||||
tmp->CCBUF[0].reg = (uint32_t)motor->motor_status.duty_cycle;
|
||||
|
||||
|
||||
|
||||
volatile uint8_t cur_comm_step = MOTOR_COMMUTATION_STEPS[currentHall];
|
||||
motor->motor_status.cur_comm_step = cur_comm_step;
|
||||
volatile int8_t step_change = (cur_comm_step - motor->motor_status.prev_comm_step);
|
||||
|
|
@ -379,7 +381,9 @@ void BLDC_runCurrentCntl(BLDCMotor_t *motor, const float32_t curfbk, const float
|
|||
}
|
||||
|
||||
volatile float32_t duty_pu = f_abs((motor->controllers.Pi_Idc.Out_pu * motor->VoneByDcBus_pu));
|
||||
motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
|
||||
//motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
|
||||
//motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
|
||||
motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * motor->motor_param->motor_MaxPWM, 0.0f, (float32_t)MAX_PWM);
|
||||
// Remove Low duty cycle values
|
||||
//if(duty_cycle < 80.0) motor->duty_cycle = (uint16_t)0;
|
||||
//else motor->duty_cycle = (uint16_t)duty_cycle;
|
||||
|
|
@ -457,7 +461,7 @@ volatile uint8_t readHallSensorM1(void)
|
|||
motor_read = (motor_read & M1_HALL_B_MASK) | (uint8_t)((PORT->Group[M1_HALL_B_GROUP].IN.reg & M1_HALL_B_PORT)>>(M1_HALL_B_LSR));
|
||||
motor_read = (motor_read & M1_HALL_C_MASK) | (uint8_t)((PORT->Group[M1_HALL_C_GROUP].IN.reg & M1_HALL_C_PORT)>>(M1_HALL_C_LSR));
|
||||
return motor_read;
|
||||
//
|
||||
|
||||
//volatile uint8_t a = gpio_get_pin_level(M1_HALL_A_PIN);
|
||||
//volatile uint8_t b = gpio_get_pin_level(M1_HALL_B_PIN);
|
||||
//volatile uint8_t c = gpio_get_pin_level(M1_HALL_C_PIN);
|
||||
|
|
@ -469,13 +473,13 @@ volatile uint8_t readHallSensorM1(void)
|
|||
|
||||
volatile uint8_t readHallSensorM2(void)
|
||||
{
|
||||
|
||||
volatile uint8_t motor_read = 0;
|
||||
motor_read = (motor_read & M2_HALL_A_MASK) | (uint8_t)((PORT->Group[M2_HALL_A_GROUP].IN.reg & M2_HALL_A_PORT)>>(M2_HALL_A_LSR));
|
||||
motor_read = (motor_read & M2_HALL_B_MASK) | (uint8_t)((PORT->Group[M2_HALL_B_GROUP].IN.reg & M2_HALL_B_PORT)>>(M2_HALL_B_LSR));
|
||||
motor_read = (motor_read & M2_HALL_C_MASK) | (uint8_t)((PORT->Group[M2_HALL_C_GROUP].IN.reg & M2_HALL_C_PORT)>>(M2_HALL_C_LSR));
|
||||
motor_read = (motor_read & M2_HALL_A_MASK) | (uint8_t)((PORT->Group[M2_HALL_A_GROUP].IN.reg & M2_HALL_A_PORT)>>(M2_HALL_A_LSR));
|
||||
motor_read = (motor_read & M2_HALL_B_MASK) | (uint8_t)((PORT->Group[M2_HALL_B_GROUP].IN.reg & M2_HALL_B_PORT)>>(M2_HALL_B_LSR));
|
||||
motor_read = (motor_read & M2_HALL_C_MASK) | (uint8_t)((PORT->Group[M2_HALL_C_GROUP].IN.reg & M2_HALL_C_PORT)>>(M2_HALL_C_LSR));
|
||||
|
||||
return motor_read;
|
||||
|
||||
//if(((motor_read == INVALID_HALL_0) || (motor_read == INVALID_HALL_7))) {
|
||||
//Motor2.motor_state.fault = MOTOR_HALLSENSORINVALID;
|
||||
//Motor2.motor_state.currentstate = MOTOR_FAULT;
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
#include "statemachine.h"
|
||||
|
||||
#define PWM_TOP (1000)
|
||||
#define MAX_PWM (300)
|
||||
#define MAX_PWM (800)
|
||||
//#define MAX_VEL 3800
|
||||
|
||||
#define CW (0) //CBA
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
|
||||
// ----------------------------------------------------------------------
|
||||
#define DMAC_CHANNEL_ADC_SEQ 2U
|
||||
#define DMAC_CHANNEL_ADC_SRAM 3U
|
||||
#define DMAC_CHANNEL_ADC_SRAM 1U
|
||||
|
||||
/* Single Ended */
|
||||
//const uint32_t adc_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808};
|
||||
|
|
@ -40,7 +40,7 @@ struct _dma_resource *adc_dmac_sequence_resource;
|
|||
|
||||
/* DMA channel for SPI Slave TX and RX */
|
||||
#define CONF_SERCOM_1_RECEIVE_DMA_CHANNEL 0U
|
||||
#define CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL 1U
|
||||
#define CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL 3U
|
||||
|
||||
//static uint8_t tx_buffer[SLAVE_BUFFER_SIZE] = {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, 0xff, 0xff};
|
||||
|
||||
|
|
|
|||
|
|
@ -87,8 +87,8 @@ void SERCOM1_1_Handler()
|
|||
//SPI_tx_buffer[0] += 1;
|
||||
//tx_buffer[31] += 1;
|
||||
|
||||
DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
DMAC->Channel[1].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
DMAC->Channel[CONF_SERCOM_1_RECEIVE_DMA_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
DMAC->Channel[CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
|
||||
//_dma_enable_transaction(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, false);
|
||||
//_dma_enable_transaction(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, false);
|
||||
|
|
@ -140,6 +140,8 @@ void enable_NVIC_IRQ(void)
|
|||
NVIC_EnableIRQ(TCC1_0_IRQn);
|
||||
//NVIC_EnableIRQ(SERCOM1_3_IRQn);
|
||||
//NVIC_SetPriority(SERCOM1_3_IRQn, 0);
|
||||
NVIC_EnableIRQ(SERCOM1_1_IRQn);
|
||||
NVIC_SetPriority(SERCOM1_1_IRQn, 1);
|
||||
//NVIC_EnableIRQ(SERCOM1_3_IRQn);
|
||||
//NVIC_EnableIRQ(EIC_5_IRQn);
|
||||
}
|
||||
|
|
@ -223,7 +225,7 @@ int main(void)
|
|||
configure_tcc_pwm();
|
||||
adc_sync_enable_channel(&ADC_1, 6);
|
||||
//ECAT_STATE_MACHINE();
|
||||
//adc_init_dma();
|
||||
adc_init_dma();
|
||||
boardToBoardTransferInit();
|
||||
init_spi_slave_dma_descriptors();
|
||||
|
||||
|
|
@ -232,8 +234,8 @@ int main(void)
|
|||
custom_logic_enable();
|
||||
enable_NVIC_IRQ();
|
||||
|
||||
DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
DMAC->Channel[1].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
DMAC->Channel[CONF_SERCOM_1_RECEIVE_DMA_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
DMAC->Channel[CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||
|
||||
//_dma_enable_transaction(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, false);
|
||||
//_dma_enable_transaction(CONF_SERCOM_1_TRANSMIT_DMA_CHANNEL, false);
|
||||
|
|
@ -247,19 +249,19 @@ int main(void)
|
|||
|
||||
/* Replace with your application code */
|
||||
while (1) {
|
||||
//if (Motor1.timerflags.adc_readings_ready_tic) {process_currents();}
|
||||
//if (Motor1.timerflags.current_loop_tic) {
|
||||
//APPLICATION_StateMachine();
|
||||
//exec_commutation(&Motor1);
|
||||
if (Motor1.timerflags.adc_readings_ready_tic) {process_currents();}
|
||||
if (Motor1.timerflags.current_loop_tic) {
|
||||
APPLICATION_StateMachine();
|
||||
exec_commutation(&Motor1);
|
||||
////exec_commutation(&Motor2);
|
||||
//}
|
||||
}
|
||||
|
||||
if (Motor1.timerflags.motor_telemetry_flag) {
|
||||
Motor1.timerflags.motor_telemetry_flag = false;
|
||||
update_telemetry();
|
||||
update_setpoints();
|
||||
APPLICATION_StateMachine();
|
||||
exec_commutation(&Motor1);
|
||||
//APPLICATION_StateMachine();
|
||||
//exec_commutation(&Motor1);
|
||||
//exec_commutation(&Motor2);
|
||||
//*M3_Joint_abs_position = as5048a_getRawRotation(&AS_1);
|
||||
//*M3_Joint_abs_position = as5048a_getRotationDecInt(&AS_1);
|
||||
|
|
|
|||
|
|
@ -133,6 +133,7 @@ typedef struct
|
|||
const float32_t motor_Max_Spd_ELEC;
|
||||
const float32_t motor_Max_Current_IDC_A;
|
||||
MOTOR_Control_Structs controller_param;
|
||||
float32_t motor_MaxPWM;
|
||||
} BLDCMotor_param_t;
|
||||
|
||||
//static BLDCMotor_param_t FH_22mm24BXTR;
|
||||
|
|
@ -152,12 +153,41 @@ const static BLDCMotor_param_t FH_22mm24BXTR = {
|
|||
.motor_Max_Spd_RPM = 3000,
|
||||
.motor_MeasureRange_RPM = 3000 * 1.2, //(1.2f * MOTOR_MAX_SPD_RPM)f // give 20% headroom
|
||||
.motor_Max_Spd_ELEC = (3000/60)*7.0, //(MOTOR_MAX_SPD_RPM/60)*MOTOR_POLEPAIRS
|
||||
.motor_Max_Current_IDC_A = 0.368,
|
||||
//.motor_Max_Current_IDC_A = 0.368,
|
||||
.motor_Max_Current_IDC_A = 0.180,
|
||||
.controller_param.Pid_Speed.Kp = 0.00008f,
|
||||
.controller_param.Pid_Speed.Ki = 0.0000001f,
|
||||
//.controller_param.Pid_Speed.Ki = 0.0000001f,
|
||||
.controller_param.Pi_Pos.Kp = 50.0f,
|
||||
.controller_param.Pi_Pos.Ki = 0.0f,
|
||||
.motor_MaxPWM = 800.0,
|
||||
};
|
||||
|
||||
|
||||
/* Big Motor - 3216W012BXTR */
|
||||
const static BLDCMotor_param_t FH_32mm12BXTR = {
|
||||
.pwm_desc = &PWM_1,
|
||||
.speedtimer_hw = TC4,
|
||||
.motor_Poles = 14,
|
||||
.motor_polePairs = 7,
|
||||
.motor_commutationStates = 42, //polePairs * 6
|
||||
.motor_RS_Ohm = 0.88,
|
||||
.motor_LD_H = 0.000331,
|
||||
.motor_LQ_H = 0.000331,
|
||||
.motor_Flux_WB = 0.0063879968,
|
||||
.motor_Max_Spd_RPM = 1000,
|
||||
.motor_MeasureRange_RPM = 3200, //(1.2f * MOTOR_MAX_SPD_RPM)f // give 20% headroom
|
||||
.motor_Max_Spd_ELEC = 12000, //(MOTOR_MAX_SPD_RPM/60)*MOTOR_POLEPAIRS
|
||||
.motor_Max_Current_IDC_A = (1.2),
|
||||
.controller_param.Pid_Speed.Kp = 0.0004f,
|
||||
.controller_param.Pid_Speed.Ki = 0.0000001f,
|
||||
.controller_param.Pi_Pos.Kp = 50.0f,
|
||||
.controller_param.Pi_Pos.Ki = 0.000f,
|
||||
//.controller_param.Pid_Speed.Kp = 0.00002f,
|
||||
//.controller_param.Pid_Speed.Ki = 0.0f,
|
||||
//.controller_param.Pi_Pos.Kp = 4.0f,
|
||||
//.controller_param.Pi_Pos.Ki = 0.0f,
|
||||
.motor_MaxPWM = 250.0,
|
||||
};
|
||||
|
||||
/* Big Motor - 3216W024BXTR */
|
||||
|
|
@ -179,6 +209,11 @@ const static BLDCMotor_param_t FH_32mm24BXTR = {
|
|||
.controller_param.Pid_Speed.Ki = 0.0000001f,
|
||||
.controller_param.Pi_Pos.Kp = 40.0f,
|
||||
.controller_param.Pi_Pos.Ki = 0.0f,
|
||||
.motor_MaxPWM = 800.0,
|
||||
//.controller_param.Pid_Speed.Kp = 0.00002f,
|
||||
//.controller_param.Pid_Speed.Ki = 0.0f,
|
||||
//.controller_param.Pi_Pos.Kp = 4.0f,
|
||||
//.controller_param.Pi_Pos.Ki = 0.0f,
|
||||
};
|
||||
|
||||
#endif /* MOTORPARAMETERS_H_ */
|
||||
Binary file not shown.
|
|
@ -1102,7 +1102,8 @@ END_VAR
|
|||
<Action Name="_aPOS_1_entry" Id="{0ae03264-b28c-44bd-9cfc-1102ae68301e}">
|
||||
<Implementation>
|
||||
<ST><![CDATA[GVL_motor_data.M1_Desired_pos := 1000;
|
||||
GVL_motor_data.M2_Desired_pos := 1000;]]></ST>
|
||||
GVL_motor_data.M2_Desired_pos := 1000;
|
||||
GVL_motor_data.M3_Desired_pos := 1000;]]></ST>
|
||||
</Implementation>
|
||||
<ObjectProperties>
|
||||
<XmlArchive>
|
||||
|
|
@ -1121,7 +1122,8 @@ GVL_motor_data.M2_Desired_pos := 1000;]]></ST>
|
|||
<Action Name="_aPOS_2_entry" Id="{61315308-5bec-490a-a6bc-fde3430a9e9d}">
|
||||
<Implementation>
|
||||
<ST><![CDATA[GVL_motor_data.M1_Desired_pos := -500;
|
||||
GVL_motor_data.M2_Desired_pos := -500;]]></ST>
|
||||
GVL_motor_data.M2_Desired_pos := -500;
|
||||
GVL_motor_data.M3_Desired_pos := -500;]]></ST>
|
||||
</Implementation>
|
||||
<ObjectProperties>
|
||||
<XmlArchive>
|
||||
|
|
@ -1140,7 +1142,8 @@ GVL_motor_data.M2_Desired_pos := -500;]]></ST>
|
|||
<Action Name="_aPOS_3_entry" Id="{6ad81fe3-5dde-4873-8056-67e52ae14536}">
|
||||
<Implementation>
|
||||
<ST><![CDATA[GVL_motor_data.M1_Desired_pos := 0;
|
||||
GVL_motor_data.M2_Desired_pos := 0;]]></ST>
|
||||
GVL_motor_data.M2_Desired_pos := 0;
|
||||
GVL_motor_data.M3_Desired_pos := 0;]]></ST>
|
||||
</Implementation>
|
||||
<ObjectProperties>
|
||||
<XmlArchive>
|
||||
|
|
@ -1254,14 +1257,17 @@ GVL_motor_data.M2_Desired_pos := 0;]]></ST>
|
|||
<LineIds Name="POU_Position_Seq._aPOS_1_entry">
|
||||
<LineId Id="2" Count="0" />
|
||||
<LineId Id="1" Count="0" />
|
||||
<LineId Id="3" Count="0" />
|
||||
</LineIds>
|
||||
<LineIds Name="POU_Position_Seq._aPOS_2_entry">
|
||||
<LineId Id="2" Count="0" />
|
||||
<LineId Id="1" Count="0" />
|
||||
<LineId Id="3" Count="0" />
|
||||
</LineIds>
|
||||
<LineIds Name="POU_Position_Seq._aPOS_3_entry">
|
||||
<LineId Id="2" Count="0" />
|
||||
<LineId Id="1" Count="0" />
|
||||
<LineId Id="3" Count="0" />
|
||||
</LineIds>
|
||||
</POU>
|
||||
</TcPlcObject>
|
||||
Binary file not shown.
|
|
@ -15,8 +15,8 @@
|
|||
<IsTemplate>false</IsTemplate>
|
||||
<Layout><?xml version="1.0" encoding="utf-16"?>
|
||||
<Layout>
|
||||
<Window Guid="8766837b-106b-4ca8-84ce-2fbbc3ef10f3" LastFocused="132743661535497732" DockedSize="200" PopupSize="0" FloatingLocation="-1, -1" FloatingSize="550, 400" LastOpenDockSituation="Document" LastFixedDockSituation="Document" LastFixedDockLocation="Right" LastFloatingWindowGuid="00000000-0000-0000-0000-000000000000" LastDockContainerCount="0" LastDockContainerIndex="0" DockedWorkingSize="250, 400" DockedWindowGroupGuid="00000000-0000-0000-0000-000000000000" DockedIndexInWindowGroup="0" DockedSplitPath="0" DocumentWorkingSize="250, 400" DocumentWindowGroupGuid="a5d32a52-1886-4ce8-9970-731db69737a6" DocumentIndexInWindowGroup="0" DocumentSplitPath="0" FloatingWorkingSize="250, 400" FloatingWindowGroupGuid="00000000-0000-0000-0000-000000000000" FloatingIndexInWindowGroup="0" FloatingSplitPath="0" />
|
||||
<Window Guid="17812b7c-7d18-4668-ae12-d2633798b279" LastFocused="132743697189178461" DockedSize="200" PopupSize="0" FloatingLocation="-1, -1" FloatingSize="550, 400" LastOpenDockSituation="Document" LastFixedDockSituation="Document" LastFixedDockLocation="Right" LastFloatingWindowGuid="00000000-0000-0000-0000-000000000000" LastDockContainerCount="0" LastDockContainerIndex="0" DockedWorkingSize="250, 400" DockedWindowGroupGuid="00000000-0000-0000-0000-000000000000" DockedIndexInWindowGroup="0" DockedSplitPath="0" DocumentWorkingSize="250, 400" DocumentWindowGroupGuid="a5d32a52-1886-4ce8-9970-731db69737a6" DocumentIndexInWindowGroup="1" DocumentSplitPath="0" FloatingWorkingSize="250, 400" FloatingWindowGroupGuid="00000000-0000-0000-0000-000000000000" FloatingIndexInWindowGroup="0" FloatingSplitPath="0" />
|
||||
<Window Guid="8766837b-106b-4ca8-84ce-2fbbc3ef10f3" LastFocused="132743765367691913" DockedSize="200" PopupSize="0" FloatingLocation="-1, -1" FloatingSize="550, 400" LastOpenDockSituation="Document" LastFixedDockSituation="Document" LastFixedDockLocation="Right" LastFloatingWindowGuid="00000000-0000-0000-0000-000000000000" LastDockContainerCount="0" LastDockContainerIndex="0" DockedWorkingSize="250, 400" DockedWindowGroupGuid="00000000-0000-0000-0000-000000000000" DockedIndexInWindowGroup="0" DockedSplitPath="0" DocumentWorkingSize="250, 400" DocumentWindowGroupGuid="a5d32a52-1886-4ce8-9970-731db69737a6" DocumentIndexInWindowGroup="0" DocumentSplitPath="0" FloatingWorkingSize="250, 400" FloatingWindowGroupGuid="00000000-0000-0000-0000-000000000000" FloatingIndexInWindowGroup="0" FloatingSplitPath="0" />
|
||||
<Window Guid="17812b7c-7d18-4668-ae12-d2633798b279" LastFocused="132743765596671663" DockedSize="200" PopupSize="0" FloatingLocation="-1, -1" FloatingSize="550, 400" LastOpenDockSituation="Document" LastFixedDockSituation="Document" LastFixedDockLocation="Right" LastFloatingWindowGuid="00000000-0000-0000-0000-000000000000" LastDockContainerCount="0" LastDockContainerIndex="0" DockedWorkingSize="250, 400" DockedWindowGroupGuid="00000000-0000-0000-0000-000000000000" DockedIndexInWindowGroup="0" DockedSplitPath="0" DocumentWorkingSize="250, 400" DocumentWindowGroupGuid="a5d32a52-1886-4ce8-9970-731db69737a6" DocumentIndexInWindowGroup="1" DocumentSplitPath="0" FloatingWorkingSize="250, 400" FloatingWindowGroupGuid="00000000-0000-0000-0000-000000000000" FloatingIndexInWindowGroup="0" FloatingSplitPath="0" />
|
||||
<DocumentContainer Dock="5">
|
||||
<SplitLayoutSystem WorkingSize="250, 400" SplitMode="0">
|
||||
<ControlLayoutSystem WorkingSize="250, 400" Guid="a5d32a52-1886-4ce8-9970-731db69737a6" Collapsed="0" SelectedControl="17812b7c-7d18-4668-ae12-d2633798b279">
|
||||
|
|
|
|||
Loading…
Reference in New Issue