nick
/
thesis_bldc_controller
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

before implementing suspend

This commit is contained in:
Nicolas Trimborn 2021-08-31 16:08:12 +02:00
parent 1f5905d213
commit 2d40de8228
17 changed files with 175 additions and 107 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart
View File

@ -440,7 +440,7 @@ drivers:
dmac_evie_17: false dmac_evie_17: false
dmac_evie_18: false dmac_evie_18: false
dmac_evie_19: false dmac_evie_19: false
dmac_evie_2: true dmac_evie_2: false
dmac_evie_20: false dmac_evie_20: false
dmac_evie_21: false dmac_evie_21: false
dmac_evie_22: false dmac_evie_22: false
@ -504,7 +504,7 @@ drivers:
dmac_evosel_17: Event generation disabled dmac_evosel_17: Event generation disabled
dmac_evosel_18: Event generation disabled dmac_evosel_18: Event generation disabled
dmac_evosel_19: Event generation disabled dmac_evosel_19: Event generation disabled
dmac_evosel_2: Event strobe when beat transfer complete dmac_evosel_2: Event strobe when block transfer complete
dmac_evosel_20: Event generation disabled dmac_evosel_20: Event generation disabled
dmac_evosel_21: Event generation disabled dmac_evosel_21: Event generation disabled
dmac_evosel_22: Event generation disabled dmac_evosel_22: Event generation disabled
@ -940,7 +940,7 @@ drivers:
evsys_channel_27: No channel output selected evsys_channel_27: No channel output selected
evsys_channel_28: No channel output selected evsys_channel_28: No channel output selected
evsys_channel_29: No channel output selected evsys_channel_29: No channel output selected
evsys_channel_3: No channel output selected evsys_channel_3: Channel 5
evsys_channel_30: No channel output selected evsys_channel_30: No channel output selected
evsys_channel_31: No channel output selected evsys_channel_31: No channel output selected
evsys_channel_32: No channel output selected evsys_channel_32: No channel output selected
@ -1011,7 +1011,7 @@ drivers:
evsys_channel_setting_30: false evsys_channel_setting_30: false
evsys_channel_setting_31: false evsys_channel_setting_31: false
evsys_channel_setting_4: true evsys_channel_setting_4: true
evsys_channel_setting_5: true evsys_channel_setting_5: false
evsys_channel_setting_6: false evsys_channel_setting_6: false
evsys_channel_setting_7: false evsys_channel_setting_7: false
evsys_channel_setting_8: false evsys_channel_setting_8: false
@ -1344,11 +1344,11 @@ drivers:
functionality: System functionality: System
api: HAL:HPL:GCLK api: HAL:HPL:GCLK
configuration: configuration:
$input: 12000000 $input: 100000000
$input_id: External Crystal Oscillator 8-48MHz (XOSC1) $input_id: Digital Phase Locked Loop (DPLL1)
RESERVED_InputFreq: 12000000 RESERVED_InputFreq: 100000000
RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1) RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL1)
_$freq_output_Generic clock generator 0: 120000000 _$freq_output_Generic clock generator 0: 100000000
_$freq_output_Generic clock generator 1: 2000000 _$freq_output_Generic clock generator 1: 2000000
_$freq_output_Generic clock generator 10: 12000000 _$freq_output_Generic clock generator 10: 12000000
_$freq_output_Generic clock generator 11: 12000000 _$freq_output_Generic clock generator 11: 12000000
@ -1490,11 +1490,11 @@ drivers:
functionality: System functionality: System
api: HAL:HPL:MCLK api: HAL:HPL:MCLK
configuration: configuration:
$input: 120000000 $input: 100000000
$input_id: Generic clock generator 0 $input_id: Generic clock generator 0
RESERVED_InputFreq: 120000000 RESERVED_InputFreq: 100000000
RESERVED_InputFreq_id: Generic clock generator 0 RESERVED_InputFreq_id: Generic clock generator 0
_$freq_output_CPU: 120000000 _$freq_output_CPU: 100000000
cpu_clock_source: Generic clock generator 0 cpu_clock_source: Generic clock generator 0
cpu_div: '1' cpu_div: '1'
enable_cpu_clock: true enable_cpu_clock: true
@ -1557,7 +1557,7 @@ drivers:
RESERVED_InputFreq_id: Generic clock generator 1 RESERVED_InputFreq_id: Generic clock generator 1
_$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000 _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
_$freq_output_Digital Phase Locked Loop (DPLL0): 47985664 _$freq_output_Digital Phase Locked Loop (DPLL0): 47985664
_$freq_output_Digital Phase Locked Loop (DPLL1): 120000000 _$freq_output_Digital Phase Locked Loop (DPLL1): 100000000
_$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000 _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000
_$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000 _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000
dfll_arch_bplckc: false dfll_arch_bplckc: false
@ -1608,7 +1608,7 @@ drivers:
fdpll1_arch_wuf: false fdpll1_arch_wuf: false
fdpll1_clock_dcofilter: 0 fdpll1_clock_dcofilter: 0
fdpll1_clock_div: 0 fdpll1_clock_div: 0
fdpll1_ldr: 59 fdpll1_ldr: 49
fdpll1_ldrfrac: 0 fdpll1_ldrfrac: 0
fdpll1_ref_clock: Generic clock generator 1 fdpll1_ref_clock: Generic clock generator 1
xosc0_arch_cfden: false xosc0_arch_cfden: false
@ -1647,11 +1647,11 @@ drivers:
enable_port_input_event_3: false enable_port_input_event_3: false
porta_event_action_0: Output register of pin will be set to level of event porta_event_action_0: Output register of pin will be set to level of event
porta_event_action_1: Output register of pin will be set to level of event porta_event_action_1: Output register of pin will be set to level of event
porta_event_action_2: Output register of pin will be set to level of event porta_event_action_2: Set output register of pin on event
porta_event_action_3: Output register of pin will be set to level of event porta_event_action_3: Output register of pin will be set to level of event
porta_event_pin_identifier_0: 0 porta_event_pin_identifier_0: 0
porta_event_pin_identifier_1: 0 porta_event_pin_identifier_1: 0
porta_event_pin_identifier_2: 0 porta_event_pin_identifier_2: 14
porta_event_pin_identifier_3: 0 porta_event_pin_identifier_3: 0
porta_input_event_enable_0: false porta_input_event_enable_0: false
porta_input_event_enable_1: false porta_input_event_enable_1: false
@ -1802,9 +1802,9 @@ drivers:
spi_master_arch_cpol: SCK is low when idle spi_master_arch_cpol: SCK is low when idle
spi_master_arch_dbgstop: Keep running spi_master_arch_dbgstop: Keep running
spi_master_arch_dord: MSB first spi_master_arch_dord: MSB first
spi_master_arch_ibon: In data stream spi_master_arch_ibon: On buffer overflow
spi_master_arch_runstdby: false spi_master_arch_runstdby: false
spi_master_baud_rate: 4000000 spi_master_baud_rate: 1000000
spi_master_character_size: 8 bits spi_master_character_size: 8 bits
spi_master_dummybyte: 511 spi_master_dummybyte: 511
spi_master_rx_enable: true spi_master_rx_enable: true
@ -1848,7 +1848,7 @@ drivers:
spi_master_arch_dord: MSB first spi_master_arch_dord: MSB first
spi_master_arch_ibon: In data stream spi_master_arch_ibon: In data stream
spi_master_arch_runstdby: false spi_master_arch_runstdby: false
spi_master_baud_rate: 8000000 spi_master_baud_rate: 1000000
spi_master_character_size: 8 bits spi_master_character_size: 8 bits
spi_master_dummybyte: 511 spi_master_dummybyte: 511
spi_master_rx_enable: true spi_master_rx_enable: true

38
2_Motor_Master/Motor_Master/Motor_Master/ADS1299.c
View File

@ -72,8 +72,8 @@ void initialize_ads()
ADS1299_WREG(LOFF,0x02); // Set LOFF Register ADS1299_WREG(LOFF,0x02); // Set LOFF Register
for(uint8_t i=CH1SET; i<=CH4SET; i++) // set up to modify the 4 channel setting registers for(uint8_t i=CH1SET; i<=CH4SET; i++) // set up to modify the 4 channel setting registers
{ {
ADS1299.regData[i] = 0x68; // the regData array mirrors the ADS1299 register addresses //ADS1299.reg_data[i] = 0x68; // the regData array mirrors the ADS1299 register addresses
//ADS1299.regData[i] = 0x6D; // Test signal ADS1299.reg_data[i] = 0x6D; // Test signal
} }
ADS1299_WREGS(CH1SET,3); // write new channel settings ADS1299_WREGS(CH1SET,3); // write new channel settings
ADS1299_WREG(BIAS_SENSP,0xFF); // Set BIAS_SENSP Register ADS1299_WREG(BIAS_SENSP,0xFF); // Set BIAS_SENSP Register
@ -120,8 +120,22 @@ void ADS1299_START() { //start data conversion
gpio_set_pin_level(ADS1299.SS_pin, false); gpio_set_pin_level(ADS1299.SS_pin, false);
_transfer_byte(ADS1299.SPI_descr, _START); _transfer_byte(ADS1299.SPI_descr, _START);
gpio_set_pin_level(ADS1299.SS_pin, true); gpio_set_pin_level(ADS1299.SS_pin, true);
delay_us(20);
init_streaming_mode();
} }
void init_streaming_mode()
{
spi_m_sync_disable(ADS1299.SPI_descr);
/* Change to 32-Bit Mode */
SERCOM2->SPI.CTRLC.bit.ICSPACE = 4;
SERCOM2->SPI.CTRLC.bit.DATA32B= true;
SERCOM2->SPI.LENGTH.bit.LENEN = true;
SERCOM2->SPI.LENGTH.bit.LEN = 3;
/* Init SPI*/
spi_m_sync_enable(ADS1299.SPI_descr);
}
void ADS1299_STOP() { //stop data conversion void ADS1299_STOP() { //stop data conversion
gpio_set_pin_level(ADS1299.SS_pin, false); gpio_set_pin_level(ADS1299.SS_pin, false);
_transfer_byte(ADS1299.SPI_descr, _STOP); _transfer_byte(ADS1299.SPI_descr, _STOP);
@ -151,9 +165,9 @@ uint8_t ADS1299_RREG(uint8_t _address)
gpio_set_pin_level(ADS1299.SS_pin, false); gpio_set_pin_level(ADS1299.SS_pin, false);
_transfer_byte(ADS1299.SPI_descr, opcode1); _transfer_byte(ADS1299.SPI_descr, opcode1);
_transfer_byte(ADS1299.SPI_descr, 0x00); _transfer_byte(ADS1299.SPI_descr, 0x00);
ADS1299.regData[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00); ADS1299.reg_data[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00);
gpio_set_pin_level(ADS1299.SS_pin, true); gpio_set_pin_level(ADS1299.SS_pin, true);
return ADS1299.regData[_address]; return ADS1299.reg_data[_address];
} }
// Read more than one register starting at _address // Read more than one register starting at _address
@ -164,7 +178,7 @@ void ADS1299_RREGS(uint8_t _address, uint8_t _numRegistersMinusOne)
_transfer_byte(ADS1299.SPI_descr, opcode1); _transfer_byte(ADS1299.SPI_descr, opcode1);
_transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne); _transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne);
for(int i = 0; i <= _numRegistersMinusOne; i++){ // add register uint8_t to mirror array for(int i = 0; i <= _numRegistersMinusOne; i++){ // add register uint8_t to mirror array
ADS1299.regData[_address + i] = _transfer_byte(ADS1299.SPI_descr, 0x00); ADS1299.reg_data[_address + i] = _transfer_byte(ADS1299.SPI_descr, 0x00);
} }
//ADS1299.regData[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00); //ADS1299.regData[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00);
gpio_set_pin_level(ADS1299.SS_pin, true); gpio_set_pin_level(ADS1299.SS_pin, true);
@ -177,7 +191,7 @@ void ADS1299_WREG(uint8_t _address, uint8_t _value) { // Write ONE register
_transfer_byte(ADS1299.SPI_descr, 0x00); // Send number of registers to read -1 _transfer_byte(ADS1299.SPI_descr, 0x00); // Send number of registers to read -1
_transfer_byte(ADS1299.SPI_descr, _value); // Write the value to the register _transfer_byte(ADS1299.SPI_descr, _value); // Write the value to the register
gpio_set_pin_level(ADS1299.SS_pin, true); // close SPI gpio_set_pin_level(ADS1299.SS_pin, true); // close SPI
ADS1299.regData[_address] = _value; // update the mirror array ADS1299.reg_data[_address] = _value; // update the mirror array
} }
void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne) { void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne) {
@ -186,7 +200,7 @@ void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne) {
_transfer_byte(ADS1299.SPI_descr, opcode1); // Send WREG command & address _transfer_byte(ADS1299.SPI_descr, opcode1); // Send WREG command & address
_transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne); // Send number of registers to read -1 _transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne); // Send number of registers to read -1
for (int i=_address; i <=(_address + _numRegistersMinusOne); i++){ for (int i=_address; i <=(_address + _numRegistersMinusOne); i++){
_transfer_byte(ADS1299.SPI_descr, ADS1299.regData[i]); // Write to the registers _transfer_byte(ADS1299.SPI_descr, ADS1299.reg_data[i]); // Write to the registers
} }
gpio_set_pin_level(ADS1299.SS_pin, true); // close SPI gpio_set_pin_level(ADS1299.SS_pin, true); // close SPI
} }
@ -268,7 +282,7 @@ int32_t* ADS1299_UPDATECHANNELDATA()
for(int i = 0; i<8; i++){ for(int i = 0; i<8; i++){
for(int j=0; j<3; j++){ // read 24 bits of channel data from 1st ADS in 8 3 byte chunks for(int j=0; j<3; j++){ // read 24 bits of channel data from 1st ADS in 8 3 byte chunks
inByte = _transfer_byte(ADS1299.SPI_descr, 0x00); inByte = _transfer_byte(ADS1299.SPI_descr, 0x00);
_channel_data[i] = (_channel_data[i]<<8) | inByte; _ads1299_channel_data[i] = (_ads1299_channel_data[i]<<8) | inByte;
} }
} }
@ -276,13 +290,13 @@ int32_t* ADS1299_UPDATECHANNELDATA()
//reformat the numbers //reformat the numbers
for(int i=0; i<nchan; i++){ // convert 3 byte 2's compliment to 4 byte 2's compliment for(int i=0; i<nchan; i++){ // convert 3 byte 2's compliment to 4 byte 2's compliment
if(bitRead(_channel_data[i],23) == 1){ if(bitRead(_ads1299_channel_data[i],23) == 1){
_channel_data[i] |= 0xFF000000; _ads1299_channel_data[i] |= 0xFF000000;
}else{ }else{
_channel_data[i] &= 0x00FFFFFF; _ads1299_channel_data[i] &= 0x00FFFFFF;
} }
} }
return &_channel_data; return &_ads1299_channel_data;
} }
uint8_t _transfer_byte(struct spi_m_sync_descriptor *spi, uint8_t command) uint8_t _transfer_byte(struct spi_m_sync_descriptor *spi, uint8_t command)

13
2_Motor_Master/Motor_Master/Motor_Master/ADS1299.h
View File

@ -52,9 +52,11 @@
#define MISC2 0x16 #define MISC2 0x16
#define CONFIG4 0x17 #define CONFIG4 0x17
volatile int32_t _channel_data[8]; #define ADS_BUFFER_SIZE 9
volatile uint32_t ads1299_buffer[6];
volatile int32_t _ads1299_channel_data[9];
volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
volatile uint8_t _ads1299_reg_data[24];
/* Struct Definitions */ /* Struct Definitions */
volatile struct SPI_ADS1299 { volatile struct SPI_ADS1299 {
@ -62,7 +64,7 @@ volatile struct SPI_ADS1299 {
volatile bool data_ReadyFlag; volatile bool data_ReadyFlag;
volatile uint32_t SS_pin; volatile uint32_t SS_pin;
volatile uint32_t reset_pin; volatile uint32_t reset_pin;
volatile uint8_t regData [24]; volatile uint8_t* reg_data;
volatile int32_t* channel_data; volatile int32_t* channel_data;
volatile int16_t stat_1; volatile int16_t stat_1;
}; };
@ -72,11 +74,12 @@ static volatile struct SPI_ADS1299 ADS1299 = {
.data_ReadyFlag = false, .data_ReadyFlag = false,
.SS_pin = SPI2_SS, .SS_pin = SPI2_SS,
.reset_pin = ADS_RESET, .reset_pin = ADS_RESET,
.regData = {0}, .reg_data = &_ads1299_reg_data[0],
.channel_data = &_channel_data[0], .channel_data = &_ads1299_channel_data[0],
}; };
void initialize_ads(); void initialize_ads();
void init_streaming_mode();
//ADS1299 SPI Command Definitions (Datasheet, p35) //ADS1299 SPI Command Definitions (Datasheet, p35)
//System Commands //System Commands

4
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_dmac_config.h
View File

@ -687,7 +687,7 @@
// <i> Indicates whether channel event reception is enabled or not // <i> Indicates whether channel event reception is enabled or not
// <id> dmac_evie_2 // <id> dmac_evie_2
#ifndef CONF_DMAC_EVIE_2 #ifndef CONF_DMAC_EVIE_2
#define CONF_DMAC_EVIE_2 1 #define CONF_DMAC_EVIE_2 0
#endif #endif
// <o> Event Input Action // <o> Event Input Action
@ -770,7 +770,7 @@
// <i> Defines the event output selection // <i> Defines the event output selection
// <id> dmac_evosel_2 // <id> dmac_evosel_2
#ifndef CONF_DMAC_EVOSEL_2 #ifndef CONF_DMAC_EVOSEL_2
#define CONF_DMAC_EVOSEL_2 3 #define CONF_DMAC_EVOSEL_2 1
#endif #endif
// </e> // </e>

4
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_evsys_config.h
View File

@ -912,7 +912,7 @@
// <e> Channel 5 settings // <e> Channel 5 settings
// <id> evsys_channel_setting_5 // <id> evsys_channel_setting_5
#ifndef CONF_EVSYS_CHANNEL_SETTINGS_5 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_5
#define CONF_EVSYS_CHANNEL_SETTINGS_5 1 #define CONF_EVSYS_CHANNEL_SETTINGS_5 0
#endif #endif
// <y> Edge detection // <y> Edge detection
@ -5960,7 +5960,7 @@
// <id> evsys_channel_3 // <id> evsys_channel_3
// <i> Indicates which channel is chosen for user // <i> Indicates which channel is chosen for user
#ifndef CONF_CHANNEL_3 #ifndef CONF_CHANNEL_3
#define CONF_CHANNEL_3 0 #define CONF_CHANNEL_3 6
#endif #endif
// <o> Channel selection for PORT event 3 // <o> Channel selection for PORT event 3

2
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_oscctrl_config.h
View File

@ -568,7 +568,7 @@
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register // <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll1_ldr // <id> fdpll1_ldr
#ifndef CONF_FDPLL1_LDR #ifndef CONF_FDPLL1_LDR
#define CONF_FDPLL1_LDR 0x3b #define CONF_FDPLL1_LDR 0x31
#endif #endif
// <o> Clock Divider <0x0-0x7FF> // <o> Clock Divider <0x0-0x7FF>

4
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_port_config.h
View File

@ -153,7 +153,7 @@
// <i> These bits define the I/O pin from port A on which the event action will be performed // <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_2 // <id> porta_event_pin_identifier_2
#ifndef CONF_PORTA_EVCTRL_PID_2 #ifndef CONF_PORTA_EVCTRL_PID_2
#define CONF_PORTA_EVCTRL_PID_2 0x0 #define CONF_PORTA_EVCTRL_PID_2 0xe
#endif #endif
// <o> PORTA Event 2 Action // <o> PORTA Event 2 Action
@ -164,7 +164,7 @@
// <i> These bits define the event action the PORT A will perform on event input 2 // <i> These bits define the event action the PORT A will perform on event input 2
// <id> porta_event_action_2 // <id> porta_event_action_2
#ifndef CONF_PORTA_EVCTRL_EVACT_2 #ifndef CONF_PORTA_EVCTRL_EVACT_2
#define CONF_PORTA_EVCTRL_EVACT_2 0 #define CONF_PORTA_EVCTRL_EVACT_2 1
#endif #endif
// </h> // </h>

6
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h
View File

@ -218,7 +218,7 @@
// <i> The SPI data transfer rate // <i> The SPI data transfer rate
// <id> spi_master_baud_rate // <id> spi_master_baud_rate
#ifndef CONF_SERCOM_2_SPI_BAUD #ifndef CONF_SERCOM_2_SPI_BAUD
#define CONF_SERCOM_2_SPI_BAUD 4000000 #define CONF_SERCOM_2_SPI_BAUD 1000000
#endif #endif
// </h> // </h>
@ -269,7 +269,7 @@
// <0x1=>On buffer overflow // <0x1=>On buffer overflow
// <id> spi_master_arch_ibon // <id> spi_master_arch_ibon
#ifndef CONF_SERCOM_2_SPI_IBON #ifndef CONF_SERCOM_2_SPI_IBON
#define CONF_SERCOM_2_SPI_IBON 0x0 #define CONF_SERCOM_2_SPI_IBON 0x1
#endif #endif
// <q> Run in stand-by // <q> Run in stand-by
@ -377,7 +377,7 @@
// <i> The SPI data transfer rate // <i> The SPI data transfer rate
// <id> spi_master_baud_rate // <id> spi_master_baud_rate
#ifndef CONF_SERCOM_5_SPI_BAUD #ifndef CONF_SERCOM_5_SPI_BAUD
#define CONF_SERCOM_5_SPI_BAUD 8000000 #define CONF_SERCOM_5_SPI_BAUD 1000000
#endif #endif
// </h> // </h>

48
2_Motor_Master/Motor_Master/Motor_Master/Config/peripheral_clk_config.h
View File

@ -41,7 +41,7 @@
* \brief ADC1's Clock frequency * \brief ADC1's Clock frequency
*/ */
#ifndef CONF_GCLK_ADC1_FREQUENCY #ifndef CONF_GCLK_ADC1_FREQUENCY
#define CONF_GCLK_ADC1_FREQUENCY 120000000 #define CONF_GCLK_ADC1_FREQUENCY 100000000
#endif #endif
// <y> CCL Clock Source // <y> CCL Clock Source
@ -81,7 +81,7 @@
* \brief CCL's Clock frequency * \brief CCL's Clock frequency
*/ */
#ifndef CONF_GCLK_CCL_FREQUENCY #ifndef CONF_GCLK_CCL_FREQUENCY
#define CONF_GCLK_CCL_FREQUENCY 120000000 #define CONF_GCLK_CCL_FREQUENCY 100000000
#endif #endif
// <y> EIC Clock Source // <y> EIC Clock Source
@ -121,7 +121,7 @@
* \brief EIC's Clock frequency * \brief EIC's Clock frequency
*/ */
#ifndef CONF_GCLK_EIC_FREQUENCY #ifndef CONF_GCLK_EIC_FREQUENCY
#define CONF_GCLK_EIC_FREQUENCY 120000000 #define CONF_GCLK_EIC_FREQUENCY 100000000
#endif #endif
// <y> EVSYS Channel 0 Clock Source // <y> EVSYS Channel 0 Clock Source
@ -162,7 +162,7 @@
*/ */
#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY #ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000 #define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 100000000
#endif #endif
// <y> EVSYS Channel 1 Clock Source // <y> EVSYS Channel 1 Clock Source
@ -203,7 +203,7 @@
*/ */
#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY #ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000 #define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 100000000
#endif #endif
// <y> EVSYS Channel 2 Clock Source // <y> EVSYS Channel 2 Clock Source
@ -244,7 +244,7 @@
*/ */
#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY #ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000 #define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 100000000
#endif #endif
// <y> EVSYS Channel 3 Clock Source // <y> EVSYS Channel 3 Clock Source
@ -285,7 +285,7 @@
*/ */
#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY #ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000 #define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 100000000
#endif #endif
// <y> EVSYS Channel 4 Clock Source // <y> EVSYS Channel 4 Clock Source
@ -326,7 +326,7 @@
*/ */
#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY #ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000 #define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 100000000
#endif #endif
// <y> EVSYS Channel 5 Clock Source // <y> EVSYS Channel 5 Clock Source
@ -367,7 +367,7 @@
*/ */
#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY #ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000 #define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 100000000
#endif #endif
// <y> EVSYS Channel 6 Clock Source // <y> EVSYS Channel 6 Clock Source
@ -408,7 +408,7 @@
*/ */
#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY #ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000 #define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 100000000
#endif #endif
// <y> EVSYS Channel 7 Clock Source // <y> EVSYS Channel 7 Clock Source
@ -449,7 +449,7 @@
*/ */
#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY #ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000 #define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 100000000
#endif #endif
// <y> EVSYS Channel 8 Clock Source // <y> EVSYS Channel 8 Clock Source
@ -490,7 +490,7 @@
*/ */
#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY #ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000 #define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 100000000
#endif #endif
// <y> EVSYS Channel 9 Clock Source // <y> EVSYS Channel 9 Clock Source
@ -531,7 +531,7 @@
*/ */
#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY #ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000 #define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 100000000
#endif #endif
// <y> EVSYS Channel 10 Clock Source // <y> EVSYS Channel 10 Clock Source
@ -572,7 +572,7 @@
*/ */
#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY #ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000 #define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 100000000
#endif #endif
// <y> EVSYS Channel 11 Clock Source // <y> EVSYS Channel 11 Clock Source
@ -613,7 +613,7 @@
*/ */
#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY #ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000 #define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 100000000
#endif #endif
/** /**
@ -621,7 +621,7 @@
* \brief CPU's Clock frequency * \brief CPU's Clock frequency
*/ */
#ifndef CONF_CPU_FREQUENCY #ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 120000000 #define CONF_CPU_FREQUENCY 100000000
#endif #endif
// <y> Core Clock Source // <y> Core Clock Source
@ -693,7 +693,7 @@
* \brief SERCOM1's Core Clock frequency * \brief SERCOM1's Core Clock frequency
*/ */
#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 120000000 #define CONF_GCLK_SERCOM1_CORE_FREQUENCY 100000000
#endif #endif
/** /**
@ -773,7 +773,7 @@
* \brief SERCOM2's Core Clock frequency * \brief SERCOM2's Core Clock frequency
*/ */
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 120000000 #define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000
#endif #endif
/** /**
@ -853,7 +853,7 @@
* \brief SERCOM5's Core Clock frequency * \brief SERCOM5's Core Clock frequency
*/ */
#ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY #ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 120000000 #define CONF_GCLK_SERCOM5_CORE_FREQUENCY 100000000
#endif #endif
/** /**
@ -901,7 +901,7 @@
* \brief TC0's Clock frequency * \brief TC0's Clock frequency
*/ */
#ifndef CONF_GCLK_TC0_FREQUENCY #ifndef CONF_GCLK_TC0_FREQUENCY
#define CONF_GCLK_TC0_FREQUENCY 120000000 #define CONF_GCLK_TC0_FREQUENCY 100000000
#endif #endif
// <y> TC Clock Source // <y> TC Clock Source
@ -941,7 +941,7 @@
* \brief TC2's Clock frequency * \brief TC2's Clock frequency
*/ */
#ifndef CONF_GCLK_TC2_FREQUENCY #ifndef CONF_GCLK_TC2_FREQUENCY
#define CONF_GCLK_TC2_FREQUENCY 120000000 #define CONF_GCLK_TC2_FREQUENCY 100000000
#endif #endif
// <y> TC Clock Source // <y> TC Clock Source
@ -981,7 +981,7 @@
* \brief TC4's Clock frequency * \brief TC4's Clock frequency
*/ */
#ifndef CONF_GCLK_TC4_FREQUENCY #ifndef CONF_GCLK_TC4_FREQUENCY
#define CONF_GCLK_TC4_FREQUENCY 120000000 #define CONF_GCLK_TC4_FREQUENCY 100000000
#endif #endif
// <y> TCC Clock Source // <y> TCC Clock Source
@ -1021,7 +1021,7 @@
* \brief TCC0's Clock frequency * \brief TCC0's Clock frequency
*/ */
#ifndef CONF_GCLK_TCC0_FREQUENCY #ifndef CONF_GCLK_TCC0_FREQUENCY
#define CONF_GCLK_TCC0_FREQUENCY 120000000 #define CONF_GCLK_TCC0_FREQUENCY 100000000
#endif #endif
// <y> TCC Clock Source // <y> TCC Clock Source
@ -1061,7 +1061,7 @@
* \brief TCC1's Clock frequency * \brief TCC1's Clock frequency
*/ */
#ifndef CONF_GCLK_TCC1_FREQUENCY #ifndef CONF_GCLK_TCC1_FREQUENCY
#define CONF_GCLK_TCC1_FREQUENCY 120000000 #define CONF_GCLK_TCC1_FREQUENCY 100000000
#endif #endif
// <<< end of configuration section >>> // <<< end of configuration section >>>

15
2_Motor_Master/Motor_Master/Motor_Master/EtherCAT_SlaveDef.h
View File

@ -11,9 +11,12 @@
#include "Ethercat_QSPI.h" #include "Ethercat_QSPI.h"
#include "arm_math.h" #include "arm_math.h"
#include "ADS1299.h"
extern volatile uint8_t _ads1299_reg_data[24];
extern volatile int32_t _ads1299_channel_data[9];
extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
extern volatile int32_t _channel_data[8];
extern volatile uint32_t ads1299_buffer[6];
//Write To Ecat Total Bytes (XX bytes) //Write To Ecat Total Bytes (XX bytes)
/* Motor 1*/ /* Motor 1*/
@ -195,10 +198,10 @@ static void update_telemetry(void)
*M2_Motor_speed = (int16_t)Motor2.motor_status.calc_rpm; *M2_Motor_speed = (int16_t)Motor2.motor_status.calc_rpm;
//*M2_Joint_abs_position = Motor2.motor_status.actualDirection; //*M2_Joint_abs_position = Motor2.motor_status.actualDirection;
*EMG_CH1 = _channel_data[0]; *EMG_CH1 = _ads1299_channel_data[0];
*EMG_CH2 = _channel_data[1]; *EMG_CH2 = _ads1299_channel_data[1];
*EMG_CH3 = _channel_data[2]; *EMG_CH3 = _ads1299_channel_data[2];
*EMG_CH4 = _channel_data[3]; *EMG_CH4 = _ads1299_channel_data[3];
//*EMG_CH1 = 1; //*EMG_CH1 = 1;
//*EMG_CH2 = 2; //*EMG_CH2 = 2;
//*EMG_CH3 = 3; //*EMG_CH3 = 3;

15
2_Motor_Master/Motor_Master/Motor_Master/Ethercat_SlaveDef.h
View File

@ -11,9 +11,12 @@
#include "Ethercat_QSPI.h" #include "Ethercat_QSPI.h"
#include "arm_math.h" #include "arm_math.h"
#include "ADS1299.h"
extern volatile uint8_t _ads1299_reg_data[24];
extern volatile int32_t _ads1299_channel_data[9];
extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
extern volatile int32_t _channel_data[8];
extern volatile uint32_t ads1299_buffer[6];
//Write To Ecat Total Bytes (XX bytes) //Write To Ecat Total Bytes (XX bytes)
/* Motor 1*/ /* Motor 1*/
@ -195,10 +198,10 @@ static void update_telemetry(void)
*M2_Motor_speed = (int16_t)Motor2.motor_status.calc_rpm; *M2_Motor_speed = (int16_t)Motor2.motor_status.calc_rpm;
//*M2_Joint_abs_position = Motor2.motor_status.actualDirection; //*M2_Joint_abs_position = Motor2.motor_status.actualDirection;
*EMG_CH1 = _channel_data[0]; *EMG_CH1 = _ads1299_channel_data[0];
*EMG_CH2 = _channel_data[1]; *EMG_CH2 = _ads1299_channel_data[1];
*EMG_CH3 = _channel_data[2]; *EMG_CH3 = _ads1299_channel_data[2];
*EMG_CH4 = _channel_data[3]; *EMG_CH4 = _ads1299_channel_data[3];
//*EMG_CH1 = 1; //*EMG_CH1 = 1;
//*EMG_CH2 = 2; //*EMG_CH2 = 2;
//*EMG_CH3 = 3; //*EMG_CH3 = 3;

12
2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj
View File

@ -206,18 +206,18 @@
<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="IJeJ3sDxG9f3mmsLxoMLlA" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="IJeJ3sDxG9f3mmsLxoMLlA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="G4WVXUcIlVMxjaDgFB7QRQ" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="GtvN6cIK8Fs/kg861j+0lg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="q6198/8IUrGygCgey3ZoQw" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="q6198/8IUrGygCgey3ZoQw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="syaZWQ6eNniWSrMj/aJpYA" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="VFsyUAbyj+4noNzt5pFGdg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Uje5LXAS+nQpGryt9t0fYA" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Xe5v62bijwZLOPLD+rPcrA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="OHReh3YoteXQnOg0JJMWVg" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="GyB7m/Yo05896J0mPhiOaw" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_qspi_config.h" IsConfig="true" Hash="CwZ360eeEYs7T9SYFSvDug" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_qspi_config.h" IsConfig="true" Hash="CwZ360eeEYs7T9SYFSvDug" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="0jM1u/XQkwzOqyPduvYuCA" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="YhOvJRia1eKe9odgdXn9EQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" /> <AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" />
<AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="s/tLl+lpMPQWNUrjuAL0rQ" /> <AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="s728fWyHIPUXyuq8+2qWsg" />
</AcmeActionInfos> </AcmeActionInfos>
<NonsecureFilesInfo /> <NonsecureFilesInfo />
</AcmeProjectConfig> </AcmeProjectConfig>

34
2_Motor_Master/Motor_Master/Motor_Master/configuration.h
View File

@ -17,6 +17,7 @@
#include "interrupts.h" #include "interrupts.h"
#include "hpl_sercom_config.h" #include "hpl_sercom_config.h"
#include "ADS1299.h" #include "ADS1299.h"
#include "hpl_spi_m_dma.h"
// ---------------------------------------------------------------------- // ----------------------------------------------------------------------
// ADC DMA Initialization // ADC DMA Initialization
// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6] // M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
@ -144,8 +145,8 @@ static void boardToBoardTransferInit(void)
spi_m_dma_get_io_descriptor(&SPI_1_MSIF, &io); spi_m_dma_get_io_descriptor(&SPI_1_MSIF, &io);
//spi_m_dma_register_callback(&SPI_1_MSIF, SPI_M_DMA_CB_RX_DONE, b2bTransferComplete_cb); //spi_m_dma_register_callback(&SPI_1_MSIF, SPI_M_DMA_CB_RX_DONE, b2bTransferComplete_cb);
//SERCOM4->SPI.CTRLC.bit.DATA32B = true; //SERCOM4->SPI.CTRLC.bit.DATA32B = true;
SERCOM1->SPI.LENGTH.bit.LENEN = true; //SERCOM1->SPI.LENGTH.bit.LENEN = true;
SERCOM1->SPI.LENGTH.bit.LEN = 64; //SERCOM1->SPI.LENGTH.bit.LEN = 64;
SERCOM1->SPI.CTRLC.bit.ICSPACE = 4; SERCOM1->SPI.CTRLC.bit.ICSPACE = 4;
SERCOM1->SPI.CTRLC.bit.DATA32B= true; SERCOM1->SPI.CTRLC.bit.DATA32B= true;
@ -188,7 +189,7 @@ static void spi_master_init_dma_descriptors()
#define CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL 2U #define CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL 2U
#define CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL 8U #define CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL 8U
#define ADS_BUFFER_SIZE 6
/* 219 Bites total /* 219 Bites total
@ -196,25 +197,38 @@ static void spi_master_init_dma_descriptors()
* 7 (uint_32) - 24 bits * 7 (uint_32) - 24 bits
*/ */
extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE]; extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
// //
static void spi_ads1299_init_dma_descriptors() static void spi_ads1299_init_dma_descriptors()
{ {
_dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, _dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg)); (uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg));
_dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, &QSPI_rx_buffer[10]); _dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, &_ads1299_channel_data[0]);
_dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, ADS_BUFFER_SIZE); _dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, ADS_BUFFER_SIZE);
_dma_set_next_descriptor(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL); //_dma_set_next_descriptor(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL);
_dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, &ads1299_buffer[0]); _dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, &ads1299_buffer[0]);
_dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, _dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL,
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg)); (uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg));
_dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, ADS_BUFFER_SIZE); _dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, ADS_BUFFER_SIZE);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL]); hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL]);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL]); hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL]);
/* callback */
struct _dma_resource *resource_rx, *resource_tx;
_dma_get_channel_resource(&resource_rx, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL);
_dma_get_channel_resource(&resource_tx, CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL);
resource_rx->dma_cb.transfer_done = ADS1299_Transfer_Complete_cb;
//resource_rx->dma_cb.error = ADS1299_Transfer_error_cb;
/* Enable DMA transfer complete interrupt */
_dma_set_irq_state(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
//_dma_set_irq_state(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, DMA_TRANSFER_ERROR_CB, true);
} }
@ -231,9 +245,9 @@ static void spi_ads1299_init_dma_descriptors()
* CH5 - ADC1 - Result Ready * CH5 - ADC1 - Result Ready
* CH6 - ADC0 - Sequencer (Unused on master) - Currently Disabled in ASTART * CH6 - ADC0 - Sequencer (Unused on master) - Currently Disabled in ASTART
* CH7 - ADC1 - Sequencer - Triggered by TCC0 overflow event * CH7 - ADC1 - Sequencer - Triggered by TCC0 overflow event
* CH8 - SERCOM2_TX(SPI2) - Master-Slave IF * CH8 - SERCOM2_TX(SPI2) - Expansion IF (EMG)
* CH9 - SERCOM5_TX(SPI3) - Expansion IF (EMG) * CH9 - SERCOM5_TX(SPI3) - Angle Sensor
* CH10 - SERCOM1_TX(SPI1) - Angle Sensor * CH10 - SERCOM1_TX(SPI1) - Master-Slave IF
* CH11 - QSPI_TX - For ECAT DMA Mode - Currently Disabled in ASTART * CH11 - QSPI_TX - For ECAT DMA Mode - Currently Disabled in ASTART
*/ */
static void init_dma(void) static void init_dma(void)

18
2_Motor_Master/Motor_Master/Motor_Master/interrupts.h
View File

@ -10,6 +10,7 @@
#define INTERRUPTS_H_ #define INTERRUPTS_H_
#include "configuration.h" #include "configuration.h"
#include "ADS1299.h"
/* TC0 - Interrupt Handler /* TC0 - Interrupt Handler
* Configured to trigger @ 1ms * Configured to trigger @ 1ms
@ -66,6 +67,7 @@ static void b2bTransferComplete_cb(struct _dma_resource *resource)
//volatile int x = 0; //volatile int x = 0;
//PORT->Group[GPIO_PORTB].OUTCLR.reg = (1<<Slave_1->SS_pin); //PORT->Group[GPIO_PORTB].OUTCLR.reg = (1<<Slave_1->SS_pin);
//gpio_set_pin_level(SPI1_CS, true); //gpio_set_pin_level(SPI1_CS, true);
volatile int x = 0;
} }
@ -129,14 +131,24 @@ static void M2_RESET_BAR(void)
// ---------------------------------------------------------------------- // ----------------------------------------------------------------------
void ADS1299_dataReadyISR(void) void ADS1299_dataReadyISR(void)
{ {
DMAC->Channel[2].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[8].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; ADS1299.data_ReadyFlag = true;
//ADS1299.data_ReadyFlag = true;
//int32_t* temp = ADS1299_UPDATECHANNELDATA(); //int32_t* temp = ADS1299_UPDATECHANNELDATA();
volatile int x = 1; volatile int x = 1;
} }
void ADS1299_Transfer_Complete_cb(void)
{
PORT->Group[0].OUTSET.reg = (1<<GPIO_PIN(SPI2_SS));
volatile int x = 1;
}
void ADS1299_Transfer_error_cb(void)
{
//SERCOM2->SPI.STATUS.bit.BUFOVF = 1;
//PORT->Group[0].OUTSET.reg = (1<<GPIO_PIN(SPI2_SS));
volatile int x = 1;
}
#endif /* INTERRUPTS_H_ */ #endif /* INTERRUPTS_H_ */

27
2_Motor_Master/Motor_Master/Motor_Master/main.c
View File

@ -64,6 +64,9 @@ void enable_NVIC_IRQ(void)
//NVIC_EnableIRQ(TC4_IRQn); // TC4: M2_Speed_Timer //NVIC_EnableIRQ(TC4_IRQn); // TC4: M2_Speed_Timer
NVIC_EnableIRQ(DMAC_0_IRQn); NVIC_EnableIRQ(DMAC_0_IRQn);
NVIC_EnableIRQ(DMAC_1_IRQn); NVIC_EnableIRQ(DMAC_1_IRQn);
NVIC_EnableIRQ(DMAC_2_IRQn);
NVIC_EnableIRQ(DMAC_3_IRQn);
NVIC_EnableIRQ(DMAC_4_IRQn);
NVIC_SetPriority(DMAC_0_IRQn, 2); NVIC_SetPriority(DMAC_0_IRQn, 2);
NVIC_SetPriority(ADC1_0_IRQn, 3); NVIC_SetPriority(ADC1_0_IRQn, 3);
NVIC_EnableIRQ(TCC0_0_IRQn); NVIC_EnableIRQ(TCC0_0_IRQn);
@ -71,6 +74,7 @@ void enable_NVIC_IRQ(void)
NVIC_EnableIRQ(EIC_2_IRQn); NVIC_EnableIRQ(EIC_2_IRQn);
NVIC_EnableIRQ(SERCOM1_1_IRQn); NVIC_EnableIRQ(SERCOM1_1_IRQn);
NVIC_EnableIRQ(SERCOM2_1_IRQn);
//NVIC_SetPriority(SERCOM1_1_IRQn, 1); //NVIC_SetPriority(SERCOM1_1_IRQn, 1);
NVIC_EnableIRQ(TC0_IRQn); NVIC_EnableIRQ(TC0_IRQn);
//NVIC_EnableIRQ(TC0_IRQn); //NVIC_EnableIRQ(TC0_IRQn);
@ -78,6 +82,8 @@ void enable_NVIC_IRQ(void)
//NVIC_SetPriority(TCC0_0_IRQn, 3); //NVIC_SetPriority(TCC0_0_IRQn, 3);
//NVIC_EnableIRQ(EIC_5_IRQn); //NVIC_EnableIRQ(EIC_5_IRQn);
/* Reset Latch Interrupt */ /* Reset Latch Interrupt */
ext_irq_register(PIN_PB30, M1_RESET_BAR); ext_irq_register(PIN_PB30, M1_RESET_BAR);
ext_irq_register(PIN_PB31, M2_RESET_BAR); ext_irq_register(PIN_PB31, M2_RESET_BAR);
@ -166,6 +172,8 @@ int main(void)
boardToBoardTransferInit(); boardToBoardTransferInit();
/* DMA Configs */ /* DMA Configs */
init_dma(); init_dma();
/* ECAT State Machine First run */
ECAT_STATE_MACHINE(); ECAT_STATE_MACHINE();
//angle_sensor_init(); //angle_sensor_init();
@ -173,11 +181,10 @@ int main(void)
/* External IRQ Config */ /* External IRQ Config */
custom_logic_enable(); custom_logic_enable();
ext_irq_register(GPIO_PIN(ADS_DATA_RDY), ADS1299_dataReadyISR);
__enable_irq(); __enable_irq();
ADS1299_START(); ADS1299_START();
/* ADS Result Ready Interrupt, active low */
ext_irq_register(GPIO_PIN(ADS_DATA_RDY), ADS1299_dataReadyISR);
enable_NVIC_IRQ(); enable_NVIC_IRQ();
/* Replace with your application code */ /* Replace with your application code */
@ -220,7 +227,6 @@ int main(void)
} }
if (Motor1.timerflags.current_loop_tic) { if (Motor1.timerflags.current_loop_tic) {
Motor1.timerflags.current_loop_tic = false; Motor1.timerflags.current_loop_tic = false;
APPLICATION_StateMachine(); APPLICATION_StateMachine();
exec_commutation(&Motor1); exec_commutation(&Motor1);
@ -229,6 +235,19 @@ int main(void)
if (ADS1299.data_ReadyFlag){ if (ADS1299.data_ReadyFlag){
ADS1299.data_ReadyFlag = false; ADS1299.data_ReadyFlag = false;
PORT->Group[0].OUTCLR.reg = (1<<GPIO_PIN(SPI2_SS));
if ((DMAC->Channel[2].CHSTATUS.bit.FERR == true) || (DMAC->Channel[8].CHSTATUS.bit.FERR == true))
{
volatile int x = 0;
}
DMAC->Channel[2].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[8].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
//_dma_enable_transaction(2, false);
//_dma_enable_transaction(8, false);
//ADS1299_UPDATECHANNELDATA(); //ADS1299_UPDATECHANNELDATA();
} }

4
2_Motor_Master/Motor_Master/Motor_Master/motorparameters.h
View File

@ -154,7 +154,7 @@ const static BLDCMotor_param_t FH_22mm24BXTR = {
.controller_param.Pid_Speed.Kp = 0.00004f, .controller_param.Pid_Speed.Kp = 0.00004f,
.controller_param.Pid_Speed.Ki = 0.0000001f, .controller_param.Pid_Speed.Ki = 0.0000001f,
//.controller_param.Pid_Speed.Ki = 0.0000001f, //.controller_param.Pid_Speed.Ki = 0.0000001f,
.controller_param.Pi_Pos.Kp = 50.0f, .controller_param.Pi_Pos.Kp = 30.0f,
.controller_param.Pi_Pos.Ki = 0.0f, .controller_param.Pi_Pos.Ki = 0.0f,
.motor_MaxPWM = 600.0, .motor_MaxPWM = 600.0,
}; };
@ -175,7 +175,7 @@ const static BLDCMotor_param_t FH_32mm12BXTR = {
.motor_Max_Current_IDC_A = (1.2), .motor_Max_Current_IDC_A = (1.2),
.controller_param.Pid_Speed.Kp = 0.0003f, .controller_param.Pid_Speed.Kp = 0.0003f,
.controller_param.Pid_Speed.Ki = 0.0000001f, .controller_param.Pid_Speed.Ki = 0.0000001f,
.controller_param.Pi_Pos.Kp = 40.0f, .controller_param.Pi_Pos.Kp = 30.0f,
.controller_param.Pi_Pos.Ki = 0.000f, .controller_param.Pi_Pos.Ki = 0.000f,
//.controller_param.Pid_Speed.Kp = 0.00002f, //.controller_param.Pid_Speed.Kp = 0.00002f,
//.controller_param.Pid_Speed.Ki = 0.0f, //.controller_param.Pid_Speed.Ki = 0.0f,

BIN
Twincat/MotorData/.vs/MotorData/v15/.suo
View File

Binary file not shown.