Split ethercat to its own file
This commit is contained in:
Nicolas Trimborn
parent
7576bf10e9
commit
33269ff676
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@ -0,0 +1,39 @@
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/*
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* EtherCAT_QSPI.h
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*
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* Created: 31/07/2021 17:51:24
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* Author: Nick-XMG
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*/
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#ifndef ETHERCAT_QSPI_H_
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#define ETHERCAT_QSPI_H_
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#include "atmel_start.h"
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#include <hpl_qspi_config.h>
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#include <hpl_sercom_config.h>
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#define ECAT_SIZE_WR 64 //max fifo size
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#define ECAT_SIZE_RD ECAT_SIZE_WR
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#define ECAT_SIZE_WR_REG ECAT_SIZE_WR/4
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#define ECAT_SIZE_RD_REG ECAT_SIZE_WR/4
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#define buffer_size 3*ECAT_SIZE_WR_REG //changed to double
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#define motor_buffer_size buffer_size/3
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extern enum ecat_states {abort_fifo,dlt_rdram,cf_dlt_rdram,write_fifo,config_fifo,read_fifo,wait,wait2,en_SQI,temp,rd_rdy};
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extern volatile enum ecat_states ecat_state;
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extern volatile enum ecat_states next_ecat_state;
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volatile uint32_t QSPI_tx_buffer[buffer_size];
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volatile uint32_t QSPI_rx_buffer[buffer_size];
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//static uint32_t QSPI_tx_buffer[buffer_size] = {47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,
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//31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,
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//15,14,13,12,11,10, 9,8,7,6,5,4,3,2,1,0};
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//static uint32_t QSPI_rx_buffer[buffer_size] = {0};
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extern volatile bool run_ECAT;
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void config_qspi(void);
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#endif /* ETHERCAT_QSPI_H_ */
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@ -0,0 +1,216 @@
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/*
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* Ethercat_QSPI.c
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*
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* Created: 31/07/2021 17:52:21
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* Author: Nick-XMG
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*/
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#include "Ethercat_QSPI.h"
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#define SQI_READ (0x0B<<16)
#define SQI_WRITE (0x02<<16)
#define SQI_INC (0x40<<8)
#define SQI_DEC (0x80<<8)
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#define ECAT_PRAM_RD_DATA 0x0000
#define ECAT_PRAM_WR_DATA 0x0020
#define HW_CFG 0x0074
#define BYTE_TEST 0x0064
#define ECAT_PRAM_RD_ADDR_LEN 0x0308
#define ECAT_PRAM_RD_CMD 0x030C
#define ECAT_PRAM_WR_ADDR_LEN 0x0310
#define ECAT_PRAM_WR_CMD 0x0314
#define LAN9252_RDY (1<<27)
#define PDRAM_RD_ADDRESS 0x1100
#define PDRAM_RD_LENGTH ECAT_SIZE_RD //do the math later to automatize. fixed to 64 for now.
#define PDRAM_WR_ADDRESS 0x1800
#define PDRAM_WR_LENGTH ECAT_SIZE_WR
#define PDRAM_LENGTH_MAX 64
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#define PDRAM_LENGTH_SHORT 32
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#define FIFO_DEPTH 16
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#define PDRAM_REG_MAX PDRAM_LENGTH_SHORT/4
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#define PRAM_X_ABORT (1<<30)
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#define CSR_BUSY 0x80000000
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COMPILER_ALIGNED(16)
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DmacDescriptor dummy_rx_descriptor;
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DmacDescriptor dummy_tx_descriptor;
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volatile uint32_t QSPI_tx_buffer[buffer_size]={0};
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volatile uint32_t QSPI_rx_buffer[buffer_size]={0};
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volatile enum ecat_states ecat_state = wait;
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volatile enum ecat_states next_ecat_state = wait;
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volatile uint8_t wr_cnt = 0;
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volatile uint8_t rd_cnt = 0;
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static uint8_t sync_rx_buffer[2*2*buffer_size/3]={0};
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static uint8_t sync_tx_buffer[2*2*buffer_size/3]={0xED};
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static uint32_t QSPI_cmds[]={0,PRAM_X_ABORT,0,PRAM_X_ABORT,
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((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS,CSR_BUSY,
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((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX,CSR_BUSY,
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((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX*2, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX*2,CSR_BUSY,
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};
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static uint32_t zero[FIFO_DEPTH]={0};
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volatile uint32_t status = 0;
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struct _qspi_command rd_cmd = {
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.inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
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.inst_frame.bits.inst_en = 0,
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.inst_frame.bits.data_en = 1,
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.inst_frame.bits.addr_en = 1,
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.inst_frame.bits.dummy_cycles = 6,
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.inst_frame.bits.tfr_type = QSPI_READMEM_ACCESS,
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};
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struct _qspi_command wr_cmd = {
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.inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
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.inst_frame.bits.inst_en = 0,
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.inst_frame.bits.data_en = 1,
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.inst_frame.bits.addr_en = 1,
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.inst_frame.bits.dummy_cycles = 0,
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.inst_frame.bits.tfr_type = QSPI_WRITEMEM_ACCESS,
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};
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struct _qspi_command qspi_cmd = {
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.inst_frame.bits.width = QSPI_INST1_ADDR1_DATA1,
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.inst_frame.bits.inst_en = 1,
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.inst_frame.bits.data_en = 0,
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.inst_frame.bits.addr_en = 0,
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.inst_frame.bits.dummy_cycles = 0,
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.instruction = 0x38,
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.inst_frame.bits.tfr_type = QSPI_WRITE_ACCESS,
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};
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struct _qspi_command *spi_cmd= &wr_cmd;
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volatile uint8_t tx_complete =3;
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volatile uint32_t *ECAT_BYTE_TEST= QSPI_AHB+BYTE_TEST+SQI_READ;
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volatile uint32_t *ECAT_FIFO_RD_RD= QSPI_AHB+SQI_READ +ECAT_PRAM_RD_DATA;
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//volatile uint32_t *ECAT_FIFO_RD_RD= QSPI_AHB+SQI_READ +SQI_INC+ECAT_PRAM_RD_DATA;
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volatile uint32_t *ECAT_FIFO_WR_WR= QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_DATA;
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//volatile uint32_t *ECAT_FIFO_WR_WR= QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_DATA;
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volatile uint32_t *ECAT_HW_CFG_RD= QSPI_AHB+SQI_READ+HW_CFG;
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volatile uint32_t *ECAT_FIFO_RD_ADLEN_WR= QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_RD_ADDR_LEN;
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volatile uint32_t *ECAT_FIFO_WR_ADLEN_WR= QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
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volatile uint32_t *ECAT_FIFO_WR_ADLEN_RD= QSPI_AHB+SQI_READ+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
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volatile uint32_t *ECAT_FIFO_WR_CMD_RD= QSPI_AHB+SQI_READ+ECAT_PRAM_WR_CMD;
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volatile uint32_t *ECAT_FIFO_WR_CMD_WR= QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_CMD;
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volatile uint32_t *INPUT_ADDRESS ;
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volatile uint32_t *OUTPUT_ADDRESS;
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volatile uint32_t read_buffer =0;
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volatile uint8_t ecat_length= 0;
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volatile bool run_ECAT = false;
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volatile bool synced = false;
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void ECAT_STATE_MACHINE(void){
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if ((ecat_state != wait)&(ecat_state != wait2)){
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run_ECAT = false;
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switch(ecat_state){
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case en_SQI:
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spi_cmd = &qspi_cmd;
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QSPI->INSTRCTRL.bit.INSTR=spi_cmd->instruction;
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OUTPUT_ADDRESS = ECAT_FIFO_RD_ADLEN_WR;
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INPUT_ADDRESS = &QSPI_cmds[0];
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ecat_length = 0;
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next_ecat_state = rd_rdy;
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break;
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case rd_rdy:
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if (QSPI_rx_buffer[0]==LAN9252_RDY){
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next_ecat_state = abort_fifo;
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}
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else if (QSPI_rx_buffer[0]== 0xFFFFFFFF){
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next_ecat_state = en_SQI;
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QSPI_rx_buffer[0] = 0;
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}
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else{
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spi_cmd = &rd_cmd;
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OUTPUT_ADDRESS = &QSPI_rx_buffer[0];
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INPUT_ADDRESS = ECAT_HW_CFG_RD;
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ecat_length = 1;
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wr_cnt=0;
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}
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break;
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case abort_fifo:
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spi_cmd = &wr_cmd;
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OUTPUT_ADDRESS = ECAT_FIFO_WR_CMD_WR;
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INPUT_ADDRESS = &QSPI_cmds[1];
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ecat_length = 1;
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next_ecat_state = dlt_rdram;
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wr_cnt=0;
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rd_cnt=0;
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break;
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case dlt_rdram:
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spi_cmd = &wr_cmd;
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OUTPUT_ADDRESS = ECAT_FIFO_WR_WR;
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INPUT_ADDRESS = &zero[0];
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//if (wr_cnt >= 1) ecat_length = FIFO_DEPTH/2;
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//else ecat_length = FIFO_DEPTH;
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ecat_length = FIFO_DEPTH;
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next_ecat_state = cf_dlt_rdram;
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break;
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case cf_dlt_rdram:
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spi_cmd = &wr_cmd;
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OUTPUT_ADDRESS = ECAT_FIFO_WR_ADLEN_WR;
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INPUT_ADDRESS = &QSPI_cmds[4*(wr_cnt+1)];
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ecat_length = 2;
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if (wr_cnt >= 2) {
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next_ecat_state = wait;
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wr_cnt =0;
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} else {
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next_ecat_state = dlt_rdram;
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wr_cnt++;
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}
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break;
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case write_fifo:
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spi_cmd = &wr_cmd;
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OUTPUT_ADDRESS = ECAT_FIFO_WR_WR;
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INPUT_ADDRESS = &QSPI_tx_buffer[wr_cnt*FIFO_DEPTH];
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/*if (wr_cnt >= 1) ecat_length = FIFO_DEPTH/2;
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else ecat_length = FIFO_DEPTH;*/
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ecat_length = FIFO_DEPTH;
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next_ecat_state = config_fifo;
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break;
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case config_fifo:
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spi_cmd = &wr_cmd;
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OUTPUT_ADDRESS = ECAT_FIFO_RD_ADLEN_WR;
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INPUT_ADDRESS = &QSPI_cmds[4*(wr_cnt+1)];
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ecat_length = 4;
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next_ecat_state = read_fifo;
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break;
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case read_fifo:
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spi_cmd = &rd_cmd;
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OUTPUT_ADDRESS = &QSPI_rx_buffer[wr_cnt*FIFO_DEPTH];
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INPUT_ADDRESS = ECAT_FIFO_RD_RD;
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ecat_length = FIFO_DEPTH;
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if (wr_cnt >= 2) {
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// ecat_length = FIFO_DEPTH/2;
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next_ecat_state = wait2;
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wr_cnt=0;
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}
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else {
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// ecat_length = FIFO_DEPTH;
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next_ecat_state = write_fifo;
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wr_cnt++;
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}
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break;
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}
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qspi_dma_enable(&ECAT_QSPI);
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QSPI->INSTRFRAME.reg = ((*spi_cmd).inst_frame.word);
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for (uint8_t i=0;i<ecat_length;i++)
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{
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*(OUTPUT_ADDRESS+i) = *(INPUT_ADDRESS+i);
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}
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QSPI->CTRLA.bit.LASTXFER = 1;
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ecat_state = next_ecat_state;
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}
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}
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void config_qspi()
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{
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QSPI->INTENSET.bit.CSRISE = 1;
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NVIC_EnableIRQ(QSPI_IRQn);
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ecat_state =en_SQI;
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}
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QSPI_Handler(){
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if (QSPI->INTFLAG.bit.CSRISE == 1){
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QSPI->INTFLAG.bit.CSRISE = 1;
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run_ECAT =true;
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}
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}
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@ -570,6 +570,12 @@
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<Compile Include="driver_init.h">
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<SubType>compile</SubType>
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</Compile>
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<Compile Include="Ethercat_QSPI.c">
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<SubType>compile</SubType>
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</Compile>
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<Compile Include="Ethercat_QSPI.h">
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<SubType>compile</SubType>
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</Compile>
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<Compile Include="examples\driver_examples.c">
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<SubType>compile</SubType>
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</Compile>
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@ -1,238 +1,14 @@
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#include <atmel_start.h>
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#include "bldc.h"
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#include <hpl_qspi_config.h>
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#include <hpl_sercom_config.h>
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#define ECAT_SIZE_WR 64 //max fifo size
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#define ECAT_SIZE_RD ECAT_SIZE_WR
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#define ECAT_SIZE_WR_REG ECAT_SIZE_WR/4
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#define ECAT_SIZE_RD_REG ECAT_SIZE_WR/4
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#define SQI_READ (0x0B<<16)
#define SQI_WRITE (0x02<<16)
#define SQI_INC (0x40<<8)
#define SQI_DEC (0x80<<8)
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#define ECAT_PRAM_RD_DATA 0x0000
#define ECAT_PRAM_WR_DATA 0x0020
#define HW_CFG 0x0074
#define BYTE_TEST 0x0064
#define ECAT_PRAM_RD_ADDR_LEN 0x0308
#define ECAT_PRAM_RD_CMD 0x030C
#define ECAT_PRAM_WR_ADDR_LEN 0x0310
#define ECAT_PRAM_WR_CMD 0x0314
#define LAN9252_RDY (1<<27)
#define PDRAM_RD_ADDRESS 0x1100
#define PDRAM_RD_LENGTH ECAT_SIZE_RD //do the math later to automatize. fixed to 64 for now.
#define PDRAM_WR_ADDRESS 0x1800
#define PDRAM_WR_LENGTH ECAT_SIZE_WR
#define PDRAM_LENGTH_MAX 64
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#define PDRAM_LENGTH_SHORT 32
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#define FIFO_DEPTH 16
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#define PDRAM_REG_MAX PDRAM_LENGTH_SHORT/4
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#define PRAM_X_ABORT (1<<30)
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#define CSR_BUSY 0x80000000
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#define buffer_size 3*ECAT_SIZE_WR_REG //changed to double
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#define motor_buffer_size buffer_size/3
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//static uint32_t QSPI_tx_buffer[buffer_size]={0};
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//static uint32_t QSPI_rx_buffer[buffer_size]={0};
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static uint32_t QSPI_tx_buffer[buffer_size]={47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,31,30,29,
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28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,
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9,8,7,6,5,4,3,2,1,0};
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static uint32_t QSPI_rx_buffer[buffer_size]={0};
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COMPILER_ALIGNED(16)
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DmacDescriptor dummy_rx_descriptor;
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DmacDescriptor dummy_tx_descriptor;
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enum ecat_states {abort_fifo,dlt_rdram,cf_dlt_rdram,write_fifo,config_fifo,read_fifo,wait,wait2,en_SQI,temp,rd_rdy};
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volatile enum ecat_states ecat_state = wait;
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volatile enum ecat_states next_ecat_state = wait;
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volatile uint8_t wr_cnt = 0;
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volatile uint8_t rd_cnt = 0;
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static uint8_t sync_rx_buffer[2*2*buffer_size/3]={0};
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static uint8_t sync_tx_buffer[2*2*buffer_size/3]={0xED};
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static uint32_t QSPI_cmds[]={0,PRAM_X_ABORT,0,PRAM_X_ABORT,
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((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS,CSR_BUSY,
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((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX,CSR_BUSY,
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((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX*2, CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX*2,CSR_BUSY,
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};
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static uint32_t zero[FIFO_DEPTH]={0};
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volatile uint32_t status = 0;
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struct _qspi_command rd_cmd = {
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.inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
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.inst_frame.bits.inst_en = 0,
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.inst_frame.bits.data_en = 1,
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.inst_frame.bits.addr_en = 1,
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.inst_frame.bits.dummy_cycles = 6,
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.inst_frame.bits.tfr_type = QSPI_READMEM_ACCESS,
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};
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struct _qspi_command wr_cmd = {
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.inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
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.inst_frame.bits.inst_en = 0,
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.inst_frame.bits.data_en = 1,
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.inst_frame.bits.addr_en = 1,
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.inst_frame.bits.dummy_cycles = 0,
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.inst_frame.bits.tfr_type = QSPI_WRITEMEM_ACCESS,
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};
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struct _qspi_command qspi_cmd = {
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.inst_frame.bits.width = QSPI_INST1_ADDR1_DATA1,
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.inst_frame.bits.inst_en = 1,
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.inst_frame.bits.data_en = 0,
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.inst_frame.bits.addr_en = 0,
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.inst_frame.bits.dummy_cycles = 0,
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.instruction = 0x38,
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.inst_frame.bits.tfr_type = QSPI_WRITE_ACCESS,
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};
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struct _qspi_command *spi_cmd= &wr_cmd;
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volatile uint8_t tx_complete =3;
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volatile uint32_t *ECAT_BYTE_TEST= QSPI_AHB+BYTE_TEST+SQI_READ;
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volatile uint32_t *ECAT_FIFO_RD_RD= QSPI_AHB+SQI_READ +ECAT_PRAM_RD_DATA;
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//volatile uint32_t *ECAT_FIFO_RD_RD= QSPI_AHB+SQI_READ +SQI_INC+ECAT_PRAM_RD_DATA;
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volatile uint32_t *ECAT_FIFO_WR_WR= QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_DATA;
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//volatile uint32_t *ECAT_FIFO_WR_WR= QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_DATA;
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volatile uint32_t *ECAT_HW_CFG_RD= QSPI_AHB+SQI_READ+HW_CFG;
|
||||
volatile uint32_t *ECAT_FIFO_RD_ADLEN_WR= QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_RD_ADDR_LEN;
|
||||
volatile uint32_t *ECAT_FIFO_WR_ADLEN_WR= QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
|
||||
volatile uint32_t *ECAT_FIFO_WR_ADLEN_RD= QSPI_AHB+SQI_READ+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
|
||||
volatile uint32_t *ECAT_FIFO_WR_CMD_RD= QSPI_AHB+SQI_READ+ECAT_PRAM_WR_CMD;
|
||||
volatile uint32_t *ECAT_FIFO_WR_CMD_WR= QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_CMD;
|
||||
|
||||
volatile uint32_t *INPUT_ADDRESS ;
|
||||
volatile uint32_t *OUTPUT_ADDRESS;
|
||||
volatile uint32_t read_buffer =0;
|
||||
volatile uint8_t ecat_length= 0;
|
||||
|
||||
volatile bool run_ECAT = false;
|
||||
volatile bool synced = false;
|
||||
void ECAT_STATE_MACHINE(void){
|
||||
if ((ecat_state != wait)&(ecat_state != wait2)){
|
||||
run_ECAT = false;
|
||||
switch(ecat_state){
|
||||
case en_SQI:
|
||||
spi_cmd = &qspi_cmd;
|
||||
QSPI->INSTRCTRL.bit.INSTR=spi_cmd->instruction;
|
||||
OUTPUT_ADDRESS = ECAT_FIFO_RD_ADLEN_WR;
|
||||
INPUT_ADDRESS = &QSPI_cmds[0];
|
||||
ecat_length = 0;
|
||||
next_ecat_state = rd_rdy;
|
||||
|
||||
break;
|
||||
case rd_rdy:
|
||||
if (QSPI_rx_buffer[0]==LAN9252_RDY){
|
||||
next_ecat_state = abort_fifo;
|
||||
}
|
||||
else if (QSPI_rx_buffer[0]== 0xFFFFFFFF){
|
||||
next_ecat_state = en_SQI;
|
||||
QSPI_rx_buffer[0] = 0;
|
||||
}
|
||||
else{
|
||||
spi_cmd = &rd_cmd;
|
||||
OUTPUT_ADDRESS = &QSPI_rx_buffer[0];
|
||||
INPUT_ADDRESS = ECAT_HW_CFG_RD;
|
||||
ecat_length = 1;
|
||||
wr_cnt=0;
|
||||
}
|
||||
|
||||
break;
|
||||
case abort_fifo:
|
||||
spi_cmd = &wr_cmd;
|
||||
OUTPUT_ADDRESS = ECAT_FIFO_WR_CMD_WR;
|
||||
INPUT_ADDRESS = &QSPI_cmds[1];
|
||||
ecat_length = 1;
|
||||
next_ecat_state = dlt_rdram;
|
||||
wr_cnt=0;
|
||||
rd_cnt=0;
|
||||
break;
|
||||
case dlt_rdram:
|
||||
spi_cmd = &wr_cmd;
|
||||
OUTPUT_ADDRESS = ECAT_FIFO_WR_WR;
|
||||
INPUT_ADDRESS = &zero[0];
|
||||
//if (wr_cnt >= 1) ecat_length = FIFO_DEPTH/2;
|
||||
//else ecat_length = FIFO_DEPTH;
|
||||
ecat_length = FIFO_DEPTH;
|
||||
next_ecat_state = cf_dlt_rdram;
|
||||
break;
|
||||
case cf_dlt_rdram:
|
||||
spi_cmd = &wr_cmd;
|
||||
OUTPUT_ADDRESS = ECAT_FIFO_WR_ADLEN_WR;
|
||||
INPUT_ADDRESS = &QSPI_cmds[4*(wr_cnt+1)];
|
||||
ecat_length = 2;
|
||||
if (wr_cnt >= 2) {
|
||||
next_ecat_state = wait;
|
||||
wr_cnt =0;
|
||||
} else {
|
||||
next_ecat_state = dlt_rdram;
|
||||
wr_cnt++;
|
||||
}
|
||||
|
||||
break;
|
||||
case write_fifo:
|
||||
spi_cmd = &wr_cmd;
|
||||
OUTPUT_ADDRESS = ECAT_FIFO_WR_WR;
|
||||
INPUT_ADDRESS = &QSPI_tx_buffer[wr_cnt*FIFO_DEPTH];
|
||||
/*if (wr_cnt >= 1) ecat_length = FIFO_DEPTH/2;
|
||||
else ecat_length = FIFO_DEPTH;*/
|
||||
ecat_length = FIFO_DEPTH;
|
||||
next_ecat_state = config_fifo;
|
||||
break;
|
||||
case config_fifo:
|
||||
spi_cmd = &wr_cmd;
|
||||
OUTPUT_ADDRESS = ECAT_FIFO_RD_ADLEN_WR;
|
||||
INPUT_ADDRESS = &QSPI_cmds[4*(wr_cnt+1)];
|
||||
ecat_length = 4;
|
||||
next_ecat_state = read_fifo;
|
||||
break;
|
||||
case read_fifo:
|
||||
spi_cmd = &rd_cmd;
|
||||
OUTPUT_ADDRESS = &QSPI_rx_buffer[wr_cnt*FIFO_DEPTH];
|
||||
INPUT_ADDRESS = ECAT_FIFO_RD_RD;
|
||||
ecat_length = FIFO_DEPTH;
|
||||
if (wr_cnt >= 2) {
|
||||
// ecat_length = FIFO_DEPTH/2;
|
||||
next_ecat_state = wait2;
|
||||
wr_cnt=0;
|
||||
}
|
||||
else {
|
||||
// ecat_length = FIFO_DEPTH;
|
||||
next_ecat_state = write_fifo;
|
||||
wr_cnt++;
|
||||
}
|
||||
break;
|
||||
}
|
||||
qspi_dma_enable(&ECAT_QSPI);
|
||||
QSPI->INSTRFRAME.reg = ((*spi_cmd).inst_frame.word);
|
||||
for (uint8_t i=0;i<ecat_length;i++)
|
||||
{
|
||||
*(OUTPUT_ADDRESS+i) = *(INPUT_ADDRESS+i);
|
||||
}
|
||||
QSPI->CTRLA.bit.LASTXFER = 1;
|
||||
ecat_state = next_ecat_state;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void config_qspi(void)
|
||||
{
|
||||
QSPI->INTENSET.bit.CSRISE = 1;
|
||||
NVIC_EnableIRQ(QSPI_IRQn);
|
||||
ecat_state =en_SQI;
|
||||
}
|
||||
|
||||
QSPI_Handler(void){
|
||||
if (QSPI->INTFLAG.bit.CSRISE == 1){
|
||||
QSPI->INTFLAG.bit.CSRISE = 1;
|
||||
run_ECAT =true;
|
||||
}
|
||||
}
|
||||
|
||||
#include "EtherCAT_QSPI.h"
|
||||
|
||||
/**
|
||||
* Example of using TIMER_0.
|
||||
*/
|
||||
static void onems_tick(const struct timer_task *const timer_task)
|
||||
{
|
||||
if ((ecat_state == wait2)|(ecat_state == wait)) ecat_state= write_fifo;
|
||||
|
||||
if ((ecat_state == wait2)|(ecat_state == wait)) ecat_state= write_fifo;
|
||||
|
||||
run_ECAT =true;
|
||||
//run_ECAT = true;
|
||||
}
|
||||
|
|
@ -249,7 +25,6 @@ void onemstimer_init(void)
|
|||
}
|
||||
|
||||
|
||||
|
||||
int main(void)
|
||||
{
|
||||
volatile uint8_t m2_hall, m1_hall, x= 0;
|
||||
|
|
@ -259,12 +34,15 @@ int main(void)
|
|||
ECAT_STATE_MACHINE();
|
||||
onemstimer_init();
|
||||
|
||||
|
||||
/* Replace with your application code */
|
||||
while (1) {
|
||||
//delay_ms(100);
|
||||
//m1_hall = readM1Hall();
|
||||
//m2_hall = readM2Hall();
|
||||
//x += 1;
|
||||
QSPI_tx_buffer[0] += 1;
|
||||
if (run_ECAT) ECAT_STATE_MACHINE();
|
||||
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue