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removed use of spi_m_dma_transfer

This commit is contained in:
Nicolas Trimborn 2021-08-19 10:50:27 +02:00
parent 012e0f87c5
commit 412654754c
6 changed files with 111 additions and 51 deletions
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1
2_Motor_Master/Motor_Master/Motor_Master/Ethercat_QSPI.c
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@ -206,6 +206,7 @@ void config_qspi()
{
QSPI->INTENSET.bit.CSRISE = 1;
NVIC_EnableIRQ(QSPI_IRQn);
NVIC_SetPriority(QSPI_IRQn, 3);
ecat_state =en_SQI;
}

57
2_Motor_Master/Motor_Master/Motor_Master/configuration.h
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@ -16,14 +16,12 @@
#include "bldc.h"
#include "interrupts.h"
// ----------------------------------------------------------------------
// ADC DMA Initialization
// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
// ----------------------------------------------------------------------
#define DMAC_CHANNEL_ADC_SEQ 2U
#define DMAC_CHANNEL_ADC_SRAM 3U
#define DMAC_CHANNEL_ADC_SEQ 2U
#define DMAC_CHANNEL_ADC_SRAM 3U
/* Single Ended */
//const uint32_t adc_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808};
@ -147,6 +145,31 @@ inline void adc_sram_dmac_init()
// Init SPI DMA communication between Master & Slave Board
// ----------------------------------------------------------------------
#define MASTER_BUFFER_SIZE 64
/* DMA channel Descriptor */
extern DmacDescriptor _descriptor_section[DMAC_CH_NUM];
extern DmacDescriptor _write_back_section[DMAC_CH_NUM];
struct SPI_slaveboard {
struct spi_m_dma_descriptor *SPI_Mn;
uint8_t state;
uint32_t SS_pin;
uint32_t *tx_buffer;
uint32_t *rx_buffer;
};
struct SPI_slaveboard Slave_1 = {
.SPI_Mn = &SPI_1_MSIF,
.state = 0,
.SS_pin = SPI1_CS,
.tx_buffer = &QSPI_tx_buffer[16],
.rx_buffer = &QSPI_rx_buffer[16],
};
#define DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE 0u
#define DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT 1U
void boardToBoardTransferInit(void)
{
struct io_descriptor *io;
@ -157,5 +180,31 @@ void boardToBoardTransferInit(void)
spi_m_dma_enable(&SPI_1_MSIF);
}
void init_spi_master_dma_descriptors()
{
_dma_set_source_address(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE,
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
_dma_set_destination_address(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, &Slave_1.rx_buffer[0]);
_dma_set_data_amount(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, MASTER_BUFFER_SIZE);
_dma_set_source_address(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, &Slave_1.tx_buffer[0]);
_dma_set_destination_address(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT,
(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
_dma_set_data_amount(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, MASTER_BUFFER_SIZE);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE]);
hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT]);
/* callback */
struct _dma_resource *resource_rx, *resource_tx;
_dma_get_channel_resource(&resource_rx, DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE);
_dma_get_channel_resource(&resource_tx, DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT);
//resource_rx->dma_cb.transfer_done = spi_slave_rx_complete_cb;
//resource_tx->dma_cb.transfer_done = b2bTransferComplete_cb;
/* Enable DMA transfer complete interrupt */
//_dma_set_irq_state(CONF_SERCOM_1_RECEIVE_DMA_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
}
#endif /* CONFIGURATION_H_ */

26
2_Motor_Master/Motor_Master/Motor_Master/interrupts.h
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@ -9,13 +9,37 @@
#ifndef INTERRUPTS_H_
#define INTERRUPTS_H_
static void One_ms_cycle_callback(const struct timer_task *const timer_task)
{
if ((ecat_state == wait2)|(ecat_state == wait))
{
ecat_state= write_fifo;
run_ECAT =true;
}
Motor1.timerflags.motor_telemetry_flag = true;
Motor2.timerflags.motor_telemetry_flag = true;
/*Master Slave Transfer */
//tx_buffer[0] += 1;
//tx_buffer[31] += 1;
//gpio_set_pin_level(SPI1_CS, false);
//spi_m_dma_transfer(&SPI_1_MSIF, (uint8_t*)Slave_1.tx_buffer, (uint8_t*)Slave_1.rx_buffer, MASTER_BUFFER_SIZE);
//run_ECAT = true;
}
// ----------------------------------------------------------------------
// Master/Slave IF Callback
// ----------------------------------------------------------------------
static void b2bTransferComplete_cb(struct _dma_resource *resource)
{
gpio_set_pin_level(SPI1_CS, true);
PORT->Group[1].OUTSET.reg = (1<<GPIO_PIN(SPI1_CS));
//PORT->Group[1].OUTSET.reg = (1<<SPI1_CS);
//PORT->Group[GPIO_PORTB].OUTCLR.reg = (1<<Slave_1->SS_pin);
//gpio_set_pin_level(SPI1_CS, true);
}

64
2_Motor_Master/Motor_Master/Motor_Master/main.c
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@ -12,24 +12,6 @@
#include "interrupts.h"
#include "statemachine.h"
#define MASTER_BUFFER_SIZE 64
struct SPI_slaveboard {
struct spi_m_dma_descriptor *SPI_Mn;
uint8_t state;
uint32_t SS_pin;
uint32_t *tx_buffer;
uint32_t *rx_buffer;
};
struct SPI_slaveboard Slave_1 = {
.SPI_Mn = &SPI_1_MSIF,
.state = 0,
.SS_pin = SPI1_CS,
.tx_buffer = &QSPI_tx_buffer[16],
.rx_buffer = &QSPI_rx_buffer[16],
};
@ -67,25 +49,6 @@ void process_currents()
/**
* Example of using TIMER_0.
*/
static void One_ms_cycle_callback(const struct timer_task *const timer_task)
{
if ((ecat_state == wait2)|(ecat_state == wait))
{
ecat_state= write_fifo;
run_ECAT =true;
}
update_telemetry();
update_setpoints();
/*Master Slave Transfer */
//tx_buffer[0] += 1;
//tx_buffer[31] += 1;
//gpio_set_pin_level(SPI1_CS, false);
//spi_m_dma_transfer(&SPI_1_MSIF, (uint8_t*)Slave_1.tx_buffer, (uint8_t*)Slave_1.rx_buffer, MASTER_BUFFER_SIZE);
//run_ECAT = true;
}
static struct timer_task Onems_task;
@ -109,13 +72,15 @@ void One_ms_timer_init(void)
void enable_NVIC_IRQ(void)
{
ext_irq_register(M1_RST_Bar, M1_RESET_BAR);
ext_irq_register(M2_RST_Bar, M2_RESET_BAR);
NVIC_EnableIRQ(TC2_IRQn); // TC2: M1_Speed_Timer
NVIC_EnableIRQ(TC4_IRQn); // TC4: M2_Speed_Timer
//ext_irq_register(M1_RST_Bar, M1_RESET_BAR);
//ext_irq_register(M2_RST_Bar, M2_RESET_BAR);
//NVIC_EnableIRQ(TC2_IRQn); // TC2: M1_Speed_Timer
//NVIC_EnableIRQ(TC4_IRQn); // TC4: M2_Speed_Timer
NVIC_EnableIRQ(DMAC_0_IRQn);
//NVIC_SetPriority(DMAC_0_IRQn, 1);
NVIC_EnableIRQ(TCC0_0_IRQn);
NVIC_EnableIRQ(TCC1_0_IRQn);
NVIC_EnableIRQ(TCC1_0_IRQn);
//NVIC_SetPriority(TCC0_0_IRQn, 3);
//NVIC_EnableIRQ(EIC_5_IRQn);
}
@ -200,8 +165,9 @@ int main(void)
config_qspi();
configure_tcc_pwm();
adc_sync_enable_channel(&ADC_1, 6);
adc_init_dma();
boardToBoardTransferInit();
init_spi_master_dma_descriptors();
adc_init_dma();
ECAT_STATE_MACHINE();
One_ms_timer_init();
custom_logic_enable();
@ -211,6 +177,18 @@ int main(void)
/* Replace with your application code */
while (1) {
if (Motor1.timerflags.adc_readings_ready_tic) {process_currents();}
if (Motor1.timerflags.motor_telemetry_flag) {
Motor1.timerflags.motor_telemetry_flag = false;
update_telemetry();
update_setpoints();
PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
//PORT->Group[1].OUTCLR.reg = (1<<SPI1_CS);
//gpio_set_pin_level(SPI1_CS, false);
_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, false);
_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, false);
//spi_m_dma_transfer(&SPI_1_MSIF, (uint8_t*)Slave_1.tx_buffer, (uint8_t*)Slave_1.rx_buffer, MASTER_BUFFER_SIZE);
}
if (Motor1.timerflags.current_loop_tic) {
APPLICATION_StateMachine();
exec_commutation(&Motor1);

14
2_Motor_Slave/Motor_Slave/Motor_Slave/main.c
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@ -58,8 +58,10 @@ static void One_ms_cycle_callback(const struct timer_task *const timer_task)
//}
Motor1.timerflags.current_loop_tic = true;
Motor2.timerflags.current_loop_tic = true;
update_telemetry();
update_setpoints();
Motor1.timerflags.motor_telemetry_flag = true;
Motor2.timerflags.motor_telemetry_flag = true;
//update_telemetry();
//update_setpoints();
//run_ECAT = true;
@ -215,8 +217,14 @@ int main(void)
exec_commutation(&Motor1);
exec_commutation(&Motor2);
}
//if (run_ECAT) {ECAT_STATE_MACHINE();}
if (Motor1.timerflags.motor_telemetry_flag) {
Motor1.timerflags.motor_telemetry_flag = false;
update_telemetry();
update_setpoints();
}
//if (run_ECAT) {ECAT_STATE_MACHINE();}
}
}

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Twincat/MotorData/.vs/MotorData/v15/.suo
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