modified more locations with preprocessor directives

2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart

@@ -259,11 +259,11 @@ drivers:
       dmac_beatsize_27: 8-bit bus transfer
       dmac_beatsize_28: 8-bit bus transfer
       dmac_beatsize_29: 8-bit bus transfer
-      dmac_beatsize_3: 32-bit bus transfer
+      dmac_beatsize_3: 16-bit bus transfer
       dmac_beatsize_30: 8-bit bus transfer
       dmac_beatsize_31: 8-bit bus transfer
-      dmac_beatsize_4: 16-bit bus transfer
+      dmac_beatsize_4: 32-bit bus transfer
-      dmac_beatsize_5: 16-bit bus transfer
+      dmac_beatsize_5: 32-bit bus transfer
       dmac_beatsize_6: 32-bit bus transfer
       dmac_beatsize_7: 32-bit bus transfer
       dmac_beatsize_8: 32-bit bus transfer
@@ -272,8 +272,7 @@ drivers:
         the transaction
       dmac_blockact_1: Channel will be disabled if it is the last block transfer in
         the transaction
-      dmac_blockact_10: Channel will be disabled if it is the last block transfer
+      dmac_blockact_10: Channel suspend operation is complete
-        in the transaction
       dmac_blockact_11: Channel will be disabled if it is the last block transfer
         in the transaction
       dmac_blockact_12: Channel will be disabled if it is the last block transfer
@@ -315,23 +314,19 @@ drivers:
       dmac_blockact_29: Channel will be disabled if it is the last block transfer
         in the transaction
       dmac_blockact_3: Channel will be disabled if it is the last block transfer in
-        the transaction
+        the transaction and block interrupt
       dmac_blockact_30: Channel will be disabled if it is the last block transfer
         in the transaction
       dmac_blockact_31: Channel will be disabled if it is the last block transfer
         in the transaction
-      dmac_blockact_4: Channel will be disabled if it is the last block transfer in
+      dmac_blockact_4: Channel suspend operation is complete
-        the transaction and block interrupt
+      dmac_blockact_5: Channel suspend operation is complete
-      dmac_blockact_5: Channel will be disabled if it is the last block transfer in
-        the transaction and block interrupt
       dmac_blockact_6: Channel suspend operation is complete
       dmac_blockact_7: Channel suspend operation is complete
-      dmac_blockact_8: Channel will be disabled if it is the last block transfer in
+      dmac_blockact_8: Channel suspend operation is complete
-        the transaction
+      dmac_blockact_9: Channel suspend operation is complete
-      dmac_blockact_9: Channel will be disabled if it is the last block transfer in
+      dmac_channel_0_settings: true
-        the transaction
+      dmac_channel_10_settings: false
-      dmac_channel_0_settings: false
-      dmac_channel_10_settings: true
       dmac_channel_11_settings: false
       dmac_channel_12_settings: false
       dmac_channel_13_settings: false
@@ -358,10 +353,10 @@ drivers:
       dmac_channel_3_settings: true
       dmac_channel_4_settings: true
       dmac_channel_5_settings: true
-      dmac_channel_6_settings: false
+      dmac_channel_6_settings: true
       dmac_channel_7_settings: true
-      dmac_channel_8_settings: true
+      dmac_channel_8_settings: false
-      dmac_channel_9_settings: true
+      dmac_channel_9_settings: false
       dmac_dbgrun: false
       dmac_dstinc_0: true
       dmac_dstinc_1: true
@@ -389,8 +384,8 @@ drivers:
       dmac_dstinc_3: true
       dmac_dstinc_30: false
       dmac_dstinc_31: false
-      dmac_dstinc_4: true
+      dmac_dstinc_4: false
-      dmac_dstinc_5: true
+      dmac_dstinc_5: false
       dmac_dstinc_6: false
       dmac_dstinc_7: false
       dmac_dstinc_8: false
@@ -398,7 +393,7 @@ drivers:
       dmac_enable: true
       dmac_evact_0: No action
       dmac_evact_1: No action
-      dmac_evact_10: No action
+      dmac_evact_10: Channel resume operation
       dmac_evact_11: No action
       dmac_evact_12: No action
       dmac_evact_13: No action
@@ -422,15 +417,15 @@ drivers:
       dmac_evact_3: No action
       dmac_evact_30: No action
       dmac_evact_31: No action
-      dmac_evact_4: No action
+      dmac_evact_4: Channel resume operation
-      dmac_evact_5: No action
+      dmac_evact_5: Channel resume operation
       dmac_evact_6: Channel resume operation
       dmac_evact_7: Channel resume operation
-      dmac_evact_8: No action
+      dmac_evact_8: Channel resume operation
-      dmac_evact_9: No action
+      dmac_evact_9: Channel resume operation
       dmac_evie_0: false
       dmac_evie_1: false
-      dmac_evie_10: false
+      dmac_evie_10: true
       dmac_evie_11: false
       dmac_evie_12: false
       dmac_evie_13: false
@@ -440,7 +435,7 @@ drivers:
       dmac_evie_17: false
       dmac_evie_18: false
       dmac_evie_19: false
-      dmac_evie_2: true
+      dmac_evie_2: false
       dmac_evie_20: false
       dmac_evie_21: false
       dmac_evie_22: false
@@ -454,13 +449,13 @@ drivers:
       dmac_evie_3: false
       dmac_evie_30: false
       dmac_evie_31: false
-      dmac_evie_4: false
+      dmac_evie_4: true
-      dmac_evie_5: false
+      dmac_evie_5: true
       dmac_evie_6: true
       dmac_evie_7: true
-      dmac_evie_8: false
+      dmac_evie_8: true
-      dmac_evie_9: false
+      dmac_evie_9: true
-      dmac_evoe_0: false
+      dmac_evoe_0: true
       dmac_evoe_1: true
       dmac_evoe_10: false
       dmac_evoe_11: false
@@ -492,7 +487,7 @@ drivers:
       dmac_evoe_7: false
       dmac_evoe_8: false
       dmac_evoe_9: false
-      dmac_evosel_0: Event generation disabled
+      dmac_evosel_0: Event strobe when block transfer complete
       dmac_evosel_1: Event strobe when block transfer complete
       dmac_evosel_10: Event generation disabled
       dmac_evosel_11: Event generation disabled
@@ -504,7 +499,7 @@ drivers:
       dmac_evosel_17: Event generation disabled
       dmac_evosel_18: Event generation disabled
       dmac_evosel_19: Event generation disabled
-      dmac_evosel_2: Event strobe when beat transfer complete
+      dmac_evosel_2: Event strobe when block transfer complete
       dmac_evosel_20: Event generation disabled
       dmac_evosel_21: Event generation disabled
       dmac_evosel_22: Event generation disabled
@@ -626,8 +621,8 @@ drivers:
       dmac_srcinc_3: false
       dmac_srcinc_30: false
       dmac_srcinc_31: false
-      dmac_srcinc_4: false
+      dmac_srcinc_4: true
-      dmac_srcinc_5: false
+      dmac_srcinc_5: true
       dmac_srcinc_6: true
       dmac_srcinc_7: true
       dmac_srcinc_8: true
@@ -696,8 +691,8 @@ drivers:
       dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
       dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
       dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
-      dmac_trifsrc_0: QSPI Rx Trigger
+      dmac_trifsrc_0: SERCOM1 RX Trigger
-      dmac_trifsrc_1: SERCOM1 RX Trigger
+      dmac_trifsrc_1: SERCOM5 RX Trigger
       dmac_trifsrc_10: SERCOM1 TX Trigger
       dmac_trifsrc_11: QSPI Tx Trigger
       dmac_trifsrc_12: Only software/event triggers
@@ -719,13 +714,13 @@ drivers:
       dmac_trifsrc_27: Only software/event triggers
       dmac_trifsrc_28: Only software/event triggers
       dmac_trifsrc_29: Only software/event triggers
-      dmac_trifsrc_3: SERCOM5 RX Trigger
+      dmac_trifsrc_3: ADC1 Result Ready Trigger
       dmac_trifsrc_30: Only software/event triggers
       dmac_trifsrc_31: Only software/event triggers
-      dmac_trifsrc_4: ADC0 Result Ready Trigger
+      dmac_trifsrc_4: ADC1 Sequencing Trigger
-      dmac_trifsrc_5: ADC1 Result Ready Trigger
+      dmac_trifsrc_5: SERCOM2 TX Trigger
-      dmac_trifsrc_6: ADC0 Sequencing Trigger
+      dmac_trifsrc_6: SERCOM5 TX Trigger
-      dmac_trifsrc_7: ADC1 Sequencing Trigger
+      dmac_trifsrc_7: SERCOM1 TX Trigger
       dmac_trifsrc_8: SERCOM2 TX Trigger
       dmac_trifsrc_9: SERCOM5 TX Trigger
       dmac_trigact_0: One trigger required for each beat transfer
@@ -776,8 +771,8 @@ drivers:
       eic_arch_asynch11: false
       eic_arch_asynch12: false
       eic_arch_asynch13: false
-      eic_arch_asynch14: true
+      eic_arch_asynch14: false
-      eic_arch_asynch15: true
+      eic_arch_asynch15: false
       eic_arch_asynch2: true
       eic_arch_asynch3: false
       eic_arch_asynch4: false
@@ -827,7 +822,7 @@ drivers:
       eic_arch_extinteo13: false
       eic_arch_extinteo14: false
       eic_arch_extinteo15: false
-      eic_arch_extinteo2: false
+      eic_arch_extinteo2: true
       eic_arch_extinteo3: false
       eic_arch_extinteo4: false
       eic_arch_extinteo5: false
@@ -841,8 +836,8 @@ drivers:
       eic_arch_filten11: false
       eic_arch_filten12: false
       eic_arch_filten13: false
-      eic_arch_filten14: false
+      eic_arch_filten14: true
-      eic_arch_filten15: false
+      eic_arch_filten15: true
       eic_arch_filten2: false
       eic_arch_filten3: false
       eic_arch_filten4: false
@@ -863,8 +858,8 @@ drivers:
       eic_arch_sense11: No detection
       eic_arch_sense12: No detection
       eic_arch_sense13: No detection
-      eic_arch_sense14: Both-edges detection
+      eic_arch_sense14: Falling-edge detection
-      eic_arch_sense15: Both-edges detection
+      eic_arch_sense15: Falling-edge detection
       eic_arch_sense2: Falling-edge detection
       eic_arch_sense3: No detection
       eic_arch_sense4: No detection
@@ -922,14 +917,14 @@ drivers:
     api: HAL:Driver:Event_system
     configuration:
       evsys_channel_0: No channel output selected
-      evsys_channel_1: Channel 3
+      evsys_channel_1: Channel 1
-      evsys_channel_10: No channel output selected
+      evsys_channel_10: Channel 5
-      evsys_channel_11: No channel output selected
+      evsys_channel_11: Channel 4
-      evsys_channel_12: Channel 0
+      evsys_channel_12: Channel 2
       evsys_channel_17: No channel output selected
       evsys_channel_18: No channel output selected
       evsys_channel_19: No channel output selected
-      evsys_channel_2: Channel 4
+      evsys_channel_2: Channel 6
       evsys_channel_20: No channel output selected
       evsys_channel_21: No channel output selected
       evsys_channel_22: No channel output selected
@@ -940,7 +935,7 @@ drivers:
       evsys_channel_27: No channel output selected
       evsys_channel_28: No channel output selected
       evsys_channel_29: No channel output selected
-      evsys_channel_3: No channel output selected
+      evsys_channel_3: Channel 5
       evsys_channel_30: No channel output selected
       evsys_channel_31: No channel output selected
       evsys_channel_32: No channel output selected
@@ -951,16 +946,16 @@ drivers:
       evsys_channel_37: No channel output selected
       evsys_channel_38: No channel output selected
       evsys_channel_39: No channel output selected
-      evsys_channel_4: No channel output selected
+      evsys_channel_4: Channel 8
       evsys_channel_40: No channel output selected
       evsys_channel_41: No channel output selected
       evsys_channel_42: No channel output selected
       evsys_channel_43: No channel output selected
       evsys_channel_44: No channel output selected
       evsys_channel_45: No channel output selected
-      evsys_channel_46: Channel 1
+      evsys_channel_46: Channel 11
       evsys_channel_47: No channel output selected
-      evsys_channel_48: Channel 2
+      evsys_channel_48: Channel 12
       evsys_channel_49: No channel output selected
       evsys_channel_5: No channel output selected
       evsys_channel_50: No channel output selected
@@ -983,12 +978,12 @@ drivers:
       evsys_channel_66: No channel output selected
       evsys_channel_7: No channel output selected
       evsys_channel_8: No channel output selected
-      evsys_channel_9: No channel output selected
+      evsys_channel_9: Channel 0
       evsys_channel_setting_0: true
       evsys_channel_setting_1: true
       evsys_channel_setting_10: false
-      evsys_channel_setting_11: false
+      evsys_channel_setting_11: true
-      evsys_channel_setting_12: false
+      evsys_channel_setting_12: true
       evsys_channel_setting_13: false
       evsys_channel_setting_14: false
       evsys_channel_setting_15: false
@@ -996,7 +991,7 @@ drivers:
       evsys_channel_setting_17: false
       evsys_channel_setting_18: false
       evsys_channel_setting_19: false
-      evsys_channel_setting_2: true
+      evsys_channel_setting_2: false
       evsys_channel_setting_20: false
       evsys_channel_setting_21: false
       evsys_channel_setting_22: false
@@ -1007,25 +1002,25 @@ drivers:
       evsys_channel_setting_27: false
       evsys_channel_setting_28: false
       evsys_channel_setting_29: false
-      evsys_channel_setting_3: true
+      evsys_channel_setting_3: false
       evsys_channel_setting_30: false
       evsys_channel_setting_31: false
-      evsys_channel_setting_4: true
+      evsys_channel_setting_4: false
       evsys_channel_setting_5: true
-      evsys_channel_setting_6: false
+      evsys_channel_setting_6: true
-      evsys_channel_setting_7: false
+      evsys_channel_setting_7: true
-      evsys_channel_setting_8: false
+      evsys_channel_setting_8: true
       evsys_channel_setting_9: false
       evsys_edgsel_0: No event output when using the resynchronized or synchronous
         path
-      evsys_edgsel_1: No event output when using the resynchronized or synchronous
+      evsys_edgsel_1: Event is detected on the rising edge of the signal from event
-        path
+        generator
       evsys_edgsel_10: No event output when using the resynchronized or synchronous
         path
-      evsys_edgsel_11: No event output when using the resynchronized or synchronous
+      evsys_edgsel_11: Event is detected on the rising edge of the signal from event
-        path
+        generator
-      evsys_edgsel_12: No event output when using the resynchronized or synchronous
+      evsys_edgsel_12: Event is detected on the rising edge of the signal from event
-        path
+        generator
       evsys_edgsel_13: No event output when using the resynchronized or synchronous
         path
       evsys_edgsel_14: No event output when using the resynchronized or synchronous
@@ -1040,8 +1035,8 @@ drivers:
         path
       evsys_edgsel_19: No event output when using the resynchronized or synchronous
         path
-      evsys_edgsel_2: No event output when using the resynchronized or synchronous
+      evsys_edgsel_2: Event is detected on the rising edge of the signal from event
-        path
+        generator
       evsys_edgsel_20: No event output when using the resynchronized or synchronous
         path
       evsys_edgsel_21: No event output when using the resynchronized or synchronous
@@ -1072,12 +1067,12 @@ drivers:
         generator
       evsys_edgsel_5: Event is detected on the rising edge of the signal from event
         generator
-      evsys_edgsel_6: No event output when using the resynchronized or synchronous
+      evsys_edgsel_6: Event is detected on the rising edge of the signal from event
-        path
+        generator
       evsys_edgsel_7: No event output when using the resynchronized or synchronous
         path
-      evsys_edgsel_8: No event output when using the resynchronized or synchronous
+      evsys_edgsel_8: Event is detected on the rising edge of the signal from event
-        path
+        generator
       evsys_edgsel_9: No event output when using the resynchronized or synchronous
         path
       evsys_evd_0: false
@@ -1107,16 +1102,16 @@ drivers:
       evsys_evd_30: false
       evsys_evd_31: false
       evsys_evd_4: true
-      evsys_evd_5: true
+      evsys_evd_5: false
-      evsys_evd_6: false
+      evsys_evd_6: true
-      evsys_evd_7: false
+      evsys_evd_7: true
-      evsys_evd_8: false
+      evsys_evd_8: true
       evsys_evd_9: false
       evsys_evgen_0: TCC0 overflow
-      evsys_evgen_1: CCL LUT output 0
+      evsys_evgen_1: TC0 match/capture 0
       evsys_evgen_10: No event generator
-      evsys_evgen_11: No event generator
+      evsys_evgen_11: CCL LUT output 0
-      evsys_evgen_12: No event generator
+      evsys_evgen_12: CCL LUT output 2
       evsys_evgen_13: No event generator
       evsys_evgen_14: No event generator
       evsys_evgen_15: No event generator
@@ -1124,7 +1119,7 @@ drivers:
       evsys_evgen_17: No event generator
       evsys_evgen_18: No event generator
       evsys_evgen_19: No event generator
-      evsys_evgen_2: CCL LUT output 2
+      evsys_evgen_2: TC0 match/capture 1
       evsys_evgen_20: No event generator
       evsys_evgen_21: No event generator
       evsys_evgen_22: No event generator
@@ -1138,11 +1133,11 @@ drivers:
       evsys_evgen_3: TC0 match/capture 0
       evsys_evgen_30: No event generator
       evsys_evgen_31: No event generator
-      evsys_evgen_4: DMAC channel 1
+      evsys_evgen_4: TC0 match/capture 1
-      evsys_evgen_5: DMAC channel 2
+      evsys_evgen_5: EIC external interrupt 2
-      evsys_evgen_6: No event generator
+      evsys_evgen_6: DMAC channel 0
-      evsys_evgen_7: No event generator
+      evsys_evgen_7: DMAC channel 1
-      evsys_evgen_8: No event generator
+      evsys_evgen_8: DMAC channel 2
       evsys_evgen_9: No event generator
       evsys_ondemand_0: false
       evsys_ondemand_1: false
@@ -1211,8 +1206,8 @@ drivers:
       evsys_path_0: Asynchronous path
       evsys_path_1: Asynchronous path
       evsys_path_10: Synchronous path
-      evsys_path_11: Synchronous path
+      evsys_path_11: Asynchronous path
-      evsys_path_12: Synchronous path
+      evsys_path_12: Asynchronous path
       evsys_path_13: Synchronous path
       evsys_path_14: Synchronous path
       evsys_path_15: Synchronous path
@@ -1234,8 +1229,8 @@ drivers:
       evsys_path_3: Asynchronous path
       evsys_path_30: Synchronous path
       evsys_path_31: Synchronous path
-      evsys_path_4: Synchronous path
+      evsys_path_4: Asynchronous path
-      evsys_path_5: Synchronous path
+      evsys_path_5: Asynchronous path
       evsys_path_6: Synchronous path
       evsys_path_7: Synchronous path
       evsys_path_8: Synchronous path
@@ -1348,7 +1343,7 @@ drivers:
       $input_id: External Crystal Oscillator 8-48MHz (XOSC1)
       RESERVED_InputFreq: 12000000
       RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1)
-      _$freq_output_Generic clock generator 0: 120000000
+      _$freq_output_Generic clock generator 0: 100000000
       _$freq_output_Generic clock generator 1: 2000000
       _$freq_output_Generic clock generator 10: 12000000
       _$freq_output_Generic clock generator 11: 12000000
@@ -1490,11 +1485,11 @@ drivers:
     functionality: System
     api: HAL:HPL:MCLK
     configuration:
-      $input: 120000000
+      $input: 100000000
       $input_id: Generic clock generator 0
-      RESERVED_InputFreq: 120000000
+      RESERVED_InputFreq: 100000000
       RESERVED_InputFreq_id: Generic clock generator 0
-      _$freq_output_CPU: 120000000
+      _$freq_output_CPU: 100000000
       cpu_clock_source: Generic clock generator 0
       cpu_div: '1'
       enable_cpu_clock: true
@@ -1557,7 +1552,7 @@ drivers:
       RESERVED_InputFreq_id: Generic clock generator 1
       _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
       _$freq_output_Digital Phase Locked Loop (DPLL0): 47985664
-      _$freq_output_Digital Phase Locked Loop (DPLL1): 120000000
+      _$freq_output_Digital Phase Locked Loop (DPLL1): 100000000
       _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000
       _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000
       dfll_arch_bplckc: false
@@ -1608,7 +1603,7 @@ drivers:
       fdpll1_arch_wuf: false
       fdpll1_clock_dcofilter: 0
       fdpll1_clock_div: 0
-      fdpll1_ldr: 59
+      fdpll1_ldr: 49
       fdpll1_ldrfrac: 0
       fdpll1_ref_clock: Generic clock generator 1
       xosc0_arch_cfden: false
@@ -1643,24 +1638,24 @@ drivers:
     configuration:
       enable_port_input_event_0: true
       enable_port_input_event_1: true
-      enable_port_input_event_2: false
+      enable_port_input_event_2: true
-      enable_port_input_event_3: false
+      enable_port_input_event_3: true
       porta_event_action_0: Output register of pin will be set to level of event
       porta_event_action_1: Output register of pin will be set to level of event
-      porta_event_action_2: Output register of pin will be set to level of event
+      porta_event_action_2: Clear output register of pin on event
-      porta_event_action_3: Output register of pin will be set to level of event
+      porta_event_action_3: Set output register of pin on event
       porta_event_pin_identifier_0: 0
       porta_event_pin_identifier_1: 0
-      porta_event_pin_identifier_2: 0
+      porta_event_pin_identifier_2: 14
-      porta_event_pin_identifier_3: 0
+      porta_event_pin_identifier_3: 14
       porta_input_event_enable_0: false
       porta_input_event_enable_1: false
-      porta_input_event_enable_2: false
+      porta_input_event_enable_2: true
-      porta_input_event_enable_3: false
+      porta_input_event_enable_3: true
       portb_event_action_0: Clear output register of pin on event
       portb_event_action_1: Set output register of pin on event
-      portb_event_action_2: Output register of pin will be set to level of event
+      portb_event_action_2: Clear output register of pin on event
-      portb_event_action_3: Output register of pin will be set to level of event
+      portb_event_action_3: Set output register of pin on event
       portb_event_pin_identifier_0: 22
       portb_event_pin_identifier_1: 22
       portb_event_pin_identifier_2: 0
@@ -1759,8 +1754,8 @@ drivers:
       spi_master_arch_runstdby: false
       spi_master_baud_rate: 2000000
       spi_master_character_size: 8 bits
-      spi_master_dma_rx_channel: 1
+      spi_master_dma_rx_channel: 0
-      spi_master_dma_tx_channel: 10
+      spi_master_dma_tx_channel: 7
       spi_master_dummybyte: 511
       spi_master_rx_channel: true
       spi_master_rx_enable: true
@@ -1802,9 +1797,9 @@ drivers:
       spi_master_arch_cpol: SCK is low when idle
       spi_master_arch_dbgstop: Keep running
       spi_master_arch_dord: MSB first
-      spi_master_arch_ibon: In data stream
+      spi_master_arch_ibon: On buffer overflow
       spi_master_arch_runstdby: false
-      spi_master_baud_rate: 4000000
+      spi_master_baud_rate: 1000000
       spi_master_character_size: 8 bits
       spi_master_dummybyte: 511
       spi_master_rx_enable: true
@@ -1848,7 +1843,7 @@ drivers:
       spi_master_arch_dord: MSB first
       spi_master_arch_ibon: In data stream
       spi_master_arch_runstdby: false
-      spi_master_baud_rate: 8000000
+      spi_master_baud_rate: 1000000
       spi_master_character_size: 8 bits
       spi_master_dummybyte: 511
       spi_master_rx_enable: true
@@ -1885,8 +1880,8 @@ drivers:
     functionality: Timer
     api: Lite:TC:Timer
     configuration:
-      cc_cc0: 117
+      cc_cc0: 10
-      cc_cc1: 180
+      cc_cc1: 60
       cc_control: true
       count_control: false
       count_count: 0
@@ -1901,7 +1896,7 @@ drivers:
       ctrla_enable: true
       ctrla_mode: 1
       ctrla_ondemand: false
-      ctrla_prescaler: DIV1024
+      ctrla_prescaler: DIV8
       ctrla_prescsync: GCLK
       ctrla_runstdby: false
       ctrlbset_cmd: NONE
@@ -1925,9 +1920,9 @@ drivers:
       intenset_err: false
       intenset_mc0: false
       intenset_mc1: true
-      intenset_ovf: false
+      intenset_ovf: true
       per_control: true
-      per_per: 255
+      per_per: 250
       wave_control: true
       wave_wavegen: NFRQ
     optional_signals: []
@@ -1936,11 +1931,11 @@ drivers:
       domain_group:
         nodes:
         - name: TC
-          input: Generic clock generator 0
+          input: Generic clock generator 1
           external: false
           external_frequency: 0
         configuration:
-          tc_gclk_selection: Generic clock generator 0
+          tc_gclk_selection: Generic clock generator 1
   TC_SPEED_M1:
     user_label: TC_SPEED_M1
     definition: Atmel:SAME51_Drivers:0.0.1::SAME51J19A-MF::TC2::driver_config_definition::32-bit.Counter.Mode::Lite:TC:Timer

2_Motor_Master/Motor_Master/Motor_Master/ADS1299.c

@@ -72,8 +72,8 @@ void initialize_ads()
 	ADS1299_WREG(LOFF,0x02);			   // Set LOFF Register
 	for(uint8_t i=CH1SET; i<=CH4SET; i++)  // set up to modify the 4 channel setting registers
 	{  
-		ADS1299.regData[i] = 0x68;        // the regData array mirrors the ADS1299 register addresses
+		//ADS1299.reg_data[i] = 0x68;        // the regData array mirrors the ADS1299 register addresses
-		//ADS1299.regData[i] = 0x6D;          // Test signal
+		ADS1299.reg_data[i] = 0x6D;          // Test signal
 	}
 	ADS1299_WREGS(CH1SET,3);               // write new channel settings
 	ADS1299_WREG(BIAS_SENSP,0xFF);		   // Set BIAS_SENSP Register
@@ -120,8 +120,21 @@ void ADS1299_START() {			//start data conversion
 	gpio_set_pin_level(ADS1299.SS_pin, false);
 	_transfer_byte(ADS1299.SPI_descr, _START);
 	gpio_set_pin_level(ADS1299.SS_pin, true);
+	init_streaming_mode();
+	
 }
 
+void init_streaming_mode()
+{
+	spi_m_sync_disable(ADS1299.SPI_descr);
+	/* Change to 32-Bit Mode */
+	SERCOM2->SPI.CTRLC.bit.ICSPACE = 4;
+	SERCOM2->SPI.CTRLC.bit.DATA32B= true;
+	SERCOM2->SPI.LENGTH.bit.LENEN = true;
+	SERCOM2->SPI.LENGTH.bit.LEN = 3;
+	/* Init SPI*/
+	spi_m_sync_enable(ADS1299.SPI_descr);
+}
 void ADS1299_STOP() {			//stop data conversion
 	gpio_set_pin_level(ADS1299.SS_pin, false);
 	_transfer_byte(ADS1299.SPI_descr, _STOP);
@@ -151,9 +164,9 @@ uint8_t ADS1299_RREG(uint8_t _address)
 	gpio_set_pin_level(ADS1299.SS_pin, false);
 	_transfer_byte(ADS1299.SPI_descr, opcode1);
 	_transfer_byte(ADS1299.SPI_descr, 0x00);
-	ADS1299.regData[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00);
+	ADS1299.reg_data[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00);
 	gpio_set_pin_level(ADS1299.SS_pin, true);
-	return ADS1299.regData[_address];
+	return ADS1299.reg_data[_address];
 }
 
 // Read more than one register starting at _address
@@ -164,7 +177,7 @@ void ADS1299_RREGS(uint8_t _address, uint8_t _numRegistersMinusOne)
 	_transfer_byte(ADS1299.SPI_descr, opcode1);
 	_transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne);
 	for(int i = 0; i <= _numRegistersMinusOne; i++){			//  add register uint8_t to mirror array
-        ADS1299.regData[_address + i] = _transfer_byte(ADS1299.SPI_descr, 0x00);	
+        ADS1299.reg_data[_address + i] = _transfer_byte(ADS1299.SPI_descr, 0x00);	
 	}
 	//ADS1299.regData[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00);
 	gpio_set_pin_level(ADS1299.SS_pin, true);
@@ -177,7 +190,7 @@ void ADS1299_WREG(uint8_t _address, uint8_t _value) {					//  Write ONE register
 	_transfer_byte(ADS1299.SPI_descr, 0x00);						//	Send number of registers to read -1
 	_transfer_byte(ADS1299.SPI_descr, _value);					//  Write the value to the register
 	gpio_set_pin_level(ADS1299.SS_pin, true);					//  close SPI
-	ADS1299.regData[_address] = _value;							//  update the mirror array
+	ADS1299.reg_data[_address] = _value;							//  update the mirror array
 }
 
 void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne) {
@@ -186,7 +199,7 @@ void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne) {
 	_transfer_byte(ADS1299.SPI_descr, opcode1);					//  Send WREG command & address
 	_transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne);	//	Send number of registers to read -1
 	for (int i=_address; i <=(_address + _numRegistersMinusOne); i++){
-		_transfer_byte(ADS1299.SPI_descr, ADS1299.regData[i]);	//  Write to the registers
+		_transfer_byte(ADS1299.SPI_descr, ADS1299.reg_data[i]);	//  Write to the registers
 	}
 	gpio_set_pin_level(ADS1299.SS_pin, true);					//  close SPI
 }
@@ -256,7 +269,7 @@ void ADS1299_RDATA() {	//  use in Stop Read Continuous mode when DRDY goes low
 int32_t* ADS1299_UPDATECHANNELDATA()
 {
 	uint8_t inByte;
-	int nchan=4;  //assume 8 channel.  If needed, it automatically changes to 16 automatically in a later block.
+	int nchan=8;  //assume 8 channel.  If needed, it automatically changes to 16 automatically in a later block.
 	gpio_set_pin_level(ADS1299.SS_pin, false);				//  open SPI
 	
 	// READ CHANNEL DATA FROM FIRST ADS IN DAISY LINE
@@ -268,7 +281,7 @@ int32_t* ADS1299_UPDATECHANNELDATA()
 	for(int i = 0; i<8; i++){
 		for(int j=0; j<3; j++){		//  read 24 bits of channel data from 1st ADS in 8 3 byte chunks
 			inByte = _transfer_byte(ADS1299.SPI_descr, 0x00);
-			_channel_data[i] = (_channel_data[i]<<8) | inByte;
+			_ads1299_channel_data[i] = (_ads1299_channel_data[i]<<8) | inByte;
 		}
 	}
 		
@@ -276,13 +289,13 @@ int32_t* ADS1299_UPDATECHANNELDATA()
 	
 	//reformat the numbers
 	for(int i=0; i<nchan; i++){			// convert 3 byte 2's compliment to 4 byte 2's compliment	
-		if(bitRead(_channel_data[i],23) == 1){	
+		if(bitRead(_ads1299_channel_data[i],23) == 1){	
-			_channel_data[i] |= 0xFF000000;
+			_ads1299_channel_data[i] |= 0xFF000000;
 		}else{
-			_channel_data[i] &= 0x00FFFFFF;
+			_ads1299_channel_data[i] &= 0x00FFFFFF;
 		}
 	}
-	return &_channel_data;
+	return &_ads1299_channel_data;
 }
 
 uint8_t _transfer_byte(struct spi_m_sync_descriptor *spi, uint8_t command)

2_Motor_Master/Motor_Master/Motor_Master/ADS1299.h

@@ -52,8 +52,11 @@
 #define MISC2       0x16
 #define CONFIG4     0x17
 
-volatile int32_t _channel_data[8];
+#define ADS_BUFFER_SIZE 9
 
+volatile int32_t _ads1299_channel_data[9];
+volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
+volatile uint8_t _ads1299_reg_data[24];
 
 /* Struct Definitions */
 volatile struct SPI_ADS1299 {
@@ -61,8 +64,8 @@ volatile struct SPI_ADS1299 {
 	volatile bool data_ReadyFlag;
 	volatile uint32_t SS_pin;
 	volatile uint32_t reset_pin;
-	volatile uint8_t regData [24];
+	volatile uint8_t* reg_data;
-	volatile int32_t* channel_data; // Must Equal n_dev
+	volatile int32_t* channel_data; 
 	volatile int16_t  stat_1;
 };
 
@@ -71,11 +74,12 @@ static volatile struct SPI_ADS1299 ADS1299 = {
 	.data_ReadyFlag = false,
 	.SS_pin = SPI2_SS,
 	.reset_pin = ADS_RESET,
-	.regData = {0}, 
+	.reg_data = &_ads1299_reg_data[0], 
-	.channel_data = &_channel_data[0],
+	.channel_data = &_ads1299_channel_data[0],
 };
 
 void initialize_ads();
+void init_streaming_mode();
 
 //ADS1299 SPI Command Definitions (Datasheet, p35)
 //System Commands

2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_dmac_config.h

@@ -105,7 +105,7 @@
 // <e> Channel 0 settings
 // <id> dmac_channel_0_settings
 #ifndef CONF_DMAC_CHANNEL_0_SETTINGS
-#define CONF_DMAC_CHANNEL_0_SETTINGS 0
+#define CONF_DMAC_CHANNEL_0_SETTINGS 1
 #endif
 
 // <q> Channel Run in Standby
@@ -214,7 +214,7 @@
 // <i> Defines the peripheral trigger which is source of the transfer
 // <id> dmac_trifsrc_0
 #ifndef CONF_DMAC_TRIGSRC_0
-#define CONF_DMAC_TRIGSRC_0 83
+#define CONF_DMAC_TRIGSRC_0 6
 #endif
 
 // <o> Channel Arbitration Level
@@ -232,7 +232,7 @@
 // <i> Indicates whether channel event generation is enabled or not
 // <id> dmac_evoe_0
 #ifndef CONF_DMAC_EVOE_0
-#define CONF_DMAC_EVOE_0 0
+#define CONF_DMAC_EVOE_0 1
 #endif
 
 // <q> Channel Event Input
@@ -322,7 +322,7 @@
 // <i> Defines the event output selection
 // <id> dmac_evosel_0
 #ifndef CONF_DMAC_EVOSEL_0
-#define CONF_DMAC_EVOSEL_0 0
+#define CONF_DMAC_EVOSEL_0 1
 #endif
 // </e>
 
@@ -438,7 +438,7 @@
 // <i> Defines the peripheral trigger which is source of the transfer
 // <id> dmac_trifsrc_1
 #ifndef CONF_DMAC_TRIGSRC_1
-#define CONF_DMAC_TRIGSRC_1 6
+#define CONF_DMAC_TRIGSRC_1 14
 #endif
 
 // <o> Channel Arbitration Level
@@ -687,7 +687,7 @@
 // <i> Indicates whether channel event reception is enabled or not
 // <id> dmac_evie_2
 #ifndef CONF_DMAC_EVIE_2
-#define CONF_DMAC_EVIE_2 1
+#define CONF_DMAC_EVIE_2 0
 #endif
 
 // <o> Event Input Action
@@ -770,7 +770,7 @@
 // <i> Defines the event output selection
 // <id> dmac_evosel_2
 #ifndef CONF_DMAC_EVOSEL_2
-#define CONF_DMAC_EVOSEL_2 3
+#define CONF_DMAC_EVOSEL_2 1
 #endif
 // </e>
 
@@ -886,7 +886,7 @@
 // <i> Defines the peripheral trigger which is source of the transfer
 // <id> dmac_trifsrc_3
 #ifndef CONF_DMAC_TRIGSRC_3
-#define CONF_DMAC_TRIGSRC_3 14
+#define CONF_DMAC_TRIGSRC_3 70
 #endif
 
 // <o> Channel Arbitration Level
@@ -973,7 +973,7 @@
 // <i> Defines the size of one beat
 // <id> dmac_beatsize_3
 #ifndef CONF_DMAC_BEATSIZE_3
-#define CONF_DMAC_BEATSIZE_3 2
+#define CONF_DMAC_BEATSIZE_3 1
 #endif
 
 // <o> Block Action
@@ -984,7 +984,7 @@
 // <i> Defines the the DMAC should take after a block transfer has completed
 // <id> dmac_blockact_3
 #ifndef CONF_DMAC_BLOCKACT_3
-#define CONF_DMAC_BLOCKACT_3 0
+#define CONF_DMAC_BLOCKACT_3 1
 #endif
 
 // <o> Event Output Selection
@@ -1110,7 +1110,7 @@
 // <i> Defines the peripheral trigger which is source of the transfer
 // <id> dmac_trifsrc_4
 #ifndef CONF_DMAC_TRIGSRC_4
-#define CONF_DMAC_TRIGSRC_4 68
+#define CONF_DMAC_TRIGSRC_4 71
 #endif
 
 // <o> Channel Arbitration Level
@@ -1135,7 +1135,7 @@
 // <i> Indicates whether channel event reception is enabled or not
 // <id> dmac_evie_4
 #ifndef CONF_DMAC_EVIE_4
-#define CONF_DMAC_EVIE_4 0
+#define CONF_DMAC_EVIE_4 1
 #endif
 
 // <o> Event Input Action
@@ -1149,7 +1149,7 @@
 // <i> Defines the event input action
 // <id> dmac_evact_4
 #ifndef CONF_DMAC_EVACT_4
-#define CONF_DMAC_EVACT_4 0
+#define CONF_DMAC_EVACT_4 5
 #endif
 
 // <o> Address Increment Step Size
@@ -1180,14 +1180,14 @@
 // <i> Indicates whether the source address incrementation is enabled or not
 // <id> dmac_srcinc_4
 #ifndef CONF_DMAC_SRCINC_4
-#define CONF_DMAC_SRCINC_4 0
+#define CONF_DMAC_SRCINC_4 1
 #endif
 
 // <q> Destination Address Increment
 // <i> Indicates whether the destination address incrementation is enabled or not
 // <id> dmac_dstinc_4
 #ifndef CONF_DMAC_DSTINC_4
-#define CONF_DMAC_DSTINC_4 1
+#define CONF_DMAC_DSTINC_4 0
 #endif
 
 // <o> Beat Size
@@ -1197,7 +1197,7 @@
 // <i> Defines the size of one beat
 // <id> dmac_beatsize_4
 #ifndef CONF_DMAC_BEATSIZE_4
-#define CONF_DMAC_BEATSIZE_4 1
+#define CONF_DMAC_BEATSIZE_4 2
 #endif
 
 // <o> Block Action
@@ -1208,7 +1208,7 @@
 // <i> Defines the the DMAC should take after a block transfer has completed
 // <id> dmac_blockact_4
 #ifndef CONF_DMAC_BLOCKACT_4
-#define CONF_DMAC_BLOCKACT_4 1
+#define CONF_DMAC_BLOCKACT_4 2
 #endif
 
 // <o> Event Output Selection
@@ -1334,7 +1334,7 @@
 // <i> Defines the peripheral trigger which is source of the transfer
 // <id> dmac_trifsrc_5
 #ifndef CONF_DMAC_TRIGSRC_5
-#define CONF_DMAC_TRIGSRC_5 70
+#define CONF_DMAC_TRIGSRC_5 9
 #endif
 
 // <o> Channel Arbitration Level
@@ -1359,7 +1359,7 @@
 // <i> Indicates whether channel event reception is enabled or not
 // <id> dmac_evie_5
 #ifndef CONF_DMAC_EVIE_5
-#define CONF_DMAC_EVIE_5 0
+#define CONF_DMAC_EVIE_5 1
 #endif
 
 // <o> Event Input Action
@@ -1373,7 +1373,7 @@
 // <i> Defines the event input action
 // <id> dmac_evact_5
 #ifndef CONF_DMAC_EVACT_5
-#define CONF_DMAC_EVACT_5 0
+#define CONF_DMAC_EVACT_5 5
 #endif
 
 // <o> Address Increment Step Size
@@ -1404,14 +1404,14 @@
 // <i> Indicates whether the source address incrementation is enabled or not
 // <id> dmac_srcinc_5
 #ifndef CONF_DMAC_SRCINC_5
-#define CONF_DMAC_SRCINC_5 0
+#define CONF_DMAC_SRCINC_5 1
 #endif
 
 // <q> Destination Address Increment
 // <i> Indicates whether the destination address incrementation is enabled or not
 // <id> dmac_dstinc_5
 #ifndef CONF_DMAC_DSTINC_5
-#define CONF_DMAC_DSTINC_5 1
+#define CONF_DMAC_DSTINC_5 0
 #endif
 
 // <o> Beat Size
@@ -1421,7 +1421,7 @@
 // <i> Defines the size of one beat
 // <id> dmac_beatsize_5
 #ifndef CONF_DMAC_BEATSIZE_5
-#define CONF_DMAC_BEATSIZE_5 1
+#define CONF_DMAC_BEATSIZE_5 2
 #endif
 
 // <o> Block Action
@@ -1432,7 +1432,7 @@
 // <i> Defines the the DMAC should take after a block transfer has completed
 // <id> dmac_blockact_5
 #ifndef CONF_DMAC_BLOCKACT_5
-#define CONF_DMAC_BLOCKACT_5 1
+#define CONF_DMAC_BLOCKACT_5 2
 #endif
 
 // <o> Event Output Selection
@@ -1449,7 +1449,7 @@
 // <e> Channel 6 settings
 // <id> dmac_channel_6_settings
 #ifndef CONF_DMAC_CHANNEL_6_SETTINGS
-#define CONF_DMAC_CHANNEL_6_SETTINGS 0
+#define CONF_DMAC_CHANNEL_6_SETTINGS 1
 #endif
 
 // <q> Channel Run in Standby
@@ -1558,7 +1558,7 @@
 // <i> Defines the peripheral trigger which is source of the transfer
 // <id> dmac_trifsrc_6
 #ifndef CONF_DMAC_TRIGSRC_6
-#define CONF_DMAC_TRIGSRC_6 69
+#define CONF_DMAC_TRIGSRC_6 15
 #endif
 
 // <o> Channel Arbitration Level
@@ -1782,7 +1782,7 @@
 // <i> Defines the peripheral trigger which is source of the transfer
 // <id> dmac_trifsrc_7
 #ifndef CONF_DMAC_TRIGSRC_7
-#define CONF_DMAC_TRIGSRC_7 71
+#define CONF_DMAC_TRIGSRC_7 7
 #endif
 
 // <o> Channel Arbitration Level
@@ -1897,7 +1897,7 @@
 // <e> Channel 8 settings
 // <id> dmac_channel_8_settings
 #ifndef CONF_DMAC_CHANNEL_8_SETTINGS
-#define CONF_DMAC_CHANNEL_8_SETTINGS 1
+#define CONF_DMAC_CHANNEL_8_SETTINGS 0
 #endif
 
 // <q> Channel Run in Standby
@@ -2031,7 +2031,7 @@
 // <i> Indicates whether channel event reception is enabled or not
 // <id> dmac_evie_8
 #ifndef CONF_DMAC_EVIE_8
-#define CONF_DMAC_EVIE_8 0
+#define CONF_DMAC_EVIE_8 1
 #endif
 
 // <o> Event Input Action
@@ -2045,7 +2045,7 @@
 // <i> Defines the event input action
 // <id> dmac_evact_8
 #ifndef CONF_DMAC_EVACT_8
-#define CONF_DMAC_EVACT_8 0
+#define CONF_DMAC_EVACT_8 5
 #endif
 
 // <o> Address Increment Step Size
@@ -2104,7 +2104,7 @@
 // <i> Defines the the DMAC should take after a block transfer has completed
 // <id> dmac_blockact_8
 #ifndef CONF_DMAC_BLOCKACT_8
-#define CONF_DMAC_BLOCKACT_8 0
+#define CONF_DMAC_BLOCKACT_8 2
 #endif
 
 // <o> Event Output Selection
@@ -2121,7 +2121,7 @@
 // <e> Channel 9 settings
 // <id> dmac_channel_9_settings
 #ifndef CONF_DMAC_CHANNEL_9_SETTINGS
-#define CONF_DMAC_CHANNEL_9_SETTINGS 1
+#define CONF_DMAC_CHANNEL_9_SETTINGS 0
 #endif
 
 // <q> Channel Run in Standby
@@ -2255,7 +2255,7 @@
 // <i> Indicates whether channel event reception is enabled or not
 // <id> dmac_evie_9
 #ifndef CONF_DMAC_EVIE_9
-#define CONF_DMAC_EVIE_9 0
+#define CONF_DMAC_EVIE_9 1
 #endif
 
 // <o> Event Input Action
@@ -2269,7 +2269,7 @@
 // <i> Defines the event input action
 // <id> dmac_evact_9
 #ifndef CONF_DMAC_EVACT_9
-#define CONF_DMAC_EVACT_9 0
+#define CONF_DMAC_EVACT_9 5
 #endif
 
 // <o> Address Increment Step Size
@@ -2328,7 +2328,7 @@
 // <i> Defines the the DMAC should take after a block transfer has completed
 // <id> dmac_blockact_9
 #ifndef CONF_DMAC_BLOCKACT_9
-#define CONF_DMAC_BLOCKACT_9 0
+#define CONF_DMAC_BLOCKACT_9 2
 #endif
 
 // <o> Event Output Selection
@@ -2345,7 +2345,7 @@
 // <e> Channel 10 settings
 // <id> dmac_channel_10_settings
 #ifndef CONF_DMAC_CHANNEL_10_SETTINGS
-#define CONF_DMAC_CHANNEL_10_SETTINGS 1
+#define CONF_DMAC_CHANNEL_10_SETTINGS 0
 #endif
 
 // <q> Channel Run in Standby
@@ -2479,7 +2479,7 @@
 // <i> Indicates whether channel event reception is enabled or not
 // <id> dmac_evie_10
 #ifndef CONF_DMAC_EVIE_10
-#define CONF_DMAC_EVIE_10 0
+#define CONF_DMAC_EVIE_10 1
 #endif
 
 // <o> Event Input Action
@@ -2493,7 +2493,7 @@
 // <i> Defines the event input action
 // <id> dmac_evact_10
 #ifndef CONF_DMAC_EVACT_10
-#define CONF_DMAC_EVACT_10 0
+#define CONF_DMAC_EVACT_10 5
 #endif
 
 // <o> Address Increment Step Size
@@ -2552,7 +2552,7 @@
 // <i> Defines the the DMAC should take after a block transfer has completed
 // <id> dmac_blockact_10
 #ifndef CONF_DMAC_BLOCKACT_10
-#define CONF_DMAC_BLOCKACT_10 0
+#define CONF_DMAC_BLOCKACT_10 2
 #endif
 
 // <o> Event Output Selection

2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_eic_config.h

@@ -182,7 +182,7 @@
 // <i> Indicates whether the external interrupt 2 event output is enabled or not
 // <id> eic_arch_extinteo2
 #ifndef CONF_EIC_EXTINTEO2
-#define CONF_EIC_EXTINTEO2 0
+#define CONF_EIC_EXTINTEO2 1
 #endif
 
 // <y> Input 2 Sense Configuration
@@ -756,7 +756,7 @@
 // <i> Indicates whether the external interrupt 14 filter is enabled or not
 // <id> eic_arch_filten14
 #ifndef CONF_EIC_FILTEN14
-#define CONF_EIC_FILTEN14 0
+#define CONF_EIC_FILTEN14 1
 #endif
 
 // <q> External Interrupt 14 Debounce Enable
@@ -783,14 +783,14 @@
 // <i> This defines input sense trigger
 // <id> eic_arch_sense14
 #ifndef CONF_EIC_SENSE14
-#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_BOTH_Val
+#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_FALL_Val
 #endif
 
 // <q> External Interrupt 14 Asynchronous Edge Detection Mode
 // <i> Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
 // <id> eic_arch_asynch14
 #ifndef CONF_EIC_ASYNCH14
-#define CONF_EIC_ASYNCH14 1
+#define CONF_EIC_ASYNCH14 0
 #endif
 
 // </e>
@@ -805,7 +805,7 @@
 // <i> Indicates whether the external interrupt 15 filter is enabled or not
 // <id> eic_arch_filten15
 #ifndef CONF_EIC_FILTEN15
-#define CONF_EIC_FILTEN15 0
+#define CONF_EIC_FILTEN15 1
 #endif
 
 // <q> External Interrupt 15 Debounce Enable
@@ -832,14 +832,14 @@
 // <i> This defines input sense trigger
 // <id> eic_arch_sense15
 #ifndef CONF_EIC_SENSE15
-#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_BOTH_Val
+#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_FALL_Val
 #endif
 
 // <q> External Interrupt 15 Asynchronous Edge Detection Mode
 // <i> Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
 // <id> eic_arch_asynch15
 #ifndef CONF_EIC_ASYNCH15
-#define CONF_EIC_ASYNCH15 1
+#define CONF_EIC_ASYNCH15 0
 #endif
 
 // </e>

2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_evsys_config.h

@@ -199,7 +199,7 @@
 // <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
 // <id> evsys_edgsel_1
 #ifndef CONF_EDGSEL_1
-#define CONF_EDGSEL_1 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#define CONF_EDGSEL_1 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
 #endif
 
 // <y> Path selection
@@ -333,7 +333,7 @@
 // <0x77=>CCL LUT output 3
 // <id> evsys_evgen_1
 #ifndef CONF_EVGEN_1
-#define CONF_EVGEN_1 116
+#define CONF_EVGEN_1 74
 #endif
 
 // <q> Overrun channel interrupt
@@ -369,7 +369,7 @@
 // <e> Channel 2 settings
 // <id> evsys_channel_setting_2
 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_2
-#define CONF_EVSYS_CHANNEL_SETTINGS_2 1
+#define CONF_EVSYS_CHANNEL_SETTINGS_2 0
 #endif
 
 // <y> Edge detection
@@ -380,7 +380,7 @@
 // <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
 // <id> evsys_edgsel_2
 #ifndef CONF_EDGSEL_2
-#define CONF_EDGSEL_2 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#define CONF_EDGSEL_2 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
 #endif
 
 // <y> Path selection
@@ -514,7 +514,7 @@
 // <0x77=>CCL LUT output 3
 // <id> evsys_evgen_2
 #ifndef CONF_EVGEN_2
-#define CONF_EVGEN_2 118
+#define CONF_EVGEN_2 75
 #endif
 
 // <q> Overrun channel interrupt
@@ -550,7 +550,7 @@
 // <e> Channel 3 settings
 // <id> evsys_channel_setting_3
 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_3
-#define CONF_EVSYS_CHANNEL_SETTINGS_3 1
+#define CONF_EVSYS_CHANNEL_SETTINGS_3 0
 #endif
 
 // <y> Edge detection
@@ -731,7 +731,7 @@
 // <e> Channel 4 settings
 // <id> evsys_channel_setting_4
 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_4
-#define CONF_EVSYS_CHANNEL_SETTINGS_4 1
+#define CONF_EVSYS_CHANNEL_SETTINGS_4 0
 #endif
 
 // <y> Edge detection
@@ -752,7 +752,7 @@
 // <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
 // <id> evsys_path_4
 #ifndef CONF_PATH_4
-#define CONF_PATH_4 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#define CONF_PATH_4 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
 #endif
 
 // <o> Event generator
@@ -876,7 +876,7 @@
 // <0x77=>CCL LUT output 3
 // <id> evsys_evgen_4
 #ifndef CONF_EVGEN_4
-#define CONF_EVGEN_4 35
+#define CONF_EVGEN_4 75
 #endif
 
 // <q> Overrun channel interrupt
@@ -933,7 +933,7 @@
 // <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
 // <id> evsys_path_5
 #ifndef CONF_PATH_5
-#define CONF_PATH_5 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#define CONF_PATH_5 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
 #endif
 
 // <o> Event generator
@@ -1057,7 +1057,7 @@
 // <0x77=>CCL LUT output 3
 // <id> evsys_evgen_5
 #ifndef CONF_EVGEN_5
-#define CONF_EVGEN_5 36
+#define CONF_EVGEN_5 20
 #endif
 
 // <q> Overrun channel interrupt
@@ -1071,7 +1071,7 @@
 // <i> Indicates whether event detected interrupt is enabled or not
 // <id> evsys_evd_5
 #ifndef CONF_EVD_5
-#define CONF_EVD_5 1
+#define CONF_EVD_5 0
 #endif
 
 // <q> On demand clock
@@ -1093,7 +1093,7 @@
 // <e> Channel 6 settings
 // <id> evsys_channel_setting_6
 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_6
-#define CONF_EVSYS_CHANNEL_SETTINGS_6 0
+#define CONF_EVSYS_CHANNEL_SETTINGS_6 1
 #endif
 
 // <y> Edge detection
@@ -1104,7 +1104,7 @@
 // <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
 // <id> evsys_edgsel_6
 #ifndef CONF_EDGSEL_6
-#define CONF_EDGSEL_6 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#define CONF_EDGSEL_6 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
 #endif
 
 // <y> Path selection
@@ -1238,7 +1238,7 @@
 // <0x77=>CCL LUT output 3
 // <id> evsys_evgen_6
 #ifndef CONF_EVGEN_6
-#define CONF_EVGEN_6 0
+#define CONF_EVGEN_6 34
 #endif
 
 // <q> Overrun channel interrupt
@@ -1252,7 +1252,7 @@
 // <i> Indicates whether event detected interrupt is enabled or not
 // <id> evsys_evd_6
 #ifndef CONF_EVD_6
-#define CONF_EVD_6 0
+#define CONF_EVD_6 1
 #endif
 
 // <q> On demand clock
@@ -1274,7 +1274,7 @@
 // <e> Channel 7 settings
 // <id> evsys_channel_setting_7
 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_7
-#define CONF_EVSYS_CHANNEL_SETTINGS_7 0
+#define CONF_EVSYS_CHANNEL_SETTINGS_7 1
 #endif
 
 // <y> Edge detection
@@ -1419,7 +1419,7 @@
 // <0x77=>CCL LUT output 3
 // <id> evsys_evgen_7
 #ifndef CONF_EVGEN_7
-#define CONF_EVGEN_7 0
+#define CONF_EVGEN_7 35
 #endif
 
 // <q> Overrun channel interrupt
@@ -1433,7 +1433,7 @@
 // <i> Indicates whether event detected interrupt is enabled or not
 // <id> evsys_evd_7
 #ifndef CONF_EVD_7
-#define CONF_EVD_7 0
+#define CONF_EVD_7 1
 #endif
 
 // <q> On demand clock
@@ -1455,7 +1455,7 @@
 // <e> Channel 8 settings
 // <id> evsys_channel_setting_8
 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_8
-#define CONF_EVSYS_CHANNEL_SETTINGS_8 0
+#define CONF_EVSYS_CHANNEL_SETTINGS_8 1
 #endif
 
 // <y> Edge detection
@@ -1466,7 +1466,7 @@
 // <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
 // <id> evsys_edgsel_8
 #ifndef CONF_EDGSEL_8
-#define CONF_EDGSEL_8 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#define CONF_EDGSEL_8 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
 #endif
 
 // <y> Path selection
@@ -1600,7 +1600,7 @@
 // <0x77=>CCL LUT output 3
 // <id> evsys_evgen_8
 #ifndef CONF_EVGEN_8
-#define CONF_EVGEN_8 0
+#define CONF_EVGEN_8 36
 #endif
 
 // <q> Overrun channel interrupt
@@ -1614,7 +1614,7 @@
 // <i> Indicates whether event detected interrupt is enabled or not
 // <id> evsys_evd_8
 #ifndef CONF_EVD_8
-#define CONF_EVD_8 0
+#define CONF_EVD_8 1
 #endif
 
 // <q> On demand clock
@@ -1998,7 +1998,7 @@
 // <e> Channel 11 settings
 // <id> evsys_channel_setting_11
 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_11
-#define CONF_EVSYS_CHANNEL_SETTINGS_11 0
+#define CONF_EVSYS_CHANNEL_SETTINGS_11 1
 #endif
 
 // <y> Edge detection
@@ -2009,7 +2009,7 @@
 // <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
 // <id> evsys_edgsel_11
 #ifndef CONF_EDGSEL_11
-#define CONF_EDGSEL_11 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#define CONF_EDGSEL_11 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
 #endif
 
 // <y> Path selection
@@ -2019,7 +2019,7 @@
 // <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
 // <id> evsys_path_11
 #ifndef CONF_PATH_11
-#define CONF_PATH_11 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#define CONF_PATH_11 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
 #endif
 
 // <o> Event generator
@@ -2143,7 +2143,7 @@
 // <0x77=>CCL LUT output 3
 // <id> evsys_evgen_11
 #ifndef CONF_EVGEN_11
-#define CONF_EVGEN_11 0
+#define CONF_EVGEN_11 116
 #endif
 
 // <q> Overrun channel interrupt
@@ -2179,7 +2179,7 @@
 // <e> Channel 12 settings
 // <id> evsys_channel_setting_12
 #ifndef CONF_EVSYS_CHANNEL_SETTINGS_12
-#define CONF_EVSYS_CHANNEL_SETTINGS_12 0
+#define CONF_EVSYS_CHANNEL_SETTINGS_12 1
 #endif
 
 // <y> Edge detection
@@ -2190,7 +2190,7 @@
 // <EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val"> Event is detected on the rising and falling edge of the signal from event generator
 // <id> evsys_edgsel_12
 #ifndef CONF_EDGSEL_12
-#define CONF_EDGSEL_12 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val
+#define CONF_EDGSEL_12 EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
 #endif
 
 // <y> Path selection
@@ -2200,7 +2200,7 @@
 // <EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val"> Asynchronous path
 // <id> evsys_path_12
 #ifndef CONF_PATH_12
-#define CONF_PATH_12 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
+#define CONF_PATH_12 EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val
 #endif
 
 // <o> Event generator
@@ -2324,7 +2324,7 @@
 // <0x77=>CCL LUT output 3
 // <id> evsys_evgen_12
 #ifndef CONF_EVGEN_12
-#define CONF_EVGEN_12 0
+#define CONF_EVGEN_12 118
 #endif
 
 // <q> Overrun channel interrupt
@@ -5880,7 +5880,7 @@
 // <id> evsys_channel_1
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_1
-#define CONF_CHANNEL_1 4
+#define CONF_CHANNEL_1 2
 #endif
 
 // <o> Channel selection for PORT event 1
@@ -5920,7 +5920,7 @@
 // <id> evsys_channel_2
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_2
-#define CONF_CHANNEL_2 5
+#define CONF_CHANNEL_2 7
 #endif
 
 // <o> Channel selection for PORT event 2
@@ -5960,7 +5960,7 @@
 // <id> evsys_channel_3
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_3
-#define CONF_CHANNEL_3 0
+#define CONF_CHANNEL_3 6
 #endif
 
 // <o> Channel selection for PORT event 3
@@ -6000,7 +6000,7 @@
 // <id> evsys_channel_4
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_4
-#define CONF_CHANNEL_4 0
+#define CONF_CHANNEL_4 9
 #endif
 //</h>
 
@@ -6202,7 +6202,7 @@
 // <id> evsys_channel_9
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_9
-#define CONF_CHANNEL_9 0
+#define CONF_CHANNEL_9 1
 #endif
 
 // <o> Channel selection for DMAC channel 5
@@ -6242,7 +6242,7 @@
 // <id> evsys_channel_10
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_10
-#define CONF_CHANNEL_10 0
+#define CONF_CHANNEL_10 6
 #endif
 
 // <o> Channel selection for DMAC channel 6
@@ -6282,7 +6282,7 @@
 // <id> evsys_channel_11
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_11
-#define CONF_CHANNEL_11 0
+#define CONF_CHANNEL_11 5
 #endif
 
 // <o> Channel selection for DMAC channel 7
@@ -6322,7 +6322,7 @@
 // <id> evsys_channel_12
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_12
-#define CONF_CHANNEL_12 1
+#define CONF_CHANNEL_12 3
 #endif
 //</h>
 
@@ -7544,7 +7544,7 @@
 // <id> evsys_channel_46
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_46
-#define CONF_CHANNEL_46 2
+#define CONF_CHANNEL_46 12
 #endif
 
 // <o> Channel selection for TC3 event
@@ -7624,7 +7624,7 @@
 // <id> evsys_channel_48
 // <i> Indicates which channel is chosen for user
 #ifndef CONF_CHANNEL_48
-#define CONF_CHANNEL_48 3
+#define CONF_CHANNEL_48 13
 #endif
 
 // <o> Channel selection for TC5 event

2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_oscctrl_config.h

@@ -568,7 +568,7 @@
 // <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
 // <id> fdpll1_ldr
 #ifndef CONF_FDPLL1_LDR
-#define CONF_FDPLL1_LDR 0x3b
+#define CONF_FDPLL1_LDR 0x31
 #endif
 
 // <o> Clock Divider <0x0-0x7FF>

2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_port_config.h

@@ -137,7 +137,7 @@
 // <e> PORT Input Event 2 configuration
 // <id> enable_port_input_event_2
 #ifndef CONF_PORT_EVCTRL_PORT_2
-#define CONF_PORT_EVCTRL_PORT_2 0
+#define CONF_PORT_EVCTRL_PORT_2 1
 #endif
 
 // <h> PORT Input Event 2 configuration on PORT A
@@ -146,14 +146,14 @@
 // <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
 // <id> porta_input_event_enable_2
 #ifndef CONF_PORTA_EVCTRL_PORTEI_2
-#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
+#define CONF_PORTA_EVCTRL_PORTEI_2 0x1
 #endif
 
 // <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
 // <i> These bits define the I/O pin from port A on which the event action will be performed
 // <id> porta_event_pin_identifier_2
 #ifndef CONF_PORTA_EVCTRL_PID_2
-#define CONF_PORTA_EVCTRL_PID_2 0x0
+#define CONF_PORTA_EVCTRL_PID_2 0xe
 #endif
 
 // <o> PORTA Event 2 Action
@@ -164,7 +164,7 @@
 // <i> These bits define the event action the PORT A will perform on event input 2
 // <id> porta_event_action_2
 #ifndef CONF_PORTA_EVCTRL_EVACT_2
-#define CONF_PORTA_EVCTRL_EVACT_2 0
+#define CONF_PORTA_EVCTRL_EVACT_2 2
 #endif
 
 // </h>
@@ -192,7 +192,7 @@
 // <i> These bits define the event action the PORT B will perform on event input 2
 // <id> portb_event_action_2
 #ifndef CONF_PORTB_EVCTRL_EVACT_2
-#define CONF_PORTB_EVCTRL_EVACT_2 0
+#define CONF_PORTB_EVCTRL_EVACT_2 2
 #endif
 
 // </h>
@@ -202,7 +202,7 @@
 // <e> PORT Input Event 3 configuration
 // <id> enable_port_input_event_3
 #ifndef CONF_PORT_EVCTRL_PORT_3
-#define CONF_PORT_EVCTRL_PORT_3 0
+#define CONF_PORT_EVCTRL_PORT_3 1
 #endif
 
 // <h> PORT Input Event 3 configuration on PORT A
@@ -211,14 +211,14 @@
 // <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
 // <id> porta_input_event_enable_3
 #ifndef CONF_PORTA_EVCTRL_PORTEI_3
-#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
+#define CONF_PORTA_EVCTRL_PORTEI_3 0x1
 #endif
 
 // <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
 // <i> These bits define the I/O pin from port A on which the event action will be performed
 // <id> porta_event_pin_identifier_3
 #ifndef CONF_PORTA_EVCTRL_PID_3
-#define CONF_PORTA_EVCTRL_PID_3 0x0
+#define CONF_PORTA_EVCTRL_PID_3 0xe
 #endif
 
 // <o> PORTA Event 3 Action
@@ -229,7 +229,7 @@
 // <i> These bits define the event action the PORT A will perform on event input 3
 // <id> porta_event_action_3
 #ifndef CONF_PORTA_EVCTRL_EVACT_3
-#define CONF_PORTA_EVCTRL_EVACT_3 0
+#define CONF_PORTA_EVCTRL_EVACT_3 1
 #endif
 
 // </h>
@@ -257,7 +257,7 @@
 // <i> These bits define the event action the PORT B will perform on event input 3
 // <id> portb_event_action_3
 #ifndef CONF_PORTB_EVCTRL_EVACT_3
-#define CONF_PORTB_EVCTRL_EVACT_3 0
+#define CONF_PORTB_EVCTRL_EVACT_3 1
 #endif
 
 // </h>

2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h

@@ -15,7 +15,7 @@
 //<i> This defines DMA channel to be used
 //<id> spi_master_dma_tx_channel
 #ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL
-#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 10
+#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 7
 #endif
 
 // <e> SPI RX Channel Enable
@@ -28,7 +28,7 @@
 //<i> This defines DMA channel to be used
 //<id> spi_master_dma_rx_channel
 #ifndef CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL
-#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 1
+#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 0
 #endif
 
 // </e>
@@ -218,7 +218,7 @@
 // <i> The SPI data transfer rate
 // <id> spi_master_baud_rate
 #ifndef CONF_SERCOM_2_SPI_BAUD
-#define CONF_SERCOM_2_SPI_BAUD 4000000
+#define CONF_SERCOM_2_SPI_BAUD 1000000
 #endif
 
 // </h>
@@ -269,7 +269,7 @@
 // <0x1=>On buffer overflow
 // <id> spi_master_arch_ibon
 #ifndef CONF_SERCOM_2_SPI_IBON
-#define CONF_SERCOM_2_SPI_IBON 0x0
+#define CONF_SERCOM_2_SPI_IBON 0x1
 #endif
 
 // <q> Run in stand-by
@@ -377,7 +377,7 @@
 // <i> The SPI data transfer rate
 // <id> spi_master_baud_rate
 #ifndef CONF_SERCOM_5_SPI_BAUD
-#define CONF_SERCOM_5_SPI_BAUD 8000000
+#define CONF_SERCOM_5_SPI_BAUD 1000000
 #endif
 
 // </h>

2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_tc_config.h

@@ -0,0 +1,180 @@
+/* Auto-generated config file hpl_tc_config.h */
+#ifndef HPL_TC_CONFIG_H
+#define HPL_TC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#ifndef CONF_TC0_ENABLE
+#define CONF_TC0_ENABLE 1
+#endif
+
+#include "peripheral_clk_config.h"
+
+// <h> Basic configuration
+
+// <o> Prescaler
+// <0x0=> No division
+// <0x1=> Divide by 2
+// <0x2=> Divide by 4
+// <0x3=> Divide by 8
+// <0x4=> Divide by 16
+// <0x5=> Divide by 64
+// <0x6=> Divide by 256
+// <0x7=> Divide by 1024
+// <i> This defines the prescaler value
+// <id> timer_prescaler
+#ifndef CONF_TC0_PRESCALER
+#define CONF_TC0_PRESCALER 0x3
+#endif
+
+// <o> Length of one timer tick in uS <0-4294967295>
+// <id> timer_tick
+#ifndef CONF_TC0_TIMER_TICK
+#define CONF_TC0_TIMER_TICK 100
+#endif
+// </h>
+
+// <e> Advanced configuration
+// <id> timer_advanced_configuration
+#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE
+#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 1
+#endif
+
+// <y> Prescaler and Counter Synchronization Selection
+// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
+// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
+// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
+// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
+// <id> tc_arch_presync
+#ifndef CONF_TC0_PRESCSYNC
+#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the module will continue to run in standby sleep mode
+// <id> tc_arch_runstdby
+#ifndef CONF_TC0_RUNSTDBY
+#define CONF_TC0_RUNSTDBY 0
+#endif
+
+// <q> Run in debug mode
+// <i> Indicates whether the module will run in debug mode
+// <id> tc_arch_dbgrun
+#ifndef CONF_TC0_DBGRUN
+#define CONF_TC0_DBGRUN 0
+#endif
+
+// <q> Run on demand
+// <i> Run if requested by some other peripheral in the device
+// <id> tc_arch_ondemand
+#ifndef CONF_TC0_ONDEMAND
+#define CONF_TC0_ONDEMAND 0
+#endif
+
+// </e>
+
+// <e> Event control
+// <id> timer_event_control
+#ifndef CONF_TC0_EVENT_CONTROL_ENABLE
+#define CONF_TC0_EVENT_CONTROL_ENABLE 1
+#endif
+
+// <q> Output Event On Match or Capture on Channel 0
+// <i> Enable output of event on timer tick
+// <id> tc_arch_mceo0
+#ifndef CONF_TC0_MCEO0
+#define CONF_TC0_MCEO0 1
+#endif
+
+// <q> Output Event On Match or Capture on Channel 1
+// <i> Enable output of event on timer tick
+// <id> tc_arch_mceo1
+#ifndef CONF_TC0_MCEO1
+#define CONF_TC0_MCEO1 1
+#endif
+
+// <q> Output Event On Timer Tick
+// <i> Enable output of event on timer tick
+// <id> tc_arch_ovfeo
+#ifndef CONF_TC0_OVFEO
+#define CONF_TC0_OVFEO 0
+#endif
+
+// <q> Event Input
+// <i> Enable asynchronous input events
+// <id> tc_arch_tcei
+#ifndef CONF_TC0_TCEI
+#define CONF_TC0_TCEI 0
+#endif
+
+// <q> Inverted Event Input
+// <i> Invert the asynchronous input events
+// <id> tc_arch_tcinv
+#ifndef CONF_TC0_TCINV
+#define CONF_TC0_TCINV 0
+#endif
+
+// <o> Event action
+// <0=> Event action disabled
+// <1=> Start, restart or re-trigger TC on event
+// <2=> Count on event
+// <3=> Start on event
+// <4=> Time stamp capture
+// <5=> Period captured in CC0, pulse width in CC1
+// <6=> Period captured in CC1, pulse width in CC0
+// <7=> Pulse width capture
+// <i> Event which will be performed on an event
+//<id> tc_arch_evact
+#ifndef CONF_TC0_EVACT
+#define CONF_TC0_EVACT 0
+#endif
+// </e>
+
+// Default values which the driver needs in order to work correctly
+
+// Mode set to 32-bit
+#ifndef CONF_TC0_MODE
+#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val
+#endif
+
+// CC 1 register set to 0
+#ifndef CONF_TC0_CC1
+#define CONF_TC0_CC1 0
+#endif
+
+#ifndef CONF_TC0_ALOCK
+#define CONF_TC0_ALOCK 0
+#endif
+
+// Not used in 32-bit mode
+#define CONF_TC0_PER 0
+
+// Calculating correct top value based on requested tick interval.
+#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER)
+
+// Prescaler set to 64
+#if CONF_TC0_PRESCALER > 0x4
+#undef CONF_TC0_PRESCALE
+#define CONF_TC0_PRESCALE 64
+#endif
+
+// Prescaler set to 256
+#if CONF_TC0_PRESCALER > 0x5
+#undef CONF_TC0_PRESCALE
+#define CONF_TC0_PRESCALE 256
+#endif
+
+// Prescaler set to 1024
+#if CONF_TC0_PRESCALER > 0x6
+#undef CONF_TC0_PRESCALE
+#define CONF_TC0_PRESCALE 1024
+#endif
+
+#ifndef CONF_TC0_CC0
+#define CONF_TC0_CC0                                                                                                   \
+	(uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE)))
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_TC_CONFIG_H

2_Motor_Master/Motor_Master/Motor_Master/Config/peripheral_clk_config.h

@@ -41,7 +41,7 @@
  * \brief ADC1's Clock frequency
  */
 #ifndef CONF_GCLK_ADC1_FREQUENCY
-#define CONF_GCLK_ADC1_FREQUENCY 120000000
+#define CONF_GCLK_ADC1_FREQUENCY 100000000
 #endif
 
 // <y> CCL Clock Source
@@ -81,7 +81,7 @@
  * \brief CCL's Clock frequency
  */
 #ifndef CONF_GCLK_CCL_FREQUENCY
-#define CONF_GCLK_CCL_FREQUENCY 120000000
+#define CONF_GCLK_CCL_FREQUENCY 100000000
 #endif
 
 // <y> EIC Clock Source
@@ -121,7 +121,7 @@
  * \brief EIC's Clock frequency
  */
 #ifndef CONF_GCLK_EIC_FREQUENCY
-#define CONF_GCLK_EIC_FREQUENCY 120000000
+#define CONF_GCLK_EIC_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 0 Clock Source
@@ -162,7 +162,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 1 Clock Source
@@ -203,7 +203,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 2 Clock Source
@@ -244,7 +244,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 3 Clock Source
@@ -285,7 +285,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 4 Clock Source
@@ -326,7 +326,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 5 Clock Source
@@ -367,7 +367,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 6 Clock Source
@@ -408,7 +408,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 7 Clock Source
@@ -449,7 +449,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 8 Clock Source
@@ -490,7 +490,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 9 Clock Source
@@ -531,7 +531,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 10 Clock Source
@@ -572,7 +572,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 100000000
 #endif
 
 // <y> EVSYS Channel 11 Clock Source
@@ -613,7 +613,7 @@
  */
 
 #ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
-#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000
+#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 100000000
 #endif
 
 /**
@@ -621,7 +621,7 @@
  * \brief CPU's Clock frequency
  */
 #ifndef CONF_CPU_FREQUENCY
-#define CONF_CPU_FREQUENCY 120000000
+#define CONF_CPU_FREQUENCY 100000000
 #endif
 
 // <y> Core Clock Source
@@ -693,7 +693,7 @@
  * \brief SERCOM1's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 120000000
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 100000000
 #endif
 
 /**
@@ -773,7 +773,7 @@
  * \brief SERCOM2's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 120000000
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000
 #endif
 
 /**
@@ -853,7 +853,7 @@
  * \brief SERCOM5's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 120000000
+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 100000000
 #endif
 
 /**
@@ -893,7 +893,7 @@
 
 // <i> Select the clock source for TC.
 #ifndef CONF_GCLK_TC0_SRC
-#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
 #endif
 
 /**
@@ -901,7 +901,7 @@
  * \brief TC0's Clock frequency
  */
 #ifndef CONF_GCLK_TC0_FREQUENCY
-#define CONF_GCLK_TC0_FREQUENCY 120000000
+#define CONF_GCLK_TC0_FREQUENCY 2000000
 #endif
 
 // <y> TC Clock Source
@@ -941,7 +941,7 @@
  * \brief TC2's Clock frequency
  */
 #ifndef CONF_GCLK_TC2_FREQUENCY
-#define CONF_GCLK_TC2_FREQUENCY 120000000
+#define CONF_GCLK_TC2_FREQUENCY 100000000
 #endif
 
 // <y> TC Clock Source
@@ -981,7 +981,7 @@
  * \brief TC4's Clock frequency
  */
 #ifndef CONF_GCLK_TC4_FREQUENCY
-#define CONF_GCLK_TC4_FREQUENCY 120000000
+#define CONF_GCLK_TC4_FREQUENCY 100000000
 #endif
 
 // <y> TCC Clock Source
@@ -1021,7 +1021,7 @@
  * \brief TCC0's Clock frequency
  */
 #ifndef CONF_GCLK_TCC0_FREQUENCY
-#define CONF_GCLK_TCC0_FREQUENCY 120000000
+#define CONF_GCLK_TCC0_FREQUENCY 100000000
 #endif
 
 // <y> TCC Clock Source
@@ -1061,7 +1061,7 @@
  * \brief TCC1's Clock frequency
  */
 #ifndef CONF_GCLK_TCC1_FREQUENCY
-#define CONF_GCLK_TCC1_FREQUENCY 120000000
+#define CONF_GCLK_TCC1_FREQUENCY 100000000
 #endif
 
 // <<< end of configuration section >>>

2_Motor_Master/Motor_Master/Motor_Master/Debug.xml

@@ -0,0 +1,126 @@
+<ArmGcc>
+  <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+  <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+  <armgcc.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>DEBUG</Value>
+      <Value>ARM_MATH_CM4=1</Value>
+    </ListValues>
+  </armgcc.compiler.symbols.DefSymbols>
+  <armgcc.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+      <Value>../Config</Value>
+      <Value>../</Value>
+      <Value>../examples</Value>
+      <Value>../hal/include</Value>
+      <Value>../hal/utils/include</Value>
+      <Value>../hpl/adc</Value>
+      <Value>../hpl/ccl</Value>
+      <Value>../hpl/cmcc</Value>
+      <Value>../hpl/core</Value>
+      <Value>../hpl/dmac</Value>
+      <Value>../hpl/eic</Value>
+      <Value>../hpl/evsys</Value>
+      <Value>../hpl/gclk</Value>
+      <Value>../hpl/mclk</Value>
+      <Value>../hpl/osc32kctrl</Value>
+      <Value>../hpl/oscctrl</Value>
+      <Value>../hpl/pm</Value>
+      <Value>../hpl/port</Value>
+      <Value>../hpl/qspi</Value>
+      <Value>../hpl/ramecc</Value>
+      <Value>../hpl/sercom</Value>
+      <Value>../hpl/tc</Value>
+      <Value>../hpl/tcc</Value>
+      <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcc.linker.general.UseNewlibNano>True</armgcc.linker.general.UseNewlibNano>
+  <armgcc.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>libarm_cortexM4lf_math.a</Value>
+    </ListValues>
+  </armgcc.linker.libraries.Libraries>
+  <armgcc.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>C:\Users\Nick-XMG\Documents\github\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master\Motor_Master\Motor_Master\cmsis</Value>
+      <Value>C:\Users\ge37vez\Documents\Git Repos\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master\Motor_Master\Motor_Master\cmsis</Value>
+      <Value>%24(ProjectDir)\Device_Startup</Value>
+    </ListValues>
+  </armgcc.linker.libraries.LibrarySearchPaths>
+  <armgcc.linker.optimization.GarbageCollectUnusedSections>True</armgcc.linker.optimization.GarbageCollectUnusedSections>
+  <armgcc.linker.memorysettings.ExternalRAM />
+  <armgcc.linker.miscellaneous.LinkerFlags>-Tsame51j19a_flash.ld -std=gnu99 -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mfp16-format=ieee</armgcc.linker.miscellaneous.LinkerFlags>
+  <armgcc.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+      <Value>../Config</Value>
+      <Value>../</Value>
+      <Value>../examples</Value>
+      <Value>../hal/include</Value>
+      <Value>../hal/utils/include</Value>
+      <Value>../hpl/adc</Value>
+      <Value>../hpl/ccl</Value>
+      <Value>../hpl/cmcc</Value>
+      <Value>../hpl/core</Value>
+      <Value>../hpl/dmac</Value>
+      <Value>../hpl/eic</Value>
+      <Value>../hpl/evsys</Value>
+      <Value>../hpl/gclk</Value>
+      <Value>../hpl/mclk</Value>
+      <Value>../hpl/osc32kctrl</Value>
+      <Value>../hpl/oscctrl</Value>
+      <Value>../hpl/pm</Value>
+      <Value>../hpl/port</Value>
+      <Value>../hpl/qspi</Value>
+      <Value>../hpl/ramecc</Value>
+      <Value>../hpl/sercom</Value>
+      <Value>../hpl/tc</Value>
+      <Value>../hpl/tcc</Value>
+      <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
+    </ListValues>
+  </armgcc.assembler.general.IncludePaths>
+  <armgcc.assembler.debugging.DebugLevel>Default (-g)</armgcc.assembler.debugging.DebugLevel>
+  <armgcc.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+      <Value>../Config</Value>
+      <Value>../</Value>
+      <Value>../examples</Value>
+      <Value>../hal/include</Value>
+      <Value>../hal/utils/include</Value>
+      <Value>../hpl/adc</Value>
+      <Value>../hpl/ccl</Value>
+      <Value>../hpl/cmcc</Value>
+      <Value>../hpl/core</Value>
+      <Value>../hpl/dmac</Value>
+      <Value>../hpl/eic</Value>
+      <Value>../hpl/evsys</Value>
+      <Value>../hpl/gclk</Value>
+      <Value>../hpl/mclk</Value>
+      <Value>../hpl/osc32kctrl</Value>
+      <Value>../hpl/oscctrl</Value>
+      <Value>../hpl/pm</Value>
+      <Value>../hpl/port</Value>
+      <Value>../hpl/qspi</Value>
+      <Value>../hpl/ramecc</Value>
+      <Value>../hpl/sercom</Value>
+      <Value>../hpl/tc</Value>
+      <Value>../hpl/tcc</Value>
+      <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
+    </ListValues>
+  </armgcc.preprocessingassembler.general.IncludePaths>
+  <armgcc.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcc.preprocessingassembler.debugging.DebugLevel>
+</ArmGcc>

2_Motor_Master/Motor_Master/Motor_Master/EtherCAT_SlaveDef.h

@@ -11,8 +11,12 @@
 
 #include "Ethercat_QSPI.h"
 #include "arm_math.h"
+#include "ADS1299.h"
+
+extern volatile uint8_t _ads1299_reg_data[24];
+extern volatile int32_t _ads1299_channel_data[9];
+extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
 
-extern volatile int32_t _channel_data[8];
 
 //Write To Ecat Total Bytes (XX bytes)
 /* Motor 1*/
@@ -194,10 +198,10 @@ static void update_telemetry(void)
 	*M2_Motor_speed				= (int16_t)Motor2.motor_status.calc_rpm;
 	//*M2_Joint_abs_position		= Motor2.motor_status.actualDirection;
 	
-	*EMG_CH1					= _channel_data[0];
+	*EMG_CH1					= _ads1299_channel_data[0];
-	*EMG_CH2					= _channel_data[1];
+	*EMG_CH2					= _ads1299_channel_data[1];
-	*EMG_CH3					= _channel_data[2];
+	*EMG_CH3					= _ads1299_channel_data[2];
-	*EMG_CH4					= _channel_data[3];
+	*EMG_CH4					= _ads1299_channel_data[3];
 	//*EMG_CH1					= 1;
 	//*EMG_CH2					= 2;
 	//*EMG_CH3					= 3;

2_Motor_Master/Motor_Master/Motor_Master/Ethercat_SlaveDef.h

@@ -11,8 +11,12 @@
 
 #include "Ethercat_QSPI.h"
 #include "arm_math.h"
+#include "ADS1299.h"
+
+extern volatile uint8_t _ads1299_reg_data[24];
+extern volatile int32_t _ads1299_channel_data[9];
+extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
 
-extern volatile int32_t _channel_data[8];
 
 //Write To Ecat Total Bytes (XX bytes)
 /* Motor 1*/
@@ -194,10 +198,10 @@ static void update_telemetry(void)
 	*M2_Motor_speed				= (int16_t)Motor2.motor_status.calc_rpm;
 	//*M2_Joint_abs_position		= Motor2.motor_status.actualDirection;
 	
-	*EMG_CH1					= _channel_data[0];
+	*EMG_CH1					= _ads1299_channel_data[0];
-	*EMG_CH2					= _channel_data[1];
+	*EMG_CH2					= _ads1299_channel_data[1];
-	*EMG_CH3					= _channel_data[2];
+	*EMG_CH3					= _ads1299_channel_data[2];
-	*EMG_CH4					= _channel_data[3];
+	*EMG_CH4					= _ads1299_channel_data[3];
 	//*EMG_CH1					= 1;
 	//*EMG_CH2					= 2;
 	//*EMG_CH3					= 3;

2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.componentinfo.xml

@@ -91,7 +91,7 @@
 					<Attribute>template</Attribute>
 					<Category>source</Category>
 					<Condition>C Exe</Condition>
-					<FileContentHash>5/u/VzT6YicSrkF/TEhsaQ==</FileContentHash>
+					<FileContentHash>bVtz6/s2nKLwVTITbJPLlQ==</FileContentHash>
 					<FileVersion></FileVersion>
 					<Name>templates/main.c</Name>
 					<SelectString>Main file (.c)</SelectString>

2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj

@@ -150,7 +150,7 @@
           <AcmeProjectActionInfo Action="File" Source="hri/hri_usb_e51.h" IsConfig="false" Hash="x6M7vYgNCS2oECqykr5+yw" />
           <AcmeProjectActionInfo Action="File" Source="hri/hri_wdt_e51.h" IsConfig="false" Hash="o9Rg/hyuMzwOCphVc7uG1w" />
           <AcmeProjectActionInfo Action="File" Source="main.c" IsConfig="false" Hash="k0AH7j+BrmdFhBPzCCMptA" />
-          <AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="G20g4A90o1iiMw5JKqZlrQ" />
+          <AcmeProjectActionInfo Action="File" Source="driver_init.c" IsConfig="false" Hash="3OxQAqTAa4rYMj/raXEwmA" />
           <AcmeProjectActionInfo Action="File" Source="driver_init.h" IsConfig="false" Hash="NyJtBqCuH2RlTy0iltvcfg" />
           <AcmeProjectActionInfo Action="File" Source="atmel_start_pins.h" IsConfig="false" Hash="q332kmNEqTBha3F9F86pCg" />
           <AcmeProjectActionInfo Action="File" Source="examples/driver_examples.h" IsConfig="false" Hash="yuNriNBbj5kyY6X2I3Qu+A" />
@@ -197,7 +197,7 @@
           <AcmeProjectActionInfo Action="File" Source="hpl/qspi/hpl_qspi.c" IsConfig="false" Hash="woXbbCFkSWus6J14PHJlHw" />
           <AcmeProjectActionInfo Action="File" Source="hpl/ramecc/hpl_ramecc.c" IsConfig="false" Hash="pMdmwVWBg16VG8HOwA3DPw" />
           <AcmeProjectActionInfo Action="File" Source="hpl/sercom/hpl_sercom.c" IsConfig="false" Hash="hcMq5dgdlyb9xXr1YOQnMQ" />
-          <AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.c" IsConfig="false" Hash="rgTvxuBnL9g4Ehy4toqpuA" />
+          <AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.c" IsConfig="false" Hash="kz+bp4op9YRjnBul3eSRqA" />
           <AcmeProjectActionInfo Action="File" Source="hpl/tc/tc_lite.h" IsConfig="false" Hash="zTBTKMmLh2GsbqmbMsUX8g" />
           <AcmeProjectActionInfo Action="File" Source="hpl/tcc/hpl_tcc.c" IsConfig="false" Hash="DC3UZSTUv1CDjekNxClhVg" />
           <AcmeProjectActionInfo Action="File" Source="hpl/tcc/hpl_tcc.h" IsConfig="false" Hash="rdWkAK12qkOYV59tWwzy6A" />
@@ -206,26 +206,28 @@
           <AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="IJeJ3sDxG9f3mmsLxoMLlA" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="G4WVXUcIlVMxjaDgFB7QRQ" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="c2mFPMtMeiOShLEVxcw7dA" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="S8xJxIaG6pS6BEvDgxKh9w" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="Zre11F0UnVVaJqMRScEOwA" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="razEOr+ddCtzmAhy4QVzhg" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="cB1sDpQYOnu3879R9Q3umQ" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_mclk_config.h" IsConfig="true" Hash="pxBzoQXTG66x4dbzVzxteg" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_osc32kctrl_config.h" IsConfig="true" Hash="HgvzEqDUH4jq/syjj/+G+Q" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Uje5LXAS+nQpGryt9t0fYA" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Xe5v62bijwZLOPLD+rPcrA" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="OHReh3YoteXQnOg0JJMWVg" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="6ehr8XBnb+p6XoRmEyYIGw" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_qspi_config.h" IsConfig="true" Hash="CwZ360eeEYs7T9SYFSvDug" />
-          <AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="0jM1u/XQkwzOqyPduvYuCA" />
+          <AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="tTBTi6avaSGiP8DXcNnKeQ" />
           <AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" />
-          <AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="s/tLl+lpMPQWNUrjuAL0rQ" />
+          <AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="9AMUnzTI9+M2WQoaURqWRA" />
         </AcmeActionInfos>
         <NonsecureFilesInfo />
       </AcmeProjectConfig>
     </AcmeProjectConfig>
-    <avrtool>com.atmel.avrdbg.tool.atmelice</avrtool>
+    <avrtool>
+    </avrtool>
     <avrtoolserialnumber>J42700013287</avrtoolserialnumber>
     <avrdeviceexpectedsignature>0x61810302</avrdeviceexpectedsignature>
-    <avrtoolinterface>SWD</avrtoolinterface>
+    <avrtoolinterface>
+    </avrtoolinterface>
     <com_atmel_avrdbg_tool_atmelice>
       <ToolOptions>
         <InterfaceProperties>
@@ -254,7 +256,6 @@
   </armgcc.compiler.symbols.DefSymbols>
   <armgcc.compiler.directories.IncludePaths>
     <ListValues>
-      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
       <Value>../Config</Value>
       <Value>../</Value>
       <Value>../examples</Value>
@@ -279,6 +280,7 @@
       <Value>../hpl/tc</Value>
       <Value>../hpl/tcc</Value>
       <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
       <Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
     </ListValues>
   </armgcc.compiler.directories.IncludePaths>
@@ -304,7 +306,6 @@
   <armgcc.linker.miscellaneous.LinkerFlags>-Tsame51j19a_flash.ld</armgcc.linker.miscellaneous.LinkerFlags>
   <armgcc.assembler.general.IncludePaths>
     <ListValues>
-      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
       <Value>../Config</Value>
       <Value>../</Value>
       <Value>../examples</Value>
@@ -329,12 +330,12 @@
       <Value>../hpl/tc</Value>
       <Value>../hpl/tcc</Value>
       <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
       <Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
     </ListValues>
   </armgcc.assembler.general.IncludePaths>
   <armgcc.preprocessingassembler.general.IncludePaths>
     <ListValues>
-      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
       <Value>../Config</Value>
       <Value>../</Value>
       <Value>../examples</Value>
@@ -359,6 +360,7 @@
       <Value>../hpl/tc</Value>
       <Value>../hpl/tcc</Value>
       <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
       <Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
     </ListValues>
   </armgcc.preprocessingassembler.general.IncludePaths>
@@ -381,7 +383,6 @@
   </armgcc.compiler.symbols.DefSymbols>
   <armgcc.compiler.directories.IncludePaths>
     <ListValues>
-      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
       <Value>../Config</Value>
       <Value>../</Value>
       <Value>../examples</Value>
@@ -406,6 +407,7 @@
       <Value>../hpl/tc</Value>
       <Value>../hpl/tcc</Value>
       <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
       <Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
     </ListValues>
   </armgcc.compiler.directories.IncludePaths>
@@ -432,7 +434,6 @@
   <armgcc.linker.miscellaneous.LinkerFlags>-Tsame51j19a_flash.ld -std=gnu99 -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mfp16-format=ieee</armgcc.linker.miscellaneous.LinkerFlags>
   <armgcc.assembler.general.IncludePaths>
     <ListValues>
-      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
       <Value>../Config</Value>
       <Value>../</Value>
       <Value>../examples</Value>
@@ -457,13 +458,13 @@
       <Value>../hpl/tc</Value>
       <Value>../hpl/tcc</Value>
       <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
       <Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
     </ListValues>
   </armgcc.assembler.general.IncludePaths>
   <armgcc.assembler.debugging.DebugLevel>Default (-g)</armgcc.assembler.debugging.DebugLevel>
   <armgcc.preprocessingassembler.general.IncludePaths>
     <ListValues>
-      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
       <Value>../Config</Value>
       <Value>../</Value>
       <Value>../examples</Value>
@@ -488,6 +489,7 @@
       <Value>../hpl/tc</Value>
       <Value>../hpl/tcc</Value>
       <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
       <Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
     </ListValues>
   </armgcc.preprocessingassembler.general.IncludePaths>

2_Motor_Master/Motor_Master/Motor_Master/Release.xml

@@ -0,0 +1,122 @@
+<ArmGcc>
+  <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+  <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+  <armgcc.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>NDEBUG</Value>
+    </ListValues>
+  </armgcc.compiler.symbols.DefSymbols>
+  <armgcc.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+      <Value>../Config</Value>
+      <Value>../</Value>
+      <Value>../examples</Value>
+      <Value>../hal/include</Value>
+      <Value>../hal/utils/include</Value>
+      <Value>../hpl/adc</Value>
+      <Value>../hpl/ccl</Value>
+      <Value>../hpl/cmcc</Value>
+      <Value>../hpl/core</Value>
+      <Value>../hpl/dmac</Value>
+      <Value>../hpl/eic</Value>
+      <Value>../hpl/evsys</Value>
+      <Value>../hpl/gclk</Value>
+      <Value>../hpl/mclk</Value>
+      <Value>../hpl/osc32kctrl</Value>
+      <Value>../hpl/oscctrl</Value>
+      <Value>../hpl/pm</Value>
+      <Value>../hpl/port</Value>
+      <Value>../hpl/qspi</Value>
+      <Value>../hpl/ramecc</Value>
+      <Value>../hpl/sercom</Value>
+      <Value>../hpl/tc</Value>
+      <Value>../hpl/tcc</Value>
+      <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=softfp -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcc.linker.general.UseNewlibNano>True</armgcc.linker.general.UseNewlibNano>
+  <armgcc.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>libarm_cortexM4lf_math.a</Value>
+    </ListValues>
+  </armgcc.linker.libraries.Libraries>
+  <armgcc.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>C:\Users\Nick-XMG\Documents\github\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master\Motor_Master\Motor_Master\cmsis</Value>
+      <Value>C:\Users\ge37vez\Documents\Git Repos\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master\Motor_Master\Motor_Master\cmsis</Value>
+      <Value>%24(ProjectDir)\Device_Startup</Value>
+    </ListValues>
+  </armgcc.linker.libraries.LibrarySearchPaths>
+  <armgcc.linker.optimization.GarbageCollectUnusedSections>True</armgcc.linker.optimization.GarbageCollectUnusedSections>
+  <armgcc.linker.miscellaneous.LinkerFlags>-Tsame51j19a_flash.ld</armgcc.linker.miscellaneous.LinkerFlags>
+  <armgcc.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+      <Value>../Config</Value>
+      <Value>../</Value>
+      <Value>../examples</Value>
+      <Value>../hal/include</Value>
+      <Value>../hal/utils/include</Value>
+      <Value>../hpl/adc</Value>
+      <Value>../hpl/ccl</Value>
+      <Value>../hpl/cmcc</Value>
+      <Value>../hpl/core</Value>
+      <Value>../hpl/dmac</Value>
+      <Value>../hpl/eic</Value>
+      <Value>../hpl/evsys</Value>
+      <Value>../hpl/gclk</Value>
+      <Value>../hpl/mclk</Value>
+      <Value>../hpl/osc32kctrl</Value>
+      <Value>../hpl/oscctrl</Value>
+      <Value>../hpl/pm</Value>
+      <Value>../hpl/port</Value>
+      <Value>../hpl/qspi</Value>
+      <Value>../hpl/ramecc</Value>
+      <Value>../hpl/sercom</Value>
+      <Value>../hpl/tc</Value>
+      <Value>../hpl/tcc</Value>
+      <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
+    </ListValues>
+  </armgcc.assembler.general.IncludePaths>
+  <armgcc.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+      <Value>../Config</Value>
+      <Value>../</Value>
+      <Value>../examples</Value>
+      <Value>../hal/include</Value>
+      <Value>../hal/utils/include</Value>
+      <Value>../hpl/adc</Value>
+      <Value>../hpl/ccl</Value>
+      <Value>../hpl/cmcc</Value>
+      <Value>../hpl/core</Value>
+      <Value>../hpl/dmac</Value>
+      <Value>../hpl/eic</Value>
+      <Value>../hpl/evsys</Value>
+      <Value>../hpl/gclk</Value>
+      <Value>../hpl/mclk</Value>
+      <Value>../hpl/osc32kctrl</Value>
+      <Value>../hpl/oscctrl</Value>
+      <Value>../hpl/pm</Value>
+      <Value>../hpl/port</Value>
+      <Value>../hpl/qspi</Value>
+      <Value>../hpl/ramecc</Value>
+      <Value>../hpl/sercom</Value>
+      <Value>../hpl/tc</Value>
+      <Value>../hpl/tcc</Value>
+      <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\atmel\SAME51_DFP\1.1.139\include</Value>
+    </ListValues>
+  </armgcc.preprocessingassembler.general.IncludePaths>
+</ArmGcc>

2_Motor_Master/Motor_Master/Motor_Master/bldc.c

@@ -49,7 +49,8 @@ void motor_StateMachine(BLDCMotor_t* const motor)
 		case MOTOR_VI_CTRL_STATE:	
 			switch (motor->regulation_loop_count) {
 				case 0: /* PWM FREQ / 25 - 1kHz */	
-				case 5: case 10: case 15: case 20:/* PWM FREQ / 5 - 5kHz */
+				//case 5: case 10: case 15: case 20:/* PWM FREQ / 5 - 5kHz */
+				case 5: case 15: /* PWM FREQ / 5 - 5kHz */
 					calculate_motor_speed(motor);
 					BLDC_runSpeedCntl(motor, (float32_t)motor->motor_status.calc_rpm, (float32_t)motor->motor_setpoints.desired_speed);	
 				default: /* PWM FREQ - 25kHz */
@@ -93,6 +94,7 @@ void BldcInitStruct(BLDCMotor_t* const motor, BLDCMotor_param_t * const motor_pa
 	//  Assign Motor Parameters:
 	// ----------------------------------------------------------------------
 	motor->motor_param						 = motor_param;
+							
 	
 	// ----------------------------------------------------------------------
 	// Initialize State Machine:
@@ -218,9 +220,9 @@ void exec_commutation(BLDCMotor_t* const motor)
 		
 	if (currentHall == INVALID_HALL_7)
 	{
-		motor->motor_state.currentstate == MOTOR_FAULT;
+		///motor->motor_state.currentstate == MOTOR_FAULT;
-		motor->motor_state.fault == MOTOR_HALLSENSORINVALID;
+		//motor->motor_state.fault == MOTOR_HALLSENSORINVALID;
-		return;
+		//return;
 	}
 																		   
 	// ----------------------------------------------------------------------

2_Motor_Master/Motor_Master/Motor_Master/configuration.h

@@ -16,25 +16,8 @@
 #include "bldc.h"
 #include "interrupts.h"
 #include "hpl_sercom_config.h"
-
+#include "ADS1299.h"
-// ----------------------------------------------------------------------
+#include "hpl_spi_m_dma.h"
-// ADC DMA Initialization
-// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
-// ----------------------------------------------------------------------
-
-#define CONF_ADC_0_ADC_RES_READY_CHANNEL 4U
-#define CONF_ADC_1_ADC_RES_READY_CHANNEL 5U
-#define CONF_ADC_0_SEQUENCER_CHANNEL	 6U
-#define CONF_ADC_1_SEQUENCER_CHANNEL	 7U
-
-const uint32_t adc0_seq_regs[4]	= {0};
-const uint32_t adc1_seq_regs[4]	= {0x0089, 0x0088, 0x0087, 0x0086}; /* Differential */
-//const uint32_t adc1_seq_regs[4]	= {0x1807, 0x1806, 0x1809, 0x1808}; /* Single Ended */
-volatile int16_t adc0_res[4]	= {0};
-volatile int16_t adc1_res[4]	= {0};
-
-struct _dma_resource *adc_sram_dma_resource;
-struct _dma_resource *adc_dmac_sequence_resource;
 
 // ----------------------------------------------------------------------
 // PWM Timer Initialization
@@ -89,6 +72,24 @@ static void configure_tcc_pwm(void)
 
 }
 
+// ----------------------------------------------------------------------
+// ADC DMA Initialization
+// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
+// ----------------------------------------------------------------------
+
+//#define CONF_ADC_0_ADC_RES_READY_CHANNEL 4U
+#define CONF_ADC_1_ADC_RES_READY_CHANNEL 3U
+//#define CONF_ADC_0_SEQUENCER_CHANNEL	 6U
+#define CONF_ADC_1_SEQUENCER_CHANNEL	 4U
+
+const uint32_t adc0_seq_regs[4]	= {0};
+const uint32_t adc1_seq_regs[4]	= {0x0089, 0x0088, 0x0087, 0x0086}; /* Differential */
+//const uint32_t adc1_seq_regs[4]	= {0x1807, 0x1806, 0x1809, 0x1808}; /* Single Ended */
+volatile int16_t adc0_res[4]	= {0};
+volatile int16_t adc1_res[4]	= {0};
+
+struct _dma_resource *adc_sram_dma_resource;
+struct _dma_resource *adc_dmac_sequence_resource;
 
 
 
@@ -147,8 +148,8 @@ static void boardToBoardTransferInit(void)
 	spi_m_dma_get_io_descriptor(&SPI_1_MSIF, &io);
 	//spi_m_dma_register_callback(&SPI_1_MSIF, SPI_M_DMA_CB_RX_DONE, b2bTransferComplete_cb);
 	//SERCOM4->SPI.CTRLC.bit.DATA32B = true;
-	SERCOM1->SPI.LENGTH.bit.LENEN = true;
+	//SERCOM1->SPI.LENGTH.bit.LENEN = true;
-	SERCOM1->SPI.LENGTH.bit.LEN = 64;
+	//SERCOM1->SPI.LENGTH.bit.LEN = 64;
 	
 	SERCOM1->SPI.CTRLC.bit.ICSPACE = 4;
 	SERCOM1->SPI.CTRLC.bit.DATA32B= true;
@@ -164,14 +165,18 @@ static void spi_master_init_dma_descriptors()
 	_dma_set_data_amount(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, MASTER_BUFFER_SIZE_LONG);
 	_dma_set_next_descriptor(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL);
 	
+	
 	_dma_set_source_address(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, &QSPI_rx_buffer[16]);
 	_dma_set_destination_address(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL,
 								(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF.dev.prvt))->DATA.reg));
 	_dma_set_data_amount(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, MASTER_BUFFER_SIZE_LONG);
+	_dma_set_next_descriptor(CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL, CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL);
 	
 	
 	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL]);
 	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL]);
+	
+	
 	/* callback */
 	//struct _dma_resource *resource_rx, *resource_tx;
 	//_dma_get_channel_resource(&resource_rx, CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL);
@@ -184,6 +189,63 @@ static void spi_master_init_dma_descriptors()
 	
 }
 
+// ----------------------------------------------------------------------
+// SPI DMA communication ADS1299
+// ----------------------------------------------------------------------
+//
+
+#define CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL	2U
+#define CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL	5U
+
+
+
+/*  219 Bites total 
+* Number format is 24 bit
+* 7 (uint_32) - 24 bits
+*/
+extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
+//
+static void spi_ads1299_init_dma_descriptors()
+{
+	_dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL,
+						   (uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg));
+	_dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL,  &_ads1299_channel_data[0]);
+	_dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, ADS_BUFFER_SIZE);
+	_dma_set_next_descriptor(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL);
+	
+	
+	_dma_set_source_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, &ads1299_buffer[0]);
+	_dma_set_destination_address(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL,
+							(uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg));
+	_dma_set_data_amount(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, ADS_BUFFER_SIZE);
+	_dma_set_next_descriptor(CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL, CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL);
+	
+	
+	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL]);
+	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL]);
+	
+	
+	/* callback */
+	struct _dma_resource *resource_rx, *resource_tx;
+	_dma_get_channel_resource(&resource_rx, CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL);
+	_dma_get_channel_resource(&resource_tx, CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL);
+	resource_rx->dma_cb.transfer_done = ADS1299_Transfer_Complete_cb;
+	//resource_rx->dma_cb.error = ADS1299_Transfer_error_cb;
+
+	/* Enable DMA transfer complete interrupt */
+	_dma_set_irq_state(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
+	//_dma_set_irq_state(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, DMA_TRANSFER_ERROR_CB, true);
+	
+
+	
+	
+}
+
+
+// ----------------------------------------------------------------------
+// Overall DMA Init
+// ----------------------------------------------------------------------
+
 /* Peripherals should be configured before interacting with dma
 * CH0 - QSPI_RX - For ECAT DMA Mode - Currently Disabled in ASTART
 * CH1 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin
@@ -193,15 +255,17 @@ static void spi_master_init_dma_descriptors()
 * CH5 - ADC1 - Result Ready
 * CH6 - ADC0 - Sequencer (Unused on master) - Currently Disabled in ASTART
 * CH7 - ADC1 - Sequencer - Triggered by TCC0 overflow event
-* CH8 - SERCOM2_TX(SPI2)
+* CH8 - SERCOM2_TX(SPI2) - Expansion IF (EMG)
-* CH9 - SERCOM5_TX(SPI3)
+* CH9 - SERCOM5_TX(SPI3) - Angle Sensor
-* CH10 - SERCOM1_TX(SPI1)
+* CH10 - SERCOM1_TX(SPI1) - Master-Slave IF
 * CH11 - QSPI_TX - For ECAT DMA Mode - Currently Disabled in ASTART
 */
 static void init_dma(void)
 {
 	spi_master_init_dma_descriptors();
+	spi_ads1299_init_dma_descriptors();
 	adc_init_dma_descriptors();
+	
 }
 
 

2_Motor_Master/Motor_Master/Motor_Master/driver_init.c

@@ -165,6 +165,10 @@ void EVENT_SYSTEM_0_init(void)
 	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_3, CONF_GCLK_EVSYS_CHANNEL_3_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
 	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_4, CONF_GCLK_EVSYS_CHANNEL_4_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
 	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_5, CONF_GCLK_EVSYS_CHANNEL_5_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_6, CONF_GCLK_EVSYS_CHANNEL_6_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_7, CONF_GCLK_EVSYS_CHANNEL_7_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_8, CONF_GCLK_EVSYS_CHANNEL_8_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_11, CONF_GCLK_EVSYS_CHANNEL_11_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
 
 	hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);
 

2_Motor_Master/Motor_Master/Motor_Master/hal/documentation/timer.rst

@@ -0,0 +1,52 @@
+============================
+The Timer driver (bare-bone)
+============================
+
+The Timer driver provides means for delayed and periodical function invocation.
+
+A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has
+been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a
+configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically
+changes execution delays and periods for all tasks in the timers task queue.
+
+A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue
+and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on
+the period set in the task configuration.
+In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to
+reuse the memory of expired task in the callback.
+
+Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available.
+
+Features
+--------
+* Initialization and de-initialization
+* Starting and stopping
+* Timer tasks - periodical invocation of functions
+* Changing and obtaining of the period of a timer
+
+Applications
+------------
+* Delayed and periodical function execution for middle-ware stacks and applications.
+
+Dependencies
+------------
+* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt.
+
+Concurrency
+-----------
+The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during
+the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed
+until the task adding or removing is complete.
+
+The task queue is not protected from the access by interrupts not used by the driver. Due to this
+it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes
+the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver.
+
+Limitations
+-----------
+* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts.
+* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task.
+
+Knows issues and workarounds
+----------------------------
+Not applicable

2_Motor_Master/Motor_Master/Motor_Master/hal/include/hal_timer.h

@@ -0,0 +1,206 @@
+/**
+ * \file
+ *
+ * \brief Timer task functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_TIMER_H_INCLUDED
+#define _HAL_TIMER_H_INCLUDED
+
+#include <utils_list.h>
+#include <hpl_timer.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_timer
+ *
+ * @{
+ */
+
+/**
+ * \brief Timer mode type
+ */
+enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT };
+
+/**
+ * \brief Timer task descriptor
+ *
+ * The timer task descriptor forward declaration.
+ */
+struct timer_task;
+
+/**
+ * \brief Timer task callback function type
+ */
+typedef void (*timer_cb_t)(const struct timer_task *const timer_task);
+
+/**
+ * \brief Timer task structure
+ */
+struct timer_task {
+	struct list_element elem;       /*! List element. */
+	uint32_t            time_label; /*! Absolute timer start time. */
+
+	uint32_t             interval; /*! Number of timer ticks before calling the task. */
+	timer_cb_t           cb;       /*! Function pointer to the task. */
+	enum timer_task_mode mode;     /*! Task mode: one shot or repeat. */
+};
+
+/**
+ * \brief Timer structure
+ */
+struct timer_descriptor {
+	struct _timer_device   device;
+	uint32_t               time;
+	struct list_descriptor tasks; /*! Timer tasks list. */
+	volatile uint8_t       flags;
+};
+
+/**
+ * \brief Initialize timer
+ *
+ * This function initializes the given timer.
+ * It checks if the given hardware is not initialized and if the given hardware
+ * is permitted to be initialized.
+ *
+ * \param[out] descr A timer descriptor to initialize
+ * \param[in] hw The pointer to the hardware instance
+ * \param[in] func The pointer to a set of function pointers
+ *
+ * \return Initialization status.
+ */
+int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func);
+
+/**
+ * \brief Deinitialize timer
+ *
+ * This function deinitializes the given timer.
+ * It checks if the given hardware is initialized and if the given hardware is
+ * permitted to be deinitialized.
+ *
+ * \param[in] descr A timer descriptor to deinitialize
+ *
+ * \return De-initialization status.
+ */
+int32_t timer_deinit(struct timer_descriptor *const descr);
+
+/**
+ * \brief Start timer
+ *
+ * This function starts the given timer.
+ * It checks if the given hardware is initialized.
+ *
+ * \param[in] descr The timer descriptor of a timer to start
+ *
+ * \return Timer starting status.
+ */
+int32_t timer_start(struct timer_descriptor *const descr);
+
+/**
+ * \brief Stop timer
+ *
+ * This function stops the given timer.
+ * It checks if the given hardware is initialized.
+ *
+ * \param[in] descr The timer descriptor of a timer to stop
+ *
+ * \return Timer stopping status.
+ */
+int32_t timer_stop(struct timer_descriptor *const descr);
+
+/**
+ * \brief Set amount of clock cycles per timer tick
+ *
+ * This function sets the amount of clock cycles per timer tick for the given timer.
+ * It checks if the given hardware is initialized.
+ *
+ * \param[in] descr The timer descriptor of a timer to stop
+ * \param[in] clock_cycles The amount of clock cycles per tick to set
+ *
+ * \return Setting clock cycles amount status.
+ */
+int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles);
+
+/**
+ * \brief Retrieve the amount of clock cycles in a tick
+ *
+ * This function retrieves how many clock cycles there are in a single timer tick.
+ * It checks if the given hardware is initialized.
+ *
+ * \param[in]  descr The timer descriptor of a timer to convert ticks to
+ * clock cycles
+ * \param[out] cycles The amount of clock cycles
+ *
+ * \return The status of clock cycles retrieving.
+ */
+int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles);
+
+/**
+ * \brief Add timer task
+ *
+ * This function adds the given timer task to the given timer.
+ * It checks if the given hardware is initialized.
+ *
+ * \param[in] descr The timer descriptor of a timer to add task to
+ * \param[in] task A task to add
+ *
+ * \return Timer's task adding status.
+ */
+int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task);
+
+/**
+ * \brief Remove timer task
+ *
+ * This function removes the given timer task from the given timer.
+ * It checks if the given hardware is initialized.
+ *
+ * \param[in] descr The timer descriptor of a timer to remove task from
+ * \param[in] task A task to remove
+ *
+ * \return Timer's task removing status.
+ */
+int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t timer_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_TIMER_H_INCLUDED */

2_Motor_Master/Motor_Master/Motor_Master/hal/src/hal_timer.c

@@ -0,0 +1,250 @@
+/**
+ * \file
+ *
+ * \brief Timer functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_timer.h"
+#include <utils_assert.h>
+#include <utils.h>
+#include <hal_atomic.h>
+#include <hpl_irq.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Timer flags
+ */
+#define TIMER_FLAG_QUEUE_IS_TAKEN 1
+#define TIMER_FLAG_INTERRUPT_TRIGERRED 2
+
+static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time);
+static void timer_process_counted(struct _timer_device *device);
+
+/**
+ * \brief Initialize timer
+ */
+int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func)
+{
+	ASSERT(descr && hw);
+	_timer_init(&descr->device, hw);
+	descr->time                           = 0;
+	descr->device.timer_cb.period_expired = timer_process_counted;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinitialize timer
+ */
+int32_t timer_deinit(struct timer_descriptor *const descr)
+{
+	ASSERT(descr);
+	_timer_deinit(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Start timer
+ */
+int32_t timer_start(struct timer_descriptor *const descr)
+{
+	ASSERT(descr);
+	if (_timer_is_started(&descr->device)) {
+		return ERR_DENIED;
+	}
+	_timer_start(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Stop timer
+ */
+int32_t timer_stop(struct timer_descriptor *const descr)
+{
+	ASSERT(descr);
+	if (!_timer_is_started(&descr->device)) {
+		return ERR_DENIED;
+	}
+	_timer_stop(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set amount of clock cycler per timer tick
+ */
+int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles)
+{
+	ASSERT(descr);
+	_timer_set_period(&descr->device, clock_cycles);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Add timer task
+ */
+int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task)
+{
+	ASSERT(descr && task);
+
+	descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN;
+	if (is_list_element(&descr->tasks, task)) {
+		descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN;
+		ASSERT(false);
+		return ERR_ALREADY_INITIALIZED;
+	}
+	task->time_label = descr->time;
+	timer_add_timer_task(&descr->tasks, task, descr->time);
+
+	descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN;
+	if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) {
+		CRITICAL_SECTION_ENTER()
+		descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED;
+		_timer_set_irq(&descr->device);
+		CRITICAL_SECTION_LEAVE()
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Remove timer task
+ */
+int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task)
+{
+	ASSERT(descr && task);
+
+	descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN;
+	if (!is_list_element(&descr->tasks, task)) {
+		descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN;
+		ASSERT(false);
+		return ERR_NOT_FOUND;
+	}
+	list_delete_element(&descr->tasks, task);
+
+	descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN;
+	if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) {
+		CRITICAL_SECTION_ENTER()
+		descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED;
+		_timer_set_irq(&descr->device);
+		CRITICAL_SECTION_LEAVE()
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve the amount of clock cycles in a tick
+ */
+int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles)
+{
+	ASSERT(descr && cycles);
+	*cycles = _timer_get_period(&descr->device);
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t timer_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+/**
+ * \internal Insert a timer task into sorted timer's list
+ *
+ * \param[in] head The pointer to the head of timer task list
+ * \param[in] task The pointer to task to add
+ * \param[in] time Current timer time
+ */
+static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time)
+{
+	struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list);
+
+	if (!head) {
+		list_insert_as_head(list, new_task);
+		return;
+	}
+
+	for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) {
+		uint32_t time_left;
+
+		if (it->time_label <= time) {
+			time_left = it->interval - (time - it->time_label);
+		} else {
+			time_left = it->interval - (0xFFFFFFFF - it->time_label) - time;
+		}
+		if (time_left >= new_task->interval)
+			break;
+		prev = it;
+	}
+
+	if (it == head) {
+		list_insert_as_head(list, new_task);
+	} else {
+		list_insert_after(prev, new_task);
+	}
+}
+
+/**
+ * \internal Process interrupts
+ */
+static void timer_process_counted(struct _timer_device *device)
+{
+	struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device);
+	struct timer_task *      it    = (struct timer_task *)list_get_head(&timer->tasks);
+	uint32_t                 time  = ++timer->time;
+
+	if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) {
+		timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED;
+		return;
+	}
+
+	while (it && ((time - it->time_label) >= it->interval)) {
+		struct timer_task *tmp = it;
+
+		list_remove_head(&timer->tasks);
+		if (TIMER_TASK_REPEAT == tmp->mode) {
+			tmp->time_label = time;
+			timer_add_timer_task(&timer->tasks, tmp, time);
+		}
+		it = (struct timer_task *)list_get_head(&timer->tasks);
+
+		tmp->cb(tmp);
+	}
+}

2_Motor_Master/Motor_Master/Motor_Master/hpl/tc/hpl_tc.c

@@ -0,0 +1,357 @@
+
+/**
+ * \file
+ *
+ * \brief SAM TC
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_pwm.h>
+#include <hpl_tc_config.h>
+#include <hpl_timer.h>
+#include <utils.h>
+#include <utils_assert.h>
+#include <hpl_tc_base.h>
+
+#ifndef CONF_TC0_ENABLE
+#define CONF_TC0_ENABLE 0
+#endif
+#ifndef CONF_TC1_ENABLE
+#define CONF_TC1_ENABLE 0
+#endif
+#ifndef CONF_TC2_ENABLE
+#define CONF_TC2_ENABLE 0
+#endif
+#ifndef CONF_TC3_ENABLE
+#define CONF_TC3_ENABLE 0
+#endif
+#ifndef CONF_TC4_ENABLE
+#define CONF_TC4_ENABLE 0
+#endif
+#ifndef CONF_TC5_ENABLE
+#define CONF_TC5_ENABLE 0
+#endif
+#ifndef CONF_TC6_ENABLE
+#define CONF_TC6_ENABLE 0
+#endif
+#ifndef CONF_TC7_ENABLE
+#define CONF_TC7_ENABLE 0
+#endif
+
+/**
+ * \brief Macro is used to fill usart configuration structure based on its
+ * number
+ *
+ * \param[in] n The number of structures
+ */
+#define TC_CONFIGURATION(n)                                                                                            \
+	{                                                                                                                  \
+		n, TC##n##_IRQn,                                                                                               \
+		    TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC)                              \
+		        | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos)  \
+		        | TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos),             \
+		    (CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos)                    \
+		        | (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos)            \
+		        | (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos),           \
+		    (CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1,      \
+	}
+/**
+ * \brief TC configuration type
+ */
+struct tc_configuration {
+	uint8_t                number;
+	IRQn_Type              irq;
+	hri_tc_ctrla_reg_t     ctrl_a;
+	hri_tc_evctrl_reg_t    event_ctrl;
+	hri_tc_dbgctrl_reg_t   dbg_ctrl;
+	hri_tccount8_per_reg_t per;
+	hri_tccount32_cc_reg_t cc0;
+	hri_tccount32_cc_reg_t cc1;
+};
+
+/**
+ * \brief Array of TC configurations
+ */
+static struct tc_configuration _tcs[] = {
+#if CONF_TC0_ENABLE == 1
+    TC_CONFIGURATION(0),
+#endif
+#if CONF_TC1_ENABLE == 1
+    TC_CONFIGURATION(1),
+#endif
+#if CONF_TC2_ENABLE == 1
+    TC_CONFIGURATION(2),
+#endif
+#if CONF_TC3_ENABLE == 1
+    TC_CONFIGURATION(3),
+#endif
+#if CONF_TC4_ENABLE == 1
+    TC_CONFIGURATION(4),
+#endif
+#if CONF_TC5_ENABLE == 1
+    TC_CONFIGURATION(5),
+#endif
+#if CONF_TC6_ENABLE == 1
+    TC_CONFIGURATION(6),
+#endif
+#if CONF_TC7_ENABLE == 1
+    TC_CONFIGURATION(7),
+#endif
+};
+
+static struct _timer_device *_tc0_dev = NULL;
+
+static struct _pwm_device *_tc2_dev = NULL;
+
+static struct _pwm_device *_tc4_dev = NULL;
+
+static int8_t         get_tc_index(const void *const hw);
+static void           _tc_init_irq_param(const void *const hw, void *dev);
+static inline uint8_t _get_hardware_offset(const void *const hw);
+/**
+ * \brief Initialize TC
+ */
+int32_t _timer_init(struct _timer_device *const device, void *const hw)
+{
+	int8_t i = get_tc_index(hw);
+
+	device->hw = hw;
+	ASSERT(ARRAY_SIZE(_tcs));
+
+	if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) {
+		if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) {
+			hri_tc_clear_CTRLA_ENABLE_bit(hw);
+			hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE);
+		}
+		hri_tc_write_CTRLA_reg(hw, TC_CTRLA_SWRST);
+	}
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
+
+	hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a);
+	hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl);
+	hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl);
+	hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MFRQ);
+
+	if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+		hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0);
+		hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
+
+	} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) {
+		hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0);
+		hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1);
+
+	} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) {
+		hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0);
+		hri_tccount8_write_CC_reg(hw, 1, (uint8_t)_tcs[i].cc1);
+		hri_tccount8_write_PER_reg(hw, _tcs[i].per);
+	}
+	hri_tc_set_INTEN_OVF_bit(hw);
+
+	_tc_init_irq_param(hw, (void *)device);
+	NVIC_DisableIRQ(_tcs[i].irq);
+	NVIC_ClearPendingIRQ(_tcs[i].irq);
+	NVIC_EnableIRQ(_tcs[i].irq);
+
+	return ERR_NONE;
+}
+/**
+ * \brief De-initialize TC
+ */
+void _timer_deinit(struct _timer_device *const device)
+{
+	void *const hw = device->hw;
+	int8_t      i  = get_tc_index(hw);
+	ASSERT(ARRAY_SIZE(_tcs));
+
+	NVIC_DisableIRQ(_tcs[i].irq);
+
+	hri_tc_clear_CTRLA_ENABLE_bit(hw);
+	hri_tc_set_CTRLA_SWRST_bit(hw);
+}
+/**
+ * \brief Start hardware timer
+ */
+void _timer_start(struct _timer_device *const device)
+{
+	hri_tc_set_CTRLA_ENABLE_bit(device->hw);
+}
+/**
+ * \brief Stop hardware timer
+ */
+void _timer_stop(struct _timer_device *const device)
+{
+	hri_tc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+/**
+ * \brief Set timer period
+ */
+void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles)
+{
+	void *const hw = device->hw;
+
+	if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
+		hri_tccount32_write_CC_reg(hw, 0, clock_cycles);
+	} else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
+		hri_tccount16_write_CC_reg(hw, 0, (uint16_t)clock_cycles);
+	} else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
+		hri_tccount8_write_PER_reg(hw, clock_cycles);
+	}
+}
+/**
+ * \brief Retrieve timer period
+ */
+uint32_t _timer_get_period(const struct _timer_device *const device)
+{
+	void *const hw = device->hw;
+
+	if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
+		return hri_tccount32_read_CC_reg(hw, 0);
+	} else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
+		return hri_tccount16_read_CC_reg(hw, 0);
+	} else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
+		return hri_tccount8_read_PER_reg(hw);
+	}
+
+	return 0;
+}
+/**
+ * \brief Check if timer is running
+ */
+bool _timer_is_started(const struct _timer_device *const device)
+{
+	return hri_tc_get_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve timer helper functions
+ */
+struct _timer_hpl_interface *_tc_get_timer(void)
+{
+	return NULL;
+}
+
+/**
+ * \brief Retrieve pwm helper functions
+ */
+struct _pwm_hpl_interface *_tc_get_pwm(void)
+{
+	return NULL;
+}
+/**
+ * \brief Set timer IRQ
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+void _timer_set_irq(struct _timer_device *const device)
+{
+	void *const hw = device->hw;
+	int8_t      i  = get_tc_index(hw);
+	ASSERT(ARRAY_SIZE(_tcs));
+
+	_irq_set(_tcs[i].irq);
+}
+/**
+ * \internal TC interrupt handler for Timer
+ *
+ * \param[in] instance TC instance number
+ */
+static void tc_interrupt_handler(struct _timer_device *device)
+{
+	void *const hw = device->hw;
+
+	if (hri_tc_get_interrupt_OVF_bit(hw)) {
+		hri_tc_clear_interrupt_OVF_bit(hw);
+		device->timer_cb.period_expired(device);
+	}
+}
+
+/**
+ * \brief TC interrupt handler
+ */
+void TC0_Handler(void)
+{
+	tc_interrupt_handler(_tc0_dev);
+}
+
+/**
+ * \internal Retrieve TC index
+ *
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return The index of TC configuration
+ */
+static int8_t get_tc_index(const void *const hw)
+{
+	uint8_t index = _get_hardware_offset(hw);
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_tcs); i++) {
+		if (_tcs[i].number == index) {
+			return i;
+		}
+	}
+
+	ASSERT(false);
+	return -1;
+}
+
+/**
+ * \brief Init irq param with the given tc hardware instance
+ */
+static void _tc_init_irq_param(const void *const hw, void *dev)
+{
+	if (hw == TC0) {
+		_tc0_dev = (struct _timer_device *)dev;
+	}
+	if (hw == TC2) {
+		_tc2_dev = (struct _pwm_device *)dev;
+	}
+	if (hw == TC4) {
+		_tc4_dev = (struct _pwm_device *)dev;
+	}
+}
+
+/**
+ * \internal Retrieve TC hardware index
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+static inline uint8_t _get_hardware_offset(const void *const hw)
+{
+	/* List of available TC modules. */
+	Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
+
+	/* Find index for TC instance. */
+	for (uint32_t i = 0; i < TC_INST_NUM; i++) {
+		if ((uint32_t)hw == (uint32_t)tc_modules[i]) {
+			return i;
+		}
+	}
+	return 0;
+}

2_Motor_Master/Motor_Master/Motor_Master/hpl/tc/hpl_tc_base.h

@@ -0,0 +1,77 @@
+/**
+ * \file
+ *
+ * \brief SAM Timer/Counter
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _HPL_TC_BASE_H_INCLUDED
+#define _HPL_TC_BASE_H_INCLUDED
+
+#include <hpl_timer.h>
+#include <hpl_pwm.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup tc_group TC Hardware Proxy Layer
+ *
+ * \section tc_hpl_rev Revision History
+ * - v0.0.0.1 Initial Commit
+ *
+ *@{
+ */
+
+/**
+ * \name HPL functions
+ */
+//@{
+
+/**
+ * \brief Retrieve timer helper functions
+ *
+ * \return A pointer to set of timer helper functions
+ */
+struct _timer_hpl_interface *_tc_get_timer(void);
+
+/**
+ * \brief Retrieve pwm helper functions
+ *
+ * \return A pointer to set of pwm helper functions
+ */
+struct _pwm_hpl_interface *_tc_get_pwm(void);
+
+//@}
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HPL_TC_BASE_H_INCLUDED */

2_Motor_Master/Motor_Master/Motor_Master/hpl/tc/tc_lite.c

@@ -60,7 +60,7 @@ int8_t TIMER_0_init()
 	                           | 0 << TC_CTRLA_PRESCSYNC_Pos /* Prescaler and Counter Synchronization: 0 */
 	                           | 0 << TC_CTRLA_ONDEMAND_Pos  /* Clock On Demand: disabled */
 	                           | 0 << TC_CTRLA_RUNSTDBY_Pos  /* Run in Standby: disabled */
-	                           | 7 << TC_CTRLA_PRESCALER_Pos /* Setting: 7 */
+	                           | 3 << TC_CTRLA_PRESCALER_Pos /* Setting: 3 */
 	                           | 0x1 << TC_CTRLA_MODE_Pos);  /* Operating Mode: 0x1 */
 
 	hri_tc_write_CTRLB_reg(TC0,
@@ -76,13 +76,13 @@ int8_t TIMER_0_init()
 
 	// hri_tc_write_DBGCTRL_reg(TC0,0); /* Run in debug: 0 */
 
-	hri_tccount8_write_CC_reg(TC0, 0, 0x75); /* Compare/Capture Value: 0x75 */
+	hri_tccount8_write_CC_reg(TC0, 0, 0xa); /* Compare/Capture Value: 0xa */
 
-	hri_tccount8_write_CC_reg(TC0, 1, 0xc4); /* Compare/Capture Value: 0xb4 */
+	hri_tccount8_write_CC_reg(TC0, 1, 0x3c); /* Compare/Capture Value: 0x3c */
 
 	// hri_tccount8_write_COUNT_reg(TC0,0x0); /* Counter Value: 0x0 */
 
-	hri_tc_write_PER_reg(TC0, 0xff); /* Period Value: 0xff */
+	hri_tc_write_PER_reg(TC0, 0xfa); /* Period Value: 0xfa */
 
 	hri_tc_write_EVCTRL_reg(TC0,
 	                        1 << TC_EVCTRL_MCEO0_Pos       /* Match or Capture Channel 0 Event Output Enable: enabled */
@@ -96,7 +96,7 @@ int8_t TIMER_0_init()
 	                       0 << TC_INTENSET_MC0_Pos         /* Match or Capture Channel 0 Interrupt Enable: disabled */
 	                           | 1 << TC_INTENSET_MC1_Pos   /* Match or Capture Channel 1 Interrupt Enable: enabled */
 	                           | 0 << TC_INTENSET_ERR_Pos   /* Error Interrupt Enable: disabled */
-	                           | 0 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: disabled */
+	                           | 1 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: enabled */
 
 	hri_tc_write_CTRLA_ENABLE_bit(TC0, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */
 

2_Motor_Master/Motor_Master/Motor_Master/interrupts.h

@@ -9,6 +9,8 @@
 #ifndef INTERRUPTS_H_
 #define INTERRUPTS_H_
 
+#include "configuration.h"
+#include "ADS1299.h"
 
 /* TC0 - Interrupt Handler 
 * Configured to trigger @ 1ms
@@ -17,6 +19,12 @@ void TC0_Handler( void ){
 	if (TC0->COUNT8.INTFLAG.bit.OVF && TC0->COUNT8.INTENSET.bit.OVF)             
 	{
 		TC0->COUNT8.INTFLAG.bit.OVF = 0x01;
+		if ((ecat_state == wait2)|(ecat_state == wait))
+		{
+			ecat_state= write_fifo;
+			run_ECAT =true;
+		}
+		Motor1.timerflags.motor_telemetry_flag = true;
 	}	
 	if (TC0->COUNT8.INTFLAG.bit.MC0 && TC0->COUNT8.INTENSET.bit.MC0)
 	{
@@ -25,12 +33,8 @@ void TC0_Handler( void ){
 	if (TC0->COUNT8.INTFLAG.bit.MC1 && TC0->COUNT8.INTENSET.bit.MC1)
 	{
 		TC0->COUNT8.INTFLAG.bit.MC1 = 0x01;
-		if ((ecat_state == wait2)|(ecat_state == wait))
+		DMAC->Channel[7].CHCTRLB.bit.CMD = 0x02;
-		{
+		
-			ecat_state= write_fifo;
-			run_ECAT =true;
-		}
-		Motor1.timerflags.motor_telemetry_flag = true;
 	}
 }
 
@@ -65,6 +69,7 @@ static void	b2bTransferComplete_cb(struct _dma_resource *resource)
 	//volatile int x = 0;
 	//PORT->Group[GPIO_PORTB].OUTCLR.reg = (1<<Slave_1->SS_pin);
 	//gpio_set_pin_level(SPI1_CS, true);
+	volatile int x = 0;
 }
 
 
@@ -112,11 +117,15 @@ void TC4_Handler(void)
 static void M1_RESET_BAR(void)
 {
 	volatile int x = 0;
+	Motor1.motor_state.currentstate = MOTOR_FAULT;
+	Motor1.motor_state.fault = MOTOR_DRIVER_OVER_CURRENT;
 }
 
 static void M2_RESET_BAR(void)
 {
 	volatile int x = 0;
+	Motor2.motor_state.currentstate = MOTOR_FAULT;
+	Motor2.motor_state.fault = MOTOR_DRIVER_OVER_CURRENT;
 }
 
 // ----------------------------------------------------------------------
@@ -124,12 +133,24 @@ static void M2_RESET_BAR(void)
 // ----------------------------------------------------------------------
 void ADS1299_dataReadyISR(void)
 {
-	//ADS1299.data_ReadyFlag = true;
+	
+	ADS1299.data_ReadyFlag = true;
 	//int32_t* temp =  ADS1299_UPDATECHANNELDATA();
 	volatile int x = 1;
 }
 
+void ADS1299_Transfer_Complete_cb(void)
+{
+	//PORT->Group[0].OUTSET.reg = (1<<GPIO_PIN(SPI2_SS));
+	volatile int x = 1;
+}
 
+void ADS1299_Transfer_error_cb(void)
+{
+	//SERCOM2->SPI.STATUS.bit.BUFOVF = 1;
+	//PORT->Group[0].OUTSET.reg = (1<<GPIO_PIN(SPI2_SS));
+	volatile int x = 1;
+}
 
 
 #endif /* INTERRUPTS_H_ */

2_Motor_Master/Motor_Master/Motor_Master/main.c

@@ -8,13 +8,15 @@
 #include "EtherCAT_QSPI.h"
 
 //#include "MSIF_master.h"
+
 #include "configuration.h"
+#include "interrupts.h"
 #include "bldc.h"
 #include "bldc_types.h"
 #include "EtherCAT_SlaveDef.h"
-#include "interrupts.h"
 #include "statemachine.h"
 
+
 #include "angle_sensors.h"
 #include "ADS1299.h"
 
@@ -29,8 +31,8 @@ void process_currents()
 	volatile int16_t phase_A_current_raw, phase_B_current_raw;
 	
 	/* Motor 1 */
-	phase_A_current_raw = (adc1_res[0] + Motor1.Voffset_lsb.A);
+	phase_A_current_raw = (adc1_res[0] - Motor1.Voffset_lsb.A);
-	phase_B_current_raw = (adc1_res[1] + Motor1.Voffset_lsb.B)*-1;
+	phase_B_current_raw = (adc1_res[1] - Motor1.Voffset_lsb.B)*-1;
 	// Covert from LSB to PU (A) and filter out small readings
 	Motor1.Iphase_pu.A = phase_A_current_raw * LSB_TO_PU;
 	Motor1.Iphase_pu.B = phase_B_current_raw * LSB_TO_PU;
@@ -38,8 +40,8 @@ void process_currents()
 	Motor1.Iphase_pu.C = -Motor1.Iphase_pu.A - Motor1.Iphase_pu.B;
 	
 	/* Motor 2 negative is A instead of B*/ 
-	phase_A_current_raw = (adc1_res[2] + Motor2.Voffset_lsb.A);
+	phase_A_current_raw = (adc1_res[2] - Motor2.Voffset_lsb.A);
-	phase_B_current_raw = (adc1_res[3] + Motor2.Voffset_lsb.B)*-1;
+	phase_B_current_raw = (adc1_res[3] - Motor2.Voffset_lsb.B)*-1;
 	// Covert from LSB to PU (A) and filter out small readings
 	Motor2.Iphase_pu.A = phase_A_current_raw * LSB_TO_PU;
 	Motor2.Iphase_pu.B = phase_B_current_raw * LSB_TO_PU;
@@ -62,18 +64,31 @@ void enable_NVIC_IRQ(void)
 	//NVIC_EnableIRQ(TC4_IRQn);	 // TC4: M2_Speed_Timer
 	NVIC_EnableIRQ(DMAC_0_IRQn);
 	NVIC_EnableIRQ(DMAC_1_IRQn);
+	NVIC_EnableIRQ(DMAC_2_IRQn);
+	NVIC_EnableIRQ(DMAC_3_IRQn);
+	NVIC_EnableIRQ(DMAC_4_IRQn);
 	NVIC_SetPriority(DMAC_0_IRQn, 2);
 	NVIC_SetPriority(ADC1_0_IRQn, 3);
 	NVIC_EnableIRQ(TCC0_0_IRQn);
-	NVIC_EnableIRQ(TCC1_0_IRQn);
+	//NVIC_EnableIRQ(TCC1_0_IRQn);
 	NVIC_EnableIRQ(EIC_2_IRQn);
+	         
 	NVIC_EnableIRQ(SERCOM1_1_IRQn);
+	NVIC_EnableIRQ(SERCOM2_1_IRQn);
 	//NVIC_SetPriority(SERCOM1_1_IRQn, 1);
 	NVIC_EnableIRQ(TC0_IRQn);
 	//NVIC_EnableIRQ(TC0_IRQn);
 	//NVIC_SetPriority(EIC_2_IRQn, 3);
 	//NVIC_SetPriority(TCC0_0_IRQn, 3);
 	//NVIC_EnableIRQ(EIC_5_IRQn);
+	
+	
+	
+	/* Reset Latch Interrupt */
+	ext_irq_register(PIN_PB30, M1_RESET_BAR);
+	ext_irq_register(PIN_PB31, M2_RESET_BAR);
+	NVIC_EnableIRQ(EIC_14_IRQn);
+	NVIC_EnableIRQ(EIC_15_IRQn);
 }
 
 void APPLICATION_StateMachine(void)
@@ -91,11 +106,8 @@ void APPLICATION_StateMachine(void)
 		case SYSTEM_INIT:
 			/* Toggle driver reset Latch */
 			gpio_set_pin_level(M1_RST, true);
-			delay_ms(1);
 			gpio_set_pin_level(M1_RST, false);
-			delay_ms(1);
 			gpio_set_pin_level(M2_RST, true);
-			delay_ms(1);
 			gpio_set_pin_level(M2_RST, false);
 			/* Update State Variables */
 			applicationStatus.previousstate = applicationStatus.currentstate;
@@ -160,17 +172,32 @@ int main(void)
 	boardToBoardTransferInit();
 	/* DMA Configs */
 	init_dma();
+	
+	/* ECAT State Machine First run */
 	ECAT_STATE_MACHINE();
 		
 	//angle_sensor_init();
-	//initialize_ads();
+	initialize_ads();
 	/* External IRQ Config */
 	custom_logic_enable();
-	enable_NVIC_IRQ();
-	__enable_irq();
 	
-	//ext_irq_register(GPIO_PIN(ADS_DATA_RDY), ADS1299_dataReadyISR);
+	__enable_irq();
-	//ADS1299_START();
+	ADS1299_START();
+	delay_us(20);
+	/* ADS Result Ready Interrupt, active low */
+	
+	/* Enable Reception 
+	* Enable RX channels at startup,  Linked to itself so never ends
+	*/
+	_dma_enable_transaction(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, false);
+	_dma_enable_transaction(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, false);
+	
+	/* Clear Exint Flag */
+	EIC->INTFLAG.bit.EXTINT = (1<<2);
+	
+	ext_irq_register(GPIO_PIN(ADS_DATA_RDY), ADS1299_dataReadyISR);
+	enable_NVIC_IRQ();
+	
 	
 	/* Replace with your application code */
 	while (1) {
@@ -179,19 +206,21 @@ int main(void)
 		if (Motor1.timerflags.motor_telemetry_flag) {
 			
 			Motor1.timerflags.motor_telemetry_flag = false;	
-			delay_us(10);
+
-			DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+			//DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
-			DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+			if (DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLA.bit.ENABLE)
+				{
+				/* Resume */
+					//DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLB.bit.CMD = 0x02;
+				}
+			else {
+			/* Enable */
+					DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;	
+			}			
 					
-			if (DMAC->Channel[CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL].CHSTATUS.bit.PEND == true)
-			{
-				volatile int x = 0;
-			}
-			
-			
 			update_telemetry();
 			update_setpoints();
-	
+				
 			//PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
 
 			//_dma_enable_transaction(CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL, false);
@@ -212,7 +241,6 @@ int main(void)
 		}
 		
 		if (Motor1.timerflags.current_loop_tic) {
-			
 				Motor1.timerflags.current_loop_tic = false;
 				APPLICATION_StateMachine();
 				exec_commutation(&Motor1);
@@ -221,6 +249,24 @@ int main(void)
 		
 		if (ADS1299.data_ReadyFlag){
 			ADS1299.data_ReadyFlag = false;
+			//PORT->Group[0].OUTCLR.reg = (1<<GPIO_PIN(SPI2_SS));
+			
+			if (DMAC->Channel[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL].CHCTRLA.bit.ENABLE)
+			{
+			/* Resume */
+				//DMAC->Channel[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL].CHCTRLB.bit.CMD = 0x02;
+				volatile int x = 0;
+			} else {
+				DMAC->Channel[CONF_SERCOM_2_SPI_M_DMA_TX_CHANNEL].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+			/* Enable */
+			//DMAC->Channel[8].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+				
+			}		
+			
+			//_dma_enable_transaction(2, false);
+			//_dma_enable_transaction(8, false);
+					
+			
 			//ADS1299_UPDATECHANNELDATA();
 		}
 

2_Motor_Master/Motor_Master/Motor_Master/motorparameters.h

@@ -154,7 +154,7 @@ const static BLDCMotor_param_t FH_22mm24BXTR = {
 	.controller_param.Pid_Speed.Kp = 0.00004f,
 	.controller_param.Pid_Speed.Ki = 0.0000001f,
 	//.controller_param.Pid_Speed.Ki = 0.0000001f,
-	.controller_param.Pi_Pos.Kp	   = 50.0f,
+	.controller_param.Pi_Pos.Kp	   = 30.0f,
 	.controller_param.Pi_Pos.Ki	   = 0.0f,
 	.motor_MaxPWM = 600.0,
 };
@@ -169,13 +169,13 @@ const static BLDCMotor_param_t FH_32mm12BXTR = {
 	.motor_LD_H					   = 0.000331,
 	.motor_LQ_H					   = 0.000331,
 	.motor_Flux_WB				   = 0.0063879968,
-	.motor_Max_Spd_RPM			   = 1000,
+	.motor_Max_Spd_RPM			   = 2000,
 	.motor_MeasureRange_RPM		   = 3200,		//(1.2f * MOTOR_MAX_SPD_RPM)f   // give 20% headroom
 	.motor_Max_Spd_ELEC			   = 12000,		//(MOTOR_MAX_SPD_RPM/60)*MOTOR_POLEPAIRS
 	.motor_Max_Current_IDC_A	   = (1.2),
-	.controller_param.Pid_Speed.Kp = 0.0004f,
+	.controller_param.Pid_Speed.Kp = 0.0003f,
 	.controller_param.Pid_Speed.Ki = 0.0000001f,
-	.controller_param.Pi_Pos.Kp	   = 50.0f,
+	.controller_param.Pi_Pos.Kp	   = 30.0f,
 	.controller_param.Pi_Pos.Ki	   = 0.000f,
 	//.controller_param.Pid_Speed.Kp = 0.00002f,
 	//.controller_param.Pid_Speed.Ki = 0.0f,

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51.atsln

@@ -0,0 +1,22 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "Two_Motor_D51", "Two_Motor_D51\Two_Motor_D51.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.env_conf

@@ -0,0 +1,6 @@
+<environment>
+  <configurations/>
+  <device-packs>
+    <device-pack device="ATSAMD51J18A" name="SAMD51_DFP" vendor="Atmel" version="1.2.139"/>
+  </device-packs>
+</environment>

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/.atmelstart/AtmelStart.gpdsc

@@ -0,0 +1,254 @@
+<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
+  <vendor>Atmel</vendor>
+  <name>Two_Motor_D51</name>
+  <description>Project generated by Atmel Start</description>
+  <url>http://start.atmel.com/</url>
+  <releases>
+    <release version="1.0.1">Initial version</release>
+  </releases>
+  <taxonomy>
+    <description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
+  </taxonomy>
+  <generators>
+    <generator id="AtmelStart">
+      <description>Atmel Start</description>
+      <select Dname="ATSAMD51J18A" Dvendor="Atmel:3"/>
+      <command>http://start.atmel.com/</command>
+      <files>
+        <file category="generator" name="atmel_start_config.atstart"/>
+        <file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
+      </files>
+    </generator>
+  </generators>
+  <conditions>
+    <condition id="CMSIS Device Startup">
+      <description>Dependency on CMSIS core and Device Startup components</description>
+      <require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
+      <require Cclass="Device" Cgroup="Startup" Cversion="1.2.0"/>
+    </condition>
+    <condition id="ARMCC, GCC, IAR">
+      <require Dname="ATSAMD51J18A"/>
+      <accept Tcompiler="ARMCC"/>
+      <accept Tcompiler="GCC"/>
+      <accept Tcompiler="IAR"/>
+    </condition>
+    <condition id="GCC">
+      <require Dname="ATSAMD51J18A"/>
+      <accept Tcompiler="GCC"/>
+    </condition>
+  </conditions>
+  <components generator="AtmelStart">
+    <component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
+      <description>Atmel Start Framework</description>
+      <RTE_Components_h>#define ATMEL_START</RTE_Components_h>
+      <files>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/custom_logic.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/evsys.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/ext_irq.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_async.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/pwm.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/quad_spi_dma.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_dma.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_sync.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_slave_sync.rst"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_custom_logic.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_evsys.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_ext_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_i2c_m_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_qspi_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_s_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_cmcc.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_custom_logic.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_evsys.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ext_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_cache.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_evsys.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_async.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_qspi_dma.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
+        <file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hpl/doc_lite/tc.rst"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_cmcc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dac_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hmatrixb_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_i2s_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_icm_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pcc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pdec_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_qspi_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ramecc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sdhc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_d51.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_d51.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_pwm.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_pwm.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_timer.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_ext_irq.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_pwm.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_dma.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_sync.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_s_sync.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/ccl/hpl_ccl.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/cmcc/hpl_cmcc.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m4.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/eic/hpl_eic.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/evsys/hpl_evsys.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/qspi/hpl_qspi.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_adc_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_ccl_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_eic_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_evsys_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_qspi_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tcc_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="config"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/adc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/ccl"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/cmcc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/eic"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/evsys"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/qspi"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/ramecc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/tc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/tcc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+      </files>
+    </component>
+  </components>
+</package>

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.c

@@ -0,0 +1,330 @@
+/*
+ * ADS1299.c
+ *
+ * Created: 8/22/2021 3:25:55 PM
+ *  Author: ge37vez
+ */ 
+
+#include "ADS1299.h"
+
+/* Settings 
+* No daisy:
+* 4 EMG channels channels at 1000.0 Hz.
+* Gain 24, SRB2 Open, Normal electrode input
+* Route all Channels_P to Bias derivation
+* Route all Channels_P to Bias derivation
+* Lead off functions off
+
+Expected ADS Board Registers
+* ADS_ID, 00, 3C, 0, 0, 1, 1, 1, 1, 1, 0
+* CONFIG1, 01, 94, 1, 0, 0, 1, 0, 1, 0, 0
+* CONFIG2, 02, C0, 1, 1, 0, 0, 0, 0, 0, 0
+* CONFIG3, 03, EC, 1, 1, 1, 0, 1, 1, 0, 0
+* LOFF, 04, 02, 0, 0, 0, 0, 0, 0, 1, 0
+* CH1SET, 05, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH2SET, 06, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH3SET, 07, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH4SET, 08, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH5SET, 09, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH6SET, 0A, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH7SET, 0B, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* CH8SET, 0C, 68, 0, 1, 1, 0, 1, 0, 0, 0
+* BIAS_SENSP, 0D, FF, 1, 1, 1, 1, 1, 1, 1, 1
+* BIAS_SENSN, 0E, FF, 1, 1, 1, 1, 1, 1, 1, 1
+* LOFF_SENSP, 0F, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* LOFF_SENSN, 10, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* LOFF_FLIP, 11, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* LOFF_STATP, 12, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* LOFF_STATN, 13, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* GPIO, 14, 0F, 0, 0, 0, 0, 1, 1, 1, 1
+* MISC1, 15, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* MISC2, 16, 00, 0, 0, 0, 0, 0, 0, 0, 0
+* CONFIG4, 17, 00, 0, 0, 0, 0, 0, 0, 0, 0
+*/
+
+void initialize_ads()
+{
+	spi_m_sync_disable(ADS1299.SPI_descr);
+	/* Set Mode 1 */
+	hri_sercomspi_write_CTRLA_CPOL_bit((SercomSpi *)(ADS1299.SPI_descr->dev.prvt), false);
+	hri_sercomspi_write_CTRLA_CPHA_bit((SercomSpi *)(ADS1299.SPI_descr->dev.prvt), true);
+	/* Init SPI*/
+	spi_m_sync_enable(ADS1299.SPI_descr);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+	delay_us(20);
+	
+	/* Reset ADS1299 - Reset Active Low*/
+	gpio_set_pin_level(ADS1299.reset_pin, false);
+	delay_us(20);
+	gpio_set_pin_level(ADS1299.reset_pin, true);
+	delay_us(20);
+	
+	ADS1299_RESET();					   // all registers set to default
+	ADS1299_SDATAC();					   // stop Read Data Continuous mode to communicate with ADS
+	ADS1299_RREGS(0x00, 0x17);			   // read ADS registers starting at 0x00 and ending at 0x17
+
+	/* Write Config Registers */
+	ADS1299_WREG(CONFIG1,0x94);			   // Set Config 1 Register
+	//ADS1299_WREG(CONFIG2,0xC0);		   // Set Config 2 Register - Standard
+	ADS1299_WREG(CONFIG2,0xD4);			   // Set Config 2 Register - internal test signal, pulsed
+	//ADS1299_WREG(CONFIG2,0xD7);		   // Set Config 2 Register - internal test signal, DC
+	ADS1299_WREG(CONFIG3,0xEC);			   // Set Config 3 Register
+	ADS1299_WREG(LOFF,0x02);			   // Set LOFF Register
+	for(uint8_t i=CH1SET; i<=CH4SET; i++)  // set up to modify the 4 channel setting registers
+	{  
+		//ADS1299.reg_data[i] = 0x68;        // the regData array mirrors the ADS1299 register addresses
+		ADS1299.reg_data[i] = 0x6D;          // Test signal
+	}
+	ADS1299_WREGS(CH1SET,3);               // write new channel settings
+	ADS1299_WREG(BIAS_SENSP,0xFF);		   // Set BIAS_SENSP Register
+	ADS1299_WREG(BIAS_SENSN,0xFF);		   // Set BIAS_SENSN Register
+	ADS1299_WREG(BIAS_SENSP,0xFF);		   // Set BIAS_SENSP Register
+	ADS1299_WREG(GPIO_REG,0x0F);		   // Set BIAS_SENSP Register
+	/* Remaining Registers left at 0x00 */
+	ADS1299_RREGS(0x00, 0x17);			   // read ADS registers to verify settings
+	ADS1299_RDATAC();					   // enter Read Data Continuous mode
+	volatile int x = 0;
+}
+
+uint8_t getDeviceID()
+{
+	uint8_t data = ADS1299_RREG(0x00);
+	return data;
+}
+
+// ----------------------------------------------------------------------
+// AS5048 Registers & Commands
+// ----------------------------------------------------------------------
+
+void ADS1299_WAKEUP() {
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _WAKEUP);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+	delay_us(3);  		//must wait 4 tCLK cycles before sending another command (Datasheet, pg. 35)
+}
+
+void ADS1299_STANDBY() {		// only allowed to send WAKEUP after sending STANDBY
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _STANDBY);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+}
+
+void ADS1299_RESET() {			// reset all the registers to default settings
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _RESET);
+	delay_us(12);   	//must wait 18 tCLK cycles to execute this command (Datasheet, pg. 35)
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+}
+
+void ADS1299_START() {			//start data conversion
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _START);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+	init_streaming_mode();
+	
+}
+
+void init_streaming_mode()
+{
+	spi_m_sync_disable(ADS1299.SPI_descr);
+	/* Change to 32-Bit Mode */
+	SERCOM2->SPI.CTRLC.bit.ICSPACE = 4;
+	SERCOM2->SPI.CTRLC.bit.DATA32B= true;
+	SERCOM2->SPI.LENGTH.bit.LENEN = true;
+	SERCOM2->SPI.LENGTH.bit.LEN = 3;
+	/* Init SPI*/
+	spi_m_sync_enable(ADS1299.SPI_descr);
+}
+void ADS1299_STOP() {			//stop data conversion
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _STOP);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+}
+
+void ADS1299_RDATAC() {
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _RDATAC);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+	delay_us(3);
+}
+void ADS1299_SDATAC() {
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, _SDATAC);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+	delay_us(3);   //must wait 4 tCLK cycles after executing this command (Datasheet, pg. 37)
+}
+
+// ----------------------------------------------------------------------
+// SPI register Related Commands
+// ----------------------------------------------------------------------
+//  reads ONE register at _address
+uint8_t ADS1299_RREG(uint8_t _address) 
+{
+	uint8_t opcode1 = _address + 0x20; 							//  RREG expects 001rrrrr where rrrrr = _address
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, opcode1);
+	_transfer_byte(ADS1299.SPI_descr, 0x00);
+	ADS1299.reg_data[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+	return ADS1299.reg_data[_address];
+}
+
+// Read more than one register starting at _address
+void ADS1299_RREGS(uint8_t _address, uint8_t _numRegistersMinusOne) 
+{
+	uint8_t opcode1 = _address + 0x20; 							//  RREG expects 001rrrrr where rrrrr = _address
+	gpio_set_pin_level(ADS1299.SS_pin, false);
+	_transfer_byte(ADS1299.SPI_descr, opcode1);
+	_transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne);
+	for(int i = 0; i <= _numRegistersMinusOne; i++){			//  add register uint8_t to mirror array
+        ADS1299.reg_data[_address + i] = _transfer_byte(ADS1299.SPI_descr, 0x00);	
+	}
+	//ADS1299.regData[_address] = _transfer_byte(ADS1299.SPI_descr, 0x00);
+	gpio_set_pin_level(ADS1299.SS_pin, true);
+}
+
+void ADS1299_WREG(uint8_t _address, uint8_t _value) {					//  Write ONE register at _address
+	uint8_t opcode1 = _address + 0x40; 							//  WREG expects 010rrrrr where rrrrr = _address
+	gpio_set_pin_level(ADS1299.SS_pin, false); 					//  open SPI
+	_transfer_byte(ADS1299.SPI_descr, opcode1);					//  Send WREG command & address
+	_transfer_byte(ADS1299.SPI_descr, 0x00);						//	Send number of registers to read -1
+	_transfer_byte(ADS1299.SPI_descr, _value);					//  Write the value to the register
+	gpio_set_pin_level(ADS1299.SS_pin, true);					//  close SPI
+	ADS1299.reg_data[_address] = _value;							//  update the mirror array
+}
+
+void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne) {
+	uint8_t opcode1 = _address + 0x40;							//  WREG expects 010rrrrr where rrrrr = _address
+	gpio_set_pin_level(ADS1299.SS_pin, false); 					//  open SPI
+	_transfer_byte(ADS1299.SPI_descr, opcode1);					//  Send WREG command & address
+	_transfer_byte(ADS1299.SPI_descr, _numRegistersMinusOne);	//	Send number of registers to read -1
+	for (int i=_address; i <=(_address + _numRegistersMinusOne); i++){
+		_transfer_byte(ADS1299.SPI_descr, ADS1299.reg_data[i]);	//  Write to the registers
+	}
+	gpio_set_pin_level(ADS1299.SS_pin, true);					//  close SPI
+}
+
+//read data
+void ADS1299_RDATA() {	//  use in Stop Read Continuous mode when DRDY goes low
+	uint8_t inByte;
+	ADS1299.stat_1 = 0;							//  clear the status registers
+	int nchan = 4;	//assume 4 channel.  
+	gpio_set_pin_level(ADS1299.SS_pin, false);				//  open SPI
+	_transfer_byte(ADS1299.SPI_descr, _RDATA);
+	
+	for(int i=0; i<3; i++){			//  read 3 byte status register (1100+LOFF_STATP+LOFF_STATN+GPIO[7:4])
+		inByte = _transfer_byte(ADS1299.SPI_descr, 0x00);
+		ADS1299.stat_1 = (ADS1299.stat_1<<8) | inByte;
+	}
+	
+	for(int i = 0; i<nchan; i++){
+		for(int j=0; j<3; j++){		//  read 24 bits of channel data from 1st ADS in 8 3 byte chunks
+			inByte = _transfer_byte(ADS1299.SPI_descr, 0x00);
+			ADS1299.channel_data[i] = (ADS1299.channel_data[i]<<8) | inByte;
+		}
+	}
+		
+	for(int i=0; i<nchan; i++){			// convert 3 byte 2's compliment to 4 byte 2's compliment
+		if(bitRead(ADS1299.channel_data[i],23) == 1){
+			ADS1299.channel_data[i] |= 0xFF000000;
+			}else{
+			ADS1299.channel_data[i] &= 0x00FFFFFF;
+		}
+	}
+}
+
+
+//int32_t* ADS1299_UPDATECHANNELDATA()
+//{
+	//uint8_t inByte;
+	//int nchan=4;  //assume 8 channel.  If needed, it automatically changes to 16 automatically in a later block.
+	//gpio_set_pin_level(ADS1299.SS_pin, false);				//  open SPI
+	//
+	//// READ CHANNEL DATA FROM FIRST ADS IN DAISY LINE
+	//for(int i=0; i<3; i++){		//  read 3 byte status register from ADS 1 (1100+LOFF_STATP+LOFF_STATN+GPIO[7:4])
+		//inByte = _transfer_byte(ADS1299.SPI_descr,0x00);
+		//ADS1299.stat_1 = (ADS1299.stat_1<<8) | inByte;				
+	//}
+	//
+	//for(int i = 0; i<8; i++){
+		//for(int j=0; j<3; j++){		//  read 24 bits of channel data from 1st ADS in 8 3 byte chunks
+			//inByte = _transfer_byte(ADS1299.SPI_descr, 0x00);
+			//ADS1299.channel_data[i] = (ADS1299.channel_data[i]<<8) | inByte;
+		//}
+	//}
+		//
+	//gpio_set_pin_level(ADS1299.SS_pin, true);				//  close SPI
+	//
+	////reformat the numbers
+	//for(int i=0; i<nchan; i++){			// convert 3 byte 2's compliment to 4 byte 2's compliment	
+		//if(bitRead(ADS1299.channel_data[i],23) == 1){	
+			//ADS1299.channel_data[i] |= 0xFF000000;
+		//}else{
+			//ADS1299.channel_data[i] &= 0x00FFFFFF;
+		//}
+	//}
+	//return &ADS1299.channel_data;
+//}
+
+int32_t* ADS1299_UPDATECHANNELDATA()
+{
+	uint8_t inByte;
+	int nchan=8;  //assume 8 channel.  If needed, it automatically changes to 16 automatically in a later block.
+	gpio_set_pin_level(ADS1299.SS_pin, false);				//  open SPI
+	
+	// READ CHANNEL DATA FROM FIRST ADS IN DAISY LINE
+	for(int i=0; i<3; i++){		//  read 3 byte status register from ADS 1 (1100+LOFF_STATP+LOFF_STATN+GPIO[7:4])
+		inByte = _transfer_byte(ADS1299.SPI_descr,0x00);
+		ADS1299.stat_1 = (ADS1299.stat_1<<8) | inByte;				
+	}
+	
+	for(int i = 0; i<8; i++){
+		for(int j=0; j<3; j++){		//  read 24 bits of channel data from 1st ADS in 8 3 byte chunks
+			inByte = _transfer_byte(ADS1299.SPI_descr, 0x00);
+			_ads1299_channel_data[i] = (_ads1299_channel_data[i]<<8) | inByte;
+		}
+	}
+		
+	gpio_set_pin_level(ADS1299.SS_pin, true);				//  close SPI
+	
+	//reformat the numbers
+	for(int i=0; i<nchan; i++){			// convert 3 byte 2's compliment to 4 byte 2's compliment	
+		if(bitRead(_ads1299_channel_data[i],23) == 1){	
+			_ads1299_channel_data[i] |= 0xFF000000;
+		}else{
+			_ads1299_channel_data[i] &= 0x00FFFFFF;
+		}
+	}
+	return &_ads1299_channel_data;
+}
+
+uint8_t _transfer_byte(struct spi_m_sync_descriptor *spi, uint8_t command)
+{
+	uint8_t in_buf[1], out_buf[1];
+	uint8_t wordRead;
+	
+	out_buf[0] = command; 
+	struct spi_xfer xfer;
+	xfer.rxbuf = in_buf;
+	xfer.txbuf = out_buf;
+	xfer.size  = 1;
+	spi_m_sync_transfer(ADS1299.SPI_descr, &xfer);
+	wordRead = in_buf[0];
+	return (wordRead);
+}
+
+uint16_t _transfer_word(struct spi_m_sync_descriptor *spi, uint16_t command)
+{
+	uint8_t in_buf[2], out_buf[2];
+	uint16_t wordRead;
+	
+	out_buf[1] = command & 0xFF;
+	out_buf[0] = ( command >> 8 ) & 0xFF;
+	struct spi_xfer  xfer;
+	xfer.rxbuf = in_buf;
+	xfer.txbuf = (uint8_t *)out_buf;
+	xfer.size  = 2;
+	spi_m_sync_transfer(ADS1299.SPI_descr, &xfer);
+	wordRead = (uint16_t)((in_buf[0] << 8) | in_buf[1]);
+	return (wordRead);
+}

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/ADS1299.h

@@ -0,0 +1,113 @@
+/*
+ * ADS1299.h
+ *
+ * Created: 8/22/2021 3:25:39 PM
+ *  Author: ge37vez
+ */ 
+
+
+#ifndef ADS1299_H_
+#define ADS1299_H_
+
+#include "atmel_start.h"
+
+#define bitRead(value, bit) (((value) >> (bit)) & 0x01)
+#define bitSet(value, bit) ((value) |= (1UL << (bit)))
+#define bitClear(value, bit) ((value) &= ~(1UL << (bit)))
+#define bitWrite(value, bit, bitvalue) ((bitvalue) ? bitSet(value, bit) : bitClear(value, bit))
+
+//SPI Command Definition Byte Assignments (Datasheet, p35)
+#define _WAKEUP		0x02 // Wake-up from standby mode
+#define _STANDBY	0x04 // Enter Standby mode
+#define _RESET		0x06 // Reset the device registers to default
+#define _START		0x08 // Start and restart (synchronize) conversions
+#define _STOP		0x0A // Stop conversion
+#define _RDATAC		0x10 // Enable Read Data Continuous mode (default mode at power-up)
+#define _SDATAC		0x11 // Stop Read Data Continuous mode
+#define _RDATA		0x12 // Read data by command; supports multiple read back
+
+//Register Addresses
+#define ID			0x00
+#define CONFIG1		0x01
+#define CONFIG2		0x02
+#define CONFIG3		0x03
+#define LOFF		0x04
+#define CH1SET		0x05
+#define CH2SET		0x06
+#define CH3SET		0x07
+#define CH4SET		0x08
+#define CH5SET		0x09
+#define CH6SET		0x0A
+#define CH7SET		0x0B
+#define CH8SET		0x0C
+#define BIAS_SENSP  0x0D
+#define BIAS_SENSN  0x0E
+#define LOFF_SENSP  0x0F
+#define LOFF_SENSN  0x10
+#define LOFF_FLIP   0x11
+#define LOFF_STATP  0x12
+#define LOFF_STATN  0x13
+#define GPIO_REG    0x14
+#define MISC1       0x15
+#define MISC2       0x16
+#define CONFIG4     0x17
+
+#define ADS_BUFFER_SIZE 9
+
+volatile int32_t _ads1299_channel_data[9];
+volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
+volatile uint8_t _ads1299_reg_data[24];
+
+/* Struct Definitions */
+volatile struct SPI_ADS1299 {
+	volatile struct spi_m_sync_descriptor *SPI_descr;
+	volatile bool data_ReadyFlag;
+	volatile uint32_t SS_pin;
+	volatile uint32_t reset_pin;
+	volatile uint8_t* reg_data;
+	volatile int32_t* channel_data; 
+	volatile int16_t  stat_1;
+};
+
+static volatile struct SPI_ADS1299 ADS1299 = {
+	.SPI_descr = &SPI_2,
+	.data_ReadyFlag = false,
+	.SS_pin = SPI2_SS,
+	.reset_pin = ADS_RESET,
+	.reg_data = &_ads1299_reg_data[0], 
+	.channel_data = &_ads1299_channel_data[0],
+};
+
+void initialize_ads();
+void init_streaming_mode();
+
+//ADS1299 SPI Command Definitions (Datasheet, p35)
+//System Commands
+void ADS1299_WAKEUP();
+void ADS1299_STANDBY();
+void ADS1299_RESET();
+void ADS1299_START();
+void ADS1299_STOP();
+
+//Data Read Commands
+void ADS1299_RDATAC();
+void ADS1299_SDATAC();
+void ADS1299_RDATA();
+
+//Register Read/Write Commands
+uint8_t getDeviceID();
+uint8_t ADS1299_RREG(uint8_t _address);
+void ADS1299_RREGS(uint8_t _address, uint8_t _numRegistersMinusOne);
+void printRegisterName(uint8_t _address);
+void ADS1299_WREG(uint8_t _address, uint8_t _value);
+void ADS1299_WREGS(uint8_t _address, uint8_t _numRegistersMinusOne);
+void printHex(uint8_t _data);
+int32_t* ADS1299_UPDATECHANNELDATA();
+
+uint8_t _transfer_byte(struct spi_m_sync_descriptor *spi, uint8_t command);
+uint16_t _transfer_word(struct spi_m_sync_descriptor *spi, uint16_t command);
+//SPI Transfer function
+
+
+
+#endif /* ADS1299_H_ */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/RTE_Components.h

@@ -0,0 +1,54 @@
+ /**
+ * \file
+ *
+ * \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
+ *
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.
+ *
+ * \acme_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \acme_license_stop
+ *
+ * Project: Two_Motor_D51
+ * Target:  ATSAMD51J18A 
+ *
+ **/
+
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+#define ATMEL_START
+
+#endif /* RTE_COMPONENTS_H */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_adc_config.h

@@ -0,0 +1,595 @@
+/* Auto-generated config file hpl_adc_config.h */
+#ifndef HPL_ADC_CONFIG_H
+#define HPL_ADC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#ifndef CONF_ADC_0_ENABLE
+#define CONF_ADC_0_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <o> Conversion Result Resolution
+// <0x0=>12-bit
+// <0x1=>16-bit (averaging must be enabled)
+// <0x2=>10-bit
+// <0x3=>8-bit
+// <i>  Defines the bit resolution for the ADC sample values (RESSEL)
+// <id> adc_resolution
+#ifndef CONF_ADC_0_RESSEL
+#define CONF_ADC_0_RESSEL 0x0
+#endif
+
+// <o> Reference Selection
+// <0x0=>Internal bandgap reference
+// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
+// <0x3=>VDDANA
+// <0x4=>External reference A
+// <0x5=>External reference B
+// <0x6=>External reference C
+// <i> Select the reference for the ADC (REFSEL)
+// <id> adc_reference
+#ifndef CONF_ADC_0_REFSEL
+#define CONF_ADC_0_REFSEL 0x0
+#endif
+
+// <o> Prescaler configuration
+// <0x0=>Peripheral clock divided by 2
+// <0x1=>Peripheral clock divided by 4
+// <0x2=>Peripheral clock divided by 8
+// <0x3=>Peripheral clock divided by 16
+// <0x4=>Peripheral clock divided by 32
+// <0x5=>Peripheral clock divided by 64
+// <0x6=>Peripheral clock divided by 128
+// <0x7=>Peripheral clock divided by 256
+// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
+// <id> adc_prescaler
+#ifndef CONF_ADC_0_PRESCALER
+#define CONF_ADC_0_PRESCALER 0x0
+#endif
+
+// <q> Free Running Mode
+// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
+// <id> adc_freerunning_mode
+#ifndef CONF_ADC_0_FREERUN
+#define CONF_ADC_0_FREERUN 0
+#endif
+
+// <q> Differential Mode
+// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
+// <id> adc_differential_mode
+#ifndef CONF_ADC_0_DIFFMODE
+#define CONF_ADC_0_DIFFMODE 0
+#endif
+
+// <o> Positive Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x08=>ADC AIN8 pin
+// <0x09=>ADC AIN9 pin
+// <0x0A=>ADC AIN10 pin
+// <0x0B=>ADC AIN11 pin
+// <0x0C=>ADC AIN12 pin
+// <0x0D=>ADC AIN13 pin
+// <0x0E=>ADC AIN14 pin
+// <0x0F=>ADC AIN15 pin
+// <0x18=>1/4 scaled core supply
+// <0x19=>1/4 Scaled VBAT Supply
+// <0x1A=>1/4 scaled I/O supply
+// <0x1B=>Bandgap voltage
+// <0x1C=>Temperature reference (PTAT)
+// <0x1D=>Temperature reference (CTAT)
+// <0x1E=>DAC Output
+// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
+// <id> adc_pinmux_positive
+#ifndef CONF_ADC_0_MUXPOS
+#define CONF_ADC_0_MUXPOS 0x0
+#endif
+
+// <o> Negative Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x18=>Internal ground
+// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
+// <id> adc_pinmux_negative
+#ifndef CONF_ADC_0_MUXNEG
+#define CONF_ADC_0_MUXNEG 0x0
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> adc_advanced_settings
+#ifndef CONF_ADC_0_ADVANCED
+#define CONF_ADC_0_ADVANCED 0
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
+// <id> adc_arch_runstdby
+#ifndef CONF_ADC_0_RUNSTDBY
+#define CONF_ADC_0_RUNSTDBY 0
+#endif
+
+// <q>Debug Run
+// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
+// <id> adc_arch_dbgrun
+#ifndef CONF_ADC_0_DBGRUN
+#define CONF_ADC_0_DBGRUN 0
+#endif
+
+// <q> On Demand Control
+// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
+// <id> adc_arch_ondemand
+#ifndef CONF_ADC_0_ONDEMAND
+#define CONF_ADC_0_ONDEMAND 0
+#endif
+
+// <q> Left-Adjusted Result
+// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
+// <id> adc_arch_leftadj
+#ifndef CONF_ADC_0_LEFTADJ
+#define CONF_ADC_0_LEFTADJ 0
+#endif
+
+// <q> Reference Buffer Offset Compensation Enable
+// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
+// <id> adc_arch_refcomp
+#ifndef CONF_ADC_0_REFCOMP
+#define CONF_ADC_0_REFCOMP 0
+#endif
+
+// <q>Comparator Offset Compensation Enable
+// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
+// <id> adc_arch_offcomp
+#ifndef CONF_ADC_0_OFFCOMP
+#define CONF_ADC_0_OFFCOMP 0
+#endif
+
+// <q> Digital Correction Logic Enabled
+// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
+// <id> adc_arch_corren
+#ifndef CONF_ADC_0_CORREN
+#define CONF_ADC_0_CORREN 0
+#endif
+
+// <o> Offset Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
+// <id> adc_arch_offsetcorr
+#ifndef CONF_ADC_0_OFFSETCORR
+#define CONF_ADC_0_OFFSETCORR 0
+#endif
+
+// <o> Gain Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
+// <id> adc_arch_gaincorr
+#ifndef CONF_ADC_0_GAINCORR
+#define CONF_ADC_0_GAINCORR 0
+#endif
+
+// <o> Adjusting Result / Division Coefficient <0-7>
+// <i> These bits define the division coefficient in 2n steps. (ADJRES)
+// <id> adc_arch_adjres
+#ifndef CONF_ADC_0_ADJRES
+#define CONF_ADC_0_ADJRES 0x0
+#endif
+
+// <o.0..10> Number of Samples to be Collected
+// <0x0=>1 sample
+// <0x1=>2 samples
+// <0x2=>4 samples
+// <0x3=>8 samples
+// <0x4=>16 samples
+// <0x5=>32 samples
+// <0x6=>64 samples
+// <0x7=>128 samples
+// <0x8=>256 samples
+// <0x9=>512 samples
+// <0xA=>1024 samples
+// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
+// <id> adc_arch_samplenum
+#ifndef CONF_ADC_0_SAMPLENUM
+#define CONF_ADC_0_SAMPLENUM 0x0
+#endif
+
+// <o> Sampling Time Length <0-63>
+// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
+// <id> adc_arch_samplen
+#ifndef CONF_ADC_0_SAMPLEN
+#define CONF_ADC_0_SAMPLEN 0
+#endif
+
+// <o> Window Monitor Mode
+// <0x0=>No window mode
+// <0x1=>Mode 1: RESULT above lower threshold
+// <0x2=>Mode 2: RESULT beneath upper threshold
+// <0x3=>Mode 3: RESULT inside lower and upper threshold
+// <0x4=>Mode 4: RESULT outside lower and upper threshold
+// <i> These bits enable and define the window monitor mode. (WINMODE)
+// <id> adc_arch_winmode
+#ifndef CONF_ADC_0_WINMODE
+#define CONF_ADC_0_WINMODE 0x0
+#endif
+
+// <o> Window Monitor Lower Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
+// <id> adc_arch_winlt
+#ifndef CONF_ADC_0_WINLT
+#define CONF_ADC_0_WINLT 0
+#endif
+
+// <o> Window Monitor Upper Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
+// <id> adc_arch_winut
+#ifndef CONF_ADC_0_WINUT
+#define CONF_ADC_0_WINUT 0
+#endif
+
+// <o> Bitmask for positive input sequence <0-4294967295>
+// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
+// <id> adc_arch_seqen
+#ifndef CONF_ADC_0_SEQEN
+#define CONF_ADC_0_SEQEN 0x0
+#endif
+
+// </e>
+
+// <e> Event Control
+// <id> adc_arch_event_settings
+#ifndef CONF_ADC_0_EVENT_CONTROL
+#define CONF_ADC_0_EVENT_CONTROL 0
+#endif
+
+// <q> Window Monitor Event Out
+// <i> Enables event output on window event (WINMONEO)
+// <id> adc_arch_winmoneo
+#ifndef CONF_ADC_0_WINMONEO
+#define CONF_ADC_0_WINMONEO 0
+#endif
+
+// <q> Result Ready Event Out
+// <i> Enables event output on result ready event (RESRDEO)
+// <id> adc_arch_resrdyeo
+#ifndef CONF_ADC_0_RESRDYEO
+#define CONF_ADC_0_RESRDYEO 0
+#endif
+
+// <q> Invert flush Event Signal
+// <i> Invert the flush event input signal (FLUSHINV)
+// <id> adc_arch_flushinv
+#ifndef CONF_ADC_0_FLUSHINV
+#define CONF_ADC_0_FLUSHINV 0
+#endif
+
+// <q> Trigger Flush On Event
+// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
+// <id> adc_arch_flushei
+#ifndef CONF_ADC_0_FLUSHEI
+#define CONF_ADC_0_FLUSHEI 0
+#endif
+
+// <q> Invert Start Conversion Event Signal
+// <i> Invert the start conversion event input signal (STARTINV)
+// <id> adc_arch_startinv
+#ifndef CONF_ADC_0_STARTINV
+#define CONF_ADC_0_STARTINV 0
+#endif
+
+// <q> Trigger Conversion On Event
+// <i> Trigger a conversion on event. (STARTEI)
+// <id> adc_arch_startei
+#ifndef CONF_ADC_0_STARTEI
+#define CONF_ADC_0_STARTEI 0
+#endif
+
+// </e>
+
+#ifndef CONF_ADC_1_ENABLE
+#define CONF_ADC_1_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <o> Conversion Result Resolution
+// <0x0=>12-bit
+// <0x1=>16-bit (averaging must be enabled)
+// <0x2=>10-bit
+// <0x3=>8-bit
+// <i>  Defines the bit resolution for the ADC sample values (RESSEL)
+// <id> adc_resolution
+#ifndef CONF_ADC_1_RESSEL
+#define CONF_ADC_1_RESSEL 0x0
+#endif
+
+// <o> Reference Selection
+// <0x0=>Internal bandgap reference
+// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
+// <0x3=>VDDANA
+// <0x4=>External reference A
+// <0x5=>External reference B
+// <0x6=>External reference C
+// <i> Select the reference for the ADC (REFSEL)
+// <id> adc_reference
+#ifndef CONF_ADC_1_REFSEL
+#define CONF_ADC_1_REFSEL 0x4
+#endif
+
+// <o> Prescaler configuration
+// <0x0=>Peripheral clock divided by 2
+// <0x1=>Peripheral clock divided by 4
+// <0x2=>Peripheral clock divided by 8
+// <0x3=>Peripheral clock divided by 16
+// <0x4=>Peripheral clock divided by 32
+// <0x5=>Peripheral clock divided by 64
+// <0x6=>Peripheral clock divided by 128
+// <0x7=>Peripheral clock divided by 256
+// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
+// <id> adc_prescaler
+#ifndef CONF_ADC_1_PRESCALER
+#define CONF_ADC_1_PRESCALER 0x2
+#endif
+
+// <q> Free Running Mode
+// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
+// <id> adc_freerunning_mode
+#ifndef CONF_ADC_1_FREERUN
+#define CONF_ADC_1_FREERUN 0
+#endif
+
+// <q> Differential Mode
+// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
+// <id> adc_differential_mode
+#ifndef CONF_ADC_1_DIFFMODE
+#define CONF_ADC_1_DIFFMODE 1
+#endif
+
+// <o> Positive Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x08=>ADC AIN8 pin
+// <0x09=>ADC AIN9 pin
+// <0x0A=>ADC AIN10 pin
+// <0x0B=>ADC AIN11 pin
+// <0x0C=>ADC AIN12 pin
+// <0x0D=>ADC AIN13 pin
+// <0x0E=>ADC AIN14 pin
+// <0x0F=>ADC AIN15 pin
+// <0x18=>1/4 scaled core supply
+// <0x19=>1/4 Scaled VBAT Supply
+// <0x1A=>1/4 scaled I/O supply
+// <0x1B=>Bandgap voltage
+// <0x1C=>Temperature reference (PTAT)
+// <0x1D=>Temperature reference (CTAT)
+// <0x1E=>DAC Output
+// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
+// <id> adc_pinmux_positive
+#ifndef CONF_ADC_1_MUXPOS
+#define CONF_ADC_1_MUXPOS 0x6
+#endif
+
+// <o> Negative Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x18=>Internal ground
+// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
+// <id> adc_pinmux_negative
+#ifndef CONF_ADC_1_MUXNEG
+#define CONF_ADC_1_MUXNEG 0x0
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> adc_advanced_settings
+#ifndef CONF_ADC_1_ADVANCED
+#define CONF_ADC_1_ADVANCED 1
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
+// <id> adc_arch_runstdby
+#ifndef CONF_ADC_1_RUNSTDBY
+#define CONF_ADC_1_RUNSTDBY 0
+#endif
+
+// <q>Debug Run
+// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
+// <id> adc_arch_dbgrun
+#ifndef CONF_ADC_1_DBGRUN
+#define CONF_ADC_1_DBGRUN 0
+#endif
+
+// <q> On Demand Control
+// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
+// <id> adc_arch_ondemand
+#ifndef CONF_ADC_1_ONDEMAND
+#define CONF_ADC_1_ONDEMAND 0
+#endif
+
+// <q> Left-Adjusted Result
+// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
+// <id> adc_arch_leftadj
+#ifndef CONF_ADC_1_LEFTADJ
+#define CONF_ADC_1_LEFTADJ 0
+#endif
+
+// <q> Reference Buffer Offset Compensation Enable
+// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
+// <id> adc_arch_refcomp
+#ifndef CONF_ADC_1_REFCOMP
+#define CONF_ADC_1_REFCOMP 0
+#endif
+
+// <q>Comparator Offset Compensation Enable
+// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
+// <id> adc_arch_offcomp
+#ifndef CONF_ADC_1_OFFCOMP
+#define CONF_ADC_1_OFFCOMP 0
+#endif
+
+// <q> Digital Correction Logic Enabled
+// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
+// <id> adc_arch_corren
+#ifndef CONF_ADC_1_CORREN
+#define CONF_ADC_1_CORREN 0
+#endif
+
+// <o> Offset Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
+// <id> adc_arch_offsetcorr
+#ifndef CONF_ADC_1_OFFSETCORR
+#define CONF_ADC_1_OFFSETCORR 0
+#endif
+
+// <o> Gain Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
+// <id> adc_arch_gaincorr
+#ifndef CONF_ADC_1_GAINCORR
+#define CONF_ADC_1_GAINCORR 0
+#endif
+
+// <o> Adjusting Result / Division Coefficient <0-7>
+// <i> These bits define the division coefficient in 2n steps. (ADJRES)
+// <id> adc_arch_adjres
+#ifndef CONF_ADC_1_ADJRES
+#define CONF_ADC_1_ADJRES 0x0
+#endif
+
+// <o.0..10> Number of Samples to be Collected
+// <0x0=>1 sample
+// <0x1=>2 samples
+// <0x2=>4 samples
+// <0x3=>8 samples
+// <0x4=>16 samples
+// <0x5=>32 samples
+// <0x6=>64 samples
+// <0x7=>128 samples
+// <0x8=>256 samples
+// <0x9=>512 samples
+// <0xA=>1024 samples
+// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
+// <id> adc_arch_samplenum
+#ifndef CONF_ADC_1_SAMPLENUM
+#define CONF_ADC_1_SAMPLENUM 0x0
+#endif
+
+// <o> Sampling Time Length <0-63>
+// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
+// <id> adc_arch_samplen
+#ifndef CONF_ADC_1_SAMPLEN
+#define CONF_ADC_1_SAMPLEN 2
+#endif
+
+// <o> Window Monitor Mode
+// <0x0=>No window mode
+// <0x1=>Mode 1: RESULT above lower threshold
+// <0x2=>Mode 2: RESULT beneath upper threshold
+// <0x3=>Mode 3: RESULT inside lower and upper threshold
+// <0x4=>Mode 4: RESULT outside lower and upper threshold
+// <i> These bits enable and define the window monitor mode. (WINMODE)
+// <id> adc_arch_winmode
+#ifndef CONF_ADC_1_WINMODE
+#define CONF_ADC_1_WINMODE 0x0
+#endif
+
+// <o> Window Monitor Lower Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
+// <id> adc_arch_winlt
+#ifndef CONF_ADC_1_WINLT
+#define CONF_ADC_1_WINLT 0
+#endif
+
+// <o> Window Monitor Upper Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
+// <id> adc_arch_winut
+#ifndef CONF_ADC_1_WINUT
+#define CONF_ADC_1_WINUT 0
+#endif
+
+// <o> Bitmask for positive input sequence <0-4294967295>
+// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
+// <id> adc_arch_seqen
+#ifndef CONF_ADC_1_SEQEN
+#define CONF_ADC_1_SEQEN 0x0
+#endif
+
+// </e>
+
+// <e> Event Control
+// <id> adc_arch_event_settings
+#ifndef CONF_ADC_1_EVENT_CONTROL
+#define CONF_ADC_1_EVENT_CONTROL 1
+#endif
+
+// <q> Window Monitor Event Out
+// <i> Enables event output on window event (WINMONEO)
+// <id> adc_arch_winmoneo
+#ifndef CONF_ADC_1_WINMONEO
+#define CONF_ADC_1_WINMONEO 0
+#endif
+
+// <q> Result Ready Event Out
+// <i> Enables event output on result ready event (RESRDEO)
+// <id> adc_arch_resrdyeo
+#ifndef CONF_ADC_1_RESRDYEO
+#define CONF_ADC_1_RESRDYEO 1
+#endif
+
+// <q> Invert flush Event Signal
+// <i> Invert the flush event input signal (FLUSHINV)
+// <id> adc_arch_flushinv
+#ifndef CONF_ADC_1_FLUSHINV
+#define CONF_ADC_1_FLUSHINV 0
+#endif
+
+// <q> Trigger Flush On Event
+// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
+// <id> adc_arch_flushei
+#ifndef CONF_ADC_1_FLUSHEI
+#define CONF_ADC_1_FLUSHEI 0
+#endif
+
+// <q> Invert Start Conversion Event Signal
+// <i> Invert the start conversion event input signal (STARTINV)
+// <id> adc_arch_startinv
+#ifndef CONF_ADC_1_STARTINV
+#define CONF_ADC_1_STARTINV 0
+#endif
+
+// <q> Trigger Conversion On Event
+// <i> Trigger a conversion on event. (STARTEI)
+// <id> adc_arch_startei
+#ifndef CONF_ADC_1_STARTEI
+#define CONF_ADC_1_STARTEI 0
+#endif
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_ADC_CONFIG_H

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_ccl_config.h

@@ -0,0 +1,499 @@
+/* Auto-generated config file hpl_ccl_config.h */
+#ifndef HPL_CCL_CONFIG_H
+#define HPL_CCL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <o> Sequential Control Logic 0
+// <0x0=> Sequential logic is disabled
+// <0x1=> D flip flop
+// <0x2=> JK flip flop
+// <0x3=> D latch
+// <0x4=> RS latch
+// <i> Selects mode for sequential module 0
+// <id> ccl_arch_seqsel_0
+#ifndef CONF_CCL_SEQSEL_0
+#define CONF_CCL_SEQSEL_0 0x0
+#endif
+
+// <o> Sequential Control Logic 1
+// <0x0=> Sequential logic is disabled
+// <0x1=> D flip flop
+// <0x2=> JK flip flop
+// <0x3=> D latch
+// <0x4=> RS latch
+// <i> Selects mode for sequential module 1
+// <id> ccl_arch_seqsel_1
+#ifndef CONF_CCL_SEQSEL_1
+#define CONF_CCL_SEQSEL_1 0x0
+#endif
+
+// <e> Lookup Table Control 0
+// <i> Enable and setup the lookup table module 0
+// <id> ccl_arch_lutctrl0
+#ifndef CONF_CCL_LUTCTRL_EN_0
+#define CONF_CCL_LUTCTRL_EN_0 1
+#endif
+
+// <o> Truth Table <0x00-0xFF>
+// <i> Define the value of truth logic according to inputs IN[2:0]
+// <id> ccl_arch_truth_0
+#ifndef CONF_CCL_TRUTH_0
+#define CONF_CCL_TRUTH_0 0x96
+#endif
+
+// <o> Input Source Selection 0
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel0_0
+#ifndef CONF_CCL_INSEL0_0
+#define CONF_CCL_INSEL0_0 0x4
+#endif
+
+// <o> Input Source Selection 1
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel1_0
+#ifndef CONF_CCL_INSEL1_0
+#define CONF_CCL_INSEL1_0 0x4
+#endif
+
+// <o> Input Source Selection 2
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel2_0
+#ifndef CONF_CCL_INSEL2_0
+#define CONF_CCL_INSEL2_0 0x4
+#endif
+
+// <q> Edge detector enable
+// <id> ccl_arch_edgesel_0
+#ifndef CONF_CCL_EDGESEL_0
+#define CONF_CCL_EDGESEL_0 0
+#endif
+
+// <o> Output Filter
+// <0x0=> Disabled
+// <0x1=> Synchronizer Enabled
+// <0x2=> Filter Enabled
+// <id> ccl_arch_filtsel_0
+#ifndef CONF_CCL_FILTSEL_0
+#define CONF_CCL_FILTSEL_0 0x0
+#endif
+
+// <h> Event settings 0
+
+// <q> Event output enable
+// <id> ccl_arch_luteo_0
+#ifndef CONF_CCL_LUTEO_0
+#define CONF_CCL_LUTEO_0 1
+#endif
+
+// <q> Event input enable
+// <id> ccl_arch_lutei_0
+#ifndef CONF_CCL_LUTEI_0
+#define CONF_CCL_LUTEI_0 0
+#endif
+
+// <q> Event input invert
+// <id> ccl_arch_invei_0
+#ifndef CONF_CCL_INVEI_0
+#define CONF_CCL_INVEI_0 0
+#endif
+
+// </h>
+
+// </e>
+
+// <hidden> Persistance settings 0
+
+// <s> Expression Persistance
+// <id> ccl_e_persistance_0
+#define EXPRESSION_PERSISTANCE_0 ""
+
+// <s> Logic Persistance
+// <id> ccl_l_persistance_0
+#define LOGIC_PERSISTANCE_0 ""
+
+// </hidden>
+
+// <e> Lookup Table Control 1
+// <i> Enable and setup the lookup table module 1
+// <id> ccl_arch_lutctrl1
+#ifndef CONF_CCL_LUTCTRL_EN_1
+#define CONF_CCL_LUTCTRL_EN_1 0
+#endif
+
+// <o> Truth Table <0x00-0xFF>
+// <i> Define the value of truth logic according to inputs IN[2:0]
+// <id> ccl_arch_truth_1
+#ifndef CONF_CCL_TRUTH_1
+#define CONF_CCL_TRUTH_1 0x0
+#endif
+
+// <o> Input Source Selection 0
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel0_1
+#ifndef CONF_CCL_INSEL0_1
+#define CONF_CCL_INSEL0_1 0x4
+#endif
+
+// <o> Input Source Selection 1
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel1_1
+#ifndef CONF_CCL_INSEL1_1
+#define CONF_CCL_INSEL1_1 0x4
+#endif
+
+// <o> Input Source Selection 2
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel2_1
+#ifndef CONF_CCL_INSEL2_1
+#define CONF_CCL_INSEL2_1 0x4
+#endif
+
+// <q> Edge detector enable
+// <id> ccl_arch_edgesel_1
+#ifndef CONF_CCL_EDGESEL_1
+#define CONF_CCL_EDGESEL_1 0
+#endif
+
+// <o> Output Filter
+// <0x0=> Disabled
+// <0x1=> Synchronizer Enabled
+// <0x2=> Filter Enabled
+// <id> ccl_arch_filtsel_1
+#ifndef CONF_CCL_FILTSEL_1
+#define CONF_CCL_FILTSEL_1 0x0
+#endif
+
+// <h> Event settings 1
+
+// <q> Event output enable
+// <id> ccl_arch_luteo_1
+#ifndef CONF_CCL_LUTEO_1
+#define CONF_CCL_LUTEO_1 0
+#endif
+
+// <q> Event input enable
+// <id> ccl_arch_lutei_1
+#ifndef CONF_CCL_LUTEI_1
+#define CONF_CCL_LUTEI_1 0
+#endif
+
+// <q> Event input invert
+// <id> ccl_arch_invei_1
+#ifndef CONF_CCL_INVEI_1
+#define CONF_CCL_INVEI_1 0
+#endif
+
+// </h>
+
+// </e>
+
+// <hidden> Persistance settings 1
+
+// <s> Expression Persistance
+// <id> ccl_e_persistance_1
+#define EXPRESSION_PERSISTANCE_1 ""
+
+// <s> Logic Persistance
+// <id> ccl_l_persistance_1
+#define LOGIC_PERSISTANCE_1 ""
+
+// </hidden>
+
+// <e> Lookup Table Control 2
+// <i> Enable and setup the lookup table module 2
+// <id> ccl_arch_lutctrl2
+#ifndef CONF_CCL_LUTCTRL_EN_2
+#define CONF_CCL_LUTCTRL_EN_2 1
+#endif
+
+// <o> Truth Table <0x00-0xFF>
+// <i> Define the value of truth logic according to inputs IN[2:0]
+// <id> ccl_arch_truth_2
+#ifndef CONF_CCL_TRUTH_2
+#define CONF_CCL_TRUTH_2 0x96
+#endif
+
+// <o> Input Source Selection 0
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel0_2
+#ifndef CONF_CCL_INSEL0_2
+#define CONF_CCL_INSEL0_2 0x4
+#endif
+
+// <o> Input Source Selection 1
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel1_2
+#ifndef CONF_CCL_INSEL1_2
+#define CONF_CCL_INSEL1_2 0x4
+#endif
+
+// <o> Input Source Selection 2
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel2_2
+#ifndef CONF_CCL_INSEL2_2
+#define CONF_CCL_INSEL2_2 0x4
+#endif
+
+// <q> Edge detector enable
+// <id> ccl_arch_edgesel_2
+#ifndef CONF_CCL_EDGESEL_2
+#define CONF_CCL_EDGESEL_2 0
+#endif
+
+// <o> Output Filter
+// <0x0=> Disabled
+// <0x1=> Synchronizer Enabled
+// <0x2=> Filter Enabled
+// <id> ccl_arch_filtsel_2
+#ifndef CONF_CCL_FILTSEL_2
+#define CONF_CCL_FILTSEL_2 0x0
+#endif
+
+// <h> Event settings 2
+
+// <q> Event output enable
+// <id> ccl_arch_luteo_2
+#ifndef CONF_CCL_LUTEO_2
+#define CONF_CCL_LUTEO_2 1
+#endif
+
+// <q> Event input enable
+// <id> ccl_arch_lutei_2
+#ifndef CONF_CCL_LUTEI_2
+#define CONF_CCL_LUTEI_2 0
+#endif
+
+// <q> Event input invert
+// <id> ccl_arch_invei_2
+#ifndef CONF_CCL_INVEI_2
+#define CONF_CCL_INVEI_2 0
+#endif
+
+// </h>
+
+// </e>
+
+// <hidden> Persistance settings 2
+
+// <s> Expression Persistance
+// <id> ccl_e_persistance_2
+#define EXPRESSION_PERSISTANCE_2 ""
+
+// <s> Logic Persistance
+// <id> ccl_l_persistance_2
+#define LOGIC_PERSISTANCE_2 ""
+
+// </hidden>
+
+// <e> Lookup Table Control 3
+// <i> Enable and setup the lookup table module 3
+// <id> ccl_arch_lutctrl3
+#ifndef CONF_CCL_LUTCTRL_EN_3
+#define CONF_CCL_LUTCTRL_EN_3 0
+#endif
+
+// <o> Truth Table <0x00-0xFF>
+// <i> Define the value of truth logic according to inputs IN[2:0]
+// <id> ccl_arch_truth_3
+#ifndef CONF_CCL_TRUTH_3
+#define CONF_CCL_TRUTH_3 0x0
+#endif
+
+// <o> Input Source Selection 0
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel0_3
+#ifndef CONF_CCL_INSEL0_3
+#define CONF_CCL_INSEL0_3 0x4
+#endif
+
+// <o> Input Source Selection 1
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel1_3
+#ifndef CONF_CCL_INSEL1_3
+#define CONF_CCL_INSEL1_3 0x4
+#endif
+
+// <o> Input Source Selection 2
+// <0x0=> Masked input
+// <0x1=> Feedback input source
+// <0x2=> Linked LookUpTable input source
+// <0x3=> Event input source
+// <0x4=> IO pin input source
+// <0x5=> AC input source
+// <0x6=> TC input source
+// <0x7=> Alternative TC input source
+// <0x8=> TCC input source
+// <0x9=> SERCOM input source
+// <id> ccl_arch_insel2_3
+#ifndef CONF_CCL_INSEL2_3
+#define CONF_CCL_INSEL2_3 0x4
+#endif
+
+// <q> Edge detector enable
+// <id> ccl_arch_edgesel_3
+#ifndef CONF_CCL_EDGESEL_3
+#define CONF_CCL_EDGESEL_3 0
+#endif
+
+// <o> Output Filter
+// <0x0=> Disabled
+// <0x1=> Synchronizer Enabled
+// <0x2=> Filter Enabled
+// <id> ccl_arch_filtsel_3
+#ifndef CONF_CCL_FILTSEL_3
+#define CONF_CCL_FILTSEL_3 0x0
+#endif
+
+// <h> Event settings 3
+
+// <q> Event output enable
+// <id> ccl_arch_luteo_3
+#ifndef CONF_CCL_LUTEO_3
+#define CONF_CCL_LUTEO_3 0
+#endif
+
+// <q> Event input enable
+// <id> ccl_arch_lutei_3
+#ifndef CONF_CCL_LUTEI_3
+#define CONF_CCL_LUTEI_3 0
+#endif
+
+// <q> Event input invert
+// <id> ccl_arch_invei_3
+#ifndef CONF_CCL_INVEI_3
+#define CONF_CCL_INVEI_3 0
+#endif
+
+// </h>
+
+// </e>
+
+// <hidden> Persistance settings 3
+
+// <s> Expression Persistance
+// <id> ccl_e_persistance_3
+#define EXPRESSION_PERSISTANCE_3 ""
+
+// <s> Logic Persistance
+// <id> ccl_l_persistance_3
+#define LOGIC_PERSISTANCE_3 ""
+
+// </hidden>
+
+// <e> Advanced configurations
+// <id> ccl_arch_advanced_settings
+#ifndef CONF_CCL_ADVANCED
+#define CONF_CCL_ADVANCED 0
+#endif
+
+// <q> Run in Standby
+// <id> ccl_arch_runstdby
+#ifndef CONF_CCL_RUNSTDBY
+#define CONF_CCL_RUNSTDBY 0
+#endif
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_CCL_CONFIG_H

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_cmcc_config.h

@@ -0,0 +1,54 @@
+/* Auto-generated config file hpl_cmcc_config.h */
+#ifndef HPL_CMCC_CONFIG_H
+#define HPL_CMCC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic Configuration
+
+// <q> Cache enable
+//<i> Defines the cache should be enabled or not.
+// <id> cmcc_enable
+#ifndef CONF_CMCC_ENABLE
+#define CONF_CMCC_ENABLE 0x0
+#endif
+
+// <o> Cache Size
+//<i> Defines the cache memory size to be configured.
+// <0x0=>1 KB
+// <0x1=>2 KB
+// <0x2=>4 KB
+// <id> cache_size
+#ifndef CONF_CMCC_CACHE_SIZE
+#define CONF_CMCC_CACHE_SIZE 0x2
+#endif
+
+// <e> Advanced Configuration
+// <id> cmcc_advanced_configuration
+// <q> Data cache disable
+//<i> Defines the data cache should be disabled or not.
+// <id> cmcc_data_cache_disable
+#ifndef CONF_CMCC_DATA_CACHE_DISABLE
+#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
+#endif
+
+// <q> Instruction cache disable
+//<i> Defines the Instruction cache should be disabled or not.
+// <id> cmcc_inst_cache_disable
+#ifndef CONF_CMCC_INST_CACHE_DISABLE
+#define CONF_CMCC_INST_CACHE_DISABLE 0x0
+#endif
+
+// <q> Clock Gating disable
+//<i> Defines the clock gating should be disabled or not.
+// <id> cmcc_clock_gating_disable
+#ifndef CONF_CMCC_CLK_GATING_DISABLE
+#define CONF_CMCC_CLK_GATING_DISABLE 0x0
+#endif
+
+// </e>
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_CMCC_CONFIG_H

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_eic_config.h

@@ -0,0 +1,913 @@
+/* Auto-generated config file hpl_eic_config.h */
+#ifndef HPL_EIC_CONFIG_H
+#define HPL_EIC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic Settings
+// <o> Clock Selection
+// <i> Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or
+// <i> either by CLK_ULP32K when power consumption is the priority.
+// <0x0=> Clocked by GCLK
+// <0x1=> Clocked by ULPOSC32K
+// <id> eic_arch_cksel
+#ifndef CONF_EIC_CKSEL
+#define CONF_EIC_CKSEL 0
+#endif
+
+// <o> Pin Sampler frequency selection
+// <i> Indicates the sampling rate of the EXTINT pin.
+// <0x0=> The sampling rate is EIC clock
+// <0x1=> The sampling rate is the prescaled clock
+// <id> eic_arch_tickon
+#ifndef CONF_EIC_TICKON
+#define CONF_EIC_TICKON 0
+#endif
+
+// </h>
+
+// <e> Non-Maskable Interrupt Control
+// <id> eic_arch_nmi_ctrl
+#ifndef CONF_EIC_ENABLE_NMI_CTRL
+#define CONF_EIC_ENABLE_NMI_CTRL 0
+#endif
+
+// <q> Non-Maskable Interrupt Filter Enable
+// <i> Indicates whether the mon-maskable interrupt filter is enabled or not
+// <id> eic_arch_nmifilten
+#ifndef CONF_EIC_NMIFILTEN
+#define CONF_EIC_NMIFILTEN 0
+#endif
+
+// <y> Non-Maskable Interrupt Sense
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines non-maskable interrupt sense
+// <id> eic_arch_nmisense
+#ifndef CONF_EIC_NMISENSE
+#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> Asynchronous Edge Detection Mode
+// <i> Indicates the interrupt detection mode operated synchronously or asynchronousl
+// <id> eic_arch_nmiasynch
+#ifndef CONF_EIC_NMIASYNCH
+#define CONF_EIC_NMIASYNCH 0
+#endif
+// </e>
+
+// <e> Interrupt 0 Settings
+// <id> eic_arch_enable_irq_setting0
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING0
+#define CONF_EIC_ENABLE_IRQ_SETTING0 0
+#endif
+
+// <q> External Interrupt 0 Filter Enable
+// <i> Indicates whether the external interrupt 0 filter is enabled or not
+// <id> eic_arch_filten0
+#ifndef CONF_EIC_FILTEN0
+#define CONF_EIC_FILTEN0 0
+#endif
+
+// <q> External Interrupt 0 Debounce Enable
+// <i> Indicates whether the external interrupt 0 debounce is enabled or not
+// <id> eic_arch_debounce_enable0
+#ifndef CONF_EIC_DEBOUNCE_ENABLE0
+#define CONF_EIC_DEBOUNCE_ENABLE0 0
+#endif
+
+// <q> External Interrupt 0 Event Output Enable
+// <i> Indicates whether the external interrupt 0 event output is enabled or not
+// <id> eic_arch_extinteo0
+#ifndef CONF_EIC_EXTINTEO0
+#define CONF_EIC_EXTINTEO0 0
+#endif
+
+// <y> Input 0 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense0
+#ifndef CONF_EIC_SENSE0
+#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 0 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch0
+#ifndef CONF_EIC_ASYNCH0
+#define CONF_EIC_ASYNCH0 0
+#endif
+
+// </e>
+
+// <e> Interrupt 1 Settings
+// <id> eic_arch_enable_irq_setting1
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING1
+#define CONF_EIC_ENABLE_IRQ_SETTING1 0
+#endif
+
+// <q> External Interrupt 1 Filter Enable
+// <i> Indicates whether the external interrupt 1 filter is enabled or not
+// <id> eic_arch_filten1
+#ifndef CONF_EIC_FILTEN1
+#define CONF_EIC_FILTEN1 0
+#endif
+
+// <q> External Interrupt 1 Debounce Enable
+// <i> Indicates whether the external interrupt 1 debounce is enabled or not
+// <id> eic_arch_debounce_enable1
+#ifndef CONF_EIC_DEBOUNCE_ENABLE1
+#define CONF_EIC_DEBOUNCE_ENABLE1 0
+#endif
+
+// <q> External Interrupt 1 Event Output Enable
+// <i> Indicates whether the external interrupt 1 event output is enabled or not
+// <id> eic_arch_extinteo1
+#ifndef CONF_EIC_EXTINTEO1
+#define CONF_EIC_EXTINTEO1 0
+#endif
+
+// <y> Input 1 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense1
+#ifndef CONF_EIC_SENSE1
+#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 1 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch1
+#ifndef CONF_EIC_ASYNCH1
+#define CONF_EIC_ASYNCH1 0
+#endif
+
+// </e>
+
+// <e> Interrupt 2 Settings
+// <id> eic_arch_enable_irq_setting2
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING2
+#define CONF_EIC_ENABLE_IRQ_SETTING2 1
+#endif
+
+// <q> External Interrupt 2 Filter Enable
+// <i> Indicates whether the external interrupt 2 filter is enabled or not
+// <id> eic_arch_filten2
+#ifndef CONF_EIC_FILTEN2
+#define CONF_EIC_FILTEN2 0
+#endif
+
+// <q> External Interrupt 2 Debounce Enable
+// <i> Indicates whether the external interrupt 2 debounce is enabled or not
+// <id> eic_arch_debounce_enable2
+#ifndef CONF_EIC_DEBOUNCE_ENABLE2
+#define CONF_EIC_DEBOUNCE_ENABLE2 0
+#endif
+
+// <q> External Interrupt 2 Event Output Enable
+// <i> Indicates whether the external interrupt 2 event output is enabled or not
+// <id> eic_arch_extinteo2
+#ifndef CONF_EIC_EXTINTEO2
+#define CONF_EIC_EXTINTEO2 1
+#endif
+
+// <y> Input 2 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense2
+#ifndef CONF_EIC_SENSE2
+#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_FALL_Val
+#endif
+
+// <q> External Interrupt 2 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch2
+#ifndef CONF_EIC_ASYNCH2
+#define CONF_EIC_ASYNCH2 1
+#endif
+
+// </e>
+
+// <e> Interrupt 3 Settings
+// <id> eic_arch_enable_irq_setting3
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING3
+#define CONF_EIC_ENABLE_IRQ_SETTING3 0
+#endif
+
+// <q> External Interrupt 3 Filter Enable
+// <i> Indicates whether the external interrupt 3 filter is enabled or not
+// <id> eic_arch_filten3
+#ifndef CONF_EIC_FILTEN3
+#define CONF_EIC_FILTEN3 0
+#endif
+
+// <q> External Interrupt 3 Debounce Enable
+// <i> Indicates whether the external interrupt 3 debounce is enabled or not
+// <id> eic_arch_debounce_enable3
+#ifndef CONF_EIC_DEBOUNCE_ENABLE3
+#define CONF_EIC_DEBOUNCE_ENABLE3 0
+#endif
+
+// <q> External Interrupt 3 Event Output Enable
+// <i> Indicates whether the external interrupt 3 event output is enabled or not
+// <id> eic_arch_extinteo3
+#ifndef CONF_EIC_EXTINTEO3
+#define CONF_EIC_EXTINTEO3 0
+#endif
+
+// <y> Input 3 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense3
+#ifndef CONF_EIC_SENSE3
+#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 3 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch3
+#ifndef CONF_EIC_ASYNCH3
+#define CONF_EIC_ASYNCH3 0
+#endif
+
+// </e>
+
+// <e> Interrupt 4 Settings
+// <id> eic_arch_enable_irq_setting4
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING4
+#define CONF_EIC_ENABLE_IRQ_SETTING4 0
+#endif
+
+// <q> External Interrupt 4 Filter Enable
+// <i> Indicates whether the external interrupt 4 filter is enabled or not
+// <id> eic_arch_filten4
+#ifndef CONF_EIC_FILTEN4
+#define CONF_EIC_FILTEN4 0
+#endif
+
+// <q> External Interrupt 4 Debounce Enable
+// <i> Indicates whether the external interrupt 4 debounce is enabled or not
+// <id> eic_arch_debounce_enable4
+#ifndef CONF_EIC_DEBOUNCE_ENABLE4
+#define CONF_EIC_DEBOUNCE_ENABLE4 0
+#endif
+
+// <q> External Interrupt 4 Event Output Enable
+// <i> Indicates whether the external interrupt 4 event output is enabled or not
+// <id> eic_arch_extinteo4
+#ifndef CONF_EIC_EXTINTEO4
+#define CONF_EIC_EXTINTEO4 0
+#endif
+
+// <y> Input 4 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense4
+#ifndef CONF_EIC_SENSE4
+#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 4 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch4
+#ifndef CONF_EIC_ASYNCH4
+#define CONF_EIC_ASYNCH4 0
+#endif
+
+// </e>
+
+// <e> Interrupt 5 Settings
+// <id> eic_arch_enable_irq_setting5
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING5
+#define CONF_EIC_ENABLE_IRQ_SETTING5 0
+#endif
+
+// <q> External Interrupt 5 Filter Enable
+// <i> Indicates whether the external interrupt 5 filter is enabled or not
+// <id> eic_arch_filten5
+#ifndef CONF_EIC_FILTEN5
+#define CONF_EIC_FILTEN5 0
+#endif
+
+// <q> External Interrupt 5 Debounce Enable
+// <i> Indicates whether the external interrupt 5 debounce is enabled or not
+// <id> eic_arch_debounce_enable5
+#ifndef CONF_EIC_DEBOUNCE_ENABLE5
+#define CONF_EIC_DEBOUNCE_ENABLE5 0
+#endif
+
+// <q> External Interrupt 5 Event Output Enable
+// <i> Indicates whether the external interrupt 5 event output is enabled or not
+// <id> eic_arch_extinteo5
+#ifndef CONF_EIC_EXTINTEO5
+#define CONF_EIC_EXTINTEO5 0
+#endif
+
+// <y> Input 5 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense5
+#ifndef CONF_EIC_SENSE5
+#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 5 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch5
+#ifndef CONF_EIC_ASYNCH5
+#define CONF_EIC_ASYNCH5 0
+#endif
+
+// </e>
+
+// <e> Interrupt 6 Settings
+// <id> eic_arch_enable_irq_setting6
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING6
+#define CONF_EIC_ENABLE_IRQ_SETTING6 0
+#endif
+
+// <q> External Interrupt 6 Filter Enable
+// <i> Indicates whether the external interrupt 6 filter is enabled or not
+// <id> eic_arch_filten6
+#ifndef CONF_EIC_FILTEN6
+#define CONF_EIC_FILTEN6 0
+#endif
+
+// <q> External Interrupt 6 Debounce Enable
+// <i> Indicates whether the external interrupt 6 debounce is enabled or not
+// <id> eic_arch_debounce_enable6
+#ifndef CONF_EIC_DEBOUNCE_ENABLE6
+#define CONF_EIC_DEBOUNCE_ENABLE6 0
+#endif
+
+// <q> External Interrupt 6 Event Output Enable
+// <i> Indicates whether the external interrupt 6 event output is enabled or not
+// <id> eic_arch_extinteo6
+#ifndef CONF_EIC_EXTINTEO6
+#define CONF_EIC_EXTINTEO6 0
+#endif
+
+// <y> Input 6 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense6
+#ifndef CONF_EIC_SENSE6
+#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 6 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch6
+#ifndef CONF_EIC_ASYNCH6
+#define CONF_EIC_ASYNCH6 0
+#endif
+
+// </e>
+
+// <e> Interrupt 7 Settings
+// <id> eic_arch_enable_irq_setting7
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING7
+#define CONF_EIC_ENABLE_IRQ_SETTING7 0
+#endif
+
+// <q> External Interrupt 7 Filter Enable
+// <i> Indicates whether the external interrupt 7 filter is enabled or not
+// <id> eic_arch_filten7
+#ifndef CONF_EIC_FILTEN7
+#define CONF_EIC_FILTEN7 0
+#endif
+
+// <q> External Interrupt 7 Debounce Enable
+// <i> Indicates whether the external interrupt 7 debounce is enabled or not
+// <id> eic_arch_debounce_enable7
+#ifndef CONF_EIC_DEBOUNCE_ENABLE7
+#define CONF_EIC_DEBOUNCE_ENABLE7 0
+#endif
+
+// <q> External Interrupt 7 Event Output Enable
+// <i> Indicates whether the external interrupt 7 event output is enabled or not
+// <id> eic_arch_extinteo7
+#ifndef CONF_EIC_EXTINTEO7
+#define CONF_EIC_EXTINTEO7 0
+#endif
+
+// <y> Input 7 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense7
+#ifndef CONF_EIC_SENSE7
+#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 7 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch7
+#ifndef CONF_EIC_ASYNCH7
+#define CONF_EIC_ASYNCH7 0
+#endif
+
+// </e>
+
+// <e> Interrupt 8 Settings
+// <id> eic_arch_enable_irq_setting8
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING8
+#define CONF_EIC_ENABLE_IRQ_SETTING8 0
+#endif
+
+// <q> External Interrupt 8 Filter Enable
+// <i> Indicates whether the external interrupt 8 filter is enabled or not
+// <id> eic_arch_filten8
+#ifndef CONF_EIC_FILTEN8
+#define CONF_EIC_FILTEN8 0
+#endif
+
+// <q> External Interrupt 8 Debounce Enable
+// <i> Indicates whether the external interrupt 8 debounce is enabled or not
+// <id> eic_arch_debounce_enable8
+#ifndef CONF_EIC_DEBOUNCE_ENABLE8
+#define CONF_EIC_DEBOUNCE_ENABLE8 0
+#endif
+
+// <q> External Interrupt 8 Event Output Enable
+// <i> Indicates whether the external interrupt 8 event output is enabled or not
+// <id> eic_arch_extinteo8
+#ifndef CONF_EIC_EXTINTEO8
+#define CONF_EIC_EXTINTEO8 0
+#endif
+
+// <y> Input 8 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense8
+#ifndef CONF_EIC_SENSE8
+#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 8 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch8
+#ifndef CONF_EIC_ASYNCH8
+#define CONF_EIC_ASYNCH8 0
+#endif
+
+// </e>
+
+// <e> Interrupt 9 Settings
+// <id> eic_arch_enable_irq_setting9
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING9
+#define CONF_EIC_ENABLE_IRQ_SETTING9 0
+#endif
+
+// <q> External Interrupt 9 Filter Enable
+// <i> Indicates whether the external interrupt 9 filter is enabled or not
+// <id> eic_arch_filten9
+#ifndef CONF_EIC_FILTEN9
+#define CONF_EIC_FILTEN9 0
+#endif
+
+// <q> External Interrupt 9 Debounce Enable
+// <i> Indicates whether the external interrupt 9 debounce is enabled or not
+// <id> eic_arch_debounce_enable9
+#ifndef CONF_EIC_DEBOUNCE_ENABLE9
+#define CONF_EIC_DEBOUNCE_ENABLE9 0
+#endif
+
+// <q> External Interrupt 9 Event Output Enable
+// <i> Indicates whether the external interrupt 9 event output is enabled or not
+// <id> eic_arch_extinteo9
+#ifndef CONF_EIC_EXTINTEO9
+#define CONF_EIC_EXTINTEO9 0
+#endif
+
+// <y> Input 9 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense9
+#ifndef CONF_EIC_SENSE9
+#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 9 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch9
+#ifndef CONF_EIC_ASYNCH9
+#define CONF_EIC_ASYNCH9 0
+#endif
+
+// </e>
+
+// <e> Interrupt 10 Settings
+// <id> eic_arch_enable_irq_setting10
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING10
+#define CONF_EIC_ENABLE_IRQ_SETTING10 0
+#endif
+
+// <q> External Interrupt 10 Filter Enable
+// <i> Indicates whether the external interrupt 10 filter is enabled or not
+// <id> eic_arch_filten10
+#ifndef CONF_EIC_FILTEN10
+#define CONF_EIC_FILTEN10 0
+#endif
+
+// <q> External Interrupt 10 Debounce Enable
+// <i> Indicates whether the external interrupt 10 debounce is enabled or not
+// <id> eic_arch_debounce_enable10
+#ifndef CONF_EIC_DEBOUNCE_ENABLE10
+#define CONF_EIC_DEBOUNCE_ENABLE10 0
+#endif
+
+// <q> External Interrupt 10 Event Output Enable
+// <i> Indicates whether the external interrupt 10 event output is enabled or not
+// <id> eic_arch_extinteo10
+#ifndef CONF_EIC_EXTINTEO10
+#define CONF_EIC_EXTINTEO10 0
+#endif
+
+// <y> Input 10 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense10
+#ifndef CONF_EIC_SENSE10
+#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 10 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch10
+#ifndef CONF_EIC_ASYNCH10
+#define CONF_EIC_ASYNCH10 0
+#endif
+
+// </e>
+
+// <e> Interrupt 11 Settings
+// <id> eic_arch_enable_irq_setting11
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING11
+#define CONF_EIC_ENABLE_IRQ_SETTING11 0
+#endif
+
+// <q> External Interrupt 11 Filter Enable
+// <i> Indicates whether the external interrupt 11 filter is enabled or not
+// <id> eic_arch_filten11
+#ifndef CONF_EIC_FILTEN11
+#define CONF_EIC_FILTEN11 0
+#endif
+
+// <q> External Interrupt 11 Debounce Enable
+// <i> Indicates whether the external interrupt 11 debounce is enabled or not
+// <id> eic_arch_debounce_enable11
+#ifndef CONF_EIC_DEBOUNCE_ENABLE11
+#define CONF_EIC_DEBOUNCE_ENABLE11 0
+#endif
+
+// <q> External Interrupt 11 Event Output Enable
+// <i> Indicates whether the external interrupt 11 event output is enabled or not
+// <id> eic_arch_extinteo11
+#ifndef CONF_EIC_EXTINTEO11
+#define CONF_EIC_EXTINTEO11 0
+#endif
+
+// <y> Input 11 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense11
+#ifndef CONF_EIC_SENSE11
+#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 11 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch11
+#ifndef CONF_EIC_ASYNCH11
+#define CONF_EIC_ASYNCH11 0
+#endif
+
+// </e>
+
+// <e> Interrupt 12 Settings
+// <id> eic_arch_enable_irq_setting12
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING12
+#define CONF_EIC_ENABLE_IRQ_SETTING12 0
+#endif
+
+// <q> External Interrupt 12 Filter Enable
+// <i> Indicates whether the external interrupt 12 filter is enabled or not
+// <id> eic_arch_filten12
+#ifndef CONF_EIC_FILTEN12
+#define CONF_EIC_FILTEN12 0
+#endif
+
+// <q> External Interrupt 12 Debounce Enable
+// <i> Indicates whether the external interrupt 12 debounce is enabled or not
+// <id> eic_arch_debounce_enable12
+#ifndef CONF_EIC_DEBOUNCE_ENABLE12
+#define CONF_EIC_DEBOUNCE_ENABLE12 0
+#endif
+
+// <q> External Interrupt 12 Event Output Enable
+// <i> Indicates whether the external interrupt 12 event output is enabled or not
+// <id> eic_arch_extinteo12
+#ifndef CONF_EIC_EXTINTEO12
+#define CONF_EIC_EXTINTEO12 0
+#endif
+
+// <y> Input 12 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense12
+#ifndef CONF_EIC_SENSE12
+#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 12 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch12
+#ifndef CONF_EIC_ASYNCH12
+#define CONF_EIC_ASYNCH12 0
+#endif
+
+// </e>
+
+// <e> Interrupt 13 Settings
+// <id> eic_arch_enable_irq_setting13
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING13
+#define CONF_EIC_ENABLE_IRQ_SETTING13 0
+#endif
+
+// <q> External Interrupt 13 Filter Enable
+// <i> Indicates whether the external interrupt 13 filter is enabled or not
+// <id> eic_arch_filten13
+#ifndef CONF_EIC_FILTEN13
+#define CONF_EIC_FILTEN13 0
+#endif
+
+// <q> External Interrupt 13 Debounce Enable
+// <i> Indicates whether the external interrupt 13 debounce is enabled or not
+// <id> eic_arch_debounce_enable13
+#ifndef CONF_EIC_DEBOUNCE_ENABLE13
+#define CONF_EIC_DEBOUNCE_ENABLE13 0
+#endif
+
+// <q> External Interrupt 13 Event Output Enable
+// <i> Indicates whether the external interrupt 13 event output is enabled or not
+// <id> eic_arch_extinteo13
+#ifndef CONF_EIC_EXTINTEO13
+#define CONF_EIC_EXTINTEO13 0
+#endif
+
+// <y> Input 13 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense13
+#ifndef CONF_EIC_SENSE13
+#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 13 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch13
+#ifndef CONF_EIC_ASYNCH13
+#define CONF_EIC_ASYNCH13 0
+#endif
+
+// </e>
+
+// <e> Interrupt 14 Settings
+// <id> eic_arch_enable_irq_setting14
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING14
+#define CONF_EIC_ENABLE_IRQ_SETTING14 1
+#endif
+
+// <q> External Interrupt 14 Filter Enable
+// <i> Indicates whether the external interrupt 14 filter is enabled or not
+// <id> eic_arch_filten14
+#ifndef CONF_EIC_FILTEN14
+#define CONF_EIC_FILTEN14 1
+#endif
+
+// <q> External Interrupt 14 Debounce Enable
+// <i> Indicates whether the external interrupt 14 debounce is enabled or not
+// <id> eic_arch_debounce_enable14
+#ifndef CONF_EIC_DEBOUNCE_ENABLE14
+#define CONF_EIC_DEBOUNCE_ENABLE14 0
+#endif
+
+// <q> External Interrupt 14 Event Output Enable
+// <i> Indicates whether the external interrupt 14 event output is enabled or not
+// <id> eic_arch_extinteo14
+#ifndef CONF_EIC_EXTINTEO14
+#define CONF_EIC_EXTINTEO14 0
+#endif
+
+// <y> Input 14 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense14
+#ifndef CONF_EIC_SENSE14
+#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_FALL_Val
+#endif
+
+// <q> External Interrupt 14 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch14
+#ifndef CONF_EIC_ASYNCH14
+#define CONF_EIC_ASYNCH14 0
+#endif
+
+// </e>
+
+// <e> Interrupt 15 Settings
+// <id> eic_arch_enable_irq_setting15
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING15
+#define CONF_EIC_ENABLE_IRQ_SETTING15 1
+#endif
+
+// <q> External Interrupt 15 Filter Enable
+// <i> Indicates whether the external interrupt 15 filter is enabled or not
+// <id> eic_arch_filten15
+#ifndef CONF_EIC_FILTEN15
+#define CONF_EIC_FILTEN15 1
+#endif
+
+// <q> External Interrupt 15 Debounce Enable
+// <i> Indicates whether the external interrupt 15 debounce is enabled or not
+// <id> eic_arch_debounce_enable15
+#ifndef CONF_EIC_DEBOUNCE_ENABLE15
+#define CONF_EIC_DEBOUNCE_ENABLE15 0
+#endif
+
+// <q> External Interrupt 15 Event Output Enable
+// <i> Indicates whether the external interrupt 15 event output is enabled or not
+// <id> eic_arch_extinteo15
+#ifndef CONF_EIC_EXTINTEO15
+#define CONF_EIC_EXTINTEO15 0
+#endif
+
+// <y> Input 15 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense15
+#ifndef CONF_EIC_SENSE15
+#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_FALL_Val
+#endif
+
+// <q> External Interrupt 15 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch15
+#ifndef CONF_EIC_ASYNCH15
+#define CONF_EIC_ASYNCH15 0
+#endif
+
+// </e>
+
+// <h> Debouncer 0 Settings
+// <o> Debouncer Frequency Selection
+// <0x0=>Divided by 2
+// <0x1=>Divided by 4
+// <0x2=>Divided by 8
+// <0x3=>Divided by 16
+// <0x4=>Divided by 32
+// <0x5=>Divided by 64
+// <0x6=>Divided by 128
+// <0x7=>Divided by 256
+// <i> Select the debouncer low frequency clock for pins
+
+//   <i> EXTINT[7:0].
+
+// <id> eic_arch_prescaler0
+#ifndef CONF_EIC_DPRESCALER0
+#define CONF_EIC_DPRESCALER0 EIC_DPRESCALER_PRESCALER0(0x0)
+#endif
+
+// <o> Low frequency samples
+// <0x0=>3
+// <0x1=>7
+// <i> Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from
+// <i> current pin state to next pin state in synchronous debouncing mode.
+// <id> eic_arch_states0
+#ifndef CONF_EIC_STATES0
+#define CONF_EIC_STATES0 0x0
+#endif
+
+// </h>
+
+// <h> Debouncer 1 Settings
+// <o> Debouncer Frequency Selection
+// <0x0=>Divided by 2
+// <0x1=>Divided by 4
+// <0x2=>Divided by 8
+// <0x3=>Divided by 16
+// <0x4=>Divided by 32
+// <0x5=>Divided by 64
+// <0x6=>Divided by 128
+// <0x7=>Divided by 256
+// <i> Select the debouncer low frequency clock for pins
+
+//   <i> EXTINT[15:8].
+
+// <id> eic_arch_prescaler1
+#ifndef CONF_EIC_DPRESCALER1
+#define CONF_EIC_DPRESCALER1 EIC_DPRESCALER_PRESCALER1(0x0)
+#endif
+
+// <o> Low frequency samples
+// <0x0=>3
+// <0x1=>7
+// <i> Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from
+// <i> current pin state to next pin state in synchronous debouncing mode.
+// <id> eic_arch_states1
+#ifndef CONF_EIC_STATES1
+#define CONF_EIC_STATES1 0x0
+#endif
+
+// </h>
+
+#define CONFIG_EIC_EXTINT_MAP {2, PIN_PA02}, {7, PIN_PA07}, {14, PIN_PB30}, {15, PIN_PB31},
+
+// <<< end of configuration section >>>
+
+#endif // HPL_EIC_CONFIG_H

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_gclk_config.h

@@ -0,0 +1,920 @@
+/* Auto-generated config file hpl_gclk_config.h */
+#ifndef HPL_GCLK_CONFIG_H
+#define HPL_GCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> Generic clock generator 0 configuration
+// <i> Indicates whether generic clock 0 configuration is enabled or not
+// <id> enable_gclk_gen_0
+#ifndef CONF_GCLK_GENERATOR_0_CONFIG
+#define CONF_GCLK_GENERATOR_0_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 0 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 0
+// <id> gclk_gen_0_oscillator
+#ifndef CONF_GCLK_GEN_0_SOURCE
+#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_0_runstdby
+#ifndef CONF_GCLK_GEN_0_RUNSTDBY
+#define CONF_GCLK_GEN_0_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_0_div_sel
+#ifndef CONF_GCLK_GEN_0_DIVSEL
+#define CONF_GCLK_GEN_0_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_0_oe
+#ifndef CONF_GCLK_GEN_0_OE
+#define CONF_GCLK_GEN_0_OE 1
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_0_oov
+#ifndef CONF_GCLK_GEN_0_OOV
+#define CONF_GCLK_GEN_0_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_0_idc
+#ifndef CONF_GCLK_GEN_0_IDC
+#define CONF_GCLK_GEN_0_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_0_enable
+#ifndef CONF_GCLK_GEN_0_GENEN
+#define CONF_GCLK_GEN_0_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 0 division <0x0000-0xFFFF>
+// <id> gclk_gen_0_div
+#ifndef CONF_GCLK_GEN_0_DIV
+#define CONF_GCLK_GEN_0_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 1 configuration
+// <i> Indicates whether generic clock 1 configuration is enabled or not
+// <id> enable_gclk_gen_1
+#ifndef CONF_GCLK_GENERATOR_1_CONFIG
+#define CONF_GCLK_GENERATOR_1_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 1 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 1
+// <id> gclk_gen_1_oscillator
+#ifndef CONF_GCLK_GEN_1_SOURCE
+#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_1_runstdby
+#ifndef CONF_GCLK_GEN_1_RUNSTDBY
+#define CONF_GCLK_GEN_1_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_1_div_sel
+#ifndef CONF_GCLK_GEN_1_DIVSEL
+#define CONF_GCLK_GEN_1_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_1_oe
+#ifndef CONF_GCLK_GEN_1_OE
+#define CONF_GCLK_GEN_1_OE 1
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_1_oov
+#ifndef CONF_GCLK_GEN_1_OOV
+#define CONF_GCLK_GEN_1_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_1_idc
+#ifndef CONF_GCLK_GEN_1_IDC
+#define CONF_GCLK_GEN_1_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_1_enable
+#ifndef CONF_GCLK_GEN_1_GENEN
+#define CONF_GCLK_GEN_1_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 1 division <0x0000-0xFFFF>
+// <id> gclk_gen_1_div
+#ifndef CONF_GCLK_GEN_1_DIV
+#define CONF_GCLK_GEN_1_DIV 24
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 2 configuration
+// <i> Indicates whether generic clock 2 configuration is enabled or not
+// <id> enable_gclk_gen_2
+#ifndef CONF_GCLK_GENERATOR_2_CONFIG
+#define CONF_GCLK_GENERATOR_2_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 2 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 2
+// <id> gclk_gen_2_oscillator
+#ifndef CONF_GCLK_GEN_2_SOURCE
+#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSCULP32K
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_2_runstdby
+#ifndef CONF_GCLK_GEN_2_RUNSTDBY
+#define CONF_GCLK_GEN_2_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_2_div_sel
+#ifndef CONF_GCLK_GEN_2_DIVSEL
+#define CONF_GCLK_GEN_2_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_2_oe
+#ifndef CONF_GCLK_GEN_2_OE
+#define CONF_GCLK_GEN_2_OE 1
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_2_oov
+#ifndef CONF_GCLK_GEN_2_OOV
+#define CONF_GCLK_GEN_2_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_2_idc
+#ifndef CONF_GCLK_GEN_2_IDC
+#define CONF_GCLK_GEN_2_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_2_enable
+#ifndef CONF_GCLK_GEN_2_GENEN
+#define CONF_GCLK_GEN_2_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 2 division <0x0000-0xFFFF>
+// <id> gclk_gen_2_div
+#ifndef CONF_GCLK_GEN_2_DIV
+#define CONF_GCLK_GEN_2_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 3 configuration
+// <i> Indicates whether generic clock 3 configuration is enabled or not
+// <id> enable_gclk_gen_3
+#ifndef CONF_GCLK_GENERATOR_3_CONFIG
+#define CONF_GCLK_GENERATOR_3_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 3 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 3
+// <id> gclk_gen_3_oscillator
+#ifndef CONF_GCLK_GEN_3_SOURCE
+#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_3_runstdby
+#ifndef CONF_GCLK_GEN_3_RUNSTDBY
+#define CONF_GCLK_GEN_3_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_3_div_sel
+#ifndef CONF_GCLK_GEN_3_DIVSEL
+#define CONF_GCLK_GEN_3_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_3_oe
+#ifndef CONF_GCLK_GEN_3_OE
+#define CONF_GCLK_GEN_3_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_3_oov
+#ifndef CONF_GCLK_GEN_3_OOV
+#define CONF_GCLK_GEN_3_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_3_idc
+#ifndef CONF_GCLK_GEN_3_IDC
+#define CONF_GCLK_GEN_3_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_3_enable
+#ifndef CONF_GCLK_GEN_3_GENEN
+#define CONF_GCLK_GEN_3_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 3 division <0x0000-0xFFFF>
+// <id> gclk_gen_3_div
+#ifndef CONF_GCLK_GEN_3_DIV
+#define CONF_GCLK_GEN_3_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 4 configuration
+// <i> Indicates whether generic clock 4 configuration is enabled or not
+// <id> enable_gclk_gen_4
+#ifndef CONF_GCLK_GENERATOR_4_CONFIG
+#define CONF_GCLK_GENERATOR_4_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 4 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 4
+// <id> gclk_gen_4_oscillator
+#ifndef CONF_GCLK_GEN_4_SOURCE
+#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_4_runstdby
+#ifndef CONF_GCLK_GEN_4_RUNSTDBY
+#define CONF_GCLK_GEN_4_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_4_div_sel
+#ifndef CONF_GCLK_GEN_4_DIVSEL
+#define CONF_GCLK_GEN_4_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_4_oe
+#ifndef CONF_GCLK_GEN_4_OE
+#define CONF_GCLK_GEN_4_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_4_oov
+#ifndef CONF_GCLK_GEN_4_OOV
+#define CONF_GCLK_GEN_4_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_4_idc
+#ifndef CONF_GCLK_GEN_4_IDC
+#define CONF_GCLK_GEN_4_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_4_enable
+#ifndef CONF_GCLK_GEN_4_GENEN
+#define CONF_GCLK_GEN_4_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 4 division <0x0000-0xFFFF>
+// <id> gclk_gen_4_div
+#ifndef CONF_GCLK_GEN_4_DIV
+#define CONF_GCLK_GEN_4_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 5 configuration
+// <i> Indicates whether generic clock 5 configuration is enabled or not
+// <id> enable_gclk_gen_5
+#ifndef CONF_GCLK_GENERATOR_5_CONFIG
+#define CONF_GCLK_GENERATOR_5_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 5 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 5
+// <id> gclk_gen_5_oscillator
+#ifndef CONF_GCLK_GEN_5_SOURCE
+#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_5_runstdby
+#ifndef CONF_GCLK_GEN_5_RUNSTDBY
+#define CONF_GCLK_GEN_5_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_5_div_sel
+#ifndef CONF_GCLK_GEN_5_DIVSEL
+#define CONF_GCLK_GEN_5_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_5_oe
+#ifndef CONF_GCLK_GEN_5_OE
+#define CONF_GCLK_GEN_5_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_5_oov
+#ifndef CONF_GCLK_GEN_5_OOV
+#define CONF_GCLK_GEN_5_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_5_idc
+#ifndef CONF_GCLK_GEN_5_IDC
+#define CONF_GCLK_GEN_5_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_5_enable
+#ifndef CONF_GCLK_GEN_5_GENEN
+#define CONF_GCLK_GEN_5_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 5 division <0x0000-0xFFFF>
+// <id> gclk_gen_5_div
+#ifndef CONF_GCLK_GEN_5_DIV
+#define CONF_GCLK_GEN_5_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 6 configuration
+// <i> Indicates whether generic clock 6 configuration is enabled or not
+// <id> enable_gclk_gen_6
+#ifndef CONF_GCLK_GENERATOR_6_CONFIG
+#define CONF_GCLK_GENERATOR_6_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 6 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 6
+// <id> gclk_gen_6_oscillator
+#ifndef CONF_GCLK_GEN_6_SOURCE
+#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_6_runstdby
+#ifndef CONF_GCLK_GEN_6_RUNSTDBY
+#define CONF_GCLK_GEN_6_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_6_div_sel
+#ifndef CONF_GCLK_GEN_6_DIVSEL
+#define CONF_GCLK_GEN_6_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_6_oe
+#ifndef CONF_GCLK_GEN_6_OE
+#define CONF_GCLK_GEN_6_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_6_oov
+#ifndef CONF_GCLK_GEN_6_OOV
+#define CONF_GCLK_GEN_6_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_6_idc
+#ifndef CONF_GCLK_GEN_6_IDC
+#define CONF_GCLK_GEN_6_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_6_enable
+#ifndef CONF_GCLK_GEN_6_GENEN
+#define CONF_GCLK_GEN_6_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 6 division <0x0000-0xFFFF>
+// <id> gclk_gen_6_div
+#ifndef CONF_GCLK_GEN_6_DIV
+#define CONF_GCLK_GEN_6_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 7 configuration
+// <i> Indicates whether generic clock 7 configuration is enabled or not
+// <id> enable_gclk_gen_7
+#ifndef CONF_GCLK_GENERATOR_7_CONFIG
+#define CONF_GCLK_GENERATOR_7_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 7 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 7
+// <id> gclk_gen_7_oscillator
+#ifndef CONF_GCLK_GEN_7_SOURCE
+#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_7_runstdby
+#ifndef CONF_GCLK_GEN_7_RUNSTDBY
+#define CONF_GCLK_GEN_7_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_7_div_sel
+#ifndef CONF_GCLK_GEN_7_DIVSEL
+#define CONF_GCLK_GEN_7_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_7_oe
+#ifndef CONF_GCLK_GEN_7_OE
+#define CONF_GCLK_GEN_7_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_7_oov
+#ifndef CONF_GCLK_GEN_7_OOV
+#define CONF_GCLK_GEN_7_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_7_idc
+#ifndef CONF_GCLK_GEN_7_IDC
+#define CONF_GCLK_GEN_7_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_7_enable
+#ifndef CONF_GCLK_GEN_7_GENEN
+#define CONF_GCLK_GEN_7_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 7 division <0x0000-0xFFFF>
+// <id> gclk_gen_7_div
+#ifndef CONF_GCLK_GEN_7_DIV
+#define CONF_GCLK_GEN_7_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 8 configuration
+// <i> Indicates whether generic clock 8 configuration is enabled or not
+// <id> enable_gclk_gen_8
+#ifndef CONF_GCLK_GENERATOR_8_CONFIG
+#define CONF_GCLK_GENERATOR_8_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 8 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 8
+// <id> gclk_gen_8_oscillator
+#ifndef CONF_GCLK_GEN_8_SOURCE
+#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_8_runstdby
+#ifndef CONF_GCLK_GEN_8_RUNSTDBY
+#define CONF_GCLK_GEN_8_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_8_div_sel
+#ifndef CONF_GCLK_GEN_8_DIVSEL
+#define CONF_GCLK_GEN_8_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_8_oe
+#ifndef CONF_GCLK_GEN_8_OE
+#define CONF_GCLK_GEN_8_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_8_oov
+#ifndef CONF_GCLK_GEN_8_OOV
+#define CONF_GCLK_GEN_8_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_8_idc
+#ifndef CONF_GCLK_GEN_8_IDC
+#define CONF_GCLK_GEN_8_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_8_enable
+#ifndef CONF_GCLK_GEN_8_GENEN
+#define CONF_GCLK_GEN_8_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 8 division <0x0000-0xFFFF>
+// <id> gclk_gen_8_div
+#ifndef CONF_GCLK_GEN_8_DIV
+#define CONF_GCLK_GEN_8_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 9 configuration
+// <i> Indicates whether generic clock 9 configuration is enabled or not
+// <id> enable_gclk_gen_9
+#ifndef CONF_GCLK_GENERATOR_9_CONFIG
+#define CONF_GCLK_GENERATOR_9_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 9 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 9
+// <id> gclk_gen_9_oscillator
+#ifndef CONF_GCLK_GEN_9_SOURCE
+#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_9_runstdby
+#ifndef CONF_GCLK_GEN_9_RUNSTDBY
+#define CONF_GCLK_GEN_9_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_9_div_sel
+#ifndef CONF_GCLK_GEN_9_DIVSEL
+#define CONF_GCLK_GEN_9_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_9_oe
+#ifndef CONF_GCLK_GEN_9_OE
+#define CONF_GCLK_GEN_9_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_9_oov
+#ifndef CONF_GCLK_GEN_9_OOV
+#define CONF_GCLK_GEN_9_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_9_idc
+#ifndef CONF_GCLK_GEN_9_IDC
+#define CONF_GCLK_GEN_9_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_9_enable
+#ifndef CONF_GCLK_GEN_9_GENEN
+#define CONF_GCLK_GEN_9_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 9 division <0x0000-0xFFFF>
+// <id> gclk_gen_9_div
+#ifndef CONF_GCLK_GEN_9_DIV
+#define CONF_GCLK_GEN_9_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 10 configuration
+// <i> Indicates whether generic clock 10 configuration is enabled or not
+// <id> enable_gclk_gen_10
+#ifndef CONF_GCLK_GENERATOR_10_CONFIG
+#define CONF_GCLK_GENERATOR_10_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 10 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 10
+// <id> gclk_gen_10_oscillator
+#ifndef CONF_GCLK_GEN_10_SOURCE
+#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_10_runstdby
+#ifndef CONF_GCLK_GEN_10_RUNSTDBY
+#define CONF_GCLK_GEN_10_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_10_div_sel
+#ifndef CONF_GCLK_GEN_10_DIVSEL
+#define CONF_GCLK_GEN_10_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_10_oe
+#ifndef CONF_GCLK_GEN_10_OE
+#define CONF_GCLK_GEN_10_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_10_oov
+#ifndef CONF_GCLK_GEN_10_OOV
+#define CONF_GCLK_GEN_10_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_10_idc
+#ifndef CONF_GCLK_GEN_10_IDC
+#define CONF_GCLK_GEN_10_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_10_enable
+#ifndef CONF_GCLK_GEN_10_GENEN
+#define CONF_GCLK_GEN_10_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 10 division <0x0000-0xFFFF>
+// <id> gclk_gen_10_div
+#ifndef CONF_GCLK_GEN_10_DIV
+#define CONF_GCLK_GEN_10_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 11 configuration
+// <i> Indicates whether generic clock 11 configuration is enabled or not
+// <id> enable_gclk_gen_11
+#ifndef CONF_GCLK_GENERATOR_11_CONFIG
+#define CONF_GCLK_GENERATOR_11_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 11 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 11
+// <id> gclk_gen_11_oscillator
+#ifndef CONF_GCLK_GEN_11_SOURCE
+#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_11_runstdby
+#ifndef CONF_GCLK_GEN_11_RUNSTDBY
+#define CONF_GCLK_GEN_11_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_11_div_sel
+#ifndef CONF_GCLK_GEN_11_DIVSEL
+#define CONF_GCLK_GEN_11_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_11_oe
+#ifndef CONF_GCLK_GEN_11_OE
+#define CONF_GCLK_GEN_11_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_11_oov
+#ifndef CONF_GCLK_GEN_11_OOV
+#define CONF_GCLK_GEN_11_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_11_idc
+#ifndef CONF_GCLK_GEN_11_IDC
+#define CONF_GCLK_GEN_11_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_11_enable
+#ifndef CONF_GCLK_GEN_11_GENEN
+#define CONF_GCLK_GEN_11_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 11 division <0x0000-0xFFFF>
+// <id> gclk_gen_11_div
+#ifndef CONF_GCLK_GEN_11_DIV
+#define CONF_GCLK_GEN_11_DIV 1
+#endif
+// </h>
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_GCLK_CONFIG_H

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_mclk_config.h

@@ -0,0 +1,104 @@
+/* Auto-generated config file hpl_mclk_config.h */
+#ifndef HPL_MCLK_CONFIG_H
+#define HPL_MCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+// <e> System Configuration
+// <i> Indicates whether configuration for system is enabled or not
+// <id> enable_cpu_clock
+#ifndef CONF_SYSTEM_CONFIG
+#define CONF_SYSTEM_CONFIG 1
+#endif
+
+// <h> Basic settings
+// <y> CPU Clock source
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <i> This defines the clock source for the CPU
+// <id> cpu_clock_source
+#ifndef CONF_CPU_SRC
+#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> CPU Clock Division Factor
+// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
+// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
+// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
+// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
+// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
+// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
+// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
+// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
+// <i> Prescalar for CPU clock
+// <id> cpu_div
+#ifndef CONF_MCLK_CPUDIV
+#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
+#endif
+// <y> Low Power Clock Division
+// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
+// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
+// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
+// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
+// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
+// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
+// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
+// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
+// <id> mclk_arch_lpdiv
+#ifndef CONF_MCLK_LPDIV
+#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
+#endif
+
+// <y> Backup Clock Division
+// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
+// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
+// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
+// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
+// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
+// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
+// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
+// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
+// <id> mclk_arch_bupdiv
+#ifndef CONF_MCLK_BUPDIV
+#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
+#endif
+// <y> High-Speed Clock Division
+// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
+// <id> mclk_arch_hsdiv
+#ifndef CONF_MCLK_HSDIV
+#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
+#endif
+// </h>
+
+// <h> NVM Settings
+// <o> NVM Wait States
+// <i> These bits select the number of wait states for a read operation.
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <id> nvm_wait_states
+#ifndef CONF_NVM_WAIT_STATE
+#define CONF_NVM_WAIT_STATE 0
+#endif
+
+// </h>
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_MCLK_CONFIG_H

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_osc32kctrl_config.h

@@ -0,0 +1,165 @@
+/* Auto-generated config file hpl_osc32kctrl_config.h */
+#ifndef HPL_OSC32KCTRL_CONFIG_H
+#define HPL_OSC32KCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> RTC Source configuration
+// <id> enable_rtc_source
+#ifndef CONF_RTCCTRL_CONFIG
+#define CONF_RTCCTRL_CONFIG 0
+#endif
+
+// <h> RTC source control
+// <y> RTC Clock Source Selection
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <i> This defines the clock source for RTC
+// <id> rtc_source_oscillator
+#ifndef CONF_RTCCTRL_SRC
+#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
+#endif
+
+// <q> Use 1 kHz output
+// <id> rtc_1khz_selection
+#ifndef CONF_RTCCTRL_1KHZ
+
+#define CONF_RTCCTRL_1KHZ 0
+
+#endif
+
+#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
+#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
+#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
+#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
+#else
+#error unexpected CONF_RTCCTRL_SRC
+#endif
+
+// </h>
+// </e>
+
+// <e> 32kHz External Crystal Oscillator Configuration
+// <i> Indicates whether configuration for External 32K Osc is enabled or not
+// <id> enable_xosc32k
+#ifndef CONF_XOSC32K_CONFIG
+#define CONF_XOSC32K_CONFIG 0
+#endif
+
+// <h> 32kHz External Crystal Oscillator Control
+// <q> Oscillator enable
+// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
+// <id> xosc32k_arch_enable
+#ifndef CONF_XOSC32K_ENABLE
+#define CONF_XOSC32K_ENABLE 0
+#endif
+
+// <o> Start-Up Time
+// <0x0=>62592us
+// <0x1=>125092us
+// <0x2=>500092us
+// <0x3=>1000092us
+// <0x4=>2000092us
+// <0x5=>4000092us
+// <0x6=>8000092us
+// <id> xosc32k_arch_startup
+#ifndef CONF_XOSC32K_STARTUP
+#define CONF_XOSC32K_STARTUP 0x0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> xosc32k_arch_ondemand
+#ifndef CONF_XOSC32K_ONDEMAND
+#define CONF_XOSC32K_ONDEMAND 1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> xosc32k_arch_runstdby
+#ifndef CONF_XOSC32K_RUNSTDBY
+#define CONF_XOSC32K_RUNSTDBY 0
+#endif
+
+// <q> 1kHz Output Enable
+// <i> Indicates whether 1kHz Output is enabled or not
+// <id> xosc32k_arch_en1k
+#ifndef CONF_XOSC32K_EN1K
+#define CONF_XOSC32K_EN1K 0
+#endif
+
+// <q> 32kHz Output Enable
+// <i> Indicates whether 32kHz Output is enabled or not
+// <id> xosc32k_arch_en32k
+#ifndef CONF_XOSC32K_EN32K
+#define CONF_XOSC32K_EN32K 0
+#endif
+
+// <q> Clock Switch Back
+// <i> Indicates whether Clock Switch Back is enabled or not
+// <id> xosc32k_arch_swben
+#ifndef CONF_XOSC32K_SWBEN
+#define CONF_XOSC32K_SWBEN 0
+#endif
+
+// <q> Clock Failure Detector
+// <i> Indicates whether Clock Failure Detector is enabled or not
+// <id> xosc32k_arch_cfden
+#ifndef CONF_XOSC32K_CFDEN
+#define CONF_XOSC32K_CFDEN 0
+#endif
+
+// <q> Clock Failure Detector Event Out
+// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
+// <id> xosc32k_arch_cfdeo
+#ifndef CONF_XOSC32K_CFDEO
+#define CONF_XOSC32K_CFDEO 0
+#endif
+
+// <q> Crystal connected to XIN32/XOUT32 Enable
+// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// <id> xosc32k_arch_xtalen
+#ifndef CONF_XOSC32K_XTALEN
+#define CONF_XOSC32K_XTALEN 1
+#endif
+
+// <o> Control Gain Mode
+// <0x0=>Low Power mode
+// <0x1=>Standard mode
+// <0x2=>High Speed mode
+// <id> xosc32k_arch_cgm
+#ifndef CONF_XOSC32K_CGM
+#define CONF_XOSC32K_CGM 0x1
+#endif
+
+// </h>
+// </e>
+
+// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
+// <i> Indicates whether configuration for OSCULP32K is enabled or not
+// <id> enable_osculp32k
+#ifndef CONF_OSCULP32K_CONFIG
+#define CONF_OSCULP32K_CONFIG 1
+#endif
+
+// <h> 32kHz Ultra Low Power Internal Oscillator Control
+
+// <q> Oscillator Calibration Control
+// <i> Indicates whether Oscillator Calibration is enabled or not
+// <id> osculp32k_calib_enable
+#ifndef CONF_OSCULP32K_CALIB_ENABLE
+#define CONF_OSCULP32K_CALIB_ENABLE 0
+#endif
+
+// <o> Oscillator Calibration <0x0-0x3F>
+// <id> osculp32k_calib
+#ifndef CONF_OSCULP32K_CALIB
+#define CONF_OSCULP32K_CALIB 0x0
+#endif
+
+// </h>
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_OSC32KCTRL_CONFIG_H

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_oscctrl_config.h

@@ -0,0 +1,640 @@
+/* Auto-generated config file hpl_oscctrl_config.h */
+#ifndef HPL_OSCCTRL_CONFIG_H
+#define HPL_OSCCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> External Multipurpose Crystal Oscillator Configuration
+// <i> Indicates whether configuration for XOSC0 is enabled or not
+// <id> enable_xosc0
+#ifndef CONF_XOSC0_CONFIG
+#define CONF_XOSC0_CONFIG 0
+#endif
+
+// <o> Frequency <8000000-48000000>
+// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
+// <id> xosc0_frequency
+#ifndef CONF_XOSC_FREQUENCY
+#define CONF_XOSC0_FREQUENCY 12000000
+#endif
+
+// <h> External Multipurpose Crystal Oscillator Control
+// <q> Oscillator enable
+// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
+// <id> xosc0_arch_enable
+#ifndef CONF_XOSC0_ENABLE
+#define CONF_XOSC0_ENABLE 0
+#endif
+
+// <o> Start-Up Time
+// <0x0=>31us
+// <0x1=>61us
+// <0x2=>122us
+// <0x3=>244us
+// <0x4=>488us
+// <0x5=>977us
+// <0x6=>1953us
+// <0x7=>3906us
+// <0x8=>7813us
+// <0x9=>15625us
+// <0xA=>31250us
+// <0xB=>62500us
+// <0xC=>125000us
+// <0xD=>250000us
+// <0xE=>500000us
+// <0xF=>1000000us
+// <id> xosc0_arch_startup
+#ifndef CONF_XOSC0_STARTUP
+#define CONF_XOSC0_STARTUP 0
+#endif
+
+// <q> Clock Switch Back
+// <i> Indicates whether Clock Switch Back is enabled or not
+// <id> xosc0_arch_swben
+#ifndef CONF_XOSC0_SWBEN
+#define CONF_XOSC0_SWBEN 0
+#endif
+
+// <q> Clock Failure Detector
+// <i> Indicates whether Clock Failure Detector is enabled or not
+// <id> xosc0_arch_cfden
+#ifndef CONF_XOSC0_CFDEN
+#define CONF_XOSC0_CFDEN 0
+#endif
+
+// <q> Automatic Loop Control Enable
+// <i> Indicates whether Automatic Loop Control is enabled or not
+// <id> xosc0_arch_enalc
+#ifndef CONF_XOSC0_ENALC
+#define CONF_XOSC0_ENALC 0
+#endif
+
+// <q> Low Buffer Gain Enable
+// <i> Indicates whether Low Buffer Gain is enabled or not
+// <id> xosc0_arch_lowbufgain
+#ifndef CONF_XOSC0_LOWBUFGAIN
+#define CONF_XOSC0_LOWBUFGAIN 0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> xosc0_arch_ondemand
+#ifndef CONF_XOSC0_ONDEMAND
+#define CONF_XOSC0_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> xosc0_arch_runstdby
+#ifndef CONF_XOSC0_RUNSTDBY
+#define CONF_XOSC0_RUNSTDBY 0
+#endif
+
+// <q> Crystal connected to XIN/XOUT Enable
+// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// <id> xosc0_arch_xtalen
+#ifndef CONF_XOSC0_XTALEN
+#define CONF_XOSC0_XTALEN 0
+#endif
+//</h>
+//</e>
+
+#if CONF_XOSC0_FREQUENCY >= 32000000
+#define CONF_XOSC0_CFDPRESC 0x0
+#define CONF_XOSC0_IMULT 0x7
+#define CONF_XOSC0_IPTAT 0x3
+#elif CONF_XOSC0_FREQUENCY >= 24000000
+#define CONF_XOSC0_CFDPRESC 0x1
+#define CONF_XOSC0_IMULT 0x6
+#define CONF_XOSC0_IPTAT 0x3
+#elif CONF_XOSC0_FREQUENCY >= 16000000
+#define CONF_XOSC0_CFDPRESC 0x2
+#define CONF_XOSC0_IMULT 0x5
+#define CONF_XOSC0_IPTAT 0x3
+#elif CONF_XOSC0_FREQUENCY >= 8000000
+#define CONF_XOSC0_CFDPRESC 0x3
+#define CONF_XOSC0_IMULT 0x4
+#define CONF_XOSC0_IPTAT 0x3
+#endif
+
+// <e> External Multipurpose Crystal Oscillator Configuration
+// <i> Indicates whether configuration for XOSC1 is enabled or not
+// <id> enable_xosc1
+#ifndef CONF_XOSC1_CONFIG
+#define CONF_XOSC1_CONFIG 0
+#endif
+
+// <o> Frequency <8000000-48000000>
+// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
+// <id> xosc1_frequency
+#ifndef CONF_XOSC_FREQUENCY
+#define CONF_XOSC1_FREQUENCY 12000000
+#endif
+
+// <h> External Multipurpose Crystal Oscillator Control
+// <q> Oscillator enable
+// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
+// <id> xosc1_arch_enable
+#ifndef CONF_XOSC1_ENABLE
+#define CONF_XOSC1_ENABLE 0
+#endif
+
+// <o> Start-Up Time
+// <0x0=>31us
+// <0x1=>61us
+// <0x2=>122us
+// <0x3=>244us
+// <0x4=>488us
+// <0x5=>977us
+// <0x6=>1953us
+// <0x7=>3906us
+// <0x8=>7813us
+// <0x9=>15625us
+// <0xA=>31250us
+// <0xB=>62500us
+// <0xC=>125000us
+// <0xD=>250000us
+// <0xE=>500000us
+// <0xF=>1000000us
+// <id> xosc1_arch_startup
+#ifndef CONF_XOSC1_STARTUP
+#define CONF_XOSC1_STARTUP 0
+#endif
+
+// <q> Clock Switch Back
+// <i> Indicates whether Clock Switch Back is enabled or not
+// <id> xosc1_arch_swben
+#ifndef CONF_XOSC1_SWBEN
+#define CONF_XOSC1_SWBEN 0
+#endif
+
+// <q> Clock Failure Detector
+// <i> Indicates whether Clock Failure Detector is enabled or not
+// <id> xosc1_arch_cfden
+#ifndef CONF_XOSC1_CFDEN
+#define CONF_XOSC1_CFDEN 0
+#endif
+
+// <q> Automatic Loop Control Enable
+// <i> Indicates whether Automatic Loop Control is enabled or not
+// <id> xosc1_arch_enalc
+#ifndef CONF_XOSC1_ENALC
+#define CONF_XOSC1_ENALC 0
+#endif
+
+// <q> Low Buffer Gain Enable
+// <i> Indicates whether Low Buffer Gain is enabled or not
+// <id> xosc1_arch_lowbufgain
+#ifndef CONF_XOSC1_LOWBUFGAIN
+#define CONF_XOSC1_LOWBUFGAIN 0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> xosc1_arch_ondemand
+#ifndef CONF_XOSC1_ONDEMAND
+#define CONF_XOSC1_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> xosc1_arch_runstdby
+#ifndef CONF_XOSC1_RUNSTDBY
+#define CONF_XOSC1_RUNSTDBY 0
+#endif
+
+// <q> Crystal connected to XIN/XOUT Enable
+// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// <id> xosc1_arch_xtalen
+#ifndef CONF_XOSC1_XTALEN
+#define CONF_XOSC1_XTALEN 1
+#endif
+//</h>
+//</e>
+
+#if CONF_XOSC1_FREQUENCY >= 32000000
+#define CONF_XOSC1_CFDPRESC 0x0
+#define CONF_XOSC1_IMULT 0x7
+#define CONF_XOSC1_IPTAT 0x3
+#elif CONF_XOSC1_FREQUENCY >= 24000000
+#define CONF_XOSC1_CFDPRESC 0x1
+#define CONF_XOSC1_IMULT 0x6
+#define CONF_XOSC1_IPTAT 0x3
+#elif CONF_XOSC1_FREQUENCY >= 16000000
+#define CONF_XOSC1_CFDPRESC 0x2
+#define CONF_XOSC1_IMULT 0x5
+#define CONF_XOSC1_IPTAT 0x3
+#elif CONF_XOSC1_FREQUENCY >= 8000000
+#define CONF_XOSC1_CFDPRESC 0x3
+#define CONF_XOSC1_IMULT 0x4
+#define CONF_XOSC1_IPTAT 0x3
+#endif
+
+// <e> DFLL Configuration
+// <i> Indicates whether configuration for DFLL is enabled or not
+// <id> enable_dfll
+#ifndef CONF_DFLL_CONFIG
+#define CONF_DFLL_CONFIG 1
+#endif
+
+// <y> Reference Clock Source
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+// <i> Select the clock source
+// <id> dfll_ref_clock
+#ifndef CONF_DFLL_GCLK
+#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK2_Val
+#endif
+
+// <h> Digital Frequency Locked Loop Control
+// <q> DFLL Enable
+// <i> Indicates whether DFLL is enabled or not
+// <id> dfll_arch_enable
+#ifndef CONF_DFLL_ENABLE
+#define CONF_DFLL_ENABLE 1
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> dfll_arch_ondemand
+#ifndef CONF_DFLL_ONDEMAND
+#define CONF_DFLL_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> dfll_arch_runstdby
+#ifndef CONF_DFLL_RUNSTDBY
+#define CONF_DFLL_RUNSTDBY 0
+#endif
+
+// <q> USB Clock Recovery Mode
+// <i> Indicates whether USB Clock Recovery Mode is enabled or not
+// <id> dfll_arch_usbcrm
+#ifndef CONF_DFLL_USBCRM
+#define CONF_DFLL_USBCRM 0
+#endif
+
+// <q> Wait Lock
+// <i> Indicates whether Wait Lock is enabled or not
+// <id> dfll_arch_waitlock
+#ifndef CONF_DFLL_WAITLOCK
+#define CONF_DFLL_WAITLOCK 1
+#endif
+
+// <q> Bypass Coarse Lock
+// <i> Indicates whether Bypass Coarse Lock is enabled or not
+// <id> dfll_arch_bplckc
+#ifndef CONF_DFLL_BPLCKC
+#define CONF_DFLL_BPLCKC 0
+#endif
+
+// <q> Quick Lock Disable
+// <i> Indicates whether Quick Lock Disable is enabled or not
+// <id> dfll_arch_qldis
+#ifndef CONF_DFLL_QLDIS
+#define CONF_DFLL_QLDIS 0
+#endif
+
+// <q> Chill Cycle Disable
+// <i> Indicates whether Chill Cycle Disable is enabled or not
+// <id> dfll_arch_ccdis
+#ifndef CONF_DFLL_CCDIS
+#define CONF_DFLL_CCDIS 0
+#endif
+
+// <q> Lose Lock After Wake
+// <i> Indicates whether Lose Lock After Wake is enabled or not
+// <id> dfll_arch_llaw
+#ifndef CONF_DFLL_LLAW
+#define CONF_DFLL_LLAW 0
+#endif
+
+// <q> Stable DFLL Frequency
+// <i> Indicates whether Stable DFLL Frequency is enabled or not
+// <id> dfll_arch_stable
+#ifndef CONF_DFLL_STABLE
+#define CONF_DFLL_STABLE 0
+#endif
+
+// <o> Operating Mode Selection
+// <0=>Open Loop Mode
+// <1=>Closed Loop Mode
+// <id> dfll_mode
+#ifndef CONF_DFLL_MODE
+#define CONF_DFLL_MODE 0x0
+#endif
+
+// <o> Coarse Maximum Step <0x0-0x1F>
+// <id> dfll_arch_cstep
+#ifndef CONF_DFLL_CSTEP
+#define CONF_DFLL_CSTEP 0x1
+#endif
+
+// <o> Fine Maximum Step <0x0-0xFF>
+// <id> dfll_arch_fstep
+#ifndef CONF_DFLL_FSTEP
+#define CONF_DFLL_FSTEP 0x1
+#endif
+
+// <o> DFLL Multiply Factor <0x0-0xFFFF>
+//  <id> dfll_mul
+#ifndef CONF_DFLL_MUL
+#define CONF_DFLL_MUL 0x0
+#endif
+
+// <e> DFLL Calibration Overwrite
+// <i> Indicates whether Overwrite Calibration value of DFLL
+// <id> dfll_arch_calibration
+#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
+#define CONF_DFLL_OVERWRITE_CALIBRATION 0
+#endif
+
+// <o> Coarse Value <0x0-0x3F>
+// <id> dfll_arch_coarse
+#ifndef CONF_DFLL_COARSE
+#define CONF_DFLL_COARSE (0x1f / 4)
+#endif
+
+// <o> Fine Value <0x0-0xFF>
+// <id> dfll_arch_fine
+#ifndef CONF_DFLL_FINE
+#define CONF_DFLL_FINE (0x80)
+#endif
+
+//</e>
+
+//</h>
+
+//</e>
+
+// <e> FDPLL0 Configuration
+// <i> Indicates whether configuration for FDPLL0 is enabled or not
+// <id> enable_fdpll0
+#ifndef CONF_FDPLL0_CONFIG
+#define CONF_FDPLL0_CONFIG 0
+#endif
+
+// <y> Reference Clock Source
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+// <i> Select the clock source.
+// <id> fdpll0_ref_clock
+#ifndef CONF_FDPLL0_GCLK
+#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// <h> Digital Phase Locked Loop Control
+// <q> Enable
+// <i> Indicates whether Digital Phase Locked Loop is enabled or not
+// <id> fdpll0_arch_enable
+#ifndef CONF_FDPLL0_ENABLE
+#define CONF_FDPLL0_ENABLE 0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> fdpll0_arch_ondemand
+#ifndef CONF_FDPLL0_ONDEMAND
+#define CONF_FDPLL0_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> fdpll0_arch_runstdby
+#ifndef CONF_FDPLL0_RUNSTDBY
+#define CONF_FDPLL0_RUNSTDBY 0
+#endif
+
+// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
+// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
+// <id> fdpll0_ldrfrac
+#ifndef CONF_FDPLL0_LDRFRAC
+#define CONF_FDPLL0_LDRFRAC 0xd
+#endif
+
+// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
+// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
+// <id> fdpll0_ldr
+#ifndef CONF_FDPLL0_LDR
+#define CONF_FDPLL0_LDR 0x5b7
+#endif
+
+// <o> Clock Divider <0x0-0x7FF>
+// <i> This Clock divider is only for XOSC clock input to DPLL
+// <id> fdpll0_clock_div
+#ifndef CONF_FDPLL0_DIV
+#define CONF_FDPLL0_DIV 0x0
+#endif
+
+// <q> DCO Filter Enable
+// <i> Indicates whether DCO Filter Enable is enabled or not
+// <id> fdpll0_arch_dcoen
+#ifndef CONF_FDPLL0_DCOEN
+#define CONF_FDPLL0_DCOEN 0
+#endif
+
+// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
+// <id> fdpll0_clock_dcofilter
+#ifndef CONF_FDPLL0_DCOFILTER
+#define CONF_FDPLL0_DCOFILTER 0x0
+#endif
+
+// <q> Lock Bypass
+// <i> Indicates whether Lock Bypass is enabled or not
+// <id> fdpll0_arch_lbypass
+#ifndef CONF_FDPLL0_LBYPASS
+#define CONF_FDPLL0_LBYPASS 0
+#endif
+
+// <o> Lock Time
+// <0x0=>No time-out, automatic lock
+// <0x4=>The Time-out if no lock within 800 us
+// <0x5=>The Time-out if no lock within 900 us
+// <0x6=>The Time-out if no lock within 1 ms
+// <0x7=>The Time-out if no lock within 11 ms
+// <id> fdpll0_arch_ltime
+#ifndef CONF_FDPLL0_LTIME
+#define CONF_FDPLL0_LTIME 0x0
+#endif
+
+// <o> Reference Clock Selection
+// <0x0=>GCLK clock reference
+// <0x1=>XOSC32K clock reference
+// <0x2=>XOSC0 clock reference
+// <0x3=>XOSC1 clock reference
+// <id> fdpll0_arch_refclk
+#ifndef CONF_FDPLL0_REFCLK
+#define CONF_FDPLL0_REFCLK 0x1
+#endif
+
+// <q> Wake Up Fast
+// <i> Indicates whether Wake Up Fast is enabled or not
+// <id> fdpll0_arch_wuf
+#ifndef CONF_FDPLL0_WUF
+#define CONF_FDPLL0_WUF 0
+#endif
+
+// <o> Proportional Integral Filter Selection <0x0-0xF>
+// <id> fdpll0_arch_filter
+#ifndef CONF_FDPLL0_FILTER
+#define CONF_FDPLL0_FILTER 0x0
+#endif
+
+//</h>
+//</e>
+// <e> FDPLL1 Configuration
+// <i> Indicates whether configuration for FDPLL1 is enabled or not
+// <id> enable_fdpll1
+#ifndef CONF_FDPLL1_CONFIG
+#define CONF_FDPLL1_CONFIG 1
+#endif
+
+// <y> Reference Clock Source
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+// <i> Select the clock source.
+// <id> fdpll1_ref_clock
+#ifndef CONF_FDPLL1_GCLK
+#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+// <h> Digital Phase Locked Loop Control
+// <q> Enable
+// <i> Indicates whether Digital Phase Locked Loop is enabled or not
+// <id> fdpll1_arch_enable
+#ifndef CONF_FDPLL1_ENABLE
+#define CONF_FDPLL1_ENABLE 1
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> fdpll1_arch_ondemand
+#ifndef CONF_FDPLL1_ONDEMAND
+#define CONF_FDPLL1_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> fdpll1_arch_runstdby
+#ifndef CONF_FDPLL1_RUNSTDBY
+#define CONF_FDPLL1_RUNSTDBY 0
+#endif
+
+// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
+// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
+// <id> fdpll1_ldrfrac
+#ifndef CONF_FDPLL1_LDRFRAC
+#define CONF_FDPLL1_LDRFRAC 0x0
+#endif
+
+// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
+// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
+// <id> fdpll1_ldr
+#ifndef CONF_FDPLL1_LDR
+#define CONF_FDPLL1_LDR 0x31
+#endif
+
+// <o> Clock Divider <0x0-0x7FF>
+// <i> This Clock divider is only for XOSC clock input to DPLL
+// <id> fdpll1_clock_div
+#ifndef CONF_FDPLL1_DIV
+#define CONF_FDPLL1_DIV 0x0
+#endif
+
+// <q> DCO Filter Enable
+// <i> Indicates whether DCO Filter Enable is enabled or not
+// <id> fdpll1_arch_dcoen
+#ifndef CONF_FDPLL1_DCOEN
+#define CONF_FDPLL1_DCOEN 0
+#endif
+
+// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
+// <id> fdpll1_clock_dcofilter
+#ifndef CONF_FDPLL1_DCOFILTER
+#define CONF_FDPLL1_DCOFILTER 0x0
+#endif
+
+// <q> Lock Bypass
+// <i> Indicates whether Lock Bypass is enabled or not
+// <id> fdpll1_arch_lbypass
+#ifndef CONF_FDPLL1_LBYPASS
+#define CONF_FDPLL1_LBYPASS 0
+#endif
+
+// <o> Lock Time
+// <0x0=>No time-out, automatic lock
+// <0x4=>The Time-out if no lock within 800 us
+// <0x5=>The Time-out if no lock within 900 us
+// <0x6=>The Time-out if no lock within 1 ms
+// <0x7=>The Time-out if no lock within 11 ms
+// <id> fdpll1_arch_ltime
+#ifndef CONF_FDPLL1_LTIME
+#define CONF_FDPLL1_LTIME 0x0
+#endif
+
+// <o> Reference Clock Selection
+// <0x0=>GCLK clock reference
+// <0x1=>XOSC32K clock reference
+// <0x2=>XOSC0 clock reference
+// <0x3=>XOSC1 clock reference
+// <id> fdpll1_arch_refclk
+#ifndef CONF_FDPLL1_REFCLK
+#define CONF_FDPLL1_REFCLK 0x0
+#endif
+
+// <q> Wake Up Fast
+// <i> Indicates whether Wake Up Fast is enabled or not
+// <id> fdpll1_arch_wuf
+#ifndef CONF_FDPLL1_WUF
+#define CONF_FDPLL1_WUF 0
+#endif
+
+// <o> Proportional Integral Filter Selection <0x0-0xF>
+// <id> fdpll1_arch_filter
+#ifndef CONF_FDPLL1_FILTER
+#define CONF_FDPLL1_FILTER 0x0
+#endif
+
+//</h>
+//</e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_OSCCTRL_CONFIG_H

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_port_config.h

@@ -0,0 +1,284 @@
+/* Auto-generated config file hpl_port_config.h */
+#ifndef HPL_PORT_CONFIG_H
+#define HPL_PORT_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> PORT Input Event 0 configuration
+// <id> enable_port_input_event_0
+#ifndef CONF_PORT_EVCTRL_PORT_0
+#define CONF_PORT_EVCTRL_PORT_0 1
+#endif
+
+// <h> PORT Input Event 0 configuration on PORT A
+
+// <q> PORTA Input Event 0 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
+// <id> porta_input_event_enable_0
+#ifndef CONF_PORTA_EVCTRL_PORTEI_0
+#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
+#endif
+
+// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_0
+#ifndef CONF_PORTA_EVCTRL_PID_0
+#define CONF_PORTA_EVCTRL_PID_0 0x0
+#endif
+
+// <o> PORTA Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 0
+// <id> porta_event_action_0
+#ifndef CONF_PORTA_EVCTRL_EVACT_0
+#define CONF_PORTA_EVCTRL_EVACT_0 0
+#endif
+
+// </h>
+// <h> PORT Input Event 0 configuration on PORT B
+
+// <q> PORTB Input Event 0 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
+// <id> portb_input_event_enable_0
+#ifndef CONF_PORTB_EVCTRL_PORTEI_0
+#define CONF_PORTB_EVCTRL_PORTEI_0 0x1
+#endif
+
+// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_0
+#ifndef CONF_PORTB_EVCTRL_PID_0
+#define CONF_PORTB_EVCTRL_PID_0 0x16
+#endif
+
+// <o> PORTB Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 0
+// <id> portb_event_action_0
+#ifndef CONF_PORTB_EVCTRL_EVACT_0
+#define CONF_PORTB_EVCTRL_EVACT_0 2
+#endif
+
+// </h>
+
+// </e>
+
+// <e> PORT Input Event 1 configuration
+// <id> enable_port_input_event_1
+#ifndef CONF_PORT_EVCTRL_PORT_1
+#define CONF_PORT_EVCTRL_PORT_1 1
+#endif
+
+// <h> PORT Input Event 1 configuration on PORT A
+
+// <q> PORTA Input Event 1 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
+// <id> porta_input_event_enable_1
+#ifndef CONF_PORTA_EVCTRL_PORTEI_1
+#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
+#endif
+
+// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_1
+#ifndef CONF_PORTA_EVCTRL_PID_1
+#define CONF_PORTA_EVCTRL_PID_1 0x0
+#endif
+
+// <o> PORTA Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 1
+// <id> porta_event_action_1
+#ifndef CONF_PORTA_EVCTRL_EVACT_1
+#define CONF_PORTA_EVCTRL_EVACT_1 0
+#endif
+
+// </h>
+// <h> PORT Input Event 1 configuration on PORT B
+
+// <q> PORTB Input Event 1 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
+// <id> portb_input_event_enable_1
+#ifndef CONF_PORTB_EVCTRL_PORTEI_1
+#define CONF_PORTB_EVCTRL_PORTEI_1 0x1
+#endif
+
+// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_1
+#ifndef CONF_PORTB_EVCTRL_PID_1
+#define CONF_PORTB_EVCTRL_PID_1 0x16
+#endif
+
+// <o> PORTB Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 1
+// <id> portb_event_action_1
+#ifndef CONF_PORTB_EVCTRL_EVACT_1
+#define CONF_PORTB_EVCTRL_EVACT_1 1
+#endif
+
+// </h>
+
+// </e>
+
+// <e> PORT Input Event 2 configuration
+// <id> enable_port_input_event_2
+#ifndef CONF_PORT_EVCTRL_PORT_2
+#define CONF_PORT_EVCTRL_PORT_2 1
+#endif
+
+// <h> PORT Input Event 2 configuration on PORT A
+
+// <q> PORTA Input Event 2 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
+// <id> porta_input_event_enable_2
+#ifndef CONF_PORTA_EVCTRL_PORTEI_2
+#define CONF_PORTA_EVCTRL_PORTEI_2 0x1
+#endif
+
+// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_2
+#ifndef CONF_PORTA_EVCTRL_PID_2
+#define CONF_PORTA_EVCTRL_PID_2 0xe
+#endif
+
+// <o> PORTA Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 2
+// <id> porta_event_action_2
+#ifndef CONF_PORTA_EVCTRL_EVACT_2
+#define CONF_PORTA_EVCTRL_EVACT_2 2
+#endif
+
+// </h>
+// <h> PORT Input Event 2 configuration on PORT B
+
+// <q> PORTB Input Event 2 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
+// <id> portb_input_event_enable_2
+#ifndef CONF_PORTB_EVCTRL_PORTEI_2
+#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
+#endif
+
+// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_2
+#ifndef CONF_PORTB_EVCTRL_PID_2
+#define CONF_PORTB_EVCTRL_PID_2 0x0
+#endif
+
+// <o> PORTB Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 2
+// <id> portb_event_action_2
+#ifndef CONF_PORTB_EVCTRL_EVACT_2
+#define CONF_PORTB_EVCTRL_EVACT_2 0
+#endif
+
+// </h>
+
+// </e>
+
+// <e> PORT Input Event 3 configuration
+// <id> enable_port_input_event_3
+#ifndef CONF_PORT_EVCTRL_PORT_3
+#define CONF_PORT_EVCTRL_PORT_3 1
+#endif
+
+// <h> PORT Input Event 3 configuration on PORT A
+
+// <q> PORTA Input Event 3 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
+// <id> porta_input_event_enable_3
+#ifndef CONF_PORTA_EVCTRL_PORTEI_3
+#define CONF_PORTA_EVCTRL_PORTEI_3 0x1
+#endif
+
+// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_3
+#ifndef CONF_PORTA_EVCTRL_PID_3
+#define CONF_PORTA_EVCTRL_PID_3 0xe
+#endif
+
+// <o> PORTA Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 3
+// <id> porta_event_action_3
+#ifndef CONF_PORTA_EVCTRL_EVACT_3
+#define CONF_PORTA_EVCTRL_EVACT_3 1
+#endif
+
+// </h>
+// <h> PORT Input Event 3 configuration on PORT B
+
+// <q> PORTB Input Event 3 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
+// <id> portb_input_event_enable_3
+#ifndef CONF_PORTB_EVCTRL_PORTEI_3
+#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
+#endif
+
+// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_3
+#ifndef CONF_PORTB_EVCTRL_PID_3
+#define CONF_PORTB_EVCTRL_PID_3 0x0
+#endif
+
+// <o> PORTB Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 3
+// <id> portb_event_action_3
+#ifndef CONF_PORTB_EVCTRL_EVACT_3
+#define CONF_PORTB_EVCTRL_EVACT_3 0
+#endif
+
+// </h>
+
+// </e>
+
+#define CONF_PORTA_EVCTRL                                                                                              \
+	(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos         \
+	 | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1)                       \
+	 | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1)               \
+	 | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos           \
+	 | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3)                       \
+	 | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
+#define CONF_PORTB_EVCTRL                                                                                              \
+	(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos         \
+	 | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1)                       \
+	 | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1)               \
+	 | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos           \
+	 | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3)                       \
+	 | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
+
+// <<< end of configuration section >>>
+
+#endif // HPL_PORT_CONFIG_H

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_qspi_config.h

@@ -0,0 +1,98 @@
+/* Auto-generated config file hpl_qspi_config.h */
+#ifndef HPL_QSPI_CONFIG_H
+#define HPL_QSPI_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+// <h> Basic settings
+
+#ifndef CONF_CONF_QSPI_ENABLE
+#define CONF_CONF_QSPI_ENABLE 1
+#endif
+
+// <o> Baud rate <1-150000000>
+// <i> The SPI data transfer rate. Note: (fqspi_clock / baudrate) < 255
+// <id> qspi_baud_rate
+#ifndef CONF_QSPI_BAUD
+#define CONF_QSPI_BAUD 6000000
+#endif
+
+// <o> Clock Polarity
+// <0x0=>The inactive state value of SPCK is logic level zero.
+// <0x1=>The inactive state value of SPCK is logic level one.
+// <i> Determines the inactive state value of the serial clock (SPCK).
+// <id> qspi_cpol
+#ifndef CONF_QSPI_CPOL
+#define CONF_QSPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
+// <0x1=>Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
+// <i> Determines which edge of SPCK causes data to change and which edge causes data to be captured.
+// <id> qspi_cpha
+#ifndef CONF_QSPI_CPHA
+#define CONF_QSPI_CPHA 0x0
+#endif
+
+//<o> QSPI DMA TX Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> qspi_dma_tx_channel
+#ifndef CONF_QSPI_DMA_TX_CHANNEL
+#define CONF_QSPI_DMA_TX_CHANNEL 1
+#endif
+
+//<o> QSPI DMA RX  Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> qspi_dma_rx_channel
+#ifndef CONF_QSPI_DMA_RX_CHANNEL
+#define CONF_QSPI_DMA_RX_CHANNEL 0
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> qspi_advanced
+#ifndef CONF_QSPI_ADVANCED
+#define CONF_QSPI_ADVANCED 0
+#endif
+
+// <o> Delay Before QSCK (ns) <0-255000>
+// <i> This field defines the delay from QCS falling edge (activation) to the first valid QSCK transition (in ns).
+// <id> qspi_dlybs
+#ifndef CONF_QSPI_DLY_BS
+#define CONF_QSPI_DLY_BS 0
+#endif
+
+// <o> Minimum Inactive QCS Delay (ns) <0-8160000>
+// <i> This field defines the minimum delay between the deactivation and the activation of QCS (in ns).
+// <id> qspi_dlycs
+#ifndef CONF_QSPI_DLY_CS
+#define CONF_QSPI_DLY_CS 0
+#endif
+
+// </e>
+
+/* Calculate baud register value from requested baudrate value */
+#ifndef CONF_QSPI_BAUD_RATE
+#define CONF_QSPI_BAUD_RATE ((CONF_CPU_FREQUENCY / CONF_QSPI_BAUD) - 1)
+#if CONF_QSPI_BAUD > CONF_CPU_FREQUENCY || CONF_QSPI_BAUD_RATE > 255
+#warning Invalid baudrate, please check.
+#endif
+#endif
+
+/* Calculates the value of the CSR DLYCS field given the desired delay (in ns) */
+#ifndef CONF_QSPI_DLYCS
+#define CONF_QSPI_DLYCS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_CS) / 1000)
+#endif
+
+/* Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
+#ifndef CONF_QSPI_DLYBS
+#define CONF_QSPI_DLYBS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_BS) / 1000)
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_QSPI_CONFIG_H

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Config/hpl_sercom_config.h

@@ -0,0 +1,791 @@
+/* Auto-generated config file hpl_sercom_config.h */
+#ifndef HPL_SERCOM_CONFIG_H
+#define HPL_SERCOM_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+#endif
+
+#ifndef CONF_SERCOM_0_I2CM_ENABLE
+#define CONF_SERCOM_0_I2CM_ENABLE 1
+#endif
+
+// <h> Basic
+
+// <o> I2C Bus clock speed (Hz) <1-400000>
+// <i> I2C Bus clock (SCL) speed measured in Hz
+// <id> i2c_master_baud_rate
+#ifndef CONF_SERCOM_0_I2CM_BAUD
+#define CONF_SERCOM_0_I2CM_BAUD 100000
+#endif
+
+// </h>
+
+// <e> Advanced
+// <id> i2c_master_advanced
+#ifndef CONF_SERCOM_0_I2CM_ADVANCED_CONFIG
+#define CONF_SERCOM_0_I2CM_ADVANCED_CONFIG 0
+#endif
+
+// <o> TRise (ns) <0-300>
+// <i> Determined by the bus impedance, check electric characteristics in the datasheet
+// <i> Standard Fast Mode: typical 215ns, max 300ns
+// <i> Fast Mode +: typical 60ns, max 100ns
+// <i> High Speed Mode: typical 20ns, max 40ns
+// <id> i2c_master_arch_trise
+
+#ifndef CONF_SERCOM_0_I2CM_TRISE
+#define CONF_SERCOM_0_I2CM_TRISE 215
+#endif
+
+// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
+// <i> This enables the master SCL low extend time-out
+// <id> i2c_master_arch_mexttoen
+#ifndef CONF_SERCOM_0_I2CM_MEXTTOEN
+#define CONF_SERCOM_0_I2CM_MEXTTOEN 0
+#endif
+
+// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
+// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
+// <id> i2c_master_arch_sexttoen
+#ifndef CONF_SERCOM_0_I2CM_SEXTTOEN
+#define CONF_SERCOM_0_I2CM_SEXTTOEN 0
+#endif
+
+// <q> SCL Low Time-Out (LOWTOUT)
+// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
+// <id> i2c_master_arch_lowtout
+#ifndef CONF_SERCOM_0_I2CM_LOWTOUT
+#define CONF_SERCOM_0_I2CM_LOWTOUT 0
+#endif
+
+// <o> Inactive Time-Out (INACTOUT)
+// <0x0=>Disabled
+// <0x1=>5-6 SCL cycle time-out(50-60us)
+// <0x2=>10-11 SCL cycle time-out(100-110us)
+// <0x3=>20-21 SCL cycle time-out(200-210us)
+// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
+// <id> i2c_master_arch_inactout
+#ifndef CONF_SERCOM_0_I2CM_INACTOUT
+#define CONF_SERCOM_0_I2CM_INACTOUT 0x0
+#endif
+
+// <o> SDA Hold Time (SDAHOLD)
+// <0=>Disabled
+// <1=>50-100ns hold time
+// <2=>300-600ns hold time
+// <3=>400-800ns hold time
+// <i> Defines the SDA hold time with respect to the negative edge of SCL
+// <id> i2c_master_arch_sdahold
+#ifndef CONF_SERCOM_0_I2CM_SDAHOLD
+#define CONF_SERCOM_0_I2CM_SDAHOLD 0x2
+#endif
+
+// <q> Run in stand-by
+// <i> Determine if the module shall run in standby sleep mode
+// <id> i2c_master_arch_runstdby
+#ifndef CONF_SERCOM_0_I2CM_RUNSTDBY
+#define CONF_SERCOM_0_I2CM_RUNSTDBY 0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> i2c_master_arch_dbgstop
+#ifndef CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE
+#define CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE 0
+#endif
+
+// </e>
+
+#ifndef CONF_SERCOM_0_I2CM_SPEED
+#define CONF_SERCOM_0_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
+#endif
+#if CONF_SERCOM_0_I2CM_TRISE < 215 || CONF_SERCOM_0_I2CM_TRISE > 300
+#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
+#undef CONF_SERCOM_0_I2CM_TRISE
+#define CONF_SERCOM_0_I2CM_TRISE 215U
+#endif
+
+//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
+// BAUD + BAUDLOW = --------------------------------------------------------------------
+//                  i2c_scl_freq
+// BAUD:    register value low  [7:0]
+// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
+#define CONF_SERCOM_0_I2CM_BAUD_BAUDLOW                                                                                \
+	(((CONF_GCLK_SERCOM0_CORE_FREQUENCY - (CONF_SERCOM_0_I2CM_BAUD * 10U)                                              \
+	   - (CONF_SERCOM_0_I2CM_TRISE * (CONF_SERCOM_0_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM0_CORE_FREQUENCY / 10000U)    \
+	      / 1000U))                                                                                                    \
+	      * 10U                                                                                                        \
+	  + 5U)                                                                                                            \
+	 / (CONF_SERCOM_0_I2CM_BAUD * 10U))
+#ifndef CONF_SERCOM_0_I2CM_BAUD_RATE
+#if CONF_SERCOM_0_I2CM_BAUD_BAUDLOW > (0xFF * 2)
+#warning Requested I2C baudrate too low, please check
+#define CONF_SERCOM_0_I2CM_BAUD_RATE 0xFF
+#elif CONF_SERCOM_0_I2CM_BAUD_BAUDLOW <= 1
+#warning Requested I2C baudrate too high, please check
+#define CONF_SERCOM_0_I2CM_BAUD_RATE 1
+#else
+#define CONF_SERCOM_0_I2CM_BAUD_RATE                                                                                   \
+	((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
+	     ? (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
+	     : (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2))
+#endif
+#endif
+
+#include <peripheral_clk_config.h>
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_1_SPI_ENABLE
+#define CONF_SERCOM_1_SPI_ENABLE 1
+#endif
+
+//<o> SPI DMA TX Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> spi_master_dma_tx_channel
+#ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 7
+#endif
+
+// <e> SPI RX Channel Enable
+// <id> spi_master_rx_channel
+#ifndef CONF_SERCOM_1_SPI_RX_CHANNEL
+#define CONF_SERCOM_1_SPI_RX_CHANNEL 1
+#endif
+
+//<o> DMA Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> spi_master_dma_rx_channel
+#ifndef CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL 0
+#endif
+
+// </e>
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_1_SPI_MODE
+#define CONF_SERCOM_1_SPI_MODE 0x03
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave (RXEN)
+// <id> spi_master_rx_enable
+#ifndef CONF_SERCOM_1_SPI_RXEN
+#define CONF_SERCOM_1_SPI_RXEN 0x1
+#endif
+
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_master_character_size
+#ifndef CONF_SERCOM_1_SPI_CHSIZE
+#define CONF_SERCOM_1_SPI_CHSIZE 0x0
+#endif
+// <o> Baud rate <1-18000000>
+// <i> The SPI data transfer rate
+// <id> spi_master_baud_rate
+#ifndef CONF_SERCOM_1_SPI_BAUD
+#define CONF_SERCOM_1_SPI_BAUD 1000000
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> spi_master_advanced
+#ifndef CONF_SERCOM_1_SPI_ADVANCED
+#define CONF_SERCOM_1_SPI_ADVANCED 1
+#endif
+
+// <o> Dummy byte <0x00-0x1ff>
+// <id> spi_master_dummybyte
+// <i> Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_1_SPI_DUMMYBYTE
+#define CONF_SERCOM_1_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first (DORD)
+// <id> spi_master_arch_dord
+#ifndef CONF_SERCOM_1_SPI_DORD
+#define CONF_SERCOM_1_SPI_DORD 0x0
+#endif
+
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_master_arch_cpol
+#ifndef CONF_SERCOM_1_SPI_CPOL
+#define CONF_SERCOM_1_SPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_master_arch_cpha
+#ifndef CONF_SERCOM_1_SPI_CPHA
+#define CONF_SERCOM_1_SPI_CPHA 0x0
+#endif
+
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_master_arch_ibon
+#ifndef CONF_SERCOM_1_SPI_IBON
+#define CONF_SERCOM_1_SPI_IBON 0x0
+#endif
+
+// <q> Run in stand-by
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_master_arch_runstdby
+#ifndef CONF_SERCOM_1_SPI_RUNSTDBY
+#define CONF_SERCOM_1_SPI_RUNSTDBY 0x0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// <id> spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_1_SPI_DBGSTOP
+#define CONF_SERCOM_1_SPI_DBGSTOP 0
+#endif
+
+// </e>
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_1_SPI_AMODE_EN
+#define CONF_SERCOM_1_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_AMODE
+#define CONF_SERCOM_1_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_ADDR
+#define CONF_SERCOM_1_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_ADDRMASK
+#define CONF_SERCOM_1_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_SSDE
+#define CONF_SERCOM_1_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_MSSEN
+#define CONF_SERCOM_1_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_1_SPI_PLOADEN
+#define CONF_SERCOM_1_SPI_PLOADEN 0
+#endif
+
+// <o> Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// <id> spi_master_rxpo
+#ifndef CONF_SERCOM_1_SPI_RXPO
+#define CONF_SERCOM_1_SPI_RXPO 3
+#endif
+
+// <o> Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// <id> spi_master_txpo
+#ifndef CONF_SERCOM_1_SPI_TXPO
+#define CONF_SERCOM_1_SPI_TXPO 0
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_1_SPI_BAUD_RATE
+#define CONF_SERCOM_1_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM1_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_1_SPI_BAUD)) - 1
+#endif
+
+#include <peripheral_clk_config.h>
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_2_SPI_ENABLE
+#define CONF_SERCOM_2_SPI_ENABLE 1
+#endif
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_2_SPI_MODE
+#define CONF_SERCOM_2_SPI_MODE 0x03
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave (RXEN)
+// <id> spi_master_rx_enable
+#ifndef CONF_SERCOM_2_SPI_RXEN
+#define CONF_SERCOM_2_SPI_RXEN 0x1
+#endif
+
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_master_character_size
+#ifndef CONF_SERCOM_2_SPI_CHSIZE
+#define CONF_SERCOM_2_SPI_CHSIZE 0x0
+#endif
+// <o> Baud rate <1-18000000>
+// <i> The SPI data transfer rate
+// <id> spi_master_baud_rate
+#ifndef CONF_SERCOM_2_SPI_BAUD
+#define CONF_SERCOM_2_SPI_BAUD 1000000
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> spi_master_advanced
+#ifndef CONF_SERCOM_2_SPI_ADVANCED
+#define CONF_SERCOM_2_SPI_ADVANCED 1
+#endif
+
+// <o> Dummy byte <0x00-0x1ff>
+// <id> spi_master_dummybyte
+// <i> Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_2_SPI_DUMMYBYTE
+#define CONF_SERCOM_2_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first (DORD)
+// <id> spi_master_arch_dord
+#ifndef CONF_SERCOM_2_SPI_DORD
+#define CONF_SERCOM_2_SPI_DORD 0x0
+#endif
+
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_master_arch_cpol
+#ifndef CONF_SERCOM_2_SPI_CPOL
+#define CONF_SERCOM_2_SPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_master_arch_cpha
+#ifndef CONF_SERCOM_2_SPI_CPHA
+#define CONF_SERCOM_2_SPI_CPHA 0x1
+#endif
+
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_master_arch_ibon
+#ifndef CONF_SERCOM_2_SPI_IBON
+#define CONF_SERCOM_2_SPI_IBON 0x1
+#endif
+
+// <q> Run in stand-by
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_master_arch_runstdby
+#ifndef CONF_SERCOM_2_SPI_RUNSTDBY
+#define CONF_SERCOM_2_SPI_RUNSTDBY 0x0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// <id> spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_2_SPI_DBGSTOP
+#define CONF_SERCOM_2_SPI_DBGSTOP 0
+#endif
+
+// </e>
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_2_SPI_AMODE_EN
+#define CONF_SERCOM_2_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_AMODE
+#define CONF_SERCOM_2_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_ADDR
+#define CONF_SERCOM_2_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_ADDRMASK
+#define CONF_SERCOM_2_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_SSDE
+#define CONF_SERCOM_2_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_MSSEN
+#define CONF_SERCOM_2_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_2_SPI_PLOADEN
+#define CONF_SERCOM_2_SPI_PLOADEN 0
+#endif
+
+// <o> Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// <id> spi_master_rxpo
+#ifndef CONF_SERCOM_2_SPI_RXPO
+#define CONF_SERCOM_2_SPI_RXPO 3
+#endif
+
+// <o> Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// <id> spi_master_txpo
+#ifndef CONF_SERCOM_2_SPI_TXPO
+#define CONF_SERCOM_2_SPI_TXPO 0
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_2_SPI_BAUD_RATE
+#define CONF_SERCOM_2_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM2_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_2_SPI_BAUD)) - 1
+#endif
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_3_SPI_ENABLE
+#define CONF_SERCOM_3_SPI_ENABLE 0
+#endif
+
+// Set module in SPI Slave mode
+#ifndef CONF_SERCOM_3_SPI_MODE
+#define CONF_SERCOM_3_SPI_MODE 0x02
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave. (RXEN)
+// <id> spi_slave_rx_enable
+#ifndef CONF_SERCOM_3_SPI_RXEN
+#define CONF_SERCOM_3_SPI_RXEN 0x1
+#endif
+
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus. (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_slave_character_size
+#ifndef CONF_SERCOM_3_SPI_CHSIZE
+#define CONF_SERCOM_3_SPI_CHSIZE 0x0
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> spi_slave_advanced
+#ifndef CONF_SERCOM_3_SPI_ADVANCED
+#define CONF_SERCOM_3_SPI_ADVANCED 0
+#endif
+
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first. (DORD)
+// <id> spi_slave_arch_dord
+#ifndef CONF_SERCOM_3_SPI_DORD
+#define CONF_SERCOM_3_SPI_DORD 0x0
+#endif
+
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_slave_arch_cpol
+#ifndef CONF_SERCOM_3_SPI_CPOL
+#define CONF_SERCOM_3_SPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_slave_arch_cpha
+#ifndef CONF_SERCOM_3_SPI_CPHA
+#define CONF_SERCOM_3_SPI_CPHA 0x1
+#endif
+
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted. (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_slave_arch_ibon
+#ifndef CONF_SERCOM_3_SPI_IBON
+#define CONF_SERCOM_3_SPI_IBON 0x0
+#endif
+
+// <q> Slave Select Low Detect Enable
+// <i> This bit enables wake up when the slave select (_SS) pin transitions from high to low. (SSDE)
+// <id> spi_slave_arch_ssde
+#ifndef CONF_SERCOM_3_SPI_SSDE
+#define CONF_SERCOM_3_SPI_SSDE 0
+#endif
+
+// <q> Slave Detect Preload Enable
+// <i> Setting this bit will enable preloading of the slave shift register when there is no transfer in progress. (PLOADEN)
+// <id> spi_slave_arch_ploaden
+#ifndef CONF_SERCOM_3_SPI_PLOADEN
+#define CONF_SERCOM_3_SPI_PLOADEN 0
+#endif
+
+// <q> Enable SPI address mode
+// <i> This will enable SPI frames with address, first received character is treated as address. (FORM=SPI_ADDR)
+// <id> spi_slave_arch_amode_en
+#ifndef CONF_SERCOM_3_SPI_AMODE_EN
+#define CONF_SERCOM_3_SPI_AMODE_EN 0
+#endif
+
+// <o> Address Mode
+// <0x0=>Address mask
+// <0x1=>Two unique addresses
+// <0x2=>Address range
+// <i> These bits set the slave addressing mode when the frame format with address is used. (AMODE)
+// <id> spi_slave_arch_amode
+#ifndef CONF_SERCOM_3_SPI_AMODE
+#define CONF_SERCOM_3_SPI_AMODE 0
+#endif
+
+// <o> Address <0-255>
+// <i> These bits hold the address when SPI address modes is enabled. (ADDR)
+// <id> spi_slave_arch_addr
+#ifndef CONF_SERCOM_3_SPI_ADDR
+#define CONF_SERCOM_3_SPI_ADDR 0
+#endif
+
+// <o> Address mask <0-255>
+// <i> These bits hold the address mask when SPI address mode is enabled. (ADDRMASK)
+// <id> spi_slave_arch_addrmask
+#ifndef CONF_SERCOM_3_SPI_ADDRMASK
+#define CONF_SERCOM_3_SPI_ADDRMASK 0
+#endif
+
+// <q> Run in stand-by
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_slave_arch_runstdby
+#ifndef CONF_SERCOM_3_SPI_RUNSTDBY
+#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// <id> spi_slave_arch_dbgstop
+#ifndef CONF_SERCOM_3_SPI_DBGSTOP
+#define CONF_SERCOM_3_SPI_DBGSTOP 0
+#endif
+
+// </e>
+
+// This bit is not applicable in slave mode
+#ifndef CONF_SERCOM_3_SPI_MSSEN
+#define CONF_SERCOM_3_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_BAUD_RATE
+#define CONF_SERCOM_3_SPI_BAUD_RATE 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE
+#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x0
+#endif
+
+#include <peripheral_clk_config.h>
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_5_SPI_ENABLE
+#define CONF_SERCOM_5_SPI_ENABLE 1
+#endif
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_5_SPI_MODE
+#define CONF_SERCOM_5_SPI_MODE 0x03
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave (RXEN)
+// <id> spi_master_rx_enable
+#ifndef CONF_SERCOM_5_SPI_RXEN
+#define CONF_SERCOM_5_SPI_RXEN 0x1
+#endif
+
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_master_character_size
+#ifndef CONF_SERCOM_5_SPI_CHSIZE
+#define CONF_SERCOM_5_SPI_CHSIZE 0x0
+#endif
+// <o> Baud rate <1-18000000>
+// <i> The SPI data transfer rate
+// <id> spi_master_baud_rate
+#ifndef CONF_SERCOM_5_SPI_BAUD
+#define CONF_SERCOM_5_SPI_BAUD 1000000
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> spi_master_advanced
+#ifndef CONF_SERCOM_5_SPI_ADVANCED
+#define CONF_SERCOM_5_SPI_ADVANCED 0
+#endif
+
+// <o> Dummy byte <0x00-0x1ff>
+// <id> spi_master_dummybyte
+// <i> Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_5_SPI_DUMMYBYTE
+#define CONF_SERCOM_5_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first (DORD)
+// <id> spi_master_arch_dord
+#ifndef CONF_SERCOM_5_SPI_DORD
+#define CONF_SERCOM_5_SPI_DORD 0x0
+#endif
+
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_master_arch_cpol
+#ifndef CONF_SERCOM_5_SPI_CPOL
+#define CONF_SERCOM_5_SPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_master_arch_cpha
+#ifndef CONF_SERCOM_5_SPI_CPHA
+#define CONF_SERCOM_5_SPI_CPHA 0x0
+#endif
+
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_master_arch_ibon
+#ifndef CONF_SERCOM_5_SPI_IBON
+#define CONF_SERCOM_5_SPI_IBON 0x0
+#endif
+
+// <q> Run in stand-by
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_master_arch_runstdby
+#ifndef CONF_SERCOM_5_SPI_RUNSTDBY
+#define CONF_SERCOM_5_SPI_RUNSTDBY 0x0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// <id> spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_5_SPI_DBGSTOP
+#define CONF_SERCOM_5_SPI_DBGSTOP 0
+#endif
+
+// </e>
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_5_SPI_AMODE_EN
+#define CONF_SERCOM_5_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_AMODE
+#define CONF_SERCOM_5_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_ADDR
+#define CONF_SERCOM_5_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_ADDRMASK
+#define CONF_SERCOM_5_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_SSDE
+#define CONF_SERCOM_5_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_MSSEN
+#define CONF_SERCOM_5_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_5_SPI_PLOADEN
+#define CONF_SERCOM_5_SPI_PLOADEN 0
+#endif
+
+// <o> Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// <id> spi_master_rxpo
+#ifndef CONF_SERCOM_5_SPI_RXPO
+#define CONF_SERCOM_5_SPI_RXPO 3
+#endif
+
+// <o> Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// <id> spi_master_txpo
+#ifndef CONF_SERCOM_5_SPI_TXPO
+#define CONF_SERCOM_5_SPI_TXPO 0
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_5_SPI_BAUD_RATE
+#define CONF_SERCOM_5_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM5_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_5_SPI_BAUD)) - 1
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SERCOM_CONFIG_H

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Debug.xml

@@ -0,0 +1,126 @@
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+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+      <Value>%24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include</Value>
+      <Value>../Config</Value>
+      <Value>../</Value>
+      <Value>../examples</Value>
+      <Value>../hal/include</Value>
+      <Value>../hal/utils/include</Value>
+      <Value>../hpl/adc</Value>
+      <Value>../hpl/ccl</Value>
+      <Value>../hpl/cmcc</Value>
+      <Value>../hpl/core</Value>
+      <Value>../hpl/dmac</Value>
+      <Value>../hpl/eic</Value>
+      <Value>../hpl/evsys</Value>
+      <Value>../hpl/gclk</Value>
+      <Value>../hpl/mclk</Value>
+      <Value>../hpl/osc32kctrl</Value>
+      <Value>../hpl/oscctrl</Value>
+      <Value>../hpl/pm</Value>
+      <Value>../hpl/port</Value>
+      <Value>../hpl/qspi</Value>
+      <Value>../hpl/ramecc</Value>
+      <Value>../hpl/sercom</Value>
+      <Value>../hpl/tc</Value>
+      <Value>../hpl/tcc</Value>
+      <Value>../hri</Value>
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.level>Optimize debugging experience (-Og)</armgcc.compiler.optimization.level>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcc.linker.general.UseNewlibNano>True</armgcc.linker.general.UseNewlibNano>
+  <armgcc.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>libarm_cortexM4lf_math.a</Value>
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+  </armgcc.linker.libraries.Libraries>
+  <armgcc.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>C:\Users\ge37vez\Documents\Git Repos\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master_D51\Two_Motor_D51\Two_Motor_D51\cmsis</Value>
+      <Value>%24(ProjectDir)\Device_Startup</Value>
+    </ListValues>
+  </armgcc.linker.libraries.LibrarySearchPaths>
+  <armgcc.linker.optimization.GarbageCollectUnusedSections>True</armgcc.linker.optimization.GarbageCollectUnusedSections>
+  <armgcc.linker.memorysettings.ExternalRAM />
+  <armgcc.linker.miscellaneous.LinkerFlags>-Tsamd51j18a_flash.ld -std=gnu99 -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mfp16-format=ieee</armgcc.linker.miscellaneous.LinkerFlags>
+  <armgcc.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+      <Value>%24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include</Value>
+      <Value>../Config</Value>
+      <Value>../</Value>
+      <Value>../examples</Value>
+      <Value>../hal/include</Value>
+      <Value>../hal/utils/include</Value>
+      <Value>../hpl/adc</Value>
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+      <Value>../hpl/oscctrl</Value>
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+      <Value>../hpl/port</Value>
+      <Value>../hpl/qspi</Value>
+      <Value>../hpl/ramecc</Value>
+      <Value>../hpl/sercom</Value>
+      <Value>../hpl/tc</Value>
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+      <Value>../hri</Value>
+    </ListValues>
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+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
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+      <Value>../Config</Value>
+      <Value>../</Value>
+      <Value>../examples</Value>
+      <Value>../hal/include</Value>
+      <Value>../hal/utils/include</Value>
+      <Value>../hpl/adc</Value>
+      <Value>../hpl/ccl</Value>
+      <Value>../hpl/cmcc</Value>
+      <Value>../hpl/core</Value>
+      <Value>../hpl/dmac</Value>
+      <Value>../hpl/eic</Value>
+      <Value>../hpl/evsys</Value>
+      <Value>../hpl/gclk</Value>
+      <Value>../hpl/mclk</Value>
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+      <Value>../hpl/oscctrl</Value>
+      <Value>../hpl/pm</Value>
+      <Value>../hpl/port</Value>
+      <Value>../hpl/qspi</Value>
+      <Value>../hpl/ramecc</Value>
+      <Value>../hpl/sercom</Value>
+      <Value>../hpl/tc</Value>
+      <Value>../hpl/tcc</Value>
+      <Value>../hri</Value>
+    </ListValues>
+  </armgcc.preprocessingassembler.general.IncludePaths>
+  <armgcc.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcc.preprocessingassembler.debugging.DebugLevel>
+</ArmGcc>

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Default.xml

@@ -0,0 +1,475 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Configurations xmlns:i="http://www.w3.org/2001/XMLSchema-instance" z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/" xmlns="DefaultValues">
+	<Configurations>
+		<Configuration z:Id="i2">
+			<Compiler_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:KeyValueOfstringstring>
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+					<d4p1:Value>None</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>IncludePaths</d4p1:Key>
+					<d4p1:Value>NDEBUG</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>MiscellaneousSettings</d4p1:Key>
+					<d4p1:Value>-std=gnu99</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>OptimizationLevel</d4p1:Key>
+					<d4p1:Value>Optimize for size (-Os)</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>SymbolDefines</d4p1:Key>
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+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
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+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>Verbose</d4p1:Key>
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+					<d4p1:Key>armgcc.linker.general.DoNotUseStandardStartFiles</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.DoNotUseDefaultLibraries</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.NoStartupOrDefaultLibs</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.OmitAllSymbolInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.NoSharedLibraries</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.GenerateMAPFile</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.UseNewlibNano</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.AdditionalSpecs</d4p1:Key>
+					<d4p1:Value>None</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.GarbageCollectUnusedSections</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.EnableFastMath</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.GeneratePositionIndependentCode</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.Flash</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.Sram</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.ExternalRAM</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.miscellaneous.OtherOptions</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.miscellaneous.OtherObjects</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+			</Linker_dictionary>
+			<Name>Debug</Name>
+		</Configuration>
+	</Configurations>
+</Configurations>

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/samd51j18a_flash.ld

@@ -0,0 +1,163 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD51J18A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
+  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    .bkupram (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sbkupram = .;
+        *(.bkupram .bkupram.*);
+        . = ALIGN(8);
+        _ebkupram = .;
+    } > bkupram
+
+    .qspi (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sqspi = .;
+        *(.qspi .qspi.*);
+        . = ALIGN(8);
+        _eqspi = .;
+    } > qspi
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/samd51j18a_sram.ld

@@ -0,0 +1,162 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD51J18A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
+  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    .bkupram (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sbkupram = .;
+        *(.bkupram .bkupram.*);
+        . = ALIGN(8);
+        _ebkupram = .;
+    } > bkupram
+
+    .qspi (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sqspi = .;
+        *(.qspi .qspi.*);
+        . = ALIGN(8);
+        _eqspi = .;
+    } > qspi
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/startup_samd51.c

@@ -0,0 +1,546 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAMD51
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd51.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&_estack),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+        uint32_t *pSrc, *pDest;
+
+        /* Initialize the relocate segment */
+        pSrc = &_etext;
+        pDest = &_srelocate;
+
+        if (pSrc != pDest) {
+                for (; pDest < &_erelocate;) {
+                        *pDest++ = *pSrc++;
+                }
+        }
+
+        /* Clear the zero segment */
+        for (pDest = &_szero; pDest < &_ezero;) {
+                *pDest++ = 0;
+        }
+
+        /* Set the vector table base address */
+        pSrc = (uint32_t *) & _sfixed;
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+#if __FPU_USED
+        /* Enable FPU */
+        SCB->CPACR |=  (0xFu << 20);
+        __DSB();
+        __ISB();
+#endif
+
+        /* Initialize the C library */
+        __libc_init_array();
+
+        /* Branch to main function */
+        main();
+
+        /* Infinite loop */
+        while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Device_Startup/system_samd51.c

@@ -0,0 +1,64 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd51.h"
+
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ *  the source for the main clock at chip startup.
+ */
+#define __SYSTEM_CLOCK    (48000000)
+
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Initialize the system
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void)
+{
+        // Keep the default device state after reset
+        SystemCoreClock = __SYSTEM_CLOCK;
+        return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+        // Not implemented
+        SystemCoreClock = __SYSTEM_CLOCK;
+        return;
+}

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_QSPI.c

@@ -0,0 +1,219 @@
+/*
+ * Ethercat_QSPI.c
+ *
+ * Created: 31/07/2021 17:52:21
+ *  Author: Nick-XMG
+ */ 
+
+#include "Ethercat_QSPI.h"
+#include <hpl_qspi_config.h>
+#include <hpl_sercom_config.h>
+
+#define SQI_READ				(0x0B<<16)
#define SQI_WRITE				(0x02<<16)
#define SQI_INC					(0x40<<8)
#define SQI_DEC					(0x80<<8)
+#define ECAT_PRAM_RD_DATA		0x0000
#define ECAT_PRAM_WR_DATA		0x0020
#define HW_CFG					0x0074
#define	BYTE_TEST				0x0064
#define ECAT_PRAM_RD_ADDR_LEN	0x0308
#define ECAT_PRAM_RD_CMD		0x030C
#define ECAT_PRAM_WR_ADDR_LEN	0x0310
#define ECAT_PRAM_WR_CMD		0x0314

#define LAN9252_RDY				(1<<27)

#define PDRAM_RD_ADDRESS		0x1100
#define PDRAM_RD_LENGTH			ECAT_SIZE_RD //do the math later to automatize. fixed to 64 for now.
#define PDRAM_WR_ADDRESS		0x1800
#define PDRAM_WR_LENGTH			ECAT_SIZE_WR
#define PDRAM_LENGTH_MAX		64
+#define PDRAM_LENGTH_SHORT		32
+#define FIFO_DEPTH				16
+#define PDRAM_REG_MAX			PDRAM_LENGTH_SHORT/4
+#define PRAM_X_ABORT			(1<<30)
+#define CSR_BUSY				0x80000000
+
+COMPILER_ALIGNED(16)
+DmacDescriptor dummy_rx_descriptor;
+DmacDescriptor dummy_tx_descriptor;
+
+volatile uint32_t QSPI_tx_buffer[buffer_size]={0};
+volatile uint32_t QSPI_rx_buffer[buffer_size]={0};
+
+volatile enum ecat_states ecat_state = wait;
+volatile enum ecat_states next_ecat_state = wait;
+
+volatile uint8_t wr_cnt = 0;
+volatile uint8_t rd_cnt = 0;
+
+static uint8_t sync_rx_buffer[2*2*buffer_size/3]={0};
+static uint8_t sync_tx_buffer[2*2*buffer_size/3]={0xED};
+
+
+static uint32_t QSPI_cmds[]={0,PRAM_X_ABORT,0,PRAM_X_ABORT,
+							 ((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS,						CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS,CSR_BUSY,
+							 ((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX,	CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX,CSR_BUSY,
+							 ((PDRAM_LENGTH_MAX)<<16)+PDRAM_RD_ADDRESS+PDRAM_LENGTH_MAX*2,	CSR_BUSY,(PDRAM_LENGTH_MAX<<16)+PDRAM_WR_ADDRESS+PDRAM_LENGTH_MAX*2,CSR_BUSY,
+							 };
+			
+static uint32_t zero[FIFO_DEPTH]={0};	
+				
+volatile uint32_t status = 0;	
+	
+	struct _qspi_command rd_cmd = {
+	.inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
+	 .inst_frame.bits.inst_en = 0,
+	 .inst_frame.bits.data_en = 1,
+	 .inst_frame.bits.addr_en = 1,
+	 .inst_frame.bits.dummy_cycles = 6,
+	 .inst_frame.bits.tfr_type = QSPI_READMEM_ACCESS,
+ };	
+ 
+ struct _qspi_command wr_cmd = {
+	 .inst_frame.bits.width = QSPI_INST4_ADDR4_DATA4,
+	 .inst_frame.bits.inst_en = 0,
+	 .inst_frame.bits.data_en = 1,
+	 .inst_frame.bits.addr_en = 1,
+	 .inst_frame.bits.dummy_cycles = 0,
+	 .inst_frame.bits.tfr_type = QSPI_WRITEMEM_ACCESS,
+ };	
+ 
+ struct _qspi_command qspi_cmd = {
+	 .inst_frame.bits.width = QSPI_INST1_ADDR1_DATA1,
+	 .inst_frame.bits.inst_en = 1,
+	 .inst_frame.bits.data_en = 0,
+	 .inst_frame.bits.addr_en = 0,
+	 .inst_frame.bits.dummy_cycles = 0,
+	 .instruction = 0x38,
+	 .inst_frame.bits.tfr_type = QSPI_WRITE_ACCESS,
+ };
+ 
+struct _qspi_command *spi_cmd= &wr_cmd;
+volatile uint8_t tx_complete =3;
+volatile uint32_t *ECAT_BYTE_TEST=			QSPI_AHB+BYTE_TEST+SQI_READ;
+volatile uint32_t *ECAT_FIFO_RD_RD=			QSPI_AHB+SQI_READ +ECAT_PRAM_RD_DATA;
+//volatile uint32_t *ECAT_FIFO_RD_RD=			QSPI_AHB+SQI_READ +SQI_INC+ECAT_PRAM_RD_DATA;
+
+volatile uint32_t *ECAT_FIFO_WR_WR=			QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_DATA;
+//volatile uint32_t *ECAT_FIFO_WR_WR=			QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_DATA;
+
+volatile uint32_t *ECAT_HW_CFG_RD=			QSPI_AHB+SQI_READ+HW_CFG;
+volatile uint32_t *ECAT_FIFO_RD_ADLEN_WR=   QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_RD_ADDR_LEN;
+volatile uint32_t *ECAT_FIFO_WR_ADLEN_WR=   QSPI_AHB+SQI_WRITE+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
+volatile uint32_t *ECAT_FIFO_WR_ADLEN_RD=   QSPI_AHB+SQI_READ+SQI_INC+ECAT_PRAM_WR_ADDR_LEN;
+volatile uint32_t *ECAT_FIFO_WR_CMD_RD=		QSPI_AHB+SQI_READ+ECAT_PRAM_WR_CMD;
+volatile uint32_t *ECAT_FIFO_WR_CMD_WR=		QSPI_AHB+SQI_WRITE+ECAT_PRAM_WR_CMD;
+ 
+volatile uint32_t *INPUT_ADDRESS ;
+volatile uint32_t *OUTPUT_ADDRESS;
+volatile uint32_t read_buffer =0;
+volatile uint8_t ecat_length= 0;
+
+volatile bool run_ECAT = false;
+volatile bool synced = false;
+
+void ECAT_STATE_MACHINE(void){
+	if ((ecat_state != wait)&(ecat_state != wait2)){
+		run_ECAT = false;
+		switch(ecat_state){
+		case en_SQI:
+			spi_cmd = &qspi_cmd;
+			QSPI->INSTRCTRL.bit.INSTR=spi_cmd->instruction;
+			OUTPUT_ADDRESS = ECAT_FIFO_RD_ADLEN_WR;
+			INPUT_ADDRESS = &QSPI_cmds[0];
+			ecat_length = 0;
+			next_ecat_state = rd_rdy;
+			
+			break;
+		case rd_rdy:
+			if (QSPI_rx_buffer[0]==LAN9252_RDY){
+				next_ecat_state = abort_fifo;
+			}
+			else if (QSPI_rx_buffer[0]== 0xFFFFFFFF){
+				next_ecat_state = en_SQI;
+				QSPI_rx_buffer[0] = 0;
+			}
+			else{
+			spi_cmd = &rd_cmd;
+			OUTPUT_ADDRESS = &QSPI_rx_buffer[0];
+			INPUT_ADDRESS = ECAT_HW_CFG_RD;
+			ecat_length = 1;
+			wr_cnt=0;
+			}
+		
+		break;
+		case abort_fifo:	
+			spi_cmd = &wr_cmd;
+			OUTPUT_ADDRESS = ECAT_FIFO_WR_CMD_WR;
+			INPUT_ADDRESS = &QSPI_cmds[1];
+			ecat_length = 1;
+			next_ecat_state = dlt_rdram;
+			wr_cnt=0;
+			rd_cnt=0;
+		break;
+		case dlt_rdram:
+			spi_cmd = &wr_cmd;
+			OUTPUT_ADDRESS = ECAT_FIFO_WR_WR;
+			INPUT_ADDRESS = &zero[0];
+			//if (wr_cnt >= 1) ecat_length = FIFO_DEPTH/2;
+			//else ecat_length = FIFO_DEPTH;
+			ecat_length = FIFO_DEPTH;
+			next_ecat_state = cf_dlt_rdram;
+		break;
+		case cf_dlt_rdram:
+			spi_cmd = &wr_cmd;
+			OUTPUT_ADDRESS = ECAT_FIFO_WR_ADLEN_WR;
+			INPUT_ADDRESS = &QSPI_cmds[4*(wr_cnt+1)];
+			ecat_length = 2;
+			if (wr_cnt >= 2) {
+				next_ecat_state = wait;
+				wr_cnt =0;
+			} else {
+				next_ecat_state = dlt_rdram;
+				wr_cnt++;
+			}
+			
+		break;
+		case write_fifo:
+			spi_cmd = &wr_cmd;
+			OUTPUT_ADDRESS = ECAT_FIFO_WR_WR;
+			INPUT_ADDRESS = &QSPI_tx_buffer[wr_cnt*FIFO_DEPTH];
+			/*if (wr_cnt >= 1) ecat_length = FIFO_DEPTH/2;
+			else ecat_length = FIFO_DEPTH;*/
+			ecat_length = FIFO_DEPTH;
+			next_ecat_state = config_fifo;
+		break;
+		case config_fifo:	
+			spi_cmd = &wr_cmd;
+			OUTPUT_ADDRESS = ECAT_FIFO_RD_ADLEN_WR;
+			INPUT_ADDRESS = &QSPI_cmds[4*(wr_cnt+1)];
+			ecat_length = 4;
+			next_ecat_state = read_fifo;
+		break;
+		case read_fifo:	
+			spi_cmd = &rd_cmd;
+			OUTPUT_ADDRESS = &QSPI_rx_buffer[wr_cnt*FIFO_DEPTH];
+			INPUT_ADDRESS = ECAT_FIFO_RD_RD;
+			ecat_length = FIFO_DEPTH;
+			if (wr_cnt >= 2) {
+//				ecat_length = FIFO_DEPTH/2;
+				next_ecat_state = wait2;
+				wr_cnt=0;
+				}
+			else {
+//				ecat_length = FIFO_DEPTH;
+				next_ecat_state = write_fifo;
+				wr_cnt++;
+			}	
+		break;
+		}
+		qspi_dma_enable(&ECAT_QSPI);
+		QSPI->INSTRFRAME.reg = ((*spi_cmd).inst_frame.word);
+		for (uint8_t i=0;i<ecat_length;i++)
+		{
+		*(OUTPUT_ADDRESS+i) = *(INPUT_ADDRESS+i);
+		}
+		QSPI->CTRLA.bit.LASTXFER = 1;	
+		ecat_state = next_ecat_state; 
+	}
+}
+
+void config_qspi()
+{
+	QSPI->INTENSET.bit.CSRISE = 1;
+	NVIC_EnableIRQ(QSPI_IRQn);
+	NVIC_SetPriority(QSPI_IRQn, 3);
+	ecat_state =en_SQI;
+}
+
+QSPI_Handler(){
+	if (QSPI->INTFLAG.bit.CSRISE == 1){
+		QSPI->INTFLAG.bit.CSRISE = 1;
+		run_ECAT =true;
+	}
+}
+

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_QSPI.h

@@ -0,0 +1,38 @@
+/*
+ * EtherCAT_QSPI.h
+ *
+ * Created: 31/07/2021 17:51:24
+ *  Author: Nick-XMG
+ */ 
+#ifndef ETHERCAT_QSPI_H_
+#define ETHERCAT_QSPI_H_
+
+#include "atmel_start.h"
+
+
+#define ECAT_SIZE_WR			64 //max fifo size
+#define ECAT_SIZE_RD			ECAT_SIZE_WR
+#define ECAT_SIZE_WR_REG		ECAT_SIZE_WR/4
+#define ECAT_SIZE_RD_REG		ECAT_SIZE_WR/4
+
+#define buffer_size			3*ECAT_SIZE_WR_REG  //changed to double
+#define motor_buffer_size	buffer_size/3
+
+
+extern enum ecat_states {abort_fifo,dlt_rdram,cf_dlt_rdram,write_fifo,config_fifo,read_fifo,wait,wait2,en_SQI,temp,rd_rdy};
+extern volatile enum ecat_states ecat_state;
+extern volatile enum ecat_states next_ecat_state;
+
+volatile uint32_t QSPI_tx_buffer[buffer_size];
+volatile uint32_t QSPI_rx_buffer[buffer_size];
+
+//static uint32_t QSPI_tx_buffer[buffer_size] =  {47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,
+												 //31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,
+												 //15,14,13,12,11,10, 9,8,7,6,5,4,3,2,1,0};
+//static uint32_t QSPI_rx_buffer[buffer_size] =	{0};
+extern volatile bool run_ECAT;
+void config_qspi(void);
+
+
+
+#endif /* ETHERCAT_QSPI_H_ */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Ethercat_SlaveDef.h

@@ -0,0 +1,352 @@
+/*
+ * EtherCAT_SlaveDef.h
+ *
+ * Created: 01/08/2021 12:56:16
+ *  Author: Nick-XMG
+ */ 
+
+
+#ifndef ETHERCAT_SLAVEDEF_H_
+#define ETHERCAT_SLAVEDEF_H_
+
+#include "Ethercat_QSPI.h"
+#include "arm_math.h"
+#include "ADS1299.h"
+
+extern volatile uint8_t _ads1299_reg_data[24];
+extern volatile int32_t _ads1299_channel_data[9];
+extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
+
+
+//Write To Ecat Total Bytes (XX bytes)
+/* Motor 1*/
+static volatile uint8_t  *M1_Status				    =	(uint8_t *)&QSPI_tx_buffer[0];
+static volatile uint8_t	 *M1_Mode					= (((uint8_t *)&QSPI_tx_buffer[0])+1);
+static volatile int16_t  *M1_Joint_rel_position		= (((int16_t *)&QSPI_tx_buffer[0])+1);
+static volatile int16_t  *M1_Joint_abs_position		=  ((int16_t *)&QSPI_tx_buffer[1]);
+static volatile int16_t  *M1_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[1])+1);
+static volatile int16_t  *M1_Motor_current_bus		=  ((int16_t *)&QSPI_tx_buffer[2]);
+static volatile int16_t  *M1_Motor_currentPhA		= (((int16_t *)&QSPI_tx_buffer[2])+1);
+static volatile int16_t  *M1_Motor_currentPhB		=  ((int16_t *)&QSPI_tx_buffer[3]);
+static volatile int16_t  *M1_Motor_currentPhC		= (((int16_t *)&QSPI_tx_buffer[3])+1);
+static volatile int16_t  *M1_Motor__hallState		=  ((int16_t *)&QSPI_tx_buffer[4]);
+static volatile int16_t  *M1_Motor_dutyCycle		= (((int16_t *)&QSPI_tx_buffer[4])+1);
+/* Motor 2*/
+static volatile uint8_t  *M2_Status				    =	(uint8_t *)&QSPI_tx_buffer[5];
+static volatile uint8_t	 *M2_Mode					= (((uint8_t *)&QSPI_tx_buffer[5])+1);
+static volatile int16_t  *M2_Joint_rel_position		= (((int16_t *)&QSPI_tx_buffer[5])+1);
+static volatile int16_t  *M2_Joint_abs_position		=  ((int16_t *)&QSPI_tx_buffer[6]);
+static volatile int16_t  *M2_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[6])+1);
+static volatile int16_t  *M2_Motor_current_bus		=  ((int16_t *)&QSPI_tx_buffer[7]);
+static volatile int16_t  *M2_Motor_currentPhA		= (((int16_t *)&QSPI_tx_buffer[7])+1);
+static volatile int16_t  *M2_Motor_currentPhB		=  ((int16_t *)&QSPI_tx_buffer[8]);
+static volatile int16_t  *M2_Motor_currentPhC		= (((int16_t *)&QSPI_tx_buffer[8])+1);
+static volatile int16_t  *M2_Motor__hallState		=  ((int16_t *)&QSPI_tx_buffer[9]);
+static volatile int16_t  *M2_Motor_dutyCycle		= (((int16_t *)&QSPI_tx_buffer[9])+1);
+/* EMG */
+static volatile int32_t  *EMG_CH1					= (((int32_t *)&QSPI_tx_buffer[10]));
+static volatile int32_t  *EMG_CH2					= (((int32_t *)&QSPI_tx_buffer[11]));
+static volatile int32_t  *EMG_CH3					= (((int32_t *)&QSPI_tx_buffer[12]));
+static volatile int32_t  *EMG_CH4					= (((int32_t *)&QSPI_tx_buffer[13]));
+
+/* Reserved space */
+static volatile int16_t  *Spare1_tx					= (((int16_t *)&QSPI_tx_buffer[14]));
+static volatile int16_t  *Spare2_tx					= (((int16_t *)&QSPI_tx_buffer[14])+1);
+static volatile int16_t  *Spare3_tx					= (((int16_t *)&QSPI_tx_buffer[15]));
+static volatile int16_t  *Spare4_tx					= (((int16_t *)&QSPI_tx_buffer[15])+1);
+
+/* Motor 3*/
+static volatile uint8_t  *M3_Status				    =	(uint8_t *)&QSPI_tx_buffer[16];
+static volatile uint8_t	 *M3_Mode					= (((uint8_t *)&QSPI_tx_buffer[16])+1);
+static volatile int16_t  *M3_Joint_rel_position		= (((int16_t *)&QSPI_tx_buffer[16])+1);
+static volatile int16_t  *M3_Joint_abs_position		=  ((int16_t *)&QSPI_tx_buffer[17]);
+static volatile int16_t  *M3_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[17])+1);
+static volatile int16_t  *M3_Motor_current_bus		=  ((int16_t *)&QSPI_tx_buffer[18]);
+static volatile int16_t  *M3_Motor_currentPhA		= (((int16_t *)&QSPI_tx_buffer[18])+1);
+static volatile int16_t  *M3_Motor_currentPhB		=  ((int16_t *)&QSPI_tx_buffer[19]);
+static volatile int16_t  *M3_Motor_currentPhC		= (((int16_t *)&QSPI_tx_buffer[19])+1);
+static volatile int16_t  *M3_Motor__hallState		=  ((int16_t *)&QSPI_tx_buffer[20]);
+static volatile int16_t  *M3_Motor_dutyCycle		= (((int16_t *)&QSPI_tx_buffer[20])+1);
+/* Motor 4*/
+static volatile uint8_t  *M4_Status				    =	(uint8_t *)&QSPI_tx_buffer[21];
+static volatile uint8_t	 *M4_Mode					= (((uint8_t *)&QSPI_tx_buffer[21])+1);
+static volatile int16_t  *M4_Joint_rel_position		= (((int16_t *)&QSPI_tx_buffer[21])+1);
+static volatile int16_t  *M4_Joint_abs_position		=  ((int16_t *)&QSPI_tx_buffer[22]);
+static volatile int16_t  *M4_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[22])+1);
+static volatile int16_t  *M4_Motor_current_bus		=  ((int16_t *)&QSPI_tx_buffer[23]);
+static volatile int16_t  *M4_Motor_currentPhA		= (((int16_t *)&QSPI_tx_buffer[23])+1);
+static volatile int16_t  *M4_Motor_currentPhB		=  ((int16_t *)&QSPI_tx_buffer[24]);
+static volatile int16_t  *M4_Motor_currentPhC		= (((int16_t *)&QSPI_tx_buffer[24])+1);
+static volatile int16_t  *M4_Motor__hallState		=  ((int16_t *)&QSPI_tx_buffer[25]);
+static volatile int16_t  *M4_Motor_dutyCycle		= (((int16_t *)&QSPI_tx_buffer[25])+1);
+/* IMU */
+static volatile int16_t  *q_x0						= (((int16_t *)&QSPI_tx_buffer[26]));
+static volatile int16_t  *q_y0						= (((int16_t *)&QSPI_tx_buffer[26])+1);
+static volatile int16_t  *q_z0						= (((int16_t *)&QSPI_tx_buffer[27]));
+static volatile int16_t  *q_w0						= (((int16_t *)&QSPI_tx_buffer[27])+1);
+/* EMG */
+static volatile int16_t  *FSR_CH1					= (((int16_t *)&QSPI_tx_buffer[28]));
+static volatile int16_t  *FSR_CH2					= (((int16_t *)&QSPI_tx_buffer[28])+1);
+static volatile int16_t  *FSR_CH3					= (((int16_t *)&QSPI_tx_buffer[29]));
+static volatile int16_t  *FSR_CH4					= (((int16_t *)&QSPI_tx_buffer[29])+1);
+static volatile int16_t  *FSR_CH5					= (((int16_t *)&QSPI_tx_buffer[30]));
+static volatile int16_t  *Pressure_CH1				= (((int16_t *)&QSPI_tx_buffer[30])+1);
+static volatile int16_t  *Pressure_CH2				= (((int16_t *)&QSPI_tx_buffer[31]));
+static volatile int16_t  *Pressure_CH3				= (((int16_t *)&QSPI_tx_buffer[31])+1);
+
+//Read From Ecat Total (XX Bytes)
+//QSPI_rx_buffer
+/* Motor 1*/
+static volatile uint8_t  *M1_Control_mode			= ((uint8_t *)&QSPI_rx_buffer[0]);
+static volatile uint8_t	 *M1_Control_set			= (((uint8_t *)&QSPI_rx_buffer[0])+1);
+static volatile int16_t  *M1_Desired_pos			= ((int16_t *)&QSPI_rx_buffer[0]+1);
+static volatile int16_t  *M1_Desired_speed			= ((int16_t *)&QSPI_rx_buffer[1]);
+static volatile int16_t  *M1_Desired_current		= ((int16_t *)&QSPI_rx_buffer[1]+1);
+static volatile int16_t  *M1_Max_pos				= ((int16_t *)&QSPI_rx_buffer[2]);
+static volatile int16_t  *M1_Max_velocity			= ((int16_t *)&QSPI_rx_buffer[2]+1);
+static volatile int16_t  *M1_Max_current			= ((int16_t *)&QSPI_rx_buffer[3]);
+static volatile int16_t  *M1_Desired_dc				= ((int16_t *)&QSPI_rx_buffer[3]+1); //Spare
+///* Motor 2*/
+static volatile uint8_t  *M2_Control_mode			= ((uint8_t *)&QSPI_rx_buffer[4]);
+static volatile uint8_t	 *M2_Control_set			= (((uint8_t *)&QSPI_rx_buffer[4])+1);
+static volatile int16_t  *M2_Desired_pos			= ((int16_t *)&QSPI_rx_buffer[4]+1);
+static volatile int16_t  *M2_Desired_speed			= ((int16_t *)&QSPI_rx_buffer[5]);
+static volatile int16_t  *M2_Desired_current		= ((int16_t *)&QSPI_rx_buffer[5]+1);
+static volatile int16_t  *M2_Max_pos				= ((int16_t *)&QSPI_rx_buffer[6]);
+static volatile int16_t  *M2_Max_velocity			= ((int16_t *)&QSPI_rx_buffer[6]+1);
+static volatile int16_t  *M2_Max_current			= ((int16_t *)&QSPI_rx_buffer[7]);
+static volatile int16_t  *M2_Desired_dc				= ((int16_t *)&QSPI_rx_buffer[7]+1); //Spare
+
+/* Reserved space */
+/* 64 bytes reserved for each */
+static volatile int16_t  *Spare1_rx					= ((int16_t *)&QSPI_rx_buffer[8]);		//Spare
+static volatile int16_t  *Spare2_rx					= ((int16_t *)&QSPI_rx_buffer[8]+1);	//Spare
+static volatile int16_t  *Spare3_rx					= ((int16_t *)&QSPI_rx_buffer[9]);		//Spare
+static volatile int16_t  *Spare4_rx					= ((int16_t *)&QSPI_rx_buffer[9]+1);	//Spare
+static volatile int16_t  *Spare5_rx					= ((int16_t *)&QSPI_rx_buffer[10]);		//Spare
+static volatile int16_t  *Spare6_rx					= ((int16_t *)&QSPI_rx_buffer[10]+1);	//Spare
+static volatile int16_t  *Spare7_rx					= ((int16_t *)&QSPI_rx_buffer[11]);		//Spare
+static volatile int16_t  *Spare8_rx					= ((int16_t *)&QSPI_rx_buffer[11]+1);	//Spare
+static volatile int16_t  *Spare9_rx					= ((int16_t *)&QSPI_rx_buffer[12]);		//Spare
+static volatile int16_t  *Spare10_rx				= ((int16_t *)&QSPI_rx_buffer[12]+1);	//Spare
+static volatile int16_t  *Spare11_rx				= ((int16_t *)&QSPI_rx_buffer[13]);		//Spare
+static volatile int16_t  *Spare12_rx				= ((int16_t *)&QSPI_rx_buffer[13]+1);	//Spare
+static volatile int16_t  *Spare13_rx				= ((int16_t *)&QSPI_rx_buffer[14]);		//Spare
+static volatile int16_t  *Spare14_rx				= ((int16_t *)&QSPI_rx_buffer[14]+1);	//Spare
+static volatile int16_t  *Spare15_rx				= ((int16_t *)&QSPI_rx_buffer[15]);		//Spare
+static volatile int16_t  *Spare16_rx				= ((int16_t *)&QSPI_rx_buffer[15]+1);	//Spare
+
+///* Motor 3*/
+static volatile uint8_t  *M3_Control_mode			= ((uint8_t *)&QSPI_rx_buffer[16]);
+static volatile uint8_t	 *M3_Control_set			= (((uint8_t *)&QSPI_rx_buffer[16])+1);
+static volatile int16_t  *M3_Desired_pos			= ((int16_t *)&QSPI_rx_buffer[16]+1);
+static volatile int16_t  *M3_Desired_speed			= ((int16_t *)&QSPI_rx_buffer[17]);
+static volatile int16_t  *M3_Desired_current		= ((int16_t *)&QSPI_rx_buffer[17]+1);
+static volatile int16_t  *M3_Max_pos				= ((int16_t *)&QSPI_rx_buffer[18]);
+static volatile int16_t  *M3_Max_velocity			= ((int16_t *)&QSPI_rx_buffer[18]+1);
+static volatile int16_t  *M3_Max_current			= ((int16_t *)&QSPI_rx_buffer[19]);
+static volatile int16_t  *M3_Spare					= ((int16_t *)&QSPI_rx_buffer[19]+1); //Spare
+///* Motor 4*/
+static volatile uint8_t  *M4_Control_mode			= ((uint8_t *)&QSPI_rx_buffer[20]);
+static volatile uint8_t	 *M4_Control_set			= (((uint8_t *)&QSPI_rx_buffer[20])+1);
+static volatile int16_t  *M4_Desired_pos			= ((int16_t *)&QSPI_rx_buffer[20]+1);
+static volatile int16_t  *M4_Desired_speed			= ((int16_t *)&QSPI_rx_buffer[21]);
+static volatile int16_t  *M4_Desired_current		= ((int16_t *)&QSPI_rx_buffer[21]+1);
+static volatile int16_t  *M4_Max_pos				= ((int16_t *)&QSPI_rx_buffer[22]);
+static volatile int16_t  *M4_Max_velocity			= ((int16_t *)&QSPI_rx_buffer[22]+1);
+static volatile int16_t  *M4_Max_current			= ((int16_t *)&QSPI_rx_buffer[23]);
+static volatile int16_t  *M4_Spare					= ((int16_t *)&QSPI_rx_buffer[23]+1); //Spare
+
+static void update_telemetry(void)
+{
+	inline int16_t convert_to_mA(volatile float32_t current_PU)
+	{
+		return (int16_t)(current_PU*1000.0f);
+	}
+	//
+	//*M1_Status				    = 0;
+	//*M1_Mode					= 0;
+	
+	/* Motor 1 */
+	*M1_Status					= Motor1.motor_state.fault;
+	*M1_Mode					= Motor1.motor_state.currentstate;
+	*M1_Joint_rel_position		= Motor1.motor_status.Num_Steps;
+	*M1_Joint_abs_position		= Motor1.motor_setpoints.desired_position + 1 ;
+	//*M1_Joint_abs_position		= Motor1.motor_status.abs_position;
+	//*M1_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[1])+1);
+	*M1_Motor_current_bus		= convert_to_mA(Motor1.Iphase_pu.Bus);
+	*M1_Motor_currentPhA		= convert_to_mA(Motor1.Iphase_pu.A);
+	*M1_Motor_currentPhB		= convert_to_mA(Motor1.Iphase_pu.B);
+	*M1_Motor_currentPhC		= convert_to_mA(Motor1.Iphase_pu.C);
+	*M1_Motor__hallState		= Motor1.motor_status.currentHallPattern;
+	*M1_Motor_dutyCycle			= Motor1.motor_status.duty_cycle;
+	*M1_Motor_speed				= (int16_t)Motor1.motor_status.calc_rpm;
+	//*M1_Joint_abs_position		= Motor1.motor_status.actualDirection;
+	/* Motor 2 */
+	*M2_Status					= Motor2.motor_state.fault;
+	*M2_Mode					= Motor2.motor_state.currentstate;
+	*M2_Joint_rel_position		= Motor2.motor_status.Num_Steps;
+	//*M2_Joint_abs_position		= Motor2.motor_status.abs_position;
+	*M2_Joint_abs_position		= Motor2.motor_setpoints.desired_position + 1 ;
+	//*M1_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[1])+1);
+	*M2_Motor_current_bus		= convert_to_mA( Motor2.Iphase_pu.Bus);
+	*M2_Motor_currentPhA		= convert_to_mA( Motor2.Iphase_pu.A); 
+	*M2_Motor_currentPhB		= convert_to_mA( Motor2.Iphase_pu.B); 
+	*M2_Motor_currentPhC		= convert_to_mA(Motor2.Iphase_pu.C);
+	*M2_Motor__hallState		= Motor2.motor_status.currentHallPattern;
+	*M2_Motor_dutyCycle			= Motor2.motor_status.duty_cycle;
+	*M2_Motor_speed				= (int16_t)Motor2.motor_status.calc_rpm;
+	//*M2_Joint_abs_position		= Motor2.motor_status.actualDirection;
+	
+	*EMG_CH1					= _ads1299_channel_data[0];
+	*EMG_CH2					= _ads1299_channel_data[1];
+	*EMG_CH3					= _ads1299_channel_data[2];
+	*EMG_CH4					= _ads1299_channel_data[3];
+	//*EMG_CH1					= 1;
+	//*EMG_CH2					= 2;
+	//*EMG_CH3					= 3;
+	//*EMG_CH4					= 4;
+}
+
+static void update_setpoints(void)
+{
+	Motor1.motor_setpoints.desired_position	= *M1_Desired_pos;
+	Motor1.motor_setpoints.desired_speed	= *M1_Desired_speed;
+	Motor1.motor_setpoints.desired_torque	= *M1_Desired_current;
+	Motor1.motor_setpoints.max_current		= *M1_Max_current;
+	Motor1.motor_setpoints.max_torque		= *M1_Max_current;
+	Motor1.motor_setpoints.max_velocity		= *M1_Max_velocity;
+	
+	Motor2.motor_setpoints.desired_position	= *M2_Desired_pos;
+	Motor2.motor_setpoints.desired_speed	= *M2_Desired_speed;
+	Motor2.motor_setpoints.desired_torque	= *M2_Desired_current;
+	Motor2.motor_setpoints.max_current		= *M2_Max_current;
+	Motor2.motor_setpoints.max_torque		= *M2_Max_current;
+	Motor2.motor_setpoints.max_velocity		= *M2_Max_velocity;
+	
+	//*M3_Desired_pos			= 1;
+	//*M3_Desired_speed		= 2;
+	//*M3_Desired_current		= 3;
+	//*M3_Max_current			= 4;
+	//*M3_Max_current			= 5;
+	//*M3_Max_velocity		= 6;
+	//
+	//*M4_Desired_pos			= 7;
+	//*M4_Desired_speed		= 8;
+	//*M4_Desired_current		= 9;
+	//*M4_Max_current         = 10;
+	//*M4_Max_current			= 11;
+	//*M4_Max_velocity		= 12;
+	
+	
+	//volatile uint8_t a = *M1_Control_mode;
+	//volatile uint8_t b = *M1_Control_set;
+	//volatile int16_t c = *M1_Desired_pos;
+	//volatile int16_t d = *M1_Desired_speed;
+	//volatile int16_t e = *M1_Desired_current;
+	//volatile int16_t f = *M1_Max_pos;
+	//volatile int16_t g = *M1_Max_velocity;
+	//volatile int16_t h = *M1_Max_current;
+	//volatile int16_t i = *M1_Spare;
+	//inline float32_t convert_int_to_PU(volatile int16_t input)
+	//{
+		//return ((float32_t)(input/1000.0f));
+	//}
+	////Motor1.des_mode						= 0;
+	////Motor1.set							= 0;
+	//Motor1.motor_setpoints.desired_position	= *desired_position;
+	//Motor1.motor_setpoints.desired_speed	= *desired_speed;
+	////Motor1.desired_speed					= 1500;
+	//Motor1.motor_setpoints.desired_torque	= convert_int_to_PU(*desired_torque);
+	////Motor1.controllerParam.I_kp			= 0;
+	////Motor1.controllerParam.I_ki			= 0;
+	////Motor1.controllerParam.V_kp			= 0;
+	////Motor1.controllerParam.V_kd			= 0;
+	////Motor1.controllerParam.V_kd			= 0;
+	////Motor1.controllerParam.P_kp			= 0;
+	////Motor1.controllerParam.P_ki			= 0;
+	////Motor1.reductionRatio					= 0;
+	//Motor1.motor_setpoints.max_velocity		= *max_velocity;
+	//Motor1.motor_setpoints.max_current		= convert_int_to_PU(*max_current);
+	//Motor1.motor_setpoints.max_torque		= convert_int_to_PU(*max_torque);	 
+	////Motor1.Spare1							= 0;
+	////Motor1.Spare2							= 0;
+	////Motor1.Spare3							= 0;
+	////Motor1.Spare4							= 0;	 
+}
+
+
+static inline void comms_check(void)
+{
+	/* Motor 1*/
+	*M1_Status				    = 1;
+	*M1_Mode					= 2;
+	*M1_Joint_rel_position		= -3;
+	//*M1_Joint_abs_position		= 4;
+	*M1_Motor_speed				= -5;
+	*M1_Motor_current_bus		= 6;
+	*M1_Motor_currentPhA		= -7;
+	*M1_Motor_currentPhB		= 8;
+	*M1_Motor_currentPhC		= -9;
+	*M1_Motor__hallState		= 10;
+	*M1_Motor_dutyCycle			= -11;
+	/* Motor 2*/
+	*M2_Status				    = 12;
+	*M2_Mode					= 13;
+	*M2_Joint_rel_position		= 14;
+	//*M2_Joint_abs_position		= -15;
+	*M2_Motor_speed				= 16;
+	*M2_Motor_current_bus		= -17;
+	*M2_Motor_currentPhA		= 18;
+	*M2_Motor_currentPhB		= -19;
+	*M2_Motor_currentPhC		= 20;
+	*M2_Motor__hallState		= -21;
+	*M3_Motor_dutyCycle			= 22;
+	/* EMG */
+	*EMG_CH1					= -23;
+	*EMG_CH2					= 24;
+	*EMG_CH3					= -25;
+	*EMG_CH4					= 26;
+	
+	
+	/* Motor 3*/
+	*M3_Status				    = 1;
+	*M3_Mode					= 2;
+	*M3_Joint_rel_position		= -3;
+	*M3_Joint_abs_position		= 4;
+	*M3_Motor_speed				= -5;
+	*M3_Motor_current_bus		= 6;
+	*M3_Motor_currentPhA		= -7;
+	*M3_Motor_currentPhB		= 8;
+	*M3_Motor_currentPhC		= -9;
+	*M3_Motor__hallState		= 10;
+	*M3_Motor_dutyCycle			= -11;
+	/* Motor 4*/
+	*M4_Status				    = 12;
+	*M4_Mode					= 13;
+	*M4_Joint_rel_position		= 14;
+	*M4_Joint_abs_position		= -15;
+	*M4_Motor_speed				= 16;
+	*M4_Motor_current_bus		= -17;
+	*M4_Motor_currentPhA		= 18;
+	*M4_Motor_currentPhB		= -19;
+	*M4_Motor_currentPhC		= 20;
+	*M4_Motor__hallState		= -21;
+	*M4_Motor_dutyCycle			= 22;
+	/* IMU */
+	*q_x0						= 23;
+	*q_y0						= -24;
+	*q_z0						= 25;
+	*q_w0						= -26;
+	/* EMG */
+	*FSR_CH1					= 27;
+	*FSR_CH2					= -28;
+	*FSR_CH3					= 29;
+	*FSR_CH4					= -30;
+	*FSR_CH5					= 31;
+	*Pressure_CH1				= -32;
+	*Pressure_CH2				= 33;
+	*Pressure_CH3				= -34;	
+}
+
+#endif /* ETHERCAT_SLAVEDEF_H_ */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/MSIF_slave.h

@@ -0,0 +1,287 @@
+/*
+ * master_slave_IF.h
+ *
+ * Created: 8/18/2021 4:32:19 PM
+ *  Author: ge37vez
+ */ 
+
+
+#ifndef MASTER_SLAVE_IF_H_
+#define MASTER_SLAVE_IF_H_
+
+#include "bldc.h"
+
+#define SLAVE_BUFFER_SIZE_BYTES	64
+#define SLAVE_BUFFER_SIZE_LONG	SLAVE_BUFFER_SIZE_BYTES/4
+
+static uint32_t SPI_rx_buffer[SLAVE_BUFFER_SIZE_LONG] =	{0};
+static uint32_t SPI_tx_buffer[SLAVE_BUFFER_SIZE_LONG] =	{0};
+
+//static uint8_t SPI_tx_buffer[SLAVE_BUFFER_SIZE] =	{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,
+													//18,19,20,21,22,23,24,25,26,27,28,29,30,31};
+
+//tx_buffer
+/* Motor 3*/
+static volatile uint8_t  *M3_Status				    =	(uint8_t *)&SPI_tx_buffer[0];
+static volatile uint8_t	 *M3_Mode					= (((uint8_t *)&SPI_tx_buffer[0])+1);
+static volatile int16_t  *M3_Joint_rel_position		= (((int16_t *)&SPI_tx_buffer[0])+1);
+static volatile int16_t  *M3_Joint_abs_position		=  ((int16_t *)&SPI_tx_buffer[1]);
+static volatile int16_t  *M3_Motor_speed			= (((int16_t *)&SPI_tx_buffer[1])+1);
+static volatile int16_t  *M3_Motor_current_bus		=  ((int16_t *)&SPI_tx_buffer[2]);
+static volatile int16_t  *M3_Motor_currentPhA		= (((int16_t *)&SPI_tx_buffer[2])+1);
+static volatile int16_t  *M3_Motor_currentPhB		=  ((int16_t *)&SPI_tx_buffer[3]);
+static volatile int16_t  *M3_Motor_currentPhC		= (((int16_t *)&SPI_tx_buffer[3])+1);
+static volatile int16_t  *M3_Motor__hallState		=  ((int16_t *)&SPI_tx_buffer[4]);
+static volatile int16_t  *M3_Motor_dutyCycle		= (((int16_t *)&SPI_tx_buffer[4])+1);
+/* Motor 4*/
+static volatile uint8_t  *M4_Status				    =	(uint8_t *)&SPI_tx_buffer[5];
+static volatile uint8_t	 *M4_Mode					= (((uint8_t *)&SPI_tx_buffer[5])+1);
+static volatile int16_t  *M4_Joint_rel_position		= (((int16_t *)&SPI_tx_buffer[5])+1);
+static volatile int16_t  *M4_Joint_abs_position		=  ((int16_t *)&SPI_tx_buffer[6]);
+static volatile int16_t  *M4_Motor_speed			= (((int16_t *)&SPI_tx_buffer[6])+1);
+static volatile int16_t  *M4_Motor_current_bus		=  ((int16_t *)&SPI_tx_buffer[7]);
+static volatile int16_t  *M4_Motor_currentPhA		= (((int16_t *)&SPI_tx_buffer[7])+1);
+static volatile int16_t  *M4_Motor_currentPhB		=  ((int16_t *)&SPI_tx_buffer[8]);
+static volatile int16_t  *M4_Motor_currentPhC		= (((int16_t *)&SPI_tx_buffer[8])+1);
+static volatile int16_t  *M4_Motor__hallState		=  ((int16_t *)&SPI_tx_buffer[9]);
+static volatile int16_t  *M4_Motor_dutyCycle		= (((int16_t *)&SPI_tx_buffer[9])+1);
+/* IMU */
+static volatile int16_t  *q_x0						=	(int16_t *)&SPI_tx_buffer[10];		
+static volatile int16_t  *q_y0						= (((int16_t *)&SPI_tx_buffer[10])+1);	
+static volatile int16_t  *q_z0						=	(int16_t *)&SPI_tx_buffer[11];		
+static volatile int16_t  *q_w0						= (((int16_t *)&SPI_tx_buffer[11])+1);	
+/* EMG */
+static volatile int16_t  *FSR_CH1					=   (int16_t *)&SPI_tx_buffer[12];		//2 byte - 48  of 64
+static volatile int16_t  *FSR_CH2					= (((int16_t *)&SPI_tx_buffer[12])+1);
+static volatile int16_t  *FSR_CH3					=	(int16_t *)&SPI_tx_buffer[13];		//2 byte - 52  of 64
+static volatile int16_t  *FSR_CH4					= (((int16_t *)&SPI_tx_buffer[13])+1);
+static volatile int16_t  *FSR_CH5					=	(int16_t *)&SPI_tx_buffer[14];		//2 byte - 56  of 64
+static volatile int16_t  *Pressure_CH1				= (((int16_t *)&SPI_tx_buffer[14])+1);
+static volatile int16_t  *Pressure_CH2				=	(int16_t *)&SPI_tx_buffer[15];		//2 byte - 60  of 64
+static volatile int16_t  *Pressure_CH3				= (((int16_t *)&SPI_tx_buffer[15])+1);
+
+//rx_buffer
+///* Motor 3*/
+static volatile uint8_t  *M3_Control_mode			=	 (uint8_t *)&SPI_rx_buffer[0];		//1 byte - 0  of 32
+static volatile uint8_t	 *M3_Control_set			=  (((uint8_t *)&SPI_rx_buffer[0])+1);	//1 byte - 1  of 32
+static volatile int16_t  *M3_Desired_pos			=	((int16_t *)&SPI_rx_buffer[0]+1);	//2 byte - 2  of 32
+static volatile int16_t  *M3_Desired_speed			=	 (int16_t *)&SPI_rx_buffer[1];		//2 byte - 4  of 32
+static volatile int16_t  *M3_Desired_current		=   ((int16_t *)&SPI_rx_buffer[1]+1);	//2 byte - 6  of 32
+static volatile int16_t  *M3_Max_pos				=	 (int16_t *)&SPI_rx_buffer[2];		//2 byte - 8  of 32
+static volatile int16_t  *M3_Max_velocity			=	((int16_t *)&SPI_rx_buffer[2]+1);	//2 byte - 10 of 32
+static volatile int16_t  *M3_Max_current			=	 (int16_t *)&SPI_rx_buffer[3];		//2 byte - 12 of 32
+static volatile int16_t  *M3_Spare					=	((int16_t *)&SPI_rx_buffer[3]+1);	//2 byte - 14 of 32
+///* Motor 4*/
+static volatile uint8_t  *M4_Control_mode			=	 (uint8_t *)&SPI_rx_buffer[4];		//1 byte - 16 of 32
+static volatile uint8_t	 *M4_Control_set			=  (((uint8_t *)&SPI_rx_buffer[4])+1);	//1 byte - 17 of 32
+static volatile int16_t  *M4_Desired_pos			=	((int16_t *)&SPI_rx_buffer[4]+1);	//2 byte - 18 of 32
+static volatile int16_t  *M4_Desired_speed			=	 (int16_t *)&SPI_rx_buffer[5];		//2 byte - 20 of 32
+static volatile int16_t  *M4_Desired_current		=	((int16_t *)&SPI_rx_buffer[5]+1);	//2 byte - 22 of 32
+static volatile int16_t  *M4_Max_pos				=	 (int16_t *)&SPI_rx_buffer[6];		//2 byte - 24 of 32
+static volatile int16_t  *M4_Max_velocity			=	((int16_t *)&SPI_rx_buffer[6]+1);	//2 byte - 26 of 32
+static volatile int16_t  *M4_Max_current			=	 (int16_t *)&SPI_rx_buffer[7];		//2 byte - 28 of 32
+static volatile int16_t  *M4_Spare					=	((int16_t *)&SPI_rx_buffer[7]+1);	//2 byte - 30 of 32
+
+
+////tx_buffer
+///* Motor 3*/
+//static volatile uint8_t  *M3_Status				    =	(uint8_t *)&SPI_tx_buffer[0];		//1 byte - 0  of 64
+//static volatile uint8_t	 *M3_Mode					=   (uint8_t *)&SPI_tx_buffer[1];		//1 byte - 1  of 64
+//static volatile int16_t  *M3_Joint_rel_position		=	(int16_t *)&SPI_tx_buffer[2];		//2 byte - 2  of 64
+//static volatile int16_t  *M3_Joint_abs_position		=   (int16_t *)&SPI_tx_buffer[4];		//2 byte - 4  of 64
+//static volatile int16_t  *M3_Motor_speed			=   (int16_t *)&SPI_tx_buffer[6];		//2 byte - 6  of 64
+//static volatile int16_t  *M3_Motor_current_bus		=   (int16_t *)&SPI_tx_buffer[8];		//2 byte - 8  of 64
+//static volatile int16_t  *M3_Motor_currentPhA		=   (int16_t *)&SPI_tx_buffer[10];		//2 byte - 10  of 64
+//static volatile int16_t  *M3_Motor_currentPhB		=   (int16_t *)&SPI_tx_buffer[12];		//2 byte - 12  of 64
+//static volatile int16_t  *M3_Motor_currentPhC		=   (int16_t *)&SPI_tx_buffer[14];		//2 byte - 14  of 64
+//static volatile int16_t  *M3_Motor__hallState		=   (int16_t *)&SPI_tx_buffer[16];		//2 byte - 16  of 64
+//static volatile int16_t  *M3_Motor_dutyCycle		=   (int16_t *)&SPI_tx_buffer[18];		//2 byte - 18  of 64
+///* Motor 4*/
+//static volatile uint8_t  *M4_Status				    =	(uint8_t *)&SPI_tx_buffer[20];		//1 byte - 20  of 64
+//static volatile uint8_t	 *M4_Mode					=   (uint8_t *)&SPI_tx_buffer[21];		//1 byte - 21  of 64
+//static volatile int16_t  *M4_Joint_rel_position		=	(int16_t *)&SPI_tx_buffer[22];		//2 byte - 22  of 64
+//static volatile int16_t  *M4_Joint_abs_position		=	(int16_t *)&SPI_tx_buffer[24];		//2 byte - 24  of 64
+//static volatile int16_t  *M4_Motor_speed			=	(int16_t *)&SPI_tx_buffer[26];		//2 byte - 26  of 64
+//static volatile int16_t  *M4_Motor_current_bus		=	(int16_t *)&SPI_tx_buffer[28];		//2 byte - 28  of 64
+//static volatile int16_t  *M4_Motor_currentPhA		=	(int16_t *)&SPI_tx_buffer[30];		//2 byte - 30  of 64
+//static volatile int16_t  *M4_Motor_currentPhB		=	(int16_t *)&SPI_tx_buffer[32];		//2 byte - 32  of 64
+//static volatile int16_t  *M4_Motor_currentPhC		=	(int16_t *)&SPI_tx_buffer[34];		//2 byte - 34  of 64
+//static volatile int16_t  *M4_Motor__hallState		=	(int16_t *)&SPI_tx_buffer[36];		//2 byte - 36  of 64
+//static volatile int16_t  *M4_Motor_dutyCycle		=	(int16_t *)&SPI_tx_buffer[38];		//2 byte - 38  of 64
+///* IMU */
+//static volatile int16_t  *q_x0						=	(int16_t *)&SPI_tx_buffer[40];		//2 byte - 40  of 64
+//static volatile int16_t  *q_y0						=	(int16_t *)&SPI_tx_buffer[42];		//2 byte - 42  of 64
+//static volatile int16_t  *q_z0						=	(int16_t *)&SPI_tx_buffer[44];		//2 byte - 44  of 64
+//static volatile int16_t  *q_w0						=	(int16_t *)&SPI_tx_buffer[46];		//2 byte - 46  of 64
+///* EMG */
+//static volatile int16_t  *FSR_CH1					=	(int16_t *)&SPI_tx_buffer[48];		//2 byte - 48  of 64
+//static volatile int16_t  *FSR_CH2					=	(int16_t *)&SPI_tx_buffer[50];		//2 byte - 50  of 64
+//static volatile int16_t  *FSR_CH3					=	(int16_t *)&SPI_tx_buffer[52];		//2 byte - 52  of 64
+//static volatile int16_t  *FSR_CH4					=	(int16_t *)&SPI_tx_buffer[54];		//2 byte - 54  of 64
+//static volatile int16_t  *FSR_CH5					=	(int16_t *)&SPI_tx_buffer[56];		//2 byte - 56  of 64
+//static volatile int16_t  *Pressure_CH1				=	(int16_t *)&SPI_tx_buffer[58];		//2 byte - 58  of 64
+//static volatile int16_t  *Pressure_CH2				=	(int16_t *)&SPI_tx_buffer[60];		//2 byte - 60  of 64
+//static volatile int16_t  *Pressure_CH3				=	(int16_t *)&SPI_tx_buffer[62];		//2 byte - 62  of 64
+//
+////rx_buffer
+/////* Motor 3*/
+//static volatile uint8_t  *M3_Control_mode			=	(uint8_t *)&SPI_rx_buffer[0];		//1 byte - 0  of 32
+//static volatile uint8_t	 *M3_Control_set			=	(uint8_t *)&SPI_rx_buffer[1];		//1 byte - 1  of 32
+//static volatile int16_t  *M3_Desired_pos			=	(int16_t *)&SPI_rx_buffer[2];		//2 byte - 2  of 32
+//static volatile int16_t  *M3_Desired_speed			=	(int16_t *)&SPI_rx_buffer[4];		//2 byte - 4  of 32
+//static volatile int16_t  *M3_Desired_current		=	(int16_t *)&SPI_rx_buffer[6];		//2 byte - 6  of 32
+//static volatile int16_t  *M3_Max_pos				=	(int16_t *)&SPI_rx_buffer[8];		//2 byte - 8  of 32
+//static volatile int16_t  *M3_Max_velocity			=	(int16_t *)&SPI_rx_buffer[10];		//2 byte - 10 of 32
+//static volatile int16_t  *M3_Max_current			=	(int16_t *)&SPI_rx_buffer[12];		//2 byte - 12 of 32
+//static volatile int16_t  *M3_Spare					=	(int16_t *)&SPI_rx_buffer[14];		//2 byte - 14 of 32
+/////* Motor 4*/
+//static volatile uint8_t  *M4_Control_mode			=	(int16_t *)&SPI_rx_buffer[16];		//1 byte - 16 of 32
+//static volatile uint8_t	 *M4_Control_set			=	(int16_t *)&SPI_rx_buffer[17];		//1 byte - 17 of 32
+//static volatile int16_t  *M4_Desired_pos			=	(int16_t *)&SPI_rx_buffer[18];		//2 byte - 18 of 32
+//static volatile int16_t  *M4_Desired_speed			=	(int16_t *)&SPI_rx_buffer[20];		//2 byte - 20 of 32
+//static volatile int16_t  *M4_Desired_current		=	(int16_t *)&SPI_rx_buffer[22];		//2 byte - 22 of 32
+//static volatile int16_t  *M4_Max_pos				=	(int16_t *)&SPI_rx_buffer[24];		//2 byte - 24 of 32
+//static volatile int16_t  *M4_Max_velocity			=	(int16_t *)&SPI_rx_buffer[26];		//2 byte - 26 of 32
+//static volatile int16_t  *M4_Max_current			=	(int16_t *)&SPI_rx_buffer[28];		//2 byte - 28 of 32
+//static volatile int16_t  *M4_Spare					=	(int16_t *)&SPI_rx_buffer[30];		//2 byte - 30 of 32
+
+
+
+
+static void update_telemetry(void)
+{
+	inline int16_t convert_to_mA(volatile float32_t current_PU)
+	{
+		return (int16_t)(current_PU*1000.0f);
+	}
+	//
+	//*M3_Status				    = 0;
+	//*M3_Mode					= 0;
+	
+	/* Motor 1 */
+	*M3_Status					= Motor1.motor_state.fault;
+	*M3_Mode					= Motor1.motor_state.currentstate;
+	*M3_Joint_rel_position		= Motor1.motor_status.Num_Steps;
+	*M3_Joint_abs_position		= Motor1.motor_setpoints.desired_position + 1 ;
+	//*M3_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[1]+1);
+	*M3_Motor_current_bus		= convert_to_mA(Motor1.Iphase_pu.Bus);
+	*M3_Motor_currentPhA		= convert_to_mA(Motor1.Iphase_pu.A);
+	*M3_Motor_currentPhB		= convert_to_mA(Motor1.Iphase_pu.B);
+	*M3_Motor_currentPhC		= convert_to_mA(Motor1.Iphase_pu.C);
+	*M3_Motor__hallState		= Motor1.motor_status.currentHallPattern;
+	*M3_Motor_dutyCycle			= Motor1.motor_status.duty_cycle;
+	*M3_Motor_speed				= (int16_t)Motor1.motor_status.calc_rpm;
+	//*M3_Joint_abs_position		= ;
+	/* Motor 2 */
+	*M4_Status					= Motor2.motor_state.fault;
+	*M4_Mode					= Motor2.motor_state.currentstate;
+	*M4_Joint_rel_position		= Motor2.motor_status.Num_Steps;
+	*M4_Joint_abs_position		= Motor2.motor_setpoints.desired_position + 1 ;
+	//*M3_Motor_speed			= (((int16_t *)&QSPI_tx_buffer[1]+1);
+	*M4_Motor_current_bus		= convert_to_mA( Motor2.Iphase_pu.Bus);
+	*M4_Motor_currentPhA		= convert_to_mA( Motor2.Iphase_pu.A); 
+	*M4_Motor_currentPhB		= convert_to_mA( Motor2.Iphase_pu.B); 
+	*M4_Motor_currentPhC		= convert_to_mA(Motor2.Iphase_pu.C);
+	*M4_Motor__hallState		= Motor2.motor_status.currentHallPattern;
+	*M4_Motor_dutyCycle			= Motor2.motor_status.duty_cycle;
+	*M4_Motor_speed				= (int16_t)Motor2.motor_status.calc_rpm;
+	//*M4_Joint_abs_position		= Motor2.motor_status.actualDirection;
+}
+
+static void update_setpoints(void)
+{
+	Motor1.motor_setpoints.desired_position	= *M3_Desired_pos;
+	Motor1.motor_setpoints.desired_speed	= *M3_Desired_speed;
+	Motor1.motor_setpoints.desired_torque	= *M3_Desired_current;
+	Motor1.motor_setpoints.max_current		= *M3_Max_current;
+	Motor1.motor_setpoints.max_torque		= *M3_Max_current;
+	Motor1.motor_setpoints.max_velocity		= *M3_Max_velocity;
+	
+	Motor2.motor_setpoints.desired_position	= *M4_Desired_pos;
+	Motor2.motor_setpoints.desired_speed	= *M4_Desired_speed;
+	Motor2.motor_setpoints.desired_torque	= *M4_Desired_current;
+	Motor2.motor_setpoints.max_current		= *M4_Max_current;
+	Motor2.motor_setpoints.max_torque		= *M4_Max_current;
+	Motor2.motor_setpoints.max_velocity		= *M4_Max_velocity;
+	
+	volatile int y = 0;
+	//volatile uint8_t a = *M3_Control_mode;
+	//volatile uint8_t b = *M3_Control_set;
+	//volatile int16_t c = *M3_Desired_pos;
+	//volatile int16_t d = *M3_Desired_speed;
+	//volatile int16_t e = *M3_Desired_current;
+	//volatile int16_t f = *M3_Max_pos;
+	//volatile int16_t g = *M3_Max_velocity;
+	//volatile int16_t h = *M3_Max_current;
+	//volatile int16_t i = *M3_Spare;
+	//inline float32_t convert_int_to_PU(volatile int16_t input)
+	//{
+		//return ((float32_t)(input/1000.0f));
+	//}
+	////Motor1.des_mode						= 0;
+	////Motor1.set							= 0;
+	//Motor1.motor_setpoints.desired_position	= *desired_position;
+	//Motor1.motor_setpoints.desired_speed	= *desired_speed;
+	////Motor1.desired_speed					= 1500;
+	//Motor1.motor_setpoints.desired_torque	= convert_int_to_PU(*desired_torque);
+	////Motor1.controllerParam.I_kp			= 0;
+	////Motor1.controllerParam.I_ki			= 0;
+	////Motor1.controllerParam.V_kp			= 0;
+	////Motor1.controllerParam.V_kd			= 0;
+	////Motor1.controllerParam.V_kd			= 0;
+	////Motor1.controllerParam.P_kp			= 0;
+	////Motor1.controllerParam.P_ki			= 0;
+	////Motor1.reductionRatio					= 0;
+	//Motor1.motor_setpoints.max_velocity		= *max_velocity;
+	//Motor1.motor_setpoints.max_current		= convert_int_to_PU(*max_current);
+	//Motor1.motor_setpoints.max_torque		= convert_int_to_PU(*max_torque);	 
+	////Motor1.Spare1							= 0;
+	////Motor1.Spare2							= 0;
+	////Motor1.Spare3							= 0;
+	////Motor1.Spare4							= 0;	 
+}
+
+static inline void comms_check(void)
+{
+	/* Motor 1*/
+	*M3_Status				    = 1;
+	*M3_Mode					= 2;
+	*M3_Joint_rel_position		= -3;
+	*M3_Joint_abs_position		= 4;
+	*M3_Motor_speed				= -5;
+	*M3_Motor_current_bus		= 6;
+	*M3_Motor_currentPhA		= -7;
+	*M3_Motor_currentPhB		= 8;
+	*M3_Motor_currentPhC		= -9;
+	*M3_Motor__hallState		= 10;
+	*M3_Motor_dutyCycle			= -11;
+	/* Motor 2*/
+	*M4_Status				    = 12;
+	*M4_Mode					= 13;
+	*M4_Joint_rel_position		= 14;
+	*M4_Joint_abs_position		= -15;
+	*M4_Motor_speed				= 16;
+	*M4_Motor_current_bus		= -17;
+	*M4_Motor_currentPhA		= 18;
+	*M4_Motor_currentPhB		= -19;
+	*M4_Motor_currentPhC		= 20;
+	*M4_Motor__hallState		= -21;
+	*M4_Motor_dutyCycle			= 22;
+	
+	/* IMU */
+	*q_x0						= 23;
+	*q_y0						= -24;
+	*q_z0						= 25;
+	*q_w0						= -26;
+	/* EMG */
+	*FSR_CH1					= 27;
+	*FSR_CH2					= -28;
+	*FSR_CH3					= 29;
+	*FSR_CH4					= -30;
+	*FSR_CH5					= 31;
+	*Pressure_CH1				= -32;
+	*Pressure_CH2				= 33;
+	*Pressure_CH3				= -34;
+}
+
+#endif /* MASTER_SLAVE_IF_H_ */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Release.xml

@@ -0,0 +1,121 @@
+<ArmGcc>
+  <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+  <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
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+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+      <Value>../Config</Value>
+      <Value>../</Value>
+      <Value>../examples</Value>
+      <Value>../hal/include</Value>
+      <Value>../hal/utils/include</Value>
+      <Value>../hpl/adc</Value>
+      <Value>../hpl/ccl</Value>
+      <Value>../hpl/cmcc</Value>
+      <Value>../hpl/core</Value>
+      <Value>../hpl/dmac</Value>
+      <Value>../hpl/eic</Value>
+      <Value>../hpl/evsys</Value>
+      <Value>../hpl/gclk</Value>
+      <Value>../hpl/mclk</Value>
+      <Value>../hpl/osc32kctrl</Value>
+      <Value>../hpl/oscctrl</Value>
+      <Value>../hpl/pm</Value>
+      <Value>../hpl/port</Value>
+      <Value>../hpl/qspi</Value>
+      <Value>../hpl/ramecc</Value>
+      <Value>../hpl/sercom</Value>
+      <Value>../hpl/tc</Value>
+      <Value>../hpl/tcc</Value>
+      <Value>../hri</Value>
+      <Value>%24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include</Value>
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=softfp -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcc.linker.general.UseNewlibNano>True</armgcc.linker.general.UseNewlibNano>
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+    <ListValues>
+      <Value>libm</Value>
+      <Value>libarm_cortexM4lf_math.a</Value>
+    </ListValues>
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+  <armgcc.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>C:\Users\ge37vez\Documents\Git Repos\bldc_control_thesis\bldc_firmware_thesis\2_Motor_Master_D51\Two_Motor_D51\Two_Motor_D51\cmsis</Value>
+      <Value>%24(ProjectDir)\Device_Startup</Value>
+    </ListValues>
+  </armgcc.linker.libraries.LibrarySearchPaths>
+  <armgcc.linker.optimization.GarbageCollectUnusedSections>True</armgcc.linker.optimization.GarbageCollectUnusedSections>
+  <armgcc.linker.miscellaneous.LinkerFlags>-Tsamd51j18a_flash.ld</armgcc.linker.miscellaneous.LinkerFlags>
+  <armgcc.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+      <Value>../Config</Value>
+      <Value>../</Value>
+      <Value>../examples</Value>
+      <Value>../hal/include</Value>
+      <Value>../hal/utils/include</Value>
+      <Value>../hpl/adc</Value>
+      <Value>../hpl/ccl</Value>
+      <Value>../hpl/cmcc</Value>
+      <Value>../hpl/core</Value>
+      <Value>../hpl/dmac</Value>
+      <Value>../hpl/eic</Value>
+      <Value>../hpl/evsys</Value>
+      <Value>../hpl/gclk</Value>
+      <Value>../hpl/mclk</Value>
+      <Value>../hpl/osc32kctrl</Value>
+      <Value>../hpl/oscctrl</Value>
+      <Value>../hpl/pm</Value>
+      <Value>../hpl/port</Value>
+      <Value>../hpl/qspi</Value>
+      <Value>../hpl/ramecc</Value>
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+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+      <Value>../Config</Value>
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+      <Value>../hal/include</Value>
+      <Value>../hal/utils/include</Value>
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+      <Value>../hpl/ramecc</Value>
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+      <Value>%24(PackRepoDir)\atmel\SAMD51_DFP\1.2.139\samd51a\include</Value>
+    </ListValues>
+  </armgcc.preprocessingassembler.general.IncludePaths>
+</ArmGcc>

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/Two_Motor_D51.componentinfo.xml

@@ -0,0 +1,169 @@
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+<Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement">
+	<ProjectComponents>
+		<ProjectComponent z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/">
+			<CApiVersion></CApiVersion>
+			<CBundle></CBundle>
+			<CClass>CMSIS</CClass>
+			<CGroup>CORE</CGroup>
+			<CSub></CSub>
+			<CVariant></CVariant>
+			<CVendor>ARM</CVendor>
+			<CVersion>5.1.2</CVersion>
+			<DefaultRepoPath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs</DefaultRepoPath>
+			<DependentComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays" />
+			<Description></Description>
+			<Files xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
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+					<Attribute></Attribute>
+					<Category>include</Category>
+					<Condition></Condition>
+					<FileContentHash i:nil="true" />
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+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+			</Files>
+			<PackName>CMSIS</PackName>
+			<PackPath>C:/Program Files (x86)/Atmel/Studio/7.0/Packs/arm/CMSIS/5.4.0/ARM.CMSIS.pdsc</PackPath>
+			<PackVersion>5.4.0</PackVersion>
+			<PresentInProject>true</PresentInProject>
+			<ReferenceConditionId>ARMv6_7_8-M Device</ReferenceConditionId>
+			<RteComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:string></d4p1:string>
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+			<Status>Resolved</Status>
+			<VersionMode>Fixed</VersionMode>
+			<IsComponentInAtProject>true</IsComponentInAtProject>
+		</ProjectComponent>
+		<ProjectComponent z:Id="i2" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/">
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+					<FileContentHash i:nil="true" />
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+					<Condition>C</Condition>
+					<FileContentHash>rD3kwzrlLE7LjuVvGHbYTA==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>samd51a/include/sam.h</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMD51_DFP\1.2.139\samd51a\templates\main.c</AbsolutePath>
+					<Attribute>template</Attribute>
+					<Category>source</Category>
+					<Condition>C Exe</Condition>
+					<FileContentHash>TPnvYzYy0YGcha5CM94fSQ==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>samd51a/templates/main.c</Name>
+					<SelectString>Main file (.c)</SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMD51_DFP\1.2.139\samd51a\templates\main.cpp</AbsolutePath>
+					<Attribute>template</Attribute>
+					<Category>source</Category>
+					<Condition>C Exe</Condition>
+					<FileContentHash>Wwcf/gxegRQ10+cCzYcFIw==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>samd51a/templates/main.cpp</Name>
+					<SelectString>Main file (.cpp)</SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMD51_DFP\1.2.139\samd51a\gcc\system_samd51.c</AbsolutePath>
+					<Attribute>config</Attribute>
+					<Category>source</Category>
+					<Condition>GCC Exe</Condition>
+					<FileContentHash>doJVlmj1zJFW6L6a8gLeVw==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>samd51a/gcc/system_samd51.c</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMD51_DFP\1.2.139\samd51a\gcc\gcc\startup_samd51.c</AbsolutePath>
+					<Attribute>config</Attribute>
+					<Category>source</Category>
+					<Condition>GCC Exe</Condition>
+					<FileContentHash>LhhJYPvpcWu0vydBG4SgQw==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>samd51a/gcc/gcc/startup_samd51.c</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMD51_DFP\1.2.139\samd51a\gcc\gcc\samd51j18a_flash.ld</AbsolutePath>
+					<Attribute>config</Attribute>
+					<Category>linkerScript</Category>
+					<Condition>GCC Exe</Condition>
+					<FileContentHash>kizNDwM8mlji3yBhqFJC1w==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>samd51a/gcc/gcc/samd51j18a_flash.ld</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMD51_DFP\1.2.139\samd51a\gcc\gcc\samd51j18a_sram.ld</AbsolutePath>
+					<Attribute>config</Attribute>
+					<Category>other</Category>
+					<Condition>GCC Exe</Condition>
+					<FileContentHash>ihuVSODgd+Jo5ymXBKJu0A==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>samd51a/gcc/gcc/samd51j18a_sram.ld</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+			</Files>
+			<PackName>SAMD51_DFP</PackName>
+			<PackPath>C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/SAMD51_DFP/1.2.139/Atmel.SAMD51_DFP.pdsc</PackPath>
+			<PackVersion>1.2.139</PackVersion>
+			<PresentInProject>true</PresentInProject>
+			<ReferenceConditionId>ATSAMD51J18A</ReferenceConditionId>
+			<RteComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:string></d4p1:string>
+			</RteComponents>
+			<Status>Resolved</Status>
+			<VersionMode>Fixed</VersionMode>
+			<IsComponentInAtProject>true</IsComponentInAtProject>
+		</ProjectComponent>
+	</ProjectComponents>
+</Store>

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/angle_sensors.c

@@ -0,0 +1,130 @@
+
+/*
+ * angle_sensors.c
+ *
+ * Created: 8/21/2021 11:34:44 AM
+ *  Author: ge37vez
+ */ 
+
+#include "angle_sensors.h"
+#define	AS5048A_MAX_VALUE					   (8191.0f)
+#include "arm_math.h"
+
+void angle_sensor_init()
+{
+	spi_m_sync_disable(ANGLESENSOR.SPI_descr);
+	// Set Mode 1 : CPOL = 0; CPHA = 1;
+	
+	#ifdef AS5048
+	/* Set Mode 1 */
+	hri_sercomspi_write_CTRLA_CPOL_bit((SercomSpi *)(ANGLESENSOR.SPI_descr->dev.prvt), false);
+	hri_sercomspi_write_CTRLA_CPHA_bit((SercomSpi *)(ANGLESENSOR.SPI_descr->dev.prvt), true);
+	#elif defined A1335
+	/* Set Mode 3 */
+	hri_sercomspi_write_CTRLA_CPOL_bit((SercomSpi *)(ANGLESENSOR.SPI_descr->dev.prvt), true);
+	hri_sercomspi_write_CTRLA_CPHA_bit((SercomSpi *)(ANGLESENSOR.SPI_descr->dev.prvt), true);	
+	#endif 
+	
+	spi_m_sync_enable(ANGLESENSOR.SPI_descr);
+	gpio_set_pin_level(ANGLESENSOR.SS_pin, true);
+}
+
+int16_t* ang_sense_read(ASCommand command)
+{
+	_read(command); // Send command to device(s)
+	return _read(command); // Read-out device(s)
+}
+
+int16_t* read_angle()
+{
+	_read(AS_CMD_ANGLE); // Send command to device(s)
+	return _read(AS_CMD_ANGLE); // Read-out device(s)
+}
+
+int16_t* _read(ASCommand command)
+{
+	
+	if(ANGLESENSOR.n_dev == 1)
+	{
+		// Give command to start reading the angle
+		gpio_set_pin_level(ANGLESENSOR.SS_pin, false);
+		uint16_t temp = _spi_transfer16(&ANGLESENSOR, command);
+		ANGLESENSOR._readBuffer[0] = (int16_t)(temp & AS_MASK);
+		gpio_set_pin_level(ANGLESENSOR.SS_pin, true);
+		//delay_us(1); // Wait at least 350ns after chip select
+	} else {
+		// Enable the sensor on the chain
+		gpio_set_pin_level(ANGLESENSOR.SS_pin, false);
+		//delay_us(1); // Wait at least 350ns after chip select
+		for(int i = 0; i < ANGLESENSOR.n_dev; ++i)
+		{
+			uint16_t temp = _spi_transfer16(&ANGLESENSOR, command);
+			ANGLESENSOR._readBuffer[i] = (int16_t)(temp & AS_MASK);
+		}
+		gpio_set_pin_level(ANGLESENSOR.SS_pin, true);
+		//delay_us(1); // Wait at least 350ns after chip select
+	}
+	return &ANGLESENSOR._readBuffer;
+}
+
+
+bool parity_check(int16_t sensor_result)
+{
+	// Use the LSb of result to keep track of parity (0 = even, 1 = odd)
+	int16_t result = sensor_result;
+	    
+	for(int i = 1; i <= 15; ++i) {
+		sensor_result >>= 1;
+		result ^= sensor_result;
+	}
+	// Parity should be even
+	return (result & 0x0001) == 0;
+}
+
+int16_t degrees(int16_t sensor_result)
+{
+	uint16_t data;
+	int16_t rotation;
+	
+	#ifdef AS5048
+	
+	rotation = (int16_t)(sensor_result & AS_MASK); //- static_cast<int16_t>(this->position);
+	if (rotation > AS5048A_MAX_VALUE) {
+		rotation = -((0x3FFF) - rotation); //more than -180
+	}
+		
+	float angleDegrees = 360.0 * ((rotation) + AS5048A_MAX_VALUE) / (AS5048A_MAX_VALUE * 2.0);
+	//float angleDegrees = 360.0 * ((sensor_result &= 0x3FFF) + AS5048A_MAX_VALUE) / (AS5048A_MAX_VALUE * 2.0);
+	//float32_t angleDegrees = 360.0 * (rotation + AS5048A_MAX_VALUE) * 0.000061042607;
+	
+	return (int16_t)(angleDegrees * 10 + .5);
+	
+	#elif defined A1335
+	float angleDegrees = ((sensor_result & AS_MASK) * 360.0 / 4096.0);
+	
+	//int16_t angle_deg = (sensor_result &= 0x3FFF) * 36000 / 0x4000;
+	//return angle_deg;
+	return (int16_t)(angleDegrees * 10 + .5);
+	#endif
+}
+
+int16_t mask(int16_t sensor_results)
+{
+	return (sensor_results &= 0x3FFF);
+}
+
+uint16_t _spi_transfer16(struct spi_m_sync_descriptor *spi, uint16_t command)
+{
+	uint8_t in_buf[2], out_buf[2];
+	uint16_t wordRead;
+	
+	out_buf[1] = command & 0xFF;
+	out_buf[0] = ( command >> 8 ) & 0xFF;
+	struct spi_xfer  xfer;
+	xfer.rxbuf = in_buf;
+	xfer.txbuf = (uint8_t *)out_buf;
+	xfer.size  = 2;
+	spi_m_sync_transfer(&SPI_3, &xfer);
+	wordRead = (uint16_t)((in_buf[0] << 8) | in_buf[1]);
+	return (wordRead);
+}

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/angle_sensors.h

@@ -0,0 +1,111 @@
+/*
+ * angle_sensors.h
+ *
+ * Created: 8/21/2021 11:16:13 AM
+ *  Author: ge37vez
+ */ 
+
+
+#ifndef ANGLE_SENSORS_H_
+#define ANGLE_SENSORS_H_
+
+#include "atmel_start.h"
+
+//Define Sensor type (One one at at time supported)
+//#define AS5048
+#define A1335
+
+// ----------------------------------------------------------------------
+// AS5048 Registers & Commands
+// ----------------------------------------------------------------------
+#ifdef AS5048
+
+typedef enum {
+	AS_FLAG_PARITY = 0x8000,
+	AS_FLAG_READ = 0x4000,
+	AS_MASK = 0x3FFF,
+} ASFlag;
+
+typedef enum {
+	AS_CMD_NOP = 0x0000,
+	AS_CMD_ERROR = 0x0001 | AS_FLAG_READ,       // Reads error register of sensor and clear error flags
+	AS_CMD_DIAGNOSTICS = 0x3FFD |  AS_FLAG_READ, // Reads automatic gain control and diagnostics info
+	AS_CMD_MAGNITUDE = 0x3FFE | AS_FLAG_READ,
+	AS_CMD_ANGLE = 0x3FFF| AS_FLAG_PARITY | AS_FLAG_READ,
+} ASCommand;
+
+// Masks for bits in the result of the AS_CMD_DIAGNOSTICS command
+typedef enum {
+	AS_DIAG_CORDIC_OVERFLOW = 0x0200,
+	AS_DIAG_HIGH_MAGNETIC = 0x0400,
+	AS_DIAG_LOW_MAGNETIC = 0x0800,
+} ASDiagnostics;
+
+// ----------------------------------------------------------------------
+// A1335 Registers & Commands
+// ----------------------------------------------------------------------
+#elif defined A1335
+
+typedef enum {
+	AS_FLAG_PARITY = 0x8000,
+	AS_FLAG_READ = 0x00,
+	AS_ADDRESS_MASK = 0x3F,
+	AS_MASK = 0x0FFF,
+} ASFlag;
+
+typedef enum {
+	AS_CMD_NOP = 0x0000,
+	AS_CMD_ERROR = 0x0001 | AS_FLAG_READ,       // Reads error register of sensor and clear error flags
+	AS_CMD_DIAGNOSTICS = 0x3FFD |  AS_FLAG_READ, // Reads automatic gain control and diagnostics info
+	AS_CMD_MAGNITUDE = (uint16_t)(((0x2A & AS_ADDRESS_MASK) | AS_FLAG_READ) << 8),
+	AS_CMD_ANGLE = (uint16_t)(((0x20 & AS_ADDRESS_MASK) | AS_FLAG_READ) << 8),
+	AS_CMD_TEMP = ((0x28 & AS_ADDRESS_MASK) | AS_FLAG_READ) << 8,
+} ASCommand;
+
+// Masks for bits in the result of the AS_CMD_DIAGNOSTICS command
+typedef enum {
+	AS_DIAG_CORDIC_OVERFLOW = 0x0200,
+	AS_DIAG_HIGH_MAGNETIC = 0x0400,
+	AS_DIAG_LOW_MAGNETIC = 0x0800,
+} ASDiagnostics;
+
+#endif
+
+/* Struct Definitions */
+struct SPI_ANGLE_SENSOR {
+	struct spi_m_sync_descriptor *SPI_descr;
+	uint8_t flags;
+	uint32_t SS_pin;
+	uint8_t n_dev;
+	int16_t _readBuffer[2]; // Must Equal n_dev
+};
+
+static struct SPI_ANGLE_SENSOR ANGLESENSOR = {
+	.SPI_descr = &SPI_3,
+	.flags = 0,
+	.SS_pin = SPI3_SS,
+	.n_dev = 2,
+	._readBuffer = {0} // Must Equal n_dev
+};
+
+void angle_sensor_init();
+int16_t* ang_sense_read(ASCommand command);
+// Performs a single angle measurement on all sensors
+// @return Array of raw angle data. To get the 14-bit value representing
+//     the angle, apply the mask() to the result.
+int16_t* read_angle();
+// Applies the mask to the first n bytes in the read buffer (for daisychained sensors).
+static int16_t mask(int16_t sensor_results);
+// Checks if the return value from the sensor has the right parity
+// @return true if ok
+static bool parity_check(int16_t sensor_result);
+// Returns an angle from 0 to 36000 (degrees times 100).
+// @param sensor_result is one of the values returned by read_angle or read_angle_sequential
+int16_t degrees(int16_t sensor_result);
+    
+// Intended to be used Internally
+int16_t* _read(ASCommand command);	
+uint16_t _spi_transfer16(struct spi_m_sync_descriptor *spi, uint16_t value);
+	
+
+#endif /* ANGLE_SENSORS_H_ */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start.c

@@ -0,0 +1,9 @@
+#include <atmel_start.h>
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void)
+{
+	system_init();
+}

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start.h

@@ -0,0 +1,18 @@
+#ifndef ATMEL_START_H_INCLUDED
+#define ATMEL_START_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "driver_init.h"
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/atmel_start_pins.h

@@ -0,0 +1,80 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef ATMEL_START_PINS_H_INCLUDED
+#define ATMEL_START_PINS_H_INCLUDED
+
+#include <hal_gpio.h>
+
+// SAMD51 has 14 pin functions
+
+#define GPIO_PIN_FUNCTION_A 0
+#define GPIO_PIN_FUNCTION_B 1
+#define GPIO_PIN_FUNCTION_C 2
+#define GPIO_PIN_FUNCTION_D 3
+#define GPIO_PIN_FUNCTION_E 4
+#define GPIO_PIN_FUNCTION_F 5
+#define GPIO_PIN_FUNCTION_G 6
+#define GPIO_PIN_FUNCTION_H 7
+#define GPIO_PIN_FUNCTION_I 8
+#define GPIO_PIN_FUNCTION_J 9
+#define GPIO_PIN_FUNCTION_K 10
+#define GPIO_PIN_FUNCTION_L 11
+#define GPIO_PIN_FUNCTION_M 12
+#define GPIO_PIN_FUNCTION_N 13
+
+#define SPI1_MOSI GPIO(GPIO_PORTA, 0)
+#define SPI1_SCK GPIO(GPIO_PORTA, 1)
+#define ADS_DATA_RDY GPIO(GPIO_PORTA, 2)
+#define ANAREF_3V GPIO(GPIO_PORTA, 3)
+#define M1_HALLA GPIO(GPIO_PORTA, 4)
+#define M1_HALLB GPIO(GPIO_PORTA, 5)
+#define M1_HALLC GPIO(GPIO_PORTA, 6)
+#define ECAT_SYNC GPIO(GPIO_PORTA, 7)
+#define ECAT_QSPI_MOSI GPIO(GPIO_PORTA, 8)
+#define ECAT_QSPI_MISO GPIO(GPIO_PORTA, 9)
+#define ECAT_QSPI_DATA2 GPIO(GPIO_PORTA, 10)
+#define ECAT_QSPI_DATA3 GPIO(GPIO_PORTA, 11)
+#define SPI2_MOSI GPIO(GPIO_PORTA, 12)
+#define SPI2_SCK GPIO(GPIO_PORTA, 13)
+#define SPI2_SS GPIO(GPIO_PORTA, 14)
+#define SPI2_MISO GPIO(GPIO_PORTA, 15)
+#define M2_PWMA GPIO(GPIO_PORTA, 16)
+#define M2_PWMB GPIO(GPIO_PORTA, 17)
+#define M2_PWMC GPIO(GPIO_PORTA, 18)
+#define M2_ENA GPIO(GPIO_PORTA, 19)
+#define M2_ENB GPIO(GPIO_PORTA, 20)
+#define M2_ENC GPIO(GPIO_PORTA, 21)
+#define M2_HALLA GPIO(GPIO_PORTA, 22)
+#define M2_HALLB GPIO(GPIO_PORTA, 23)
+#define M2_HALLC GPIO(GPIO_PORTA, 24)
+#define M1_RST GPIO(GPIO_PORTA, 25)
+#define M2_RST GPIO(GPIO_PORTA, 27)
+#define SPI3_SS GPIO(GPIO_PORTB, 0)
+#define SPI3_MISO GPIO(GPIO_PORTB, 1)
+#define SPI3_MOSI GPIO(GPIO_PORTB, 2)
+#define SPI3_SCK GPIO(GPIO_PORTB, 3)
+#define M1_IA GPIO(GPIO_PORTB, 4)
+#define M1_IB GPIO(GPIO_PORTB, 5)
+#define M2_IA GPIO(GPIO_PORTB, 6)
+#define M2_IB GPIO(GPIO_PORTB, 7)
+#define half_VREF GPIO(GPIO_PORTB, 8)
+#define ADS_RESET GPIO(GPIO_PORTB, 9)
+#define ECAT_QSPI_SCK GPIO(GPIO_PORTB, 10)
+#define ECAT_QSPI_CS GPIO(GPIO_PORTB, 11)
+#define M1_PWMA GPIO(GPIO_PORTB, 12)
+#define M1_PWMB GPIO(GPIO_PORTB, 13)
+#define M1_PWMC GPIO(GPIO_PORTB, 14)
+#define M1_ENA GPIO(GPIO_PORTB, 15)
+#define M1_ENB GPIO(GPIO_PORTB, 16)
+#define M1_ENC GPIO(GPIO_PORTB, 17)
+#define SPI1_CS GPIO(GPIO_PORTB, 22)
+#define SPI1_MISO GPIO(GPIO_PORTB, 23)
+#define M1_RST_Bar GPIO(GPIO_PORTB, 30)
+#define M2_RST_Bar GPIO(GPIO_PORTB, 31)
+
+#endif // ATMEL_START_PINS_H_INCLUDED

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc.c

@@ -0,0 +1,554 @@
+/*
+ * bldc.c
+ *
+ * Created: 31/07/2021 14:56:17
+ *  Author: Nick-XMG
+ */ 
+
+#include "bldc.h"
+
+#include "utilities.h"
+#include "Ethercat_SlaveDef.h"
+
+void motor_StateMachine(BLDCMotor_t* const motor)
+{
+	
+	//if (motor->motor_state.fault)
+	//{
+		//motor->motor_state.previousstate = motor->motor_state.currentstate;
+		//motor->motor_state.currentstate = MOTOR_FAULT;
+	//}
+	
+	switch (motor->motor_state.currentstate)
+	{
+		case MOTOR_INIT: ;
+			volatile uint8_t currentHall = motor->readHall();
+			if((currentHall > 6) || (currentHall < 1) )  {
+				motor->motor_state.fault = MOTOR_HALLSENSORINVALID;
+				motor->motor_state.currentstate = MOTOR_FAULT;
+				break;	
+			} 
+			motor->motor_state.previousstate = motor->motor_state.currentstate;
+			motor->motor_state.currentstate = MOTOR_IDLE;
+		break;
+		case  MOTOR_IDLE:
+			//hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw,  DISABLE_PATTERN);
+			motor->motor_state.previousstate = motor->motor_state.currentstate;
+			motor->motor_state.currentstate = MOTOR_PVI_CTRL_STATE;
+		break;
+		case MOTOR_OPEN_LOOP_STATE:
+			BLDC_runOpenLoop(motor, 100);
+			calculate_motor_speed(motor);
+			motor->motor_state.previousstate = motor->motor_state.currentstate;
+		break;
+		case MOTOR_V_CTRL_STATE:
+			calculate_motor_speed(motor);
+			BLDC_runSpeedCntl(motor, (float32_t)motor->motor_status.calc_rpm, (float32_t)motor->motor_setpoints.desired_speed);
+			motor->motor_state.previousstate = motor->motor_state.currentstate;	
+		break;	
+		case MOTOR_VI_CTRL_STATE:	
+			switch (motor->regulation_loop_count) {
+				case 0: /* PWM FREQ / 25 - 1kHz */	
+				//case 5: case 10: case 15: case 20:/* PWM FREQ / 5 - 5kHz */
+				case 5: case 15: /* PWM FREQ / 5 - 5kHz */
+					calculate_motor_speed(motor);
+					BLDC_runSpeedCntl(motor, (float32_t)motor->motor_status.calc_rpm, (float32_t)motor->motor_setpoints.desired_speed);	
+				default: /* PWM FREQ - 25kHz */
+					select_active_phase(motor);
+					BLDC_runCurrentCntl(motor,(float32_t)motor->Iphase_pu.Bus, (float32_t)motor->controllers.Pi_Idc.Ref_pu);
+				break;
+			} // end switch(regulation_loop_count)
+			if(motor->regulation_loop_count > 23) motor->regulation_loop_count = 0;
+			else motor->regulation_loop_count++;
+		break;
+		case MOTOR_PVI_CTRL_STATE:	
+			switch (motor->regulation_loop_count) {
+				case 0: /* PWM FREQ / 25 - 1kHz */
+					BLDC_runPosCntl(motor, motor->motor_status.Num_Steps, motor->motor_setpoints.desired_position);	
+				case 5: case 10: case 15: case 20:/* PWM FREQ / 5 - 5kHz */
+					calculate_motor_speed(motor);	
+					BLDC_runSpeedCntl(motor, (float32_t)motor->motor_status.calc_rpm, (float32_t)motor->controllers.Pid_Speed.Ref_pu);
+				default: /* PWM FREQ - 25kHz */
+					select_active_phase(motor);
+					//select_active_phase(&Motor2, Motor2.motor_status.currentHallPattern);
+					BLDC_runCurrentCntl(motor, motor->Iphase_pu.Bus, motor->controllers.Pi_Idc.Ref_pu);
+				break;
+			} // end switch(regulation_loop_count)
+			if(motor->regulation_loop_count > 23) motor->regulation_loop_count = 0;
+			else motor->regulation_loop_count++;
+		break;
+		case MOTOR_FAULT:
+			disable_phases(motor);
+		break;
+	} //end switch (motor->motor_state.currentstate)
+	
+	// ----------------------------------------------------------------------
+	// Run Commutation
+	// ----------------------------------------------------------------------
+	
+}
+
+void BldcInitStruct(BLDCMotor_t* const motor, BLDCMotor_param_t * const motor_param)
+{
+	// ----------------------------------------------------------------------
+	//  Assign Motor Parameters:
+	// ----------------------------------------------------------------------
+	motor->motor_param						 = motor_param;
+							
+	
+	// ----------------------------------------------------------------------
+	// Initialize State Machine:
+	// ----------------------------------------------------------------------
+	motor->motor_state.currentstate			 = 	MOTOR_INIT;
+	motor->motor_state.previousstate		 =	MOTOR_INIT;
+	motor->motor_state.fault				 =	MOTOR_NOFAULT;			
+	// ----------------------------------------------------------------------
+	//  Initialize Status Struct:
+	// ----------------------------------------------------------------------
+	motor->motor_status.actualDirection		 = 0;
+	motor->motor_status.duty_cycle			 = 0;
+	motor->motor_status.calc_rpm			 = 0;
+	motor->motor_status.abs_position		 = 0;
+	motor->motor_status.Num_Steps			 = 0;
+	motor->motor_status.cur_comm_step		 = 0;
+	motor->motor_status.currentHallPattern	 = 1;
+	//motor->motor_status.nextHallPattern	 = 3;
+	
+	motor->motor_status.speed_average		 = 0;
+	motor->motor_status.count				 = 1;
+		
+	// ----------------------------------------------------------------------
+	//  Initialize Phase Current Struct:
+	// ----------------------------------------------------------------------
+	motor->Iphase_pu.A						 = 0;
+	motor->Iphase_pu.B						 = 0;
+	motor->Iphase_pu.C						 = 0;
+	motor->Iphase_pu.Bus					 = 0;
+		
+	// ----------------------------------------------------------------------
+	//  Initialize Timers:
+	// ----------------------------------------------------------------------
+	motor->timerflags.pwm_cycle_tic			 = false;
+	motor->timerflags.control_loop_tic		 = false;
+	motor->timerflags.motor_telemetry_flag	 = false;
+	motor->timerflags.control_loop_tic		 = false;
+	motor->timerflags.adc_readings_ready_tic = false;
+	
+	// ----------------------------------------------------------------------
+	//  Current Sensors Calibration offsets:
+	// ----------------------------------------------------------------------
+	motor->Voffset_lsb.A					 = 0;
+	motor->Voffset_lsb.B					 = 0;
+	
+	// ----------------------------------------------------------------------
+	//  Regulation Loop Counter
+	// ----------------------------------------------------------------------
+	motor->regulation_loop_count			 = 0;
+
+	// ----------------------------------------------------------------------
+	//  Initialize Bus Voltage:
+	// ----------------------------------------------------------------------
+	motor->VdcBus_pu						 = DEVICE_DC_VOLTAGE_V;
+	motor->VoneByDcBus_pu					 = 1.0f/DEVICE_DC_VOLTAGE_V;
+	
+	// ----------------------------------------------------------------------
+	//  Initialize Setpoints Struct:
+	// ----------------------------------------------------------------------
+	motor->motor_setpoints.desiredDirection	 = 0;
+	motor->motor_setpoints.desired_torque	 = 0.0;
+	motor->motor_setpoints.desired_speed	 = 0;
+	motor->motor_setpoints.desired_position  = 0;
+	motor->motor_setpoints.max_current		 = 0.0;
+	motor->motor_setpoints.max_torque		 = 0.0;
+	motor->motor_setpoints.max_velocity		 = 0;
+	motor->motor_setpoints.directionOffset	 = 0;
+		
+	//// ------------------------------------------------------------------------------
+	//// Initialize PI current control 
+	//// ------------------------------------------------------------------------------
+	PI_objectInit(&motor->controllers.Pi_Idc);
+	float32_t motorLs_H   = motor_param->motor_LQ_H	  * 2.0f;
+	float32_t motorRs_OHM = motor_param->motor_RS_Ohm * 2.0f;
+	motor->controllers.Pi_Idc.Kp = PI_calcKp(motorLs_H, DEVICE_SHUNT_CURRENT_A, DEVICE_DC_VOLTAGE_V, DEVICE_ISR_PERIOD_Sec);
+	motor->controllers.Pi_Idc.Ki = PI_calcKi(motorRs_OHM, motorLs_H, DEVICE_ISR_PERIOD_Sec);
+	
+	//// ------------------------------------------------------------------------------
+	//// Initialize PD Vel control 
+	//// ------------------------------------------------------------------------------
+	PID_objectInit(&motor->controllers.Pid_Speed);
+	/* V Control Gains */
+	//motor->controllers.Pid_Speed.Kp = 0.005f;
+	//motor->controllers.Pid_Speed.Ki = 0.00001f;
+	//motor->controllers.Pid_Speed.Kd = 0.001f;
+		
+	/* VI Control Gains */
+	//motor->controllers.Pid_Speed.Kp = 0.0002f;
+	//motor->controllers.Pid_Speed.Ki = 0.0000001f;
+	motor->controllers.Pid_Speed.Kp = motor_param->controller_param.Pid_Speed.Kp;
+	motor->controllers.Pid_Speed.Ki = motor_param->controller_param.Pid_Speed.Ki;
+	
+	//motor->controllers.Pid_Speed.Kp = 0.0005f;
+	//motor->controllers.Pid_Speed.Ki = 0.0f;
+	//motor->controllers.Pid_Speed.Kd = 0.0001f;
+	
+	/* Limits */
+	motor->controllers.Pid_Speed.OutMax_pu =  (motor_param->motor_Max_Current_IDC_A);
+	motor->controllers.Pid_Speed.OutMin_pu = -(motor_param->motor_Max_Current_IDC_A);
+	
+	//// ------------------------------------------------------------------------------
+	////  Initialize PI Position control
+	//// ------------------------------------------------------------------------------
+	PI_objectInit(&motor->controllers.Pi_Pos);
+	//motor->controllers.Pi_Pos.Kp = 40.0f;
+	//motor->controllers.Pi_Pos.Ki = 0.0f;	
+	motor->controllers.Pi_Pos.Kp = motor_param->controller_param.Pi_Pos.Kp;
+	motor->controllers.Pi_Pos.Ki = motor_param->controller_param.Pi_Pos.Ki;
+	motor->controllers.Pi_Pos.OutMax_pu =  (motor_param->motor_Max_Spd_RPM);
+	motor->controllers.Pi_Pos.OutMin_pu = -(motor_param->motor_Max_Spd_RPM);
+}
+
+void exec_commutation(BLDCMotor_t* const motor)
+{
+	
+	// ----------------------------------------------------------------------
+	// Read Motor Hall Sensors
+	// ----------------------------------------------------------------------
+	//tic_port(DEBUG_2_PORT);
+	//motor->motor_status.currentHallPattern = readM1Hall();
+	volatile uint8_t currentHall = motor->readHall();
+	motor->motor_status.currentHallPattern = currentHall;
+		
+	if (currentHall == INVALID_HALL_7)
+	{
+		///motor->motor_state.currentstate == MOTOR_FAULT;
+		//motor->motor_state.fault == MOTOR_HALLSENSORINVALID;
+		//return;
+	}
+																		   
+	// ----------------------------------------------------------------------
+	// Set Pattern Buffers
+	// ----------------------------------------------------------------------
+	volatile uint16_t temp_M1	= COMMUTATION_PATTERN[currentHall + 
+													  motor->motor_setpoints.directionOffset];
+
+	//TCC0->PATTBUF.reg = temp_M1;
+	Tcc * tmp = (Tcc *)motor->pwm_desc->device.hw;
+	tmp->PATTBUF.reg = (uint16_t)temp_M1;
+	//motor->motor_param->pwm_desc->device.hw->PATTBUF.reg = temp_M1;
+	//hri_tcc_write_PATTBUF_reg(motor->motor_param->pwm_desc->device.hw,  temp_M1);
+	
+	// ----------------------------------------------------------------------
+	// Set Calculated Duty Cycle
+	// ----------------------------------------------------------------------
+	//hri_tcc_write_CCBUF_CCBUF_bf(motor->motor_param->pwm_desc->device.hw, 0, motor->motor_status.duty_cycle);
+	tmp->CCBUF[0].reg = (uint32_t)motor->motor_status.duty_cycle;
+
+
+	volatile uint8_t cur_comm_step = MOTOR_COMMUTATION_STEPS[currentHall];
+	motor->motor_status.cur_comm_step = cur_comm_step;
+	volatile int8_t step_change = (cur_comm_step - motor->motor_status.prev_comm_step);
+	
+	switch(step_change)
+	{
+		case 1: case -5:
+			motor->motor_status.Num_Steps += 1;
+			motor->motor_status.actualDirection = CW;
+		//Motor1.motor_setpoints.directionOffset = DIRECTION_CW_OFFSET;
+		break;
+		case -1: case 5:
+			motor->motor_status.Num_Steps -= 1;
+			motor->motor_status.actualDirection = CCW;
+		//Motor1.motor_setpoints.directionOffset = DIRECTION_CCW_OFFSET;
+		break;
+		default:
+		// do nothing
+		break;
+	}
+	motor->motor_status.prev_comm_step = cur_comm_step;
+	//toc_port(DEBUG_2_PORT);
+}
+
+//// ------------------------------------------------------------------------------
+// Current Selection Based on Hall State
+// Direction":
+// CW  -> Always positive current
+// CCW -> Always negative current
+//// ------------------------------------------------------------------------------
+void select_active_phase(BLDCMotor_t* const Motor)
+{
+	uint8_t hall_state = Motor->motor_status.currentHallPattern;
+	volatile float32_t phase_current = 0;
+	switch(hall_state)
+	{
+		case 0b001:	case 0b011:
+		phase_current = Motor->Iphase_pu.C;
+		break;
+			
+		case 0b010:	case 0b110:
+		phase_current = Motor->Iphase_pu.B;
+		break;
+			
+		case 0b100: case 0b101:
+		phase_current = Motor->Iphase_pu.A;
+		break;
+			
+		default :
+		//phase_current = 0;	// Invalid hall code
+		break;
+	}	
+	Motor->Iphase_pu.Bus = phase_current;
+}
+
+void calculate_motor_speed(BLDCMotor_t* const motor)
+{	
+	//tic_port(DEBUG_2_PORT);
+	volatile uint32_t temp_rpm = 0;
+	hri_tccount32_read_CC_reg(motor->speedtimer_hw, 0); /* Read CC0 but throw away)*/
+	volatile uint32_t period_after_capture = hri_tccount32_read_CC_reg(motor->speedtimer_hw, 1);
+	if((period_after_capture >= UINT32_MAX)||(period_after_capture == 0)||(period_after_capture > 600000))  {
+		motor->motor_status.calc_rpm = 0;
+	} else {
+		////uint32_t test = (SPEEDFACTOR, period_after_capture);
+		////temp_rpm = SPEEDFACTOR / period_after_capture;
+		////tic_port(DEBUG_3_PORT);
+		temp_rpm = HZ_TO_RPM / (period_after_capture * motor->motor_param->motor_commutationStates);
+		//temp_rpm = HZ_TO_RPM * period_after_capture;
+		////toc_port(DEBUG_3_PORT);
+		
+		//uint32_t muti = DEVICE_SPEEDTC_FREQUENCY_Hz*60;
+		//temp_rpm = (muti) / (period_after_capture*42);
+	}
+	
+	if(motor->motor_status.actualDirection == CCW) /* Changed from CCW */
+	{
+		//*motor_speed = -1* Motor1.calc_rpm;
+		temp_rpm = -1 * temp_rpm;
+	} else { 
+		//*motor_speed = Motor1.calc_rpm;
+		temp_rpm = temp_rpm;
+	}
+		
+	//motor->motor_status.calc_rpm = (int16_t)temp_rpm;
+	
+	#ifdef AVERAGE_SPEED_MEASURE
+		
+		// To avoid noise an average is realized on 8 samples
+		motor->motor_status.speed_average += temp_rpm;
+		if(motor->motor_status.count >= n_SAMPLE)
+		{
+			
+			motor->motor_status.count = 1;
+			motor->motor_status.calc_rpm = (motor->motor_status.speed_average >> 3); // divide by 8
+			//Motor1.motor_status.calc_rpm = (speed_average); // divide by 8
+			motor->motor_status.speed_average = 0;
+			//*Spare_byte1 = motorState.actualDirection;
+			if(motor->motor_status.actualDirection == CCW) /* Changed from CCW */
+			{
+				//*motor_speed = -1* Motor1.calc_rpm;
+				motor->motor_status.calc_rpm = -1* motor->motor_status.calc_rpm;
+			} else { 
+				//*motor_speed = Motor1.calc_rpm;
+				motor->motor_status.calc_rpm = motor->motor_status.calc_rpm;
+			}
+			return;
+		}
+		else motor->motor_status.count++;
+	#endif
+	
+	motor->motor_status.calc_rpm = (int16_t)temp_rpm;
+	//toc_port(DEBUG_2_PORT);	
+}
+
+
+void disable_phases(BLDCMotor_t* const motor)
+{
+	Tcc * tmp = (Tcc *)motor->pwm_desc->device.hw;
+	tmp->PATTBUF.reg = DISABLE_PATTERN;
+}
+
+//------------------------------------------------------------------------------
+// pi current control
+//------------------------------------------------------------------------------
+void BLDC_runCurrentCntl(BLDCMotor_t *motor, const float32_t curfbk, const float32_t curRef)
+{
+	motor->controllers.Pi_Idc.Fbk_pu = f_clamp(curfbk, -DEVICE_SHUNT_CURRENT_A, DEVICE_SHUNT_CURRENT_A); // Clamped to max current sensor readingspeedfbk;
+	motor->controllers.Pi_Idc.Ref_pu = f_clamp(curRef, -motor->motor_param->motor_Max_Current_IDC_A, 
+														motor->motor_param->motor_Max_Current_IDC_A);	// Clamp desired to Motor Max Current i_ref_clamped;
+	
+	//*Spare_1 = (int16_t)(motor->controllers.Pi_Idc.Ref_pu * 1000);  // Send Req Current to TC
+
+	motor->controllers.Pi_Idc.OutMax_pu = motor->VdcBus_pu;
+	motor->controllers.Pi_Idc.OutMin_pu = -motor->VdcBus_pu;
+	PI_run_series(&motor->controllers.Pi_Idc);
+	
+	if(motor->controllers.Pi_Idc.Out_pu > 0) {
+		motor->motor_setpoints.desiredDirection = 0; 
+		motor->motor_setpoints.directionOffset = 0;
+	} else {
+		motor->motor_setpoints.desiredDirection = 1;
+		motor->motor_setpoints.directionOffset = 8;
+	}
+
+	volatile float32_t duty_pu = f_abs((motor->controllers.Pi_Idc.Out_pu * motor->VoneByDcBus_pu));
+	//motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
+	//motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
+	motor->motor_status.duty_cycle = (uint16_t)f_clamp(duty_pu * motor->motor_param->motor_MaxPWM, 0.0f, (float32_t)MAX_PWM);
+	// Remove Low duty cycle values
+	//if(duty_cycle < 80.0) motor->duty_cycle = (uint16_t)0;
+	//else motor->duty_cycle = (uint16_t)duty_cycle;
+	
+}
+
+//// ------------------------------------------------------------------------------
+// Speed Control: Input in RPM units (int16_t)
+//------------------------------------------------------------------------------
+void BLDC_runSpeedCntl(BLDCMotor_t *motor, const float32_t speedfbk, const float32_t speedRef)
+{
+	//tic_port(DEBUG_3_PORT);
+	motor->controllers.Pid_Speed.Fbk_pu = speedfbk; 
+	motor->controllers.Pid_Speed.Ref_pu = f_clamp(speedRef, -motor->motor_param->motor_Max_Spd_RPM, 
+															 motor->motor_param->motor_Max_Spd_RPM);	
+	
+	if (motor->motor_state.currentstate == MOTOR_V_CTRL_STATE)
+	{
+		/* Output Pu in Volts (PWM %) */
+		motor->controllers.Pid_Speed.OutMax_pu = motor->VdcBus_pu;
+		motor->controllers.Pid_Speed.OutMin_pu = -motor->VdcBus_pu;
+		
+		PID_run_parallel(&motor->controllers.Pid_Speed);
+		
+		if(motor->controllers.Pid_Speed.Out_pu > 0) {
+			motor->motor_setpoints.desiredDirection = 0; 
+			motor->motor_setpoints.directionOffset = 0;
+		} else {
+			motor->motor_setpoints.desiredDirection = 1;
+			motor->motor_setpoints.directionOffset = 8;
+		}
+		/* Process unit is Volts */
+		volatile float32_t duty_pu = f_abs((motor->controllers.Pid_Speed.Out_pu * motor->VoneByDcBus_pu));
+		volatile float32_t duty_cycle = f_clamp(duty_pu *  (float32_t)MAX_PWM, 0.0f, (float32_t)MAX_PWM);
+		motor->motor_status.duty_cycle = (uint16_t)duty_cycle;
+	} else 	{
+		/* Pu in Current (Amps) */
+		motor->controllers.Pid_Speed.OutMax_pu =  (motor->motor_param->motor_Max_Current_IDC_A);
+		motor->controllers.Pid_Speed.OutMin_pu = -(motor->motor_param->motor_Max_Current_IDC_A);
+		PID_run_parallel(&motor->controllers.Pid_Speed);
+		motor->controllers.Pi_Idc.Ref_pu = motor->controllers.Pid_Speed.Out_pu;
+	}
+	//toc_port(DEBUG_3_PORT);
+}
+
+//// ------------------------------------------------------------------------------
+// Position Control:Input in Hall step units (int16_t)
+//------------------------------------------------------------------------------
+void BLDC_runPosCntl(BLDCMotor_t *motor, const int16_t posfbk, const int16_t posRef)
+{
+	/* Output Pu in RPM */
+	motor->controllers.Pi_Pos.OutMax_pu = motor->motor_param->motor_Max_Spd_RPM;
+	motor->controllers.Pi_Pos.OutMin_pu = -motor->motor_param->motor_Max_Spd_RPM;
+	motor->controllers.Pi_Pos.Fbk_pu = posfbk;	
+	motor->controllers.Pi_Pos.Ref_pu = posRef;	
+	PI_run_series(&motor->controllers.Pi_Pos);
+	motor->controllers.Pid_Speed.Ref_pu = motor->controllers.Pi_Pos.Out_pu;
+}
+
+void BLDC_runOpenLoop(BLDCMotor_t *motor, int16_t duty)
+{
+	if (duty < 0){
+		motor->motor_setpoints.directionOffset = DIRECTION_CCW_OFFSET;
+	} else {
+		motor->motor_setpoints.directionOffset = DIRECTION_CW_OFFSET;
+	}
+	motor->motor_status.duty_cycle = u_clamp(abs(duty), 0, MAX_PWM); 
+}
+
+volatile uint8_t readHallSensorM1(void)
+{
+	
+	volatile uint8_t motor_read = 0;
+	motor_read = (motor_read & M1_HALL_A_MASK) | (uint8_t)((PORT->Group[M1_HALL_A_GROUP].IN.reg & M1_HALL_A_PORT)>>(M1_HALL_A_LSR));
+	motor_read = (motor_read & M1_HALL_B_MASK) | (uint8_t)((PORT->Group[M1_HALL_B_GROUP].IN.reg & M1_HALL_B_PORT)>>(M1_HALL_B_LSR));
+	motor_read = (motor_read & M1_HALL_C_MASK) | (uint8_t)((PORT->Group[M1_HALL_C_GROUP].IN.reg & M1_HALL_C_PORT)>>(M1_HALL_C_LSR));
+	return motor_read;
+	
+	//volatile uint8_t a = gpio_get_pin_level(M1_HALL_A_PIN);
+	//volatile uint8_t b = gpio_get_pin_level(M1_HALL_B_PIN);
+	//volatile uint8_t c = gpio_get_pin_level(M1_HALL_C_PIN);
+	//return ((a << 2)	|
+			//(b << 1)	|
+			//(c << 0));
+	
+}
+
+volatile uint8_t readHallSensorM2(void)
+{
+	
+	volatile uint8_t motor_read = 0;
+	motor_read = (motor_read & M2_HALL_A_MASK) | (uint8_t)((PORT->Group[M2_HALL_A_GROUP].IN.reg & M2_HALL_A_PORT)>>(M2_HALL_A_LSR)); 
+	motor_read = (motor_read & M2_HALL_B_MASK) | (uint8_t)((PORT->Group[M2_HALL_B_GROUP].IN.reg & M2_HALL_B_PORT)>>(M2_HALL_B_LSR)); 
+	motor_read = (motor_read & M2_HALL_C_MASK) | (uint8_t)((PORT->Group[M2_HALL_C_GROUP].IN.reg & M2_HALL_C_PORT)>>(M2_HALL_C_LSR)); 
+	
+	return motor_read;
+	//if(((motor_read == INVALID_HALL_0) || (motor_read == INVALID_HALL_7))) {
+		//Motor2.motor_state.fault = MOTOR_HALLSENSORINVALID;
+		//Motor2.motor_state.currentstate = MOTOR_FAULT;
+		////applicationStatus.currentstate = APP_FAULT;
+	//}
+		
+	//volatile uint8_t a = gpio_get_pin_level(M2_HALL_A_PIN);
+	//volatile uint8_t b = gpio_get_pin_level(M2_HALL_B_PIN);
+	//volatile uint8_t c = gpio_get_pin_level(M2_HALL_C_PIN);	
+	//volatile uint8_t motor_read2 = ((a << 2)|(b << 1)|(c << 0));
+	//return ((a << 2)	|
+			//(b << 1)	|
+			//(c << 0));
+	
+}
+
+// ----------------------------------------------------------------------
+// Before Power up, Measure and average offset voltage for Current Sensor
+// This voltage is subtracted from all reading for Bi-Directional Current
+// Measurement
+// ----------------------------------------------------------------------
+void read_zero_current_offset_value(BLDCMotor_t *motor1, BLDCMotor_t *motor2)
+{
+	volatile int32_t phase_zero_current_offset [NUM_CUR_SENSORS] = {0};
+	volatile int16_t zero_current_offset_temp = 0;
+	const uint8_t samples = 32;
+	
+	adc_sync_enable_channel(&ADC_1, 9);
+	for (int n=0; n<NUM_CUR_SENSORS; n++)
+	{
+		ADC1->INPUTCTRL.reg = adc1_seq_regs[n];
+		for (int i=0; i<samples; i++)
+		{
+			while (ADC1->STATUS.bit.ADCBUSY) {};					 /* Wait for bus synchronization. */
+			ADC1->SWTRIG.bit.START = true;							 /* Start the ADC using a software trigger. */
+			while (ADC1->INTFLAG.bit.RESRDY == 0);					 /* Wait for the result ready flag to be set. */
+			ADC1->INTFLAG.reg = ADC_INTFLAG_RESRDY;					 /* Clear the flag. */
+			zero_current_offset_temp	= (int16_t)ADC1->RESULT.reg; /* Read the value. */
+			phase_zero_current_offset[n] += zero_current_offset_temp;
+		}
+		phase_zero_current_offset[n] = 	phase_zero_current_offset[n]/samples;
+	}
+	adc_sync_disable_channel(&ADC_1, 9);
+	
+	motor1->Voffset_lsb.A = phase_zero_current_offset[0];
+	motor1->Voffset_lsb.B = phase_zero_current_offset[1];
+	motor2->Voffset_lsb.A = phase_zero_current_offset[2];
+	motor2->Voffset_lsb.B = phase_zero_current_offset[3];
+	
+	/* Check for Defective current sensor based on offset from nominal 1.5V (O current voltage) */
+	
+	if ((abs(motor1->Voffset_lsb.A) > MAX_CUR_SENSE_OFFSET) || (abs(motor1->Voffset_lsb.B) > MAX_CUR_SENSE_OFFSET))
+	{
+		motor1->motor_state.currentstate = MOTOR_FAULT;
+		motor1->motor_state.fault = MOTOR_CURRENTS_SENSOR;
+	}
+	
+	if ((abs(motor2->Voffset_lsb.A) > MAX_CUR_SENSE_OFFSET) || (abs(motor2->Voffset_lsb.B) > MAX_CUR_SENSE_OFFSET))
+	{
+		motor2->motor_state.currentstate = MOTOR_FAULT;
+		motor2->motor_state.fault = MOTOR_CURRENTS_SENSOR;
+	}
+}

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc.h

@@ -0,0 +1,110 @@
+/*
+ * bldc.h
+ *
+ * Created: 31/07/2021 14:56:02
+ *  Author: Nick-XMG
+ */ 
+
+#ifndef BLDC_H_
+#define BLDC_H_
+
+// ----------------------------------------------------------------------
+// 	header files
+// ----------------------------------------------------------------------
+#include "atmel_start.h"
+#include "bldc_types.h"
+#include "motorparameters.h"
+#include "statemachine.h"
+
+#define PWM_TOP					(1000)
+#define MAX_PWM					(800)
+//#define MAX_VEL					3800
+
+#define CW						(0) //CBA
+#define DIRECTION_CW_OFFSET		(0) //CBA
+#define CCW						(1) //ABC
+#define DIRECTION_CCW_OFFSET	(8) //CBA
+
+/* if the Hall sensor reads 0x0 or 0x7 that means either one of the hall sensor is damaged or disconnected*/
+#define INVALID_HALL_0              (0)
+#define INVALID_HALL_7              (7)
+
+//#define AVERAGE_SPEED_MEASURE		1
+#define n_SAMPLE 8
+
+// ----------------------------------------------------------------------
+// 	ADC Parameters
+// ----------------------------------------------------------------------
+#define ADC_VOLTAGE_REFERENCE		(3.0f)
+#define ADC_RESOLUTION				(12)
+#define ADC_MAX_COUNTS				(1<<ADC_RESOLUTION)
+#define ADC_LSB_SIZE				(ADC_VOLTAGE_REFERENCE/ADC_MAX_COUNTS)
+#define LSB_TO_PU					(ADC_LSB_SIZE * ONEON_CURRENT_SENSOR_SENSITIVITY)
+
+//static const uint32_t adc1_seq_regs[4]	= {0x0089, 0x0088, 0x0087, 0x0086};
+//static volatile int16_t adc0_res[4]	= {0};
+//static volatile int16_t adc1_res[4]	= {0};
+	
+extern const uint32_t adc1_seq_regs[4];
+extern volatile int16_t adc1_res[4];
+
+// ----------------------------------------------------------------------
+// Define the control and PWM frequencies:
+// ----------------------------------------------------------------------
+#define DEVICE_MCU_FREQUENCY_Hz        (120000000U)
+#define DEVICE_SPEEDTC_DIV			   (4U)
+#define DEVICE_SPEEDTC_FREQUENCY_Hz    (DEVICE_MCU_FREQUENCY_Hz/DEVICE_SPEEDTC_DIV)
+#define DEVICE_PWM_FREQUENCY_kHz       (25.0f)
+#define DEVICE_ISR_FREQUENCY_kHz       DEVICE_PWM_FREQUENCY_kHz
+#define DEVICE_ISR_PERIOD_Sec		   (0.001f/DEVICE_ISR_FREQUENCY_kHz)
+#define HZ_TO_RPM					   (DEVICE_SPEEDTC_FREQUENCY_Hz * 60)
+//#define HZ_TO_RPM					   MOTOR_COMUTATION_STATES/(DEVICE_SPEEDTC_FREQUENCY_Hz * 60)
+
+// ----------------------------------------------------------------------
+// Define the device quantities (voltage, current, speed)
+// ----------------------------------------------------------------------
+#define DEVICE_DC_VOLTAGE_V					24.0f   // max. ADC bus voltage(PEAK) [V]
+#define DEVICE_SHUNT_CURRENT_A				2.5f    // phase current(PEAK) [A]
+#define CURRENT_SENSOR_SENSITIVITY			0.4f    //V/A
+#define ONEON_CURRENT_SENSOR_SENSITIVITY	2.5f    //V/A
+#define MAX_CUR_SENSE_OFFSET				100
+#define NUM_CUR_SENSORS						4
+// ----------------------------------------------------------------------
+// 	global variables
+// ----------------------------------------------------------------------
+
+static const uint8_t HALL_PATTERN_ARRAY[16]		= {0, 5, 3, 1, 6, 4, 2, 0, 0, 3, 6, 2, 5, 1, 4, 0 };
+static const uint8_t MOTOR_COMMUTATION_STEPS[8]		= {9, 1, 3, 2, 5, 6, 4, 9};
+
+static volatile BLDCMotor_t Motor1 = {
+	.pwm_desc = &PWM_0,
+	.speedtimer_hw = TC2,
+};
+static volatile BLDCMotor_t Motor2  = {
+	.pwm_desc = &PWM_1,
+	.speedtimer_hw = TC4,
+};
+
+static volatile MOTOR_STATE_t Motor1_Status;
+static volatile MOTOR_STATE_t Motor2_Status;
+
+// ----------------------------------------------------------------------
+// 	functions
+// ----------------------------------------------------------------------
+void motor_StateMachine(BLDCMotor_t* const motor);
+void BldcInitStruct(BLDCMotor_t* const motor, BLDCMotor_param_t* constmotor_param);
+void exec_commutation(BLDCMotor_t* const motor);
+void select_active_phase(BLDCMotor_t* const Motor);
+void calculate_motor_speed(BLDCMotor_t* const motor);
+void disable_phases(BLDCMotor_t* const motor);
+// ----------------------------------------------------------------------
+// 	Static Functions
+// ----------------------------------------------------------------------
+static void BLDC_runSpeedCntl(BLDCMotor_t *motor, const float32_t speedfbk, const float32_t speedRef);
+static void BLDC_runCurrentCntl(BLDCMotor_t *motor, const float32_t curfbk, const float32_t curRef);
+static void BLDC_runPosCntl(BLDCMotor_t *motor, int16_t posfbk, int16_t posRef);
+static void BLDC_runOpenLoop(BLDCMotor_t *motor, int16_t duty);
+volatile uint8_t readHallSensorM1(void);
+volatile uint8_t readHallSensorM2(void);
+
+#endif /* BLDC_H_ */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/bldc_types.h

@@ -0,0 +1,107 @@
+/*
+ * bldc_types.h
+ *
+ * Created: 8/5/2021 9:40:45 AM
+ *  Author: ge37vez
+ */ 
+
+
+#ifndef BLDC_TYPES_H_
+#define BLDC_TYPES_H_
+
+#include "atmel_start.h"
+#include "control.h"
+#include "motorparameters.h"
+#include "statemachine.h"
+
+// ----------------------------------------------------------------------
+// 	function Pointer
+// ----------------------------------------------------------------------
+typedef uint8_t (*readHallSensor)(void);
+
+// ----------------------------------------------------------------------
+// 	Type Definitions
+// ----------------------------------------------------------------------
+volatile typedef struct
+{
+	volatile float32_t A;          // Phase A
+	volatile float32_t B;          // Phase B
+	volatile float32_t C;          // Phase C
+	volatile float32_t Bus;        // Currently Active Phase Current
+} MOTOR_PHASES_t;
+
+volatile typedef struct
+{
+	volatile int16_t A;          // Phase A measured offset
+	volatile int16_t B;          // Phase B measured offset
+} MOTOR_phase_offset_t;
+
+volatile typedef struct timerflags
+{
+	volatile bool pwm_cycle_tic;
+	volatile bool current_loop_tic;
+	volatile bool control_loop_tic;
+	volatile bool adc_readings_ready_tic;
+	volatile bool motor_telemetry_flag;
+}	TIMERflags_t;
+
+volatile typedef struct
+{
+	volatile uint8_t   desiredDirection;	//! The desired direction of rotation.
+	volatile uint8_t   directionOffset;
+	volatile float32_t desired_torque;
+	volatile int16_t   desired_speed;
+	volatile int16_t   desired_position;
+	volatile float32_t max_torque;
+	volatile float32_t max_current;
+	volatile int16_t   max_velocity;
+}	MOTOR_Setpoints;
+
+volatile typedef struct
+{
+	volatile uint8_t   actualDirection;	//! The actual direction of rotation.
+	volatile uint16_t  duty_cycle;
+	volatile int16_t   calc_rpm;
+	volatile int16_t   abs_position;
+	volatile int16_t   Num_Steps;
+	/* Hall States */
+	//volatile uint8_t   prevHallPattern;
+	volatile uint8_t   currentHallPattern;
+	//volatile uint8_t   nextHallPattern;
+	/* Commutation State */
+	volatile uint8_t   cur_comm_step;
+	volatile uint8_t   prev_comm_step;
+	volatile uint32_t speed_average;
+	volatile uint8_t count;
+}	MOTOR_Status;
+
+// ----------------------------------------------------------------------
+// 	Main BLDC Struct
+// ----------------------------------------------------------------------
+volatile typedef struct BLDCmotor
+{
+	/* Hardware */
+	volatile BLDCMotor_param_t *motor_param;
+	struct pwm_descriptor const *pwm_desc;
+	void *const speedtimer_hw;
+	/* Status */
+	volatile MOTOR_STATE_t motor_state;
+	volatile MOTOR_Status motor_status;
+	/* Measured Values */
+	volatile MOTOR_PHASES_t Iphase_pu;
+	volatile MOTOR_phase_offset_t Voffset_lsb;
+	volatile float32_t VdcBus_pu, VoneByDcBus_pu;
+	/* Motor Flags */
+	volatile TIMERflags_t timerflags;
+	volatile uint8_t regulation_loop_count;
+	/* Controllers */
+	volatile MOTOR_Control_Structs controllers;
+	/* Setpoints */
+	volatile MOTOR_Setpoints motor_setpoints;
+	/* Function Pointers*/
+	volatile readHallSensor readHall;
+} BLDCMotor_t;
+
+
+
+#endif /* BLDC_TYPES_H_ */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/configuration.h

@@ -0,0 +1,449 @@
+/*
+ * configuration.h
+ *
+ * Created: 02/08/2021 21:15:49
+ *  Author: Nick-XMG
+ */ 
+
+#ifndef CONFIGURATION_H_
+#define CONFIGURATION_H_
+
+// ----------------------------------------------------------------------	
+// ----------------------------------------------------------------------	
+// ----------------------------------------------------------------------
+// Configure System to be either Master or Slave.  Set only one of these 
+// ----------------------------------------------------------------------
+#define _MASTER
+//#define _SLAVE
+// ----------------------------------------------------------------------	
+// ----------------------------------------------------------------------	
+// ----------------------------------------------------------------------
+// ----------------------------------------------------------------------		
+	
+
+// ----------------------------------------------------------------------
+// Header Files
+// ----------------------------------------------------------------------
+
+#ifdef _MASTER
+#include "EtherCAT_QSPI.h"
+#endif // MASTER
+#ifdef _SLAVE
+#include "MSIF_slave.h"
+#endif // SLAVE
+
+#include "atmel_start_pins.h"
+#include "bldc.h"
+#include "interrupts.h"
+#include "hpl_sercom_config.h"
+#include "ADS1299.h"
+#include "hpl_spi_m_dma.h"
+
+#ifdef _SLAVE
+#include "hal_spi_s_sync.h"
+#include "hpl_spi_s_sync.h"
+#endif // SLAVE
+
+/* DMA channel Descriptor */
+extern DmacDescriptor _descriptor_section[DMAC_CH_NUM];
+extern DmacDescriptor _write_back_section[DMAC_CH_NUM];
+
+// ----------------------------------------------------------------------
+// DMA CHANNEL NUMBER CONFIGURATION
+// ----------------------------------------------------------------------
+/* MASTER
+* CH0 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin
+* CH1 - SERCOM5_RX(SPI3) - Angle Sensor
+* CH2 - SERCOM2_RX(SPI2) - Expansion IF (EMG) - Beat Transfer Event Drives CS Pin
+* CH3 - ADC1 - Result Ready
+* CH4 - ADC1 - Sequencer - Triggered by TCC0 overflow event
+* CH5 - SERCOM2_TX(SPI2) - Expansion IF (EMG)
+* CH6 - SERCOM5_TX(SPI3) - Angle Sensor
+* CH7 - SERCOM1_TX(SPI1) - Master-Slave IF
+SLAVE
+* CH0 - SERCOM1_RX(SPI1) - Master-Slave IF - Beat Transfer Event Drives CS Pin
+* CH1 - SERCOM5_RX(SPI3) - Angle Sensor
+* CH2 - ADC0 - Result Ready
+* CH3 - ADC1 - Result Ready
+* CH4 - ADC1 - Sequencer - Triggered by TCC0 overflow event
+* CH5 - ADC0 - Sequencer
+* CH6 - SERCOM5_TX(SPI3) - Angle Sensor
+* CH7 - SERCOM1_TX(SPI1) - Master-Slave IF
+*/
+
+#define CONF_SERCOM_1_SPI_DMA_RX_CHANNEL		0U
+#define CONF_SERCOM_1_SPI_DMA_TX_CHANNEL		7U
+#define CONF_ADC_1_ADC_RES_READY_CHANNEL		3U
+#define CONF_ADC_1_SEQUENCER_CHANNEL			4U
+
+#ifdef _MASTER
+	#define CONF_SERCOM_2_SPI_DMA_RX_CHANNEL	2U
+	#define CONF_SERCOM_2_SPI_DMA_TX_CHANNEL	5U
+#else
+	#define CONF_ADC_0_ADC_RES_READY_CHANNEL	2U
+	#define CONF_ADC_0_SEQUENCER_CHANNEL		5U
+#endif 
+
+// ----------------------------------------------------------------------
+// PWM Timer Initialization
+// ----------------------------------------------------------------------
+static void configure_tcc_pwm(void)
+{	
+	/* TCC0 */
+	hri_tcc_set_WEXCTRL_OTMX_bf(TCC0, 0x02);
+	
+	hri_tcc_set_WAVE_POL0_bit(TCC0);
+	hri_tcc_set_WAVE_POL1_bit(TCC0);
+	hri_tcc_set_WAVE_POL2_bit(TCC0);
+	hri_tcc_set_WAVE_POL3_bit(TCC0);
+	hri_tcc_set_WAVE_POL4_bit(TCC0);
+	hri_tcc_set_WAVE_POL5_bit(TCC0);
+	hri_tcc_write_CC_CC_bf(TCC0, 0, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 1, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 2, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 3, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 4, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 5, 0);
+	hri_tcc_write_PER_reg(TCC0,1200);
+	//hri_tcc_write_CCBUF_CCBUF_bf(TCC0, 0,250);
+	hri_tcc_write_CTRLA_ENABLE_bit(TCC0, 1 << TCC_CTRLA_ENABLE_Pos);	
+	
+	/* TCC1 */
+	hri_tcc_set_WEXCTRL_OTMX_bf(TCC1, 0x02);
+	hri_tcc_write_CC_CC_bf(TCC1, 0, 0);
+	hri_tcc_write_CC_CC_bf(TCC1, 1, 0);
+	hri_tcc_write_CC_CC_bf(TCC1, 2, 0);
+	hri_tcc_write_CC_CC_bf(TCC1, 3, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 4, 0);
+	hri_tcc_write_CC_CC_bf(TCC0, 5, 0);
+	//
+	////pwm_set_parameters(&TCC_PWM, 1000, 250);
+	hri_tcc_set_WAVE_POL0_bit(TCC1);
+	hri_tcc_set_WAVE_POL1_bit(TCC1);
+	hri_tcc_set_WAVE_POL2_bit(TCC1);
+	hri_tcc_set_WAVE_POL3_bit(TCC1);
+	hri_tcc_set_WAVE_POL4_bit(TCC1);
+	hri_tcc_set_WAVE_POL5_bit(TCC1);
+	
+	hri_tcc_write_PER_reg(TCC1,1200);
+	//hri_tcc_write_CCBUF_CCBUF_bf(TCC1, 0, 250);
+	hri_tcc_clear_CTRLA_ENABLE_bit(TCC1);
+	hri_tcc_write_CTRLA_MSYNC_bit(TCC1, true);
+	//hri_tcc_write_CTRLA_ENABLE_bit(TCC1, 1 << TCC_CTRLA_ENABLE_Pos); /* Enable: enabled */
+	
+	//pwm_register_callback(&PWM_0, PWM_PERIOD_CB, pwm_cb);
+	pwm_enable(&PWM_0);
+	pwm_enable(&PWM_1);
+}
+
+// ----------------------------------------------------------------------
+// ADC DMA Initialization
+// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
+// FSR1 =ADC0_AIN[0], FSR2 =ADC0_AIN[3], FSR3 =ADC0_AIN[7], FSR4 =ADC0_AIN[10], FSR5 =ADC0_AIN[11]
+// ----------------------------------------------------------------------
+#define CURRENT_SENSOR_CHANNELS 4U
+#define SENSOR_CHANNELS			5U
+const uint32_t adc0_seq_regs[SENSOR_CHANNELS]	   = {0x1801, 0x1803, 0x1807, 0x180A, 0x180B };	/* Single Ended */
+const uint32_t adc1_seq_regs[4]					   = {0x0089, 0x0088, 0x0087, 0x0086};			/* Differential */
+//const uint32_t adc1_seq_regs[4]				   = {0x1807, 0x1806, 0x1809, 0x1808};			/* Single Ended */
+volatile int16_t adc1_res[CURRENT_SENSOR_CHANNELS] = {0};
+
+struct _dma_resource *adc0_sram_dma_resource;
+struct _dma_resource *adc1_sram_dma_resource;
+
+#ifdef _SLAVE
+static void adc0_dmac_sequence_init()
+{
+	/* Configure the DMAC source address, destination address,
+	 * next descriptor address, data count and Enable the DMAC Channel 
+	 */
+	_dma_set_source_address(CONF_ADC_0_SEQUENCER_CHANNEL, (const void *)adc0_seq_regs);
+	_dma_set_destination_address(CONF_ADC_0_SEQUENCER_CHANNEL, (const void *)&ADC0->DSEQDATA.reg);
+	_dma_set_data_amount(CONF_ADC_0_SEQUENCER_CHANNEL, 4);
+	_dma_set_next_descriptor(CONF_ADC_0_SEQUENCER_CHANNEL, CONF_ADC_0_SEQUENCER_CHANNEL);
+	_dma_enable_transaction(CONF_ADC_0_SEQUENCER_CHANNEL, false);
+	hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[CONF_ADC_0_SEQUENCER_CHANNEL], 0x01);	//Suspend
+}
+
+static void adc0_sram_dmac_init()
+{
+	_dma_set_source_address(CONF_ADC_0_ADC_RES_READY_CHANNEL, (const void *)&ADC0->RESULT.reg);
+	_dma_set_destination_address(CONF_ADC_0_ADC_RES_READY_CHANNEL, (const void *)&FSR_CH1);
+	_dma_set_data_amount(CONF_ADC_0_ADC_RES_READY_CHANNEL, SENSOR_CHANNELS);
+	_dma_set_irq_state(CONF_ADC_0_ADC_RES_READY_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
+	_dma_get_channel_resource(&adc1_sram_dma_resource, CONF_ADC_0_ADC_RES_READY_CHANNEL);
+	adc1_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback;
+	_dma_set_next_descriptor(CONF_ADC_0_ADC_RES_READY_CHANNEL, CONF_ADC_0_ADC_RES_READY_CHANNEL); /*?????*/
+	_dma_enable_transaction(CONF_ADC_0_ADC_RES_READY_CHANNEL, false);
+}
+#endif //SLAVE
+
+static void adc1_dmac_sequence_init()
+{
+	/* Configure the DMAC source address, destination address,
+	 * next descriptor address, data count and Enable the DMAC Channel 
+	 */
+	_dma_set_source_address(CONF_ADC_1_SEQUENCER_CHANNEL, (const void *)adc1_seq_regs);
+	_dma_set_destination_address(CONF_ADC_1_SEQUENCER_CHANNEL, (const void *)&ADC1->DSEQDATA.reg);
+	_dma_set_data_amount(CONF_ADC_1_SEQUENCER_CHANNEL, CURRENT_SENSOR_CHANNELS);
+	_dma_set_next_descriptor(CONF_ADC_1_SEQUENCER_CHANNEL, CONF_ADC_1_SEQUENCER_CHANNEL);
+	_dma_enable_transaction(CONF_ADC_1_SEQUENCER_CHANNEL, false);
+	hri_dmacchannel_set_CHCTRLB_CMD_bf(&DMAC->Channel[CONF_ADC_1_SEQUENCER_CHANNEL], 0x01);	//Suspend
+}
+
+static void adc1_sram_dmac_init()
+{
+	_dma_set_source_address(CONF_ADC_1_ADC_RES_READY_CHANNEL, (const void *)&ADC1->RESULT.reg);
+	_dma_set_destination_address(CONF_ADC_1_ADC_RES_READY_CHANNEL, (const void *)adc1_res);
+	_dma_set_data_amount(CONF_ADC_1_ADC_RES_READY_CHANNEL, CURRENT_SENSOR_CHANNELS);
+	_dma_set_irq_state(CONF_ADC_1_ADC_RES_READY_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
+	_dma_get_channel_resource(&adc1_sram_dma_resource, CONF_ADC_1_ADC_RES_READY_CHANNEL);
+	adc1_sram_dma_resource[0].dma_cb.transfer_done = adc_sram_dma_callback;
+	_dma_set_next_descriptor(CONF_ADC_1_ADC_RES_READY_CHANNEL, CONF_ADC_1_ADC_RES_READY_CHANNEL); /*?????*/
+	_dma_enable_transaction(CONF_ADC_1_ADC_RES_READY_CHANNEL, false);
+}
+
+// ----------------------------------------------------------------------
+// ADC Initialization
+// ----------------------------------------------------------------------
+#ifdef _SLAVE
+static void adc0_dma_init(void)
+{
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(GPIO(GPIO_PORTA, 2), GPIO_DIRECTION_OFF);
+	gpio_set_pin_function(GPIO(GPIO_PORTA, 2), PINMUX_PA02B_ADC0_AIN0);
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(GPIO(GPIO_PORTB, 9), GPIO_DIRECTION_OFF);
+	gpio_set_pin_function(GPIO(GPIO_PORTB, 9), PINMUX_PB09B_ADC0_AIN3);
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(GPIO(GPIO_PORTA, 7), GPIO_DIRECTION_OFF);
+	gpio_set_pin_function(GPIO(GPIO_PORTA, 7), PINMUX_PA07B_ADC0_AIN7);
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(GPIO(GPIO_PORTA, 10), GPIO_DIRECTION_OFF);
+	gpio_set_pin_function(GPIO(GPIO_PORTA, 10), PINMUX_PA10B_ADC0_AIN10);
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(GPIO(GPIO_PORTA, 11), GPIO_DIRECTION_OFF);
+	gpio_set_pin_function(GPIO(GPIO_PORTA, 11), PINMUX_PA11B_ADC0_AIN11);
+	
+	adc0_sram_dmac_init();
+	adc0_dmac_sequence_init();
+	hri_adc_set_DSEQCTRL_INPUTCTRL_bit(ADC0);
+	hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC0);
+}
+#endif //SLAVE
+
+static void adc1_dma_init(void)
+{
+	adc1_sram_dmac_init();
+	adc1_dmac_sequence_init();
+	hri_adc_set_DSEQCTRL_INPUTCTRL_bit(ADC1);
+	hri_adc_set_DSEQCTRL_AUTOSTART_bit(ADC1);
+}
+
+
+
+// ----------------------------------------------------------------------
+// SPI DMA communication between Master & Slave Board
+// ----------------------------------------------------------------------
+#define MASTER_SLAVE_BUFFER_SIZE	64
+#define MASTER_SLAVE_BUFFER_SIZE_LONG	MASTER_SLAVE_BUFFER_SIZE/4
+
+static void boardToBoardTransferInit(void)
+{
+	#ifdef _MASTER
+		struct io_descriptor *io;
+		spi_m_dma_get_io_descriptor(&SPI_1_MSIF_M, &io);
+		//spi_m_dma_register_callback(&SPI_1_MSIF, SPI_M_DMA_CB_RX_DONE, b2bTransferComplete_cb);
+		//SERCOM4->SPI.CTRLC.bit.DATA32B = true;
+		//SERCOM1->SPI.LENGTH.bit.LENEN = true;
+		//SERCOM1->SPI.LENGTH.bit.LEN = 64;
+	
+		SERCOM1->SPI.CTRLC.bit.ICSPACE = 4;
+		SERCOM1->SPI.CTRLC.bit.DATA32B= true;
+		gpio_set_pin_level(SPI1_CS, true);
+		spi_m_dma_enable(&SPI_1_MSIF_M);
+	#endif //MASTER
+	#ifdef _SLAVE
+		spi_m_dma_deinit(&SPI_1_MSIF_M);
+		spi_s_sync_init(&SPI_1_MSIF_S, SERCOM1);
+		SPI_1_MSIF_Slave_PORT_init();
+		SERCOM1->SPI.CTRLC.bit.DATA32B = true;
+		hri_sercomspi_set_CTRLB_PLOADEN_bit(SERCOM1);
+		hri_sercomspi_write_CTRLA_MODE_bf(SERCOM1, 0x02);
+		hri_sercomspi_write_CTRLB_MSSEN_bit(SERCOM1, true);
+		spi_s_sync_enable(&SPI_1_MSIF_S);
+		
+		NVIC_DisableIRQ((IRQn_Type)SERCOM1_1_IRQn);
+		NVIC_ClearPendingIRQ((IRQn_Type)SERCOM1_1_IRQn);
+		NVIC_EnableIRQ((IRQn_Type)SERCOM1_1_IRQn);
+		hri_sercomspi_set_INTEN_TXC_bit(SERCOM1);
+		hri_sercomspi_set_INTEN_SSL_bit(SERCOM1);
+	#endif //SLAVE
+}
+
+
+#ifdef _SLAVE
+void SPI_1_MSIF_Slave_PORT_init(void)
+{
+
+	// Set pin direction to input
+	gpio_set_pin_direction(SPI1_MOSI, GPIO_DIRECTION_IN);
+	gpio_set_pin_pull_mode(SPI1_MOSI,	GPIO_PULL_OFF);
+	gpio_set_pin_function(SPI1_MOSI, PINMUX_PA00D_SERCOM1_PAD0);
+
+	gpio_set_pin_level(SPI1_SCK,	false);
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI1_SCK, GPIO_DIRECTION_OUT);
+	gpio_set_pin_function(SPI1_SCK, PINMUX_PA01D_SERCOM1_PAD1);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(SPI1_CS, GPIO_DIRECTION_IN);
+	gpio_set_pin_pull_mode(SPI1_CS, GPIO_PULL_OFF);
+
+	gpio_set_pin_function(SPI1_CS, PINMUX_PB22C_SERCOM1_PAD2);
+	gpio_set_pin_level(SPI1_MISO, false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI1_MISO, GPIO_DIRECTION_OUT);
+	gpio_set_pin_function(SPI1_MISO, PINMUX_PB23C_SERCOM1_PAD3);
+}
+#endif //SLAVE
+
+static void spi_master_slave_if_dma_descriptor_init()
+{
+	#ifdef _MASTER
+		_dma_set_source_address(CONF_SERCOM_1_SPI_DMA_RX_CHANNEL,
+								(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF_M.dev.prvt))->DATA.reg));
+		_dma_set_destination_address(CONF_SERCOM_1_SPI_DMA_RX_CHANNEL, &QSPI_tx_buffer[16]);
+		_dma_set_data_amount(CONF_SERCOM_1_SPI_DMA_RX_CHANNEL, MASTER_SLAVE_BUFFER_SIZE_LONG);
+		_dma_set_next_descriptor(CONF_SERCOM_1_SPI_DMA_RX_CHANNEL, CONF_SERCOM_1_SPI_DMA_RX_CHANNEL);
+	
+	
+		_dma_set_source_address(CONF_SERCOM_1_SPI_DMA_TX_CHANNEL, &QSPI_rx_buffer[16]);
+		_dma_set_destination_address(CONF_SERCOM_1_SPI_DMA_TX_CHANNEL,
+									(uint32_t *)&(((SercomSpi *)(SPI_1_MSIF_M.dev.prvt))->DATA.reg));
+		_dma_set_data_amount(CONF_SERCOM_1_SPI_DMA_TX_CHANNEL, MASTER_SLAVE_BUFFER_SIZE_LONG);
+		_dma_set_next_descriptor(CONF_SERCOM_1_SPI_DMA_TX_CHANNEL, CONF_SERCOM_1_SPI_DMA_TX_CHANNEL);
+	
+	
+		hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_DMA_TX_CHANNEL]);
+		hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_1_SPI_DMA_RX_CHANNEL]);
+	
+		/* callback */
+		//struct _dma_resource *resource_rx, *resource_tx;
+		//_dma_get_channel_resource(&resource_rx, CONF_SERCOM_1_SPI_M_DMA_RX_CHANNEL);
+		//_dma_get_channel_resource(&resource_tx, CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL);
+		//resource_rx->dma_cb.transfer_done = spi_slave_rx_complete_cb;
+		//resource_tx->dma_cb.transfer_done = b2bTransferComplete_cb;
+
+		/* Enable DMA transfer complete interrupt */
+		//_dma_set_irq_state(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, DMA_TRANSFER_COMPLETE_CB, true);
+	#endif //MASTER
+	#ifdef _SLAVE
+	
+	
+	#endif //SLAVE
+}
+
+
+
+#ifdef _MASTER
+extern volatile uint32_t ads1299_buffer[ADS_BUFFER_SIZE];
+static void spi_ads1299_init_dma_descriptors()
+{
+	_dma_set_source_address(CONF_SERCOM_2_SPI_DMA_RX_CHANNEL,
+						   (uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg));
+	_dma_set_destination_address(CONF_SERCOM_2_SPI_DMA_RX_CHANNEL,  &_ads1299_channel_data[0]);
+	_dma_set_data_amount(CONF_SERCOM_2_SPI_DMA_RX_CHANNEL, ADS_BUFFER_SIZE);
+	_dma_set_next_descriptor(CONF_SERCOM_2_SPI_DMA_RX_CHANNEL, CONF_SERCOM_2_SPI_DMA_RX_CHANNEL);
+	
+	
+	_dma_set_source_address(CONF_SERCOM_2_SPI_DMA_TX_CHANNEL, &ads1299_buffer[0]);
+	_dma_set_destination_address(CONF_SERCOM_2_SPI_DMA_TX_CHANNEL,
+							(uint32_t *)&(((SercomSpi *)(SPI_2.dev.prvt))->DATA.reg));
+	_dma_set_data_amount(CONF_SERCOM_2_SPI_DMA_TX_CHANNEL, ADS_BUFFER_SIZE);
+	_dma_set_next_descriptor(CONF_SERCOM_2_SPI_DMA_TX_CHANNEL, CONF_SERCOM_2_SPI_DMA_TX_CHANNEL);
+	
+	
+	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_DMA_RX_CHANNEL]);
+	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[CONF_SERCOM_2_SPI_DMA_TX_CHANNEL]);
+	
+	
+	/* callback */
+	struct _dma_resource *resource_rx, *resource_tx;
+	_dma_get_channel_resource(&resource_rx, CONF_SERCOM_2_SPI_DMA_RX_CHANNEL);
+	_dma_get_channel_resource(&resource_tx, CONF_SERCOM_2_SPI_DMA_TX_CHANNEL);
+	resource_rx->dma_cb.transfer_done = ADS1299_Transfer_Complete_cb;
+	resource_rx->dma_cb.error = ADS1299_Transfer_error_cb;
+	
+	resource_tx->dma_cb.transfer_done = ADS1299_Transfer_Complete_cb;
+	/* Enable DMA transfer complete interrupt */
+	_dma_set_irq_state(CONF_SERCOM_2_SPI_DMA_RX_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
+	_dma_set_irq_state(CONF_SERCOM_2_SPI_DMA_TX_CHANNEL, DMA_TRANSFER_COMPLETE_CB, true);
+	//_dma_set_irq_state(CONF_SERCOM_2_SPI_M_DMA_RX_CHANNEL, DMA_TRANSFER_ERROR_CB, true);	
+}
+#endif //MASTER
+
+// ----------------------------------------------------------------------
+// Overall DMA Init
+// ----------------------------------------------------------------------
+static void init_dma(void)
+{
+	spi_master_slave_if_dma_descriptor_init();
+	adc1_dma_init();
+	#ifdef _MASTER
+		spi_ads1299_init_dma_descriptors();
+	#else
+		adc0_dma_init();
+	#endif //MASTER
+}
+
+// ----------------------------------------------------------------------
+// Overall DMA Init
+// ----------------------------------------------------------------------
+
+/* Master Event System Configured in ATMEL START.  Slave retains some of
+the same events which are reconfigured and enabled
+* CH0 - TCC0 OVF
+* CH1 - TC0 OVF (1ms) - telemetry
+* CH2 - TC1 OVF (1ms) - Angle Sensor
+* CH3 - CCL output 0
+* CH4 - CCL output 2
+*/
+
+void slave_event_system_config(void)
+{
+	event_system_deinit();
+
+	uint16_t slave_channel_confs[5] = 
+	{ 
+		0x0229,	/* EVGEN = 29(TCC0_OVF)		  , Path = 2(ASYNCHRONOUS), Edgesel = 0(NO_EVT_OUTPUT)*/ 
+		0x0000, //0x0649,	/* EVGEN = 49(TC0_OVF)		  , Path = 2(ASYNCHRONOUS), Edgesel = 1(RISING_EDGE)  */
+		0x0000, //0x044C,	/* EVGEN = 4C(TC1_OVF)		  , Path = 2(ASYNCHRONOUS), Edgesel = 1(RISING_EDGE)  */
+		0x0674,	/* EVGEN = 74(CCL_LUTOUT0)	  , Path = 2(ASYNCHRONOUS), Edgesel = 1(RISING_EDGE)  */
+		0x0276	/* EVGEN = 76(CCL_LUTOUT2), Path = 2(ASYNCHRONOUS), Edgesel = 1(RISING_EDGE)  */
+	};
+	uint32_t slave_interrupt_cfg[5] = 
+	{	
+		0x00 /* The Event Detected Channel interrupt is disabled, The Overrun Channel interrupt is disabled. */
+	};	
+	
+	/* USER_ID, Channel n-1 */										
+	//hri_evsys_write_USER_reg(EVSYS, 0x01, 0x02); /*PORT_EV0 - CH1*/
+	//hri_evsys_write_USER_reg(EVSYS, 0x02, 0x07); /*PORT_EV1 - CH6*/
+	//hri_evsys_write_USER_reg(EVSYS, 0x03, 0x06); /*PORT_EV2 - CH5*/
+	//hri_evsys_write_USER_reg(EVSYS, 0x04, 0x09); /*PORT_EV3 - CH8*/
+	hri_evsys_write_USER_reg(EVSYS, 0x09, 0x01); /*DMAC_CH4 - CH0 */
+	//hri_evsys_write_USER_reg(EVSYS, 0x10, 0x06); /*DMAC_CH5 - CH1*/
+	//hri_evsys_write_USER_reg(EVSYS, 0x12, 0x03); /*DMAC_CH7 - CH2*/
+	hri_evsys_write_USER_reg(EVSYS, 0x46, 0x0c); /*TC2 - CH11*/
+	hri_evsys_write_USER_reg(EVSYS, 0x48, 0x0d); /*TC4 - CH12 */
+	
+	uint8_t i;
+	for (i = 0; i < 5; i++) { 
+		hri_evsys_write_CHANNEL_reg(EVSYS, i, slave_channel_confs[i]);
+		hri_evsys_write_CHINTEN_reg(EVSYS, i, slave_interrupt_cfg[i]);
+	}	 
+}
+
+#endif /* CONFIGURATION_H_ */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/control.h

@@ -0,0 +1,262 @@
+/*
+ * pi.h
+ *
+ * Created: 01/02/2021 21:36:11
+ *  Author: Nick-XMG
+ */ 
+#ifndef CONTROL_H_
+#define CONTROL_H_
+
+// ----------------------------------------------------------------------
+// 	history
+// ----------------------------------------------------------------------
+// 	01.02.2021 - initial Revision
+
+// ----------------------------------------------------------------------
+// 	header files
+// ----------------------------------------------------------------------
+#include "arm_math.h"
+#include "atmel_start.h"
+#include "utilities.h"
+// ----------------------------------------------------------------------
+// 	#defines
+// ----------------------------------------------------------------------
+// ----------------------------------------------------------------------
+// 	global variables
+// ----------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+	#endif
+	
+/* PI Structure */
+typedef volatile struct
+{
+	volatile float32_t Kp;          // the proportional gain for the PI controller
+	volatile float32_t Ki;          // the integral gain for the PI controller
+
+	volatile float32_t Ref_pu;      // the reference value [pu]
+	volatile float32_t Fbk_pu;      // the feedback value [pu]
+	volatile float32_t Ff_pu;       // the feedForward value [pu]
+
+	volatile float32_t OutMin_pu;   // the saturation low limit for the controller output [pu]
+	volatile float32_t OutMax_pu;   // the saturation high limit for the controller output [pu]
+	volatile float32_t Out_pu;      // the controller output [pu]
+
+	volatile float32_t Ui;          // the integrator value for the PI controller
+	volatile float32_t error;          // the integrator value for the PI controller
+	volatile bool SatFlag;   // flag to signal controller saturation
+} PI_t;
+
+/* PID Structure */
+typedef volatile struct
+{
+	volatile float32_t  Kp;                //!< the proportional gain for the PID controller
+	volatile float32_t  Ki;                //!< the integral gain for the PID controller
+	volatile float32_t  Kd;                //!< the derivative gain for the PID controller
+
+	volatile float32_t  Ref_pu;          //!< the reference input value
+	volatile float32_t  Fbk_pu;        //!< the feedback input value
+	volatile float32_t  Ff_pu;         //!< the feedforward input value
+	
+	volatile float32_t  OutMin_pu;            //!< the minimum output value allowed for the PID controller
+	volatile float32_t  OutMax_pu;            //!< the maximum output value allowed for the PID controller
+	volatile float32_t	Out_pu;      // the controller output [pu]
+	
+	volatile float32_t  Ui;                //!< the integrator start value for the PID controller
+	volatile float32_t  Ud;
+	volatile float32_t error;          // the integrator value for the PI controller
+	
+	//FILTER_FO_Handle derFilterHandle;   //!< the derivative filter handle
+	//FILTER_FO_Obj    derFilter;         //!< the derivative filter object
+} PID_t;
+
+volatile typedef struct
+{
+	volatile PI_t	Pi_Idc;
+	volatile PID_t	Pid_Speed;
+	volatile PI_t	Pi_Pos;
+}	MOTOR_Control_Structs;
+
+// ----------------------------------------------------------------------
+// 	functions
+// ----------------------------------------------------------------------
+// function to set default values for the object
+
+//inline float32_t clamp(const float32_t d, const float32_t min, const float32_t max) {
+	//const float32_t t = d < min ? min : d;
+	//return t > max ? max : t;
+//}
+
+
+static inline void PI_objectInit(volatile PI_t *pPi_obj)
+{
+	PI_t *obj = (PI_t *)pPi_obj;
+
+	// Function initializes the object with default values
+	//fix16_t Kp = fix16_from_float32_t(1.0);
+	obj->Kp			= 0.0f;
+	obj->Ki			= 0.0f;
+	obj->Fbk_pu		= 0.0f;
+	obj->Ref_pu		= 0.0f;
+	obj->Ff_pu		= 0.0f;
+	obj->Out_pu		= 0.0f;
+	obj->OutMax_pu	= 0.0f;
+	obj->OutMin_pu	= 0.0f;
+	obj->Ui			= 0.0f;
+	obj->SatFlag	= false;
+}
+
+static inline void PID_objectInit(volatile PID_t *pPiD_obj)
+{
+	PID_t *obj = (PID_t *)pPiD_obj;
+
+	// Function initializes the object with default values
+	//fix16_t Kp = fix16_from_float32_t(1.0);
+	obj->Kp			= 0.0f;
+	obj->Ki			= 0.0f;
+	obj->Kd			= 0.0f;
+	obj->Fbk_pu		= 0.0f;
+	obj->Ref_pu		= 0.0f;
+	obj->Ff_pu		= 0.0f;
+	obj->Out_pu		= 0.0f;
+	obj->OutMax_pu	= 0.0f;
+	obj->OutMin_pu	= 0.0f;
+	obj->Ui			= 0.0f;
+	obj->Ud			= 0.0f;
+}
+
+// ----------------------------------------------------------------------
+//	PI Calculation
+// ----------------------------------------------------------------------
+static inline void PI_run_series(volatile PI_t *pPi_obj)
+{
+	PI_t *obj = (PI_t *)pPi_obj;
+	volatile float32_t Up;
+
+	// Compute the controller error
+	obj->error = obj->Ref_pu - obj->Fbk_pu;
+
+	// Compute the proportional term
+	Up = obj->Kp *obj->error;
+
+	// Compute the integral term in series form and saturate	
+	obj->Ui = f_clamp((obj->Ui + (obj->Ki * Up)), obj->OutMin_pu, obj->OutMax_pu);
+
+	// Saturate the output
+ 	obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);
+}
+
+static inline void PI_run_parallel(volatile PI_t *pPi_obj)
+{
+	PI_t *obj = (PI_t *)pPi_obj;
+	volatile float32_t Up;
+	
+	// Compute the controller error
+	obj->error = obj->Ref_pu - obj->Fbk_pu;
+	
+	// Compute the proportional term
+	Up = obj->Kp * obj->error;
+	
+	// Compute the integral term in parallel form and saturate
+	obj->Ui = f_clamp((obj->Ui + (obj->Ki * obj->error)), obj->OutMin_pu, obj->OutMax_pu);
+	
+	obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);  // Saturate the output
+} // end of PI_run_parallel() function
+
+
+// ----------------------------------------------------------------------
+//	PID Calculation
+// ----------------------------------------------------------------------
+static inline void PID_run_series(volatile PID_t *pPid_obj)
+{
+	PID_t *obj = (PID_t *)pPid_obj;
+	volatile float32_t Up, Ud_tmp;
+	
+	// Compute the controller error
+	obj->error = obj->Ref_pu - obj->Fbk_pu;
+	
+	// Compute the proportional term
+	Up = obj->Kp * obj->error;
+	
+	if(obj->Ki>0.0f){
+		// Compute the integral term in parallel form and saturate
+		obj->Ui = f_clamp((obj->Ui + (obj->Ki * Up)), obj->OutMin_pu, obj->OutMax_pu);
+	}
+	
+	Ud_tmp = obj->Kd * obj->Ui; // Compute the derivative term
+	
+	obj->Ud = Ud_tmp; // Replace with filter
+
+	obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ud + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);  // Saturate the output
+	
+}
+
+static inline void PID_run_parallel(volatile PID_t *pPid_obj)
+{
+	PID_t *obj = (PID_t *)pPid_obj;
+	volatile float32_t Up, Ud_tmp;
+
+	
+	// Compute the controller error
+	obj->error = obj->Ref_pu - obj->Fbk_pu;
+	
+	// Compute the proportional term
+	Up = obj->Kp * obj->error;
+	
+	if(obj->Ki>0.0f){
+		// Compute the integral term in parallel form and saturate
+		obj->Ui = f_clamp((obj->Ui + (obj->Ki * obj->error)), obj->OutMin_pu, obj->OutMax_pu);
+	}
+	
+	Ud_tmp = obj->Kd * obj->error;   // Compute the derivative term
+
+	obj->Ud = Ud_tmp; // Replace with filter
+
+	obj->Out_pu = f_clamp((Up + obj->Ui + obj->Ud + obj->Ff_pu), obj->OutMin_pu, obj->OutMax_pu);  // Saturate the output
+}
+
+
+// ----------------------------------------------------------------------
+// Calculate Current Parameters
+// ----------------------------------------------------------------------
+
+static inline float32_t PI_calcKp(const float32_t Ls_H, const float32_t deviceCurrent_A, const float32_t deviceVoltage_V,
+const float32_t deviceCtrlPeriode_Sec)
+{
+	// calculation is based on "Betragsoptimum"
+	// Kp = Ls/(2*tau)
+	float32_t x1;
+	float32_t y1;
+	float32_t Kp;
+
+	// multiplication with deviceCurrent_A is to get per unit values
+	x1 = (float32_t)(Ls_H * deviceCurrent_A);
+
+	y1 = (float32_t)(2.0f * deviceCtrlPeriode_Sec);
+
+	// multiplication with deviceVoltage_V is to get per unit values
+	y1 = (float32_t)(y1 * deviceVoltage_V);
+
+	Kp = (x1 / y1);
+	return Kp;
+}
+
+static inline float32_t PI_calcKi(const float32_t Rs_Ohm, const float32_t Ls_H, const float32_t deviceCtrlPeriode_Sec)
+{
+	// calculation is based on "TI - MotorWare's documentation"
+	float32_t RsByLs = (float32_t)(Rs_Ohm / Ls_H);
+	float32_t Ki = RsByLs * deviceCtrlPeriode_Sec;
+	//fix16_t Ki = 0;
+	return Ki;
+}
+
+// ----------------------------------------------------------------------
+// 	end of file
+// ----------------------------------------------------------------------
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+#endif /* BLDC_PI_H_ */
+

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/driver_init.c

@@ -0,0 +1,856 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+
+#include "driver_init.h"
+#include <peripheral_clk_config.h>
+#include <utils.h>
+#include <hal_init.h>
+
+#include <hpl_adc_base.h>
+#include <hpl_adc_base.h>
+
+struct spi_m_sync_descriptor SPI_2;
+struct spi_m_sync_descriptor SPI_3;
+
+struct adc_sync_descriptor ADC_0;
+
+struct adc_sync_descriptor ADC_1;
+
+struct qspi_dma_descriptor ECAT_QSPI;
+
+struct i2c_m_async_desc I2C_0;
+
+struct spi_m_dma_descriptor SPI_1_MSIF_M;
+
+struct spi_s_sync_descriptor SPI_1_MSIF_S;
+
+struct pwm_descriptor PWM_0;
+
+struct pwm_descriptor PWM_1;
+
+void ADC_0_PORT_init(void)
+{
+}
+
+void ADC_0_CLOCK_init(void)
+{
+	hri_mclk_set_APBDMASK_ADC0_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void ADC_0_init(void)
+{
+	ADC_0_CLOCK_init();
+	ADC_0_PORT_init();
+	adc_sync_init(&ADC_0, ADC0, (void *)NULL);
+}
+
+void ADC_1_PORT_init(void)
+{
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(half_VREF, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(half_VREF, PINMUX_PB08B_ADC1_AIN0);
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(M1_IA, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(M1_IA, PINMUX_PB04B_ADC1_AIN6);
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(M1_IB, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(M1_IB, PINMUX_PB05B_ADC1_AIN7);
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(M2_IA, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(M2_IA, PINMUX_PB06B_ADC1_AIN8);
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(M2_IB, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(M2_IB, PINMUX_PB07B_ADC1_AIN9);
+}
+
+void ADC_1_CLOCK_init(void)
+{
+	hri_mclk_set_APBDMASK_ADC1_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, ADC1_GCLK_ID, CONF_GCLK_ADC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void ADC_1_init(void)
+{
+	ADC_1_CLOCK_init();
+	ADC_1_PORT_init();
+	adc_sync_init(&ADC_1, ADC1, (void *)NULL);
+}
+
+void DIGITAL_GLUE_LOGIC_0_PORT_init(void)
+{
+
+	gpio_set_pin_function(M1_HALLA, PINMUX_PA04N_CCL_IN0);
+
+	gpio_set_pin_function(M1_HALLB, PINMUX_PA05N_CCL_IN1);
+
+	gpio_set_pin_function(M1_HALLC, PINMUX_PA06N_CCL_IN2);
+
+	gpio_set_pin_function(M2_HALLA, PINMUX_PA22N_CCL_IN6);
+
+	gpio_set_pin_function(M2_HALLB, PINMUX_PA23N_CCL_IN7);
+
+	gpio_set_pin_function(M2_HALLC, PINMUX_PA24N_CCL_IN8);
+}
+
+void DIGITAL_GLUE_LOGIC_0_CLOCK_init(void)
+{
+	hri_mclk_set_APBCMASK_CCL_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, CCL_GCLK_ID, CONF_GCLK_CCL_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void DIGITAL_GLUE_LOGIC_0_init(void)
+{
+	DIGITAL_GLUE_LOGIC_0_CLOCK_init();
+	custom_logic_init();
+	DIGITAL_GLUE_LOGIC_0_PORT_init();
+}
+
+void EXTERNAL_IRQ_0_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_mclk_set_APBAMASK_EIC_bit(MCLK);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(ADS_DATA_RDY, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(ADS_DATA_RDY,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ADS_DATA_RDY, PINMUX_PA02A_EIC_EXTINT2);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(ECAT_SYNC, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(ECAT_SYNC,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_SYNC, PINMUX_PA07A_EIC_EXTINT7);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(M1_RST_Bar, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(M1_RST_Bar,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(M1_RST_Bar, PINMUX_PB30A_EIC_EXTINT14);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(M2_RST_Bar, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(M2_RST_Bar,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(M2_RST_Bar, PINMUX_PB31A_EIC_EXTINT15);
+
+	ext_irq_init();
+}
+
+void EVENT_SYSTEM_0_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_0, CONF_GCLK_EVSYS_CHANNEL_0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_1, CONF_GCLK_EVSYS_CHANNEL_1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_2, CONF_GCLK_EVSYS_CHANNEL_2_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_3, CONF_GCLK_EVSYS_CHANNEL_3_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_5, CONF_GCLK_EVSYS_CHANNEL_5_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_6, CONF_GCLK_EVSYS_CHANNEL_6_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_7, CONF_GCLK_EVSYS_CHANNEL_7_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_8, CONF_GCLK_EVSYS_CHANNEL_8_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, EVSYS_GCLK_ID_11, CONF_GCLK_EVSYS_CHANNEL_11_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBBMASK_EVSYS_bit(MCLK);
+
+	event_system_init();
+}
+
+void ECAT_QSPI_PORT_init(void)
+{
+
+	// Set pin direction to input
+	gpio_set_pin_direction(ECAT_QSPI_CS, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(ECAT_QSPI_CS,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_QSPI_CS, PINMUX_PB11H_QSPI_CS);
+
+	gpio_set_pin_direction(ECAT_QSPI_MOSI,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(ECAT_QSPI_MOSI,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(ECAT_QSPI_MOSI,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_QSPI_MOSI,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PA08H_QSPI_DATA0"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA08H_QSPI_DATA0);
+
+	gpio_set_pin_direction(ECAT_QSPI_MISO,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(ECAT_QSPI_MISO,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(ECAT_QSPI_MISO,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_QSPI_MISO,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PA09H_QSPI_DATA1"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA09H_QSPI_DATA1);
+
+	gpio_set_pin_direction(ECAT_QSPI_DATA2,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(ECAT_QSPI_DATA2,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(ECAT_QSPI_DATA2,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_QSPI_DATA2,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PA10H_QSPI_DATA2"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA10H_QSPI_DATA2);
+
+	gpio_set_pin_direction(ECAT_QSPI_DATA3,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(ECAT_QSPI_DATA3,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(ECAT_QSPI_DATA3,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_QSPI_DATA3,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PA11H_QSPI_DATA3"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA11H_QSPI_DATA3);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(ECAT_QSPI_SCK, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(ECAT_QSPI_SCK,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(ECAT_QSPI_SCK, PINMUX_PB10H_QSPI_SCK);
+}
+
+void ECAT_QSPI_CLOCK_init(void)
+{
+	hri_mclk_set_AHBMASK_QSPI_bit(MCLK);
+	hri_mclk_set_AHBMASK_QSPI_2X_bit(MCLK);
+	hri_mclk_set_APBCMASK_QSPI_bit(MCLK);
+}
+
+void ECAT_QSPI_init(void)
+{
+	ECAT_QSPI_CLOCK_init();
+	qspi_dma_init(&ECAT_QSPI, QSPI);
+	ECAT_QSPI_PORT_init();
+}
+
+void I2C_0_PORT_init(void)
+{
+}
+
+void I2C_0_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK);
+}
+
+void I2C_0_init(void)
+{
+	I2C_0_CLOCK_init();
+	i2c_m_async_init(&I2C_0, SERCOM0);
+	I2C_0_PORT_init();
+}
+
+void SPI_1_MSIF_M_PORT_init(void)
+{
+
+	gpio_set_pin_level(SPI1_MOSI,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI1_MOSI, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI1_MOSI, PINMUX_PA00D_SERCOM1_PAD0);
+
+	gpio_set_pin_level(SPI1_SCK,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI1_SCK, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI1_SCK, PINMUX_PA01D_SERCOM1_PAD1);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(SPI1_MISO, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(SPI1_MISO,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(SPI1_MISO, PINMUX_PB23C_SERCOM1_PAD3);
+}
+
+void SPI_1_MSIF_M_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBAMASK_SERCOM1_bit(MCLK);
+}
+
+void SPI_1_MSIF_M_init(void)
+{
+	SPI_1_MSIF_M_CLOCK_init();
+	spi_m_dma_init(&SPI_1_MSIF_M, SERCOM1);
+	SPI_1_MSIF_M_PORT_init();
+}
+
+void SPI_2_PORT_init(void)
+{
+
+	gpio_set_pin_level(SPI2_MOSI,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI2_MOSI, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI2_MOSI, PINMUX_PA12C_SERCOM2_PAD0);
+
+	gpio_set_pin_level(SPI2_SCK,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI2_SCK, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI2_SCK, PINMUX_PA13C_SERCOM2_PAD1);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(SPI2_MISO, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(SPI2_MISO,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(SPI2_MISO, PINMUX_PA15C_SERCOM2_PAD3);
+}
+
+void SPI_2_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
+}
+
+void SPI_2_init(void)
+{
+	SPI_2_CLOCK_init();
+	spi_m_sync_init(&SPI_2, SERCOM2);
+	SPI_2_PORT_init();
+}
+
+void SPI_1_MSIF_S_PORT_init(void)
+{
+}
+
+void SPI_1_MSIF_S_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK);
+}
+
+void SPI_1_MSIF_S_init(void)
+{
+	//SPI_1_MSIF_S_CLOCK_init();
+	//spi_s_sync_init(&SPI_1_MSIF_S, SERCOM3);
+	//SPI_1_MSIF_S_PORT_init();
+}
+
+void SPI_3_PORT_init(void)
+{
+
+	gpio_set_pin_level(SPI3_MOSI,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI3_MOSI, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI3_MOSI, PINMUX_PB02D_SERCOM5_PAD0);
+
+	gpio_set_pin_level(SPI3_SCK,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI3_SCK, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI3_SCK, PINMUX_PB03D_SERCOM5_PAD1);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(SPI3_MISO, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(SPI3_MISO,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(SPI3_MISO, PINMUX_PB01D_SERCOM5_PAD3);
+}
+
+void SPI_3_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_CORE, CONF_GCLK_SERCOM5_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_SLOW, CONF_GCLK_SERCOM5_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBDMASK_SERCOM5_bit(MCLK);
+}
+
+void SPI_3_init(void)
+{
+	SPI_3_CLOCK_init();
+	spi_m_sync_init(&SPI_3, SERCOM5);
+	SPI_3_PORT_init();
+}
+
+void TIMER_0_CLOCK_init(void)
+{
+	hri_mclk_set_APBAMASK_TC0_bit(MCLK);
+
+	hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void TIMER_SPARE_CLOCK_init(void)
+{
+	hri_mclk_set_APBAMASK_TC1_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TC1_GCLK_ID, CONF_GCLK_TC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void TC_SPEED_M1_CLOCK_init(void)
+{
+	hri_mclk_set_APBBMASK_TC2_bit(MCLK);
+
+	hri_mclk_set_APBBMASK_TC3_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TC2_GCLK_ID, CONF_GCLK_TC2_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void TC_SPEED_M2_CLOCK_init(void)
+{
+	hri_mclk_set_APBCMASK_TC4_bit(MCLK);
+
+	hri_mclk_set_APBCMASK_TC5_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TC4_GCLK_ID, CONF_GCLK_TC4_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void PWM_0_PORT_init(void)
+{
+
+	gpio_set_pin_function(M1_PWMA, PINMUX_PB12G_TCC0_WO0);
+
+	gpio_set_pin_function(M1_PWMB, PINMUX_PB13G_TCC0_WO1);
+
+	gpio_set_pin_function(M1_PWMC, PINMUX_PB14G_TCC0_WO2);
+
+	gpio_set_pin_function(M1_ENA, PINMUX_PB15G_TCC0_WO3);
+
+	gpio_set_pin_function(M1_ENB, PINMUX_PB16G_TCC0_WO4);
+
+	gpio_set_pin_function(M1_ENC, PINMUX_PB17G_TCC0_WO5);
+}
+
+void PWM_0_CLOCK_init(void)
+{
+
+	hri_mclk_set_APBBMASK_TCC0_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, CONF_GCLK_TCC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void PWM_0_init(void)
+{
+	PWM_0_CLOCK_init();
+	PWM_0_PORT_init();
+	pwm_init(&PWM_0, TCC0, _tcc_get_pwm());
+}
+
+void PWM_1_PORT_init(void)
+{
+
+	gpio_set_pin_function(M2_PWMA, PINMUX_PA16F_TCC1_WO0);
+
+	gpio_set_pin_function(M2_PWMB, PINMUX_PA17F_TCC1_WO1);
+
+	gpio_set_pin_function(M2_PWMC, PINMUX_PA18F_TCC1_WO2);
+
+	gpio_set_pin_function(M2_ENA, PINMUX_PA19F_TCC1_WO3);
+
+	gpio_set_pin_function(M2_ENB, PINMUX_PA20F_TCC1_WO4);
+
+	gpio_set_pin_function(M2_ENC, PINMUX_PA21F_TCC1_WO5);
+}
+
+void PWM_1_CLOCK_init(void)
+{
+
+	hri_mclk_set_APBBMASK_TCC1_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TCC1_GCLK_ID, CONF_GCLK_TCC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void PWM_1_init(void)
+{
+	PWM_1_CLOCK_init();
+	PWM_1_PORT_init();
+	pwm_init(&PWM_1, TCC1, _tcc_get_pwm());
+}
+
+void system_init(void)
+{
+	init_mcu();
+
+	// GPIO on PA03
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(ANAREF_3V, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(ANAREF_3V, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PA14
+
+	gpio_set_pin_level(SPI2_SS,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   true);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI2_SS, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI2_SS, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PA25
+
+	gpio_set_pin_level(M1_RST,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(M1_RST, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(M1_RST, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PA27
+
+	gpio_set_pin_level(M2_RST,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(M2_RST, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(M2_RST, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PB00
+
+	gpio_set_pin_level(SPI3_SS,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   true);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI3_SS, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI3_SS, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PB09
+
+	gpio_set_pin_level(ADS_RESET,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   true);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(ADS_RESET, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(ADS_RESET, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PB22
+
+	gpio_set_pin_level(SPI1_CS,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   true);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(SPI1_CS, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(SPI1_CS, GPIO_PIN_FUNCTION_OFF);
+
+	ADC_0_init();
+
+	ADC_1_init();
+
+	DIGITAL_GLUE_LOGIC_0_init();
+
+	EXTERNAL_IRQ_0_init();
+
+	EVENT_SYSTEM_0_init();
+
+	ECAT_QSPI_init();
+
+	I2C_0_init();
+
+	SPI_1_MSIF_M_init();
+
+	SPI_2_init();
+
+	SPI_1_MSIF_S_init();
+
+	SPI_3_init();
+
+	TIMER_0_CLOCK_init();
+
+	TIMER_0_init();
+
+	TIMER_SPARE_CLOCK_init();
+
+	TIMER_SPARE_init();
+
+	TC_SPEED_M1_CLOCK_init();
+
+	TC_SPEED_M1_init();
+
+	TC_SPEED_M2_CLOCK_init();
+
+	TC_SPEED_M2_init();
+
+	PWM_0_init();
+
+	PWM_1_init();
+}

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/driver_init.h

@@ -0,0 +1,142 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef DRIVER_INIT_INCLUDED
+#define DRIVER_INIT_INCLUDED
+
+#include "atmel_start_pins.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <hal_atomic.h>
+#include <hal_delay.h>
+#include <hal_gpio.h>
+#include <hal_init.h>
+#include <hal_io.h>
+#include <hal_sleep.h>
+
+#include <hal_adc_sync.h>
+
+#include <hal_adc_sync.h>
+
+#include <hal_custom_logic.h>
+
+#include <hal_ext_irq.h>
+
+#include <hal_evsys.h>
+
+#include <hal_qspi_dma.h>
+
+#include <hal_i2c_m_async.h>
+
+#include <hal_spi_m_dma.h>
+#include <hal_spi_m_sync.h>
+
+#include <hal_spi_s_sync.h>
+#include <hal_spi_m_sync.h>
+#include <tc_lite.h>
+#include <tc_lite.h>
+#include <tc_lite.h>
+#include <tc_lite.h>
+
+#include <hal_pwm.h>
+#include <hpl_tcc.h>
+
+#include <hal_pwm.h>
+#include <hpl_tcc.h>
+
+extern struct adc_sync_descriptor ADC_0;
+
+extern struct adc_sync_descriptor ADC_1;
+
+extern struct qspi_dma_descriptor ECAT_QSPI;
+
+extern struct i2c_m_async_desc I2C_0;
+
+extern struct spi_m_dma_descriptor  SPI_1_MSIF_M;
+extern struct spi_m_sync_descriptor SPI_2;
+
+extern struct spi_s_sync_descriptor SPI_1_MSIF_S;
+extern struct spi_m_sync_descriptor SPI_3;
+
+extern struct pwm_descriptor PWM_0;
+
+extern struct pwm_descriptor PWM_1;
+
+void ADC_0_PORT_init(void);
+void ADC_0_CLOCK_init(void);
+void ADC_0_init(void);
+
+void ADC_1_PORT_init(void);
+void ADC_1_CLOCK_init(void);
+void ADC_1_init(void);
+
+void DIGITAL_GLUE_LOGIC_0_PORT_init(void);
+void DIGITAL_GLUE_LOGIC_0_CLOCK_init(void);
+void DIGITAL_GLUE_LOGIC_0_init(void);
+
+void ECAT_QSPI_PORT_init(void);
+void ECAT_QSPI_CLOCK_init(void);
+void ECAT_QSPI_init(void);
+
+void I2C_0_PORT_init(void);
+void I2C_0_CLOCK_init(void);
+void I2C_0_init(void);
+
+void SPI_1_MSIF_M_PORT_init(void);
+void SPI_1_MSIF_M_CLOCK_init(void);
+void SPI_1_MSIF_M_init(void);
+
+void SPI_2_PORT_init(void);
+void SPI_2_CLOCK_init(void);
+void SPI_2_init(void);
+
+void SPI_1_MSIF_S_PORT_init(void);
+void SPI_1_MSIF_S_CLOCK_init(void);
+void SPI_1_MSIF_S_init(void);
+void SPI_1_MSIF_S_example(void);
+
+void SPI_3_PORT_init(void);
+void SPI_3_CLOCK_init(void);
+void SPI_3_init(void);
+
+void TIMER_0_CLOCK_init(void);
+
+int8_t TIMER_0_init(void);
+
+void TIMER_SPARE_CLOCK_init(void);
+
+int8_t TIMER_SPARE_init(void);
+
+void TC_SPEED_M1_CLOCK_init(void);
+
+int8_t TC_SPEED_M1_init(void);
+
+void TC_SPEED_M2_CLOCK_init(void);
+
+int8_t TC_SPEED_M2_init(void);
+
+void PWM_0_PORT_init(void);
+void PWM_0_CLOCK_init(void);
+void PWM_0_init(void);
+
+void PWM_1_PORT_init(void);
+void PWM_1_CLOCK_init(void);
+void PWM_1_init(void);
+
+/**
+ * \brief Perform system initialization, initialize pins and clocks for
+ * peripherals
+ */
+void system_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif // DRIVER_INIT_INCLUDED

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/examples/driver_examples.c

@@ -0,0 +1,210 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+
+#include "driver_examples.h"
+#include "driver_init.h"
+#include "utils.h"
+
+/**
+ * Example of using ADC_0 to generate waveform.
+ */
+void ADC_0_example(void)
+{
+	uint8_t buffer[2];
+
+	adc_sync_enable_channel(&ADC_0, 0);
+
+	while (1) {
+		adc_sync_read_channel(&ADC_0, 0, buffer, 2);
+	}
+}
+
+/**
+ * Example of using ADC_1 to generate waveform.
+ */
+void ADC_1_example(void)
+{
+	uint8_t buffer[2];
+
+	adc_sync_enable_channel(&ADC_1, 0);
+
+	while (1) {
+		adc_sync_read_channel(&ADC_1, 0, buffer, 2);
+	}
+}
+
+/**
+ * Example of using DIGITAL_GLUE_LOGIC_0.
+ */
+void DIGITAL_GLUE_LOGIC_0_example(void)
+{
+	custom_logic_enable();
+	/* Customer logic now works. */
+}
+
+static void button_on_PA02_pressed(void)
+{
+}
+
+static void button_on_PA07_pressed(void)
+{
+}
+
+static void button_on_PB30_pressed(void)
+{
+}
+
+static void button_on_PB31_pressed(void)
+{
+}
+
+/**
+ * Example of using EXTERNAL_IRQ_0
+ */
+void EXTERNAL_IRQ_0_example(void)
+{
+
+	ext_irq_register(PIN_PA02, button_on_PA02_pressed);
+	ext_irq_register(PIN_PA07, button_on_PA07_pressed);
+	ext_irq_register(PIN_PB30, button_on_PB30_pressed);
+	ext_irq_register(PIN_PB31, button_on_PB31_pressed);
+}
+
+static uint8_t buf[16] = {0x0};
+
+static void xfer_complete_cb_ECAT_QSPI(struct _dma_resource *resource)
+{
+	/* Transfer completed */
+}
+
+/**
+ * Example of using ECAT_QSPI to get N25Q256A status value,
+ * and check bit 0 which indicate embedded operation is busy or not.
+ */
+void ECAT_QSPI_example(void)
+{
+	struct _qspi_command cmd = {
+	    .inst_frame.bits.inst_en      = 1,
+	    .inst_frame.bits.data_en      = 1,
+	    .inst_frame.bits.addr_en      = 1,
+	    .inst_frame.bits.dummy_cycles = 8,
+	    .inst_frame.bits.tfr_type     = QSPI_READMEM_ACCESS,
+	    .instruction                  = 0x0B,
+	    .address                      = 0,
+	    .buf_len                      = 14,
+	    .rx_buf                       = buf,
+	};
+
+	qspi_dma_register_callback(&ECAT_QSPI, QSPI_DMA_CB_XFER_DONE, xfer_complete_cb_ECAT_QSPI);
+	qspi_dma_enable(&ECAT_QSPI);
+	qspi_dma_serial_run_command(&ECAT_QSPI, &cmd);
+}
+
+static uint8_t I2C_0_example_str[12] = "Hello World!";
+
+void I2C_0_tx_complete(struct i2c_m_async_desc *const i2c)
+{
+}
+
+void I2C_0_example(void)
+{
+	struct io_descriptor *I2C_0_io;
+
+	i2c_m_async_get_io_descriptor(&I2C_0, &I2C_0_io);
+	i2c_m_async_enable(&I2C_0);
+	i2c_m_async_register_callback(&I2C_0, I2C_M_ASYNC_TX_COMPLETE, (FUNC_PTR)I2C_0_tx_complete);
+	i2c_m_async_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
+
+	io_write(I2C_0_io, I2C_0_example_str, 12);
+}
+
+/**
+ * Example of using SPI_1_MSIF_M to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
+ */
+
+static uint8_t example_SPI_1_MSIF_M[12] = "Hello World!";
+
+static void tx_complete_cb_SPI_1_MSIF_M(struct _dma_resource *resource)
+{
+	/* Transfer completed */
+}
+
+void SPI_1_MSIF_M_example(void)
+{
+	struct io_descriptor *io;
+	spi_m_dma_get_io_descriptor(&SPI_1_MSIF_M, &io);
+
+	spi_m_dma_register_callback(&SPI_1_MSIF_M, SPI_M_DMA_CB_TX_DONE, tx_complete_cb_SPI_1_MSIF_M);
+	spi_m_dma_enable(&SPI_1_MSIF_M);
+	io_write(io, example_SPI_1_MSIF_M, 12);
+}
+
+/**
+ * Example of using SPI_2 to write "Hello World" using the IO abstraction.
+ */
+static uint8_t example_SPI_2[12] = "Hello World!";
+
+void SPI_2_example(void)
+{
+	struct io_descriptor *io;
+	spi_m_sync_get_io_descriptor(&SPI_2, &io);
+
+	spi_m_sync_enable(&SPI_2);
+	io_write(io, example_SPI_2, 12);
+}
+
+/**
+ * Example of using SPI_1_MSIF_S to write "Hello World" using the IO abstraction.
+ */
+static uint8_t example_SPI_1_MSIF_S[12] = "Hello World!";
+
+void SPI_1_MSIF_S_example(void)
+{
+	struct io_descriptor *io;
+	spi_s_sync_get_io_descriptor(&SPI_1_MSIF_S, &io);
+
+	spi_s_sync_enable(&SPI_1_MSIF_S);
+	io_write(io, example_SPI_1_MSIF_S, 12);
+}
+
+/**
+ * Example of using SPI_3 to write "Hello World" using the IO abstraction.
+ */
+static uint8_t example_SPI_3[12] = "Hello World!";
+
+void SPI_3_example(void)
+{
+	struct io_descriptor *io;
+	spi_m_sync_get_io_descriptor(&SPI_3, &io);
+
+	spi_m_sync_enable(&SPI_3);
+	io_write(io, example_SPI_3, 12);
+}
+
+/**
+ * Example of using PWM_0.
+ */
+void PWM_0_example(void)
+{
+	pwm_set_parameters(&PWM_0, 10000, 5000);
+	pwm_enable(&PWM_0);
+}
+
+/**
+ * Example of using PWM_1.
+ */
+void PWM_1_example(void)
+{
+	pwm_set_parameters(&PWM_1, 10000, 5000);
+	pwm_enable(&PWM_1);
+}

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/examples/driver_examples.h

@@ -0,0 +1,36 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef DRIVER_EXAMPLES_H_INCLUDED
+#define DRIVER_EXAMPLES_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void ADC_0_example(void);
+
+void ADC_1_example(void);
+
+void DIGITAL_GLUE_LOGIC_0_example(void);
+
+void EXTERNAL_IRQ_0_example(void);
+
+void ECAT_QSPI_example(void);
+
+void I2C_0_example(void);
+
+void SPI_1_MSIF_M_example(void);
+
+void PWM_0_example(void);
+
+void PWM_1_example(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif // DRIVER_EXAMPLES_H_INCLUDED

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/adc_sync.rst

@@ -0,0 +1,74 @@
+======================
+ADC Synchronous driver
+======================
+
+An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
+A reference signal with a known voltage level is quantified into equally
+sized chunks, each representing a digital value from 0 to the highest number
+possible with the bit resolution supported by the ADC. The input voltage
+measured by the ADC is compared against these chunks and the chunk with the
+closest voltage level defines the digital value that can be used to represent
+the analog input voltage level.
+
+Usually an ADC can operate in either differential or single-ended mode.
+In differential mode two signals (V+ and V-) are compared against each other
+and the resulting digital value represents the relative voltage level between
+V+ and V-. This means that if the input voltage level on V+ is lower than on
+V- the digital value is negative, which also means that in differential
+mode one bit is lost to the sign. In single-ended mode only V+ is compared
+against the reference voltage, and the resulting digital value can only be
+positive, but the full bit-range of the ADC can be used.
+
+Usually multiple resolutions are supported by the ADC, lower resolution can
+reduce the conversion time, but lose accuracy.
+
+Some ADCs has a gain stage on the input lines which can be used to increase the
+dynamic range. The default gain value is usually x1, which means that the
+conversion range is from 0V to the reference voltage.
+Applications can change the gain stage, to increase or reduce the conversion
+range.
+
+The window mode allows the conversion result to be compared to a set of
+predefined threshold values. Applications can use callback function to monitor
+if the conversion result exceeds predefined threshold value.
+
+Usually multiple reference voltages are supported by the ADC, both internal and
+external with difference voltage levels. The reference voltage have an impact
+on the accuracy, and should be selected to cover the full range of the analog
+input signal and never less than the expected maximum input voltage.
+
+There are two conversion modes supported by ADC, single shot and free running.
+In single shot mode the ADC only make one conversion when triggered by the
+application, in free running mode it continues to make conversion from it
+is triggered until it is stopped by the application. When window monitoring,
+the ADC should be set to free running mode.
+
+Features
+--------
+* Initialization and de-initialization
+* Support multiple Conversion Mode, Single or Free run
+* Start ADC Conversion
+* Read Conversion Result
+
+Applications
+------------
+* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
+* Measurement of external sensor. E.g., Temperature, humidity sensor value.
+* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
+
+Dependencies
+------------
+* ADC hardware
+
+Concurrency
+-----------
+N/A
+
+Limitations
+-----------
+N/A
+
+Knows issues and workarounds
+----------------------------
+N/A
+

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/custom_logic.rst

@@ -0,0 +1,32 @@
+===========================================================
+Digital Glue Logic based on Configurable Custom Logic (CCL)
+===========================================================
+
+Custom logic driver offers a way to initialize on-chip programmable logic
+units, so that a specific logic box is built. Then this "box" can be connected
+to internal or external circuit to perform the logic operations.
+
+Features
+--------
+* Initialization and de-initialization
+* Enabling and disabling
+
+Applications
+------------
+* Connected to external circuit, as a logic operation box, e.g., as adder.
+
+Dependencies
+------------
+* Programmable logic control units
+
+Concurrency
+-----------
+N/A
+
+Limitations
+-----------
+N/A
+
+Knows issues and workarounds
+----------------------------
+N/A

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/evsys.rst

@@ -0,0 +1,24 @@
+===================
+Event system driver
+===================
+
+Event system allows autonomous, low-latency and configurable communication between peripherals.
+
+Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition
+to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that
+respond to events are event users, peripherals that generate events are called event generators. A peripheral can have
+one or more event generators and can have one or more event users.
+
+Communication is made without CPU intervention and without consuming system resources such as bus or RAM bandwidth. This
+reduces the load on the CPU and system resources, compared to a traditional interrupt-based system.
+
+The Event System consists of several channels which route the internal events from generators
+to users. Each event generator can be selected as source for multiple channels, but a channel cannot
+be set to use multiple event generators at the same time.
+
+Event system driver allows to configure event system of an MCU.
+
+Limitations
+-----------
+
+ - Event channel configuration is static

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/ext_irq.rst

@@ -0,0 +1,39 @@
+==============
+EXT IRQ driver
+==============
+
+The External Interrupt driver allows external pins to be
+configured as interrupt lines. Each interrupt line can be
+individually masked and can generate an interrupt on rising,
+falling or both edges, or on high or low levels. Some of
+external pin can also be configured to wake up the device
+from sleep modes where all clocks have been disabled.
+External pins can also generate an event.
+
+Features
+--------
+* Initialization and de-initialization
+* Enabling and disabling
+* Detect external pins interrupt
+
+Applications
+------------
+* Generate an interrupt on rising, falling or both edges,
+  or on high or low levels.
+
+Dependencies
+------------
+* GPIO hardware
+
+Concurrency
+-----------
+N/A
+
+Limitations
+-----------
+N/A
+
+Knows issues and workarounds
+----------------------------
+N/A
+

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/i2c_master_async.rst

@@ -0,0 +1,110 @@
+==============================
+I2C Master asynchronous driver
+==============================
+
+I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
+for on-board low-speed bi-directional communication between controllers and
+peripherals. The master device is responsible for initiating and controlling
+all transfers on the I2C bus. Only one master device can be active on the I2C
+bus at the time, but the master role can be transferred between devices on the
+same I2C bus. I2C uses only two bidirectional open-drain lines, usually
+designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
+resistors.
+
+The stop condition is automatically controlled by the driver if the I/O write and
+read functions are used, but can be manually controlled by using the
+i2c_m_async_transfer function.
+
+Often a master accesses different information in the slave by accessing
+different registers in the slave. This is done by first sending a message to
+the target slave containing the register address, followed by a repeated start
+condition (no stop condition between) ending with transferring register data.
+This scheme is supported by the i2c_m_async_cmd_write and i2c_m_async_cmd_read
+function, but limited to 8-bit register addresses.
+
+Transfer callbacks are executed at the end of a full transfer, that is when
+a complete message with address is either sent or read from the slave. When the
+i2c_m_async_transfer function is used the tx and rx callbacks are triggered
+regardless of if a stop condition is generated at the end of the message.
+
+The tx and rx callbacks are reused for the cmd functions and are triggered at
+the end of a full register write or read, that is after the register address has
+been written to the slave and data has been transferred to or from the master.
+
+The error callback is executed as soon as an error is detected, the error
+situation can both be detected while processing an interrupt or detected by
+the hardware which may trigger a special error interrupt. In situations where
+errors are detected by software, there will be a slight delay from the error
+occurs until the error callback is triggered due to software processing.
+
+I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
+Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
+stick within the SCL clock frequency range supported by the selected mode.
+The requested SCL clock frequency is not validated by the
+i2c_m_async_set_baudrate function against the selected I2C mode.
+
+Features
+--------
+
+	* I2C Master support
+	* Initialization and de-initialization
+	* Enabling and disabling
+	* Run-time bus speed configuration
+	* Write and read I2C messages
+	* Slave register access functions (limited to 8-bit address)
+	* Manual or automatic stop condition generation
+	* 10- and 7- bit addressing
+	* I2C Modes supported
+	       +----------------------+-------------------+
+	       |* Standard/Fast mode  | (SCL: 1 - 400kHz) |
+	       +----------------------+-------------------+
+	       |* Fastmode+           | (SCL: 1 - 1000kHz)|
+	       +----------------------+-------------------+
+	       |* Highspeed mode      | (SCL: 1 - 3400kHz)|
+	       +----------------------+-------------------+
+	* Callback on buffer transfer complete and error events
+
+Applications
+------------
+
+* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
+* Data communication between micro controllers
+* Controlling displays
+
+Dependencies
+------------
+
+* I2C Master capable hardware with char transfer complete and error interrupt
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+General
+^^^^^^^
+
+	* System Management Bus (SMBus) not supported
+	* Power Management Bus (PMBus) not supported
+	* Buffer content should not be changed before transfer is complete
+	* Due to software processing some errors may have a detection delay.
+
+Clock considerations
+^^^^^^^^^^^^^^^^^^^^
+
+The register value for the requested I2C speed is calculated and placed in the
+correct register, but not validated if it works correctly with the
+clock/prescaler settings used for the module. To validate the I2C speed
+setting use the formula found in the configuration file for the module.
+Selectable speed is automatically limited within the speed range defined by
+the I2C mode selected.
+
+Known issues and workarounds
+----------------------------
+
+N/A
+
+

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/pwm.rst

@@ -0,0 +1,53 @@
+The PWM Driver(bare-bone)
+=========================
+
+Pulse-width modulation (PWM) is used to create an analog behavior
+digitally by controlling the amount of power transferred to the
+connected peripheral. This is achieved by controlling the high period
+(duty-cycle) of a periodic signal.
+
+User can change the period or duty cycle whenever PWM is running. The
+function pwm_set_parameters is used to configure these two parameters.
+Note these are raw register values and the parameter duty_cycle means
+the period of first half during one cycle, which should be not beyond
+total period value.
+
+In addition, user can also get multi PWM channels output from different
+peripherals at the same time, which is implemented more flexible by the
+function pointers.
+
+Features
+--------
+
+* Initialization/de-initialization
+* Enabling/disabling
+* Run-time control of PWM duty-cycle and period
+* Notifications about errors and one PWM cycle is done
+
+Applications
+------------
+
+Motor control, ballast, LED, H-bridge, power converters, and
+other types of power control applications.
+
+Dependencies
+------------
+
+The peripheral which can perform waveform generation like frequency
+generation and pulse-width modulation, such as Timer/Counter.
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+The current driver doesn't support the features like recoverable,
+non-recoverable faults, dithering, dead-time insertion.
+
+Known issues and workarounds
+----------------------------
+
+N/A

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/quad_spi_dma.rst

@@ -0,0 +1,46 @@
+The Quad SPI DMA Driver
+=================================
+
+The Quad SPI Interface (QSPI) is a synchronous serial data link that provides
+communication with external devices in master mode.
+
+The QSPI DMA driver uses DMA system to transfer data between QSPI Memory region
+and external device. User must configure DMAC system driver accordingly. Callback 
+function is called when all the data is transferred or transfer error occurred, 
+if it is registered via qspi_dma_register_callback() function.
+
+
+Features
+--------
+
+* Initialization/de-initialization
+* Enabling/disabling
+* Register callback function
+* Execute command in Serial Memory Mode
+
+Applications
+------------
+
+They are commonly used in an application for using serial flash memory operating
+in single-bit SPI, Dual SPI and Quad SPI. 
+
+Dependencies
+------------
+
+Serial NOR flash with Multiple I/O hardware
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+N.A
+
+Known issues and workarounds
+----------------------------
+
+N/A
+

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/spi_master_dma.rst

@@ -0,0 +1,56 @@
+The SPI Master DMA Driver
+==================================
+
+The serial peripheral interface (SPI) is a DMA serial communication
+interface.
+
+The SPI Master DMA driver uses DMA system to transfer data from
+a memory buffer to SPI (Memory to Peripheral), and receive data
+from SPI to a memory buffer (Peripheral to Memory).User must configure
+DMA system driver accordingly. A callback is called when all the data
+is transfered or all the data is received, if it is registered via 
+spi_m_dma_register_callback function.
+
+Features
+--------
+
+* Initialization/de-initialization
+* Enabling/disabling
+* Control of the following settings:
+
+  * Baudrate
+  * SPI mode
+  * Character size
+  * Data order
+* Data transfer: transmission, reception and full-duplex
+* Notifications about transfer completion and errors via callbacks
+
+Applications
+------------
+
+Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card,
+LCD controller, etc.
+
+Dependencies
+------------
+
+SPI master capable hardware and DMA hardware, with data sent/received.
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+When only uses DMA channel to receive data, the transfer channel must enable to
+send dummy data to the slave.
+
+While read/write/transfer is in progress, the data buffer used must be kept
+unchanged.
+
+Known issues and workarounds
+----------------------------
+
+N/A

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/spi_master_sync.rst

@@ -0,0 +1,51 @@
+The SPI Master Synchronous Driver
+=================================
+
+The serial peripheral interface (SPI) is a synchronous serial communication
+interface.
+
+SPI devices communicate in full duplex mode using a master-slave
+architecture with a single master. The master device originates the frame for
+reading and writing. Multiple slave devices are supported through selection
+with individual slave select (SS) lines.
+
+Features
+--------
+
+* Initialization/de-initialization
+* Enabling/disabling
+* Control of the following settings:
+
+  * Baudrate
+  * SPI mode
+  * Character size
+  * Data order
+* Data transfer: transmission, reception and full-duplex
+
+Applications
+------------
+
+Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card,
+LCD controller, etc.
+
+Dependencies
+------------
+
+SPI master capable hardware
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+The slave select (SS) is not automatically inserted during read/write/transfer,
+user must use I/O to control the devices' SS.
+
+Known issues and workarounds
+----------------------------
+
+N/A
+

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/documentation/spi_slave_sync.rst

@@ -0,0 +1,60 @@
+The SPI Slave Synchronous Driver
+================================
+
+The serial peripheral interface (SPI) is a synchronous serial communication
+interface.
+
+SPI devices communicate in full duplex mode using a master-slave
+architecture with a single master. The slave device uses the control signal
+and clocks from master for reading and writing. Slave device is selected through
+slave select (SS) line.
+
+When data is read or written through the I/O writing function, the driver keeps
+polling until amount of characters achieved. Also it's possible to perform
+full-duplex read and write through transfer function, which process read and
+write at the same time.
+
+When SS detection is considered, a "break on SS detection" option can be enabled
+to make it possible to terminate the read/write/transfer on SS desertion.
+
+Features
+--------
+
+* Initialization/de-initialization
+* Enabling/disabling
+* Control of the following settings:
+
+  * SPI mode
+  * Character size
+  * Data order
+* Data transfer: transmission, reception and full-duplex
+
+Applications
+------------
+
+* SPI to I2C bridge that bridges SPI commands to I2C interface.
+
+Dependencies
+------------
+
+SPI slave capable hardware
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+N/A
+
+Known issues and workarounds
+----------------------------
+
+When writing data through SPI slave, the time that the data appears on data line
+depends on the SPI hardware, and previous writing state, since there can be
+data in output fifo filled by previous broken transmitting. The number of such
+dummy/broken characters is limited by hardware. Whether these dummy/broken
+characters can be flushed is also limited by hardware.
+

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_adc_sync.h

@@ -0,0 +1,277 @@
+/**
+ * \file
+ *
+ * \brief ADC functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_ADC_SYNC_H_INCLUDED
+#define _HAL_ADC_SYNC_H_INCLUDED
+
+#include <hpl_adc_sync.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_adc_sync
+ *
+ * @{
+ */
+
+/**
+ * \brief ADC descriptor
+ *
+ * The ADC descriptor forward declaration.
+ */
+struct adc_sync_descriptor;
+
+/**
+ * \brief ADC descriptor
+ */
+struct adc_sync_descriptor {
+	/** ADC device */
+	struct _adc_sync_device device;
+};
+
+/**
+ * \brief Initialize ADC
+ *
+ * This function initializes the given ADC descriptor.
+ * It checks if the given hardware is not initialized and if the given hardware
+ * is permitted to be initialized.
+ *
+ * \param[out] descr An ADC descriptor to initialize
+ * \param[in] hw     The pointer to hardware instance
+ * \param[in] func   The pointer to a set of functions pointers
+ *
+ * \return Initialization status.
+ */
+int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * This function deinitializes the given ADC descriptor.
+ * It checks if the given hardware is initialized and if the given hardware is
+ * permitted to be deinitialized.
+ *
+ * \param[in] descr An ADC descriptor to deinitialize
+ *
+ * \return De-initialization status.
+ */
+int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr);
+
+/**
+ * \brief Enable ADC
+ *
+ * Use this function to set the ADC peripheral to enabled state.
+ *
+ * \param[in] descr    Pointer to the ADC descriptor
+ * \param[in] channel  Channel number
+ *
+ * \return Operation status
+ *
+ */
+int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Disable ADC
+ *
+ * Use this function to set the ADC peripheral to disabled state.
+ *
+ * \param[in] descr   Pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ *
+ * \return Operation status
+ *
+ */
+int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Read data from ADC
+ *
+ * \param[in] descr    The pointer to the ADC descriptor
+ * \param[in] channel  Channel number
+ * \param[in] buf      A buffer to read data to
+ * \param[in] length   The size of a buffer
+ *
+ * \return The number of bytes read.
+ */
+int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
+                              const uint16_t length);
+
+/**
+ * \brief Set ADC reference source
+ *
+ * This function sets ADC reference source.
+ *
+ * \param[in] descr     The pointer to the ADC descriptor
+ * \param[in] reference A reference source to set
+ *
+ * \return Status of the ADC reference source setting.
+ */
+int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference);
+
+/**
+ * \brief Set ADC resolution
+ *
+ * This function sets ADC resolution.
+ *
+ * \param[in] descr      The pointer to the ADC descriptor
+ * \param[in] resolution A resolution to set
+ *
+ * \return Status of the ADC resolution setting.
+ */
+int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * This function sets ADC positive and negative input sources.
+ *
+ * \param[in] descr     The pointer to the ADC descriptor
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ *
+ * \return Status of the ADC channels setting.
+ */
+int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
+                            const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set ADC conversion mode
+ *
+ * This function sets ADC conversion mode.
+ *
+ * \param[in] descr The pointer to the ADC descriptor
+ * \param[in] mode  A conversion mode to set
+ *
+ * \return Status of the ADC conversion mode setting.
+ */
+int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set ADC differential mode
+ *
+ * This function sets ADC differential mode.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ *
+ * \return Status of the ADC differential mode setting.
+ */
+int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                               const enum adc_differential_mode mode);
+
+/**
+ * \brief Set ADC channel gain
+ *
+ * This function sets ADC channel gain.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ * \param[in] gain    A gain to set
+ *
+ * \return Status of the ADC gain setting.
+ */
+int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                  const adc_gain_t gain);
+
+/**
+ * \brief Set ADC window mode
+ *
+ * This function sets ADC window mode.
+ *
+ * \param[in] descr The pointer to the ADC descriptor
+ * \param[in] mode  A window mode to set
+ *
+ * \return Status of the ADC window mode setting.
+ */
+int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode);
+
+/**
+ * \brief Set ADC thresholds
+ *
+ * This function sets ADC positive and negative thresholds.
+ *
+ * \param[in] descr         The pointer to the ADC descriptor
+ * \param[in] low_threshold A lower thresholds to set
+ * \param[in] up_threshold  An upper thresholds to set
+ *
+ * \return Status of the ADC thresholds setting.
+ */
+int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
+                                const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * This function retrieves ADC threshold state.
+ *
+ * \param[in] descr  The pointer to the ADC descriptor
+ * \param[out] state The threshold state
+ *
+ * \return The state of ADC thresholds state retrieving.
+ */
+int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr,
+                                     adc_threshold_status_t *const           state);
+
+/**
+ * \brief Check if conversion is complete
+ *
+ * This function checks if the ADC has finished the conversion.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ *
+ * \return The status of ADC conversion completion checking.
+ * \retval 1 The conversion is complete
+ * \retval 0 The conversion is not complete
+ */
+int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t adc_sync_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#include <hpl_missing_features.h>
+
+#endif /* _HAL_ADC_SYNC_H_INCLUDED */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_atomic.h

@@ -0,0 +1,120 @@
+/**
+ * \file
+ *
+ * \brief Critical sections related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_ATOMIC_H_INCLUDED
+#define _HAL_ATOMIC_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_helper_atomic
+ *
+ *@{
+ */
+
+/**
+ * \brief Type for the register holding global interrupt enable flag
+ */
+typedef uint32_t hal_atomic_t;
+
+/**
+ * \brief Helper macro for entering critical sections
+ *
+ * This macro is recommended to be used instead of a direct call
+ * hal_enterCritical() function to enter critical
+ * sections. No semicolon is required after the macro.
+ *
+ * \section atomic_usage Usage Example
+ * \code
+ * CRITICAL_SECTION_ENTER()
+ * Critical code
+ * CRITICAL_SECTION_LEAVE()
+ * \endcode
+ */
+#define CRITICAL_SECTION_ENTER()                                                                                       \
+	{                                                                                                                  \
+		volatile hal_atomic_t __atomic;                                                                                \
+		atomic_enter_critical(&__atomic);
+
+/**
+ * \brief Helper macro for leaving critical sections
+ *
+ * This macro is recommended to be used instead of a direct call
+ * hal_leaveCritical() function to leave critical
+ * sections. No semicolon is required after the macro.
+ */
+#define CRITICAL_SECTION_LEAVE()                                                                                       \
+	atomic_leave_critical(&__atomic);                                                                                  \
+	}
+
+/**
+ * \brief Disable interrupts, enter critical section
+ *
+ * Disables global interrupts. Supports nested critical sections,
+ * so that global interrupts are only re-enabled
+ * upon leaving the outermost nested critical section.
+ *
+ * \param[out] atomic The pointer to a variable to store the value of global
+ * interrupt enable flag
+ */
+void atomic_enter_critical(hal_atomic_t volatile *atomic);
+
+/**
+ * \brief Exit atomic section
+ *
+ * Enables global interrupts. Supports nested critical sections,
+ * so that global interrupts are only re-enabled
+ * upon leaving the outermost nested critical section.
+ *
+ * \param[in] atomic The pointer to a variable, which stores the latest stored
+ * value of the global interrupt enable flag
+ */
+void atomic_leave_critical(hal_atomic_t volatile *atomic);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t atomic_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_ATOMIC_H_INCLUDED */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_cache.h

@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief HAL cache functionality implementation.
+ *
+ * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".  NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef HAL_CACHE_H_
+#define HAL_CACHE_H_
+
+#include <hpl_cmcc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Enable cache module
+ *
+ * \param[in] pointer pointing to the starting address of cache module
+ *
+ * \return status of operation
+ */
+int32_t cache_enable(const void *hw);
+
+/**
+ * \brief Disable cache module
+ *
+ * \param[in] pointer pointing to the starting address of cache module
+ *
+ * \return status of operation
+ */
+int32_t cache_disable(const void *hw);
+
+/**
+ * \brief Initialize cache module
+ *
+ * This function initialize cache module configuration.
+ *
+ * \return status of operation
+ */
+int32_t cache_init(void);
+
+/**
+ * \brief Configure cache module
+ *
+ * \param[in] pointer pointing to the starting address of cache module
+ * \param[in] cache configuration structure pointer
+ *
+ * \return status of operation
+ */
+int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
+
+/**
+ * \brief Invalidate entire cache entries
+ *
+ * \param[in] pointer pointing to the starting address of cache module
+ *
+ * \return status of operation
+ */
+int32_t cache_invalidate_all(const void *hw);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_CACHE_H_ */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_custom_logic.h

@@ -0,0 +1,89 @@
+/**
+ * \file
+ *
+ * \brief Custom Control Logic functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hpl_custom_logic.h"
+
+#ifndef _HAL_CUSTOM_LOGIC_H_INCLUDED
+#define _HAL_CUSTOM_LOGIC_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_custom_logic
+ *
+ *@{
+ */
+
+/**
+ *  \brief Initialize the custom logic hardware
+ *  \return Initialization operation status
+ */
+static inline int32_t custom_logic_init(void)
+{
+	return _custom_logic_init();
+}
+
+/**
+ *  \brief Disable and reset the custom logic hardware
+ */
+static inline void custom_logic_deinit(void)
+{
+	_custom_logic_deinit();
+}
+
+/**
+ *  \brief Enable the custom logic hardware
+ *  \return Initialization operation status
+ */
+static inline int32_t custom_logic_enable(void)
+{
+	return _custom_logic_enable();
+}
+
+/**
+ *  \brief Disable the custom logic hardware
+ */
+static inline void custom_logic_disable(void)
+{
+	_custom_logic_disable();
+}
+
+	/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_CUSTOM_LOGIC_H_INCLUDED */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_delay.h

@@ -0,0 +1,89 @@
+/**
+ * \file
+ *
+ * \brief HAL delay related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_irq.h>
+#include <hpl_reset.h>
+#include <hpl_sleep.h>
+
+#ifndef _HAL_DELAY_H_INCLUDED
+#define _HAL_DELAY_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_delay Delay Driver
+ *
+ *@{
+ */
+
+/**
+ * \brief Initialize Delay driver
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+void delay_init(void *const hw);
+
+/**
+ * \brief Perform delay in us
+ *
+ * This function performs delay for the given amount of microseconds.
+ *
+ * \param[in] us The amount delay in us
+ */
+void delay_us(const uint16_t us);
+
+/**
+ * \brief Perform delay in ms
+ *
+ * This function performs delay for the given amount of milliseconds.
+ *
+ * \param[in] ms The amount delay in ms
+ */
+void delay_ms(const uint16_t ms);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t delay_get_version(void);
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HAL_DELAY_H_INCLUDED */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_evsys.h

@@ -0,0 +1,116 @@
+/**
+ * \file
+ *
+ * \brief HAL event system related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_evsys.h>
+
+#ifndef _HAL_EVSYS_H_INCLUDED
+#define _HAL_EVSYS_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_evsys
+ *
+ * @{
+ */
+
+/**
+ * \brief Initialize event system.
+ *
+ * \return Initialization status.
+ */
+int32_t event_system_init(void);
+
+/**
+ * \brief Deinitialize event system.
+ *
+ * \return De-initialization status.
+ */
+int32_t event_system_deinit(void);
+
+/**
+ * \brief Enable event reception by the given user from the given channel
+ *
+ * \param[in] user A user to enable
+ * \param[in] channel A channel the user is assigned to
+ *
+ * \return Status of operation.
+ */
+int32_t event_system_enable_user(const uint16_t user, const uint16_t channel);
+
+/**
+ * \brief Disable event reception by the given user from the given channel
+ *
+ * \param[in] user A user to disable
+ * \param[in] channel A channel the user is assigned to
+ *
+ * \return Status of operation.
+ */
+int32_t event_system_disable_user(const uint16_t user, const uint16_t channel);
+
+/**
+ * \brief Enable event generation by the given generator for the given channel
+ *
+ * \param[in] generator A generator to disable
+ * \param[in] channel A channel the generator is assigned to
+ *
+ * \return Status of operation.
+ */
+int32_t event_system_enable_generator(const uint16_t generator, const uint16_t channel);
+
+/**
+ * \brief Disable event generation by the given generator for the given channel
+ *
+ * \param[in] generator A generator to disable
+ * \param[in] channel A channel the generator is assigned to
+ *
+ * \return Status of operation.
+ */
+int32_t event_system_disable_generator(const uint16_t generator, const uint16_t channel);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t event_system_get_version(void);
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HAL_EVSYS_H_INCLUDED */

2_Motor_Master_D51/Two_Motor_D51/Two_Motor_D51/hal/include/hal_ext_irq.h

@@ -0,0 +1,118 @@
+/**
+ * \file
+ *
+ * \brief External interrupt functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_EXT_IRQ_H_INCLUDED
+#define _HAL_EXT_IRQ_H_INCLUDED
+
+#include <hpl_ext_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_ext_irq
+ *
+ * @{
+ */
+
+/**
+ * \brief External IRQ callback type
+ */
+typedef void (*ext_irq_cb_t)(void);
+
+/**
+ * \brief Initialize external IRQ component, if any
+ *
+ * \return Initialization status.
+ * \retval -1 External IRQ module is already initialized
+ * \retval 0 The initialization is completed successfully
+ */
+int32_t ext_irq_init(void);
+
+/**
+ * \brief Deinitialize external IRQ, if any
+ *
+ * \return De-initialization status.
+ * \retval -1 External IRQ module is already deinitialized
+ * \retval 0 The de-initialization is completed successfully
+ */
+int32_t ext_irq_deinit(void);
+
+/**
+ * \brief Register callback for the given external interrupt
+ *
+ * \param[in] pin Pin to enable external IRQ on
+ * \param[in] cb Callback function
+ *
+ * \return Registration status.
+ * \retval -1 Passed parameters were invalid
+ * \retval 0 The callback registration is completed successfully
+ */
+int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb);
+
+/**
+ * \brief Enable external IRQ
+ *
+ * \param[in] pin Pin to enable external IRQ on
+ *
+ * \return Enabling status.
+ * \retval -1 Passed parameters were invalid
+ * \retval 0 The enabling is completed successfully
+ */
+int32_t ext_irq_enable(const uint32_t pin);
+
+/**
+ * \brief Disable external IRQ
+ *
+ * \param[in] pin Pin to enable external IRQ on
+ *
+ * \return Disabling status.
+ * \retval -1 Passed parameters were invalid
+ * \retval 0 The disabling is completed successfully
+ */
+int32_t ext_irq_disable(const uint32_t pin);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t ext_irq_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_EXT_IRQ_H_INCLUDED */