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fixed the dma issue

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This commit is contained in:
Nicolas Trimborn
2021-08-25 20:03:50 +02:00
parent fadb312ed1
commit c00c82e6e6
20 changed files with 174 additions and 135 deletions
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42
2_Motor_Master/Motor_Master/Motor_Master/.atmelstart/atmel_start_config.atstart
View File

@@ -41,7 +41,7 @@ drivers:
adc_arch_refcomp: false
adc_arch_resrdyeo: true
adc_arch_runstdby: false
adc_arch_samplen: 3
adc_arch_samplen: 2
adc_arch_samplenum: 1 sample
adc_arch_seqen: 0
adc_arch_startei: false
@@ -237,7 +237,7 @@ drivers:
api: HAL:HPL:DMAC
configuration:
dmac_beatsize_0: 8-bit bus transfer
dmac_beatsize_1: 8-bit bus transfer
dmac_beatsize_1: 16-bit bus transfer
dmac_beatsize_10: 8-bit bus transfer
dmac_beatsize_11: 8-bit bus transfer
dmac_beatsize_12: 8-bit bus transfer
@@ -259,7 +259,7 @@ drivers:
dmac_beatsize_27: 8-bit bus transfer
dmac_beatsize_28: 8-bit bus transfer
dmac_beatsize_29: 8-bit bus transfer
dmac_beatsize_3: 16-bit bus transfer
dmac_beatsize_3: 8-bit bus transfer
dmac_beatsize_30: 8-bit bus transfer
dmac_beatsize_31: 8-bit bus transfer
dmac_beatsize_4: 8-bit bus transfer
@@ -271,7 +271,7 @@ drivers:
dmac_blockact_0: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_1: Channel will be disabled if it is the last block transfer in
the transaction
the transaction and block interrupt
dmac_blockact_10: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_11: Channel will be disabled if it is the last block transfer
@@ -314,7 +314,7 @@ drivers:
dmac_blockact_29: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_3: Channel will be disabled if it is the last block transfer in
the transaction and block interrupt
the transaction
dmac_blockact_30: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_31: Channel will be disabled if it is the last block transfer
@@ -365,7 +365,7 @@ drivers:
dmac_channel_9_settings: false
dmac_dbgrun: false
dmac_dstinc_0: true
dmac_dstinc_1: false
dmac_dstinc_1: true
dmac_dstinc_10: false
dmac_dstinc_11: false
dmac_dstinc_12: false
@@ -387,7 +387,7 @@ drivers:
dmac_dstinc_27: false
dmac_dstinc_28: false
dmac_dstinc_29: false
dmac_dstinc_3: true
dmac_dstinc_3: false
dmac_dstinc_30: false
dmac_dstinc_31: false
dmac_dstinc_4: false
@@ -537,7 +537,7 @@ drivers:
dmac_lvl_17: Channel priority 0
dmac_lvl_18: Channel priority 0
dmac_lvl_19: Channel priority 0
dmac_lvl_2: Channel priority 1
dmac_lvl_2: Channel priority 0
dmac_lvl_20: Channel priority 0
dmac_lvl_21: Channel priority 0
dmac_lvl_22: Channel priority 0
@@ -548,7 +548,7 @@ drivers:
dmac_lvl_27: Channel priority 0
dmac_lvl_28: Channel priority 0
dmac_lvl_29: Channel priority 0
dmac_lvl_3: Channel priority 1
dmac_lvl_3: Channel priority 0
dmac_lvl_30: Channel priority 0
dmac_lvl_31: Channel priority 0
dmac_lvl_4: Channel priority 0
@@ -562,15 +562,15 @@ drivers:
dmac_lvlen2: true
dmac_lvlen3: true
dmac_lvlpri0: 0
dmac_lvlpri1: 1
dmac_lvlpri1: 0
dmac_lvlpri2: 0
dmac_lvlpri3: 0
dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
dmac_runstdby_0: false
dmac_runstdby_1: false
dmac_runstdby_0: true
dmac_runstdby_1: true
dmac_runstdby_10: false
dmac_runstdby_11: false
dmac_runstdby_12: false
@@ -581,7 +581,7 @@ drivers:
dmac_runstdby_17: false
dmac_runstdby_18: false
dmac_runstdby_19: false
dmac_runstdby_2: false
dmac_runstdby_2: true
dmac_runstdby_20: false
dmac_runstdby_21: false
dmac_runstdby_22: false
@@ -592,7 +592,7 @@ drivers:
dmac_runstdby_27: false
dmac_runstdby_28: false
dmac_runstdby_29: false
dmac_runstdby_3: false
dmac_runstdby_3: true
dmac_runstdby_30: false
dmac_runstdby_31: false
dmac_runstdby_4: false
@@ -602,7 +602,7 @@ drivers:
dmac_runstdby_8: false
dmac_runstdby_9: false
dmac_srcinc_0: false
dmac_srcinc_1: true
dmac_srcinc_1: false
dmac_srcinc_10: false
dmac_srcinc_11: false
dmac_srcinc_12: false
@@ -624,7 +624,7 @@ drivers:
dmac_srcinc_27: false
dmac_srcinc_28: false
dmac_srcinc_29: false
dmac_srcinc_3: false
dmac_srcinc_3: true
dmac_srcinc_30: false
dmac_srcinc_31: false
dmac_srcinc_4: false
@@ -656,7 +656,7 @@ drivers:
dmac_stepsel_27: Step size settings apply to the destination address
dmac_stepsel_28: Step size settings apply to the destination address
dmac_stepsel_29: Step size settings apply to the destination address
dmac_stepsel_3: Step size settings apply to the destination address
dmac_stepsel_3: Step size settings apply to the source address
dmac_stepsel_30: Step size settings apply to the destination address
dmac_stepsel_31: Step size settings apply to the destination address
dmac_stepsel_4: Step size settings apply to the destination address
@@ -698,7 +698,7 @@ drivers:
dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_trifsrc_0: SERCOM1 RX Trigger
dmac_trifsrc_1: SERCOM1 TX Trigger
dmac_trifsrc_1: ADC1 Result Ready Trigger
dmac_trifsrc_10: Only software/event triggers
dmac_trifsrc_11: Only software/event triggers
dmac_trifsrc_12: Only software/event triggers
@@ -720,7 +720,7 @@ drivers:
dmac_trifsrc_27: Only software/event triggers
dmac_trifsrc_28: Only software/event triggers
dmac_trifsrc_29: Only software/event triggers
dmac_trifsrc_3: ADC1 Result Ready Trigger
dmac_trifsrc_3: SERCOM1 TX Trigger
dmac_trifsrc_30: Only software/event triggers
dmac_trifsrc_31: Only software/event triggers
dmac_trifsrc_4: Only software/event triggers
@@ -1758,10 +1758,10 @@ drivers:
spi_master_arch_dord: MSB first
spi_master_arch_ibon: In data stream
spi_master_arch_runstdby: false
spi_master_baud_rate: 8000000
spi_master_baud_rate: 2000000
spi_master_character_size: 8 bits
spi_master_dma_rx_channel: 0
spi_master_dma_tx_channel: 1
spi_master_dma_tx_channel: 3
spi_master_dummybyte: 511
spi_master_rx_channel: true
spi_master_rx_enable: true

2
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_adc_config.h
View File

@@ -209,7 +209,7 @@
// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
// <id> adc_arch_samplen
#ifndef CONF_ADC_1_SAMPLEN
#define CONF_ADC_1_SAMPLEN 3
#define CONF_ADC_1_SAMPLEN 2
#endif
// <o> Window Monitor Mode

36
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_dmac_config.h
View File

@@ -51,7 +51,7 @@
// <o> Level 1 Channel Priority Number <0x00-0xFF>
// <id> dmac_lvlpri1
#ifndef CONF_DMAC_LVLPRI1
#define CONF_DMAC_LVLPRI1 1
#define CONF_DMAC_LVLPRI1 0
#endif
// <q> Priority Level 2
// <i> Indicates whether Priority Level 2 is enabled or not
@@ -112,7 +112,7 @@
// <i> Indicates whether channel 0 is running in standby mode or not
// <id> dmac_runstdby_0
#ifndef CONF_DMAC_RUNSTDBY_0
#define CONF_DMAC_RUNSTDBY_0 0
#define CONF_DMAC_RUNSTDBY_0 1
#endif
// <o> Trigger action
@@ -336,7 +336,7 @@
// <i> Indicates whether channel 1 is running in standby mode or not
// <id> dmac_runstdby_1
#ifndef CONF_DMAC_RUNSTDBY_1
#define CONF_DMAC_RUNSTDBY_1 0
#define CONF_DMAC_RUNSTDBY_1 1
#endif
// <o> Trigger action
@@ -438,7 +438,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_1
#ifndef CONF_DMAC_TRIGSRC_1
#define CONF_DMAC_TRIGSRC_1 7
#define CONF_DMAC_TRIGSRC_1 70
#endif
// <o> Channel Arbitration Level
@@ -508,14 +508,14 @@
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_1
#ifndef CONF_DMAC_SRCINC_1
#define CONF_DMAC_SRCINC_1 1
#define CONF_DMAC_SRCINC_1 0
#endif
// <q> Destination Address Increment
// <i> Indicates whether the destination address incrementation is enabled or not
// <id> dmac_dstinc_1
#ifndef CONF_DMAC_DSTINC_1
#define CONF_DMAC_DSTINC_1 0
#define CONF_DMAC_DSTINC_1 1
#endif
// <o> Beat Size
@@ -525,7 +525,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_1
#ifndef CONF_DMAC_BEATSIZE_1
#define CONF_DMAC_BEATSIZE_1 0
#define CONF_DMAC_BEATSIZE_1 1
#endif
// <o> Block Action
@@ -536,7 +536,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_1
#ifndef CONF_DMAC_BLOCKACT_1
#define CONF_DMAC_BLOCKACT_1 0
#define CONF_DMAC_BLOCKACT_1 1
#endif
// <o> Event Output Selection
@@ -560,7 +560,7 @@
// <i> Indicates whether channel 2 is running in standby mode or not
// <id> dmac_runstdby_2
#ifndef CONF_DMAC_RUNSTDBY_2
#define CONF_DMAC_RUNSTDBY_2 0
#define CONF_DMAC_RUNSTDBY_2 1
#endif
// <o> Trigger action
@@ -673,7 +673,7 @@
// <i> Defines the arbitration level for this channel
// <id> dmac_lvl_2
#ifndef CONF_DMAC_LVL_2
#define CONF_DMAC_LVL_2 1
#define CONF_DMAC_LVL_2 0
#endif
// <q> Channel Event Output
@@ -784,7 +784,7 @@
// <i> Indicates whether channel 3 is running in standby mode or not
// <id> dmac_runstdby_3
#ifndef CONF_DMAC_RUNSTDBY_3
#define CONF_DMAC_RUNSTDBY_3 0
#define CONF_DMAC_RUNSTDBY_3 1
#endif
// <o> Trigger action
@@ -886,7 +886,7 @@
// <i> Defines the peripheral trigger which is source of the transfer
// <id> dmac_trifsrc_3
#ifndef CONF_DMAC_TRIGSRC_3
#define CONF_DMAC_TRIGSRC_3 70
#define CONF_DMAC_TRIGSRC_3 7
#endif
// <o> Channel Arbitration Level
@@ -897,7 +897,7 @@
// <i> Defines the arbitration level for this channel
// <id> dmac_lvl_3
#ifndef CONF_DMAC_LVL_3
#define CONF_DMAC_LVL_3 1
#define CONF_DMAC_LVL_3 0
#endif
// <q> Channel Event Output
@@ -949,21 +949,21 @@
// <i> Defines whether source or destination addresses are using the step size settings
// <id> dmac_stepsel_3
#ifndef CONF_DMAC_STEPSEL_3
#define CONF_DMAC_STEPSEL_3 0
#define CONF_DMAC_STEPSEL_3 1
#endif
// <q> Source Address Increment
// <i> Indicates whether the source address incrementation is enabled or not
// <id> dmac_srcinc_3
#ifndef CONF_DMAC_SRCINC_3
#define CONF_DMAC_SRCINC_3 0
#define CONF_DMAC_SRCINC_3 1
#endif
// <q> Destination Address Increment
// <i> Indicates whether the destination address incrementation is enabled or not
// <id> dmac_dstinc_3
#ifndef CONF_DMAC_DSTINC_3
#define CONF_DMAC_DSTINC_3 1
#define CONF_DMAC_DSTINC_3 0
#endif
// <o> Beat Size
@@ -973,7 +973,7 @@
// <i> Defines the size of one beat
// <id> dmac_beatsize_3
#ifndef CONF_DMAC_BEATSIZE_3
#define CONF_DMAC_BEATSIZE_3 1
#define CONF_DMAC_BEATSIZE_3 0
#endif
// <o> Block Action
@@ -984,7 +984,7 @@
// <i> Defines the the DMAC should take after a block transfer has completed
// <id> dmac_blockact_3
#ifndef CONF_DMAC_BLOCKACT_3
#define CONF_DMAC_BLOCKACT_3 1
#define CONF_DMAC_BLOCKACT_3 0
#endif
// <o> Event Output Selection

4
2_Motor_Master/Motor_Master/Motor_Master/Config/hpl_sercom_config.h
View File

@@ -15,7 +15,7 @@
//<i> This defines DMA channel to be used
//<id> spi_master_dma_tx_channel
#ifndef CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 1
#define CONF_SERCOM_1_SPI_M_DMA_TX_CHANNEL 3
#endif
// <e> SPI RX Channel Enable
@@ -59,7 +59,7 @@
// <i> The SPI data transfer rate
// <id> spi_master_baud_rate
#ifndef CONF_SERCOM_1_SPI_BAUD
#define CONF_SERCOM_1_SPI_BAUD 8000000
#define CONF_SERCOM_1_SPI_BAUD 2000000
#endif
// </h>

8
2_Motor_Master/Motor_Master/Motor_Master/Motor_Master.cproj
View File

@@ -207,10 +207,10 @@
<AcmeProjectActionInfo Action="File" Source="hpl/tcc/hpl_tcc.h" IsConfig="false" Hash="rdWkAK12qkOYV59tWwzy6A" />
<AcmeProjectActionInfo Action="File" Source="atmel_start.h" IsConfig="false" Hash="9RBG5E2ViQiSP2Gn4/FGpA" />
<AcmeProjectActionInfo Action="File" Source="atmel_start.c" IsConfig="false" Hash="1RHIE7zTtYK4DURNPUqF9w" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="KQS08c8S3nvQhznT02tFlg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_adc_config.h" IsConfig="true" Hash="IJeJ3sDxG9f3mmsLxoMLlA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_ccl_config.h" IsConfig="true" Hash="Q1yijLwNXjFOsGrwEEma+g" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_cmcc_config.h" IsConfig="true" Hash="bmtxQ8rLloaRtAo2HeXZRQ" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="JdAljBjm3ndwImqgZ6Oc5w" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_dmac_config.h" IsConfig="true" Hash="InEybPQe1lA+oW1HFMWYLg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_eic_config.h" IsConfig="true" Hash="S8xJxIaG6pS6BEvDgxKh9w" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_evsys_config.h" IsConfig="true" Hash="/3bNiu/UgpvPbmvfRA+w3g" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_gclk_config.h" IsConfig="true" Hash="fvc5nhPTGTNHCTNlzs6nhA" />
@@ -219,7 +219,7 @@
<AcmeProjectActionInfo Action="File" Source="config/hpl_oscctrl_config.h" IsConfig="true" Hash="Uje5LXAS+nQpGryt9t0fYA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_port_config.h" IsConfig="true" Hash="rMTNR+5FXtu+wfT1NbfRRA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_qspi_config.h" IsConfig="true" Hash="CwZ360eeEYs7T9SYFSvDug" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="RbJ5bUxaEZKAk+siOfnj8g" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_sercom_config.h" IsConfig="true" Hash="NOEuutypdbfpBKOWCPUPuA" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_tc_config.h" IsConfig="true" Hash="T93Kr6C+WDuufZob89oPeg" />
<AcmeProjectActionInfo Action="File" Source="config/hpl_tcc_config.h" IsConfig="true" Hash="2LU7afZ/3Yx7FE2KzF9dSQ" />
<AcmeProjectActionInfo Action="File" Source="config/peripheral_clk_config.h" IsConfig="true" Hash="s/tLl+lpMPQWNUrjuAL0rQ" />
@@ -417,7 +417,7 @@
<armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
<armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
<armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
<armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
<armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
<armgcc.linker.general.UseNewlibNano>True</armgcc.linker.general.UseNewlibNano>
<armgcc.linker.libraries.Libraries>
<ListValues>

4
2_Motor_Master/Motor_Master/Motor_Master/configuration.h
View File

@@ -21,7 +21,7 @@
// M1_IA=ADC1_AIN[9], M1_IB=ADC1_AIN[8], M2_IA=ADC1_AIN[7], M2_IB=ADC1_AIN[6]
// ----------------------------------------------------------------------
#define DMAC_CHANNEL_ADC_SEQ 2U
#define DMAC_CHANNEL_ADC_SRAM 3U
#define DMAC_CHANNEL_ADC_SRAM 1U
/* Single Ended */
//const uint32_t adc_seq_regs[4] = {0x1807, 0x1806, 0x1809, 0x1808};
@@ -152,7 +152,7 @@ extern DmacDescriptor _write_back_section[DMAC_CH_NUM];
#define DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE 0u
#define DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT 1U
#define DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT 3U
void boardToBoardTransferInit(void)
{

14
2_Motor_Master/Motor_Master/Motor_Master/main.c
View File

@@ -63,14 +63,6 @@ void One_ms_timer_init(void)
timer_start(&TIMER_0);
}
//void speed_timer_init(void)
//{
//hri_tc_write_WAVE_reg(TC_SPEED_M1.device.hw, 0x00);
//hri_tc_set_CTRLA_CAPTEN0_bit(TC_SPEED_M1.device.hw);
//hri_tc_set_CTRLA_CAPTEN1_bit(TC_SPEED_M1.device.hw);
//timer_start(&TC_SPEED_M1);
//}
void enable_NVIC_IRQ(void)
{
@@ -192,9 +184,9 @@ int main(void)
Motor1.timerflags.motor_telemetry_flag = false;
update_telemetry();
update_setpoints();
//PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
//DMAC->Channel[0].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
//DMAC->Channel[1].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
PORT->Group[1].OUTCLR.reg = (1<<GPIO_PIN(SPI1_CS));
DMAC->Channel[DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
DMAC->Channel[DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
//_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_RECEIVE, false);
//_dma_enable_transaction(DMAC_CHANNEL_CONF_SERCOM_1_TRANSMIT, false);